1// SPDX-License-Identifier: GPL-2.0 2/* 3 * DTS File for HiSilicon Hi3798cv200 SoC. 4 * 5 * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd. 6 */ 7 8#include <dt-bindings/clock/histb-clock.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/phy/phy.h> 12#include <dt-bindings/reset/ti-syscon.h> 13 14/ { 15 compatible = "hisilicon,hi3798cv200"; 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 psci { 21 compatible = "arm,psci-0.2"; 22 method = "smc"; 23 }; 24 25 cpus { 26 #address-cells = <2>; 27 #size-cells = <0>; 28 29 cpu@0 { 30 compatible = "arm,cortex-a53"; 31 device_type = "cpu"; 32 reg = <0x0 0x0>; 33 enable-method = "psci"; 34 d-cache-size = <0x8000>; /* 32 KiB */ 35 d-cache-line-size = <64>; 36 d-cache-sets = <128>; 37 i-cache-size = <0x8000>; /* 32 KiB */ 38 i-cache-line-size = <64>; 39 i-cache-sets = <256>; 40 next-level-cache = <&L2>; 41 }; 42 43 cpu@1 { 44 compatible = "arm,cortex-a53"; 45 device_type = "cpu"; 46 reg = <0x0 0x1>; 47 enable-method = "psci"; 48 d-cache-size = <0x8000>; /* 32 KiB */ 49 d-cache-line-size = <64>; 50 d-cache-sets = <128>; 51 i-cache-size = <0x8000>; /* 32 KiB */ 52 i-cache-line-size = <64>; 53 i-cache-sets = <256>; 54 next-level-cache = <&L2>; 55 }; 56 57 cpu@2 { 58 compatible = "arm,cortex-a53"; 59 device_type = "cpu"; 60 reg = <0x0 0x2>; 61 enable-method = "psci"; 62 d-cache-size = <0x8000>; /* 32 KiB */ 63 d-cache-line-size = <64>; 64 d-cache-sets = <128>; 65 i-cache-size = <0x8000>; /* 32 KiB */ 66 i-cache-line-size = <64>; 67 i-cache-sets = <256>; 68 next-level-cache = <&L2>; 69 }; 70 71 cpu@3 { 72 compatible = "arm,cortex-a53"; 73 device_type = "cpu"; 74 reg = <0x0 0x3>; 75 enable-method = "psci"; 76 d-cache-size = <0x8000>; /* 32 KiB */ 77 d-cache-line-size = <64>; 78 d-cache-sets = <128>; 79 i-cache-size = <0x8000>; /* 32 KiB */ 80 i-cache-line-size = <64>; 81 i-cache-sets = <256>; 82 next-level-cache = <&L2>; 83 }; 84 }; 85 86 L2: l2-cache { 87 compatible = "cache"; 88 cache-unified; 89 cache-size = <0x80000>; /* 512 KiB */ 90 cache-line-size = <64>; 91 cache-sets = <512>; 92 cache-level = <2>; 93 }; 94 95 gic: interrupt-controller@f1001000 { 96 compatible = "arm,gic-400"; 97 reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */ 98 <0x0 0xf1002000 0x0 0x2000>, /* GICC */ 99 <0x0 0xf1004000 0x0 0x2000>, /* GICH */ 100 <0x0 0xf1006000 0x0 0x2000>; /* GICV */ 101 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | 102 IRQ_TYPE_LEVEL_HIGH)>; 103 #address-cells = <0>; 104 #interrupt-cells = <3>; 105 interrupt-controller; 106 }; 107 108 timer { 109 compatible = "arm,armv8-timer"; 110 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | 111 IRQ_TYPE_LEVEL_LOW)>, 112 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | 113 IRQ_TYPE_LEVEL_LOW)>, 114 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | 115 IRQ_TYPE_LEVEL_LOW)>, 116 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | 117 IRQ_TYPE_LEVEL_LOW)>; 118 }; 119 120 soc: soc@f0000000 { 121 compatible = "simple-bus"; 122 #address-cells = <1>; 123 #size-cells = <1>; 124 ranges = <0x0 0x0 0xf0000000 0x10000000>; 125 dma-ranges = <0x0 0x0 0x0 0x40000000>; 126 127 crg: clock-reset-controller@8a22000 { 128 compatible = "hisilicon,hi3798cv200-crg", "syscon", "simple-mfd"; 129 reg = <0x8a22000 0x1000>; 130 #clock-cells = <1>; 131 #reset-cells = <2>; 132 133 gmacphyrst: reset-controller { 134 compatible = "ti,syscon-reset"; 135 #reset-cells = <1>; 136 ti,reset-bits = < 137 0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR | DEASSERT_SET | STATUS_NONE) 138 0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR | DEASSERT_SET | STATUS_NONE) 139 >; 140 }; 141 }; 142 143 sysctrl: system-controller@8000000 { 144 compatible = "hisilicon,hi3798cv200-sysctrl", "syscon"; 145 reg = <0x8000000 0x1000>; 146 #clock-cells = <1>; 147 #reset-cells = <2>; 148 }; 149 150 perictrl: peripheral-controller@8a20000 { 151 compatible = "hisilicon,hi3798cv200-perictrl", "syscon", 152 "simple-mfd"; 153 reg = <0x8a20000 0x1000>; 154 #address-cells = <1>; 155 #size-cells = <1>; 156 ranges = <0x0 0x8a20000 0x1000>; 157 158 usb2_phy1: usb2_phy@120 { 159 compatible = "hisilicon,hi3798cv200-usb2-phy"; 160 reg = <0x120 0x4>; 161 clocks = <&crg HISTB_USB2_PHY1_REF_CLK>; 162 resets = <&crg 0xbc 4>; 163 #address-cells = <1>; 164 #size-cells = <0>; 165 166 usb2_phy1_port0: phy@0 { 167 reg = <0>; 168 #phy-cells = <0>; 169 resets = <&crg 0xbc 8>; 170 }; 171 172 usb2_phy1_port1: phy@1 { 173 reg = <1>; 174 #phy-cells = <0>; 175 resets = <&crg 0xbc 9>; 176 }; 177 }; 178 179 usb2_phy2: usb2_phy@124 { 180 compatible = "hisilicon,hi3798cv200-usb2-phy"; 181 reg = <0x124 0x4>; 182 clocks = <&crg HISTB_USB2_PHY2_REF_CLK>; 183 resets = <&crg 0xbc 6>; 184 #address-cells = <1>; 185 #size-cells = <0>; 186 187 usb2_phy2_port0: phy@0 { 188 reg = <0>; 189 #phy-cells = <0>; 190 resets = <&crg 0xbc 10>; 191 }; 192 }; 193 194 combphy0: phy@850 { 195 compatible = "hisilicon,hi3798cv200-combphy"; 196 reg = <0x850 0x8>; 197 #phy-cells = <1>; 198 clocks = <&crg HISTB_COMBPHY0_CLK>; 199 resets = <&crg 0x188 4>; 200 assigned-clocks = <&crg HISTB_COMBPHY0_CLK>; 201 assigned-clock-rates = <100000000>; 202 hisilicon,fixed-mode = <PHY_TYPE_USB3>; 203 }; 204 205 combphy1: phy@858 { 206 compatible = "hisilicon,hi3798cv200-combphy"; 207 reg = <0x858 0x8>; 208 #phy-cells = <1>; 209 clocks = <&crg HISTB_COMBPHY1_CLK>; 210 resets = <&crg 0x188 12>; 211 assigned-clocks = <&crg HISTB_COMBPHY1_CLK>; 212 assigned-clock-rates = <100000000>; 213 hisilicon,mode-select-bits = <0x0008 11 (0x3 << 11)>; 214 }; 215 }; 216 217 pmx0: pinconf@8a21000 { 218 compatible = "pinconf-single"; 219 reg = <0x8a21000 0x180>; 220 pinctrl-single,register-width = <32>; 221 pinctrl-single,function-mask = <7>; 222 pinctrl-single,gpio-range = < 223 &range 0 8 2 /* GPIO 0 */ 224 &range 8 1 0 /* GPIO 1 */ 225 &range 9 4 2 226 &range 13 1 0 227 &range 14 1 1 228 &range 15 1 0 229 &range 16 5 0 /* GPIO 2 */ 230 &range 21 3 1 231 &range 24 4 1 /* GPIO 3 */ 232 &range 28 2 2 233 &range 86 1 1 234 &range 87 1 0 235 &range 30 4 2 /* GPIO 4 */ 236 &range 34 3 0 237 &range 37 1 2 238 &range 38 3 2 /* GPIO 6 */ 239 &range 41 5 0 240 &range 46 8 1 /* GPIO 7 */ 241 &range 54 8 1 /* GPIO 8 */ 242 &range 64 7 1 /* GPIO 9 */ 243 &range 71 1 0 244 &range 72 6 1 /* GPIO 10 */ 245 &range 78 1 0 246 &range 79 1 1 247 &range 80 6 1 /* GPIO 11 */ 248 &range 70 2 1 249 &range 88 8 0 /* GPIO 12 */ 250 >; 251 252 range: gpio-range { 253 #pinctrl-single,gpio-range-cells = <3>; 254 }; 255 }; 256 257 uart0: serial@8b00000 { 258 compatible = "arm,pl011", "arm,primecell"; 259 reg = <0x8b00000 0x1000>; 260 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 261 clocks = <&sysctrl HISTB_UART0_CLK>, <&sysctrl HISTB_UART0_CLK>; 262 clock-names = "uartclk", "apb_pclk"; 263 status = "disabled"; 264 }; 265 266 uart2: serial@8b02000 { 267 compatible = "arm,pl011", "arm,primecell"; 268 reg = <0x8b02000 0x1000>; 269 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 270 clocks = <&crg HISTB_UART2_CLK>, <&crg HISTB_UART2_CLK>; 271 clock-names = "uartclk", "apb_pclk"; 272 status = "disabled"; 273 }; 274 275 i2c0: i2c@8b10000 { 276 compatible = "hisilicon,hix5hd2-i2c"; 277 reg = <0x8b10000 0x1000>; 278 #address-cells = <1>; 279 #size-cells = <0>; 280 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 281 clock-frequency = <400000>; 282 clocks = <&crg HISTB_I2C0_CLK>; 283 status = "disabled"; 284 }; 285 286 i2c1: i2c@8b11000 { 287 compatible = "hisilicon,hix5hd2-i2c"; 288 reg = <0x8b11000 0x1000>; 289 #address-cells = <1>; 290 #size-cells = <0>; 291 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 292 clock-frequency = <400000>; 293 clocks = <&crg HISTB_I2C1_CLK>; 294 status = "disabled"; 295 }; 296 297 i2c2: i2c@8b12000 { 298 compatible = "hisilicon,hix5hd2-i2c"; 299 reg = <0x8b12000 0x1000>; 300 #address-cells = <1>; 301 #size-cells = <0>; 302 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 303 clock-frequency = <400000>; 304 clocks = <&crg HISTB_I2C2_CLK>; 305 status = "disabled"; 306 }; 307 308 i2c3: i2c@8b13000 { 309 compatible = "hisilicon,hix5hd2-i2c"; 310 reg = <0x8b13000 0x1000>; 311 #address-cells = <1>; 312 #size-cells = <0>; 313 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 314 clock-frequency = <400000>; 315 clocks = <&crg HISTB_I2C3_CLK>; 316 status = "disabled"; 317 }; 318 319 i2c4: i2c@8b14000 { 320 compatible = "hisilicon,hix5hd2-i2c"; 321 reg = <0x8b14000 0x1000>; 322 #address-cells = <1>; 323 #size-cells = <0>; 324 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 325 clock-frequency = <400000>; 326 clocks = <&crg HISTB_I2C4_CLK>; 327 status = "disabled"; 328 }; 329 330 spi0: spi@8b1a000 { 331 compatible = "arm,pl022", "arm,primecell"; 332 reg = <0x8b1a000 0x1000>; 333 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 334 num-cs = <1>; 335 cs-gpios = <&gpio7 1 0>; 336 clocks = <&crg HISTB_SPI0_CLK>, <&crg HISTB_SPI0_CLK>; 337 clock-names = "sspclk", "apb_pclk"; 338 #address-cells = <1>; 339 #size-cells = <0>; 340 status = "disabled"; 341 }; 342 343 sd0: mmc@9820000 { 344 compatible = "snps,dw-mshc"; 345 reg = <0x9820000 0x10000>; 346 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 347 clocks = <&crg HISTB_SDIO0_BIU_CLK>, 348 <&crg HISTB_SDIO0_CIU_CLK>; 349 clock-names = "biu", "ciu"; 350 resets = <&crg 0x9c 4>; 351 reset-names = "reset"; 352 status = "disabled"; 353 }; 354 355 emmc: mmc@9830000 { 356 compatible = "hisilicon,hi3798cv200-dw-mshc"; 357 reg = <0x9830000 0x10000>; 358 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 359 clocks = <&crg HISTB_MMC_CIU_CLK>, 360 <&crg HISTB_MMC_BIU_CLK>, 361 <&crg HISTB_MMC_SAMPLE_CLK>, 362 <&crg HISTB_MMC_DRV_CLK>; 363 clock-names = "ciu", "biu", "ciu-sample", "ciu-drive"; 364 resets = <&crg 0xa0 4>; 365 reset-names = "reset"; 366 status = "disabled"; 367 }; 368 369 gpio0: gpio@8b20000 { 370 compatible = "arm,pl061", "arm,primecell"; 371 reg = <0x8b20000 0x1000>; 372 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 373 gpio-controller; 374 #gpio-cells = <2>; 375 interrupt-controller; 376 #interrupt-cells = <2>; 377 gpio-ranges = <&pmx0 0 0 8>; 378 clocks = <&crg HISTB_APB_CLK>; 379 clock-names = "apb_pclk"; 380 status = "disabled"; 381 }; 382 383 gpio1: gpio@8b21000 { 384 compatible = "arm,pl061", "arm,primecell"; 385 reg = <0x8b21000 0x1000>; 386 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 387 gpio-controller; 388 #gpio-cells = <2>; 389 interrupt-controller; 390 #interrupt-cells = <2>; 391 gpio-ranges = < 392 &pmx0 0 8 1 393 &pmx0 1 9 4 394 &pmx0 5 13 1 395 &pmx0 6 14 1 396 &pmx0 7 15 1 397 >; 398 clocks = <&crg HISTB_APB_CLK>; 399 clock-names = "apb_pclk"; 400 status = "disabled"; 401 }; 402 403 gpio2: gpio@8b22000 { 404 compatible = "arm,pl061", "arm,primecell"; 405 reg = <0x8b22000 0x1000>; 406 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 407 gpio-controller; 408 #gpio-cells = <2>; 409 interrupt-controller; 410 #interrupt-cells = <2>; 411 gpio-ranges = <&pmx0 0 16 5 &pmx0 5 21 3>; 412 clocks = <&crg HISTB_APB_CLK>; 413 clock-names = "apb_pclk"; 414 status = "disabled"; 415 }; 416 417 gpio3: gpio@8b23000 { 418 compatible = "arm,pl061", "arm,primecell"; 419 reg = <0x8b23000 0x1000>; 420 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 421 gpio-controller; 422 #gpio-cells = <2>; 423 interrupt-controller; 424 #interrupt-cells = <2>; 425 gpio-ranges = < 426 &pmx0 0 24 4 427 &pmx0 4 28 2 428 &pmx0 6 86 1 429 &pmx0 7 87 1 430 >; 431 clocks = <&crg HISTB_APB_CLK>; 432 clock-names = "apb_pclk"; 433 status = "disabled"; 434 }; 435 436 gpio4: gpio@8b24000 { 437 compatible = "arm,pl061", "arm,primecell"; 438 reg = <0x8b24000 0x1000>; 439 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 440 gpio-controller; 441 #gpio-cells = <2>; 442 interrupt-controller; 443 #interrupt-cells = <2>; 444 gpio-ranges = <&pmx0 0 30 4 &pmx0 4 34 3 &pmx0 7 37 1>; 445 clocks = <&crg HISTB_APB_CLK>; 446 clock-names = "apb_pclk"; 447 status = "disabled"; 448 }; 449 450 gpio5: gpio@8004000 { 451 compatible = "arm,pl061", "arm,primecell"; 452 reg = <0x8004000 0x1000>; 453 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 454 gpio-controller; 455 #gpio-cells = <2>; 456 interrupt-controller; 457 #interrupt-cells = <2>; 458 clocks = <&crg HISTB_APB_CLK>; 459 clock-names = "apb_pclk"; 460 status = "disabled"; 461 }; 462 463 gpio6: gpio@8b26000 { 464 compatible = "arm,pl061", "arm,primecell"; 465 reg = <0x8b26000 0x1000>; 466 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 467 gpio-controller; 468 #gpio-cells = <2>; 469 interrupt-controller; 470 #interrupt-cells = <2>; 471 gpio-ranges = <&pmx0 0 38 3 &pmx0 0 41 5>; 472 clocks = <&crg HISTB_APB_CLK>; 473 clock-names = "apb_pclk"; 474 status = "disabled"; 475 }; 476 477 gpio7: gpio@8b27000 { 478 compatible = "arm,pl061", "arm,primecell"; 479 reg = <0x8b27000 0x1000>; 480 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 481 gpio-controller; 482 #gpio-cells = <2>; 483 interrupt-controller; 484 #interrupt-cells = <2>; 485 gpio-ranges = <&pmx0 0 46 8>; 486 clocks = <&crg HISTB_APB_CLK>; 487 clock-names = "apb_pclk"; 488 status = "disabled"; 489 }; 490 491 gpio8: gpio@8b28000 { 492 compatible = "arm,pl061", "arm,primecell"; 493 reg = <0x8b28000 0x1000>; 494 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 495 gpio-controller; 496 #gpio-cells = <2>; 497 interrupt-controller; 498 #interrupt-cells = <2>; 499 gpio-ranges = <&pmx0 0 54 8>; 500 clocks = <&crg HISTB_APB_CLK>; 501 clock-names = "apb_pclk"; 502 status = "disabled"; 503 }; 504 505 gpio9: gpio@8b29000 { 506 compatible = "arm,pl061", "arm,primecell"; 507 reg = <0x8b29000 0x1000>; 508 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 509 gpio-controller; 510 #gpio-cells = <2>; 511 interrupt-controller; 512 #interrupt-cells = <2>; 513 gpio-ranges = <&pmx0 0 64 7 &pmx0 71 1>; 514 clocks = <&crg HISTB_APB_CLK>; 515 clock-names = "apb_pclk"; 516 status = "disabled"; 517 }; 518 519 gpio10: gpio@8b2a000 { 520 compatible = "arm,pl061", "arm,primecell"; 521 reg = <0x8b2a000 0x1000>; 522 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 523 gpio-controller; 524 #gpio-cells = <2>; 525 interrupt-controller; 526 #interrupt-cells = <2>; 527 gpio-ranges = <&pmx0 0 72 6 &pmx0 6 78 1 &pmx0 7 79 1>; 528 clocks = <&crg HISTB_APB_CLK>; 529 clock-names = "apb_pclk"; 530 status = "disabled"; 531 }; 532 533 gpio11: gpio@8b2b000 { 534 compatible = "arm,pl061", "arm,primecell"; 535 reg = <0x8b2b000 0x1000>; 536 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 537 gpio-controller; 538 #gpio-cells = <2>; 539 interrupt-controller; 540 #interrupt-cells = <2>; 541 gpio-ranges = <&pmx0 0 80 6 &pmx0 6 70 2>; 542 clocks = <&crg HISTB_APB_CLK>; 543 clock-names = "apb_pclk"; 544 status = "disabled"; 545 }; 546 547 gpio12: gpio@8b2c000 { 548 compatible = "arm,pl061", "arm,primecell"; 549 reg = <0x8b2c000 0x1000>; 550 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 551 gpio-controller; 552 #gpio-cells = <2>; 553 interrupt-controller; 554 #interrupt-cells = <2>; 555 gpio-ranges = <&pmx0 0 88 8>; 556 clocks = <&crg HISTB_APB_CLK>; 557 clock-names = "apb_pclk"; 558 status = "disabled"; 559 }; 560 561 gmac0: ethernet@9840000 { 562 compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2"; 563 reg = <0x9840000 0x1000>, 564 <0x984300c 0x4>; 565 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 566 clocks = <&crg HISTB_ETH0_MAC_CLK>, 567 <&crg HISTB_ETH0_MACIF_CLK>; 568 clock-names = "mac_core", "mac_ifc"; 569 resets = <&crg 0xcc 8>, 570 <&crg 0xcc 10>, 571 <&gmacphyrst 0>; 572 reset-names = "mac_core", "mac_ifc", "phy"; 573 status = "disabled"; 574 }; 575 576 gmac1: ethernet@9841000 { 577 compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2"; 578 reg = <0x9841000 0x1000>, 579 <0x9843010 0x4>; 580 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 581 clocks = <&crg HISTB_ETH1_MAC_CLK>, 582 <&crg HISTB_ETH1_MACIF_CLK>; 583 clock-names = "mac_core", "mac_ifc"; 584 resets = <&crg 0xcc 9>, 585 <&crg 0xcc 11>, 586 <&gmacphyrst 1>; 587 reset-names = "mac_core", "mac_ifc", "phy"; 588 status = "disabled"; 589 }; 590 591 ir: ir@8001000 { 592 compatible = "hisilicon,hix5hd2-ir"; 593 reg = <0x8001000 0x1000>; 594 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 595 clocks = <&sysctrl HISTB_IR_CLK>; 596 status = "disabled"; 597 }; 598 599 pcie: pcie@9860000 { 600 compatible = "hisilicon,hi3798cv200-pcie"; 601 reg = <0x9860000 0x1000>, 602 <0x0 0x2000>, 603 <0x2000000 0x01000000>; 604 reg-names = "control", "rc-dbi", "config"; 605 #address-cells = <3>; 606 #size-cells = <2>; 607 device_type = "pci"; 608 bus-range = <0x00 0xff>; 609 num-lanes = <1>; 610 ranges = <0x81000000 0x0 0x00000000 0x4f00000 0x0 0x100000>, 611 <0x82000000 0x0 0x3000000 0x3000000 0x0 0x01f00000>; 612 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 613 interrupt-names = "msi"; 614 #interrupt-cells = <1>; 615 interrupt-map-mask = <0 0 0 0>; 616 interrupt-map = <0 0 0 0 &gic 0 131 IRQ_TYPE_LEVEL_HIGH>; 617 clocks = <&crg HISTB_PCIE_AUX_CLK>, 618 <&crg HISTB_PCIE_PIPE_CLK>, 619 <&crg HISTB_PCIE_SYS_CLK>, 620 <&crg HISTB_PCIE_BUS_CLK>; 621 clock-names = "aux", "pipe", "sys", "bus"; 622 resets = <&crg 0x18c 6>, <&crg 0x18c 5>, <&crg 0x18c 4>; 623 reset-names = "soft", "sys", "bus"; 624 phys = <&combphy1 PHY_TYPE_PCIE>; 625 phy-names = "phy"; 626 status = "disabled"; 627 }; 628 629 ohci: usb@9880000 { 630 compatible = "generic-ohci"; 631 reg = <0x9880000 0x10000>; 632 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 633 clocks = <&crg HISTB_USB2_BUS_CLK>, 634 <&crg HISTB_USB2_12M_CLK>, 635 <&crg HISTB_USB2_48M_CLK>; 636 clock-names = "bus", "clk12", "clk48"; 637 resets = <&crg 0xb8 12>; 638 reset-names = "bus"; 639 phys = <&usb2_phy1_port0>; 640 phy-names = "usb"; 641 status = "disabled"; 642 }; 643 644 ehci: usb@9890000 { 645 compatible = "generic-ehci"; 646 reg = <0x9890000 0x10000>; 647 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 648 clocks = <&crg HISTB_USB2_BUS_CLK>, 649 <&crg HISTB_USB2_PHY_CLK>, 650 <&crg HISTB_USB2_UTMI_CLK>; 651 clock-names = "bus", "phy", "utmi"; 652 resets = <&crg 0xb8 12>, 653 <&crg 0xb8 16>, 654 <&crg 0xb8 13>; 655 reset-names = "bus", "phy", "utmi"; 656 phys = <&usb2_phy1_port0>; 657 phy-names = "usb"; 658 status = "disabled"; 659 }; 660 }; 661}; 662