1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the R-Mobile A1 (R8A77400) SoC 4 * 5 * Copyright (C) 2012 Renesas Solutions Corp. 6 */ 7 8#include <dt-bindings/clock/r8a7740-clock.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11 12/ { 13 compatible = "renesas,r8a7740"; 14 interrupt-parent = <&gic>; 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 cpus { 19 #address-cells = <1>; 20 #size-cells = <0>; 21 cpu0: cpu@0 { 22 compatible = "arm,cortex-a9"; 23 device_type = "cpu"; 24 reg = <0x0>; 25 clock-frequency = <800000000>; 26 power-domains = <&pd_a3sm>; 27 next-level-cache = <&L2>; 28 }; 29 }; 30 31 gic: interrupt-controller@c2800000 { 32 compatible = "arm,pl390"; 33 #interrupt-cells = <3>; 34 interrupt-controller; 35 reg = <0xc2800000 0x1000>, 36 <0xc2000000 0x1000>; 37 }; 38 39 L2: cache-controller@f0100000 { 40 compatible = "arm,pl310-cache"; 41 reg = <0xf0100000 0x1000>; 42 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 43 power-domains = <&pd_a3sm>; 44 arm,data-latency = <3 3 3>; 45 arm,tag-latency = <2 2 2>; 46 arm,shared-override; 47 cache-unified; 48 cache-level = <2>; 49 }; 50 51 dbsc3: memory-controller@fe400000 { 52 compatible = "renesas,dbsc3-r8a7740"; 53 reg = <0xfe400000 0x400>; 54 power-domains = <&pd_a4s>; 55 }; 56 57 pmu { 58 compatible = "arm,cortex-a9-pmu"; 59 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 60 }; 61 62 replicator { 63 compatible = "arm,coresight-static-replicator"; 64 clocks = <&cpg_clocks R8A7740_CLK_ZTR>; 65 clock-names = "atclk"; 66 power-domains = <&pd_d4>; 67 68 out-ports { 69 #address-cells = <1>; 70 #size-cells = <0>; 71 72 /* replicator output ports */ 73 port@0 { 74 reg = <0>; 75 76 replicator_out_port0: endpoint { 77 remote-endpoint = <&tpiu_in_port>; 78 }; 79 }; 80 port@1 { 81 reg = <1>; 82 83 replicator_out_port1: endpoint { 84 remote-endpoint = <&etb_in_port>; 85 }; 86 }; 87 }; 88 89 in-ports { 90 /* replicator input port */ 91 port { 92 replicator_in_port0: endpoint { 93 remote-endpoint = <&funnel_out_port>; 94 }; 95 }; 96 }; 97 }; 98 99 etb@e6fa1000 { 100 compatible = "arm,coresight-etb10", "arm,primecell"; 101 reg = <0xe6fa1000 0x1000>; 102 clocks = <&cpg_clocks R8A7740_CLK_ZT>, <&cpg_clocks R8A7740_CLK_ZTR>; 103 clock-names = "apb_pclk", "atclk"; 104 power-domains = <&pd_d4>; 105 106 in-ports { 107 port { 108 etb_in_port: endpoint { 109 remote-endpoint = <&replicator_out_port1>; 110 }; 111 }; 112 }; 113 }; 114 115 tpiu@e6fa3000 { 116 compatible = "arm,coresight-tpiu", "arm,primecell"; 117 reg = <0xe6fa3000 0x1000>; 118 clocks = <&cpg_clocks R8A7740_CLK_ZT>, <&cpg_clocks R8A7740_CLK_ZTR>; 119 clock-names = "apb_pclk", "atclk"; 120 power-domains = <&pd_d4>; 121 122 in-ports { 123 port { 124 tpiu_in_port: endpoint { 125 remote-endpoint = <&replicator_out_port0>; 126 }; 127 }; 128 }; 129 }; 130 131 funnel { 132 compatible = "arm,coresight-static-funnel"; 133 134 /* funnel output ports */ 135 out-ports { 136 port { 137 funnel_out_port: endpoint { 138 remote-endpoint = 139 <&replicator_in_port0>; 140 }; 141 }; 142 }; 143 144 in-ports { 145 #address-cells = <1>; 146 #size-cells = <0>; 147 148 /* funnel input ports */ 149 port@0 { 150 reg = <0>; 151 funnel0_in_port0: endpoint { 152 remote-endpoint = <&ptm0_out_port>; 153 }; 154 }; 155 }; 156 }; 157 158 ptm@e6fbc000 { 159 compatible = "arm,coresight-etm3x", "arm,primecell"; 160 reg = <0xe6fbc000 0x1000>; 161 clocks = <&cpg_clocks R8A7740_CLK_ZT>, <&cpg_clocks R8A7740_CLK_ZTR>; 162 clock-names = "apb_pclk", "atclk"; 163 cpu = <&cpu0>; 164 power-domains = <&pd_d4>; 165 166 out-ports { 167 port { 168 ptm0_out_port: endpoint { 169 remote-endpoint = <&funnel0_in_port0>; 170 }; 171 }; 172 }; 173 }; 174 175 ceu0: ceu@fe910000 { 176 reg = <0xfe910000 0x3000>; 177 compatible = "renesas,r8a7740-ceu"; 178 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 179 clocks = <&mstp1_clks R8A7740_CLK_CEU20>; 180 power-domains = <&pd_a4r>; 181 status = "disabled"; 182 }; 183 184 ceu1: ceu@fe914000 { 185 reg = <0xfe914000 0x3000>; 186 compatible = "renesas,r8a7740-ceu"; 187 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 188 clocks = <&mstp1_clks R8A7740_CLK_CEU21>; 189 power-domains = <&pd_a4r>; 190 status = "disabled"; 191 }; 192 193 cmt1: timer@e6138000 { 194 compatible = "renesas,r8a7740-cmt1"; 195 reg = <0xe6138000 0x170>; 196 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 197 clocks = <&mstp3_clks R8A7740_CLK_CMT1>; 198 clock-names = "fck"; 199 power-domains = <&pd_c5>; 200 status = "disabled"; 201 }; 202 203 /* irqpin0: IRQ0 - IRQ7 */ 204 irqpin0: interrupt-controller@e6900000 { 205 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; 206 #interrupt-cells = <2>; 207 interrupt-controller; 208 reg = <0xe6900000 4>, 209 <0xe6900010 4>, 210 <0xe6900020 1>, 211 <0xe6900040 1>, 212 <0xe6900060 1>; 213 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 221 clocks = <&mstp2_clks R8A7740_CLK_INTCA>; 222 power-domains = <&pd_a4s>; 223 }; 224 225 /* irqpin1: IRQ8 - IRQ15 */ 226 irqpin1: interrupt-controller@e6900004 { 227 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; 228 #interrupt-cells = <2>; 229 interrupt-controller; 230 reg = <0xe6900004 4>, 231 <0xe6900014 4>, 232 <0xe6900024 1>, 233 <0xe6900044 1>, 234 <0xe6900064 1>; 235 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 236 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 237 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 238 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 239 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 240 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 241 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 242 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 243 clocks = <&mstp2_clks R8A7740_CLK_INTCA>; 244 power-domains = <&pd_a4s>; 245 }; 246 247 /* irqpin2: IRQ16 - IRQ23 */ 248 irqpin2: interrupt-controller@e6900008 { 249 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; 250 #interrupt-cells = <2>; 251 interrupt-controller; 252 reg = <0xe6900008 4>, 253 <0xe6900018 4>, 254 <0xe6900028 1>, 255 <0xe6900048 1>, 256 <0xe6900068 1>; 257 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 258 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 259 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 260 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 261 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 262 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 263 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 264 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 265 clocks = <&mstp2_clks R8A7740_CLK_INTCA>; 266 power-domains = <&pd_a4s>; 267 }; 268 269 /* irqpin3: IRQ24 - IRQ31 */ 270 irqpin3: interrupt-controller@e690000c { 271 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; 272 #interrupt-cells = <2>; 273 interrupt-controller; 274 reg = <0xe690000c 4>, 275 <0xe690001c 4>, 276 <0xe690002c 1>, 277 <0xe690004c 1>, 278 <0xe690006c 1>; 279 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 280 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 286 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 287 clocks = <&mstp2_clks R8A7740_CLK_INTCA>; 288 power-domains = <&pd_a4s>; 289 }; 290 291 ether: ethernet@e9a00000 { 292 compatible = "renesas,gether-r8a7740"; 293 reg = <0xe9a00000 0x800>, 294 <0xe9a01800 0x800>; 295 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 296 clocks = <&mstp3_clks R8A7740_CLK_GETHER>; 297 power-domains = <&pd_a4s>; 298 phy-mode = "mii"; 299 #address-cells = <1>; 300 #size-cells = <0>; 301 status = "disabled"; 302 }; 303 304 i2c0: i2c@fff20000 { 305 #address-cells = <1>; 306 #size-cells = <0>; 307 compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic"; 308 reg = <0xfff20000 0x425>; 309 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 310 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 311 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 312 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 313 clocks = <&mstp1_clks R8A7740_CLK_IIC0>; 314 power-domains = <&pd_a4r>; 315 status = "disabled"; 316 }; 317 318 i2c1: i2c@e6c20000 { 319 #address-cells = <1>; 320 #size-cells = <0>; 321 compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic"; 322 reg = <0xe6c20000 0x425>; 323 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 324 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 325 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 326 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 327 clocks = <&mstp3_clks R8A7740_CLK_IIC1>; 328 power-domains = <&pd_a3sp>; 329 status = "disabled"; 330 }; 331 332 scifa0: serial@e6c40000 { 333 compatible = "renesas,scifa-r8a7740", "renesas,scifa"; 334 reg = <0xe6c40000 0x100>; 335 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 336 clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>; 337 clock-names = "fck"; 338 power-domains = <&pd_a3sp>; 339 status = "disabled"; 340 }; 341 342 scifa1: serial@e6c50000 { 343 compatible = "renesas,scifa-r8a7740", "renesas,scifa"; 344 reg = <0xe6c50000 0x100>; 345 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 346 clocks = <&mstp2_clks R8A7740_CLK_SCIFA1>; 347 clock-names = "fck"; 348 power-domains = <&pd_a3sp>; 349 status = "disabled"; 350 }; 351 352 scifa2: serial@e6c60000 { 353 compatible = "renesas,scifa-r8a7740", "renesas,scifa"; 354 reg = <0xe6c60000 0x100>; 355 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 356 clocks = <&mstp2_clks R8A7740_CLK_SCIFA2>; 357 clock-names = "fck"; 358 power-domains = <&pd_a3sp>; 359 status = "disabled"; 360 }; 361 362 scifa3: serial@e6c70000 { 363 compatible = "renesas,scifa-r8a7740", "renesas,scifa"; 364 reg = <0xe6c70000 0x100>; 365 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 366 clocks = <&mstp2_clks R8A7740_CLK_SCIFA3>; 367 clock-names = "fck"; 368 power-domains = <&pd_a3sp>; 369 status = "disabled"; 370 }; 371 372 scifa4: serial@e6c80000 { 373 compatible = "renesas,scifa-r8a7740", "renesas,scifa"; 374 reg = <0xe6c80000 0x100>; 375 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 376 clocks = <&mstp2_clks R8A7740_CLK_SCIFA4>; 377 clock-names = "fck"; 378 power-domains = <&pd_a3sp>; 379 status = "disabled"; 380 }; 381 382 scifa5: serial@e6cb0000 { 383 compatible = "renesas,scifa-r8a7740", "renesas,scifa"; 384 reg = <0xe6cb0000 0x100>; 385 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 386 clocks = <&mstp2_clks R8A7740_CLK_SCIFA5>; 387 clock-names = "fck"; 388 power-domains = <&pd_a3sp>; 389 status = "disabled"; 390 }; 391 392 scifa6: serial@e6cc0000 { 393 compatible = "renesas,scifa-r8a7740", "renesas,scifa"; 394 reg = <0xe6cc0000 0x100>; 395 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 396 clocks = <&mstp2_clks R8A7740_CLK_SCIFA6>; 397 clock-names = "fck"; 398 power-domains = <&pd_a3sp>; 399 status = "disabled"; 400 }; 401 402 scifa7: serial@e6cd0000 { 403 compatible = "renesas,scifa-r8a7740", "renesas,scifa"; 404 reg = <0xe6cd0000 0x100>; 405 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 406 clocks = <&mstp2_clks R8A7740_CLK_SCIFA7>; 407 clock-names = "fck"; 408 power-domains = <&pd_a3sp>; 409 status = "disabled"; 410 }; 411 412 scifb: serial@e6c30000 { 413 compatible = "renesas,scifb-r8a7740", "renesas,scifb"; 414 reg = <0xe6c30000 0x100>; 415 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 416 clocks = <&mstp2_clks R8A7740_CLK_SCIFB>; 417 clock-names = "fck"; 418 power-domains = <&pd_a3sp>; 419 status = "disabled"; 420 }; 421 422 pfc: pinctrl@e6050000 { 423 compatible = "renesas,pfc-r8a7740"; 424 reg = <0xe6050000 0x8000>, 425 <0xe605800c 0x20>; 426 gpio-controller; 427 #gpio-cells = <2>; 428 gpio-ranges = <&pfc 0 0 212>; 429 interrupts-extended = 430 <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>, 431 <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>, 432 <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>, 433 <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>, 434 <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>, 435 <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>, 436 <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>, 437 <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>; 438 power-domains = <&pd_c5>; 439 }; 440 441 tpu: pwm@e6600000 { 442 compatible = "renesas,tpu-r8a7740", "renesas,tpu"; 443 reg = <0xe6600000 0x148>; 444 clocks = <&mstp3_clks R8A7740_CLK_TPU0>; 445 power-domains = <&pd_a3sp>; 446 status = "disabled"; 447 #pwm-cells = <3>; 448 }; 449 450 mmcif0: mmc@e6bd0000 { 451 compatible = "renesas,mmcif-r8a7740", "renesas,sh-mmcif"; 452 reg = <0xe6bd0000 0x100>; 453 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 454 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 455 clocks = <&mstp3_clks R8A7740_CLK_MMC>; 456 power-domains = <&pd_a3sp>; 457 status = "disabled"; 458 }; 459 460 sdhi0: mmc@e6850000 { 461 compatible = "renesas,sdhi-r8a7740"; 462 reg = <0xe6850000 0x100>; 463 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 464 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 465 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 466 clocks = <&mstp3_clks R8A7740_CLK_SDHI0>; 467 power-domains = <&pd_a3sp>; 468 cap-sd-highspeed; 469 cap-sdio-irq; 470 status = "disabled"; 471 }; 472 473 sdhi1: mmc@e6860000 { 474 compatible = "renesas,sdhi-r8a7740"; 475 reg = <0xe6860000 0x100>; 476 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 477 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 478 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 479 clocks = <&mstp3_clks R8A7740_CLK_SDHI1>; 480 power-domains = <&pd_a3sp>; 481 cap-sd-highspeed; 482 cap-sdio-irq; 483 status = "disabled"; 484 }; 485 486 sdhi2: mmc@e6870000 { 487 compatible = "renesas,sdhi-r8a7740"; 488 reg = <0xe6870000 0x100>; 489 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 490 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 491 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 492 clocks = <&mstp4_clks R8A7740_CLK_SDHI2>; 493 power-domains = <&pd_a3sp>; 494 cap-sd-highspeed; 495 cap-sdio-irq; 496 status = "disabled"; 497 }; 498 499 sh_fsi2: sound@fe1f0000 { 500 #sound-dai-cells = <1>; 501 compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2"; 502 reg = <0xfe1f0000 0x400>; 503 interrupts = <GIC_SPI 9 0x4>; 504 clocks = <&mstp3_clks R8A7740_CLK_FSI>; 505 power-domains = <&pd_a4mp>; 506 status = "disabled"; 507 }; 508 509 lcdc0: lcd-controller@fe940000 { 510 compatible = "renesas,r8a7740-lcdc"; 511 reg = <0xfe940000 0x4000>; 512 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 513 clocks = <&mstp1_clks R8A7740_CLK_LCDC0>, 514 <&cpg_clocks R8A7740_CLK_M3>, <&lcdlclk0_clk>, 515 <&vou_clk>; 516 clock-names = "fck", "media", "lclk", "video"; 517 power-domains = <&pd_a4lc>; 518 status = "disabled"; 519 520 ports { 521 #address-cells = <1>; 522 #size-cells = <0>; 523 524 port@0 { 525 reg = <0>; 526 527 lcdc0_rgb: endpoint { 528 }; 529 }; 530 }; 531 }; 532 533 lcdc1: lcd-controller@fe944000 { 534 compatible = "renesas,r8a7740-lcdc"; 535 reg = <0xfe944000 0x4000>; 536 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 537 clocks = <&mstp1_clks R8A7740_CLK_LCDC1>, 538 <&cpg_clocks R8A7740_CLK_M3>, <&lcdlclk1_clk>, 539 <&vou_clk>; 540 clock-names = "fck", "media", "lclk", "video"; 541 power-domains = <&pd_a4lc>; 542 status = "disabled"; 543 544 ports { 545 #address-cells = <1>; 546 #size-cells = <0>; 547 548 port@0 { 549 reg = <0>; 550 551 lcdc1_rgb: endpoint { 552 }; 553 }; 554 555 port@1 { 556 reg = <1>; 557 558 lcdc1_hdmi: endpoint { 559 }; 560 }; 561 }; 562 }; 563 564 tmu0: timer@fff80000 { 565 compatible = "renesas,tmu-r8a7740", "renesas,tmu"; 566 reg = <0xfff80000 0x2c>; 567 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 568 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 569 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 570 interrupt-names = "tuni0", "tuni1", "tuni2"; 571 clocks = <&mstp1_clks R8A7740_CLK_TMU0>; 572 clock-names = "fck"; 573 power-domains = <&pd_a4r>; 574 575 #renesas,channels = <3>; 576 577 status = "disabled"; 578 }; 579 580 tmu1: timer@fff90000 { 581 compatible = "renesas,tmu-r8a7740", "renesas,tmu"; 582 reg = <0xfff90000 0x2c>; 583 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 586 interrupt-names = "tuni0", "tuni1", "tuni2"; 587 clocks = <&mstp1_clks R8A7740_CLK_TMU1>; 588 clock-names = "fck"; 589 power-domains = <&pd_a4r>; 590 591 #renesas,channels = <3>; 592 593 status = "disabled"; 594 }; 595 596 clocks { 597 #address-cells = <1>; 598 #size-cells = <1>; 599 ranges; 600 601 /* External root clock */ 602 extalr_clk: extalr { 603 compatible = "fixed-clock"; 604 #clock-cells = <0>; 605 clock-frequency = <32768>; 606 }; 607 extal1_clk: extal1 { 608 compatible = "fixed-clock"; 609 #clock-cells = <0>; 610 clock-frequency = <0>; 611 }; 612 extal2_clk: extal2 { 613 compatible = "fixed-clock"; 614 #clock-cells = <0>; 615 clock-frequency = <0>; 616 }; 617 dv_clk: dv { 618 compatible = "fixed-clock"; 619 #clock-cells = <0>; 620 clock-frequency = <27000000>; 621 }; 622 fmsick_clk: fmsick { 623 compatible = "fixed-clock"; 624 #clock-cells = <0>; 625 clock-frequency = <0>; 626 }; 627 fmsock_clk: fmsock { 628 compatible = "fixed-clock"; 629 #clock-cells = <0>; 630 clock-frequency = <0>; 631 }; 632 fsiack_clk: fsiack { 633 compatible = "fixed-clock"; 634 #clock-cells = <0>; 635 clock-frequency = <0>; 636 }; 637 fsibck_clk: fsibck { 638 compatible = "fixed-clock"; 639 #clock-cells = <0>; 640 clock-frequency = <0>; 641 }; 642 lcdlclk0_clk: lcdlclk0 { 643 compatible = "fixed-clock"; 644 #clock-cells = <0>; 645 clock-frequency = <0>; 646 }; 647 lcdlclk1_clk: lcdlclk1 { 648 compatible = "fixed-clock"; 649 #clock-cells = <0>; 650 clock-frequency = <0>; 651 }; 652 653 /* Special CPG clocks */ 654 cpg_clocks: cpg_clocks@e6150000 { 655 compatible = "renesas,r8a7740-cpg-clocks"; 656 reg = <0xe6150000 0x10000>; 657 clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>; 658 #clock-cells = <1>; 659 clock-output-names = "system", "pllc0", "pllc1", 660 "pllc2", "r", 661 "usb24s", 662 "i", "zg", "b", "m1", "hp", 663 "hpp", "usbp", "s", "zb", "m3", 664 "cp", "ztr", "zt"; 665 }; 666 667 /* Variable factor clocks (DIV6) */ 668 vclk1_clk: vclk1@e6150008 { 669 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; 670 reg = <0xe6150008 4>; 671 clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>, 672 <&cpg_clocks R8A7740_CLK_USB24S>, 673 <&extal1_div2_clk>, <&extalr_clk>, <0>, 674 <0>; 675 #clock-cells = <0>; 676 }; 677 vclk2_clk: vclk2@e615000c { 678 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; 679 reg = <0xe615000c 4>; 680 clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>, 681 <&cpg_clocks R8A7740_CLK_USB24S>, 682 <&extal1_div2_clk>, <&extalr_clk>, <0>, 683 <0>; 684 #clock-cells = <0>; 685 }; 686 fmsi_clk: fmsi@e6150010 { 687 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; 688 reg = <0xe6150010 4>; 689 clocks = <&pllc1_div2_clk>, <&fmsick_clk>, <0>, <0>; 690 #clock-cells = <0>; 691 }; 692 fmso_clk: fmso@e6150014 { 693 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; 694 reg = <0xe6150014 4>; 695 clocks = <&pllc1_div2_clk>, <&fmsock_clk>, <0>, <0>; 696 #clock-cells = <0>; 697 }; 698 fsia_clk: fsia@e6150018 { 699 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; 700 reg = <0xe6150018 4>; 701 clocks = <&pllc1_div2_clk>, <&fsiack_clk>, <0>, <0>; 702 #clock-cells = <0>; 703 }; 704 sub_clk: sub@e6150080 { 705 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; 706 reg = <0xe6150080 4>; 707 clocks = <&pllc1_div2_clk>, 708 <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>; 709 #clock-cells = <0>; 710 }; 711 spu_clk: spu@e6150084 { 712 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; 713 reg = <0xe6150084 4>; 714 clocks = <&pllc1_div2_clk>, 715 <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>; 716 #clock-cells = <0>; 717 }; 718 vou_clk: vou@e6150088 { 719 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; 720 reg = <0xe6150088 4>; 721 clocks = <&pllc1_div2_clk>, <&extal1_clk>, <&dv_clk>, 722 <0>; 723 #clock-cells = <0>; 724 }; 725 stpro_clk: stpro@e615009c { 726 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; 727 reg = <0xe615009c 4>; 728 clocks = <&cpg_clocks R8A7740_CLK_PLLC0>; 729 #clock-cells = <0>; 730 }; 731 732 /* Fixed factor clocks */ 733 pllc1_div2_clk: pllc1_div2 { 734 compatible = "fixed-factor-clock"; 735 clocks = <&cpg_clocks R8A7740_CLK_PLLC1>; 736 #clock-cells = <0>; 737 clock-div = <2>; 738 clock-mult = <1>; 739 }; 740 extal1_div2_clk: extal1_div2 { 741 compatible = "fixed-factor-clock"; 742 clocks = <&extal1_clk>; 743 #clock-cells = <0>; 744 clock-div = <2>; 745 clock-mult = <1>; 746 }; 747 748 /* Gate clocks */ 749 subck_clks: subck_clks@e6150080 { 750 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; 751 reg = <0xe6150080 4>; 752 clocks = <&sub_clk>, <&sub_clk>; 753 #clock-cells = <1>; 754 clock-indices = < 755 R8A7740_CLK_SUBCK R8A7740_CLK_SUBCK2 756 >; 757 clock-output-names = 758 "subck", "subck2"; 759 }; 760 mstp1_clks: mstp1_clks@e6150134 { 761 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; 762 reg = <0xe6150134 4>, <0xe6150038 4>; 763 clocks = <&cpg_clocks R8A7740_CLK_S>, 764 <&cpg_clocks R8A7740_CLK_S>, <&sub_clk>, 765 <&cpg_clocks R8A7740_CLK_B>, 766 <&cpg_clocks R8A7740_CLK_HPP>, <&sub_clk>, 767 <&cpg_clocks R8A7740_CLK_B>; 768 #clock-cells = <1>; 769 clock-indices = < 770 R8A7740_CLK_CEU21 R8A7740_CLK_CEU20 R8A7740_CLK_TMU0 771 R8A7740_CLK_LCDC1 R8A7740_CLK_IIC0 R8A7740_CLK_TMU1 772 R8A7740_CLK_LCDC0 773 >; 774 clock-output-names = 775 "ceu21", "ceu20", "tmu0", "lcdc1", "iic0", 776 "tmu1", "lcdc0"; 777 }; 778 mstp2_clks: mstp2_clks@e6150138 { 779 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; 780 reg = <0xe6150138 4>, <0xe6150040 4>; 781 clocks = <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>, 782 <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>, 783 <&cpg_clocks R8A7740_CLK_HP>, 784 <&cpg_clocks R8A7740_CLK_HP>, 785 <&cpg_clocks R8A7740_CLK_HP>, 786 <&sub_clk>, <&sub_clk>, <&sub_clk>, 787 <&sub_clk>, <&sub_clk>, <&sub_clk>, 788 <&sub_clk>; 789 #clock-cells = <1>; 790 clock-indices = < 791 R8A7740_CLK_SCIFA6 R8A7740_CLK_INTCA 792 R8A7740_CLK_SCIFA7 793 R8A7740_CLK_DMAC1 R8A7740_CLK_DMAC2 794 R8A7740_CLK_DMAC3 R8A7740_CLK_USBDMAC 795 R8A7740_CLK_SCIFA5 R8A7740_CLK_SCIFB 796 R8A7740_CLK_SCIFA0 R8A7740_CLK_SCIFA1 797 R8A7740_CLK_SCIFA2 R8A7740_CLK_SCIFA3 798 R8A7740_CLK_SCIFA4 799 >; 800 clock-output-names = 801 "scifa6", "intca", 802 "scifa7", "dmac1", "dmac2", "dmac3", 803 "usbdmac", "scifa5", "scifb", "scifa0", "scifa1", 804 "scifa2", "scifa3", "scifa4"; 805 }; 806 mstp3_clks: mstp3_clks@e615013c { 807 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; 808 reg = <0xe615013c 4>, <0xe6150048 4>; 809 clocks = <&cpg_clocks R8A7740_CLK_R>, 810 <&cpg_clocks R8A7740_CLK_HP>, 811 <&sub_clk>, 812 <&cpg_clocks R8A7740_CLK_HP>, 813 <&cpg_clocks R8A7740_CLK_HP>, 814 <&cpg_clocks R8A7740_CLK_HP>, 815 <&cpg_clocks R8A7740_CLK_HP>, 816 <&cpg_clocks R8A7740_CLK_HP>, 817 <&cpg_clocks R8A7740_CLK_HP>; 818 #clock-cells = <1>; 819 clock-indices = < 820 R8A7740_CLK_CMT1 R8A7740_CLK_FSI R8A7740_CLK_IIC1 821 R8A7740_CLK_USBF R8A7740_CLK_SDHI0 R8A7740_CLK_SDHI1 822 R8A7740_CLK_MMC R8A7740_CLK_GETHER R8A7740_CLK_TPU0 823 >; 824 clock-output-names = 825 "cmt1", "fsi", "iic1", "usbf", "sdhi0", "sdhi1", 826 "mmc", "gether", "tpu0"; 827 }; 828 mstp4_clks: mstp4_clks@e6150140 { 829 compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; 830 reg = <0xe6150140 4>, <0xe615004c 4>; 831 clocks = <&cpg_clocks R8A7740_CLK_HP>, 832 <&cpg_clocks R8A7740_CLK_HP>, 833 <&cpg_clocks R8A7740_CLK_HP>, 834 <&cpg_clocks R8A7740_CLK_HP>; 835 #clock-cells = <1>; 836 clock-indices = < 837 R8A7740_CLK_USBH R8A7740_CLK_SDHI2 838 R8A7740_CLK_USBFUNC R8A7740_CLK_USBPHY 839 >; 840 clock-output-names = 841 "usbhost", "sdhi2", "usbfunc", "usphy"; 842 }; 843 }; 844 845 sysc: system-controller@e6180000 { 846 compatible = "renesas,sysc-r8a7740", "renesas,sysc-rmobile"; 847 reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>; 848 849 pm-domains { 850 pd_c5: c5 { 851 #address-cells = <1>; 852 #size-cells = <0>; 853 #power-domain-cells = <0>; 854 855 pd_a4lc: a4lc@1 { 856 reg = <1>; 857 #power-domain-cells = <0>; 858 }; 859 860 pd_a4mp: a4mp@2 { 861 reg = <2>; 862 #power-domain-cells = <0>; 863 }; 864 865 pd_d4: d4@3 { 866 reg = <3>; 867 #power-domain-cells = <0>; 868 }; 869 870 pd_a4r: a4r@5 { 871 reg = <5>; 872 #address-cells = <1>; 873 #size-cells = <0>; 874 #power-domain-cells = <0>; 875 876 pd_a3rv: a3rv@6 { 877 reg = <6>; 878 #power-domain-cells = <0>; 879 }; 880 }; 881 882 pd_a4s: a4s@10 { 883 reg = <10>; 884 #address-cells = <1>; 885 #size-cells = <0>; 886 #power-domain-cells = <0>; 887 888 pd_a3sp: a3sp@11 { 889 reg = <11>; 890 #power-domain-cells = <0>; 891 }; 892 893 pd_a3sm: a3sm@12 { 894 reg = <12>; 895 #power-domain-cells = <0>; 896 }; 897 898 pd_a3sg: a3sg@13 { 899 reg = <13>; 900 #power-domain-cells = <0>; 901 }; 902 }; 903 904 pd_a4su: a4su@20 { 905 reg = <20>; 906 #power-domain-cells = <0>; 907 }; 908 }; 909 }; 910 }; 911}; 912