1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/V2H(P) SoC 4 * 5 * Copyright (C) 2024 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/renesas,r9a09g057-cpg.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/ { 12 compatible = "renesas,r9a09g057"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 interrupt-parent = <&gic>; 16 17 audio_extal_clk: audio-clk { 18 compatible = "fixed-clock"; 19 #clock-cells = <0>; 20 /* This value must be overridden by the board */ 21 clock-frequency = <0>; 22 }; 23 24 /* 25 * The default cluster table is based on the assumption that the PLLCA55 clock 26 * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to 27 * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be 28 * clocked to 1.8GHz as well). The table below should be overridden in the board 29 * DTS based on the PLLCA55 clock frequency. 30 */ 31 cluster0_opp: opp-table-0 { 32 compatible = "operating-points-v2"; 33 34 opp-1700000000 { 35 opp-hz = /bits/ 64 <1700000000>; 36 opp-microvolt = <900000>; 37 clock-latency-ns = <300000>; 38 }; 39 opp-850000000 { 40 opp-hz = /bits/ 64 <850000000>; 41 opp-microvolt = <800000>; 42 clock-latency-ns = <300000>; 43 }; 44 opp-425000000 { 45 opp-hz = /bits/ 64 <425000000>; 46 opp-microvolt = <800000>; 47 clock-latency-ns = <300000>; 48 }; 49 opp-212500000 { 50 opp-hz = /bits/ 64 <212500000>; 51 opp-microvolt = <800000>; 52 clock-latency-ns = <300000>; 53 opp-suspend; 54 }; 55 }; 56 57 cpus { 58 #address-cells = <1>; 59 #size-cells = <0>; 60 61 cpu0: cpu@0 { 62 compatible = "arm,cortex-a55"; 63 reg = <0>; 64 device_type = "cpu"; 65 next-level-cache = <&L3_CA55>; 66 enable-method = "psci"; 67 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK0>; 68 #cooling-cells = <2>; 69 operating-points-v2 = <&cluster0_opp>; 70 }; 71 72 cpu1: cpu@100 { 73 compatible = "arm,cortex-a55"; 74 reg = <0x100>; 75 device_type = "cpu"; 76 next-level-cache = <&L3_CA55>; 77 enable-method = "psci"; 78 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK1>; 79 #cooling-cells = <2>; 80 operating-points-v2 = <&cluster0_opp>; 81 }; 82 83 cpu2: cpu@200 { 84 compatible = "arm,cortex-a55"; 85 reg = <0x200>; 86 device_type = "cpu"; 87 next-level-cache = <&L3_CA55>; 88 enable-method = "psci"; 89 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK2>; 90 #cooling-cells = <2>; 91 operating-points-v2 = <&cluster0_opp>; 92 }; 93 94 cpu3: cpu@300 { 95 compatible = "arm,cortex-a55"; 96 reg = <0x300>; 97 device_type = "cpu"; 98 next-level-cache = <&L3_CA55>; 99 enable-method = "psci"; 100 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK3>; 101 #cooling-cells = <2>; 102 operating-points-v2 = <&cluster0_opp>; 103 }; 104 105 L3_CA55: cache-controller-0 { 106 compatible = "cache"; 107 cache-unified; 108 cache-size = <0x100000>; 109 cache-level = <3>; 110 }; 111 }; 112 113 gpu_opp_table: opp-table-1 { 114 compatible = "operating-points-v2"; 115 116 opp-630000000 { 117 opp-hz = /bits/ 64 <630000000>; 118 opp-microvolt = <800000>; 119 }; 120 121 opp-315000000 { 122 opp-hz = /bits/ 64 <315000000>; 123 opp-microvolt = <800000>; 124 }; 125 126 opp-157500000 { 127 opp-hz = /bits/ 64 <157500000>; 128 opp-microvolt = <800000>; 129 }; 130 131 opp-78750000 { 132 opp-hz = /bits/ 64 <78750000>; 133 opp-microvolt = <800000>; 134 }; 135 136 opp-19687500 { 137 opp-hz = /bits/ 64 <19687500>; 138 opp-microvolt = <800000>; 139 }; 140 }; 141 142 pmu { 143 compatible = "arm,cortex-a55-pmu"; 144 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 145 }; 146 147 psci { 148 compatible = "arm,psci-1.0", "arm,psci-0.2"; 149 method = "smc"; 150 }; 151 152 qextal_clk: qextal-clk { 153 compatible = "fixed-clock"; 154 #clock-cells = <0>; 155 /* This value must be overridden by the board */ 156 clock-frequency = <0>; 157 }; 158 159 rtxin_clk: rtxin-clk { 160 compatible = "fixed-clock"; 161 #clock-cells = <0>; 162 /* This value must be overridden by the board */ 163 clock-frequency = <0>; 164 }; 165 166 soc: soc { 167 compatible = "simple-bus"; 168 #address-cells = <2>; 169 #size-cells = <2>; 170 ranges; 171 172 icu: interrupt-controller@10400000 { 173 compatible = "renesas,r9a09g057-icu"; 174 reg = <0 0x10400000 0 0x10000>; 175 #interrupt-cells = <2>; 176 #address-cells = <0>; 177 interrupt-controller; 178 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 208 <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 221 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>, 222 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 227 <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>, 228 <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>, 229 <GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 230 <GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, 231 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 232 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 233 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 234 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 235 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>; 236 interrupt-names = "nmi", 237 "port_irq0", "port_irq1", "port_irq2", 238 "port_irq3", "port_irq4", "port_irq5", 239 "port_irq6", "port_irq7", "port_irq8", 240 "port_irq9", "port_irq10", "port_irq11", 241 "port_irq12", "port_irq13", "port_irq14", 242 "port_irq15", 243 "tint0", "tint1", "tint2", "tint3", 244 "tint4", "tint5", "tint6", "tint7", 245 "tint8", "tint9", "tint10", "tint11", 246 "tint12", "tint13", "tint14", "tint15", 247 "tint16", "tint17", "tint18", "tint19", 248 "tint20", "tint21", "tint22", "tint23", 249 "tint24", "tint25", "tint26", "tint27", 250 "tint28", "tint29", "tint30", "tint31", 251 "int-ca55-0", "int-ca55-1", 252 "int-ca55-2", "int-ca55-3", 253 "icu-error-ca55", 254 "gpt-u0-gtciada", "gpt-u0-gtciadb", 255 "gpt-u1-gtciada", "gpt-u1-gtciadb"; 256 clocks = <&cpg CPG_MOD 0x5>; 257 power-domains = <&cpg>; 258 resets = <&cpg 0x36>; 259 }; 260 261 pinctrl: pinctrl@10410000 { 262 compatible = "renesas,r9a09g057-pinctrl"; 263 reg = <0 0x10410000 0 0x10000>; 264 clocks = <&cpg CPG_CORE R9A09G057_IOTOP_0_SHCLK>; 265 gpio-controller; 266 #gpio-cells = <2>; 267 gpio-ranges = <&pinctrl 0 0 96>; 268 #interrupt-cells = <2>; 269 interrupt-controller; 270 interrupt-parent = <&icu>; 271 power-domains = <&cpg>; 272 resets = <&cpg 0xa5>, <&cpg 0xa6>; 273 }; 274 275 cpg: clock-controller@10420000 { 276 compatible = "renesas,r9a09g057-cpg"; 277 reg = <0 0x10420000 0 0x10000>; 278 clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; 279 clock-names = "audio_extal", "rtxin", "qextal"; 280 #clock-cells = <2>; 281 #reset-cells = <1>; 282 #power-domain-cells = <0>; 283 }; 284 285 sys: system-controller@10430000 { 286 compatible = "renesas,r9a09g057-sys"; 287 reg = <0 0x10430000 0 0x10000>; 288 clocks = <&cpg CPG_CORE R9A09G057_SYS_0_PCLK>; 289 resets = <&cpg 0x30>; 290 }; 291 292 tsu0: thermal@11000000 { 293 compatible = "renesas,r9a09g057-tsu", "renesas,r9a09g047-tsu"; 294 reg = <0 0x11000000 0 0x1000>; 295 interrupts = <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>, 296 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 297 interrupt-names = "adi", "adcmpi"; 298 clocks = <&cpg CPG_MOD 0x109>; 299 resets = <&cpg 0xf7>; 300 power-domains = <&cpg>; 301 #thermal-sensor-cells = <0>; 302 renesas,tsu-trim = <&sys 0x320>; 303 }; 304 305 tsu1: thermal@14002000 { 306 compatible = "renesas,r9a09g057-tsu", "renesas,r9a09g047-tsu"; 307 reg = <0 0x14002000 0 0x1000>; 308 interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>, 309 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>; 310 interrupt-names = "adi", "adcmpi"; 311 clocks = <&cpg CPG_MOD 0x10a>; 312 resets = <&cpg 0xf8>; 313 power-domains = <&cpg>; 314 #thermal-sensor-cells = <0>; 315 renesas,tsu-trim = <&sys 0x330>; 316 }; 317 318 xspi: spi@11030000 { 319 compatible = "renesas,r9a09g057-xspi", "renesas,r9a09g047-xspi"; 320 reg = <0 0x11030000 0 0x10000>, 321 <0 0x20000000 0 0x10000000>; 322 reg-names = "regs", "dirmap"; 323 interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>, 324 <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>; 325 interrupt-names = "pulse", "err_pulse"; 326 clocks = <&cpg CPG_MOD 0x9f>, 327 <&cpg CPG_MOD 0xa0>, 328 <&cpg CPG_CORE R9A09G057_SPI_CLK_SPI>, 329 <&cpg CPG_MOD 0xa1>; 330 clock-names = "ahb", "axi", "spi", "spix2"; 331 resets = <&cpg 0xa3>, <&cpg 0xa4>; 332 reset-names = "hresetn", "aresetn"; 333 power-domains = <&cpg>; 334 #address-cells = <1>; 335 #size-cells = <0>; 336 status = "disabled"; 337 }; 338 339 dmac0: dma-controller@11400000 { 340 compatible = "renesas,r9a09g057-dmac"; 341 reg = <0 0x11400000 0 0x10000>; 342 interrupts = <GIC_SPI 499 IRQ_TYPE_EDGE_RISING>, 343 <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>, 344 <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>, 345 <GIC_SPI 91 IRQ_TYPE_EDGE_RISING>, 346 <GIC_SPI 92 IRQ_TYPE_EDGE_RISING>, 347 <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>, 348 <GIC_SPI 94 IRQ_TYPE_EDGE_RISING>, 349 <GIC_SPI 95 IRQ_TYPE_EDGE_RISING>, 350 <GIC_SPI 96 IRQ_TYPE_EDGE_RISING>, 351 <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>, 352 <GIC_SPI 98 IRQ_TYPE_EDGE_RISING>, 353 <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>, 354 <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>, 355 <GIC_SPI 101 IRQ_TYPE_EDGE_RISING>, 356 <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>, 357 <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>, 358 <GIC_SPI 104 IRQ_TYPE_EDGE_RISING>; 359 interrupt-names = "error", 360 "ch0", "ch1", "ch2", "ch3", 361 "ch4", "ch5", "ch6", "ch7", 362 "ch8", "ch9", "ch10", "ch11", 363 "ch12", "ch13", "ch14", "ch15"; 364 clocks = <&cpg CPG_MOD 0x0>; 365 power-domains = <&cpg>; 366 resets = <&cpg 0x31>; 367 #dma-cells = <1>; 368 dma-channels = <16>; 369 renesas,icu = <&icu 4>; 370 }; 371 372 dmac1: dma-controller@14830000 { 373 compatible = "renesas,r9a09g057-dmac"; 374 reg = <0 0x14830000 0 0x10000>; 375 interrupts = <GIC_SPI 495 IRQ_TYPE_EDGE_RISING>, 376 <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>, 377 <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>, 378 <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>, 379 <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>, 380 <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>, 381 <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>, 382 <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>, 383 <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>, 384 <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>, 385 <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>, 386 <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>, 387 <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>, 388 <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>, 389 <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>, 390 <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>, 391 <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>; 392 interrupt-names = "error", 393 "ch0", "ch1", "ch2", "ch3", 394 "ch4", "ch5", "ch6", "ch7", 395 "ch8", "ch9", "ch10", "ch11", 396 "ch12", "ch13", "ch14", "ch15"; 397 clocks = <&cpg CPG_MOD 0x1>; 398 power-domains = <&cpg>; 399 resets = <&cpg 0x32>; 400 #dma-cells = <1>; 401 dma-channels = <16>; 402 renesas,icu = <&icu 0>; 403 }; 404 405 dmac2: dma-controller@14840000 { 406 compatible = "renesas,r9a09g057-dmac"; 407 reg = <0 0x14840000 0 0x10000>; 408 interrupts = <GIC_SPI 496 IRQ_TYPE_EDGE_RISING>, 409 <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>, 410 <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>, 411 <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>, 412 <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>, 413 <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>, 414 <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>, 415 <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>, 416 <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>, 417 <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>, 418 <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>, 419 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>, 420 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, 421 <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>, 422 <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>, 423 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>, 424 <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>; 425 interrupt-names = "error", 426 "ch0", "ch1", "ch2", "ch3", 427 "ch4", "ch5", "ch6", "ch7", 428 "ch8", "ch9", "ch10", "ch11", 429 "ch12", "ch13", "ch14", "ch15"; 430 clocks = <&cpg CPG_MOD 0x2>; 431 power-domains = <&cpg>; 432 resets = <&cpg 0x33>; 433 #dma-cells = <1>; 434 dma-channels = <16>; 435 renesas,icu = <&icu 1>; 436 }; 437 438 dmac3: dma-controller@12000000 { 439 compatible = "renesas,r9a09g057-dmac"; 440 reg = <0 0x12000000 0 0x10000>; 441 interrupts = <GIC_SPI 497 IRQ_TYPE_EDGE_RISING>, 442 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>, 443 <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>, 444 <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>, 445 <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>, 446 <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>, 447 <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>, 448 <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>, 449 <GIC_SPI 64 IRQ_TYPE_EDGE_RISING>, 450 <GIC_SPI 65 IRQ_TYPE_EDGE_RISING>, 451 <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>, 452 <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>, 453 <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>, 454 <GIC_SPI 69 IRQ_TYPE_EDGE_RISING>, 455 <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>, 456 <GIC_SPI 71 IRQ_TYPE_EDGE_RISING>, 457 <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>; 458 interrupt-names = "error", 459 "ch0", "ch1", "ch2", "ch3", 460 "ch4", "ch5", "ch6", "ch7", 461 "ch8", "ch9", "ch10", "ch11", 462 "ch12", "ch13", "ch14", "ch15"; 463 clocks = <&cpg CPG_MOD 0x3>; 464 power-domains = <&cpg>; 465 resets = <&cpg 0x34>; 466 #dma-cells = <1>; 467 dma-channels = <16>; 468 renesas,icu = <&icu 2>; 469 }; 470 471 dmac4: dma-controller@12010000 { 472 compatible = "renesas,r9a09g057-dmac"; 473 reg = <0 0x12010000 0 0x10000>; 474 interrupts = <GIC_SPI 498 IRQ_TYPE_EDGE_RISING>, 475 <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>, 476 <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>, 477 <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>, 478 <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>, 479 <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>, 480 <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 481 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 482 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, 483 <GIC_SPI 81 IRQ_TYPE_EDGE_RISING>, 484 <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>, 485 <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>, 486 <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>, 487 <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>, 488 <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>, 489 <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>, 490 <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>; 491 interrupt-names = "error", 492 "ch0", "ch1", "ch2", "ch3", 493 "ch4", "ch5", "ch6", "ch7", 494 "ch8", "ch9", "ch10", "ch11", 495 "ch12", "ch13", "ch14", "ch15"; 496 clocks = <&cpg CPG_MOD 0x4>; 497 power-domains = <&cpg>; 498 resets = <&cpg 0x35>; 499 #dma-cells = <1>; 500 dma-channels = <16>; 501 renesas,icu = <&icu 3>; 502 }; 503 504 ostm0: timer@11800000 { 505 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 506 reg = <0x0 0x11800000 0x0 0x1000>; 507 interrupts = <GIC_SPI 17 IRQ_TYPE_EDGE_RISING>; 508 clocks = <&cpg CPG_MOD 0x43>; 509 resets = <&cpg 0x6d>; 510 power-domains = <&cpg>; 511 status = "disabled"; 512 }; 513 514 ostm1: timer@11801000 { 515 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 516 reg = <0x0 0x11801000 0x0 0x1000>; 517 interrupts = <GIC_SPI 18 IRQ_TYPE_EDGE_RISING>; 518 clocks = <&cpg CPG_MOD 0x44>; 519 resets = <&cpg 0x6e>; 520 power-domains = <&cpg>; 521 status = "disabled"; 522 }; 523 524 ostm2: timer@14000000 { 525 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 526 reg = <0x0 0x14000000 0x0 0x1000>; 527 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>; 528 clocks = <&cpg CPG_MOD 0x45>; 529 resets = <&cpg 0x6f>; 530 power-domains = <&cpg>; 531 status = "disabled"; 532 }; 533 534 ostm3: timer@14001000 { 535 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 536 reg = <0x0 0x14001000 0x0 0x1000>; 537 interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>; 538 clocks = <&cpg CPG_MOD 0x46>; 539 resets = <&cpg 0x70>; 540 power-domains = <&cpg>; 541 status = "disabled"; 542 }; 543 544 ostm4: timer@12c00000 { 545 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 546 reg = <0x0 0x12c00000 0x0 0x1000>; 547 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 548 clocks = <&cpg CPG_MOD 0x47>; 549 resets = <&cpg 0x71>; 550 power-domains = <&cpg>; 551 status = "disabled"; 552 }; 553 554 ostm5: timer@12c01000 { 555 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 556 reg = <0x0 0x12c01000 0x0 0x1000>; 557 interrupts = <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 558 clocks = <&cpg CPG_MOD 0x48>; 559 resets = <&cpg 0x72>; 560 power-domains = <&cpg>; 561 status = "disabled"; 562 }; 563 564 ostm6: timer@12c02000 { 565 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 566 reg = <0x0 0x12c02000 0x0 0x1000>; 567 interrupts = <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>; 568 clocks = <&cpg CPG_MOD 0x49>; 569 resets = <&cpg 0x73>; 570 power-domains = <&cpg>; 571 status = "disabled"; 572 }; 573 574 ostm7: timer@12c03000 { 575 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 576 reg = <0x0 0x12c03000 0x0 0x1000>; 577 interrupts = <GIC_SPI 24 IRQ_TYPE_EDGE_RISING>; 578 clocks = <&cpg CPG_MOD 0x4a>; 579 resets = <&cpg 0x74>; 580 power-domains = <&cpg>; 581 status = "disabled"; 582 }; 583 584 wdt1: watchdog@14400000 { 585 compatible = "renesas,r9a09g057-wdt"; 586 reg = <0 0x14400000 0 0x400>; 587 clocks = <&cpg CPG_MOD 0x4d>, <&cpg CPG_MOD 0x4e>; 588 clock-names = "pclk", "oscclk"; 589 resets = <&cpg 0x76>; 590 power-domains = <&cpg>; 591 status = "disabled"; 592 }; 593 594 rtc: rtc@11c00800 { 595 compatible = "renesas,r9a09g057-rtca3", "renesas,rz-rtca3"; 596 reg = <0 0x11c00800 0 0x400>; 597 interrupts = <GIC_SPI 524 IRQ_TYPE_EDGE_RISING>, 598 <GIC_SPI 525 IRQ_TYPE_EDGE_RISING>, 599 <GIC_SPI 526 IRQ_TYPE_EDGE_RISING>; 600 interrupt-names = "alarm", "period", "carry"; 601 clocks = <&cpg CPG_MOD 0x53>, <&rtxin_clk>; 602 clock-names = "bus", "counter"; 603 power-domains = <&cpg>; 604 resets = <&cpg 0x79>, <&cpg 0x7a>; 605 reset-names = "rtc", "rtest"; 606 status = "disabled"; 607 }; 608 609 scif: serial@11c01400 { 610 compatible = "renesas,scif-r9a09g057"; 611 reg = <0 0x11c01400 0 0x400>; 612 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>, 619 <GIC_SPI 536 IRQ_TYPE_EDGE_RISING>, 620 <GIC_SPI 537 IRQ_TYPE_EDGE_RISING>; 621 interrupt-names = "eri", "rxi", "txi", "bri", "dri", 622 "tei", "tei-dri", "rxi-edge", "txi-edge"; 623 clocks = <&cpg CPG_MOD 0x8f>; 624 clock-names = "fck"; 625 power-domains = <&cpg>; 626 resets = <&cpg 0x95>; 627 status = "disabled"; 628 }; 629 630 i3c: i3c@12400000 { 631 compatible = "renesas,r9a09g057-i3c", "renesas,r9a09g047-i3c"; 632 reg = <0 0x12400000 0 0x10000>; 633 clocks = <&cpg CPG_MOD 0x91>, <&cpg CPG_MOD 0x92>, <&cpg CPG_MOD 0x90>; 634 clock-names = "pclk", "tclk", "pclkrw"; 635 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 636 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 637 <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH>, 638 <GIC_SPI 677 IRQ_TYPE_EDGE_RISING>, 639 <GIC_SPI 678 IRQ_TYPE_EDGE_RISING>, 640 <GIC_SPI 679 IRQ_TYPE_EDGE_RISING>, 641 <GIC_SPI 680 IRQ_TYPE_EDGE_RISING>, 642 <GIC_SPI 681 IRQ_TYPE_EDGE_RISING>, 643 <GIC_SPI 682 IRQ_TYPE_EDGE_RISING>, 644 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 645 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 646 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 647 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 648 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 649 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 650 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>; 651 interrupt-names = "ierr", "terr", "abort", "resp", 652 "cmd", "ibi", "rx", "tx", "rcv", 653 "st", "sp", "tend", "nack", 654 "al", "tmo", "wu"; 655 resets = <&cpg 0x96>, <&cpg 0x97>; 656 reset-names = "presetn", "tresetn"; 657 power-domains = <&cpg>; 658 #address-cells = <3>; 659 #size-cells = <0>; 660 status = "disabled"; 661 }; 662 663 canfd: can@12440000 { 664 compatible = "renesas,r9a09g057-canfd", "renesas,r9a09g047-canfd"; 665 reg = <0 0x12440000 0 0x40000>; 666 interrupts = <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 667 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 668 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 669 <GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH>, 670 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 671 <GIC_SPI 698 IRQ_TYPE_LEVEL_HIGH>, 672 <GIC_SPI 704 IRQ_TYPE_LEVEL_HIGH>, 673 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 674 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>, 675 <GIC_SPI 705 IRQ_TYPE_LEVEL_HIGH>, 676 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 677 <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>, 678 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 679 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 680 <GIC_SPI 701 IRQ_TYPE_LEVEL_HIGH>, 681 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 682 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 683 <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH>, 684 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 685 <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH>; 686 interrupt-names = "g_err", "g_recc", 687 "ch0_err", "ch0_rec", "ch0_trx", 688 "ch1_err", "ch1_rec", "ch1_trx", 689 "ch2_err", "ch2_rec", "ch2_trx", 690 "ch3_err", "ch3_rec", "ch3_trx", 691 "ch4_err", "ch4_rec", "ch4_trx", 692 "ch5_err", "ch5_rec", "ch5_trx"; 693 clocks = <&cpg CPG_MOD 0x9c>, <&cpg CPG_MOD 0x9d>, 694 <&cpg CPG_MOD 0x9e>; 695 clock-names = "fck", "ram_clk", "can_clk"; 696 assigned-clocks = <&cpg CPG_MOD 0x9e>; 697 assigned-clock-rates = <80000000>; 698 resets = <&cpg 0xa1>, <&cpg 0xa2>; 699 reset-names = "rstp_n", "rstc_n"; 700 power-domains = <&cpg>; 701 status = "disabled"; 702 703 channel0 { 704 status = "disabled"; 705 }; 706 channel1 { 707 status = "disabled"; 708 }; 709 channel2 { 710 status = "disabled"; 711 }; 712 channel3 { 713 status = "disabled"; 714 }; 715 channel4 { 716 status = "disabled"; 717 }; 718 channel5 { 719 status = "disabled"; 720 }; 721 }; 722 723 rspi0: spi@12800000 { 724 compatible = "renesas,r9a09g057-rspi"; 725 reg = <0x0 0x12800000 0x0 0x400>; 726 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 727 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 728 <GIC_SPI 107 IRQ_TYPE_EDGE_RISING>, 729 <GIC_SPI 500 IRQ_TYPE_EDGE_RISING>, 730 <GIC_SPI 501 IRQ_TYPE_EDGE_RISING>; 731 interrupt-names = "idle", "error", "end", "rx", "tx"; 732 clocks = <&cpg CPG_MOD 0x54>, 733 <&cpg CPG_MOD 0x55>, 734 <&cpg CPG_MOD 0x56>; 735 clock-names = "pclk", "pclk_sfr", "tclk"; 736 resets = <&cpg 0x7b>, <&cpg 0x7c>; 737 reset-names = "presetn", "tresetn"; 738 dmas = <&dmac0 0x448c>, <&dmac0 0x448d>, 739 <&dmac1 0x448c>, <&dmac1 0x448d>, 740 <&dmac2 0x448c>, <&dmac2 0x448d>, 741 <&dmac3 0x448c>, <&dmac3 0x448d>, 742 <&dmac4 0x448c>, <&dmac4 0x448d>; 743 dma-names = "rx", "tx", "rx", "tx", "rx", 744 "tx", "rx", "tx", "rx", "tx"; 745 power-domains = <&cpg>; 746 #address-cells = <1>; 747 #size-cells = <0>; 748 status = "disabled"; 749 }; 750 751 rspi1: spi@12800400 { 752 compatible = "renesas,r9a09g057-rspi"; 753 reg = <0x0 0x12800400 0x0 0x400>; 754 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 755 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 756 <GIC_SPI 110 IRQ_TYPE_EDGE_RISING>, 757 <GIC_SPI 502 IRQ_TYPE_EDGE_RISING>, 758 <GIC_SPI 503 IRQ_TYPE_EDGE_RISING>; 759 interrupt-names = "idle", "error", "end", "rx", "tx"; 760 clocks = <&cpg CPG_MOD 0x57>, 761 <&cpg CPG_MOD 0x58>, 762 <&cpg CPG_MOD 0x59>; 763 clock-names = "pclk", "pclk_sfr", "tclk"; 764 resets = <&cpg 0x7d>, <&cpg 0x7e>; 765 reset-names = "presetn", "tresetn"; 766 dmas = <&dmac0 0x448e>, <&dmac0 0x448f>, 767 <&dmac1 0x448e>, <&dmac1 0x448f>, 768 <&dmac2 0x448e>, <&dmac2 0x448f>, 769 <&dmac3 0x448e>, <&dmac3 0x448f>, 770 <&dmac4 0x448e>, <&dmac4 0x448f>; 771 dma-names = "rx", "tx", "rx", "tx", "rx", 772 "tx", "rx", "tx", "rx", "tx"; 773 power-domains = <&cpg>; 774 #address-cells = <1>; 775 #size-cells = <0>; 776 status = "disabled"; 777 }; 778 779 rspi2: spi@12800800 { 780 compatible = "renesas,r9a09g057-rspi"; 781 reg = <0x0 0x12800800 0x0 0x400>; 782 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 783 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 784 <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>, 785 <GIC_SPI 504 IRQ_TYPE_EDGE_RISING>, 786 <GIC_SPI 505 IRQ_TYPE_EDGE_RISING>; 787 interrupt-names = "idle", "error", "end", "rx", "tx"; 788 clocks = <&cpg CPG_MOD 0x5a>, 789 <&cpg CPG_MOD 0x5b>, 790 <&cpg CPG_MOD 0x5c>; 791 clock-names = "pclk", "pclk_sfr", "tclk"; 792 resets = <&cpg 0x7f>, <&cpg 0x80>; 793 reset-names = "presetn", "tresetn"; 794 dmas = <&dmac0 0x4490>, <&dmac0 0x4491>, 795 <&dmac1 0x4490>, <&dmac1 0x4491>, 796 <&dmac2 0x4490>, <&dmac2 0x4491>, 797 <&dmac3 0x4490>, <&dmac3 0x4491>, 798 <&dmac4 0x4490>, <&dmac4 0x4491>; 799 dma-names = "rx", "tx", "rx", "tx", "rx", 800 "tx", "rx", "tx", "rx", "tx"; 801 power-domains = <&cpg>; 802 #address-cells = <1>; 803 #size-cells = <0>; 804 status = "disabled"; 805 }; 806 807 rsci0: serial@12800c00 { 808 compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci"; 809 reg = <0 0x12800c00 0 0x400>; 810 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 811 <GIC_SPI 115 IRQ_TYPE_EDGE_RISING>, 812 <GIC_SPI 116 IRQ_TYPE_EDGE_RISING>, 813 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 814 <GIC_SPI 118 IRQ_TYPE_EDGE_RISING>, 815 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 816 interrupt-names = "eri", "rxi", "txi", "tei", 817 "aed", "bfd"; 818 clocks = <&cpg CPG_MOD 0x5d>, <&cpg CPG_MOD 0x5e>, 819 <&cpg CPG_MOD 0x61>, <&cpg CPG_MOD 0x60>, 820 <&cpg CPG_MOD 0x5f>; 821 clock-names = "pclk", "tclk", "tclk_div4", 822 "tclk_div16", "tclk_div64"; 823 power-domains = <&cpg>; 824 resets = <&cpg 0x81>, <&cpg 0x82>; 825 reset-names = "presetn", "tresetn"; 826 status = "disabled"; 827 }; 828 829 rsci1: serial@12801000 { 830 compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci"; 831 reg = <0 0x12801000 0 0x400>; 832 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 833 <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>, 834 <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>, 835 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 836 <GIC_SPI 124 IRQ_TYPE_EDGE_RISING>, 837 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 838 interrupt-names = "eri", "rxi", "txi", "tei", 839 "aed", "bfd"; 840 clocks = <&cpg CPG_MOD 0x62>, <&cpg CPG_MOD 0x63>, 841 <&cpg CPG_MOD 0x66>, <&cpg CPG_MOD 0x65>, 842 <&cpg CPG_MOD 0x64>; 843 clock-names = "pclk", "tclk", "tclk_div4", 844 "tclk_div16", "tclk_div64"; 845 power-domains = <&cpg>; 846 resets = <&cpg 0x83>, <&cpg 0x84>; 847 reset-names = "presetn", "tresetn"; 848 status = "disabled"; 849 }; 850 851 rsci2: serial@12801400 { 852 compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci"; 853 reg = <0 0x12801400 0 0x400>; 854 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 855 <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>, 856 <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>, 857 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 858 <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>, 859 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 860 interrupt-names = "eri", "rxi", "txi", "tei", 861 "aed", "bfd"; 862 clocks = <&cpg CPG_MOD 0x67>, <&cpg CPG_MOD 0x68>, 863 <&cpg CPG_MOD 0x6b>, <&cpg CPG_MOD 0x6a>, 864 <&cpg CPG_MOD 0x69>; 865 clock-names = "pclk", "tclk", "tclk_div4", 866 "tclk_div16", "tclk_div64"; 867 power-domains = <&cpg>; 868 resets = <&cpg 0x85>, <&cpg 0x86>; 869 reset-names = "presetn", "tresetn"; 870 status = "disabled"; 871 }; 872 873 rsci3: serial@12801800 { 874 compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci"; 875 reg = <0 0x12801800 0 0x400>; 876 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 877 <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>, 878 <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>, 879 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 880 <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, 881 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 882 interrupt-names = "eri", "rxi", "txi", "tei", 883 "aed", "bfd"; 884 clocks = <&cpg CPG_MOD 0x6c>, <&cpg CPG_MOD 0x6d>, 885 <&cpg CPG_MOD 0x70>, <&cpg CPG_MOD 0x6f>, 886 <&cpg CPG_MOD 0x6e>; 887 clock-names = "pclk", "tclk", "tclk_div4", 888 "tclk_div16", "tclk_div64"; 889 power-domains = <&cpg>; 890 resets = <&cpg 0x87>, <&cpg 0x88>; 891 reset-names = "presetn", "tresetn"; 892 status = "disabled"; 893 }; 894 895 rsci4: serial@12801c00 { 896 compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci"; 897 reg = <0 0x12801c00 0 0x400>; 898 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 899 <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>, 900 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>, 901 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 902 <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>, 903 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 904 interrupt-names = "eri", "rxi", "txi", "tei", 905 "aed", "bfd"; 906 clocks = <&cpg CPG_MOD 0x71>, <&cpg CPG_MOD 0x72>, 907 <&cpg CPG_MOD 0x75>, <&cpg CPG_MOD 0x74>, 908 <&cpg CPG_MOD 0x73>; 909 clock-names = "pclk", "tclk", "tclk_div4", 910 "tclk_div16", "tclk_div64"; 911 power-domains = <&cpg>; 912 resets = <&cpg 0x89>, <&cpg 0x8a>; 913 reset-names = "presetn", "tresetn"; 914 status = "disabled"; 915 }; 916 917 rsci5: serial@12802000 { 918 compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci"; 919 reg = <0 0x12802000 0 0x400>; 920 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 921 <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>, 922 <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>, 923 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 924 <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>, 925 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 926 interrupt-names = "eri", "rxi", "txi", "tei", 927 "aed", "bfd"; 928 clocks = <&cpg CPG_MOD 0x76>, <&cpg CPG_MOD 0x77>, 929 <&cpg CPG_MOD 0x7a>, <&cpg CPG_MOD 0x79>, 930 <&cpg CPG_MOD 0x78>; 931 clock-names = "pclk", "tclk", "tclk_div4", 932 "tclk_div16", "tclk_div64"; 933 power-domains = <&cpg>; 934 resets = <&cpg 0x8b>, <&cpg 0x8c>; 935 reset-names = "presetn", "tresetn"; 936 status = "disabled"; 937 }; 938 939 rsci6: serial@12802400 { 940 compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci"; 941 reg = <0 0x12802400 0 0x400>; 942 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>, 944 <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>, 945 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 154 IRQ_TYPE_EDGE_RISING>, 947 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 948 interrupt-names = "eri", "rxi", "txi", "tei", 949 "aed", "bfd"; 950 clocks = <&cpg CPG_MOD 0x7b>, <&cpg CPG_MOD 0x7c>, 951 <&cpg CPG_MOD 0x7f>, <&cpg CPG_MOD 0x7e>, 952 <&cpg CPG_MOD 0x7d>; 953 clock-names = "pclk", "tclk", "tclk_div4", 954 "tclk_div16", "tclk_div64"; 955 power-domains = <&cpg>; 956 resets = <&cpg 0x8d>, <&cpg 0x8e>; 957 reset-names = "presetn", "tresetn"; 958 status = "disabled"; 959 }; 960 961 rsci7: serial@12802800 { 962 compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci"; 963 reg = <0 0x12802800 0 0x400>; 964 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 965 <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>, 966 <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>, 967 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 968 <GIC_SPI 160 IRQ_TYPE_EDGE_RISING>, 969 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 970 interrupt-names = "eri", "rxi", "txi", "tei", 971 "aed", "bfd"; 972 clocks = <&cpg CPG_MOD 0x80>, <&cpg CPG_MOD 0x81>, 973 <&cpg CPG_MOD 0x84>, <&cpg CPG_MOD 0x83>, 974 <&cpg CPG_MOD 0x82>; 975 clock-names = "pclk", "tclk", "tclk_div4", 976 "tclk_div16", "tclk_div64"; 977 power-domains = <&cpg>; 978 resets = <&cpg 0x8f>, <&cpg 0x90>; 979 reset-names = "presetn", "tresetn"; 980 status = "disabled"; 981 }; 982 983 rsci8: serial@12802c00 { 984 compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci"; 985 reg = <0 0x12802c00 0 0x400>; 986 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 987 <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>, 988 <GIC_SPI 164 IRQ_TYPE_EDGE_RISING>, 989 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 990 <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>, 991 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 992 interrupt-names = "eri", "rxi", "txi", "tei", 993 "aed", "bfd"; 994 clocks = <&cpg CPG_MOD 0x85>, <&cpg CPG_MOD 0x86>, 995 <&cpg CPG_MOD 0x89>, <&cpg CPG_MOD 0x88>, 996 <&cpg CPG_MOD 0x87>; 997 clock-names = "pclk", "tclk", "tclk_div4", 998 "tclk_div16", "tclk_div64"; 999 power-domains = <&cpg>; 1000 resets = <&cpg 0x91>, <&cpg 0x92>; 1001 reset-names = "presetn", "tresetn"; 1002 status = "disabled"; 1003 }; 1004 1005 rsci9: serial@12803000 { 1006 compatible = "renesas,r9a09g057-rsci", "renesas,r9a09g047-rsci"; 1007 reg = <0 0x12803000 0 0x400>; 1008 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 1009 <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>, 1010 <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>, 1011 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 1012 <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>, 1013 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 1014 interrupt-names = "eri", "rxi", "txi", "tei", 1015 "aed", "bfd"; 1016 clocks = <&cpg CPG_MOD 0x8a>, <&cpg CPG_MOD 0x8b>, 1017 <&cpg CPG_MOD 0x8e>, <&cpg CPG_MOD 0x8d>, 1018 <&cpg CPG_MOD 0x8c>; 1019 clock-names = "pclk", "tclk", "tclk_div4", 1020 "tclk_div16", "tclk_div64"; 1021 power-domains = <&cpg>; 1022 resets = <&cpg 0x93>, <&cpg 0x94>; 1023 reset-names = "presetn", "tresetn"; 1024 status = "disabled"; 1025 }; 1026 1027 i2c0: i2c@14400400 { 1028 compatible = "renesas,riic-r9a09g057"; 1029 reg = <0 0x14400400 0 0x400>; 1030 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 1031 <GIC_SPI 507 IRQ_TYPE_EDGE_RISING>, 1032 <GIC_SPI 506 IRQ_TYPE_EDGE_RISING>, 1033 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1034 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 1035 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 1036 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 1037 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 1038 interrupt-names = "tei", "ri", "ti", "spi", "sti", 1039 "naki", "ali", "tmoi"; 1040 clocks = <&cpg CPG_MOD 0x94>; 1041 resets = <&cpg 0x98>; 1042 power-domains = <&cpg>; 1043 #address-cells = <1>; 1044 #size-cells = <0>; 1045 status = "disabled"; 1046 }; 1047 1048 i2c1: i2c@14400800 { 1049 compatible = "renesas,riic-r9a09g057"; 1050 reg = <0 0x14400800 0 0x400>; 1051 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 1052 <GIC_SPI 509 IRQ_TYPE_EDGE_RISING>, 1053 <GIC_SPI 508 IRQ_TYPE_EDGE_RISING>, 1054 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1055 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1056 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1057 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1058 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 1059 interrupt-names = "tei", "ri", "ti", "spi", "sti", 1060 "naki", "ali", "tmoi"; 1061 clocks = <&cpg CPG_MOD 0x95>; 1062 resets = <&cpg 0x99>; 1063 power-domains = <&cpg>; 1064 #address-cells = <1>; 1065 #size-cells = <0>; 1066 status = "disabled"; 1067 }; 1068 1069 i2c2: i2c@14400c00 { 1070 compatible = "renesas,riic-r9a09g057"; 1071 reg = <0 0x14400c00 0 0x400>; 1072 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1073 <GIC_SPI 511 IRQ_TYPE_EDGE_RISING>, 1074 <GIC_SPI 510 IRQ_TYPE_EDGE_RISING>, 1075 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1076 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1077 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1078 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1079 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 1080 interrupt-names = "tei", "ri", "ti", "spi", "sti", 1081 "naki", "ali", "tmoi"; 1082 clocks = <&cpg CPG_MOD 0x96>; 1083 resets = <&cpg 0x9a>; 1084 power-domains = <&cpg>; 1085 #address-cells = <1>; 1086 #size-cells = <0>; 1087 status = "disabled"; 1088 }; 1089 1090 i2c3: i2c@14401000 { 1091 compatible = "renesas,riic-r9a09g057"; 1092 reg = <0 0x14401000 0 0x400>; 1093 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1094 <GIC_SPI 513 IRQ_TYPE_EDGE_RISING>, 1095 <GIC_SPI 512 IRQ_TYPE_EDGE_RISING>, 1096 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 1097 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 1098 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 1099 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 1100 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1101 interrupt-names = "tei", "ri", "ti", "spi", "sti", 1102 "naki", "ali", "tmoi"; 1103 clocks = <&cpg CPG_MOD 0x97>; 1104 resets = <&cpg 0x9b>; 1105 power-domains = <&cpg>; 1106 #address-cells = <1>; 1107 #size-cells = <0>; 1108 status = "disabled"; 1109 }; 1110 1111 i2c4: i2c@14401400 { 1112 compatible = "renesas,riic-r9a09g057"; 1113 reg = <0 0x14401400 0 0x400>; 1114 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 1115 <GIC_SPI 515 IRQ_TYPE_EDGE_RISING>, 1116 <GIC_SPI 514 IRQ_TYPE_EDGE_RISING>, 1117 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 1118 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 1119 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 1120 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 1121 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 1122 interrupt-names = "tei", "ri", "ti", "spi", "sti", 1123 "naki", "ali", "tmoi"; 1124 clocks = <&cpg CPG_MOD 0x98>; 1125 resets = <&cpg 0x9c>; 1126 power-domains = <&cpg>; 1127 #address-cells = <1>; 1128 #size-cells = <0>; 1129 status = "disabled"; 1130 }; 1131 1132 i2c5: i2c@14401800 { 1133 compatible = "renesas,riic-r9a09g057"; 1134 reg = <0 0x14401800 0 0x400>; 1135 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 1136 <GIC_SPI 517 IRQ_TYPE_EDGE_RISING>, 1137 <GIC_SPI 516 IRQ_TYPE_EDGE_RISING>, 1138 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 1139 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 1140 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 1141 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 1142 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 1143 interrupt-names = "tei", "ri", "ti", "spi", "sti", 1144 "naki", "ali", "tmoi"; 1145 clocks = <&cpg CPG_MOD 0x99>; 1146 resets = <&cpg 0x9d>; 1147 power-domains = <&cpg>; 1148 #address-cells = <1>; 1149 #size-cells = <0>; 1150 status = "disabled"; 1151 }; 1152 1153 i2c6: i2c@14401c00 { 1154 compatible = "renesas,riic-r9a09g057"; 1155 reg = <0 0x14401c00 0 0x400>; 1156 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 1157 <GIC_SPI 519 IRQ_TYPE_EDGE_RISING>, 1158 <GIC_SPI 518 IRQ_TYPE_EDGE_RISING>, 1159 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 1160 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 1161 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 1162 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 1163 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 1164 interrupt-names = "tei", "ri", "ti", "spi", "sti", 1165 "naki", "ali", "tmoi"; 1166 clocks = <&cpg CPG_MOD 0x9a>; 1167 resets = <&cpg 0x9e>; 1168 power-domains = <&cpg>; 1169 #address-cells = <1>; 1170 #size-cells = <0>; 1171 status = "disabled"; 1172 }; 1173 1174 i2c7: i2c@14402000 { 1175 compatible = "renesas,riic-r9a09g057"; 1176 reg = <0 0x14402000 0 0x400>; 1177 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 1178 <GIC_SPI 521 IRQ_TYPE_EDGE_RISING>, 1179 <GIC_SPI 520 IRQ_TYPE_EDGE_RISING>, 1180 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 1181 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 1182 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 1183 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 1184 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1185 interrupt-names = "tei", "ri", "ti", "spi", "sti", 1186 "naki", "ali", "tmoi"; 1187 clocks = <&cpg CPG_MOD 0x9b>; 1188 resets = <&cpg 0x9f>; 1189 power-domains = <&cpg>; 1190 #address-cells = <1>; 1191 #size-cells = <0>; 1192 status = "disabled"; 1193 }; 1194 1195 i2c8: i2c@11c01000 { 1196 compatible = "renesas,riic-r9a09g057"; 1197 reg = <0 0x11c01000 0 0x400>; 1198 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, 1199 <GIC_SPI 523 IRQ_TYPE_EDGE_RISING>, 1200 <GIC_SPI 522 IRQ_TYPE_EDGE_RISING>, 1201 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 1202 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, 1203 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, 1204 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 1205 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 1206 interrupt-names = "tei", "ri", "ti", "spi", "sti", 1207 "naki", "ali", "tmoi"; 1208 clocks = <&cpg CPG_MOD 0x93>; 1209 resets = <&cpg 0xa0>; 1210 power-domains = <&cpg>; 1211 #address-cells = <1>; 1212 #size-cells = <0>; 1213 status = "disabled"; 1214 }; 1215 1216 gpu: gpu@14850000 { 1217 compatible = "renesas,r9a09g057-mali", 1218 "arm,mali-bifrost"; 1219 reg = <0x0 0x14850000 0x0 0x10000>; 1220 interrupts = <GIC_SPI 884 IRQ_TYPE_LEVEL_HIGH>, 1221 <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>, 1222 <GIC_SPI 883 IRQ_TYPE_LEVEL_HIGH>, 1223 <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>; 1224 interrupt-names = "job", "mmu", "gpu", "event"; 1225 clocks = <&cpg CPG_MOD 0xf0>, 1226 <&cpg CPG_MOD 0xf1>, 1227 <&cpg CPG_MOD 0xf2>; 1228 clock-names = "gpu", "bus", "bus_ace"; 1229 power-domains = <&cpg>; 1230 resets = <&cpg 0xdd>, 1231 <&cpg 0xde>, 1232 <&cpg 0xdf>; 1233 reset-names = "rst", "axi_rst", "ace_rst"; 1234 operating-points-v2 = <&gpu_opp_table>; 1235 status = "disabled"; 1236 }; 1237 1238 gic: interrupt-controller@14900000 { 1239 compatible = "arm,gic-v3"; 1240 reg = <0x0 0x14900000 0 0x20000>, 1241 <0x0 0x14940000 0 0x80000>; 1242 #interrupt-cells = <3>; 1243 #address-cells = <0>; 1244 interrupt-controller; 1245 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 1246 }; 1247 1248 ohci0: usb@15800000 { 1249 compatible = "generic-ohci"; 1250 reg = <0 0x15800000 0 0x100>; 1251 interrupts = <GIC_SPI 742 IRQ_TYPE_LEVEL_HIGH>; 1252 clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb6>; 1253 resets = <&usb20phyrst>, <&cpg 0xac>; 1254 phys = <&usb2_phy0 1>; 1255 phy-names = "usb"; 1256 power-domains = <&cpg>; 1257 status = "disabled"; 1258 }; 1259 1260 ohci1: usb@15810000 { 1261 compatible = "generic-ohci"; 1262 reg = <0 0x15810000 0 0x100>; 1263 interrupts = <GIC_SPI 747 IRQ_TYPE_LEVEL_HIGH>; 1264 clocks = <&cpg CPG_MOD 0xb4>, <&cpg CPG_MOD 0xb7>; 1265 resets = <&usb21phyrst>, <&cpg 0xad>; 1266 phys = <&usb2_phy1 1>; 1267 phy-names = "usb"; 1268 power-domains = <&cpg>; 1269 status = "disabled"; 1270 }; 1271 1272 ehci0: usb@15800100 { 1273 compatible = "generic-ehci"; 1274 reg = <0 0x15800100 0 0x100>; 1275 interrupts = <GIC_SPI 743 IRQ_TYPE_LEVEL_HIGH>; 1276 clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb6>; 1277 resets = <&usb20phyrst>, <&cpg 0xac>; 1278 phys = <&usb2_phy0 2>; 1279 phy-names = "usb"; 1280 companion = <&ohci0>; 1281 power-domains = <&cpg>; 1282 status = "disabled"; 1283 }; 1284 1285 ehci1: usb@15810100 { 1286 compatible = "generic-ehci"; 1287 reg = <0 0x15810100 0 0x100>; 1288 interrupts = <GIC_SPI 748 IRQ_TYPE_LEVEL_HIGH>; 1289 clocks = <&cpg CPG_MOD 0xb4>, <&cpg CPG_MOD 0xb7>; 1290 resets = <&usb21phyrst>, <&cpg 0xad>; 1291 phys = <&usb2_phy1 2>; 1292 phy-names = "usb"; 1293 companion = <&ohci1>; 1294 power-domains = <&cpg>; 1295 status = "disabled"; 1296 }; 1297 1298 usb2_phy0: usb-phy@15800200 { 1299 compatible = "renesas,usb2-phy-r9a09g057"; 1300 reg = <0 0x15800200 0 0x700>; 1301 interrupts = <GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>; 1302 clocks = <&cpg CPG_MOD 0xb3>, 1303 <&cpg CPG_CORE R9A09G057_USB2_0_CLK_CORE0>; 1304 clock-names = "fck", "usb_x1"; 1305 resets = <&usb20phyrst>; 1306 #phy-cells = <1>; 1307 power-domains = <&cpg>; 1308 status = "disabled"; 1309 }; 1310 1311 usb2_phy1: usb-phy@15810200 { 1312 compatible = "renesas,usb2-phy-r9a09g057"; 1313 reg = <0 0x15810200 0 0x700>; 1314 interrupts = <GIC_SPI 750 IRQ_TYPE_LEVEL_HIGH>; 1315 clocks = <&cpg CPG_MOD 0xb4>, 1316 <&cpg CPG_CORE R9A09G057_USB2_0_CLK_CORE1>; 1317 clock-names = "fck", "usb_x1"; 1318 resets = <&usb21phyrst>; 1319 #phy-cells = <1>; 1320 power-domains = <&cpg>; 1321 status = "disabled"; 1322 }; 1323 1324 hsusb: usb@15820000 { 1325 compatible = "renesas,usbhs-r9a09g057", 1326 "renesas,rzg2l-usbhs"; 1327 reg = <0 0x15820000 0 0x10000>; 1328 interrupts = <GIC_SPI 751 IRQ_TYPE_EDGE_RISING>, 1329 <GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>, 1330 <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>, 1331 <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>; 1332 clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb5>; 1333 resets = <&usb20phyrst>, 1334 <&cpg 0xae>; 1335 phys = <&usb2_phy0 3>; 1336 phy-names = "usb"; 1337 power-domains = <&cpg>; 1338 status = "disabled"; 1339 }; 1340 1341 usb20phyrst: usb20phy-reset@15830000 { 1342 compatible = "renesas,r9a09g057-usb2phy-reset"; 1343 reg = <0 0x15830000 0 0x10000>; 1344 clocks = <&cpg CPG_MOD 0xb6>; 1345 resets = <&cpg 0xaf>; 1346 power-domains = <&cpg>; 1347 #reset-cells = <0>; 1348 status = "disabled"; 1349 }; 1350 1351 usb21phyrst: usb21phy-reset@15840000 { 1352 compatible = "renesas,r9a09g057-usb2phy-reset"; 1353 reg = <0 0x15840000 0 0x10000>; 1354 clocks = <&cpg CPG_MOD 0xb7>; 1355 resets = <&cpg 0xaf>; 1356 power-domains = <&cpg>; 1357 #reset-cells = <0>; 1358 status = "disabled"; 1359 }; 1360 1361 xhci0: usb@15850000 { 1362 compatible = "renesas,r9a09g057-xhci", "renesas,r9a09g047-xhci"; 1363 reg = <0 0x15850000 0 0x10000>; 1364 interrupts = <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>, 1365 <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>, 1366 <GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH>, 1367 <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>, 1368 <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>; 1369 interrupt-names = "all", "smi", "hse", "pme", "xhc"; 1370 clocks = <&cpg CPG_MOD 0xaf>; 1371 power-domains = <&cpg>; 1372 resets = <&cpg 0xaa>; 1373 phys = <&usb3_phy0>, <&usb3_phy0>; 1374 phy-names = "usb2-phy", "usb3-phy"; 1375 status = "disabled"; 1376 }; 1377 1378 xhci1: usb@15860000 { 1379 compatible = "renesas,r9a09g057-xhci", "renesas,r9a09g047-xhci"; 1380 reg = <0 0x15860000 0 0x10000>; 1381 interrupts = <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>, 1382 <GIC_SPI 763 IRQ_TYPE_LEVEL_HIGH>, 1383 <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH>, 1384 <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>, 1385 <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH>; 1386 interrupt-names = "all", "smi", "hse", "pme", "xhc"; 1387 clocks = <&cpg CPG_MOD 0xb1>; 1388 power-domains = <&cpg>; 1389 resets = <&cpg 0xab>; 1390 phys = <&usb3_phy1>, <&usb3_phy1>; 1391 phy-names = "usb2-phy", "usb3-phy"; 1392 status = "disabled"; 1393 }; 1394 1395 usb3_phy0: usb-phy@15870000 { 1396 compatible = "renesas,r9a09g057-usb3-phy", "renesas,r9a09g047-usb3-phy"; 1397 reg = <0 0x15870000 0 0x10000>; 1398 clocks = <&cpg CPG_MOD 0xb0>, 1399 <&cpg CPG_CORE R9A09G057_USB3_0_CLKCORE>, 1400 <&cpg CPG_CORE R9A09G057_USB3_0_REF_ALT_CLK_P>; 1401 clock-names = "pclk", "core", "ref_alt_clk_p"; 1402 power-domains = <&cpg>; 1403 resets = <&cpg 0xaa>; 1404 #phy-cells = <0>; 1405 status = "disabled"; 1406 }; 1407 1408 usb3_phy1: usb-phy@15880000 { 1409 compatible = "renesas,r9a09g057-usb3-phy", "renesas,r9a09g047-usb3-phy"; 1410 reg = <0 0x15880000 0 0x10000>; 1411 clocks = <&cpg CPG_MOD 0xb2>, 1412 <&cpg CPG_CORE R9A09G057_USB3_1_CLKCORE>, 1413 <&cpg CPG_CORE R9A09G057_USB3_1_REF_ALT_CLK_P>; 1414 clock-names = "pclk", "core", "ref_alt_clk_p"; 1415 power-domains = <&cpg>; 1416 resets = <&cpg 0xab>; 1417 #phy-cells = <0>; 1418 status = "disabled"; 1419 }; 1420 1421 sdhi0: mmc@15c00000 { 1422 compatible = "renesas,sdhi-r9a09g057"; 1423 reg = <0x0 0x15c00000 0 0x10000>; 1424 interrupts = <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>, 1425 <GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>; 1426 clocks = <&cpg CPG_MOD 0xa3>, <&cpg CPG_MOD 0xa5>, 1427 <&cpg CPG_MOD 0xa4>, <&cpg CPG_MOD 0xa6>; 1428 clock-names = "core", "clkh", "cd", "aclk"; 1429 resets = <&cpg 0xa7>; 1430 power-domains = <&cpg>; 1431 status = "disabled"; 1432 1433 sdhi0_vqmmc: vqmmc-regulator { 1434 regulator-name = "SDHI0-VQMMC"; 1435 regulator-min-microvolt = <1800000>; 1436 regulator-max-microvolt = <3300000>; 1437 status = "disabled"; 1438 }; 1439 }; 1440 1441 sdhi1: mmc@15c10000 { 1442 compatible = "renesas,sdhi-r9a09g057"; 1443 reg = <0x0 0x15c10000 0 0x10000>; 1444 interrupts = <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>, 1445 <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>; 1446 clocks = <&cpg CPG_MOD 0xa7>, <&cpg CPG_MOD 0xa9>, 1447 <&cpg CPG_MOD 0xa8>, <&cpg CPG_MOD 0xaa>; 1448 clock-names = "core", "clkh", "cd", "aclk"; 1449 resets = <&cpg 0xa8>; 1450 power-domains = <&cpg>; 1451 status = "disabled"; 1452 1453 sdhi1_vqmmc: vqmmc-regulator { 1454 regulator-name = "SDHI1-VQMMC"; 1455 regulator-min-microvolt = <1800000>; 1456 regulator-max-microvolt = <3300000>; 1457 status = "disabled"; 1458 }; 1459 }; 1460 1461 sdhi2: mmc@15c20000 { 1462 compatible = "renesas,sdhi-r9a09g057"; 1463 reg = <0x0 0x15c20000 0 0x10000>; 1464 interrupts = <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>, 1465 <GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>; 1466 clocks = <&cpg CPG_MOD 0xab>, <&cpg CPG_MOD 0xad>, 1467 <&cpg CPG_MOD 0xac>, <&cpg CPG_MOD 0xae>; 1468 clock-names = "core", "clkh", "cd", "aclk"; 1469 resets = <&cpg 0xa9>; 1470 power-domains = <&cpg>; 1471 status = "disabled"; 1472 1473 sdhi2_vqmmc: vqmmc-regulator { 1474 regulator-name = "SDHI2-VQMMC"; 1475 regulator-min-microvolt = <1800000>; 1476 regulator-max-microvolt = <3300000>; 1477 status = "disabled"; 1478 }; 1479 }; 1480 1481 eth0: ethernet@15c30000 { 1482 compatible = "renesas,r9a09g057-gbeth", "renesas,rzv2h-gbeth", 1483 "snps,dwmac-5.20"; 1484 reg = <0 0x15c30000 0 0x10000>; 1485 interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>, 1486 <GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>, 1487 <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>, 1488 <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>, 1489 <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 1490 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 1491 <GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>, 1492 <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>, 1493 <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>, 1494 <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>, 1495 <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>; 1496 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", 1497 "rx-queue-0", "rx-queue-1", "rx-queue-2", 1498 "rx-queue-3", "tx-queue-0", "tx-queue-1", 1499 "tx-queue-2", "tx-queue-3"; 1500 clocks = <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>, 1501 <&cpg CPG_CORE R9A09G057_GBETH_0_CLK_PTP_REF_I>, 1502 <&cpg CPG_MOD 0xb8>, <&cpg CPG_MOD 0xb9>, 1503 <&cpg CPG_MOD 0xba>, <&cpg CPG_MOD 0xbb>; 1504 clock-names = "stmmaceth", "pclk", "ptp_ref", 1505 "tx", "rx", "tx-180", "rx-180"; 1506 resets = <&cpg 0xb0>; 1507 power-domains = <&cpg>; 1508 snps,multicast-filter-bins = <256>; 1509 snps,perfect-filter-entries = <128>; 1510 rx-fifo-depth = <8192>; 1511 tx-fifo-depth = <8192>; 1512 snps,fixed-burst; 1513 snps,no-pbl-x8; 1514 snps,force_thresh_dma_mode; 1515 snps,axi-config = <&stmmac_axi_setup>; 1516 snps,mtl-rx-config = <&mtl_rx_setup0>; 1517 snps,mtl-tx-config = <&mtl_tx_setup0>; 1518 snps,txpbl = <32>; 1519 snps,rxpbl = <32>; 1520 status = "disabled"; 1521 1522 mdio0: mdio { 1523 compatible = "snps,dwmac-mdio"; 1524 #address-cells = <1>; 1525 #size-cells = <0>; 1526 }; 1527 1528 mtl_rx_setup0: rx-queues-config { 1529 snps,rx-queues-to-use = <4>; 1530 snps,rx-sched-sp; 1531 1532 queue0 { 1533 snps,dcb-algorithm; 1534 snps,priority = <0x1>; 1535 snps,map-to-dma-channel = <0>; 1536 }; 1537 1538 queue1 { 1539 snps,dcb-algorithm; 1540 snps,priority = <0x2>; 1541 snps,map-to-dma-channel = <1>; 1542 }; 1543 1544 queue2 { 1545 snps,dcb-algorithm; 1546 snps,priority = <0x4>; 1547 snps,map-to-dma-channel = <2>; 1548 }; 1549 1550 queue3 { 1551 snps,dcb-algorithm; 1552 snps,priority = <0x8>; 1553 snps,map-to-dma-channel = <3>; 1554 }; 1555 }; 1556 1557 mtl_tx_setup0: tx-queues-config { 1558 snps,tx-queues-to-use = <4>; 1559 1560 queue0 { 1561 snps,dcb-algorithm; 1562 snps,priority = <0x1>; 1563 }; 1564 1565 queue1 { 1566 snps,dcb-algorithm; 1567 snps,priority = <0x2>; 1568 }; 1569 1570 queue2 { 1571 snps,dcb-algorithm; 1572 snps,priority = <0x4>; 1573 }; 1574 1575 queue3 { 1576 snps,dcb-algorithm; 1577 snps,priority = <0x8>; 1578 }; 1579 }; 1580 }; 1581 1582 eth1: ethernet@15c40000 { 1583 compatible = "renesas,r9a09g057-gbeth", "renesas,rzv2h-gbeth", 1584 "snps,dwmac-5.20"; 1585 reg = <0 0x15c40000 0 0x10000>; 1586 interrupts = <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>, 1587 <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>, 1588 <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>, 1589 <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>, 1590 <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>, 1591 <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>, 1592 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 1593 <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>, 1594 <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 1595 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>, 1596 <GIC_SPI 786 IRQ_TYPE_LEVEL_HIGH>; 1597 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", 1598 "rx-queue-0", "rx-queue-1", "rx-queue-2", 1599 "rx-queue-3", "tx-queue-0", "tx-queue-1", 1600 "tx-queue-2", "tx-queue-3"; 1601 clocks = <&cpg CPG_MOD 0xc3>, <&cpg CPG_MOD 0xc2>, 1602 <&cpg CPG_CORE R9A09G057_GBETH_1_CLK_PTP_REF_I>, 1603 <&cpg CPG_MOD 0xbe>, <&cpg CPG_MOD 0xbf>, 1604 <&cpg CPG_MOD 0xc0>, <&cpg CPG_MOD 0xc1>; 1605 clock-names = "stmmaceth", "pclk", "ptp_ref", 1606 "tx", "rx", "tx-180", "rx-180"; 1607 resets = <&cpg 0xb1>; 1608 power-domains = <&cpg>; 1609 snps,multicast-filter-bins = <256>; 1610 snps,perfect-filter-entries = <128>; 1611 rx-fifo-depth = <8192>; 1612 tx-fifo-depth = <8192>; 1613 snps,fixed-burst; 1614 snps,no-pbl-x8; 1615 snps,force_thresh_dma_mode; 1616 snps,axi-config = <&stmmac_axi_setup>; 1617 snps,mtl-rx-config = <&mtl_rx_setup1>; 1618 snps,mtl-tx-config = <&mtl_tx_setup1>; 1619 snps,txpbl = <32>; 1620 snps,rxpbl = <32>; 1621 status = "disabled"; 1622 1623 mdio1: mdio { 1624 compatible = "snps,dwmac-mdio"; 1625 #address-cells = <1>; 1626 #size-cells = <0>; 1627 }; 1628 1629 mtl_rx_setup1: rx-queues-config { 1630 snps,rx-queues-to-use = <4>; 1631 snps,rx-sched-sp; 1632 1633 queue0 { 1634 snps,dcb-algorithm; 1635 snps,priority = <0x1>; 1636 snps,map-to-dma-channel = <0>; 1637 }; 1638 1639 queue1 { 1640 snps,dcb-algorithm; 1641 snps,priority = <0x2>; 1642 snps,map-to-dma-channel = <1>; 1643 }; 1644 1645 queue2 { 1646 snps,dcb-algorithm; 1647 snps,priority = <0x4>; 1648 snps,map-to-dma-channel = <2>; 1649 }; 1650 1651 queue3 { 1652 snps,dcb-algorithm; 1653 snps,priority = <0x8>; 1654 snps,map-to-dma-channel = <3>; 1655 }; 1656 }; 1657 1658 mtl_tx_setup1: tx-queues-config { 1659 snps,tx-queues-to-use = <4>; 1660 1661 queue0 { 1662 snps,dcb-algorithm; 1663 snps,priority = <0x1>; 1664 }; 1665 1666 queue1 { 1667 snps,dcb-algorithm; 1668 snps,priority = <0x2>; 1669 }; 1670 1671 queue2 { 1672 snps,dcb-algorithm; 1673 snps,priority = <0x4>; 1674 }; 1675 1676 queue3 { 1677 snps,dcb-algorithm; 1678 snps,priority = <0x8>; 1679 }; 1680 }; 1681 }; 1682 1683 dsi: dsi@16430000 { 1684 compatible = "renesas,r9a09g057-mipi-dsi"; 1685 reg = <0 0x16430000 0 0x20000>; 1686 interrupts = <GIC_SPI 874 IRQ_TYPE_LEVEL_HIGH>, 1687 <GIC_SPI 875 IRQ_TYPE_LEVEL_HIGH>, 1688 <GIC_SPI 876 IRQ_TYPE_LEVEL_HIGH>, 1689 <GIC_SPI 877 IRQ_TYPE_LEVEL_HIGH>, 1690 <GIC_SPI 878 IRQ_TYPE_LEVEL_HIGH>, 1691 <GIC_SPI 879 IRQ_TYPE_LEVEL_HIGH>, 1692 <GIC_SPI 880 IRQ_TYPE_LEVEL_HIGH>; 1693 interrupt-names = "seq0", "seq1", "vin1", "rcv", 1694 "ferr", "ppi", "debug"; 1695 clocks = <&cpg CPG_MOD 0xec>, <&cpg CPG_MOD 0xe9>, 1696 <&cpg CPG_MOD 0xe8>, <&cpg CPG_MOD 0xea>, 1697 <&cpg CPG_MOD 0xeb>; 1698 clock-names = "pllrefclk", "aclk", "pclk", "vclk", "lpclk"; 1699 resets = <&cpg 0xd8>, <&cpg 0xd7>; 1700 reset-names = "arst", "prst"; 1701 power-domains = <&cpg>; 1702 status = "disabled"; 1703 1704 ports { 1705 #address-cells = <1>; 1706 #size-cells = <0>; 1707 1708 port@0 { 1709 reg = <0>; 1710 dsi_in: endpoint { 1711 remote-endpoint = <&du_out_dsi>; 1712 }; 1713 }; 1714 1715 port@1 { 1716 reg = <1>; 1717 dsi_out: endpoint { 1718 }; 1719 }; 1720 }; 1721 }; 1722 1723 du: display@16460000 { 1724 compatible = "renesas,r9a09g057-du"; 1725 reg = <0 0x16460000 0 0x10000>; 1726 interrupts = <GIC_SPI 882 IRQ_TYPE_LEVEL_HIGH>; 1727 clocks = <&cpg CPG_MOD 0xed>, <&cpg CPG_MOD 0xee>, 1728 <&cpg CPG_MOD 0xef>; 1729 clock-names = "aclk", "pclk", "vclk"; 1730 power-domains = <&cpg>; 1731 resets = <&cpg 0xdc>; 1732 renesas,vsps = <&vspd 0>; 1733 status = "disabled"; 1734 1735 ports { 1736 #address-cells = <1>; 1737 #size-cells = <0>; 1738 1739 port@0 { 1740 reg = <0>; 1741 du_out_dsi: endpoint { 1742 remote-endpoint = <&dsi_in>; 1743 }; 1744 }; 1745 }; 1746 }; 1747 1748 fcpvd: fcp@16470000 { 1749 compatible = "renesas,r9a09g057-fcpvd", "renesas,fcpv"; 1750 reg = <0 0x16470000 0 0x10000>; 1751 clocks = <&cpg CPG_MOD 0xed>, 1752 <&cpg CPG_MOD 0xee>, 1753 <&cpg CPG_MOD 0xef>; 1754 clock-names = "aclk", "pclk", "vclk"; 1755 power-domains = <&cpg>; 1756 resets = <&cpg 0xdc>; 1757 }; 1758 1759 vspd: vsp@16480000 { 1760 compatible = "renesas,r9a09g057-vsp2", "renesas,r9a07g044-vsp2"; 1761 reg = <0 0x16480000 0 0x10000>; 1762 interrupts = <GIC_SPI 881 IRQ_TYPE_LEVEL_HIGH>; 1763 clocks = <&cpg CPG_MOD 0xed>, 1764 <&cpg CPG_MOD 0xee>, 1765 <&cpg CPG_MOD 0xef>; 1766 clock-names = "aclk", "pclk", "vclk"; 1767 power-domains = <&cpg>; 1768 resets = <&cpg 0xdc>; 1769 renesas,fcp = <&fcpvd>; 1770 }; 1771 }; 1772 1773 stmmac_axi_setup: stmmac-axi-config { 1774 snps,lpi_en; 1775 snps,wr_osr_lmt = <0xf>; 1776 snps,rd_osr_lmt = <0xf>; 1777 snps,blen = <16 8 4 0 0 0 0>; 1778 }; 1779 1780 thermal-zones { 1781 sensor1_thermal: sensor1-thermal { 1782 polling-delay = <1000>; 1783 polling-delay-passive = <250>; 1784 thermal-sensors = <&tsu0>; 1785 1786 trips { 1787 sensor1_crit: sensor1-crit { 1788 temperature = <120000>; 1789 hysteresis = <1000>; 1790 type = "critical"; 1791 }; 1792 }; 1793 }; 1794 1795 sensor2_thermal: sensor2-thermal { 1796 polling-delay = <1000>; 1797 polling-delay-passive = <250>; 1798 thermal-sensors = <&tsu1>; 1799 1800 cooling-maps { 1801 map0 { 1802 trip = <&sensor2_target>; 1803 cooling-device = <&cpu0 0 3>, <&cpu1 0 3>, 1804 <&cpu2 0 3>, <&cpu3 0 3>; 1805 contribution = <1024>; 1806 }; 1807 }; 1808 1809 trips { 1810 sensor2_target: trip-point { 1811 temperature = <95000>; 1812 hysteresis = <1000>; 1813 type = "passive"; 1814 }; 1815 1816 sensor2_crit: sensor2-crit { 1817 temperature = <120000>; 1818 hysteresis = <1000>; 1819 type = "critical"; 1820 }; 1821 }; 1822 }; 1823 }; 1824 1825 timer { 1826 compatible = "arm,armv8-timer"; 1827 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 1828 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 1829 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 1830 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 1831 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 1832 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 1833 }; 1834}; 1835