1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 *
5 * Copyright (C) 2002 - 2011 Paul Mundt
6 * Copyright (C) 2015 Glider bvba
7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
8 *
9 * based off of the old drivers/char/sh-sci.c by:
10 *
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
16 * Removed SH7300 support (Jul 2007).
17 */
18 #undef DEBUG
19
20 #include <linux/clk.h>
21 #include <linux/console.h>
22 #include <linux/ctype.h>
23 #include <linux/cpufreq.h>
24 #include <linux/delay.h>
25 #include <linux/dmaengine.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/err.h>
28 #include <linux/errno.h>
29 #include <linux/init.h>
30 #include <linux/interrupt.h>
31 #include <linux/ioport.h>
32 #include <linux/ktime.h>
33 #include <linux/major.h>
34 #include <linux/minmax.h>
35 #include <linux/module.h>
36 #include <linux/mm.h>
37 #include <linux/of.h>
38 #include <linux/platform_device.h>
39 #include <linux/pm_runtime.h>
40 #include <linux/reset.h>
41 #include <linux/scatterlist.h>
42 #include <linux/serial.h>
43 #include <linux/serial_sci.h>
44 #include <linux/sh_dma.h>
45 #include <linux/slab.h>
46 #include <linux/string.h>
47 #include <linux/sysrq.h>
48 #include <linux/timer.h>
49 #include <linux/tty.h>
50 #include <linux/tty_flip.h>
51
52 #ifdef CONFIG_SUPERH
53 #include <asm/sh_bios.h>
54 #include <asm/platform_early.h>
55 #endif
56
57 #include "serial_mctrl_gpio.h"
58 #include "sh-sci.h"
59
60 /* Offsets into the sci_port->irqs array */
61 enum {
62 SCIx_ERI_IRQ,
63 SCIx_RXI_IRQ,
64 SCIx_TXI_IRQ,
65 SCIx_BRI_IRQ,
66 SCIx_DRI_IRQ,
67 SCIx_TEI_IRQ,
68 SCIx_NR_IRQS,
69
70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
71 };
72
73 #define SCIx_IRQ_IS_MUXED(port) \
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
78
79 enum SCI_CLKS {
80 SCI_FCK, /* Functional Clock */
81 SCI_SCK, /* Optional External Clock */
82 SCI_BRG_INT, /* Optional BRG Internal Clock Source */
83 SCI_SCIF_CLK, /* Optional BRG External Clock Source */
84 SCI_NUM_CLKS
85 };
86
87 /* Bit x set means sampling rate x + 1 is supported */
88 #define SCI_SR(x) BIT((x) - 1)
89 #define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
90
91 #define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
92 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
93 SCI_SR(19) | SCI_SR(27)
94
95 #define min_sr(_port) ffs((_port)->sampling_rate_mask)
96 #define max_sr(_port) fls((_port)->sampling_rate_mask)
97
98 /* Iterate over all supported sampling rates, from high to low */
99 #define for_each_sr(_sr, _port) \
100 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
101 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
102
103 struct plat_sci_reg {
104 u8 offset, size;
105 };
106
107 struct sci_suspend_regs {
108 u16 scdl;
109 u16 sccks;
110 u16 scsmr;
111 u16 scscr;
112 u16 scfcr;
113 u16 scsptr;
114 u16 hssrr;
115 u16 scpcr;
116 u16 scpdr;
117 u8 scbrr;
118 u8 semr;
119 };
120
121 struct sci_port_params {
122 const struct plat_sci_reg regs[SCIx_NR_REGS];
123 unsigned int fifosize;
124 unsigned int overrun_reg;
125 unsigned int overrun_mask;
126 unsigned int sampling_rate_mask;
127 unsigned int error_mask;
128 unsigned int error_clear;
129 };
130
131 struct sci_port {
132 struct uart_port port;
133
134 /* Platform configuration */
135 const struct sci_port_params *params;
136 const struct plat_sci_port *cfg;
137 unsigned int sampling_rate_mask;
138 resource_size_t reg_size;
139 struct mctrl_gpios *gpios;
140
141 /* Clocks */
142 struct clk *clks[SCI_NUM_CLKS];
143 unsigned long clk_rates[SCI_NUM_CLKS];
144
145 int irqs[SCIx_NR_IRQS];
146 char *irqstr[SCIx_NR_IRQS];
147
148 struct dma_chan *chan_tx;
149 struct dma_chan *chan_rx;
150
151 struct reset_control *rstc;
152
153 #ifdef CONFIG_SERIAL_SH_SCI_DMA
154 struct dma_chan *chan_tx_saved;
155 struct dma_chan *chan_rx_saved;
156 dma_cookie_t cookie_tx;
157 dma_cookie_t cookie_rx[2];
158 dma_cookie_t active_rx;
159 dma_addr_t tx_dma_addr;
160 unsigned int tx_dma_len;
161 struct scatterlist sg_rx[2];
162 void *rx_buf[2];
163 size_t buf_len_rx;
164 struct work_struct work_tx;
165 struct hrtimer rx_timer;
166 unsigned int rx_timeout; /* microseconds */
167 #endif
168 unsigned int rx_frame;
169 int rx_trigger;
170 struct timer_list rx_fifo_timer;
171 int rx_fifo_timeout;
172 struct sci_suspend_regs suspend_regs;
173 u16 hscif_tot;
174
175 bool has_rtscts;
176 bool autorts;
177 bool tx_occurred;
178 };
179
180 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
181
182 static struct sci_port sci_ports[SCI_NPORTS];
183 static unsigned long sci_ports_in_use;
184 static struct uart_driver sci_uart_driver;
185 static bool sci_uart_earlycon;
186 static bool sci_uart_earlycon_dev_probing;
187
188 static inline struct sci_port *
to_sci_port(struct uart_port * uart)189 to_sci_port(struct uart_port *uart)
190 {
191 return container_of(uart, struct sci_port, port);
192 }
193
194 static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
195 /*
196 * Common SCI definitions, dependent on the port's regshift
197 * value.
198 */
199 [SCIx_SCI_REGTYPE] = {
200 .regs = {
201 [SCSMR] = { 0x00, 8 },
202 [SCBRR] = { 0x01, 8 },
203 [SCSCR] = { 0x02, 8 },
204 [SCxTDR] = { 0x03, 8 },
205 [SCxSR] = { 0x04, 8 },
206 [SCxRDR] = { 0x05, 8 },
207 },
208 .fifosize = 1,
209 .overrun_reg = SCxSR,
210 .overrun_mask = SCI_ORER,
211 .sampling_rate_mask = SCI_SR(32),
212 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
213 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
214 },
215
216 /*
217 * Common definitions for legacy IrDA ports.
218 */
219 [SCIx_IRDA_REGTYPE] = {
220 .regs = {
221 [SCSMR] = { 0x00, 8 },
222 [SCBRR] = { 0x02, 8 },
223 [SCSCR] = { 0x04, 8 },
224 [SCxTDR] = { 0x06, 8 },
225 [SCxSR] = { 0x08, 16 },
226 [SCxRDR] = { 0x0a, 8 },
227 [SCFCR] = { 0x0c, 8 },
228 [SCFDR] = { 0x0e, 16 },
229 },
230 .fifosize = 1,
231 .overrun_reg = SCxSR,
232 .overrun_mask = SCI_ORER,
233 .sampling_rate_mask = SCI_SR(32),
234 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
235 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
236 },
237
238 /*
239 * Common SCIFA definitions.
240 */
241 [SCIx_SCIFA_REGTYPE] = {
242 .regs = {
243 [SCSMR] = { 0x00, 16 },
244 [SCBRR] = { 0x04, 8 },
245 [SCSCR] = { 0x08, 16 },
246 [SCxTDR] = { 0x20, 8 },
247 [SCxSR] = { 0x14, 16 },
248 [SCxRDR] = { 0x24, 8 },
249 [SCFCR] = { 0x18, 16 },
250 [SCFDR] = { 0x1c, 16 },
251 [SCPCR] = { 0x30, 16 },
252 [SCPDR] = { 0x34, 16 },
253 },
254 .fifosize = 64,
255 .overrun_reg = SCxSR,
256 .overrun_mask = SCIFA_ORER,
257 .sampling_rate_mask = SCI_SR_SCIFAB,
258 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
259 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
260 },
261
262 /*
263 * Common SCIFB definitions.
264 */
265 [SCIx_SCIFB_REGTYPE] = {
266 .regs = {
267 [SCSMR] = { 0x00, 16 },
268 [SCBRR] = { 0x04, 8 },
269 [SCSCR] = { 0x08, 16 },
270 [SCxTDR] = { 0x40, 8 },
271 [SCxSR] = { 0x14, 16 },
272 [SCxRDR] = { 0x60, 8 },
273 [SCFCR] = { 0x18, 16 },
274 [SCTFDR] = { 0x38, 16 },
275 [SCRFDR] = { 0x3c, 16 },
276 [SCPCR] = { 0x30, 16 },
277 [SCPDR] = { 0x34, 16 },
278 },
279 .fifosize = 256,
280 .overrun_reg = SCxSR,
281 .overrun_mask = SCIFA_ORER,
282 .sampling_rate_mask = SCI_SR_SCIFAB,
283 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
284 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
285 },
286
287 /*
288 * Common SH-2(A) SCIF definitions for ports with FIFO data
289 * count registers.
290 */
291 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
292 .regs = {
293 [SCSMR] = { 0x00, 16 },
294 [SCBRR] = { 0x04, 8 },
295 [SCSCR] = { 0x08, 16 },
296 [SCxTDR] = { 0x0c, 8 },
297 [SCxSR] = { 0x10, 16 },
298 [SCxRDR] = { 0x14, 8 },
299 [SCFCR] = { 0x18, 16 },
300 [SCFDR] = { 0x1c, 16 },
301 [SCSPTR] = { 0x20, 16 },
302 [SCLSR] = { 0x24, 16 },
303 },
304 .fifosize = 16,
305 .overrun_reg = SCLSR,
306 .overrun_mask = SCLSR_ORER,
307 .sampling_rate_mask = SCI_SR(32),
308 .error_mask = SCIF_DEFAULT_ERROR_MASK,
309 .error_clear = SCIF_ERROR_CLEAR,
310 },
311
312 /*
313 * The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T.
314 * It looks like a normal SCIF with FIFO data, but with a
315 * compressed address space. Also, the break out of interrupts
316 * are different: ERI/BRI, RXI, TXI, TEI, DRI.
317 */
318 [SCIx_RZ_SCIFA_REGTYPE] = {
319 .regs = {
320 [SCSMR] = { 0x00, 16 },
321 [SCBRR] = { 0x02, 8 },
322 [SCSCR] = { 0x04, 16 },
323 [SCxTDR] = { 0x06, 8 },
324 [SCxSR] = { 0x08, 16 },
325 [SCxRDR] = { 0x0A, 8 },
326 [SCFCR] = { 0x0C, 16 },
327 [SCFDR] = { 0x0E, 16 },
328 [SCSPTR] = { 0x10, 16 },
329 [SCLSR] = { 0x12, 16 },
330 [SEMR] = { 0x14, 8 },
331 },
332 .fifosize = 16,
333 .overrun_reg = SCLSR,
334 .overrun_mask = SCLSR_ORER,
335 .sampling_rate_mask = SCI_SR(32),
336 .error_mask = SCIF_DEFAULT_ERROR_MASK,
337 .error_clear = SCIF_ERROR_CLEAR,
338 },
339
340 /*
341 * The "SCIF" that is in RZ/V2H(P) SoC is similar to one found on RZ/G2L SoC
342 * with below differences,
343 * - Break out of interrupts are different: ERI, BRI, RXI, TXI, TEI, DRI,
344 * TEI-DRI, RXI-EDGE and TXI-EDGE.
345 * - SCSMR register does not have CM bit (BIT(7)) ie it does not support synchronous mode.
346 * - SCFCR register does not have SCFCR_MCE bit.
347 * - SCSPTR register has only bits SCSPTR_SPB2DT and SCSPTR_SPB2IO.
348 */
349 [SCIx_RZV2H_SCIF_REGTYPE] = {
350 .regs = {
351 [SCSMR] = { 0x00, 16 },
352 [SCBRR] = { 0x02, 8 },
353 [SCSCR] = { 0x04, 16 },
354 [SCxTDR] = { 0x06, 8 },
355 [SCxSR] = { 0x08, 16 },
356 [SCxRDR] = { 0x0a, 8 },
357 [SCFCR] = { 0x0c, 16 },
358 [SCFDR] = { 0x0e, 16 },
359 [SCSPTR] = { 0x10, 16 },
360 [SCLSR] = { 0x12, 16 },
361 [SEMR] = { 0x14, 8 },
362 },
363 .fifosize = 16,
364 .overrun_reg = SCLSR,
365 .overrun_mask = SCLSR_ORER,
366 .sampling_rate_mask = SCI_SR(32),
367 .error_mask = SCIF_DEFAULT_ERROR_MASK,
368 .error_clear = SCIF_ERROR_CLEAR,
369 },
370
371 /*
372 * Common SH-3 SCIF definitions.
373 */
374 [SCIx_SH3_SCIF_REGTYPE] = {
375 .regs = {
376 [SCSMR] = { 0x00, 8 },
377 [SCBRR] = { 0x02, 8 },
378 [SCSCR] = { 0x04, 8 },
379 [SCxTDR] = { 0x06, 8 },
380 [SCxSR] = { 0x08, 16 },
381 [SCxRDR] = { 0x0a, 8 },
382 [SCFCR] = { 0x0c, 8 },
383 [SCFDR] = { 0x0e, 16 },
384 },
385 .fifosize = 16,
386 .overrun_reg = SCLSR,
387 .overrun_mask = SCLSR_ORER,
388 .sampling_rate_mask = SCI_SR(32),
389 .error_mask = SCIF_DEFAULT_ERROR_MASK,
390 .error_clear = SCIF_ERROR_CLEAR,
391 },
392
393 /*
394 * Common SH-4(A) SCIF(B) definitions.
395 */
396 [SCIx_SH4_SCIF_REGTYPE] = {
397 .regs = {
398 [SCSMR] = { 0x00, 16 },
399 [SCBRR] = { 0x04, 8 },
400 [SCSCR] = { 0x08, 16 },
401 [SCxTDR] = { 0x0c, 8 },
402 [SCxSR] = { 0x10, 16 },
403 [SCxRDR] = { 0x14, 8 },
404 [SCFCR] = { 0x18, 16 },
405 [SCFDR] = { 0x1c, 16 },
406 [SCSPTR] = { 0x20, 16 },
407 [SCLSR] = { 0x24, 16 },
408 },
409 .fifosize = 16,
410 .overrun_reg = SCLSR,
411 .overrun_mask = SCLSR_ORER,
412 .sampling_rate_mask = SCI_SR(32),
413 .error_mask = SCIF_DEFAULT_ERROR_MASK,
414 .error_clear = SCIF_ERROR_CLEAR,
415 },
416
417 /*
418 * Common SCIF definitions for ports with a Baud Rate Generator for
419 * External Clock (BRG).
420 */
421 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
422 .regs = {
423 [SCSMR] = { 0x00, 16 },
424 [SCBRR] = { 0x04, 8 },
425 [SCSCR] = { 0x08, 16 },
426 [SCxTDR] = { 0x0c, 8 },
427 [SCxSR] = { 0x10, 16 },
428 [SCxRDR] = { 0x14, 8 },
429 [SCFCR] = { 0x18, 16 },
430 [SCFDR] = { 0x1c, 16 },
431 [SCSPTR] = { 0x20, 16 },
432 [SCLSR] = { 0x24, 16 },
433 [SCDL] = { 0x30, 16 },
434 [SCCKS] = { 0x34, 16 },
435 },
436 .fifosize = 16,
437 .overrun_reg = SCLSR,
438 .overrun_mask = SCLSR_ORER,
439 .sampling_rate_mask = SCI_SR(32),
440 .error_mask = SCIF_DEFAULT_ERROR_MASK,
441 .error_clear = SCIF_ERROR_CLEAR,
442 },
443
444 /*
445 * Common HSCIF definitions.
446 */
447 [SCIx_HSCIF_REGTYPE] = {
448 .regs = {
449 [SCSMR] = { 0x00, 16 },
450 [SCBRR] = { 0x04, 8 },
451 [SCSCR] = { 0x08, 16 },
452 [SCxTDR] = { 0x0c, 8 },
453 [SCxSR] = { 0x10, 16 },
454 [SCxRDR] = { 0x14, 8 },
455 [SCFCR] = { 0x18, 16 },
456 [SCFDR] = { 0x1c, 16 },
457 [SCSPTR] = { 0x20, 16 },
458 [SCLSR] = { 0x24, 16 },
459 [HSSRR] = { 0x40, 16 },
460 [SCDL] = { 0x30, 16 },
461 [SCCKS] = { 0x34, 16 },
462 [HSRTRGR] = { 0x54, 16 },
463 [HSTTRGR] = { 0x58, 16 },
464 },
465 .fifosize = 128,
466 .overrun_reg = SCLSR,
467 .overrun_mask = SCLSR_ORER,
468 .sampling_rate_mask = SCI_SR_RANGE(8, 32),
469 .error_mask = SCIF_DEFAULT_ERROR_MASK,
470 .error_clear = SCIF_ERROR_CLEAR,
471 },
472
473 /*
474 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
475 * register.
476 */
477 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
478 .regs = {
479 [SCSMR] = { 0x00, 16 },
480 [SCBRR] = { 0x04, 8 },
481 [SCSCR] = { 0x08, 16 },
482 [SCxTDR] = { 0x0c, 8 },
483 [SCxSR] = { 0x10, 16 },
484 [SCxRDR] = { 0x14, 8 },
485 [SCFCR] = { 0x18, 16 },
486 [SCFDR] = { 0x1c, 16 },
487 [SCLSR] = { 0x24, 16 },
488 },
489 .fifosize = 16,
490 .overrun_reg = SCLSR,
491 .overrun_mask = SCLSR_ORER,
492 .sampling_rate_mask = SCI_SR(32),
493 .error_mask = SCIF_DEFAULT_ERROR_MASK,
494 .error_clear = SCIF_ERROR_CLEAR,
495 },
496
497 /*
498 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
499 * count registers.
500 */
501 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
502 .regs = {
503 [SCSMR] = { 0x00, 16 },
504 [SCBRR] = { 0x04, 8 },
505 [SCSCR] = { 0x08, 16 },
506 [SCxTDR] = { 0x0c, 8 },
507 [SCxSR] = { 0x10, 16 },
508 [SCxRDR] = { 0x14, 8 },
509 [SCFCR] = { 0x18, 16 },
510 [SCFDR] = { 0x1c, 16 },
511 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
512 [SCRFDR] = { 0x20, 16 },
513 [SCSPTR] = { 0x24, 16 },
514 [SCLSR] = { 0x28, 16 },
515 },
516 .fifosize = 16,
517 .overrun_reg = SCLSR,
518 .overrun_mask = SCLSR_ORER,
519 .sampling_rate_mask = SCI_SR(32),
520 .error_mask = SCIF_DEFAULT_ERROR_MASK,
521 .error_clear = SCIF_ERROR_CLEAR,
522 },
523
524 /*
525 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
526 * registers.
527 */
528 [SCIx_SH7705_SCIF_REGTYPE] = {
529 .regs = {
530 [SCSMR] = { 0x00, 16 },
531 [SCBRR] = { 0x04, 8 },
532 [SCSCR] = { 0x08, 16 },
533 [SCxTDR] = { 0x20, 8 },
534 [SCxSR] = { 0x14, 16 },
535 [SCxRDR] = { 0x24, 8 },
536 [SCFCR] = { 0x18, 16 },
537 [SCFDR] = { 0x1c, 16 },
538 },
539 .fifosize = 64,
540 .overrun_reg = SCxSR,
541 .overrun_mask = SCIFA_ORER,
542 .sampling_rate_mask = SCI_SR(16),
543 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
544 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
545 },
546 };
547
548 #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset])
549
550 /*
551 * The "offset" here is rather misleading, in that it refers to an enum
552 * value relative to the port mapping rather than the fixed offset
553 * itself, which needs to be manually retrieved from the platform's
554 * register map for the given port.
555 */
sci_serial_in(struct uart_port * p,int offset)556 static unsigned int sci_serial_in(struct uart_port *p, int offset)
557 {
558 const struct plat_sci_reg *reg = sci_getreg(p, offset);
559
560 if (reg->size == 8)
561 return ioread8(p->membase + (reg->offset << p->regshift));
562 else if (reg->size == 16)
563 return ioread16(p->membase + (reg->offset << p->regshift));
564 else
565 WARN(1, "Invalid register access\n");
566
567 return 0;
568 }
569
sci_serial_out(struct uart_port * p,int offset,int value)570 static void sci_serial_out(struct uart_port *p, int offset, int value)
571 {
572 const struct plat_sci_reg *reg = sci_getreg(p, offset);
573
574 if (reg->size == 8)
575 iowrite8(value, p->membase + (reg->offset << p->regshift));
576 else if (reg->size == 16)
577 iowrite16(value, p->membase + (reg->offset << p->regshift));
578 else
579 WARN(1, "Invalid register access\n");
580 }
581
sci_port_enable(struct sci_port * sci_port)582 static void sci_port_enable(struct sci_port *sci_port)
583 {
584 unsigned int i;
585
586 if (!sci_port->port.dev)
587 return;
588
589 pm_runtime_get_sync(sci_port->port.dev);
590
591 for (i = 0; i < SCI_NUM_CLKS; i++) {
592 clk_prepare_enable(sci_port->clks[i]);
593 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
594 }
595 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
596 }
597
sci_port_disable(struct sci_port * sci_port)598 static void sci_port_disable(struct sci_port *sci_port)
599 {
600 unsigned int i;
601
602 if (!sci_port->port.dev)
603 return;
604
605 for (i = SCI_NUM_CLKS; i-- > 0; )
606 clk_disable_unprepare(sci_port->clks[i]);
607
608 pm_runtime_put_sync(sci_port->port.dev);
609 }
610
port_rx_irq_mask(struct uart_port * port)611 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
612 {
613 /*
614 * Not all ports (such as SCIFA) will support REIE. Rather than
615 * special-casing the port type, we check the port initialization
616 * IRQ enable mask to see whether the IRQ is desired at all. If
617 * it's unset, it's logically inferred that there's no point in
618 * testing for it.
619 */
620 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
621 }
622
sci_start_tx(struct uart_port * port)623 static void sci_start_tx(struct uart_port *port)
624 {
625 struct sci_port *s = to_sci_port(port);
626 unsigned short ctrl;
627
628 #ifdef CONFIG_SERIAL_SH_SCI_DMA
629 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
630 u16 new, scr = sci_serial_in(port, SCSCR);
631 if (s->chan_tx)
632 new = scr | SCSCR_TDRQE;
633 else
634 new = scr & ~SCSCR_TDRQE;
635 if (new != scr)
636 sci_serial_out(port, SCSCR, new);
637 }
638
639 if (s->chan_tx && !kfifo_is_empty(&port->state->port.xmit_fifo) &&
640 dma_submit_error(s->cookie_tx)) {
641 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE)
642 /* Switch irq from SCIF to DMA */
643 disable_irq_nosync(s->irqs[SCIx_TXI_IRQ]);
644
645 s->cookie_tx = 0;
646 schedule_work(&s->work_tx);
647 }
648 #endif
649
650 if (!s->chan_tx || s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE ||
651 port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
652 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
653 ctrl = sci_serial_in(port, SCSCR);
654
655 /*
656 * For SCI, TE (transmit enable) must be set after setting TIE
657 * (transmit interrupt enable) or in the same instruction to start
658 * the transmit process.
659 */
660 if (port->type == PORT_SCI)
661 ctrl |= SCSCR_TE;
662
663 sci_serial_out(port, SCSCR, ctrl | SCSCR_TIE);
664 }
665 }
666
sci_stop_tx(struct uart_port * port)667 static void sci_stop_tx(struct uart_port *port)
668 {
669 unsigned short ctrl;
670
671 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
672 ctrl = sci_serial_in(port, SCSCR);
673
674 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
675 ctrl &= ~SCSCR_TDRQE;
676
677 ctrl &= ~SCSCR_TIE;
678
679 sci_serial_out(port, SCSCR, ctrl);
680
681 #ifdef CONFIG_SERIAL_SH_SCI_DMA
682 if (to_sci_port(port)->chan_tx &&
683 !dma_submit_error(to_sci_port(port)->cookie_tx)) {
684 dmaengine_terminate_async(to_sci_port(port)->chan_tx);
685 to_sci_port(port)->cookie_tx = -EINVAL;
686 }
687 #endif
688 }
689
sci_start_rx(struct uart_port * port)690 static void sci_start_rx(struct uart_port *port)
691 {
692 unsigned short ctrl;
693
694 ctrl = sci_serial_in(port, SCSCR) | port_rx_irq_mask(port);
695
696 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
697 ctrl &= ~SCSCR_RDRQE;
698
699 sci_serial_out(port, SCSCR, ctrl);
700 }
701
sci_stop_rx(struct uart_port * port)702 static void sci_stop_rx(struct uart_port *port)
703 {
704 unsigned short ctrl;
705
706 ctrl = sci_serial_in(port, SCSCR);
707
708 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
709 ctrl &= ~SCSCR_RDRQE;
710
711 ctrl &= ~port_rx_irq_mask(port);
712
713 sci_serial_out(port, SCSCR, ctrl);
714 }
715
sci_clear_SCxSR(struct uart_port * port,unsigned int mask)716 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
717 {
718 if (port->type == PORT_SCI) {
719 /* Just store the mask */
720 sci_serial_out(port, SCxSR, mask);
721 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) {
722 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
723 /* Only clear the status bits we want to clear */
724 sci_serial_out(port, SCxSR, sci_serial_in(port, SCxSR) & mask);
725 } else {
726 /* Store the mask, clear parity/framing errors */
727 sci_serial_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
728 }
729 }
730
731 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
732 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
733
734 #ifdef CONFIG_CONSOLE_POLL
sci_poll_get_char(struct uart_port * port)735 static int sci_poll_get_char(struct uart_port *port)
736 {
737 unsigned short status;
738 int c;
739
740 do {
741 status = sci_serial_in(port, SCxSR);
742 if (status & SCxSR_ERRORS(port)) {
743 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
744 continue;
745 }
746 break;
747 } while (1);
748
749 if (!(status & SCxSR_RDxF(port)))
750 return NO_POLL_CHAR;
751
752 c = sci_serial_in(port, SCxRDR);
753
754 /* Dummy read */
755 sci_serial_in(port, SCxSR);
756 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
757
758 return c;
759 }
760 #endif
761
sci_poll_put_char(struct uart_port * port,unsigned char c)762 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
763 {
764 unsigned short status;
765
766 do {
767 status = sci_serial_in(port, SCxSR);
768 } while (!(status & SCxSR_TDxE(port)));
769
770 sci_serial_out(port, SCxTDR, c);
771 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
772 }
773 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
774 CONFIG_SERIAL_SH_SCI_EARLYCON */
775
sci_init_pins(struct uart_port * port,unsigned int cflag)776 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
777 {
778 struct sci_port *s = to_sci_port(port);
779
780 /*
781 * Use port-specific handler if provided.
782 */
783 if (s->cfg->ops && s->cfg->ops->init_pins) {
784 s->cfg->ops->init_pins(port, cflag);
785 return;
786 }
787
788 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
789 u16 data = sci_serial_in(port, SCPDR);
790 u16 ctrl = sci_serial_in(port, SCPCR);
791
792 /* Enable RXD and TXD pin functions */
793 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
794 if (to_sci_port(port)->has_rtscts) {
795 /* RTS# is output, active low, unless autorts */
796 if (!(port->mctrl & TIOCM_RTS)) {
797 ctrl |= SCPCR_RTSC;
798 data |= SCPDR_RTSD;
799 } else if (!s->autorts) {
800 ctrl |= SCPCR_RTSC;
801 data &= ~SCPDR_RTSD;
802 } else {
803 /* Enable RTS# pin function */
804 ctrl &= ~SCPCR_RTSC;
805 }
806 /* Enable CTS# pin function */
807 ctrl &= ~SCPCR_CTSC;
808 }
809 sci_serial_out(port, SCPDR, data);
810 sci_serial_out(port, SCPCR, ctrl);
811 } else if (sci_getreg(port, SCSPTR)->size && s->cfg->regtype != SCIx_RZV2H_SCIF_REGTYPE) {
812 u16 status = sci_serial_in(port, SCSPTR);
813
814 /* RTS# is always output; and active low, unless autorts */
815 status |= SCSPTR_RTSIO;
816 if (!(port->mctrl & TIOCM_RTS))
817 status |= SCSPTR_RTSDT;
818 else if (!s->autorts)
819 status &= ~SCSPTR_RTSDT;
820 /* CTS# and SCK are inputs */
821 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
822 sci_serial_out(port, SCSPTR, status);
823 }
824 }
825
sci_txfill(struct uart_port * port)826 static int sci_txfill(struct uart_port *port)
827 {
828 struct sci_port *s = to_sci_port(port);
829 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
830 const struct plat_sci_reg *reg;
831
832 reg = sci_getreg(port, SCTFDR);
833 if (reg->size)
834 return sci_serial_in(port, SCTFDR) & fifo_mask;
835
836 reg = sci_getreg(port, SCFDR);
837 if (reg->size)
838 return sci_serial_in(port, SCFDR) >> 8;
839
840 return !(sci_serial_in(port, SCxSR) & SCI_TDRE);
841 }
842
sci_txroom(struct uart_port * port)843 static int sci_txroom(struct uart_port *port)
844 {
845 return port->fifosize - sci_txfill(port);
846 }
847
sci_rxfill(struct uart_port * port)848 static int sci_rxfill(struct uart_port *port)
849 {
850 struct sci_port *s = to_sci_port(port);
851 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
852 const struct plat_sci_reg *reg;
853
854 reg = sci_getreg(port, SCRFDR);
855 if (reg->size)
856 return sci_serial_in(port, SCRFDR) & fifo_mask;
857
858 reg = sci_getreg(port, SCFDR);
859 if (reg->size)
860 return sci_serial_in(port, SCFDR) & fifo_mask;
861
862 return (sci_serial_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
863 }
864
865 /* ********************************************************************** *
866 * the interrupt related routines *
867 * ********************************************************************** */
868
sci_transmit_chars(struct uart_port * port)869 static void sci_transmit_chars(struct uart_port *port)
870 {
871 struct tty_port *tport = &port->state->port;
872 unsigned int stopped = uart_tx_stopped(port);
873 struct sci_port *s = to_sci_port(port);
874 unsigned short status;
875 unsigned short ctrl;
876 int count;
877
878 status = sci_serial_in(port, SCxSR);
879 if (!(status & SCxSR_TDxE(port))) {
880 ctrl = sci_serial_in(port, SCSCR);
881 if (kfifo_is_empty(&tport->xmit_fifo))
882 ctrl &= ~SCSCR_TIE;
883 else
884 ctrl |= SCSCR_TIE;
885 sci_serial_out(port, SCSCR, ctrl);
886 return;
887 }
888
889 count = sci_txroom(port);
890
891 do {
892 unsigned char c;
893
894 if (port->x_char) {
895 c = port->x_char;
896 port->x_char = 0;
897 } else if (stopped || !kfifo_get(&tport->xmit_fifo, &c)) {
898 if (port->type == PORT_SCI &&
899 kfifo_is_empty(&tport->xmit_fifo)) {
900 ctrl = sci_serial_in(port, SCSCR);
901 ctrl &= ~SCSCR_TE;
902 sci_serial_out(port, SCSCR, ctrl);
903 return;
904 }
905 break;
906 }
907
908 sci_serial_out(port, SCxTDR, c);
909 s->tx_occurred = true;
910
911 port->icount.tx++;
912 } while (--count > 0);
913
914 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
915
916 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
917 uart_write_wakeup(port);
918 if (kfifo_is_empty(&tport->xmit_fifo)) {
919 if (port->type == PORT_SCI) {
920 ctrl = sci_serial_in(port, SCSCR);
921 ctrl &= ~SCSCR_TIE;
922 ctrl |= SCSCR_TEIE;
923 sci_serial_out(port, SCSCR, ctrl);
924 }
925
926 sci_stop_tx(port);
927 }
928 }
929
sci_receive_chars(struct uart_port * port)930 static void sci_receive_chars(struct uart_port *port)
931 {
932 struct tty_port *tport = &port->state->port;
933 int i, count, copied = 0;
934 unsigned short status;
935 unsigned char flag;
936
937 status = sci_serial_in(port, SCxSR);
938 if (!(status & SCxSR_RDxF(port)))
939 return;
940
941 while (1) {
942 /* Don't copy more bytes than there is room for in the buffer */
943 count = tty_buffer_request_room(tport, sci_rxfill(port));
944
945 /* If for any reason we can't copy more data, we're done! */
946 if (count == 0)
947 break;
948
949 if (port->type == PORT_SCI) {
950 char c = sci_serial_in(port, SCxRDR);
951 if (uart_handle_sysrq_char(port, c))
952 count = 0;
953 else
954 tty_insert_flip_char(tport, c, TTY_NORMAL);
955 } else {
956 for (i = 0; i < count; i++) {
957 char c;
958
959 if (port->type == PORT_SCIF ||
960 port->type == PORT_HSCIF) {
961 status = sci_serial_in(port, SCxSR);
962 c = sci_serial_in(port, SCxRDR);
963 } else {
964 c = sci_serial_in(port, SCxRDR);
965 status = sci_serial_in(port, SCxSR);
966 }
967 if (uart_handle_sysrq_char(port, c)) {
968 count--; i--;
969 continue;
970 }
971
972 /* Store data and status */
973 if (status & SCxSR_FER(port)) {
974 flag = TTY_FRAME;
975 port->icount.frame++;
976 } else if (status & SCxSR_PER(port)) {
977 flag = TTY_PARITY;
978 port->icount.parity++;
979 } else
980 flag = TTY_NORMAL;
981
982 tty_insert_flip_char(tport, c, flag);
983 }
984 }
985
986 sci_serial_in(port, SCxSR); /* dummy read */
987 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
988
989 copied += count;
990 port->icount.rx += count;
991 }
992
993 if (copied) {
994 /* Tell the rest of the system the news. New characters! */
995 tty_flip_buffer_push(tport);
996 } else {
997 /* TTY buffers full; read from RX reg to prevent lockup */
998 sci_serial_in(port, SCxRDR);
999 sci_serial_in(port, SCxSR); /* dummy read */
1000 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1001 }
1002 }
1003
sci_handle_errors(struct uart_port * port)1004 static int sci_handle_errors(struct uart_port *port)
1005 {
1006 int copied = 0;
1007 unsigned short status = sci_serial_in(port, SCxSR);
1008 struct tty_port *tport = &port->state->port;
1009 struct sci_port *s = to_sci_port(port);
1010
1011 /* Handle overruns */
1012 if (status & s->params->overrun_mask) {
1013 port->icount.overrun++;
1014
1015 /* overrun error */
1016 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
1017 copied++;
1018 }
1019
1020 if (status & SCxSR_FER(port)) {
1021 /* frame error */
1022 port->icount.frame++;
1023
1024 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
1025 copied++;
1026 }
1027
1028 if (status & SCxSR_PER(port)) {
1029 /* parity error */
1030 port->icount.parity++;
1031
1032 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
1033 copied++;
1034 }
1035
1036 if (copied)
1037 tty_flip_buffer_push(tport);
1038
1039 return copied;
1040 }
1041
sci_handle_fifo_overrun(struct uart_port * port)1042 static int sci_handle_fifo_overrun(struct uart_port *port)
1043 {
1044 struct tty_port *tport = &port->state->port;
1045 struct sci_port *s = to_sci_port(port);
1046 const struct plat_sci_reg *reg;
1047 int copied = 0;
1048 u16 status;
1049
1050 reg = sci_getreg(port, s->params->overrun_reg);
1051 if (!reg->size)
1052 return 0;
1053
1054 status = sci_serial_in(port, s->params->overrun_reg);
1055 if (status & s->params->overrun_mask) {
1056 status &= ~s->params->overrun_mask;
1057 sci_serial_out(port, s->params->overrun_reg, status);
1058
1059 port->icount.overrun++;
1060
1061 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
1062 tty_flip_buffer_push(tport);
1063 copied++;
1064 }
1065
1066 return copied;
1067 }
1068
sci_handle_breaks(struct uart_port * port)1069 static int sci_handle_breaks(struct uart_port *port)
1070 {
1071 int copied = 0;
1072 unsigned short status = sci_serial_in(port, SCxSR);
1073 struct tty_port *tport = &port->state->port;
1074
1075 if (uart_handle_break(port))
1076 return 0;
1077
1078 if (status & SCxSR_BRK(port)) {
1079 port->icount.brk++;
1080
1081 /* Notify of BREAK */
1082 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
1083 copied++;
1084 }
1085
1086 if (copied)
1087 tty_flip_buffer_push(tport);
1088
1089 copied += sci_handle_fifo_overrun(port);
1090
1091 return copied;
1092 }
1093
scif_set_rtrg(struct uart_port * port,int rx_trig)1094 static int scif_set_rtrg(struct uart_port *port, int rx_trig)
1095 {
1096 unsigned int bits;
1097
1098 if (rx_trig >= port->fifosize)
1099 rx_trig = port->fifosize - 1;
1100 if (rx_trig < 1)
1101 rx_trig = 1;
1102
1103 /* HSCIF can be set to an arbitrary level. */
1104 if (sci_getreg(port, HSRTRGR)->size) {
1105 sci_serial_out(port, HSRTRGR, rx_trig);
1106 return rx_trig;
1107 }
1108
1109 switch (port->type) {
1110 case PORT_SCIF:
1111 if (rx_trig < 4) {
1112 bits = 0;
1113 rx_trig = 1;
1114 } else if (rx_trig < 8) {
1115 bits = SCFCR_RTRG0;
1116 rx_trig = 4;
1117 } else if (rx_trig < 14) {
1118 bits = SCFCR_RTRG1;
1119 rx_trig = 8;
1120 } else {
1121 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1122 rx_trig = 14;
1123 }
1124 break;
1125 case PORT_SCIFA:
1126 case PORT_SCIFB:
1127 if (rx_trig < 16) {
1128 bits = 0;
1129 rx_trig = 1;
1130 } else if (rx_trig < 32) {
1131 bits = SCFCR_RTRG0;
1132 rx_trig = 16;
1133 } else if (rx_trig < 48) {
1134 bits = SCFCR_RTRG1;
1135 rx_trig = 32;
1136 } else {
1137 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1138 rx_trig = 48;
1139 }
1140 break;
1141 default:
1142 WARN(1, "unknown FIFO configuration");
1143 return 1;
1144 }
1145
1146 sci_serial_out(port, SCFCR,
1147 (sci_serial_in(port, SCFCR) &
1148 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits);
1149
1150 return rx_trig;
1151 }
1152
scif_rtrg_enabled(struct uart_port * port)1153 static int scif_rtrg_enabled(struct uart_port *port)
1154 {
1155 if (sci_getreg(port, HSRTRGR)->size)
1156 return sci_serial_in(port, HSRTRGR) != 0;
1157 else
1158 return (sci_serial_in(port, SCFCR) &
1159 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0;
1160 }
1161
rx_fifo_timer_fn(struct timer_list * t)1162 static void rx_fifo_timer_fn(struct timer_list *t)
1163 {
1164 struct sci_port *s = from_timer(s, t, rx_fifo_timer);
1165 struct uart_port *port = &s->port;
1166
1167 dev_dbg(port->dev, "Rx timed out\n");
1168 scif_set_rtrg(port, 1);
1169 }
1170
rx_fifo_trigger_show(struct device * dev,struct device_attribute * attr,char * buf)1171 static ssize_t rx_fifo_trigger_show(struct device *dev,
1172 struct device_attribute *attr, char *buf)
1173 {
1174 struct uart_port *port = dev_get_drvdata(dev);
1175 struct sci_port *sci = to_sci_port(port);
1176
1177 return sprintf(buf, "%d\n", sci->rx_trigger);
1178 }
1179
rx_fifo_trigger_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1180 static ssize_t rx_fifo_trigger_store(struct device *dev,
1181 struct device_attribute *attr,
1182 const char *buf, size_t count)
1183 {
1184 struct uart_port *port = dev_get_drvdata(dev);
1185 struct sci_port *sci = to_sci_port(port);
1186 int ret;
1187 long r;
1188
1189 ret = kstrtol(buf, 0, &r);
1190 if (ret)
1191 return ret;
1192
1193 sci->rx_trigger = scif_set_rtrg(port, r);
1194 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1195 scif_set_rtrg(port, 1);
1196
1197 return count;
1198 }
1199
1200 static DEVICE_ATTR_RW(rx_fifo_trigger);
1201
rx_fifo_timeout_show(struct device * dev,struct device_attribute * attr,char * buf)1202 static ssize_t rx_fifo_timeout_show(struct device *dev,
1203 struct device_attribute *attr,
1204 char *buf)
1205 {
1206 struct uart_port *port = dev_get_drvdata(dev);
1207 struct sci_port *sci = to_sci_port(port);
1208 int v;
1209
1210 if (port->type == PORT_HSCIF)
1211 v = sci->hscif_tot >> HSSCR_TOT_SHIFT;
1212 else
1213 v = sci->rx_fifo_timeout;
1214
1215 return sprintf(buf, "%d\n", v);
1216 }
1217
rx_fifo_timeout_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1218 static ssize_t rx_fifo_timeout_store(struct device *dev,
1219 struct device_attribute *attr,
1220 const char *buf,
1221 size_t count)
1222 {
1223 struct uart_port *port = dev_get_drvdata(dev);
1224 struct sci_port *sci = to_sci_port(port);
1225 int ret;
1226 long r;
1227
1228 ret = kstrtol(buf, 0, &r);
1229 if (ret)
1230 return ret;
1231
1232 if (port->type == PORT_HSCIF) {
1233 if (r < 0 || r > 3)
1234 return -EINVAL;
1235 sci->hscif_tot = r << HSSCR_TOT_SHIFT;
1236 } else {
1237 sci->rx_fifo_timeout = r;
1238 scif_set_rtrg(port, 1);
1239 if (r > 0)
1240 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0);
1241 }
1242
1243 return count;
1244 }
1245
1246 static DEVICE_ATTR_RW(rx_fifo_timeout);
1247
1248
1249 #ifdef CONFIG_SERIAL_SH_SCI_DMA
sci_dma_tx_complete(void * arg)1250 static void sci_dma_tx_complete(void *arg)
1251 {
1252 struct sci_port *s = arg;
1253 struct uart_port *port = &s->port;
1254 struct tty_port *tport = &port->state->port;
1255 unsigned long flags;
1256
1257 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1258
1259 uart_port_lock_irqsave(port, &flags);
1260
1261 uart_xmit_advance(port, s->tx_dma_len);
1262
1263 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
1264 uart_write_wakeup(port);
1265
1266 s->tx_occurred = true;
1267
1268 if (!kfifo_is_empty(&tport->xmit_fifo)) {
1269 s->cookie_tx = 0;
1270 schedule_work(&s->work_tx);
1271 } else {
1272 s->cookie_tx = -EINVAL;
1273 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1274 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1275 u16 ctrl = sci_serial_in(port, SCSCR);
1276 sci_serial_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1277 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1278 /* Switch irq from DMA to SCIF */
1279 dmaengine_pause(s->chan_tx_saved);
1280 enable_irq(s->irqs[SCIx_TXI_IRQ]);
1281 }
1282 }
1283 }
1284
1285 uart_port_unlock_irqrestore(port, flags);
1286 }
1287
1288 /* Locking: called with port lock held */
sci_dma_rx_push(struct sci_port * s,void * buf,size_t count)1289 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1290 {
1291 struct uart_port *port = &s->port;
1292 struct tty_port *tport = &port->state->port;
1293 int copied;
1294
1295 copied = tty_insert_flip_string(tport, buf, count);
1296 if (copied < count)
1297 port->icount.buf_overrun++;
1298
1299 port->icount.rx += copied;
1300
1301 return copied;
1302 }
1303
sci_dma_rx_find_active(struct sci_port * s)1304 static int sci_dma_rx_find_active(struct sci_port *s)
1305 {
1306 unsigned int i;
1307
1308 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1309 if (s->active_rx == s->cookie_rx[i])
1310 return i;
1311
1312 return -1;
1313 }
1314
1315 /* Must only be called with uart_port_lock taken */
sci_dma_rx_chan_invalidate(struct sci_port * s)1316 static void sci_dma_rx_chan_invalidate(struct sci_port *s)
1317 {
1318 unsigned int i;
1319
1320 s->chan_rx = NULL;
1321 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1322 s->cookie_rx[i] = -EINVAL;
1323 s->active_rx = 0;
1324 }
1325
sci_dma_rx_release(struct sci_port * s)1326 static void sci_dma_rx_release(struct sci_port *s)
1327 {
1328 struct dma_chan *chan = s->chan_rx_saved;
1329 struct uart_port *port = &s->port;
1330 unsigned long flags;
1331
1332 uart_port_lock_irqsave(port, &flags);
1333 s->chan_rx_saved = NULL;
1334 sci_dma_rx_chan_invalidate(s);
1335 uart_port_unlock_irqrestore(port, flags);
1336
1337 dmaengine_terminate_sync(chan);
1338 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1339 sg_dma_address(&s->sg_rx[0]));
1340 dma_release_channel(chan);
1341 }
1342
start_hrtimer_us(struct hrtimer * hrt,unsigned long usec)1343 static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec)
1344 {
1345 long sec = usec / 1000000;
1346 long nsec = (usec % 1000000) * 1000;
1347 ktime_t t = ktime_set(sec, nsec);
1348
1349 hrtimer_start(hrt, t, HRTIMER_MODE_REL);
1350 }
1351
sci_dma_rx_reenable_irq(struct sci_port * s)1352 static void sci_dma_rx_reenable_irq(struct sci_port *s)
1353 {
1354 struct uart_port *port = &s->port;
1355 u16 scr;
1356
1357 /* Direct new serial port interrupts back to CPU */
1358 scr = sci_serial_in(port, SCSCR);
1359 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1360 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1361 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1362 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE)
1363 scif_set_rtrg(port, s->rx_trigger);
1364 else
1365 scr &= ~SCSCR_RDRQE;
1366 }
1367 sci_serial_out(port, SCSCR, scr | SCSCR_RIE);
1368 }
1369
sci_dma_rx_complete(void * arg)1370 static void sci_dma_rx_complete(void *arg)
1371 {
1372 struct sci_port *s = arg;
1373 struct dma_chan *chan = s->chan_rx;
1374 struct uart_port *port = &s->port;
1375 struct dma_async_tx_descriptor *desc;
1376 unsigned long flags;
1377 int active, count = 0;
1378
1379 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1380 s->active_rx);
1381
1382 hrtimer_cancel(&s->rx_timer);
1383
1384 uart_port_lock_irqsave(port, &flags);
1385
1386 active = sci_dma_rx_find_active(s);
1387 if (active >= 0)
1388 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1389
1390 if (count)
1391 tty_flip_buffer_push(&port->state->port);
1392
1393 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1394 DMA_DEV_TO_MEM,
1395 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1396 if (!desc)
1397 goto fail;
1398
1399 desc->callback = sci_dma_rx_complete;
1400 desc->callback_param = s;
1401 s->cookie_rx[active] = dmaengine_submit(desc);
1402 if (dma_submit_error(s->cookie_rx[active]))
1403 goto fail;
1404
1405 s->active_rx = s->cookie_rx[!active];
1406
1407 dma_async_issue_pending(chan);
1408
1409 uart_port_unlock_irqrestore(port, flags);
1410 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1411 __func__, s->cookie_rx[active], active, s->active_rx);
1412
1413 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1414
1415 return;
1416
1417 fail:
1418 /* Switch to PIO */
1419 dmaengine_terminate_async(chan);
1420 sci_dma_rx_chan_invalidate(s);
1421 sci_dma_rx_reenable_irq(s);
1422 uart_port_unlock_irqrestore(port, flags);
1423 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1424 }
1425
sci_dma_tx_release(struct sci_port * s)1426 static void sci_dma_tx_release(struct sci_port *s)
1427 {
1428 struct dma_chan *chan = s->chan_tx_saved;
1429
1430 cancel_work_sync(&s->work_tx);
1431 s->chan_tx_saved = s->chan_tx = NULL;
1432 s->cookie_tx = -EINVAL;
1433 dmaengine_terminate_sync(chan);
1434 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1435 DMA_TO_DEVICE);
1436 dma_release_channel(chan);
1437 }
1438
sci_dma_rx_submit(struct sci_port * s,bool port_lock_held)1439 static int sci_dma_rx_submit(struct sci_port *s, bool port_lock_held)
1440 {
1441 struct dma_chan *chan = s->chan_rx;
1442 struct uart_port *port = &s->port;
1443 unsigned long flags;
1444 int i;
1445
1446 for (i = 0; i < 2; i++) {
1447 struct scatterlist *sg = &s->sg_rx[i];
1448 struct dma_async_tx_descriptor *desc;
1449
1450 desc = dmaengine_prep_slave_sg(chan,
1451 sg, 1, DMA_DEV_TO_MEM,
1452 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1453 if (!desc)
1454 goto fail;
1455
1456 desc->callback = sci_dma_rx_complete;
1457 desc->callback_param = s;
1458 s->cookie_rx[i] = dmaengine_submit(desc);
1459 if (dma_submit_error(s->cookie_rx[i]))
1460 goto fail;
1461
1462 }
1463
1464 s->active_rx = s->cookie_rx[0];
1465
1466 dma_async_issue_pending(chan);
1467 return 0;
1468
1469 fail:
1470 /* Switch to PIO */
1471 if (!port_lock_held)
1472 uart_port_lock_irqsave(port, &flags);
1473 if (i)
1474 dmaengine_terminate_async(chan);
1475 sci_dma_rx_chan_invalidate(s);
1476 sci_start_rx(port);
1477 if (!port_lock_held)
1478 uart_port_unlock_irqrestore(port, flags);
1479 return -EAGAIN;
1480 }
1481
sci_dma_tx_work_fn(struct work_struct * work)1482 static void sci_dma_tx_work_fn(struct work_struct *work)
1483 {
1484 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1485 struct dma_async_tx_descriptor *desc;
1486 struct dma_chan *chan = s->chan_tx;
1487 struct uart_port *port = &s->port;
1488 struct tty_port *tport = &port->state->port;
1489 unsigned long flags;
1490 unsigned int tail;
1491 dma_addr_t buf;
1492
1493 /*
1494 * DMA is idle now.
1495 * Port xmit buffer is already mapped, and it is one page... Just adjust
1496 * offsets and lengths. Since it is a circular buffer, we have to
1497 * transmit till the end, and then the rest. Take the port lock to get a
1498 * consistent xmit buffer state.
1499 */
1500 uart_port_lock_irq(port);
1501 s->tx_dma_len = kfifo_out_linear(&tport->xmit_fifo, &tail,
1502 UART_XMIT_SIZE);
1503 buf = s->tx_dma_addr + tail;
1504 if (!s->tx_dma_len) {
1505 /* Transmit buffer has been flushed */
1506 uart_port_unlock_irq(port);
1507 return;
1508 }
1509
1510 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1511 DMA_MEM_TO_DEV,
1512 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1513 if (!desc) {
1514 uart_port_unlock_irq(port);
1515 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1516 goto switch_to_pio;
1517 }
1518
1519 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1520 DMA_TO_DEVICE);
1521
1522 desc->callback = sci_dma_tx_complete;
1523 desc->callback_param = s;
1524 s->cookie_tx = dmaengine_submit(desc);
1525 if (dma_submit_error(s->cookie_tx)) {
1526 uart_port_unlock_irq(port);
1527 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1528 goto switch_to_pio;
1529 }
1530
1531 uart_port_unlock_irq(port);
1532 dev_dbg(port->dev, "%s: %p: %u, cookie %d\n",
1533 __func__, tport->xmit_buf, tail, s->cookie_tx);
1534
1535 dma_async_issue_pending(chan);
1536 return;
1537
1538 switch_to_pio:
1539 uart_port_lock_irqsave(port, &flags);
1540 s->chan_tx = NULL;
1541 sci_start_tx(port);
1542 uart_port_unlock_irqrestore(port, flags);
1543 return;
1544 }
1545
sci_dma_rx_timer_fn(struct hrtimer * t)1546 static enum hrtimer_restart sci_dma_rx_timer_fn(struct hrtimer *t)
1547 {
1548 struct sci_port *s = container_of(t, struct sci_port, rx_timer);
1549 struct dma_chan *chan = s->chan_rx;
1550 struct uart_port *port = &s->port;
1551 struct dma_tx_state state;
1552 enum dma_status status;
1553 unsigned long flags;
1554 unsigned int read;
1555 int active, count;
1556
1557 dev_dbg(port->dev, "DMA Rx timed out\n");
1558
1559 uart_port_lock_irqsave(port, &flags);
1560
1561 active = sci_dma_rx_find_active(s);
1562 if (active < 0) {
1563 uart_port_unlock_irqrestore(port, flags);
1564 return HRTIMER_NORESTART;
1565 }
1566
1567 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1568 if (status == DMA_COMPLETE) {
1569 uart_port_unlock_irqrestore(port, flags);
1570 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1571 s->active_rx, active);
1572
1573 /* Let packet complete handler take care of the packet */
1574 return HRTIMER_NORESTART;
1575 }
1576
1577 dmaengine_pause(chan);
1578
1579 /*
1580 * sometimes DMA transfer doesn't stop even if it is stopped and
1581 * data keeps on coming until transaction is complete so check
1582 * for DMA_COMPLETE again
1583 * Let packet complete handler take care of the packet
1584 */
1585 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1586 if (status == DMA_COMPLETE) {
1587 uart_port_unlock_irqrestore(port, flags);
1588 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1589 return HRTIMER_NORESTART;
1590 }
1591
1592 /* Handle incomplete DMA receive */
1593 dmaengine_terminate_async(s->chan_rx);
1594 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1595
1596 if (read) {
1597 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1598 if (count)
1599 tty_flip_buffer_push(&port->state->port);
1600 }
1601
1602 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1603 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE)
1604 sci_dma_rx_submit(s, true);
1605
1606 sci_dma_rx_reenable_irq(s);
1607
1608 uart_port_unlock_irqrestore(port, flags);
1609
1610 return HRTIMER_NORESTART;
1611 }
1612
sci_request_dma_chan(struct uart_port * port,enum dma_transfer_direction dir)1613 static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1614 enum dma_transfer_direction dir)
1615 {
1616 struct dma_chan *chan;
1617 struct dma_slave_config cfg;
1618 int ret;
1619
1620 chan = dma_request_chan(port->dev, dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1621 if (IS_ERR(chan)) {
1622 dev_dbg(port->dev, "dma_request_chan failed\n");
1623 return NULL;
1624 }
1625
1626 memset(&cfg, 0, sizeof(cfg));
1627 cfg.direction = dir;
1628 cfg.dst_addr = port->mapbase +
1629 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1630 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1631 cfg.src_addr = port->mapbase +
1632 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1633 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1634
1635 ret = dmaengine_slave_config(chan, &cfg);
1636 if (ret) {
1637 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1638 dma_release_channel(chan);
1639 return NULL;
1640 }
1641
1642 return chan;
1643 }
1644
sci_request_dma(struct uart_port * port)1645 static void sci_request_dma(struct uart_port *port)
1646 {
1647 struct sci_port *s = to_sci_port(port);
1648 struct tty_port *tport = &port->state->port;
1649 struct dma_chan *chan;
1650
1651 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1652
1653 /*
1654 * DMA on console may interfere with Kernel log messages which use
1655 * plain putchar(). So, simply don't use it with a console.
1656 */
1657 if (uart_console(port))
1658 return;
1659
1660 if (!port->dev->of_node)
1661 return;
1662
1663 s->cookie_tx = -EINVAL;
1664
1665 /*
1666 * Don't request a dma channel if no channel was specified
1667 * in the device tree.
1668 */
1669 if (!of_property_present(port->dev->of_node, "dmas"))
1670 return;
1671
1672 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV);
1673 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1674 if (chan) {
1675 /* UART circular tx buffer is an aligned page. */
1676 s->tx_dma_addr = dma_map_single(chan->device->dev,
1677 tport->xmit_buf,
1678 UART_XMIT_SIZE,
1679 DMA_TO_DEVICE);
1680 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1681 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1682 dma_release_channel(chan);
1683 } else {
1684 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1685 __func__, UART_XMIT_SIZE,
1686 tport->xmit_buf, &s->tx_dma_addr);
1687
1688 INIT_WORK(&s->work_tx, sci_dma_tx_work_fn);
1689 s->chan_tx_saved = s->chan_tx = chan;
1690 }
1691 }
1692
1693 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM);
1694 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1695 if (chan) {
1696 unsigned int i;
1697 dma_addr_t dma;
1698 void *buf;
1699
1700 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1701 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1702 &dma, GFP_KERNEL);
1703 if (!buf) {
1704 dev_warn(port->dev,
1705 "Failed to allocate Rx dma buffer, using PIO\n");
1706 dma_release_channel(chan);
1707 return;
1708 }
1709
1710 for (i = 0; i < 2; i++) {
1711 struct scatterlist *sg = &s->sg_rx[i];
1712
1713 sg_init_table(sg, 1);
1714 s->rx_buf[i] = buf;
1715 sg_dma_address(sg) = dma;
1716 sg_dma_len(sg) = s->buf_len_rx;
1717
1718 buf += s->buf_len_rx;
1719 dma += s->buf_len_rx;
1720 }
1721
1722 hrtimer_setup(&s->rx_timer, sci_dma_rx_timer_fn, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1723
1724 s->chan_rx_saved = s->chan_rx = chan;
1725
1726 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1727 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE)
1728 sci_dma_rx_submit(s, false);
1729 }
1730 }
1731
sci_free_dma(struct uart_port * port)1732 static void sci_free_dma(struct uart_port *port)
1733 {
1734 struct sci_port *s = to_sci_port(port);
1735
1736 if (s->chan_tx_saved)
1737 sci_dma_tx_release(s);
1738 if (s->chan_rx_saved)
1739 sci_dma_rx_release(s);
1740 }
1741
sci_flush_buffer(struct uart_port * port)1742 static void sci_flush_buffer(struct uart_port *port)
1743 {
1744 struct sci_port *s = to_sci_port(port);
1745
1746 /*
1747 * In uart_flush_buffer(), the xmit circular buffer has just been
1748 * cleared, so we have to reset tx_dma_len accordingly, and stop any
1749 * pending transfers
1750 */
1751 s->tx_dma_len = 0;
1752 if (s->chan_tx) {
1753 dmaengine_terminate_async(s->chan_tx);
1754 s->cookie_tx = -EINVAL;
1755 }
1756 }
1757
sci_dma_check_tx_occurred(struct sci_port * s)1758 static void sci_dma_check_tx_occurred(struct sci_port *s)
1759 {
1760 struct dma_tx_state state;
1761 enum dma_status status;
1762
1763 if (!s->chan_tx)
1764 return;
1765
1766 status = dmaengine_tx_status(s->chan_tx, s->cookie_tx, &state);
1767 if (status == DMA_COMPLETE || status == DMA_IN_PROGRESS)
1768 s->tx_occurred = true;
1769 }
1770 #else /* !CONFIG_SERIAL_SH_SCI_DMA */
sci_request_dma(struct uart_port * port)1771 static inline void sci_request_dma(struct uart_port *port)
1772 {
1773 }
1774
sci_free_dma(struct uart_port * port)1775 static inline void sci_free_dma(struct uart_port *port)
1776 {
1777 }
1778
sci_dma_check_tx_occurred(struct sci_port * s)1779 static void sci_dma_check_tx_occurred(struct sci_port *s)
1780 {
1781 }
1782
1783 #define sci_flush_buffer NULL
1784 #endif /* !CONFIG_SERIAL_SH_SCI_DMA */
1785
sci_rx_interrupt(int irq,void * ptr)1786 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1787 {
1788 struct uart_port *port = ptr;
1789 struct sci_port *s = to_sci_port(port);
1790
1791 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1792 if (s->chan_rx) {
1793 u16 scr = sci_serial_in(port, SCSCR);
1794 u16 ssr = sci_serial_in(port, SCxSR);
1795
1796 /* Disable future Rx interrupts */
1797 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1798 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1799 disable_irq_nosync(s->irqs[SCIx_RXI_IRQ]);
1800 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1801 scif_set_rtrg(port, 1);
1802 scr |= SCSCR_RIE;
1803 } else {
1804 scr |= SCSCR_RDRQE;
1805 }
1806 } else {
1807 if (sci_dma_rx_submit(s, false) < 0)
1808 goto handle_pio;
1809
1810 scr &= ~SCSCR_RIE;
1811 }
1812 sci_serial_out(port, SCSCR, scr);
1813 /* Clear current interrupt */
1814 sci_serial_out(port, SCxSR,
1815 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1816 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n",
1817 jiffies, s->rx_timeout);
1818 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1819
1820 return IRQ_HANDLED;
1821 }
1822
1823 handle_pio:
1824 #endif
1825
1826 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) {
1827 if (!scif_rtrg_enabled(port))
1828 scif_set_rtrg(port, s->rx_trigger);
1829
1830 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP(
1831 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000));
1832 }
1833
1834 /* I think sci_receive_chars has to be called irrespective
1835 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1836 * to be disabled?
1837 */
1838 sci_receive_chars(port);
1839
1840 return IRQ_HANDLED;
1841 }
1842
sci_tx_interrupt(int irq,void * ptr)1843 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1844 {
1845 struct uart_port *port = ptr;
1846 unsigned long flags;
1847
1848 uart_port_lock_irqsave(port, &flags);
1849 sci_transmit_chars(port);
1850 uart_port_unlock_irqrestore(port, flags);
1851
1852 return IRQ_HANDLED;
1853 }
1854
sci_tx_end_interrupt(int irq,void * ptr)1855 static irqreturn_t sci_tx_end_interrupt(int irq, void *ptr)
1856 {
1857 struct uart_port *port = ptr;
1858 unsigned long flags;
1859 unsigned short ctrl;
1860
1861 if (port->type != PORT_SCI)
1862 return sci_tx_interrupt(irq, ptr);
1863
1864 uart_port_lock_irqsave(port, &flags);
1865 ctrl = sci_serial_in(port, SCSCR);
1866 ctrl &= ~(SCSCR_TE | SCSCR_TEIE);
1867 sci_serial_out(port, SCSCR, ctrl);
1868 uart_port_unlock_irqrestore(port, flags);
1869
1870 return IRQ_HANDLED;
1871 }
1872
sci_br_interrupt(int irq,void * ptr)1873 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1874 {
1875 struct uart_port *port = ptr;
1876
1877 /* Handle BREAKs */
1878 sci_handle_breaks(port);
1879
1880 /* drop invalid character received before break was detected */
1881 sci_serial_in(port, SCxRDR);
1882
1883 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1884
1885 return IRQ_HANDLED;
1886 }
1887
sci_er_interrupt(int irq,void * ptr)1888 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1889 {
1890 struct uart_port *port = ptr;
1891 struct sci_port *s = to_sci_port(port);
1892
1893 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) {
1894 /* Break and Error interrupts are muxed */
1895 unsigned short ssr_status = sci_serial_in(port, SCxSR);
1896
1897 /* Break Interrupt */
1898 if (ssr_status & SCxSR_BRK(port))
1899 sci_br_interrupt(irq, ptr);
1900
1901 /* Break only? */
1902 if (!(ssr_status & SCxSR_ERRORS(port)))
1903 return IRQ_HANDLED;
1904 }
1905
1906 /* Handle errors */
1907 if (port->type == PORT_SCI) {
1908 if (sci_handle_errors(port)) {
1909 /* discard character in rx buffer */
1910 sci_serial_in(port, SCxSR);
1911 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1912 }
1913 } else {
1914 sci_handle_fifo_overrun(port);
1915 if (!s->chan_rx)
1916 sci_receive_chars(port);
1917 }
1918
1919 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1920
1921 /* Kick the transmission */
1922 if (!s->chan_tx)
1923 sci_tx_interrupt(irq, ptr);
1924
1925 return IRQ_HANDLED;
1926 }
1927
sci_mpxed_interrupt(int irq,void * ptr)1928 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1929 {
1930 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1931 struct uart_port *port = ptr;
1932 struct sci_port *s = to_sci_port(port);
1933 irqreturn_t ret = IRQ_NONE;
1934
1935 ssr_status = sci_serial_in(port, SCxSR);
1936 scr_status = sci_serial_in(port, SCSCR);
1937 if (s->params->overrun_reg == SCxSR)
1938 orer_status = ssr_status;
1939 else if (sci_getreg(port, s->params->overrun_reg)->size)
1940 orer_status = sci_serial_in(port, s->params->overrun_reg);
1941
1942 err_enabled = scr_status & port_rx_irq_mask(port);
1943
1944 /* Tx Interrupt */
1945 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1946 !s->chan_tx)
1947 ret = sci_tx_interrupt(irq, ptr);
1948
1949 /*
1950 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1951 * DR flags
1952 */
1953 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1954 (scr_status & SCSCR_RIE))
1955 ret = sci_rx_interrupt(irq, ptr);
1956
1957 /* Error Interrupt */
1958 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1959 ret = sci_er_interrupt(irq, ptr);
1960
1961 /* Break Interrupt */
1962 if (s->irqs[SCIx_ERI_IRQ] != s->irqs[SCIx_BRI_IRQ] &&
1963 (ssr_status & SCxSR_BRK(port)) && err_enabled)
1964 ret = sci_br_interrupt(irq, ptr);
1965
1966 /* Overrun Interrupt */
1967 if (orer_status & s->params->overrun_mask) {
1968 sci_handle_fifo_overrun(port);
1969 ret = IRQ_HANDLED;
1970 }
1971
1972 return ret;
1973 }
1974
1975 static const struct sci_irq_desc {
1976 const char *desc;
1977 irq_handler_t handler;
1978 } sci_irq_desc[] = {
1979 /*
1980 * Split out handlers, the default case.
1981 */
1982 [SCIx_ERI_IRQ] = {
1983 .desc = "rx err",
1984 .handler = sci_er_interrupt,
1985 },
1986
1987 [SCIx_RXI_IRQ] = {
1988 .desc = "rx full",
1989 .handler = sci_rx_interrupt,
1990 },
1991
1992 [SCIx_TXI_IRQ] = {
1993 .desc = "tx empty",
1994 .handler = sci_tx_interrupt,
1995 },
1996
1997 [SCIx_BRI_IRQ] = {
1998 .desc = "break",
1999 .handler = sci_br_interrupt,
2000 },
2001
2002 [SCIx_DRI_IRQ] = {
2003 .desc = "rx ready",
2004 .handler = sci_rx_interrupt,
2005 },
2006
2007 [SCIx_TEI_IRQ] = {
2008 .desc = "tx end",
2009 .handler = sci_tx_end_interrupt,
2010 },
2011
2012 /*
2013 * Special muxed handler.
2014 */
2015 [SCIx_MUX_IRQ] = {
2016 .desc = "mux",
2017 .handler = sci_mpxed_interrupt,
2018 },
2019 };
2020
sci_request_irq(struct sci_port * port)2021 static int sci_request_irq(struct sci_port *port)
2022 {
2023 struct uart_port *up = &port->port;
2024 int i, j, w, ret = 0;
2025
2026 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
2027 const struct sci_irq_desc *desc;
2028 int irq;
2029
2030 /* Check if already registered (muxed) */
2031 for (w = 0; w < i; w++)
2032 if (port->irqs[w] == port->irqs[i])
2033 w = i + 1;
2034 if (w > i)
2035 continue;
2036
2037 if (SCIx_IRQ_IS_MUXED(port)) {
2038 i = SCIx_MUX_IRQ;
2039 irq = up->irq;
2040 } else {
2041 irq = port->irqs[i];
2042
2043 /*
2044 * Certain port types won't support all of the
2045 * available interrupt sources.
2046 */
2047 if (unlikely(irq < 0))
2048 continue;
2049 }
2050
2051 desc = sci_irq_desc + i;
2052 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
2053 dev_name(up->dev), desc->desc);
2054 if (!port->irqstr[j]) {
2055 ret = -ENOMEM;
2056 goto out_nomem;
2057 }
2058
2059 ret = request_irq(irq, desc->handler, up->irqflags,
2060 port->irqstr[j], port);
2061 if (unlikely(ret)) {
2062 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
2063 goto out_noirq;
2064 }
2065 }
2066
2067 return 0;
2068
2069 out_noirq:
2070 while (--i >= 0)
2071 free_irq(port->irqs[i], port);
2072
2073 out_nomem:
2074 while (--j >= 0)
2075 kfree(port->irqstr[j]);
2076
2077 return ret;
2078 }
2079
sci_free_irq(struct sci_port * port)2080 static void sci_free_irq(struct sci_port *port)
2081 {
2082 int i, j;
2083
2084 /*
2085 * Intentionally in reverse order so we iterate over the muxed
2086 * IRQ first.
2087 */
2088 for (i = 0; i < SCIx_NR_IRQS; i++) {
2089 int irq = port->irqs[i];
2090
2091 /*
2092 * Certain port types won't support all of the available
2093 * interrupt sources.
2094 */
2095 if (unlikely(irq < 0))
2096 continue;
2097
2098 /* Check if already freed (irq was muxed) */
2099 for (j = 0; j < i; j++)
2100 if (port->irqs[j] == irq)
2101 j = i + 1;
2102 if (j > i)
2103 continue;
2104
2105 free_irq(port->irqs[i], port);
2106 kfree(port->irqstr[i]);
2107
2108 if (SCIx_IRQ_IS_MUXED(port)) {
2109 /* If there's only one IRQ, we're done. */
2110 return;
2111 }
2112 }
2113 }
2114
sci_tx_empty(struct uart_port * port)2115 static unsigned int sci_tx_empty(struct uart_port *port)
2116 {
2117 unsigned short status = sci_serial_in(port, SCxSR);
2118 unsigned short in_tx_fifo = sci_txfill(port);
2119 struct sci_port *s = to_sci_port(port);
2120
2121 sci_dma_check_tx_occurred(s);
2122
2123 if (!s->tx_occurred)
2124 return TIOCSER_TEMT;
2125
2126 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
2127 }
2128
sci_set_rts(struct uart_port * port,bool state)2129 static void sci_set_rts(struct uart_port *port, bool state)
2130 {
2131 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2132 u16 data = sci_serial_in(port, SCPDR);
2133
2134 /* Active low */
2135 if (state)
2136 data &= ~SCPDR_RTSD;
2137 else
2138 data |= SCPDR_RTSD;
2139 sci_serial_out(port, SCPDR, data);
2140
2141 /* RTS# is output */
2142 sci_serial_out(port, SCPCR,
2143 sci_serial_in(port, SCPCR) | SCPCR_RTSC);
2144 } else if (sci_getreg(port, SCSPTR)->size) {
2145 u16 ctrl = sci_serial_in(port, SCSPTR);
2146
2147 /* Active low */
2148 if (state)
2149 ctrl &= ~SCSPTR_RTSDT;
2150 else
2151 ctrl |= SCSPTR_RTSDT;
2152 sci_serial_out(port, SCSPTR, ctrl);
2153 }
2154 }
2155
sci_get_cts(struct uart_port * port)2156 static bool sci_get_cts(struct uart_port *port)
2157 {
2158 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2159 /* Active low */
2160 return !(sci_serial_in(port, SCPDR) & SCPDR_CTSD);
2161 } else if (sci_getreg(port, SCSPTR)->size) {
2162 /* Active low */
2163 return !(sci_serial_in(port, SCSPTR) & SCSPTR_CTSDT);
2164 }
2165
2166 return true;
2167 }
2168
2169 /*
2170 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
2171 * CTS/RTS is supported in hardware by at least one port and controlled
2172 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
2173 * handled via the ->init_pins() op, which is a bit of a one-way street,
2174 * lacking any ability to defer pin control -- this will later be
2175 * converted over to the GPIO framework).
2176 *
2177 * Other modes (such as loopback) are supported generically on certain
2178 * port types, but not others. For these it's sufficient to test for the
2179 * existence of the support register and simply ignore the port type.
2180 */
sci_set_mctrl(struct uart_port * port,unsigned int mctrl)2181 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
2182 {
2183 struct sci_port *s = to_sci_port(port);
2184
2185 if (mctrl & TIOCM_LOOP) {
2186 const struct plat_sci_reg *reg;
2187
2188 /*
2189 * Standard loopback mode for SCFCR ports.
2190 */
2191 reg = sci_getreg(port, SCFCR);
2192 if (reg->size)
2193 sci_serial_out(port, SCFCR,
2194 sci_serial_in(port, SCFCR) | SCFCR_LOOP);
2195 }
2196
2197 mctrl_gpio_set(s->gpios, mctrl);
2198
2199 if (!s->has_rtscts)
2200 return;
2201
2202 if (!(mctrl & TIOCM_RTS)) {
2203 /* Disable Auto RTS */
2204 if (s->cfg->regtype != SCIx_RZV2H_SCIF_REGTYPE)
2205 sci_serial_out(port, SCFCR,
2206 sci_serial_in(port, SCFCR) & ~SCFCR_MCE);
2207
2208 /* Clear RTS */
2209 sci_set_rts(port, 0);
2210 } else if (s->autorts) {
2211 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2212 /* Enable RTS# pin function */
2213 sci_serial_out(port, SCPCR,
2214 sci_serial_in(port, SCPCR) & ~SCPCR_RTSC);
2215 }
2216
2217 /* Enable Auto RTS */
2218 if (s->cfg->regtype != SCIx_RZV2H_SCIF_REGTYPE)
2219 sci_serial_out(port, SCFCR,
2220 sci_serial_in(port, SCFCR) | SCFCR_MCE);
2221 } else {
2222 /* Set RTS */
2223 sci_set_rts(port, 1);
2224 }
2225 }
2226
sci_get_mctrl(struct uart_port * port)2227 static unsigned int sci_get_mctrl(struct uart_port *port)
2228 {
2229 struct sci_port *s = to_sci_port(port);
2230 struct mctrl_gpios *gpios = s->gpios;
2231 unsigned int mctrl = 0;
2232
2233 mctrl_gpio_get(gpios, &mctrl);
2234
2235 /*
2236 * CTS/RTS is handled in hardware when supported, while nothing
2237 * else is wired up.
2238 */
2239 if (s->autorts) {
2240 if (sci_get_cts(port))
2241 mctrl |= TIOCM_CTS;
2242 } else if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)) {
2243 mctrl |= TIOCM_CTS;
2244 }
2245 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR))
2246 mctrl |= TIOCM_DSR;
2247 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD))
2248 mctrl |= TIOCM_CAR;
2249
2250 return mctrl;
2251 }
2252
sci_enable_ms(struct uart_port * port)2253 static void sci_enable_ms(struct uart_port *port)
2254 {
2255 mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
2256 }
2257
sci_break_ctl(struct uart_port * port,int break_state)2258 static void sci_break_ctl(struct uart_port *port, int break_state)
2259 {
2260 unsigned short scscr, scsptr;
2261 unsigned long flags;
2262
2263 /* check whether the port has SCSPTR */
2264 if (!sci_getreg(port, SCSPTR)->size) {
2265 /*
2266 * Not supported by hardware. Most parts couple break and rx
2267 * interrupts together, with break detection always enabled.
2268 */
2269 return;
2270 }
2271
2272 uart_port_lock_irqsave(port, &flags);
2273 scsptr = sci_serial_in(port, SCSPTR);
2274 scscr = sci_serial_in(port, SCSCR);
2275
2276 if (break_state == -1) {
2277 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
2278 scscr &= ~SCSCR_TE;
2279 } else {
2280 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
2281 scscr |= SCSCR_TE;
2282 }
2283
2284 sci_serial_out(port, SCSPTR, scsptr);
2285 sci_serial_out(port, SCSCR, scscr);
2286 uart_port_unlock_irqrestore(port, flags);
2287 }
2288
sci_startup(struct uart_port * port)2289 static int sci_startup(struct uart_port *port)
2290 {
2291 struct sci_port *s = to_sci_port(port);
2292 int ret;
2293
2294 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2295
2296 s->tx_occurred = false;
2297 sci_request_dma(port);
2298
2299 ret = sci_request_irq(s);
2300 if (unlikely(ret < 0)) {
2301 sci_free_dma(port);
2302 return ret;
2303 }
2304
2305 return 0;
2306 }
2307
sci_shutdown(struct uart_port * port)2308 static void sci_shutdown(struct uart_port *port)
2309 {
2310 struct sci_port *s = to_sci_port(port);
2311 unsigned long flags;
2312 u16 scr;
2313
2314 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2315
2316 s->autorts = false;
2317 mctrl_gpio_disable_ms_sync(to_sci_port(port)->gpios);
2318
2319 uart_port_lock_irqsave(port, &flags);
2320 sci_stop_rx(port);
2321 sci_stop_tx(port);
2322 /*
2323 * Stop RX and TX, disable related interrupts, keep clock source
2324 * and HSCIF TOT bits
2325 */
2326 scr = sci_serial_in(port, SCSCR);
2327 sci_serial_out(port, SCSCR,
2328 scr & (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot));
2329 uart_port_unlock_irqrestore(port, flags);
2330
2331 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2332 if (s->chan_rx_saved) {
2333 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
2334 port->line);
2335 hrtimer_cancel(&s->rx_timer);
2336 }
2337 #endif
2338
2339 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0)
2340 timer_delete_sync(&s->rx_fifo_timer);
2341 sci_free_irq(s);
2342 sci_free_dma(port);
2343 }
2344
sci_sck_calc(struct sci_port * s,unsigned int bps,unsigned int * srr)2345 static int sci_sck_calc(struct sci_port *s, unsigned int bps,
2346 unsigned int *srr)
2347 {
2348 unsigned long freq = s->clk_rates[SCI_SCK];
2349 int err, min_err = INT_MAX;
2350 unsigned int sr;
2351
2352 if (s->port.type != PORT_HSCIF)
2353 freq *= 2;
2354
2355 for_each_sr(sr, s) {
2356 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
2357 if (abs(err) >= abs(min_err))
2358 continue;
2359
2360 min_err = err;
2361 *srr = sr - 1;
2362
2363 if (!err)
2364 break;
2365 }
2366
2367 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
2368 *srr + 1);
2369 return min_err;
2370 }
2371
sci_brg_calc(struct sci_port * s,unsigned int bps,unsigned long freq,unsigned int * dlr,unsigned int * srr)2372 static int sci_brg_calc(struct sci_port *s, unsigned int bps,
2373 unsigned long freq, unsigned int *dlr,
2374 unsigned int *srr)
2375 {
2376 int err, min_err = INT_MAX;
2377 unsigned int sr, dl;
2378
2379 if (s->port.type != PORT_HSCIF)
2380 freq *= 2;
2381
2382 for_each_sr(sr, s) {
2383 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
2384 dl = clamp(dl, 1U, 65535U);
2385
2386 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
2387 if (abs(err) >= abs(min_err))
2388 continue;
2389
2390 min_err = err;
2391 *dlr = dl;
2392 *srr = sr - 1;
2393
2394 if (!err)
2395 break;
2396 }
2397
2398 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
2399 min_err, *dlr, *srr + 1);
2400 return min_err;
2401 }
2402
2403 /* calculate sample rate, BRR, and clock select */
sci_scbrr_calc(struct sci_port * s,unsigned int bps,unsigned int * brr,unsigned int * srr,unsigned int * cks)2404 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
2405 unsigned int *brr, unsigned int *srr,
2406 unsigned int *cks)
2407 {
2408 unsigned long freq = s->clk_rates[SCI_FCK];
2409 unsigned int sr, br, prediv, scrate, c;
2410 int err, min_err = INT_MAX;
2411
2412 if (s->port.type != PORT_HSCIF)
2413 freq *= 2;
2414
2415 /*
2416 * Find the combination of sample rate and clock select with the
2417 * smallest deviation from the desired baud rate.
2418 * Prefer high sample rates to maximise the receive margin.
2419 *
2420 * M: Receive margin (%)
2421 * N: Ratio of bit rate to clock (N = sampling rate)
2422 * D: Clock duty (D = 0 to 1.0)
2423 * L: Frame length (L = 9 to 12)
2424 * F: Absolute value of clock frequency deviation
2425 *
2426 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
2427 * (|D - 0.5| / N * (1 + F))|
2428 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
2429 */
2430 for_each_sr(sr, s) {
2431 for (c = 0; c <= 3; c++) {
2432 /* integerized formulas from HSCIF documentation */
2433 prediv = sr << (2 * c + 1);
2434
2435 /*
2436 * We need to calculate:
2437 *
2438 * br = freq / (prediv * bps) clamped to [1..256]
2439 * err = freq / (br * prediv) - bps
2440 *
2441 * Watch out for overflow when calculating the desired
2442 * sampling clock rate!
2443 */
2444 if (bps > UINT_MAX / prediv)
2445 break;
2446
2447 scrate = prediv * bps;
2448 br = DIV_ROUND_CLOSEST(freq, scrate);
2449 br = clamp(br, 1U, 256U);
2450
2451 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
2452 if (abs(err) >= abs(min_err))
2453 continue;
2454
2455 min_err = err;
2456 *brr = br - 1;
2457 *srr = sr - 1;
2458 *cks = c;
2459
2460 if (!err)
2461 goto found;
2462 }
2463 }
2464
2465 found:
2466 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2467 min_err, *brr, *srr + 1, *cks);
2468 return min_err;
2469 }
2470
sci_reset(struct uart_port * port)2471 static void sci_reset(struct uart_port *port)
2472 {
2473 const struct plat_sci_reg *reg;
2474 unsigned int status;
2475 struct sci_port *s = to_sci_port(port);
2476
2477 sci_serial_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */
2478
2479 reg = sci_getreg(port, SCFCR);
2480 if (reg->size)
2481 sci_serial_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2482
2483 sci_clear_SCxSR(port,
2484 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
2485 SCxSR_BREAK_CLEAR(port));
2486 if (sci_getreg(port, SCLSR)->size) {
2487 status = sci_serial_in(port, SCLSR);
2488 status &= ~(SCLSR_TO | SCLSR_ORER);
2489 sci_serial_out(port, SCLSR, status);
2490 }
2491
2492 if (s->rx_trigger > 1) {
2493 if (s->rx_fifo_timeout) {
2494 scif_set_rtrg(port, 1);
2495 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0);
2496 } else {
2497 if (port->type == PORT_SCIFA ||
2498 port->type == PORT_SCIFB)
2499 scif_set_rtrg(port, 1);
2500 else
2501 scif_set_rtrg(port, s->rx_trigger);
2502 }
2503 }
2504 }
2505
sci_set_termios(struct uart_port * port,struct ktermios * termios,const struct ktermios * old)2506 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2507 const struct ktermios *old)
2508 {
2509 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits;
2510 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2511 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
2512 struct sci_port *s = to_sci_port(port);
2513 const struct plat_sci_reg *reg;
2514 int min_err = INT_MAX, err;
2515 unsigned long max_freq = 0;
2516 int best_clk = -1;
2517 unsigned long flags;
2518
2519 if ((termios->c_cflag & CSIZE) == CS7) {
2520 smr_val |= SCSMR_CHR;
2521 } else {
2522 termios->c_cflag &= ~CSIZE;
2523 termios->c_cflag |= CS8;
2524 }
2525 if (termios->c_cflag & PARENB)
2526 smr_val |= SCSMR_PE;
2527 if (termios->c_cflag & PARODD)
2528 smr_val |= SCSMR_PE | SCSMR_ODD;
2529 if (termios->c_cflag & CSTOPB)
2530 smr_val |= SCSMR_STOP;
2531
2532 /*
2533 * earlyprintk comes here early on with port->uartclk set to zero.
2534 * the clock framework is not up and running at this point so here
2535 * we assume that 115200 is the maximum baud rate. please note that
2536 * the baud rate is not programmed during earlyprintk - it is assumed
2537 * that the previous boot loader has enabled required clocks and
2538 * setup the baud rate generator hardware for us already.
2539 */
2540 if (!port->uartclk) {
2541 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2542 goto done;
2543 }
2544
2545 for (i = 0; i < SCI_NUM_CLKS; i++)
2546 max_freq = max(max_freq, s->clk_rates[i]);
2547
2548 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
2549 if (!baud)
2550 goto done;
2551
2552 /*
2553 * There can be multiple sources for the sampling clock. Find the one
2554 * that gives us the smallest deviation from the desired baud rate.
2555 */
2556
2557 /* Optional Undivided External Clock */
2558 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2559 port->type != PORT_SCIFB) {
2560 err = sci_sck_calc(s, baud, &srr1);
2561 if (abs(err) < abs(min_err)) {
2562 best_clk = SCI_SCK;
2563 scr_val = SCSCR_CKE1;
2564 sccks = SCCKS_CKS;
2565 min_err = err;
2566 srr = srr1;
2567 if (!err)
2568 goto done;
2569 }
2570 }
2571
2572 /* Optional BRG Frequency Divided External Clock */
2573 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2574 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2575 &srr1);
2576 if (abs(err) < abs(min_err)) {
2577 best_clk = SCI_SCIF_CLK;
2578 scr_val = SCSCR_CKE1;
2579 sccks = 0;
2580 min_err = err;
2581 dl = dl1;
2582 srr = srr1;
2583 if (!err)
2584 goto done;
2585 }
2586 }
2587
2588 /* Optional BRG Frequency Divided Internal Clock */
2589 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2590 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2591 &srr1);
2592 if (abs(err) < abs(min_err)) {
2593 best_clk = SCI_BRG_INT;
2594 scr_val = SCSCR_CKE1;
2595 sccks = SCCKS_XIN;
2596 min_err = err;
2597 dl = dl1;
2598 srr = srr1;
2599 if (!min_err)
2600 goto done;
2601 }
2602 }
2603
2604 /* Divided Functional Clock using standard Bit Rate Register */
2605 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2606 if (abs(err) < abs(min_err)) {
2607 best_clk = SCI_FCK;
2608 scr_val = 0;
2609 min_err = err;
2610 brr = brr1;
2611 srr = srr1;
2612 cks = cks1;
2613 }
2614
2615 done:
2616 if (best_clk >= 0)
2617 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2618 s->clks[best_clk], baud, min_err);
2619
2620 sci_port_enable(s);
2621
2622 /*
2623 * Program the optional External Baud Rate Generator (BRG) first.
2624 * It controls the mux to select (H)SCK or frequency divided clock.
2625 */
2626 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2627 sci_serial_out(port, SCDL, dl);
2628 sci_serial_out(port, SCCKS, sccks);
2629 }
2630
2631 uart_port_lock_irqsave(port, &flags);
2632
2633 sci_reset(port);
2634
2635 uart_update_timeout(port, termios->c_cflag, baud);
2636
2637 /* byte size and parity */
2638 bits = tty_get_frame_size(termios->c_cflag);
2639
2640 if (sci_getreg(port, SEMR)->size)
2641 sci_serial_out(port, SEMR, 0);
2642
2643 if (best_clk >= 0) {
2644 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
2645 switch (srr + 1) {
2646 case 5: smr_val |= SCSMR_SRC_5; break;
2647 case 7: smr_val |= SCSMR_SRC_7; break;
2648 case 11: smr_val |= SCSMR_SRC_11; break;
2649 case 13: smr_val |= SCSMR_SRC_13; break;
2650 case 16: smr_val |= SCSMR_SRC_16; break;
2651 case 17: smr_val |= SCSMR_SRC_17; break;
2652 case 19: smr_val |= SCSMR_SRC_19; break;
2653 case 27: smr_val |= SCSMR_SRC_27; break;
2654 }
2655 smr_val |= cks;
2656 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot);
2657 sci_serial_out(port, SCSMR, smr_val);
2658 sci_serial_out(port, SCBRR, brr);
2659 if (sci_getreg(port, HSSRR)->size) {
2660 unsigned int hssrr = srr | HSCIF_SRE;
2661 /* Calculate deviation from intended rate at the
2662 * center of the last stop bit in sampling clocks.
2663 */
2664 int last_stop = bits * 2 - 1;
2665 int deviation = DIV_ROUND_CLOSEST(min_err * last_stop *
2666 (int)(srr + 1),
2667 2 * (int)baud);
2668
2669 if (abs(deviation) >= 2) {
2670 /* At least two sampling clocks off at the
2671 * last stop bit; we can increase the error
2672 * margin by shifting the sampling point.
2673 */
2674 int shift = clamp(deviation / 2, -8, 7);
2675
2676 hssrr |= (shift << HSCIF_SRHP_SHIFT) &
2677 HSCIF_SRHP_MASK;
2678 hssrr |= HSCIF_SRDE;
2679 }
2680 sci_serial_out(port, HSSRR, hssrr);
2681 }
2682
2683 /* Wait one bit interval */
2684 udelay((1000000 + (baud - 1)) / baud);
2685 } else {
2686 /* Don't touch the bit rate configuration */
2687 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
2688 smr_val |= sci_serial_in(port, SCSMR) &
2689 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
2690 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot);
2691 sci_serial_out(port, SCSMR, smr_val);
2692 }
2693
2694 sci_init_pins(port, termios->c_cflag);
2695
2696 port->status &= ~UPSTAT_AUTOCTS;
2697 s->autorts = false;
2698 reg = sci_getreg(port, SCFCR);
2699 if (reg->size) {
2700 unsigned short ctrl = sci_serial_in(port, SCFCR);
2701
2702 if ((port->flags & UPF_HARD_FLOW) &&
2703 (termios->c_cflag & CRTSCTS)) {
2704 /* There is no CTS interrupt to restart the hardware */
2705 port->status |= UPSTAT_AUTOCTS;
2706 /* MCE is enabled when RTS is raised */
2707 s->autorts = true;
2708 }
2709
2710 /*
2711 * As we've done a sci_reset() above, ensure we don't
2712 * interfere with the FIFOs while toggling MCE. As the
2713 * reset values could still be set, simply mask them out.
2714 */
2715 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2716
2717 sci_serial_out(port, SCFCR, ctrl);
2718 }
2719 if (port->flags & UPF_HARD_FLOW) {
2720 /* Refresh (Auto) RTS */
2721 sci_set_mctrl(port, port->mctrl);
2722 }
2723
2724 /*
2725 * For SCI, TE (transmit enable) must be set after setting TIE
2726 * (transmit interrupt enable) or in the same instruction to
2727 * start the transmitting process. So skip setting TE here for SCI.
2728 */
2729 if (port->type != PORT_SCI)
2730 scr_val |= SCSCR_TE;
2731 scr_val |= SCSCR_RE | (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0));
2732 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot);
2733 if ((srr + 1 == 5) &&
2734 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
2735 /*
2736 * In asynchronous mode, when the sampling rate is 1/5, first
2737 * received data may become invalid on some SCIFA and SCIFB.
2738 * To avoid this problem wait more than 1 serial data time (1
2739 * bit time x serial data number) after setting SCSCR.RE = 1.
2740 */
2741 udelay(DIV_ROUND_UP(10 * 1000000, baud));
2742 }
2743
2744 /* Calculate delay for 2 DMA buffers (4 FIFO). */
2745 s->rx_frame = (10000 * bits) / (baud / 100);
2746 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2747 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame;
2748 #endif
2749
2750 if ((termios->c_cflag & CREAD) != 0)
2751 sci_start_rx(port);
2752
2753 uart_port_unlock_irqrestore(port, flags);
2754
2755 sci_port_disable(s);
2756
2757 if (UART_ENABLE_MS(port, termios->c_cflag))
2758 sci_enable_ms(port);
2759 }
2760
sci_pm(struct uart_port * port,unsigned int state,unsigned int oldstate)2761 static void sci_pm(struct uart_port *port, unsigned int state,
2762 unsigned int oldstate)
2763 {
2764 struct sci_port *sci_port = to_sci_port(port);
2765
2766 switch (state) {
2767 case UART_PM_STATE_OFF:
2768 sci_port_disable(sci_port);
2769 break;
2770 default:
2771 sci_port_enable(sci_port);
2772 break;
2773 }
2774 }
2775
sci_type(struct uart_port * port)2776 static const char *sci_type(struct uart_port *port)
2777 {
2778 switch (port->type) {
2779 case PORT_IRDA:
2780 return "irda";
2781 case PORT_SCI:
2782 return "sci";
2783 case PORT_SCIF:
2784 return "scif";
2785 case PORT_SCIFA:
2786 return "scifa";
2787 case PORT_SCIFB:
2788 return "scifb";
2789 case PORT_HSCIF:
2790 return "hscif";
2791 }
2792
2793 return NULL;
2794 }
2795
sci_remap_port(struct uart_port * port)2796 static int sci_remap_port(struct uart_port *port)
2797 {
2798 struct sci_port *sport = to_sci_port(port);
2799
2800 /*
2801 * Nothing to do if there's already an established membase.
2802 */
2803 if (port->membase)
2804 return 0;
2805
2806 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2807 port->membase = ioremap(port->mapbase, sport->reg_size);
2808 if (unlikely(!port->membase)) {
2809 dev_err(port->dev, "can't remap port#%d\n", port->line);
2810 return -ENXIO;
2811 }
2812 } else {
2813 /*
2814 * For the simple (and majority of) cases where we don't
2815 * need to do any remapping, just cast the cookie
2816 * directly.
2817 */
2818 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2819 }
2820
2821 return 0;
2822 }
2823
sci_release_port(struct uart_port * port)2824 static void sci_release_port(struct uart_port *port)
2825 {
2826 struct sci_port *sport = to_sci_port(port);
2827
2828 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2829 iounmap(port->membase);
2830 port->membase = NULL;
2831 }
2832
2833 release_mem_region(port->mapbase, sport->reg_size);
2834 }
2835
sci_request_port(struct uart_port * port)2836 static int sci_request_port(struct uart_port *port)
2837 {
2838 struct resource *res;
2839 struct sci_port *sport = to_sci_port(port);
2840 int ret;
2841
2842 res = request_mem_region(port->mapbase, sport->reg_size,
2843 dev_name(port->dev));
2844 if (unlikely(res == NULL)) {
2845 dev_err(port->dev, "request_mem_region failed.");
2846 return -EBUSY;
2847 }
2848
2849 ret = sci_remap_port(port);
2850 if (unlikely(ret != 0)) {
2851 release_resource(res);
2852 return ret;
2853 }
2854
2855 return 0;
2856 }
2857
sci_config_port(struct uart_port * port,int flags)2858 static void sci_config_port(struct uart_port *port, int flags)
2859 {
2860 if (flags & UART_CONFIG_TYPE) {
2861 struct sci_port *sport = to_sci_port(port);
2862
2863 port->type = sport->cfg->type;
2864 sci_request_port(port);
2865 }
2866 }
2867
sci_verify_port(struct uart_port * port,struct serial_struct * ser)2868 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2869 {
2870 if (ser->baud_base < 2400)
2871 /* No paper tape reader for Mitch.. */
2872 return -EINVAL;
2873
2874 return 0;
2875 }
2876
2877 static const struct uart_ops sci_uart_ops = {
2878 .tx_empty = sci_tx_empty,
2879 .set_mctrl = sci_set_mctrl,
2880 .get_mctrl = sci_get_mctrl,
2881 .start_tx = sci_start_tx,
2882 .stop_tx = sci_stop_tx,
2883 .stop_rx = sci_stop_rx,
2884 .enable_ms = sci_enable_ms,
2885 .break_ctl = sci_break_ctl,
2886 .startup = sci_startup,
2887 .shutdown = sci_shutdown,
2888 .flush_buffer = sci_flush_buffer,
2889 .set_termios = sci_set_termios,
2890 .pm = sci_pm,
2891 .type = sci_type,
2892 .release_port = sci_release_port,
2893 .request_port = sci_request_port,
2894 .config_port = sci_config_port,
2895 .verify_port = sci_verify_port,
2896 #ifdef CONFIG_CONSOLE_POLL
2897 .poll_get_char = sci_poll_get_char,
2898 .poll_put_char = sci_poll_put_char,
2899 #endif
2900 };
2901
sci_init_clocks(struct sci_port * sci_port,struct device * dev)2902 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2903 {
2904 const char *clk_names[] = {
2905 [SCI_FCK] = "fck",
2906 [SCI_SCK] = "sck",
2907 [SCI_BRG_INT] = "brg_int",
2908 [SCI_SCIF_CLK] = "scif_clk",
2909 };
2910 struct clk *clk;
2911 unsigned int i;
2912
2913 if (sci_port->cfg->type == PORT_HSCIF)
2914 clk_names[SCI_SCK] = "hsck";
2915
2916 for (i = 0; i < SCI_NUM_CLKS; i++) {
2917 clk = devm_clk_get_optional(dev, clk_names[i]);
2918 if (IS_ERR(clk))
2919 return PTR_ERR(clk);
2920
2921 if (!clk && i == SCI_FCK) {
2922 /*
2923 * Not all SH platforms declare a clock lookup entry
2924 * for SCI devices, in which case we need to get the
2925 * global "peripheral_clk" clock.
2926 */
2927 clk = devm_clk_get(dev, "peripheral_clk");
2928 if (IS_ERR(clk))
2929 return dev_err_probe(dev, PTR_ERR(clk),
2930 "failed to get %s\n",
2931 clk_names[i]);
2932 }
2933
2934 if (!clk)
2935 dev_dbg(dev, "failed to get %s\n", clk_names[i]);
2936 else
2937 dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i],
2938 clk, clk_get_rate(clk));
2939 sci_port->clks[i] = clk;
2940 }
2941 return 0;
2942 }
2943
2944 static const struct sci_port_params *
sci_probe_regmap(const struct plat_sci_port * cfg)2945 sci_probe_regmap(const struct plat_sci_port *cfg)
2946 {
2947 unsigned int regtype;
2948
2949 if (cfg->regtype != SCIx_PROBE_REGTYPE)
2950 return &sci_port_params[cfg->regtype];
2951
2952 switch (cfg->type) {
2953 case PORT_SCI:
2954 regtype = SCIx_SCI_REGTYPE;
2955 break;
2956 case PORT_IRDA:
2957 regtype = SCIx_IRDA_REGTYPE;
2958 break;
2959 case PORT_SCIFA:
2960 regtype = SCIx_SCIFA_REGTYPE;
2961 break;
2962 case PORT_SCIFB:
2963 regtype = SCIx_SCIFB_REGTYPE;
2964 break;
2965 case PORT_SCIF:
2966 /*
2967 * The SH-4 is a bit of a misnomer here, although that's
2968 * where this particular port layout originated. This
2969 * configuration (or some slight variation thereof)
2970 * remains the dominant model for all SCIFs.
2971 */
2972 regtype = SCIx_SH4_SCIF_REGTYPE;
2973 break;
2974 case PORT_HSCIF:
2975 regtype = SCIx_HSCIF_REGTYPE;
2976 break;
2977 default:
2978 pr_err("Can't probe register map for given port\n");
2979 return NULL;
2980 }
2981
2982 return &sci_port_params[regtype];
2983 }
2984
sci_init_single(struct platform_device * dev,struct sci_port * sci_port,unsigned int index,const struct plat_sci_port * p,bool early)2985 static int sci_init_single(struct platform_device *dev,
2986 struct sci_port *sci_port, unsigned int index,
2987 const struct plat_sci_port *p, bool early)
2988 {
2989 struct uart_port *port = &sci_port->port;
2990 const struct resource *res;
2991 unsigned int i;
2992 int ret;
2993
2994 sci_port->cfg = p;
2995
2996 port->ops = &sci_uart_ops;
2997 port->iotype = UPIO_MEM;
2998 port->line = index;
2999 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SH_SCI_CONSOLE);
3000
3001 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
3002 if (res == NULL)
3003 return -ENOMEM;
3004
3005 port->mapbase = res->start;
3006 sci_port->reg_size = resource_size(res);
3007
3008 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) {
3009 if (i)
3010 sci_port->irqs[i] = platform_get_irq_optional(dev, i);
3011 else
3012 sci_port->irqs[i] = platform_get_irq(dev, i);
3013 }
3014
3015 /*
3016 * The fourth interrupt on SCI port is transmit end interrupt, so
3017 * shuffle the interrupts.
3018 */
3019 if (p->type == PORT_SCI)
3020 swap(sci_port->irqs[SCIx_BRI_IRQ], sci_port->irqs[SCIx_TEI_IRQ]);
3021
3022 /* The SCI generates several interrupts. They can be muxed together or
3023 * connected to different interrupt lines. In the muxed case only one
3024 * interrupt resource is specified as there is only one interrupt ID.
3025 * In the non-muxed case, up to 6 interrupt signals might be generated
3026 * from the SCI, however those signals might have their own individual
3027 * interrupt ID numbers, or muxed together with another interrupt.
3028 */
3029 if (sci_port->irqs[0] < 0)
3030 return -ENXIO;
3031
3032 if (sci_port->irqs[1] < 0)
3033 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++)
3034 sci_port->irqs[i] = sci_port->irqs[0];
3035
3036 sci_port->params = sci_probe_regmap(p);
3037 if (unlikely(sci_port->params == NULL))
3038 return -EINVAL;
3039
3040 switch (p->type) {
3041 case PORT_SCIFB:
3042 sci_port->rx_trigger = 48;
3043 break;
3044 case PORT_HSCIF:
3045 sci_port->rx_trigger = 64;
3046 break;
3047 case PORT_SCIFA:
3048 sci_port->rx_trigger = 32;
3049 break;
3050 case PORT_SCIF:
3051 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE)
3052 /* RX triggering not implemented for this IP */
3053 sci_port->rx_trigger = 1;
3054 else
3055 sci_port->rx_trigger = 8;
3056 break;
3057 default:
3058 sci_port->rx_trigger = 1;
3059 break;
3060 }
3061
3062 sci_port->rx_fifo_timeout = 0;
3063 sci_port->hscif_tot = 0;
3064
3065 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
3066 * match the SoC datasheet, this should be investigated. Let platform
3067 * data override the sampling rate for now.
3068 */
3069 sci_port->sampling_rate_mask = p->sampling_rate
3070 ? SCI_SR(p->sampling_rate)
3071 : sci_port->params->sampling_rate_mask;
3072
3073 if (!early) {
3074 ret = sci_init_clocks(sci_port, &dev->dev);
3075 if (ret < 0)
3076 return ret;
3077 }
3078
3079 port->type = p->type;
3080 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags;
3081 port->fifosize = sci_port->params->fifosize;
3082
3083 if (port->type == PORT_SCI && !dev->dev.of_node) {
3084 if (sci_port->reg_size >= 0x20)
3085 port->regshift = 2;
3086 else
3087 port->regshift = 1;
3088 }
3089
3090 /*
3091 * The UART port needs an IRQ value, so we peg this to the RX IRQ
3092 * for the multi-IRQ ports, which is where we are primarily
3093 * concerned with the shutdown path synchronization.
3094 *
3095 * For the muxed case there's nothing more to do.
3096 */
3097 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
3098 port->irqflags = 0;
3099
3100 return 0;
3101 }
3102
3103 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
3104 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
serial_console_putchar(struct uart_port * port,unsigned char ch)3105 static void serial_console_putchar(struct uart_port *port, unsigned char ch)
3106 {
3107 sci_poll_put_char(port, ch);
3108 }
3109
3110 /*
3111 * Print a string to the serial port trying not to disturb
3112 * any possible real use of the port...
3113 */
serial_console_write(struct console * co,const char * s,unsigned count)3114 static void serial_console_write(struct console *co, const char *s,
3115 unsigned count)
3116 {
3117 struct sci_port *sci_port = &sci_ports[co->index];
3118 struct uart_port *port = &sci_port->port;
3119 unsigned short bits, ctrl, ctrl_temp;
3120 unsigned long flags;
3121 int locked = 1;
3122
3123 if (port->sysrq)
3124 locked = 0;
3125 else if (oops_in_progress)
3126 locked = uart_port_trylock_irqsave(port, &flags);
3127 else
3128 uart_port_lock_irqsave(port, &flags);
3129
3130 /* first save SCSCR then disable interrupts, keep clock source */
3131 ctrl = sci_serial_in(port, SCSCR);
3132 ctrl_temp = SCSCR_RE | SCSCR_TE |
3133 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
3134 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
3135 sci_serial_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot);
3136
3137 uart_console_write(port, s, count, serial_console_putchar);
3138
3139 /* wait until fifo is empty and last bit has been transmitted */
3140 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
3141 while ((sci_serial_in(port, SCxSR) & bits) != bits)
3142 cpu_relax();
3143
3144 /* restore the SCSCR */
3145 sci_serial_out(port, SCSCR, ctrl);
3146
3147 if (locked)
3148 uart_port_unlock_irqrestore(port, flags);
3149 }
3150
serial_console_setup(struct console * co,char * options)3151 static int serial_console_setup(struct console *co, char *options)
3152 {
3153 struct sci_port *sci_port;
3154 struct uart_port *port;
3155 int baud = 115200;
3156 int bits = 8;
3157 int parity = 'n';
3158 int flow = 'n';
3159 int ret;
3160
3161 /*
3162 * Refuse to handle any bogus ports.
3163 */
3164 if (co->index < 0 || co->index >= SCI_NPORTS)
3165 return -ENODEV;
3166
3167 sci_port = &sci_ports[co->index];
3168 port = &sci_port->port;
3169
3170 /*
3171 * Refuse to handle uninitialized ports.
3172 */
3173 if (!port->ops)
3174 return -ENODEV;
3175
3176 ret = sci_remap_port(port);
3177 if (unlikely(ret != 0))
3178 return ret;
3179
3180 if (options)
3181 uart_parse_options(options, &baud, &parity, &bits, &flow);
3182
3183 return uart_set_options(port, co, baud, parity, bits, flow);
3184 }
3185
3186 static struct console serial_console = {
3187 .name = "ttySC",
3188 .device = uart_console_device,
3189 .write = serial_console_write,
3190 .setup = serial_console_setup,
3191 .flags = CON_PRINTBUFFER,
3192 .index = -1,
3193 .data = &sci_uart_driver,
3194 };
3195
3196 #ifdef CONFIG_SUPERH
3197 static char early_serial_buf[32];
3198
early_serial_console_setup(struct console * co,char * options)3199 static int early_serial_console_setup(struct console *co, char *options)
3200 {
3201 /*
3202 * This early console is always registered using the earlyprintk=
3203 * parameter, which does not call add_preferred_console(). Thus
3204 * @options is always NULL and the options for this early console
3205 * are passed using a custom buffer.
3206 */
3207 WARN_ON(options);
3208
3209 return serial_console_setup(co, early_serial_buf);
3210 }
3211
3212 static struct console early_serial_console = {
3213 .name = "early_ttySC",
3214 .write = serial_console_write,
3215 .setup = early_serial_console_setup,
3216 .flags = CON_PRINTBUFFER,
3217 .index = -1,
3218 };
3219
sci_probe_earlyprintk(struct platform_device * pdev)3220 static int sci_probe_earlyprintk(struct platform_device *pdev)
3221 {
3222 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
3223
3224 if (early_serial_console.data)
3225 return -EEXIST;
3226
3227 early_serial_console.index = pdev->id;
3228
3229 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
3230
3231 if (!strstr(early_serial_buf, "keep"))
3232 early_serial_console.flags |= CON_BOOT;
3233
3234 register_console(&early_serial_console);
3235 return 0;
3236 }
3237 #endif
3238
3239 #define SCI_CONSOLE (&serial_console)
3240
3241 #else
sci_probe_earlyprintk(struct platform_device * pdev)3242 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
3243 {
3244 return -EINVAL;
3245 }
3246
3247 #define SCI_CONSOLE NULL
3248
3249 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
3250
3251 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
3252
3253 static DEFINE_MUTEX(sci_uart_registration_lock);
3254 static struct uart_driver sci_uart_driver = {
3255 .owner = THIS_MODULE,
3256 .driver_name = "sci",
3257 .dev_name = "ttySC",
3258 .major = SCI_MAJOR,
3259 .minor = SCI_MINOR_START,
3260 .nr = SCI_NPORTS,
3261 .cons = SCI_CONSOLE,
3262 };
3263
sci_remove(struct platform_device * dev)3264 static void sci_remove(struct platform_device *dev)
3265 {
3266 struct sci_port *port = platform_get_drvdata(dev);
3267 unsigned int type = port->port.type; /* uart_remove_... clears it */
3268
3269 sci_ports_in_use &= ~BIT(port->port.line);
3270 uart_remove_one_port(&sci_uart_driver, &port->port);
3271
3272 if (port->port.fifosize > 1)
3273 device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger);
3274 if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF)
3275 device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout);
3276 }
3277
3278
3279 #define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype))
3280 #define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16)
3281 #define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff)
3282
3283 static const struct of_device_id of_sci_match[] __maybe_unused = {
3284 /* SoC-specific types */
3285 {
3286 .compatible = "renesas,scif-r7s72100",
3287 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
3288 },
3289 {
3290 .compatible = "renesas,scif-r7s9210",
3291 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE),
3292 },
3293 {
3294 .compatible = "renesas,scif-r9a07g044",
3295 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE),
3296 },
3297 {
3298 .compatible = "renesas,scif-r9a09g057",
3299 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZV2H_SCIF_REGTYPE),
3300 },
3301 /* Family-specific types */
3302 {
3303 .compatible = "renesas,rcar-gen1-scif",
3304 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3305 }, {
3306 .compatible = "renesas,rcar-gen2-scif",
3307 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3308 }, {
3309 .compatible = "renesas,rcar-gen3-scif",
3310 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3311 }, {
3312 .compatible = "renesas,rcar-gen4-scif",
3313 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3314 },
3315 /* Generic types */
3316 {
3317 .compatible = "renesas,scif",
3318 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
3319 }, {
3320 .compatible = "renesas,scifa",
3321 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
3322 }, {
3323 .compatible = "renesas,scifb",
3324 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
3325 }, {
3326 .compatible = "renesas,hscif",
3327 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
3328 }, {
3329 .compatible = "renesas,sci",
3330 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
3331 }, {
3332 /* Terminator */
3333 },
3334 };
3335 MODULE_DEVICE_TABLE(of, of_sci_match);
3336
sci_reset_control_assert(void * data)3337 static void sci_reset_control_assert(void *data)
3338 {
3339 reset_control_assert(data);
3340 }
3341
sci_parse_dt(struct platform_device * pdev,unsigned int * dev_id)3342 static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
3343 unsigned int *dev_id)
3344 {
3345 struct device_node *np = pdev->dev.of_node;
3346 struct reset_control *rstc;
3347 struct plat_sci_port *p;
3348 struct sci_port *sp;
3349 const void *data;
3350 int id, ret;
3351
3352 if (!IS_ENABLED(CONFIG_OF) || !np)
3353 return ERR_PTR(-EINVAL);
3354
3355 data = of_device_get_match_data(&pdev->dev);
3356
3357 rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
3358 if (IS_ERR(rstc))
3359 return ERR_PTR(dev_err_probe(&pdev->dev, PTR_ERR(rstc),
3360 "failed to get reset ctrl\n"));
3361
3362 ret = reset_control_deassert(rstc);
3363 if (ret) {
3364 dev_err(&pdev->dev, "failed to deassert reset %d\n", ret);
3365 return ERR_PTR(ret);
3366 }
3367
3368 ret = devm_add_action_or_reset(&pdev->dev, sci_reset_control_assert, rstc);
3369 if (ret) {
3370 dev_err(&pdev->dev, "failed to register assert devm action, %d\n",
3371 ret);
3372 return ERR_PTR(ret);
3373 }
3374
3375 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
3376 if (!p)
3377 return ERR_PTR(-ENOMEM);
3378
3379 /* Get the line number from the aliases node. */
3380 id = of_alias_get_id(np, "serial");
3381 if (id < 0 && ~sci_ports_in_use)
3382 id = ffz(sci_ports_in_use);
3383 if (id < 0) {
3384 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
3385 return ERR_PTR(-EINVAL);
3386 }
3387 if (id >= ARRAY_SIZE(sci_ports)) {
3388 dev_err(&pdev->dev, "serial%d out of range\n", id);
3389 return ERR_PTR(-EINVAL);
3390 }
3391
3392 sp = &sci_ports[id];
3393 sp->rstc = rstc;
3394 *dev_id = id;
3395
3396 p->type = SCI_OF_TYPE(data);
3397 p->regtype = SCI_OF_REGTYPE(data);
3398
3399 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts");
3400
3401 return p;
3402 }
3403
sci_probe_single(struct platform_device * dev,unsigned int index,struct plat_sci_port * p,struct sci_port * sciport,struct resource * sci_res)3404 static int sci_probe_single(struct platform_device *dev,
3405 unsigned int index,
3406 struct plat_sci_port *p,
3407 struct sci_port *sciport,
3408 struct resource *sci_res)
3409 {
3410 int ret;
3411
3412 /* Sanity check */
3413 if (unlikely(index >= SCI_NPORTS)) {
3414 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
3415 index+1, SCI_NPORTS);
3416 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
3417 return -EINVAL;
3418 }
3419 BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8);
3420 if (sci_ports_in_use & BIT(index))
3421 return -EBUSY;
3422
3423 mutex_lock(&sci_uart_registration_lock);
3424 if (!sci_uart_driver.state) {
3425 ret = uart_register_driver(&sci_uart_driver);
3426 if (ret) {
3427 mutex_unlock(&sci_uart_registration_lock);
3428 return ret;
3429 }
3430 }
3431 mutex_unlock(&sci_uart_registration_lock);
3432
3433 ret = sci_init_single(dev, sciport, index, p, false);
3434 if (ret)
3435 return ret;
3436
3437 sciport->port.dev = &dev->dev;
3438 ret = devm_pm_runtime_enable(&dev->dev);
3439 if (ret)
3440 return ret;
3441
3442 sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
3443 if (IS_ERR(sciport->gpios))
3444 return PTR_ERR(sciport->gpios);
3445
3446 if (sciport->has_rtscts) {
3447 if (mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_CTS) ||
3448 mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_RTS)) {
3449 dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
3450 return -EINVAL;
3451 }
3452 sciport->port.flags |= UPF_HARD_FLOW;
3453 }
3454
3455 if (sci_uart_earlycon && sci_ports[0].port.mapbase == sci_res->start) {
3456 /*
3457 * In case:
3458 * - this is the earlycon port (mapped on index 0 in sci_ports[]) and
3459 * - it now maps to an alias other than zero and
3460 * - the earlycon is still alive (e.g., "earlycon keep_bootcon" is
3461 * available in bootargs)
3462 *
3463 * we need to avoid disabling clocks and PM domains through the runtime
3464 * PM APIs called in __device_attach(). For this, increment the runtime
3465 * PM reference counter (the clocks and PM domains were already enabled
3466 * by the bootloader). Otherwise the earlycon may access the HW when it
3467 * has no clocks enabled leading to failures (infinite loop in
3468 * sci_poll_put_char()).
3469 */
3470 pm_runtime_get_noresume(&dev->dev);
3471
3472 /*
3473 * Skip cleanup the sci_port[0] in early_console_exit(), this
3474 * port is the same as the earlycon one.
3475 */
3476 sci_uart_earlycon_dev_probing = true;
3477 }
3478
3479 return uart_add_one_port(&sci_uart_driver, &sciport->port);
3480 }
3481
sci_probe(struct platform_device * dev)3482 static int sci_probe(struct platform_device *dev)
3483 {
3484 struct plat_sci_port *p;
3485 struct resource *res;
3486 struct sci_port *sp;
3487 unsigned int dev_id;
3488 int ret;
3489
3490 /*
3491 * If we've come here via earlyprintk initialization, head off to
3492 * the special early probe. We don't have sufficient device state
3493 * to make it beyond this yet.
3494 */
3495 #ifdef CONFIG_SUPERH
3496 if (is_sh_early_platform_device(dev))
3497 return sci_probe_earlyprintk(dev);
3498 #endif
3499
3500 if (dev->dev.of_node) {
3501 p = sci_parse_dt(dev, &dev_id);
3502 if (IS_ERR(p))
3503 return PTR_ERR(p);
3504 } else {
3505 p = dev->dev.platform_data;
3506 if (p == NULL) {
3507 dev_err(&dev->dev, "no platform data supplied\n");
3508 return -EINVAL;
3509 }
3510
3511 dev_id = dev->id;
3512 }
3513
3514 sp = &sci_ports[dev_id];
3515
3516 /*
3517 * In case:
3518 * - the probed port alias is zero (as the one used by earlycon), and
3519 * - the earlycon is still active (e.g., "earlycon keep_bootcon" in
3520 * bootargs)
3521 *
3522 * defer the probe of this serial. This is a debug scenario and the user
3523 * must be aware of it.
3524 *
3525 * Except when the probed port is the same as the earlycon port.
3526 */
3527
3528 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
3529 if (!res)
3530 return -ENODEV;
3531
3532 if (sci_uart_earlycon && sp == &sci_ports[0] && sp->port.mapbase != res->start)
3533 return dev_err_probe(&dev->dev, -EBUSY, "sci_port[0] is used by earlycon!\n");
3534
3535 platform_set_drvdata(dev, sp);
3536
3537 ret = sci_probe_single(dev, dev_id, p, sp, res);
3538 if (ret)
3539 return ret;
3540
3541 if (sp->port.fifosize > 1) {
3542 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_trigger);
3543 if (ret)
3544 return ret;
3545 }
3546 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB ||
3547 sp->port.type == PORT_HSCIF) {
3548 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout);
3549 if (ret) {
3550 if (sp->port.fifosize > 1) {
3551 device_remove_file(&dev->dev,
3552 &dev_attr_rx_fifo_trigger);
3553 }
3554 return ret;
3555 }
3556 }
3557
3558 #ifdef CONFIG_SH_STANDARD_BIOS
3559 sh_bios_gdb_detach();
3560 #endif
3561
3562 sci_ports_in_use |= BIT(dev_id);
3563 return 0;
3564 }
3565
sci_console_save(struct sci_port * s)3566 static void sci_console_save(struct sci_port *s)
3567 {
3568 struct sci_suspend_regs *regs = &s->suspend_regs;
3569 struct uart_port *port = &s->port;
3570
3571 if (sci_getreg(port, SCDL)->size)
3572 regs->scdl = sci_serial_in(port, SCDL);
3573 if (sci_getreg(port, SCCKS)->size)
3574 regs->sccks = sci_serial_in(port, SCCKS);
3575 if (sci_getreg(port, SCSMR)->size)
3576 regs->scsmr = sci_serial_in(port, SCSMR);
3577 if (sci_getreg(port, SCSCR)->size)
3578 regs->scscr = sci_serial_in(port, SCSCR);
3579 if (sci_getreg(port, SCFCR)->size)
3580 regs->scfcr = sci_serial_in(port, SCFCR);
3581 if (sci_getreg(port, SCSPTR)->size)
3582 regs->scsptr = sci_serial_in(port, SCSPTR);
3583 if (sci_getreg(port, SCBRR)->size)
3584 regs->scbrr = sci_serial_in(port, SCBRR);
3585 if (sci_getreg(port, HSSRR)->size)
3586 regs->hssrr = sci_serial_in(port, HSSRR);
3587 if (sci_getreg(port, SCPCR)->size)
3588 regs->scpcr = sci_serial_in(port, SCPCR);
3589 if (sci_getreg(port, SCPDR)->size)
3590 regs->scpdr = sci_serial_in(port, SCPDR);
3591 if (sci_getreg(port, SEMR)->size)
3592 regs->semr = sci_serial_in(port, SEMR);
3593 }
3594
sci_console_restore(struct sci_port * s)3595 static void sci_console_restore(struct sci_port *s)
3596 {
3597 struct sci_suspend_regs *regs = &s->suspend_regs;
3598 struct uart_port *port = &s->port;
3599
3600 if (sci_getreg(port, SCDL)->size)
3601 sci_serial_out(port, SCDL, regs->scdl);
3602 if (sci_getreg(port, SCCKS)->size)
3603 sci_serial_out(port, SCCKS, regs->sccks);
3604 if (sci_getreg(port, SCSMR)->size)
3605 sci_serial_out(port, SCSMR, regs->scsmr);
3606 if (sci_getreg(port, SCSCR)->size)
3607 sci_serial_out(port, SCSCR, regs->scscr);
3608 if (sci_getreg(port, SCFCR)->size)
3609 sci_serial_out(port, SCFCR, regs->scfcr);
3610 if (sci_getreg(port, SCSPTR)->size)
3611 sci_serial_out(port, SCSPTR, regs->scsptr);
3612 if (sci_getreg(port, SCBRR)->size)
3613 sci_serial_out(port, SCBRR, regs->scbrr);
3614 if (sci_getreg(port, HSSRR)->size)
3615 sci_serial_out(port, HSSRR, regs->hssrr);
3616 if (sci_getreg(port, SCPCR)->size)
3617 sci_serial_out(port, SCPCR, regs->scpcr);
3618 if (sci_getreg(port, SCPDR)->size)
3619 sci_serial_out(port, SCPDR, regs->scpdr);
3620 if (sci_getreg(port, SEMR)->size)
3621 sci_serial_out(port, SEMR, regs->semr);
3622 }
3623
sci_suspend(struct device * dev)3624 static __maybe_unused int sci_suspend(struct device *dev)
3625 {
3626 struct sci_port *sport = dev_get_drvdata(dev);
3627
3628 if (sport) {
3629 uart_suspend_port(&sci_uart_driver, &sport->port);
3630
3631 if (!console_suspend_enabled && uart_console(&sport->port))
3632 sci_console_save(sport);
3633 else
3634 return reset_control_assert(sport->rstc);
3635 }
3636
3637 return 0;
3638 }
3639
sci_resume(struct device * dev)3640 static __maybe_unused int sci_resume(struct device *dev)
3641 {
3642 struct sci_port *sport = dev_get_drvdata(dev);
3643
3644 if (sport) {
3645 if (!console_suspend_enabled && uart_console(&sport->port)) {
3646 sci_console_restore(sport);
3647 } else {
3648 int ret = reset_control_deassert(sport->rstc);
3649
3650 if (ret)
3651 return ret;
3652 }
3653
3654 uart_resume_port(&sci_uart_driver, &sport->port);
3655 }
3656
3657 return 0;
3658 }
3659
3660 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
3661
3662 static struct platform_driver sci_driver = {
3663 .probe = sci_probe,
3664 .remove = sci_remove,
3665 .driver = {
3666 .name = "sh-sci",
3667 .pm = &sci_dev_pm_ops,
3668 .of_match_table = of_match_ptr(of_sci_match),
3669 },
3670 };
3671
sci_init(void)3672 static int __init sci_init(void)
3673 {
3674 pr_info("%s\n", banner);
3675
3676 return platform_driver_register(&sci_driver);
3677 }
3678
sci_exit(void)3679 static void __exit sci_exit(void)
3680 {
3681 platform_driver_unregister(&sci_driver);
3682
3683 if (sci_uart_driver.state)
3684 uart_unregister_driver(&sci_uart_driver);
3685 }
3686
3687 #if defined(CONFIG_SUPERH) && defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
3688 sh_early_platform_init_buffer("earlyprintk", &sci_driver,
3689 early_serial_buf, ARRAY_SIZE(early_serial_buf));
3690 #endif
3691 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
3692 static struct plat_sci_port port_cfg;
3693
early_console_exit(struct console * co)3694 static int early_console_exit(struct console *co)
3695 {
3696 struct sci_port *sci_port = &sci_ports[0];
3697
3698 /*
3699 * Clean the slot used by earlycon. A new SCI device might
3700 * map to this slot.
3701 */
3702 if (!sci_uart_earlycon_dev_probing) {
3703 memset(sci_port, 0, sizeof(*sci_port));
3704 sci_uart_earlycon = false;
3705 }
3706
3707 return 0;
3708 }
3709
early_console_setup(struct earlycon_device * device,int type)3710 static int __init early_console_setup(struct earlycon_device *device,
3711 int type)
3712 {
3713 if (!device->port.membase)
3714 return -ENODEV;
3715
3716 device->port.type = type;
3717 sci_ports[0].port = device->port;
3718 port_cfg.type = type;
3719 sci_ports[0].cfg = &port_cfg;
3720 sci_ports[0].params = sci_probe_regmap(&port_cfg);
3721 sci_uart_earlycon = true;
3722 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR);
3723 sci_serial_out(&sci_ports[0].port, SCSCR,
3724 SCSCR_RE | SCSCR_TE | port_cfg.scscr);
3725
3726 device->con->write = serial_console_write;
3727 device->con->exit = early_console_exit;
3728
3729 return 0;
3730 }
sci_early_console_setup(struct earlycon_device * device,const char * opt)3731 static int __init sci_early_console_setup(struct earlycon_device *device,
3732 const char *opt)
3733 {
3734 return early_console_setup(device, PORT_SCI);
3735 }
scif_early_console_setup(struct earlycon_device * device,const char * opt)3736 static int __init scif_early_console_setup(struct earlycon_device *device,
3737 const char *opt)
3738 {
3739 return early_console_setup(device, PORT_SCIF);
3740 }
rzscifa_early_console_setup(struct earlycon_device * device,const char * opt)3741 static int __init rzscifa_early_console_setup(struct earlycon_device *device,
3742 const char *opt)
3743 {
3744 port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE;
3745 return early_console_setup(device, PORT_SCIF);
3746 }
3747
rzv2hscif_early_console_setup(struct earlycon_device * device,const char * opt)3748 static int __init rzv2hscif_early_console_setup(struct earlycon_device *device,
3749 const char *opt)
3750 {
3751 port_cfg.regtype = SCIx_RZV2H_SCIF_REGTYPE;
3752 return early_console_setup(device, PORT_SCIF);
3753 }
3754
scifa_early_console_setup(struct earlycon_device * device,const char * opt)3755 static int __init scifa_early_console_setup(struct earlycon_device *device,
3756 const char *opt)
3757 {
3758 return early_console_setup(device, PORT_SCIFA);
3759 }
scifb_early_console_setup(struct earlycon_device * device,const char * opt)3760 static int __init scifb_early_console_setup(struct earlycon_device *device,
3761 const char *opt)
3762 {
3763 return early_console_setup(device, PORT_SCIFB);
3764 }
hscif_early_console_setup(struct earlycon_device * device,const char * opt)3765 static int __init hscif_early_console_setup(struct earlycon_device *device,
3766 const char *opt)
3767 {
3768 return early_console_setup(device, PORT_HSCIF);
3769 }
3770
3771 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
3772 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
3773 OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup);
3774 OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044", rzscifa_early_console_setup);
3775 OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a09g057", rzv2hscif_early_console_setup);
3776 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
3777 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
3778 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
3779 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
3780
3781 module_init(sci_init);
3782 module_exit(sci_exit);
3783
3784 MODULE_LICENSE("GPL");
3785 MODULE_ALIAS("platform:sh-sci");
3786 MODULE_AUTHOR("Paul Mundt");
3787 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
3788