1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Rockchip USB2.0 PHY with Innosilicon IP block driver
4 *
5 * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd
6 */
7
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
10 #include <linux/delay.h>
11 #include <linux/extcon-provider.h>
12 #include <linux/interrupt.h>
13 #include <linux/io.h>
14 #include <linux/gpio/consumer.h>
15 #include <linux/jiffies.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/mutex.h>
19 #include <linux/of.h>
20 #include <linux/of_irq.h>
21 #include <linux/phy/phy.h>
22 #include <linux/platform_device.h>
23 #include <linux/power_supply.h>
24 #include <linux/regmap.h>
25 #include <linux/reset.h>
26 #include <linux/mfd/syscon.h>
27 #include <linux/usb/of.h>
28 #include <linux/usb/otg.h>
29
30 #define BIT_WRITEABLE_SHIFT 16
31 #define SCHEDULE_DELAY (60 * HZ)
32 #define OTG_SCHEDULE_DELAY (2 * HZ)
33
34 struct rockchip_usb2phy;
35
36 enum rockchip_usb2phy_port_id {
37 USB2PHY_PORT_OTG,
38 USB2PHY_PORT_HOST,
39 USB2PHY_NUM_PORTS,
40 };
41
42 enum rockchip_usb2phy_host_state {
43 PHY_STATE_HS_ONLINE = 0,
44 PHY_STATE_DISCONNECT = 1,
45 PHY_STATE_CONNECT = 2,
46 PHY_STATE_FS_LS_ONLINE = 4,
47 };
48
49 /**
50 * enum usb_chg_state - Different states involved in USB charger detection.
51 * @USB_CHG_STATE_UNDEFINED: USB charger is not connected or detection
52 * process is not yet started.
53 * @USB_CHG_STATE_WAIT_FOR_DCD: Waiting for Data pins contact.
54 * @USB_CHG_STATE_DCD_DONE: Data pin contact is detected.
55 * @USB_CHG_STATE_PRIMARY_DONE: Primary detection is completed (Detects
56 * between SDP and DCP/CDP).
57 * @USB_CHG_STATE_SECONDARY_DONE: Secondary detection is completed (Detects
58 * between DCP and CDP).
59 * @USB_CHG_STATE_DETECTED: USB charger type is determined.
60 */
61 enum usb_chg_state {
62 USB_CHG_STATE_UNDEFINED = 0,
63 USB_CHG_STATE_WAIT_FOR_DCD,
64 USB_CHG_STATE_DCD_DONE,
65 USB_CHG_STATE_PRIMARY_DONE,
66 USB_CHG_STATE_SECONDARY_DONE,
67 USB_CHG_STATE_DETECTED,
68 };
69
70 static const unsigned int rockchip_usb2phy_extcon_cable[] = {
71 EXTCON_USB,
72 EXTCON_USB_HOST,
73 EXTCON_CHG_USB_SDP,
74 EXTCON_CHG_USB_CDP,
75 EXTCON_CHG_USB_DCP,
76 EXTCON_CHG_USB_SLOW,
77 EXTCON_NONE,
78 };
79
80 struct usb2phy_reg {
81 unsigned int offset;
82 unsigned int bitend;
83 unsigned int bitstart;
84 unsigned int disable;
85 unsigned int enable;
86 };
87
88 /**
89 * struct rockchip_chg_det_reg - usb charger detect registers
90 * @cp_det: charging port detected successfully.
91 * @dcp_det: dedicated charging port detected successfully.
92 * @dp_det: assert data pin connect successfully.
93 * @idm_sink_en: open dm sink curren.
94 * @idp_sink_en: open dp sink current.
95 * @idp_src_en: open dm source current.
96 * @rdm_pdwn_en: open dm pull down resistor.
97 * @vdm_src_en: open dm voltage source.
98 * @vdp_src_en: open dp voltage source.
99 * @opmode: utmi operational mode.
100 */
101 struct rockchip_chg_det_reg {
102 struct usb2phy_reg cp_det;
103 struct usb2phy_reg dcp_det;
104 struct usb2phy_reg dp_det;
105 struct usb2phy_reg idm_sink_en;
106 struct usb2phy_reg idp_sink_en;
107 struct usb2phy_reg idp_src_en;
108 struct usb2phy_reg rdm_pdwn_en;
109 struct usb2phy_reg vdm_src_en;
110 struct usb2phy_reg vdp_src_en;
111 struct usb2phy_reg opmode;
112 };
113
114 /**
115 * struct rockchip_usb2phy_port_cfg - usb-phy port configuration.
116 * @phy_sus: phy suspend register.
117 * @bvalid_det_en: vbus valid rise detection enable register.
118 * @bvalid_det_st: vbus valid rise detection status register.
119 * @bvalid_det_clr: vbus valid rise detection clear register.
120 * @disfall_en: host disconnect fall edge detection enable.
121 * @disfall_st: host disconnect fall edge detection state.
122 * @disfall_clr: host disconnect fall edge detection clear.
123 * @disrise_en: host disconnect rise edge detection enable.
124 * @disrise_st: host disconnect rise edge detection state.
125 * @disrise_clr: host disconnect rise edge detection clear.
126 * @idfall_det_en: id detection enable register, falling edge
127 * @idfall_det_st: id detection state register, falling edge
128 * @idfall_det_clr: id detection clear register, falling edge
129 * @idrise_det_en: id detection enable register, rising edge
130 * @idrise_det_st: id detection state register, rising edge
131 * @idrise_det_clr: id detection clear register, rising edge
132 * @ls_det_en: linestate detection enable register.
133 * @ls_det_st: linestate detection state register.
134 * @ls_det_clr: linestate detection clear register.
135 * @utmi_avalid: utmi vbus avalid status register.
136 * @utmi_bvalid: utmi vbus bvalid status register.
137 * @utmi_id: utmi id state register.
138 * @utmi_ls: utmi linestate state register.
139 * @utmi_hstdet: utmi host disconnect register.
140 */
141 struct rockchip_usb2phy_port_cfg {
142 struct usb2phy_reg phy_sus;
143 struct usb2phy_reg bvalid_det_en;
144 struct usb2phy_reg bvalid_det_st;
145 struct usb2phy_reg bvalid_det_clr;
146 struct usb2phy_reg disfall_en;
147 struct usb2phy_reg disfall_st;
148 struct usb2phy_reg disfall_clr;
149 struct usb2phy_reg disrise_en;
150 struct usb2phy_reg disrise_st;
151 struct usb2phy_reg disrise_clr;
152 struct usb2phy_reg idfall_det_en;
153 struct usb2phy_reg idfall_det_st;
154 struct usb2phy_reg idfall_det_clr;
155 struct usb2phy_reg idrise_det_en;
156 struct usb2phy_reg idrise_det_st;
157 struct usb2phy_reg idrise_det_clr;
158 struct usb2phy_reg ls_det_en;
159 struct usb2phy_reg ls_det_st;
160 struct usb2phy_reg ls_det_clr;
161 struct usb2phy_reg utmi_avalid;
162 struct usb2phy_reg utmi_bvalid;
163 struct usb2phy_reg utmi_id;
164 struct usb2phy_reg utmi_ls;
165 struct usb2phy_reg utmi_hstdet;
166 };
167
168 /**
169 * struct rockchip_usb2phy_cfg - usb-phy configuration.
170 * @reg: the address offset of grf for usb-phy config.
171 * @num_ports: specify how many ports that the phy has.
172 * @phy_tuning: phy default parameters tuning.
173 * @clkout_ctl: keep on/turn off output clk of phy.
174 * @port_cfgs: usb-phy port configurations.
175 * @chg_det: charger detection registers.
176 */
177 struct rockchip_usb2phy_cfg {
178 unsigned int reg;
179 unsigned int num_ports;
180 int (*phy_tuning)(struct rockchip_usb2phy *rphy);
181 struct usb2phy_reg clkout_ctl;
182 const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS];
183 const struct rockchip_chg_det_reg chg_det;
184 };
185
186 /**
187 * struct rockchip_usb2phy_port - usb-phy port data.
188 * @phy: generic phy.
189 * @port_id: flag for otg port or host port.
190 * @suspended: phy suspended flag.
191 * @vbus_attached: otg device vbus status.
192 * @host_disconnect: usb host disconnect status.
193 * @bvalid_irq: IRQ number assigned for vbus valid rise detection.
194 * @id_irq: IRQ number assigned for ID pin detection.
195 * @ls_irq: IRQ number assigned for linestate detection.
196 * @otg_mux_irq: IRQ number which multiplex otg-id/otg-bvalid/linestate
197 * irqs to one irq in otg-port.
198 * @mutex: for register updating in sm_work.
199 * @chg_work: charge detect work.
200 * @otg_sm_work: OTG state machine work.
201 * @sm_work: HOST state machine work.
202 * @port_cfg: port register configuration, assigned by driver data.
203 * @event_nb: hold event notification callback.
204 * @state: define OTG enumeration states before device reset.
205 * @mode: the dr_mode of the controller.
206 */
207 struct rockchip_usb2phy_port {
208 struct phy *phy;
209 unsigned int port_id;
210 bool suspended;
211 bool vbus_attached;
212 bool host_disconnect;
213 int bvalid_irq;
214 int id_irq;
215 int ls_irq;
216 int otg_mux_irq;
217 struct mutex mutex;
218 struct delayed_work chg_work;
219 struct delayed_work otg_sm_work;
220 struct delayed_work sm_work;
221 const struct rockchip_usb2phy_port_cfg *port_cfg;
222 struct notifier_block event_nb;
223 enum usb_otg_state state;
224 enum usb_dr_mode mode;
225 };
226
227 /**
228 * struct rockchip_usb2phy - usb2.0 phy driver data.
229 * @dev: pointer to device.
230 * @grf: General Register Files regmap.
231 * @usbgrf: USB General Register Files regmap.
232 * @clks: array of phy input clocks.
233 * @clk480m: clock struct of phy output clk.
234 * @clk480m_hw: clock struct of phy output clk management.
235 * @num_clks: number of phy input clocks.
236 * @phy_reset: phy reset control.
237 * @chg_state: states involved in USB charger detection.
238 * @chg_type: USB charger types.
239 * @dcd_retries: The retry count used to track Data contact
240 * detection process.
241 * @edev: extcon device for notification registration
242 * @irq: muxed interrupt for single irq configuration
243 * @phy_cfg: phy register configuration, assigned by driver data.
244 * @ports: phy port instance.
245 */
246 struct rockchip_usb2phy {
247 struct device *dev;
248 struct regmap *grf;
249 struct regmap *usbgrf;
250 struct clk_bulk_data *clks;
251 struct clk *clk480m;
252 struct clk_hw clk480m_hw;
253 int num_clks;
254 struct reset_control *phy_reset;
255 enum usb_chg_state chg_state;
256 enum power_supply_type chg_type;
257 u8 dcd_retries;
258 struct extcon_dev *edev;
259 int irq;
260 const struct rockchip_usb2phy_cfg *phy_cfg;
261 struct rockchip_usb2phy_port ports[USB2PHY_NUM_PORTS];
262 };
263
get_reg_base(struct rockchip_usb2phy * rphy)264 static inline struct regmap *get_reg_base(struct rockchip_usb2phy *rphy)
265 {
266 return rphy->usbgrf == NULL ? rphy->grf : rphy->usbgrf;
267 }
268
property_enable(struct regmap * base,const struct usb2phy_reg * reg,bool en)269 static inline int property_enable(struct regmap *base,
270 const struct usb2phy_reg *reg, bool en)
271 {
272 unsigned int val, mask, tmp;
273
274 tmp = en ? reg->enable : reg->disable;
275 mask = GENMASK(reg->bitend, reg->bitstart);
276 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
277
278 return regmap_write(base, reg->offset, val);
279 }
280
property_enabled(struct regmap * base,const struct usb2phy_reg * reg)281 static inline bool property_enabled(struct regmap *base,
282 const struct usb2phy_reg *reg)
283 {
284 int ret;
285 unsigned int tmp, orig;
286 unsigned int mask = GENMASK(reg->bitend, reg->bitstart);
287
288 ret = regmap_read(base, reg->offset, &orig);
289 if (ret)
290 return false;
291
292 tmp = (orig & mask) >> reg->bitstart;
293 return tmp != reg->disable;
294 }
295
rockchip_usb2phy_reset(struct rockchip_usb2phy * rphy)296 static int rockchip_usb2phy_reset(struct rockchip_usb2phy *rphy)
297 {
298 int ret;
299
300 ret = reset_control_assert(rphy->phy_reset);
301 if (ret)
302 return ret;
303
304 udelay(10);
305
306 ret = reset_control_deassert(rphy->phy_reset);
307 if (ret)
308 return ret;
309
310 usleep_range(100, 200);
311
312 return 0;
313 }
314
rockchip_usb2phy_clk_bulk_disable(void * data)315 static void rockchip_usb2phy_clk_bulk_disable(void *data)
316 {
317 struct rockchip_usb2phy *rphy = data;
318
319 clk_bulk_disable_unprepare(rphy->num_clks, rphy->clks);
320 }
321
rockchip_usb2phy_clk480m_prepare(struct clk_hw * hw)322 static int rockchip_usb2phy_clk480m_prepare(struct clk_hw *hw)
323 {
324 struct rockchip_usb2phy *rphy =
325 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
326 struct regmap *base = get_reg_base(rphy);
327 int ret;
328
329 /* turn on 480m clk output if it is off */
330 if (!property_enabled(base, &rphy->phy_cfg->clkout_ctl)) {
331 ret = property_enable(base, &rphy->phy_cfg->clkout_ctl, true);
332 if (ret)
333 return ret;
334
335 /* waiting for the clk become stable */
336 usleep_range(1200, 1300);
337 }
338
339 return 0;
340 }
341
rockchip_usb2phy_clk480m_unprepare(struct clk_hw * hw)342 static void rockchip_usb2phy_clk480m_unprepare(struct clk_hw *hw)
343 {
344 struct rockchip_usb2phy *rphy =
345 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
346 struct regmap *base = get_reg_base(rphy);
347
348 /* turn off 480m clk output */
349 property_enable(base, &rphy->phy_cfg->clkout_ctl, false);
350 }
351
rockchip_usb2phy_clk480m_prepared(struct clk_hw * hw)352 static int rockchip_usb2phy_clk480m_prepared(struct clk_hw *hw)
353 {
354 struct rockchip_usb2phy *rphy =
355 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
356 struct regmap *base = get_reg_base(rphy);
357
358 return property_enabled(base, &rphy->phy_cfg->clkout_ctl);
359 }
360
361 static unsigned long
rockchip_usb2phy_clk480m_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)362 rockchip_usb2phy_clk480m_recalc_rate(struct clk_hw *hw,
363 unsigned long parent_rate)
364 {
365 return 480000000;
366 }
367
368 static const struct clk_ops rockchip_usb2phy_clkout_ops = {
369 .prepare = rockchip_usb2phy_clk480m_prepare,
370 .unprepare = rockchip_usb2phy_clk480m_unprepare,
371 .is_prepared = rockchip_usb2phy_clk480m_prepared,
372 .recalc_rate = rockchip_usb2phy_clk480m_recalc_rate,
373 };
374
rockchip_usb2phy_clk480m_unregister(void * data)375 static void rockchip_usb2phy_clk480m_unregister(void *data)
376 {
377 struct rockchip_usb2phy *rphy = data;
378
379 of_clk_del_provider(rphy->dev->of_node);
380 clk_unregister(rphy->clk480m);
381 }
382
383 static int
rockchip_usb2phy_clk480m_register(struct rockchip_usb2phy * rphy)384 rockchip_usb2phy_clk480m_register(struct rockchip_usb2phy *rphy)
385 {
386 struct device_node *node = rphy->dev->of_node;
387 struct clk_init_data init;
388 struct clk *refclk = NULL;
389 const char *clk_name;
390 int i;
391 int ret = 0;
392
393 init.flags = 0;
394 init.name = "clk_usbphy_480m";
395 init.ops = &rockchip_usb2phy_clkout_ops;
396
397 /* optional override of the clockname */
398 of_property_read_string(node, "clock-output-names", &init.name);
399
400 for (i = 0; i < rphy->num_clks; i++) {
401 if (!strncmp(rphy->clks[i].id, "phyclk", 6)) {
402 refclk = rphy->clks[i].clk;
403 break;
404 }
405 }
406
407 if (!IS_ERR(refclk)) {
408 clk_name = __clk_get_name(refclk);
409 init.parent_names = &clk_name;
410 init.num_parents = 1;
411 } else {
412 init.parent_names = NULL;
413 init.num_parents = 0;
414 }
415
416 rphy->clk480m_hw.init = &init;
417
418 /* register the clock */
419 rphy->clk480m = clk_register(rphy->dev, &rphy->clk480m_hw);
420 if (IS_ERR(rphy->clk480m)) {
421 ret = PTR_ERR(rphy->clk480m);
422 goto err_ret;
423 }
424
425 ret = of_clk_add_provider(node, of_clk_src_simple_get, rphy->clk480m);
426 if (ret < 0)
427 goto err_clk_provider;
428
429 return devm_add_action_or_reset(rphy->dev, rockchip_usb2phy_clk480m_unregister, rphy);
430
431 err_clk_provider:
432 clk_unregister(rphy->clk480m);
433 err_ret:
434 return ret;
435 }
436
rockchip_usb2phy_extcon_register(struct rockchip_usb2phy * rphy)437 static int rockchip_usb2phy_extcon_register(struct rockchip_usb2phy *rphy)
438 {
439 struct device_node *node = rphy->dev->of_node;
440 struct extcon_dev *edev;
441 int ret;
442
443 if (of_property_present(node, "extcon")) {
444 edev = extcon_get_edev_by_phandle(rphy->dev, 0);
445 if (IS_ERR(edev))
446 return dev_err_probe(rphy->dev, PTR_ERR(edev),
447 "invalid or missing extcon\n");
448 } else {
449 /* Initialize extcon device */
450 edev = devm_extcon_dev_allocate(rphy->dev,
451 rockchip_usb2phy_extcon_cable);
452
453 if (IS_ERR(edev))
454 return dev_err_probe(rphy->dev, PTR_ERR(edev),
455 "failed to allocate extcon device\n");
456
457 ret = devm_extcon_dev_register(rphy->dev, edev);
458 if (ret)
459 return dev_err_probe(rphy->dev, ret,
460 "failed to register extcon device\n");
461 }
462
463 rphy->edev = edev;
464
465 return 0;
466 }
467
rockchip_usb2phy_enable_host_disc_irq(struct rockchip_usb2phy * rphy,struct rockchip_usb2phy_port * rport,bool en)468 static int rockchip_usb2phy_enable_host_disc_irq(struct rockchip_usb2phy *rphy,
469 struct rockchip_usb2phy_port *rport,
470 bool en)
471 {
472 int ret;
473
474 ret = property_enable(rphy->grf, &rport->port_cfg->disfall_clr, true);
475 if (ret)
476 return ret;
477
478 ret = property_enable(rphy->grf, &rport->port_cfg->disfall_en, en);
479 if (ret)
480 return ret;
481
482 ret = property_enable(rphy->grf, &rport->port_cfg->disrise_clr, true);
483 if (ret)
484 return ret;
485
486 return property_enable(rphy->grf, &rport->port_cfg->disrise_en, en);
487 }
488
rockchip_usb2phy_init(struct phy * phy)489 static int rockchip_usb2phy_init(struct phy *phy)
490 {
491 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
492 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
493 int ret = 0;
494
495 mutex_lock(&rport->mutex);
496
497 if (rport->port_id == USB2PHY_PORT_OTG) {
498 if (rport->mode != USB_DR_MODE_HOST &&
499 rport->mode != USB_DR_MODE_UNKNOWN) {
500 /* clear bvalid status and enable bvalid detect irq */
501 ret = property_enable(rphy->grf,
502 &rport->port_cfg->bvalid_det_clr,
503 true);
504 if (ret)
505 goto out;
506
507 ret = property_enable(rphy->grf,
508 &rport->port_cfg->bvalid_det_en,
509 true);
510 if (ret)
511 goto out;
512
513 /* clear id status and enable id detect irqs */
514 ret = property_enable(rphy->grf,
515 &rport->port_cfg->idfall_det_clr,
516 true);
517 if (ret)
518 goto out;
519
520 ret = property_enable(rphy->grf,
521 &rport->port_cfg->idrise_det_clr,
522 true);
523 if (ret)
524 goto out;
525
526 ret = property_enable(rphy->grf,
527 &rport->port_cfg->idfall_det_en,
528 true);
529 if (ret)
530 goto out;
531
532 ret = property_enable(rphy->grf,
533 &rport->port_cfg->idrise_det_en,
534 true);
535 if (ret)
536 goto out;
537
538 schedule_delayed_work(&rport->otg_sm_work,
539 OTG_SCHEDULE_DELAY * 3);
540 } else {
541 /* If OTG works in host only mode, do nothing. */
542 dev_dbg(&rport->phy->dev, "mode %d\n", rport->mode);
543 }
544 } else if (rport->port_id == USB2PHY_PORT_HOST) {
545 if (rport->port_cfg->disfall_en.offset) {
546 rport->host_disconnect = true;
547 ret = rockchip_usb2phy_enable_host_disc_irq(rphy, rport, true);
548 if (ret) {
549 dev_err(rphy->dev, "failed to enable disconnect irq\n");
550 goto out;
551 }
552 }
553
554 /* clear linestate and enable linestate detect irq */
555 ret = property_enable(rphy->grf,
556 &rport->port_cfg->ls_det_clr, true);
557 if (ret)
558 goto out;
559
560 ret = property_enable(rphy->grf,
561 &rport->port_cfg->ls_det_en, true);
562 if (ret)
563 goto out;
564
565 schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
566 }
567
568 out:
569 mutex_unlock(&rport->mutex);
570 return ret;
571 }
572
rockchip_usb2phy_power_on(struct phy * phy)573 static int rockchip_usb2phy_power_on(struct phy *phy)
574 {
575 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
576 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
577 struct regmap *base = get_reg_base(rphy);
578 int ret;
579
580 dev_dbg(&rport->phy->dev, "port power on\n");
581
582 if (!rport->suspended)
583 return 0;
584
585 ret = clk_prepare_enable(rphy->clk480m);
586 if (ret)
587 return ret;
588
589 ret = property_enable(base, &rport->port_cfg->phy_sus, false);
590 if (ret) {
591 clk_disable_unprepare(rphy->clk480m);
592 return ret;
593 }
594
595 /*
596 * For rk3588, it needs to reset phy when exit from
597 * suspend mode with common_on_n 1'b1(aka REFCLK_LOGIC,
598 * Bias, and PLL blocks are powered down) for lower
599 * power consumption. If you don't want to reset phy,
600 * please keep the common_on_n 1'b0 to set these blocks
601 * remain powered.
602 */
603 ret = rockchip_usb2phy_reset(rphy);
604 if (ret)
605 return ret;
606
607 /* waiting for the utmi_clk to become stable */
608 usleep_range(1500, 2000);
609
610 rport->suspended = false;
611 return 0;
612 }
613
rockchip_usb2phy_power_off(struct phy * phy)614 static int rockchip_usb2phy_power_off(struct phy *phy)
615 {
616 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
617 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
618 struct regmap *base = get_reg_base(rphy);
619 int ret;
620
621 dev_dbg(&rport->phy->dev, "port power off\n");
622
623 if (rport->suspended)
624 return 0;
625
626 ret = property_enable(base, &rport->port_cfg->phy_sus, true);
627 if (ret)
628 return ret;
629
630 rport->suspended = true;
631 clk_disable_unprepare(rphy->clk480m);
632
633 return 0;
634 }
635
rockchip_usb2phy_exit(struct phy * phy)636 static int rockchip_usb2phy_exit(struct phy *phy)
637 {
638 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
639
640 if (rport->port_id == USB2PHY_PORT_OTG &&
641 rport->mode != USB_DR_MODE_HOST &&
642 rport->mode != USB_DR_MODE_UNKNOWN) {
643 cancel_delayed_work_sync(&rport->otg_sm_work);
644 cancel_delayed_work_sync(&rport->chg_work);
645 } else if (rport->port_id == USB2PHY_PORT_HOST)
646 cancel_delayed_work_sync(&rport->sm_work);
647
648 return 0;
649 }
650
651 static const struct phy_ops rockchip_usb2phy_ops = {
652 .init = rockchip_usb2phy_init,
653 .exit = rockchip_usb2phy_exit,
654 .power_on = rockchip_usb2phy_power_on,
655 .power_off = rockchip_usb2phy_power_off,
656 .owner = THIS_MODULE,
657 };
658
rockchip_usb2phy_otg_sm_work(struct work_struct * work)659 static void rockchip_usb2phy_otg_sm_work(struct work_struct *work)
660 {
661 struct rockchip_usb2phy_port *rport =
662 container_of(work, struct rockchip_usb2phy_port,
663 otg_sm_work.work);
664 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
665 static unsigned int cable;
666 unsigned long delay;
667 bool vbus_attach, sch_work, notify_charger;
668
669 vbus_attach = property_enabled(rphy->grf,
670 &rport->port_cfg->utmi_bvalid);
671
672 sch_work = false;
673 notify_charger = false;
674 delay = OTG_SCHEDULE_DELAY;
675 dev_dbg(&rport->phy->dev, "%s otg sm work\n",
676 usb_otg_state_string(rport->state));
677
678 switch (rport->state) {
679 case OTG_STATE_UNDEFINED:
680 rport->state = OTG_STATE_B_IDLE;
681 if (!vbus_attach)
682 rockchip_usb2phy_power_off(rport->phy);
683 fallthrough;
684 case OTG_STATE_B_IDLE:
685 if (extcon_get_state(rphy->edev, EXTCON_USB_HOST) > 0) {
686 dev_dbg(&rport->phy->dev, "usb otg host connect\n");
687 rport->state = OTG_STATE_A_HOST;
688 rockchip_usb2phy_power_on(rport->phy);
689 return;
690 } else if (vbus_attach) {
691 dev_dbg(&rport->phy->dev, "vbus_attach\n");
692 switch (rphy->chg_state) {
693 case USB_CHG_STATE_UNDEFINED:
694 schedule_delayed_work(&rport->chg_work, 0);
695 return;
696 case USB_CHG_STATE_DETECTED:
697 switch (rphy->chg_type) {
698 case POWER_SUPPLY_TYPE_USB:
699 dev_dbg(&rport->phy->dev, "sdp cable is connected\n");
700 rockchip_usb2phy_power_on(rport->phy);
701 rport->state = OTG_STATE_B_PERIPHERAL;
702 notify_charger = true;
703 sch_work = true;
704 cable = EXTCON_CHG_USB_SDP;
705 break;
706 case POWER_SUPPLY_TYPE_USB_DCP:
707 dev_dbg(&rport->phy->dev, "dcp cable is connected\n");
708 rockchip_usb2phy_power_off(rport->phy);
709 notify_charger = true;
710 sch_work = true;
711 cable = EXTCON_CHG_USB_DCP;
712 break;
713 case POWER_SUPPLY_TYPE_USB_CDP:
714 dev_dbg(&rport->phy->dev, "cdp cable is connected\n");
715 rockchip_usb2phy_power_on(rport->phy);
716 rport->state = OTG_STATE_B_PERIPHERAL;
717 notify_charger = true;
718 sch_work = true;
719 cable = EXTCON_CHG_USB_CDP;
720 break;
721 default:
722 break;
723 }
724 break;
725 default:
726 break;
727 }
728 } else {
729 notify_charger = true;
730 rphy->chg_state = USB_CHG_STATE_UNDEFINED;
731 rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
732 }
733
734 if (rport->vbus_attached != vbus_attach) {
735 rport->vbus_attached = vbus_attach;
736
737 if (notify_charger && rphy->edev) {
738 extcon_set_state_sync(rphy->edev,
739 cable, vbus_attach);
740 if (cable == EXTCON_CHG_USB_SDP)
741 extcon_set_state_sync(rphy->edev,
742 EXTCON_USB,
743 vbus_attach);
744 }
745 }
746 break;
747 case OTG_STATE_B_PERIPHERAL:
748 if (!vbus_attach) {
749 dev_dbg(&rport->phy->dev, "usb disconnect\n");
750 rphy->chg_state = USB_CHG_STATE_UNDEFINED;
751 rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
752 rport->state = OTG_STATE_B_IDLE;
753 delay = 0;
754 rockchip_usb2phy_power_off(rport->phy);
755 }
756 sch_work = true;
757 break;
758 case OTG_STATE_A_HOST:
759 if (extcon_get_state(rphy->edev, EXTCON_USB_HOST) == 0) {
760 dev_dbg(&rport->phy->dev, "usb otg host disconnect\n");
761 rport->state = OTG_STATE_B_IDLE;
762 rockchip_usb2phy_power_off(rport->phy);
763 }
764 break;
765 default:
766 break;
767 }
768
769 if (sch_work)
770 schedule_delayed_work(&rport->otg_sm_work, delay);
771 }
772
chg_to_string(enum power_supply_type chg_type)773 static const char *chg_to_string(enum power_supply_type chg_type)
774 {
775 switch (chg_type) {
776 case POWER_SUPPLY_TYPE_USB:
777 return "USB_SDP_CHARGER";
778 case POWER_SUPPLY_TYPE_USB_DCP:
779 return "USB_DCP_CHARGER";
780 case POWER_SUPPLY_TYPE_USB_CDP:
781 return "USB_CDP_CHARGER";
782 default:
783 return "INVALID_CHARGER";
784 }
785 }
786
rockchip_chg_enable_dcd(struct rockchip_usb2phy * rphy,bool en)787 static void rockchip_chg_enable_dcd(struct rockchip_usb2phy *rphy,
788 bool en)
789 {
790 struct regmap *base = get_reg_base(rphy);
791
792 property_enable(base, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en);
793 property_enable(base, &rphy->phy_cfg->chg_det.idp_src_en, en);
794 }
795
rockchip_chg_enable_primary_det(struct rockchip_usb2phy * rphy,bool en)796 static void rockchip_chg_enable_primary_det(struct rockchip_usb2phy *rphy,
797 bool en)
798 {
799 struct regmap *base = get_reg_base(rphy);
800
801 property_enable(base, &rphy->phy_cfg->chg_det.vdp_src_en, en);
802 property_enable(base, &rphy->phy_cfg->chg_det.idm_sink_en, en);
803 }
804
rockchip_chg_enable_secondary_det(struct rockchip_usb2phy * rphy,bool en)805 static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy,
806 bool en)
807 {
808 struct regmap *base = get_reg_base(rphy);
809
810 property_enable(base, &rphy->phy_cfg->chg_det.vdm_src_en, en);
811 property_enable(base, &rphy->phy_cfg->chg_det.idp_sink_en, en);
812 }
813
814 #define CHG_DCD_POLL_TIME (100 * HZ / 1000)
815 #define CHG_DCD_MAX_RETRIES 6
816 #define CHG_PRIMARY_DET_TIME (40 * HZ / 1000)
817 #define CHG_SECONDARY_DET_TIME (40 * HZ / 1000)
rockchip_chg_detect_work(struct work_struct * work)818 static void rockchip_chg_detect_work(struct work_struct *work)
819 {
820 struct rockchip_usb2phy_port *rport =
821 container_of(work, struct rockchip_usb2phy_port, chg_work.work);
822 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
823 struct regmap *base = get_reg_base(rphy);
824 bool is_dcd, tmout, vout;
825 unsigned long delay;
826
827 dev_dbg(&rport->phy->dev, "chg detection work state = %d\n",
828 rphy->chg_state);
829 switch (rphy->chg_state) {
830 case USB_CHG_STATE_UNDEFINED:
831 if (!rport->suspended)
832 rockchip_usb2phy_power_off(rport->phy);
833 /* put the controller in non-driving mode */
834 property_enable(base, &rphy->phy_cfg->chg_det.opmode, false);
835 /* Start DCD processing stage 1 */
836 rockchip_chg_enable_dcd(rphy, true);
837 rphy->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
838 rphy->dcd_retries = 0;
839 delay = CHG_DCD_POLL_TIME;
840 break;
841 case USB_CHG_STATE_WAIT_FOR_DCD:
842 /* get data contact detection status */
843 is_dcd = property_enabled(rphy->grf,
844 &rphy->phy_cfg->chg_det.dp_det);
845 tmout = ++rphy->dcd_retries == CHG_DCD_MAX_RETRIES;
846 /* stage 2 */
847 if (is_dcd || tmout) {
848 /* stage 4 */
849 /* Turn off DCD circuitry */
850 rockchip_chg_enable_dcd(rphy, false);
851 /* Voltage Source on DP, Probe on DM */
852 rockchip_chg_enable_primary_det(rphy, true);
853 delay = CHG_PRIMARY_DET_TIME;
854 rphy->chg_state = USB_CHG_STATE_DCD_DONE;
855 } else {
856 /* stage 3 */
857 delay = CHG_DCD_POLL_TIME;
858 }
859 break;
860 case USB_CHG_STATE_DCD_DONE:
861 vout = property_enabled(rphy->grf,
862 &rphy->phy_cfg->chg_det.cp_det);
863 rockchip_chg_enable_primary_det(rphy, false);
864 if (vout) {
865 /* Voltage Source on DM, Probe on DP */
866 rockchip_chg_enable_secondary_det(rphy, true);
867 delay = CHG_SECONDARY_DET_TIME;
868 rphy->chg_state = USB_CHG_STATE_PRIMARY_DONE;
869 } else {
870 if (rphy->dcd_retries == CHG_DCD_MAX_RETRIES) {
871 /* floating charger found */
872 rphy->chg_type = POWER_SUPPLY_TYPE_USB_DCP;
873 rphy->chg_state = USB_CHG_STATE_DETECTED;
874 delay = 0;
875 } else {
876 rphy->chg_type = POWER_SUPPLY_TYPE_USB;
877 rphy->chg_state = USB_CHG_STATE_DETECTED;
878 delay = 0;
879 }
880 }
881 break;
882 case USB_CHG_STATE_PRIMARY_DONE:
883 vout = property_enabled(rphy->grf,
884 &rphy->phy_cfg->chg_det.dcp_det);
885 /* Turn off voltage source */
886 rockchip_chg_enable_secondary_det(rphy, false);
887 if (vout)
888 rphy->chg_type = POWER_SUPPLY_TYPE_USB_DCP;
889 else
890 rphy->chg_type = POWER_SUPPLY_TYPE_USB_CDP;
891 fallthrough;
892 case USB_CHG_STATE_SECONDARY_DONE:
893 rphy->chg_state = USB_CHG_STATE_DETECTED;
894 fallthrough;
895 case USB_CHG_STATE_DETECTED:
896 /* put the controller in normal mode */
897 property_enable(base, &rphy->phy_cfg->chg_det.opmode, true);
898 rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
899 dev_dbg(&rport->phy->dev, "charger = %s\n",
900 chg_to_string(rphy->chg_type));
901 return;
902 default:
903 return;
904 }
905
906 schedule_delayed_work(&rport->chg_work, delay);
907 }
908
909 /*
910 * The function manage host-phy port state and suspend/resume phy port
911 * to save power.
912 *
913 * we rely on utmi_linestate and utmi_hostdisconnect to identify whether
914 * devices is disconnect or not. Besides, we do not need care it is FS/LS
915 * disconnected or HS disconnected, actually, we just only need get the
916 * device is disconnected at last through rearm the delayed work,
917 * to suspend the phy port in _PHY_STATE_DISCONNECT_ case.
918 *
919 * NOTE: It may invoke *phy_powr_off or *phy_power_on which will invoke
920 * some clk related APIs, so do not invoke it from interrupt context directly.
921 */
rockchip_usb2phy_sm_work(struct work_struct * work)922 static void rockchip_usb2phy_sm_work(struct work_struct *work)
923 {
924 struct rockchip_usb2phy_port *rport =
925 container_of(work, struct rockchip_usb2phy_port, sm_work.work);
926 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
927 unsigned int sh, ul, uhd, state;
928 unsigned int ul_mask, uhd_mask;
929 int ret;
930
931 mutex_lock(&rport->mutex);
932
933 ret = regmap_read(rphy->grf, rport->port_cfg->utmi_ls.offset, &ul);
934 if (ret < 0)
935 goto next_schedule;
936
937 ul_mask = GENMASK(rport->port_cfg->utmi_ls.bitend,
938 rport->port_cfg->utmi_ls.bitstart);
939
940 if (rport->port_cfg->utmi_hstdet.offset) {
941 ret = regmap_read(rphy->grf, rport->port_cfg->utmi_hstdet.offset, &uhd);
942 if (ret < 0)
943 goto next_schedule;
944
945 uhd_mask = GENMASK(rport->port_cfg->utmi_hstdet.bitend,
946 rport->port_cfg->utmi_hstdet.bitstart);
947
948 sh = rport->port_cfg->utmi_hstdet.bitend -
949 rport->port_cfg->utmi_hstdet.bitstart + 1;
950 /* stitch on utmi_ls and utmi_hstdet as phy state */
951 state = ((uhd & uhd_mask) >> rport->port_cfg->utmi_hstdet.bitstart) |
952 (((ul & ul_mask) >> rport->port_cfg->utmi_ls.bitstart) << sh);
953 } else {
954 state = ((ul & ul_mask) >> rport->port_cfg->utmi_ls.bitstart) << 1 |
955 rport->host_disconnect;
956 }
957
958 switch (state) {
959 case PHY_STATE_HS_ONLINE:
960 dev_dbg(&rport->phy->dev, "HS online\n");
961 break;
962 case PHY_STATE_FS_LS_ONLINE:
963 /*
964 * For FS/LS device, the online state share with connect state
965 * from utmi_ls and utmi_hstdet register, so we distinguish
966 * them via suspended flag.
967 *
968 * Plus, there are two cases, one is D- Line pull-up, and D+
969 * line pull-down, the state is 4; another is D+ line pull-up,
970 * and D- line pull-down, the state is 2.
971 */
972 if (!rport->suspended) {
973 /* D- line pull-up, D+ line pull-down */
974 dev_dbg(&rport->phy->dev, "FS/LS online\n");
975 break;
976 }
977 fallthrough;
978 case PHY_STATE_CONNECT:
979 if (rport->suspended) {
980 dev_dbg(&rport->phy->dev, "Connected\n");
981 rockchip_usb2phy_power_on(rport->phy);
982 rport->suspended = false;
983 } else {
984 /* D+ line pull-up, D- line pull-down */
985 dev_dbg(&rport->phy->dev, "FS/LS online\n");
986 }
987 break;
988 case PHY_STATE_DISCONNECT:
989 if (!rport->suspended) {
990 dev_dbg(&rport->phy->dev, "Disconnected\n");
991 rockchip_usb2phy_power_off(rport->phy);
992 rport->suspended = true;
993 }
994
995 /*
996 * activate the linestate detection to get the next device
997 * plug-in irq.
998 */
999 property_enable(rphy->grf, &rport->port_cfg->ls_det_clr, true);
1000 property_enable(rphy->grf, &rport->port_cfg->ls_det_en, true);
1001
1002 /*
1003 * we don't need to rearm the delayed work when the phy port
1004 * is suspended.
1005 */
1006 mutex_unlock(&rport->mutex);
1007 return;
1008 default:
1009 dev_dbg(&rport->phy->dev, "unknown phy state\n");
1010 break;
1011 }
1012
1013 next_schedule:
1014 mutex_unlock(&rport->mutex);
1015 schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
1016 }
1017
rockchip_usb2phy_linestate_irq(int irq,void * data)1018 static irqreturn_t rockchip_usb2phy_linestate_irq(int irq, void *data)
1019 {
1020 struct rockchip_usb2phy_port *rport = data;
1021 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
1022
1023 if (!property_enabled(rphy->grf, &rport->port_cfg->ls_det_st))
1024 return IRQ_NONE;
1025
1026 mutex_lock(&rport->mutex);
1027
1028 /* disable linestate detect irq and clear its status */
1029 property_enable(rphy->grf, &rport->port_cfg->ls_det_en, false);
1030 property_enable(rphy->grf, &rport->port_cfg->ls_det_clr, true);
1031
1032 mutex_unlock(&rport->mutex);
1033
1034 /*
1035 * In this case for host phy port, a new device is plugged in,
1036 * meanwhile, if the phy port is suspended, we need rearm the work to
1037 * resume it and mange its states; otherwise, we do nothing about that.
1038 */
1039 if (rport->suspended && rport->port_id == USB2PHY_PORT_HOST)
1040 rockchip_usb2phy_sm_work(&rport->sm_work.work);
1041
1042 return IRQ_HANDLED;
1043 }
1044
rockchip_usb2phy_bvalid_irq(int irq,void * data)1045 static irqreturn_t rockchip_usb2phy_bvalid_irq(int irq, void *data)
1046 {
1047 struct rockchip_usb2phy_port *rport = data;
1048 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
1049
1050 if (!property_enabled(rphy->grf, &rport->port_cfg->bvalid_det_st))
1051 return IRQ_NONE;
1052
1053 /* clear bvalid detect irq pending status */
1054 property_enable(rphy->grf, &rport->port_cfg->bvalid_det_clr, true);
1055
1056 rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
1057
1058 return IRQ_HANDLED;
1059 }
1060
rockchip_usb2phy_id_irq(int irq,void * data)1061 static irqreturn_t rockchip_usb2phy_id_irq(int irq, void *data)
1062 {
1063 struct rockchip_usb2phy_port *rport = data;
1064 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
1065 bool id;
1066
1067 if (!property_enabled(rphy->grf, &rport->port_cfg->idfall_det_st) &&
1068 !property_enabled(rphy->grf, &rport->port_cfg->idrise_det_st))
1069 return IRQ_NONE;
1070
1071 /* clear id detect irq pending status */
1072 if (property_enabled(rphy->grf, &rport->port_cfg->idfall_det_st))
1073 property_enable(rphy->grf, &rport->port_cfg->idfall_det_clr, true);
1074
1075 if (property_enabled(rphy->grf, &rport->port_cfg->idrise_det_st))
1076 property_enable(rphy->grf, &rport->port_cfg->idrise_det_clr, true);
1077
1078 id = property_enabled(rphy->grf, &rport->port_cfg->utmi_id);
1079 extcon_set_state_sync(rphy->edev, EXTCON_USB_HOST, !id);
1080
1081 return IRQ_HANDLED;
1082 }
1083
rockchip_usb2phy_otg_mux_irq(int irq,void * data)1084 static irqreturn_t rockchip_usb2phy_otg_mux_irq(int irq, void *data)
1085 {
1086 irqreturn_t ret = IRQ_NONE;
1087
1088 ret |= rockchip_usb2phy_bvalid_irq(irq, data);
1089 ret |= rockchip_usb2phy_id_irq(irq, data);
1090
1091 return ret;
1092 }
1093
rockchip_usb2phy_host_disc_irq(int irq,void * data)1094 static irqreturn_t rockchip_usb2phy_host_disc_irq(int irq, void *data)
1095 {
1096 struct rockchip_usb2phy_port *rport = data;
1097 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
1098
1099 if (!property_enabled(rphy->grf, &rport->port_cfg->disfall_st) &&
1100 !property_enabled(rphy->grf, &rport->port_cfg->disrise_st))
1101 return IRQ_NONE;
1102
1103 mutex_lock(&rport->mutex);
1104
1105 /* clear disconnect fall or rise detect irq pending status */
1106 if (property_enabled(rphy->grf, &rport->port_cfg->disfall_st)) {
1107 property_enable(rphy->grf, &rport->port_cfg->disfall_clr, true);
1108 rport->host_disconnect = false;
1109 } else if (property_enabled(rphy->grf, &rport->port_cfg->disrise_st)) {
1110 property_enable(rphy->grf, &rport->port_cfg->disrise_clr, true);
1111 rport->host_disconnect = true;
1112 }
1113
1114 mutex_unlock(&rport->mutex);
1115
1116 return IRQ_HANDLED;
1117 }
1118
rockchip_usb2phy_irq(int irq,void * data)1119 static irqreturn_t rockchip_usb2phy_irq(int irq, void *data)
1120 {
1121 struct rockchip_usb2phy *rphy = data;
1122 struct rockchip_usb2phy_port *rport;
1123 irqreturn_t ret = IRQ_NONE;
1124 unsigned int index;
1125
1126 for (index = 0; index < rphy->phy_cfg->num_ports; index++) {
1127 rport = &rphy->ports[index];
1128 if (!rport->phy)
1129 continue;
1130
1131 if (rport->port_id == USB2PHY_PORT_HOST &&
1132 rport->port_cfg->disfall_en.offset)
1133 ret |= rockchip_usb2phy_host_disc_irq(irq, rport);
1134
1135 switch (rport->port_id) {
1136 case USB2PHY_PORT_OTG:
1137 if (rport->mode != USB_DR_MODE_HOST &&
1138 rport->mode != USB_DR_MODE_UNKNOWN)
1139 ret |= rockchip_usb2phy_otg_mux_irq(irq, rport);
1140 break;
1141 case USB2PHY_PORT_HOST:
1142 ret |= rockchip_usb2phy_linestate_irq(irq, rport);
1143 break;
1144 }
1145 }
1146
1147 return ret;
1148 }
1149
rockchip_usb2phy_port_irq_init(struct rockchip_usb2phy * rphy,struct rockchip_usb2phy_port * rport,struct device_node * child_np)1150 static int rockchip_usb2phy_port_irq_init(struct rockchip_usb2phy *rphy,
1151 struct rockchip_usb2phy_port *rport,
1152 struct device_node *child_np)
1153 {
1154 int ret;
1155
1156 /*
1157 * If the usb2 phy used combined irq for otg and host port,
1158 * don't need to init otg and host port irq separately.
1159 */
1160 if (rphy->irq > 0)
1161 return 0;
1162
1163 switch (rport->port_id) {
1164 case USB2PHY_PORT_HOST:
1165 rport->ls_irq = of_irq_get_byname(child_np, "linestate");
1166 if (rport->ls_irq < 0) {
1167 dev_err(rphy->dev, "no linestate irq provided\n");
1168 return rport->ls_irq;
1169 }
1170
1171 ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL,
1172 rockchip_usb2phy_linestate_irq,
1173 IRQF_ONESHOT,
1174 "rockchip_usb2phy", rport);
1175 if (ret) {
1176 dev_err(rphy->dev, "failed to request linestate irq handle\n");
1177 return ret;
1178 }
1179 break;
1180 case USB2PHY_PORT_OTG:
1181 /*
1182 * Some SoCs use one interrupt with otg-id/otg-bvalid/linestate
1183 * interrupts muxed together, so probe the otg-mux interrupt first,
1184 * if not found, then look for the regular interrupts one by one.
1185 */
1186 rport->otg_mux_irq = of_irq_get_byname(child_np, "otg-mux");
1187 if (rport->otg_mux_irq > 0) {
1188 ret = devm_request_threaded_irq(rphy->dev, rport->otg_mux_irq,
1189 NULL,
1190 rockchip_usb2phy_otg_mux_irq,
1191 IRQF_ONESHOT,
1192 "rockchip_usb2phy_otg",
1193 rport);
1194 if (ret) {
1195 dev_err(rphy->dev,
1196 "failed to request otg-mux irq handle\n");
1197 return ret;
1198 }
1199 } else {
1200 rport->bvalid_irq = of_irq_get_byname(child_np, "otg-bvalid");
1201 if (rport->bvalid_irq < 0) {
1202 dev_err(rphy->dev, "no vbus valid irq provided\n");
1203 ret = rport->bvalid_irq;
1204 return ret;
1205 }
1206
1207 ret = devm_request_threaded_irq(rphy->dev, rport->bvalid_irq,
1208 NULL,
1209 rockchip_usb2phy_bvalid_irq,
1210 IRQF_ONESHOT,
1211 "rockchip_usb2phy_bvalid",
1212 rport);
1213 if (ret) {
1214 dev_err(rphy->dev,
1215 "failed to request otg-bvalid irq handle\n");
1216 return ret;
1217 }
1218
1219 rport->id_irq = of_irq_get_byname(child_np, "otg-id");
1220 if (rport->id_irq < 0) {
1221 dev_err(rphy->dev, "no otg-id irq provided\n");
1222 ret = rport->id_irq;
1223 return ret;
1224 }
1225
1226 ret = devm_request_threaded_irq(rphy->dev, rport->id_irq,
1227 NULL,
1228 rockchip_usb2phy_id_irq,
1229 IRQF_ONESHOT,
1230 "rockchip_usb2phy_id",
1231 rport);
1232 if (ret) {
1233 dev_err(rphy->dev,
1234 "failed to request otg-id irq handle\n");
1235 return ret;
1236 }
1237 }
1238 break;
1239 default:
1240 return -EINVAL;
1241 }
1242
1243 return 0;
1244 }
1245
rockchip_usb2phy_host_port_init(struct rockchip_usb2phy * rphy,struct rockchip_usb2phy_port * rport,struct device_node * child_np)1246 static int rockchip_usb2phy_host_port_init(struct rockchip_usb2phy *rphy,
1247 struct rockchip_usb2phy_port *rport,
1248 struct device_node *child_np)
1249 {
1250 int ret;
1251
1252 rport->port_id = USB2PHY_PORT_HOST;
1253 rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST];
1254 rport->suspended = true;
1255
1256 mutex_init(&rport->mutex);
1257 INIT_DELAYED_WORK(&rport->sm_work, rockchip_usb2phy_sm_work);
1258
1259 ret = rockchip_usb2phy_port_irq_init(rphy, rport, child_np);
1260 if (ret) {
1261 dev_err(rphy->dev, "failed to setup host irq\n");
1262 return ret;
1263 }
1264
1265 return 0;
1266 }
1267
rockchip_otg_event(struct notifier_block * nb,unsigned long event,void * ptr)1268 static int rockchip_otg_event(struct notifier_block *nb,
1269 unsigned long event, void *ptr)
1270 {
1271 struct rockchip_usb2phy_port *rport =
1272 container_of(nb, struct rockchip_usb2phy_port, event_nb);
1273
1274 schedule_delayed_work(&rport->otg_sm_work, OTG_SCHEDULE_DELAY);
1275
1276 return NOTIFY_DONE;
1277 }
1278
rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy * rphy,struct rockchip_usb2phy_port * rport,struct device_node * child_np)1279 static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy,
1280 struct rockchip_usb2phy_port *rport,
1281 struct device_node *child_np)
1282 {
1283 int ret, id;
1284
1285 rport->port_id = USB2PHY_PORT_OTG;
1286 rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
1287 rport->state = OTG_STATE_UNDEFINED;
1288
1289 /*
1290 * set suspended flag to true, but actually don't
1291 * put phy in suspend mode, it aims to enable usb
1292 * phy and clock in power_on() called by usb controller
1293 * driver during probe.
1294 */
1295 rport->suspended = true;
1296 rport->vbus_attached = false;
1297
1298 mutex_init(&rport->mutex);
1299
1300 rport->mode = of_usb_get_dr_mode_by_phy(child_np, -1);
1301 if (rport->mode == USB_DR_MODE_HOST ||
1302 rport->mode == USB_DR_MODE_UNKNOWN) {
1303 ret = 0;
1304 goto out;
1305 }
1306
1307 INIT_DELAYED_WORK(&rport->chg_work, rockchip_chg_detect_work);
1308 INIT_DELAYED_WORK(&rport->otg_sm_work, rockchip_usb2phy_otg_sm_work);
1309
1310 ret = rockchip_usb2phy_port_irq_init(rphy, rport, child_np);
1311 if (ret) {
1312 dev_err(rphy->dev, "failed to init irq for host port\n");
1313 goto out;
1314 }
1315
1316 if (!IS_ERR(rphy->edev)) {
1317 rport->event_nb.notifier_call = rockchip_otg_event;
1318
1319 ret = devm_extcon_register_notifier(rphy->dev, rphy->edev,
1320 EXTCON_USB_HOST, &rport->event_nb);
1321 if (ret) {
1322 dev_err(rphy->dev, "register USB HOST notifier failed\n");
1323 goto out;
1324 }
1325
1326 if (!of_property_present(rphy->dev->of_node, "extcon")) {
1327 /* do initial sync of usb state */
1328 id = property_enabled(rphy->grf, &rport->port_cfg->utmi_id);
1329 extcon_set_state_sync(rphy->edev, EXTCON_USB_HOST, !id);
1330 }
1331 }
1332
1333 out:
1334 return ret;
1335 }
1336
rockchip_usb2phy_probe(struct platform_device * pdev)1337 static int rockchip_usb2phy_probe(struct platform_device *pdev)
1338 {
1339 struct device *dev = &pdev->dev;
1340 struct device_node *np = dev->of_node;
1341 struct device_node *child_np;
1342 struct phy_provider *provider;
1343 struct rockchip_usb2phy *rphy;
1344 const struct rockchip_usb2phy_cfg *phy_cfgs;
1345 unsigned int reg;
1346 int index = 0, ret;
1347
1348 rphy = devm_kzalloc(dev, sizeof(*rphy), GFP_KERNEL);
1349 if (!rphy)
1350 return -ENOMEM;
1351
1352 if (!dev->parent || !dev->parent->of_node) {
1353 rphy->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,usbgrf");
1354 if (IS_ERR(rphy->grf)) {
1355 dev_err(dev, "failed to locate usbgrf\n");
1356 return PTR_ERR(rphy->grf);
1357 }
1358 } else {
1359 rphy->grf = syscon_node_to_regmap(dev->parent->of_node);
1360 if (IS_ERR(rphy->grf))
1361 return PTR_ERR(rphy->grf);
1362 }
1363
1364 if (of_device_is_compatible(np, "rockchip,rv1108-usb2phy")) {
1365 rphy->usbgrf =
1366 syscon_regmap_lookup_by_phandle(dev->of_node,
1367 "rockchip,usbgrf");
1368 if (IS_ERR(rphy->usbgrf))
1369 return PTR_ERR(rphy->usbgrf);
1370 } else {
1371 rphy->usbgrf = NULL;
1372 }
1373
1374 if (of_property_read_u32_index(np, "reg", 0, ®)) {
1375 dev_err(dev, "the reg property is not assigned in %pOFn node\n", np);
1376 return -EINVAL;
1377 }
1378
1379 /* support address_cells=2 */
1380 if (of_property_count_u32_elems(np, "reg") > 2 && reg == 0) {
1381 if (of_property_read_u32_index(np, "reg", 1, ®)) {
1382 dev_err(dev, "the reg property is not assigned in %pOFn node\n", np);
1383 return -EINVAL;
1384 }
1385 }
1386
1387 rphy->dev = dev;
1388 phy_cfgs = device_get_match_data(dev);
1389 rphy->chg_state = USB_CHG_STATE_UNDEFINED;
1390 rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
1391 rphy->irq = platform_get_irq_optional(pdev, 0);
1392 platform_set_drvdata(pdev, rphy);
1393
1394 if (!phy_cfgs)
1395 return dev_err_probe(dev, -EINVAL, "phy configs are not assigned!\n");
1396
1397 ret = rockchip_usb2phy_extcon_register(rphy);
1398 if (ret)
1399 return ret;
1400
1401 /* find a proper config that can be matched with the DT */
1402 do {
1403 if (phy_cfgs[index].reg == reg) {
1404 rphy->phy_cfg = &phy_cfgs[index];
1405 break;
1406 }
1407
1408 ++index;
1409 } while (phy_cfgs[index].reg);
1410
1411 if (!rphy->phy_cfg) {
1412 dev_err(dev, "could not find phy config for reg=0x%08x\n", reg);
1413 return -EINVAL;
1414 }
1415
1416 rphy->phy_reset = devm_reset_control_get_optional(dev, "phy");
1417 if (IS_ERR(rphy->phy_reset))
1418 return PTR_ERR(rphy->phy_reset);
1419
1420 ret = devm_clk_bulk_get_all(dev, &rphy->clks);
1421 if (ret == -EPROBE_DEFER)
1422 return dev_err_probe(&pdev->dev, -EPROBE_DEFER,
1423 "failed to get phy clock\n");
1424
1425 /* Clocks are optional */
1426 rphy->num_clks = ret < 0 ? 0 : ret;
1427
1428 ret = rockchip_usb2phy_clk480m_register(rphy);
1429 if (ret)
1430 return dev_err_probe(dev, ret, "failed to register 480m output clock\n");
1431
1432 ret = clk_bulk_prepare_enable(rphy->num_clks, rphy->clks);
1433 if (ret)
1434 return dev_err_probe(dev, ret, "failed to enable phy clock\n");
1435
1436 ret = devm_add_action_or_reset(dev, rockchip_usb2phy_clk_bulk_disable, rphy);
1437 if (ret)
1438 return ret;
1439
1440 if (rphy->phy_cfg->phy_tuning) {
1441 ret = rphy->phy_cfg->phy_tuning(rphy);
1442 if (ret)
1443 return ret;
1444 }
1445
1446 index = 0;
1447 for_each_available_child_of_node(np, child_np) {
1448 struct rockchip_usb2phy_port *rport = &rphy->ports[index];
1449 struct phy *phy;
1450
1451 /* This driver aims to support both otg-port and host-port */
1452 if (!of_node_name_eq(child_np, "host-port") &&
1453 !of_node_name_eq(child_np, "otg-port"))
1454 goto next_child;
1455
1456 phy = devm_phy_create(dev, child_np, &rockchip_usb2phy_ops);
1457 if (IS_ERR(phy)) {
1458 ret = dev_err_probe(dev, PTR_ERR(phy), "failed to create phy\n");
1459 goto put_child;
1460 }
1461
1462 rport->phy = phy;
1463 phy_set_drvdata(rport->phy, rport);
1464
1465 /* initialize otg/host port separately */
1466 if (of_node_name_eq(child_np, "host-port")) {
1467 ret = rockchip_usb2phy_host_port_init(rphy, rport, child_np);
1468 if (ret)
1469 goto put_child;
1470 } else {
1471 ret = rockchip_usb2phy_otg_port_init(rphy, rport, child_np);
1472 if (ret)
1473 goto put_child;
1474 }
1475
1476 next_child:
1477 /* to prevent out of boundary */
1478 if (++index >= rphy->phy_cfg->num_ports) {
1479 of_node_put(child_np);
1480 break;
1481 }
1482 }
1483
1484 provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1485
1486 if (rphy->irq > 0) {
1487 ret = devm_request_threaded_irq(rphy->dev, rphy->irq, NULL,
1488 rockchip_usb2phy_irq,
1489 IRQF_ONESHOT,
1490 "rockchip_usb2phy",
1491 rphy);
1492 if (ret) {
1493 dev_err_probe(rphy->dev, ret, "failed to request usb2phy irq handle\n");
1494 goto put_child;
1495 }
1496 }
1497
1498 return PTR_ERR_OR_ZERO(provider);
1499
1500 put_child:
1501 of_node_put(child_np);
1502 return ret;
1503 }
1504
rk3128_usb2phy_tuning(struct rockchip_usb2phy * rphy)1505 static int rk3128_usb2phy_tuning(struct rockchip_usb2phy *rphy)
1506 {
1507 /* Turn off differential receiver in suspend mode */
1508 return regmap_write_bits(rphy->grf, 0x298,
1509 BIT(2) << BIT_WRITEABLE_SHIFT | BIT(2),
1510 BIT(2) << BIT_WRITEABLE_SHIFT | 0);
1511 }
1512
rk3576_usb2phy_tuning(struct rockchip_usb2phy * rphy)1513 static int rk3576_usb2phy_tuning(struct rockchip_usb2phy *rphy)
1514 {
1515 int ret;
1516 u32 reg = rphy->phy_cfg->reg;
1517
1518 /* Deassert SIDDQ to power on analog block */
1519 ret = regmap_write(rphy->grf, reg + 0x0010, GENMASK(29, 29) | 0x0000);
1520 if (ret)
1521 return ret;
1522
1523 /* Do reset after exit IDDQ mode */
1524 ret = rockchip_usb2phy_reset(rphy);
1525 if (ret)
1526 return ret;
1527
1528 /* HS DC Voltage Level Adjustment 4'b1001 : +5.89% */
1529 ret |= regmap_write(rphy->grf, reg + 0x000c, GENMASK(27, 24) | 0x0900);
1530
1531 /* HS Transmitter Pre-Emphasis Current Control 2'b10 : 2x */
1532 ret |= regmap_write(rphy->grf, reg + 0x0010, GENMASK(20, 19) | 0x0010);
1533
1534 return ret;
1535 }
1536
rk3588_usb2phy_tuning(struct rockchip_usb2phy * rphy)1537 static int rk3588_usb2phy_tuning(struct rockchip_usb2phy *rphy)
1538 {
1539 int ret;
1540 bool usb3otg = false;
1541 /*
1542 * utmi_termselect = 1'b1 (en FS terminations)
1543 * utmi_xcvrselect = 2'b01 (FS transceiver)
1544 */
1545 int suspend_cfg = 0x14;
1546
1547 if (rphy->phy_cfg->reg == 0x0000 || rphy->phy_cfg->reg == 0x4000) {
1548 /* USB2 config for USB3_0 and USB3_1 */
1549 suspend_cfg |= 0x01; /* utmi_opmode = 2'b01 (no-driving) */
1550 usb3otg = true;
1551 } else if (rphy->phy_cfg->reg == 0x8000 || rphy->phy_cfg->reg == 0xc000) {
1552 /* USB2 config for USB2_0 and USB2_1 */
1553 suspend_cfg |= 0x00; /* utmi_opmode = 2'b00 (normal) */
1554 } else {
1555 return -EINVAL;
1556 }
1557
1558 /* Deassert SIDDQ to power on analog block */
1559 ret = regmap_write(rphy->grf, 0x0008, GENMASK(29, 29) | 0x0000);
1560 if (ret)
1561 return ret;
1562
1563 /* Do reset after exit IDDQ mode */
1564 ret = rockchip_usb2phy_reset(rphy);
1565 if (ret)
1566 return ret;
1567
1568 /* suspend configuration */
1569 ret |= regmap_write(rphy->grf, 0x000c, GENMASK(20, 16) | suspend_cfg);
1570
1571 /* HS DC Voltage Level Adjustment 4'b1001 : +5.89% */
1572 ret |= regmap_write(rphy->grf, 0x0004, GENMASK(27, 24) | 0x0900);
1573
1574 /* HS Transmitter Pre-Emphasis Current Control 2'b10 : 2x */
1575 ret |= regmap_write(rphy->grf, 0x0008, GENMASK(20, 19) | 0x0010);
1576
1577 if (!usb3otg)
1578 return ret;
1579
1580 /* Pullup iddig pin for USB3_0 OTG mode */
1581 ret |= regmap_write(rphy->grf, 0x0010, GENMASK(17, 16) | 0x0003);
1582
1583 return ret;
1584 }
1585
1586 static const struct rockchip_usb2phy_cfg rk3036_phy_cfgs[] = {
1587 {
1588 .reg = 0x17c,
1589 .num_ports = 2,
1590 .phy_tuning = rk3128_usb2phy_tuning,
1591 .clkout_ctl = { 0x017c, 11, 11, 1, 0 },
1592 .port_cfgs = {
1593 [USB2PHY_PORT_OTG] = {
1594 .phy_sus = { 0x017c, 8, 0, 0, 0x1d1 },
1595 .bvalid_det_en = { 0x017c, 14, 14, 0, 1 },
1596 .bvalid_det_st = { 0x017c, 15, 15, 0, 1 },
1597 .bvalid_det_clr = { 0x017c, 15, 15, 0, 1 },
1598 .ls_det_en = { 0x017c, 12, 12, 0, 1 },
1599 .ls_det_st = { 0x017c, 13, 13, 0, 1 },
1600 .ls_det_clr = { 0x017c, 13, 13, 0, 1 },
1601 .utmi_bvalid = { 0x014c, 8, 8, 0, 1 },
1602 .utmi_id = { 0x014c, 11, 11, 0, 1 },
1603 .utmi_ls = { 0x014c, 10, 9, 0, 1 },
1604
1605 },
1606 [USB2PHY_PORT_HOST] = {
1607 .phy_sus = { 0x0194, 8, 0, 0, 0x1d1 },
1608 .ls_det_en = { 0x0194, 14, 14, 0, 1 },
1609 .ls_det_st = { 0x0194, 15, 15, 0, 1 },
1610 .ls_det_clr = { 0x0194, 15, 15, 0, 1 }
1611 }
1612 },
1613 },
1614 { /* sentinel */ }
1615 };
1616
1617 static const struct rockchip_usb2phy_cfg rk3128_phy_cfgs[] = {
1618 {
1619 .reg = 0x17c,
1620 .num_ports = 2,
1621 .phy_tuning = rk3128_usb2phy_tuning,
1622 .clkout_ctl = { 0x0190, 15, 15, 1, 0 },
1623 .port_cfgs = {
1624 [USB2PHY_PORT_OTG] = {
1625 .phy_sus = { 0x017c, 8, 0, 0, 0x1d1 },
1626 .bvalid_det_en = { 0x017c, 14, 14, 0, 1 },
1627 .bvalid_det_st = { 0x017c, 15, 15, 0, 1 },
1628 .bvalid_det_clr = { 0x017c, 15, 15, 0, 1 },
1629 .idfall_det_en = { 0x01a0, 2, 2, 0, 1 },
1630 .idfall_det_st = { 0x01a0, 3, 3, 0, 1 },
1631 .idfall_det_clr = { 0x01a0, 3, 3, 0, 1 },
1632 .idrise_det_en = { 0x01a0, 0, 0, 0, 1 },
1633 .idrise_det_st = { 0x01a0, 1, 1, 0, 1 },
1634 .idrise_det_clr = { 0x01a0, 1, 1, 0, 1 },
1635 .ls_det_en = { 0x017c, 12, 12, 0, 1 },
1636 .ls_det_st = { 0x017c, 13, 13, 0, 1 },
1637 .ls_det_clr = { 0x017c, 13, 13, 0, 1 },
1638 .utmi_bvalid = { 0x014c, 5, 5, 0, 1 },
1639 .utmi_id = { 0x014c, 8, 8, 0, 1 },
1640 .utmi_ls = { 0x014c, 7, 6, 0, 1 },
1641 },
1642 [USB2PHY_PORT_HOST] = {
1643 .phy_sus = { 0x0194, 8, 0, 0, 0x1d1 },
1644 .ls_det_en = { 0x0194, 14, 14, 0, 1 },
1645 .ls_det_st = { 0x0194, 15, 15, 0, 1 },
1646 .ls_det_clr = { 0x0194, 15, 15, 0, 1 }
1647 }
1648 },
1649 .chg_det = {
1650 .opmode = { 0x017c, 3, 0, 5, 1 },
1651 .cp_det = { 0x02c0, 6, 6, 0, 1 },
1652 .dcp_det = { 0x02c0, 5, 5, 0, 1 },
1653 .dp_det = { 0x02c0, 7, 7, 0, 1 },
1654 .idm_sink_en = { 0x0184, 8, 8, 0, 1 },
1655 .idp_sink_en = { 0x0184, 7, 7, 0, 1 },
1656 .idp_src_en = { 0x0184, 9, 9, 0, 1 },
1657 .rdm_pdwn_en = { 0x0184, 10, 10, 0, 1 },
1658 .vdm_src_en = { 0x0184, 12, 12, 0, 1 },
1659 .vdp_src_en = { 0x0184, 11, 11, 0, 1 },
1660 },
1661 },
1662 { /* sentinel */ }
1663 };
1664
1665 static const struct rockchip_usb2phy_cfg rk3228_phy_cfgs[] = {
1666 {
1667 .reg = 0x760,
1668 .num_ports = 2,
1669 .clkout_ctl = { 0x0768, 4, 4, 1, 0 },
1670 .port_cfgs = {
1671 [USB2PHY_PORT_OTG] = {
1672 .phy_sus = { 0x0760, 15, 0, 0, 0x1d1 },
1673 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 },
1674 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 },
1675 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 },
1676 .idfall_det_en = { 0x0680, 6, 6, 0, 1 },
1677 .idfall_det_st = { 0x0690, 6, 6, 0, 1 },
1678 .idfall_det_clr = { 0x06a0, 6, 6, 0, 1 },
1679 .idrise_det_en = { 0x0680, 5, 5, 0, 1 },
1680 .idrise_det_st = { 0x0690, 5, 5, 0, 1 },
1681 .idrise_det_clr = { 0x06a0, 5, 5, 0, 1 },
1682 .ls_det_en = { 0x0680, 2, 2, 0, 1 },
1683 .ls_det_st = { 0x0690, 2, 2, 0, 1 },
1684 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 },
1685 .utmi_bvalid = { 0x0480, 4, 4, 0, 1 },
1686 .utmi_id = { 0x0480, 1, 1, 0, 1 },
1687 .utmi_ls = { 0x0480, 3, 2, 0, 1 },
1688 },
1689 [USB2PHY_PORT_HOST] = {
1690 .phy_sus = { 0x0764, 15, 0, 0, 0x1d1 },
1691 .ls_det_en = { 0x0680, 4, 4, 0, 1 },
1692 .ls_det_st = { 0x0690, 4, 4, 0, 1 },
1693 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 }
1694 }
1695 },
1696 .chg_det = {
1697 .opmode = { 0x0760, 3, 0, 5, 1 },
1698 .cp_det = { 0x0884, 4, 4, 0, 1 },
1699 .dcp_det = { 0x0884, 3, 3, 0, 1 },
1700 .dp_det = { 0x0884, 5, 5, 0, 1 },
1701 .idm_sink_en = { 0x0768, 8, 8, 0, 1 },
1702 .idp_sink_en = { 0x0768, 7, 7, 0, 1 },
1703 .idp_src_en = { 0x0768, 9, 9, 0, 1 },
1704 .rdm_pdwn_en = { 0x0768, 10, 10, 0, 1 },
1705 .vdm_src_en = { 0x0768, 12, 12, 0, 1 },
1706 .vdp_src_en = { 0x0768, 11, 11, 0, 1 },
1707 },
1708 },
1709 {
1710 .reg = 0x800,
1711 .num_ports = 2,
1712 .clkout_ctl = { 0x0808, 4, 4, 1, 0 },
1713 .port_cfgs = {
1714 [USB2PHY_PORT_OTG] = {
1715 .phy_sus = { 0x800, 15, 0, 0, 0x1d1 },
1716 .ls_det_en = { 0x0684, 0, 0, 0, 1 },
1717 .ls_det_st = { 0x0694, 0, 0, 0, 1 },
1718 .ls_det_clr = { 0x06a4, 0, 0, 0, 1 }
1719 },
1720 [USB2PHY_PORT_HOST] = {
1721 .phy_sus = { 0x804, 15, 0, 0, 0x1d1 },
1722 .ls_det_en = { 0x0684, 1, 1, 0, 1 },
1723 .ls_det_st = { 0x0694, 1, 1, 0, 1 },
1724 .ls_det_clr = { 0x06a4, 1, 1, 0, 1 }
1725 }
1726 },
1727 },
1728 { /* sentinel */ }
1729 };
1730
1731 static const struct rockchip_usb2phy_cfg rk3308_phy_cfgs[] = {
1732 {
1733 .reg = 0x100,
1734 .num_ports = 2,
1735 .clkout_ctl = { 0x108, 4, 4, 1, 0 },
1736 .port_cfgs = {
1737 [USB2PHY_PORT_OTG] = {
1738 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 },
1739 .bvalid_det_en = { 0x3020, 3, 2, 0, 3 },
1740 .bvalid_det_st = { 0x3024, 3, 2, 0, 3 },
1741 .bvalid_det_clr = { 0x3028, 3, 2, 0, 3 },
1742 .idfall_det_en = { 0x3020, 5, 5, 0, 1 },
1743 .idfall_det_st = { 0x3024, 5, 5, 0, 1 },
1744 .idfall_det_clr = { 0x3028, 5, 5, 0, 1 },
1745 .idrise_det_en = { 0x3020, 4, 4, 0, 1 },
1746 .idrise_det_st = { 0x3024, 4, 4, 0, 1 },
1747 .idrise_det_clr = { 0x3028, 4, 4, 0, 1 },
1748 .ls_det_en = { 0x3020, 0, 0, 0, 1 },
1749 .ls_det_st = { 0x3024, 0, 0, 0, 1 },
1750 .ls_det_clr = { 0x3028, 0, 0, 0, 1 },
1751 .utmi_avalid = { 0x0120, 10, 10, 0, 1 },
1752 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 },
1753 .utmi_id = { 0x0120, 6, 6, 0, 1 },
1754 .utmi_ls = { 0x0120, 5, 4, 0, 1 },
1755 },
1756 [USB2PHY_PORT_HOST] = {
1757 .phy_sus = { 0x0104, 8, 0, 0, 0x1d1 },
1758 .ls_det_en = { 0x3020, 1, 1, 0, 1 },
1759 .ls_det_st = { 0x3024, 1, 1, 0, 1 },
1760 .ls_det_clr = { 0x3028, 1, 1, 0, 1 },
1761 .utmi_ls = { 0x0120, 17, 16, 0, 1 },
1762 .utmi_hstdet = { 0x0120, 19, 19, 0, 1 }
1763 }
1764 },
1765 .chg_det = {
1766 .opmode = { 0x0100, 3, 0, 5, 1 },
1767 .cp_det = { 0x0120, 24, 24, 0, 1 },
1768 .dcp_det = { 0x0120, 23, 23, 0, 1 },
1769 .dp_det = { 0x0120, 25, 25, 0, 1 },
1770 .idm_sink_en = { 0x0108, 8, 8, 0, 1 },
1771 .idp_sink_en = { 0x0108, 7, 7, 0, 1 },
1772 .idp_src_en = { 0x0108, 9, 9, 0, 1 },
1773 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 },
1774 .vdm_src_en = { 0x0108, 12, 12, 0, 1 },
1775 .vdp_src_en = { 0x0108, 11, 11, 0, 1 },
1776 },
1777 },
1778 { /* sentinel */ }
1779 };
1780
1781 static const struct rockchip_usb2phy_cfg rk3328_phy_cfgs[] = {
1782 {
1783 .reg = 0x100,
1784 .num_ports = 2,
1785 .clkout_ctl = { 0x108, 4, 4, 1, 0 },
1786 .port_cfgs = {
1787 [USB2PHY_PORT_OTG] = {
1788 .phy_sus = { 0x0100, 15, 0, 0, 0x1d1 },
1789 .bvalid_det_en = { 0x0110, 3, 2, 0, 3 },
1790 .bvalid_det_st = { 0x0114, 3, 2, 0, 3 },
1791 .bvalid_det_clr = { 0x0118, 3, 2, 0, 3 },
1792 .idfall_det_en = { 0x0110, 5, 5, 0, 1 },
1793 .idfall_det_st = { 0x0114, 5, 5, 0, 1 },
1794 .idfall_det_clr = { 0x0118, 5, 5, 0, 1 },
1795 .idrise_det_en = { 0x0110, 4, 4, 0, 1 },
1796 .idrise_det_st = { 0x0114, 4, 4, 0, 1 },
1797 .idrise_det_clr = { 0x0118, 4, 4, 0, 1 },
1798 .ls_det_en = { 0x0110, 0, 0, 0, 1 },
1799 .ls_det_st = { 0x0114, 0, 0, 0, 1 },
1800 .ls_det_clr = { 0x0118, 0, 0, 0, 1 },
1801 .utmi_avalid = { 0x0120, 10, 10, 0, 1 },
1802 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 },
1803 .utmi_id = { 0x0120, 6, 6, 0, 1 },
1804 .utmi_ls = { 0x0120, 5, 4, 0, 1 },
1805 },
1806 [USB2PHY_PORT_HOST] = {
1807 .phy_sus = { 0x104, 15, 0, 0, 0x1d1 },
1808 .ls_det_en = { 0x110, 1, 1, 0, 1 },
1809 .ls_det_st = { 0x114, 1, 1, 0, 1 },
1810 .ls_det_clr = { 0x118, 1, 1, 0, 1 },
1811 .utmi_ls = { 0x120, 17, 16, 0, 1 },
1812 .utmi_hstdet = { 0x120, 19, 19, 0, 1 }
1813 }
1814 },
1815 .chg_det = {
1816 .opmode = { 0x0100, 3, 0, 5, 1 },
1817 .cp_det = { 0x0120, 24, 24, 0, 1 },
1818 .dcp_det = { 0x0120, 23, 23, 0, 1 },
1819 .dp_det = { 0x0120, 25, 25, 0, 1 },
1820 .idm_sink_en = { 0x0108, 8, 8, 0, 1 },
1821 .idp_sink_en = { 0x0108, 7, 7, 0, 1 },
1822 .idp_src_en = { 0x0108, 9, 9, 0, 1 },
1823 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 },
1824 .vdm_src_en = { 0x0108, 12, 12, 0, 1 },
1825 .vdp_src_en = { 0x0108, 11, 11, 0, 1 },
1826 },
1827 },
1828 { /* sentinel */ }
1829 };
1830
1831 static const struct rockchip_usb2phy_cfg rk3366_phy_cfgs[] = {
1832 {
1833 .reg = 0x700,
1834 .num_ports = 2,
1835 .clkout_ctl = { 0x0724, 15, 15, 1, 0 },
1836 .port_cfgs = {
1837 [USB2PHY_PORT_HOST] = {
1838 .phy_sus = { 0x0728, 15, 0, 0, 0x1d1 },
1839 .ls_det_en = { 0x0680, 4, 4, 0, 1 },
1840 .ls_det_st = { 0x0690, 4, 4, 0, 1 },
1841 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 },
1842 .utmi_ls = { 0x049c, 14, 13, 0, 1 },
1843 .utmi_hstdet = { 0x049c, 12, 12, 0, 1 }
1844 }
1845 },
1846 },
1847 { /* sentinel */ }
1848 };
1849
1850 static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = {
1851 {
1852 .reg = 0xe450,
1853 .num_ports = 2,
1854 .clkout_ctl = { 0xe450, 4, 4, 1, 0 },
1855 .port_cfgs = {
1856 [USB2PHY_PORT_OTG] = {
1857 .phy_sus = { 0xe454, 1, 0, 2, 1 },
1858 .bvalid_det_en = { 0xe3c0, 3, 3, 0, 1 },
1859 .bvalid_det_st = { 0xe3e0, 3, 3, 0, 1 },
1860 .bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 },
1861 .idfall_det_en = { 0xe3c0, 5, 5, 0, 1 },
1862 .idfall_det_st = { 0xe3e0, 5, 5, 0, 1 },
1863 .idfall_det_clr = { 0xe3d0, 5, 5, 0, 1 },
1864 .idrise_det_en = { 0xe3c0, 4, 4, 0, 1 },
1865 .idrise_det_st = { 0xe3e0, 4, 4, 0, 1 },
1866 .idrise_det_clr = { 0xe3d0, 4, 4, 0, 1 },
1867 .utmi_avalid = { 0xe2ac, 7, 7, 0, 1 },
1868 .utmi_bvalid = { 0xe2ac, 12, 12, 0, 1 },
1869 .utmi_id = { 0xe2ac, 8, 8, 0, 1 },
1870 },
1871 [USB2PHY_PORT_HOST] = {
1872 .phy_sus = { 0xe458, 1, 0, 0x2, 0x1 },
1873 .ls_det_en = { 0xe3c0, 6, 6, 0, 1 },
1874 .ls_det_st = { 0xe3e0, 6, 6, 0, 1 },
1875 .ls_det_clr = { 0xe3d0, 6, 6, 0, 1 },
1876 .utmi_ls = { 0xe2ac, 22, 21, 0, 1 },
1877 .utmi_hstdet = { 0xe2ac, 23, 23, 0, 1 }
1878 }
1879 },
1880 .chg_det = {
1881 .opmode = { 0xe454, 3, 0, 5, 1 },
1882 .cp_det = { 0xe2ac, 2, 2, 0, 1 },
1883 .dcp_det = { 0xe2ac, 1, 1, 0, 1 },
1884 .dp_det = { 0xe2ac, 0, 0, 0, 1 },
1885 .idm_sink_en = { 0xe450, 8, 8, 0, 1 },
1886 .idp_sink_en = { 0xe450, 7, 7, 0, 1 },
1887 .idp_src_en = { 0xe450, 9, 9, 0, 1 },
1888 .rdm_pdwn_en = { 0xe450, 10, 10, 0, 1 },
1889 .vdm_src_en = { 0xe450, 12, 12, 0, 1 },
1890 .vdp_src_en = { 0xe450, 11, 11, 0, 1 },
1891 },
1892 },
1893 {
1894 .reg = 0xe460,
1895 .num_ports = 2,
1896 .clkout_ctl = { 0xe460, 4, 4, 1, 0 },
1897 .port_cfgs = {
1898 [USB2PHY_PORT_OTG] = {
1899 .phy_sus = { 0xe464, 1, 0, 2, 1 },
1900 .bvalid_det_en = { 0xe3c0, 8, 8, 0, 1 },
1901 .bvalid_det_st = { 0xe3e0, 8, 8, 0, 1 },
1902 .bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 },
1903 .idfall_det_en = { 0xe3c0, 10, 10, 0, 1 },
1904 .idfall_det_st = { 0xe3e0, 10, 10, 0, 1 },
1905 .idfall_det_clr = { 0xe3d0, 10, 10, 0, 1 },
1906 .idrise_det_en = { 0xe3c0, 9, 9, 0, 1 },
1907 .idrise_det_st = { 0xe3e0, 9, 9, 0, 1 },
1908 .idrise_det_clr = { 0xe3d0, 9, 9, 0, 1 },
1909 .utmi_avalid = { 0xe2ac, 10, 10, 0, 1 },
1910 .utmi_bvalid = { 0xe2ac, 16, 16, 0, 1 },
1911 .utmi_id = { 0xe2ac, 11, 11, 0, 1 },
1912 },
1913 [USB2PHY_PORT_HOST] = {
1914 .phy_sus = { 0xe468, 1, 0, 0x2, 0x1 },
1915 .ls_det_en = { 0xe3c0, 11, 11, 0, 1 },
1916 .ls_det_st = { 0xe3e0, 11, 11, 0, 1 },
1917 .ls_det_clr = { 0xe3d0, 11, 11, 0, 1 },
1918 .utmi_ls = { 0xe2ac, 26, 25, 0, 1 },
1919 .utmi_hstdet = { 0xe2ac, 27, 27, 0, 1 }
1920 }
1921 },
1922 },
1923 { /* sentinel */ }
1924 };
1925
1926 static const struct rockchip_usb2phy_cfg rk3562_phy_cfgs[] = {
1927 {
1928 .reg = 0xff740000,
1929 .num_ports = 2,
1930 .clkout_ctl = { 0x0108, 4, 4, 1, 0 },
1931 .port_cfgs = {
1932 [USB2PHY_PORT_OTG] = {
1933 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 },
1934 .bvalid_det_en = { 0x0110, 2, 2, 0, 1 },
1935 .bvalid_det_st = { 0x0114, 2, 2, 0, 1 },
1936 .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 },
1937 .idfall_det_en = { 0x0110, 5, 5, 0, 1 },
1938 .idfall_det_st = { 0x0114, 5, 5, 0, 1 },
1939 .idfall_det_clr = { 0x0118, 5, 5, 0, 1 },
1940 .idrise_det_en = { 0x0110, 4, 4, 0, 1 },
1941 .idrise_det_st = { 0x0114, 4, 4, 0, 1 },
1942 .idrise_det_clr = { 0x0118, 4, 4, 0, 1 },
1943 .ls_det_en = { 0x0110, 0, 0, 0, 1 },
1944 .ls_det_st = { 0x0114, 0, 0, 0, 1 },
1945 .ls_det_clr = { 0x0118, 0, 0, 0, 1 },
1946 .utmi_avalid = { 0x0120, 10, 10, 0, 1 },
1947 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 },
1948 .utmi_ls = { 0x0120, 5, 4, 0, 1 },
1949 },
1950 [USB2PHY_PORT_HOST] = {
1951 .phy_sus = { 0x0104, 8, 0, 0x1d2, 0x1d1 },
1952 .ls_det_en = { 0x0110, 1, 1, 0, 1 },
1953 .ls_det_st = { 0x0114, 1, 1, 0, 1 },
1954 .ls_det_clr = { 0x0118, 1, 1, 0, 1 },
1955 .utmi_ls = { 0x0120, 17, 16, 0, 1 },
1956 .utmi_hstdet = { 0x0120, 19, 19, 0, 1 }
1957 }
1958 },
1959 .chg_det = {
1960 .cp_det = { 0x0120, 24, 24, 0, 1 },
1961 .dcp_det = { 0x0120, 23, 23, 0, 1 },
1962 .dp_det = { 0x0120, 25, 25, 0, 1 },
1963 .idm_sink_en = { 0x0108, 8, 8, 0, 1 },
1964 .idp_sink_en = { 0x0108, 7, 7, 0, 1 },
1965 .idp_src_en = { 0x0108, 9, 9, 0, 1 },
1966 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 },
1967 .vdm_src_en = { 0x0108, 12, 12, 0, 1 },
1968 .vdp_src_en = { 0x0108, 11, 11, 0, 1 },
1969 },
1970 },
1971 { /* sentinel */ }
1972 };
1973
1974 static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = {
1975 {
1976 .reg = 0xfe8a0000,
1977 .num_ports = 2,
1978 .clkout_ctl = { 0x0008, 4, 4, 1, 0 },
1979 .port_cfgs = {
1980 [USB2PHY_PORT_OTG] = {
1981 .phy_sus = { 0x0000, 8, 0, 0, 0x1d1 },
1982 .bvalid_det_en = { 0x0080, 3, 2, 0, 3 },
1983 .bvalid_det_st = { 0x0084, 3, 2, 0, 3 },
1984 .bvalid_det_clr = { 0x0088, 3, 2, 0, 3 },
1985 .idfall_det_en = { 0x0080, 5, 5, 0, 1 },
1986 .idfall_det_st = { 0x0084, 5, 5, 0, 1 },
1987 .idfall_det_clr = { 0x0088, 5, 5, 0, 1 },
1988 .idrise_det_en = { 0x0080, 4, 4, 0, 1 },
1989 .idrise_det_st = { 0x0084, 4, 4, 0, 1 },
1990 .idrise_det_clr = { 0x0088, 4, 4, 0, 1 },
1991 .utmi_avalid = { 0x00c0, 10, 10, 0, 1 },
1992 .utmi_bvalid = { 0x00c0, 9, 9, 0, 1 },
1993 .utmi_id = { 0x00c0, 6, 6, 0, 1 },
1994 },
1995 [USB2PHY_PORT_HOST] = {
1996 /* Select suspend control from controller */
1997 .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d2 },
1998 .ls_det_en = { 0x0080, 1, 1, 0, 1 },
1999 .ls_det_st = { 0x0084, 1, 1, 0, 1 },
2000 .ls_det_clr = { 0x0088, 1, 1, 0, 1 },
2001 .utmi_ls = { 0x00c0, 17, 16, 0, 1 },
2002 .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 }
2003 }
2004 },
2005 .chg_det = {
2006 .opmode = { 0x0000, 3, 0, 5, 1 },
2007 .cp_det = { 0x00c0, 24, 24, 0, 1 },
2008 .dcp_det = { 0x00c0, 23, 23, 0, 1 },
2009 .dp_det = { 0x00c0, 25, 25, 0, 1 },
2010 .idm_sink_en = { 0x0008, 8, 8, 0, 1 },
2011 .idp_sink_en = { 0x0008, 7, 7, 0, 1 },
2012 .idp_src_en = { 0x0008, 9, 9, 0, 1 },
2013 .rdm_pdwn_en = { 0x0008, 10, 10, 0, 1 },
2014 .vdm_src_en = { 0x0008, 12, 12, 0, 1 },
2015 .vdp_src_en = { 0x0008, 11, 11, 0, 1 },
2016 },
2017 },
2018 {
2019 .reg = 0xfe8b0000,
2020 .num_ports = 2,
2021 .clkout_ctl = { 0x0008, 4, 4, 1, 0 },
2022 .port_cfgs = {
2023 [USB2PHY_PORT_OTG] = {
2024 .phy_sus = { 0x0000, 8, 0, 0x1d2, 0x1d1 },
2025 .ls_det_en = { 0x0080, 0, 0, 0, 1 },
2026 .ls_det_st = { 0x0084, 0, 0, 0, 1 },
2027 .ls_det_clr = { 0x0088, 0, 0, 0, 1 },
2028 .utmi_ls = { 0x00c0, 5, 4, 0, 1 },
2029 .utmi_hstdet = { 0x00c0, 7, 7, 0, 1 }
2030 },
2031 [USB2PHY_PORT_HOST] = {
2032 .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 },
2033 .ls_det_en = { 0x0080, 1, 1, 0, 1 },
2034 .ls_det_st = { 0x0084, 1, 1, 0, 1 },
2035 .ls_det_clr = { 0x0088, 1, 1, 0, 1 },
2036 .utmi_ls = { 0x00c0, 17, 16, 0, 1 },
2037 .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 }
2038 }
2039 },
2040 },
2041 { /* sentinel */ }
2042 };
2043
2044 static const struct rockchip_usb2phy_cfg rk3576_phy_cfgs[] = {
2045 {
2046 .reg = 0x0,
2047 .num_ports = 1,
2048 .phy_tuning = rk3576_usb2phy_tuning,
2049 .clkout_ctl = { 0x0008, 0, 0, 1, 0 },
2050 .port_cfgs = {
2051 [USB2PHY_PORT_OTG] = {
2052 .phy_sus = { 0x0000, 8, 0, 0, 0x1d1 },
2053 .bvalid_det_en = { 0x00c0, 1, 1, 0, 1 },
2054 .bvalid_det_st = { 0x00c4, 1, 1, 0, 1 },
2055 .bvalid_det_clr = { 0x00c8, 1, 1, 0, 1 },
2056 .ls_det_en = { 0x00c0, 0, 0, 0, 1 },
2057 .ls_det_st = { 0x00c4, 0, 0, 0, 1 },
2058 .ls_det_clr = { 0x00c8, 0, 0, 0, 1 },
2059 .disfall_en = { 0x00c0, 6, 6, 0, 1 },
2060 .disfall_st = { 0x00c4, 6, 6, 0, 1 },
2061 .disfall_clr = { 0x00c8, 6, 6, 0, 1 },
2062 .disrise_en = { 0x00c0, 5, 5, 0, 1 },
2063 .disrise_st = { 0x00c4, 5, 5, 0, 1 },
2064 .disrise_clr = { 0x00c8, 5, 5, 0, 1 },
2065 .utmi_avalid = { 0x0080, 1, 1, 0, 1 },
2066 .utmi_bvalid = { 0x0080, 0, 0, 0, 1 },
2067 .utmi_ls = { 0x0080, 5, 4, 0, 1 },
2068 }
2069 },
2070 .chg_det = {
2071 .cp_det = { 0x0080, 8, 8, 0, 1 },
2072 .dcp_det = { 0x0080, 8, 8, 0, 1 },
2073 .dp_det = { 0x0080, 9, 9, 1, 0 },
2074 .idm_sink_en = { 0x0010, 5, 5, 1, 0 },
2075 .idp_sink_en = { 0x0010, 5, 5, 0, 1 },
2076 .idp_src_en = { 0x0010, 14, 14, 0, 1 },
2077 .rdm_pdwn_en = { 0x0010, 14, 14, 0, 1 },
2078 .vdm_src_en = { 0x0010, 7, 6, 0, 3 },
2079 .vdp_src_en = { 0x0010, 7, 6, 0, 3 },
2080 },
2081 },
2082 {
2083 .reg = 0x2000,
2084 .num_ports = 1,
2085 .phy_tuning = rk3576_usb2phy_tuning,
2086 .clkout_ctl = { 0x2008, 0, 0, 1, 0 },
2087 .port_cfgs = {
2088 [USB2PHY_PORT_OTG] = {
2089 .phy_sus = { 0x2000, 8, 0, 0, 0x1d1 },
2090 .bvalid_det_en = { 0x20c0, 1, 1, 0, 1 },
2091 .bvalid_det_st = { 0x20c4, 1, 1, 0, 1 },
2092 .bvalid_det_clr = { 0x20c8, 1, 1, 0, 1 },
2093 .ls_det_en = { 0x20c0, 0, 0, 0, 1 },
2094 .ls_det_st = { 0x20c4, 0, 0, 0, 1 },
2095 .ls_det_clr = { 0x20c8, 0, 0, 0, 1 },
2096 .disfall_en = { 0x20c0, 6, 6, 0, 1 },
2097 .disfall_st = { 0x20c4, 6, 6, 0, 1 },
2098 .disfall_clr = { 0x20c8, 6, 6, 0, 1 },
2099 .disrise_en = { 0x20c0, 5, 5, 0, 1 },
2100 .disrise_st = { 0x20c4, 5, 5, 0, 1 },
2101 .disrise_clr = { 0x20c8, 5, 5, 0, 1 },
2102 .utmi_avalid = { 0x2080, 1, 1, 0, 1 },
2103 .utmi_bvalid = { 0x2080, 0, 0, 0, 1 },
2104 .utmi_ls = { 0x2080, 5, 4, 0, 1 },
2105 }
2106 },
2107 .chg_det = {
2108 .cp_det = { 0x2080, 8, 8, 0, 1 },
2109 .dcp_det = { 0x2080, 8, 8, 0, 1 },
2110 .dp_det = { 0x2080, 9, 9, 1, 0 },
2111 .idm_sink_en = { 0x2010, 5, 5, 1, 0 },
2112 .idp_sink_en = { 0x2010, 5, 5, 0, 1 },
2113 .idp_src_en = { 0x2010, 14, 14, 0, 1 },
2114 .rdm_pdwn_en = { 0x2010, 14, 14, 0, 1 },
2115 .vdm_src_en = { 0x2010, 7, 6, 0, 3 },
2116 .vdp_src_en = { 0x2010, 7, 6, 0, 3 },
2117 },
2118 },
2119 { /* sentinel */ }
2120 };
2121
2122 static const struct rockchip_usb2phy_cfg rk3588_phy_cfgs[] = {
2123 {
2124 .reg = 0x0000,
2125 .num_ports = 1,
2126 .phy_tuning = rk3588_usb2phy_tuning,
2127 .clkout_ctl = { 0x0000, 0, 0, 1, 0 },
2128 .port_cfgs = {
2129 [USB2PHY_PORT_OTG] = {
2130 .phy_sus = { 0x000c, 11, 11, 0, 1 },
2131 .bvalid_det_en = { 0x0080, 1, 1, 0, 1 },
2132 .bvalid_det_st = { 0x0084, 1, 1, 0, 1 },
2133 .bvalid_det_clr = { 0x0088, 1, 1, 0, 1 },
2134 .ls_det_en = { 0x0080, 0, 0, 0, 1 },
2135 .ls_det_st = { 0x0084, 0, 0, 0, 1 },
2136 .ls_det_clr = { 0x0088, 0, 0, 0, 1 },
2137 .disfall_en = { 0x0080, 6, 6, 0, 1 },
2138 .disfall_st = { 0x0084, 6, 6, 0, 1 },
2139 .disfall_clr = { 0x0088, 6, 6, 0, 1 },
2140 .disrise_en = { 0x0080, 5, 5, 0, 1 },
2141 .disrise_st = { 0x0084, 5, 5, 0, 1 },
2142 .disrise_clr = { 0x0088, 5, 5, 0, 1 },
2143 .utmi_avalid = { 0x00c0, 7, 7, 0, 1 },
2144 .utmi_bvalid = { 0x00c0, 6, 6, 0, 1 },
2145 .utmi_ls = { 0x00c0, 10, 9, 0, 1 },
2146 }
2147 },
2148 .chg_det = {
2149 .cp_det = { 0x00c0, 0, 0, 0, 1 },
2150 .dcp_det = { 0x00c0, 0, 0, 0, 1 },
2151 .dp_det = { 0x00c0, 1, 1, 1, 0 },
2152 .idm_sink_en = { 0x0008, 5, 5, 1, 0 },
2153 .idp_sink_en = { 0x0008, 5, 5, 0, 1 },
2154 .idp_src_en = { 0x0008, 14, 14, 0, 1 },
2155 .rdm_pdwn_en = { 0x0008, 14, 14, 0, 1 },
2156 .vdm_src_en = { 0x0008, 7, 6, 0, 3 },
2157 .vdp_src_en = { 0x0008, 7, 6, 0, 3 },
2158 },
2159 },
2160 {
2161 .reg = 0x4000,
2162 .num_ports = 1,
2163 .phy_tuning = rk3588_usb2phy_tuning,
2164 .clkout_ctl = { 0x0000, 0, 0, 1, 0 },
2165 .port_cfgs = {
2166 [USB2PHY_PORT_OTG] = {
2167 .phy_sus = { 0x000c, 11, 11, 0, 1 },
2168 .bvalid_det_en = { 0x0080, 1, 1, 0, 1 },
2169 .bvalid_det_st = { 0x0084, 1, 1, 0, 1 },
2170 .bvalid_det_clr = { 0x0088, 1, 1, 0, 1 },
2171 .ls_det_en = { 0x0080, 0, 0, 0, 1 },
2172 .ls_det_st = { 0x0084, 0, 0, 0, 1 },
2173 .ls_det_clr = { 0x0088, 0, 0, 0, 1 },
2174 .disfall_en = { 0x0080, 6, 6, 0, 1 },
2175 .disfall_st = { 0x0084, 6, 6, 0, 1 },
2176 .disfall_clr = { 0x0088, 6, 6, 0, 1 },
2177 .disrise_en = { 0x0080, 5, 5, 0, 1 },
2178 .disrise_st = { 0x0084, 5, 5, 0, 1 },
2179 .disrise_clr = { 0x0088, 5, 5, 0, 1 },
2180 .utmi_avalid = { 0x00c0, 7, 7, 0, 1 },
2181 .utmi_bvalid = { 0x00c0, 6, 6, 0, 1 },
2182 .utmi_ls = { 0x00c0, 10, 9, 0, 1 },
2183 }
2184 },
2185 .chg_det = {
2186 .cp_det = { 0x00c0, 0, 0, 0, 1 },
2187 .dcp_det = { 0x00c0, 0, 0, 0, 1 },
2188 .dp_det = { 0x00c0, 1, 1, 1, 0 },
2189 .idm_sink_en = { 0x0008, 5, 5, 1, 0 },
2190 .idp_sink_en = { 0x0008, 5, 5, 0, 1 },
2191 .idp_src_en = { 0x0008, 14, 14, 0, 1 },
2192 .rdm_pdwn_en = { 0x0008, 14, 14, 0, 1 },
2193 .vdm_src_en = { 0x0008, 7, 6, 0, 3 },
2194 .vdp_src_en = { 0x0008, 7, 6, 0, 3 },
2195 },
2196 },
2197 {
2198 .reg = 0x8000,
2199 .num_ports = 1,
2200 .phy_tuning = rk3588_usb2phy_tuning,
2201 .clkout_ctl = { 0x0000, 0, 0, 1, 0 },
2202 .port_cfgs = {
2203 [USB2PHY_PORT_HOST] = {
2204 .phy_sus = { 0x0008, 2, 2, 0, 1 },
2205 .ls_det_en = { 0x0080, 0, 0, 0, 1 },
2206 .ls_det_st = { 0x0084, 0, 0, 0, 1 },
2207 .ls_det_clr = { 0x0088, 0, 0, 0, 1 },
2208 .disfall_en = { 0x0080, 6, 6, 0, 1 },
2209 .disfall_st = { 0x0084, 6, 6, 0, 1 },
2210 .disfall_clr = { 0x0088, 6, 6, 0, 1 },
2211 .disrise_en = { 0x0080, 5, 5, 0, 1 },
2212 .disrise_st = { 0x0084, 5, 5, 0, 1 },
2213 .disrise_clr = { 0x0088, 5, 5, 0, 1 },
2214 .utmi_ls = { 0x00c0, 10, 9, 0, 1 },
2215 }
2216 },
2217 },
2218 {
2219 .reg = 0xc000,
2220 .num_ports = 1,
2221 .phy_tuning = rk3588_usb2phy_tuning,
2222 .clkout_ctl = { 0x0000, 0, 0, 1, 0 },
2223 .port_cfgs = {
2224 [USB2PHY_PORT_HOST] = {
2225 .phy_sus = { 0x0008, 2, 2, 0, 1 },
2226 .ls_det_en = { 0x0080, 0, 0, 0, 1 },
2227 .ls_det_st = { 0x0084, 0, 0, 0, 1 },
2228 .ls_det_clr = { 0x0088, 0, 0, 0, 1 },
2229 .disfall_en = { 0x0080, 6, 6, 0, 1 },
2230 .disfall_st = { 0x0084, 6, 6, 0, 1 },
2231 .disfall_clr = { 0x0088, 6, 6, 0, 1 },
2232 .disrise_en = { 0x0080, 5, 5, 0, 1 },
2233 .disrise_st = { 0x0084, 5, 5, 0, 1 },
2234 .disrise_clr = { 0x0088, 5, 5, 0, 1 },
2235 .utmi_ls = { 0x00c0, 10, 9, 0, 1 },
2236 }
2237 },
2238 },
2239 { /* sentinel */ }
2240 };
2241
2242 static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = {
2243 {
2244 .reg = 0x100,
2245 .num_ports = 2,
2246 .clkout_ctl = { 0x108, 4, 4, 1, 0 },
2247 .port_cfgs = {
2248 [USB2PHY_PORT_OTG] = {
2249 .phy_sus = { 0x0100, 15, 0, 0, 0x1d1 },
2250 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 },
2251 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 },
2252 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 },
2253 .ls_det_en = { 0x0680, 2, 2, 0, 1 },
2254 .ls_det_st = { 0x0690, 2, 2, 0, 1 },
2255 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 },
2256 .utmi_bvalid = { 0x0804, 10, 10, 0, 1 },
2257 .utmi_ls = { 0x0804, 13, 12, 0, 1 },
2258 },
2259 [USB2PHY_PORT_HOST] = {
2260 .phy_sus = { 0x0104, 15, 0, 0, 0x1d1 },
2261 .ls_det_en = { 0x0680, 4, 4, 0, 1 },
2262 .ls_det_st = { 0x0690, 4, 4, 0, 1 },
2263 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 },
2264 .utmi_ls = { 0x0804, 9, 8, 0, 1 },
2265 .utmi_hstdet = { 0x0804, 7, 7, 0, 1 }
2266 }
2267 },
2268 .chg_det = {
2269 .opmode = { 0x0100, 3, 0, 5, 1 },
2270 .cp_det = { 0x0804, 1, 1, 0, 1 },
2271 .dcp_det = { 0x0804, 0, 0, 0, 1 },
2272 .dp_det = { 0x0804, 2, 2, 0, 1 },
2273 .idm_sink_en = { 0x0108, 8, 8, 0, 1 },
2274 .idp_sink_en = { 0x0108, 7, 7, 0, 1 },
2275 .idp_src_en = { 0x0108, 9, 9, 0, 1 },
2276 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 },
2277 .vdm_src_en = { 0x0108, 12, 12, 0, 1 },
2278 .vdp_src_en = { 0x0108, 11, 11, 0, 1 },
2279 },
2280 },
2281 { /* sentinel */ }
2282 };
2283
2284 static const struct of_device_id rockchip_usb2phy_dt_match[] = {
2285 { .compatible = "rockchip,px30-usb2phy", .data = &rk3328_phy_cfgs },
2286 { .compatible = "rockchip,rk3036-usb2phy", .data = &rk3036_phy_cfgs },
2287 { .compatible = "rockchip,rk3128-usb2phy", .data = &rk3128_phy_cfgs },
2288 { .compatible = "rockchip,rk3228-usb2phy", .data = &rk3228_phy_cfgs },
2289 { .compatible = "rockchip,rk3308-usb2phy", .data = &rk3308_phy_cfgs },
2290 { .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs },
2291 { .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
2292 { .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },
2293 { .compatible = "rockchip,rk3562-usb2phy", .data = &rk3562_phy_cfgs },
2294 { .compatible = "rockchip,rk3568-usb2phy", .data = &rk3568_phy_cfgs },
2295 { .compatible = "rockchip,rk3576-usb2phy", .data = &rk3576_phy_cfgs },
2296 { .compatible = "rockchip,rk3588-usb2phy", .data = &rk3588_phy_cfgs },
2297 { .compatible = "rockchip,rv1108-usb2phy", .data = &rv1108_phy_cfgs },
2298 {}
2299 };
2300 MODULE_DEVICE_TABLE(of, rockchip_usb2phy_dt_match);
2301
2302 static struct platform_driver rockchip_usb2phy_driver = {
2303 .probe = rockchip_usb2phy_probe,
2304 .driver = {
2305 .name = "rockchip-usb2phy",
2306 .of_match_table = rockchip_usb2phy_dt_match,
2307 },
2308 };
2309 module_platform_driver(rockchip_usb2phy_driver);
2310
2311 MODULE_AUTHOR("Frank Wang <frank.wang@rock-chips.com>");
2312 MODULE_DESCRIPTION("Rockchip USB2.0 PHY driver");
2313 MODULE_LICENSE("GPL v2");
2314