1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * AD7606 SPI ADC driver 4 * 5 * Copyright 2011 Analog Devices Inc. 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/device.h> 10 #include <linux/err.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/interrupt.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/property.h> 16 #include <linux/pwm.h> 17 #include <linux/regulator/consumer.h> 18 #include <linux/sched.h> 19 #include <linux/slab.h> 20 #include <linux/sysfs.h> 21 #include <linux/units.h> 22 #include <linux/util_macros.h> 23 24 #include <linux/iio/backend.h> 25 #include <linux/iio/buffer.h> 26 #include <linux/iio/iio.h> 27 #include <linux/iio/sysfs.h> 28 #include <linux/iio/trigger.h> 29 #include <linux/iio/triggered_buffer.h> 30 #include <linux/iio/trigger_consumer.h> 31 32 #include "ad7606.h" 33 34 /* 35 * Scales are computed as 5000/32768 and 10000/32768 respectively, 36 * so that when applied to the raw values they provide mV values. 37 * The scale arrays are kept as IIO_VAL_INT_PLUS_MICRO, so index 38 * X is the integer part and X + 1 is the fractional part. 39 */ 40 static const unsigned int ad7606_16bit_hw_scale_avail[2][2] = { 41 { 0, 152588 }, { 0, 305176 } 42 }; 43 44 static const unsigned int ad7606_18bit_hw_scale_avail[2][2] = { 45 { 0, 38147 }, { 0, 76294 } 46 }; 47 48 static const unsigned int ad7606c_16bit_single_ended_unipolar_scale_avail[3][2] = { 49 { 0, 76294 }, { 0, 152588 }, { 0, 190735 } 50 }; 51 52 static const unsigned int ad7606c_16bit_single_ended_bipolar_scale_avail[5][2] = { 53 { 0, 76294 }, { 0, 152588 }, { 0, 190735 }, { 0, 305176 }, { 0, 381470 } 54 }; 55 56 static const unsigned int ad7606c_16bit_differential_bipolar_scale_avail[4][2] = { 57 { 0, 152588 }, { 0, 305176 }, { 0, 381470 }, { 0, 610352 } 58 }; 59 60 static const unsigned int ad7606c_18bit_single_ended_unipolar_scale_avail[3][2] = { 61 { 0, 19073 }, { 0, 38147 }, { 0, 47684 } 62 }; 63 64 static const unsigned int ad7606c_18bit_single_ended_bipolar_scale_avail[5][2] = { 65 { 0, 19073 }, { 0, 38147 }, { 0, 47684 }, { 0, 76294 }, { 0, 95367 } 66 }; 67 68 static const unsigned int ad7606c_18bit_differential_bipolar_scale_avail[4][2] = { 69 { 0, 38147 }, { 0, 76294 }, { 0, 95367 }, { 0, 152588 } 70 }; 71 72 static const unsigned int ad7606_16bit_sw_scale_avail[3][2] = { 73 { 0, 76293 }, { 0, 152588 }, { 0, 305176 } 74 }; 75 76 static const unsigned int ad7607_hw_scale_avail[2][2] = { 77 { 0, 610352 }, { 1, 220703 } 78 }; 79 80 static const unsigned int ad7609_hw_scale_avail[2][2] = { 81 { 0, 152588 }, { 0, 305176 } 82 }; 83 84 static const unsigned int ad7606_oversampling_avail[7] = { 85 1, 2, 4, 8, 16, 32, 64, 86 }; 87 88 static const unsigned int ad7616_oversampling_avail[8] = { 89 1, 2, 4, 8, 16, 32, 64, 128, 90 }; 91 92 static const struct iio_chan_spec ad7605_channels[] = { 93 IIO_CHAN_SOFT_TIMESTAMP(4), 94 AD7605_CHANNEL(0), 95 AD7605_CHANNEL(1), 96 AD7605_CHANNEL(2), 97 AD7605_CHANNEL(3), 98 }; 99 100 static const struct iio_chan_spec ad7606_channels_16bit[] = { 101 IIO_CHAN_SOFT_TIMESTAMP(8), 102 AD7606_CHANNEL(0, 16), 103 AD7606_CHANNEL(1, 16), 104 AD7606_CHANNEL(2, 16), 105 AD7606_CHANNEL(3, 16), 106 AD7606_CHANNEL(4, 16), 107 AD7606_CHANNEL(5, 16), 108 AD7606_CHANNEL(6, 16), 109 AD7606_CHANNEL(7, 16), 110 }; 111 112 static const struct iio_chan_spec ad7606_channels_18bit[] = { 113 IIO_CHAN_SOFT_TIMESTAMP(8), 114 AD7606_CHANNEL(0, 18), 115 AD7606_CHANNEL(1, 18), 116 AD7606_CHANNEL(2, 18), 117 AD7606_CHANNEL(3, 18), 118 AD7606_CHANNEL(4, 18), 119 AD7606_CHANNEL(5, 18), 120 AD7606_CHANNEL(6, 18), 121 AD7606_CHANNEL(7, 18), 122 }; 123 124 static const struct iio_chan_spec ad7607_channels[] = { 125 IIO_CHAN_SOFT_TIMESTAMP(8), 126 AD7606_CHANNEL(0, 14), 127 AD7606_CHANNEL(1, 14), 128 AD7606_CHANNEL(2, 14), 129 AD7606_CHANNEL(3, 14), 130 AD7606_CHANNEL(4, 14), 131 AD7606_CHANNEL(5, 14), 132 AD7606_CHANNEL(6, 14), 133 AD7606_CHANNEL(7, 14), 134 }; 135 136 static const struct iio_chan_spec ad7608_channels[] = { 137 IIO_CHAN_SOFT_TIMESTAMP(8), 138 AD7606_CHANNEL(0, 18), 139 AD7606_CHANNEL(1, 18), 140 AD7606_CHANNEL(2, 18), 141 AD7606_CHANNEL(3, 18), 142 AD7606_CHANNEL(4, 18), 143 AD7606_CHANNEL(5, 18), 144 AD7606_CHANNEL(6, 18), 145 AD7606_CHANNEL(7, 18), 146 }; 147 148 /* 149 * The current assumption that this driver makes for AD7616, is that it's 150 * working in Hardware Mode with Serial, Burst and Sequencer modes activated. 151 * To activate them, following pins must be pulled high: 152 * -SER/PAR 153 * -SEQEN 154 * And following pins must be pulled low: 155 * -WR/BURST 156 * -DB4/SER1W 157 */ 158 static const struct iio_chan_spec ad7616_channels[] = { 159 IIO_CHAN_SOFT_TIMESTAMP(16), 160 AD7606_CHANNEL(0, 16), 161 AD7606_CHANNEL(1, 16), 162 AD7606_CHANNEL(2, 16), 163 AD7606_CHANNEL(3, 16), 164 AD7606_CHANNEL(4, 16), 165 AD7606_CHANNEL(5, 16), 166 AD7606_CHANNEL(6, 16), 167 AD7606_CHANNEL(7, 16), 168 AD7606_CHANNEL(8, 16), 169 AD7606_CHANNEL(9, 16), 170 AD7606_CHANNEL(10, 16), 171 AD7606_CHANNEL(11, 16), 172 AD7606_CHANNEL(12, 16), 173 AD7606_CHANNEL(13, 16), 174 AD7606_CHANNEL(14, 16), 175 AD7606_CHANNEL(15, 16), 176 }; 177 178 static int ad7606c_18bit_chan_scale_setup(struct iio_dev *indio_dev, 179 struct iio_chan_spec *chan, int ch); 180 static int ad7606c_16bit_chan_scale_setup(struct iio_dev *indio_dev, 181 struct iio_chan_spec *chan, int ch); 182 static int ad7606_16bit_chan_scale_setup(struct iio_dev *indio_dev, 183 struct iio_chan_spec *chan, int ch); 184 static int ad7607_chan_scale_setup(struct iio_dev *indio_dev, 185 struct iio_chan_spec *chan, int ch); 186 static int ad7608_chan_scale_setup(struct iio_dev *indio_dev, 187 struct iio_chan_spec *chan, int ch); 188 static int ad7609_chan_scale_setup(struct iio_dev *indio_dev, 189 struct iio_chan_spec *chan, int ch); 190 191 const struct ad7606_chip_info ad7605_4_info = { 192 .channels = ad7605_channels, 193 .name = "ad7605-4", 194 .num_adc_channels = 4, 195 .num_channels = 5, 196 .scale_setup_cb = ad7606_16bit_chan_scale_setup, 197 }; 198 EXPORT_SYMBOL_NS_GPL(ad7605_4_info, "IIO_AD7606"); 199 200 const struct ad7606_chip_info ad7606_8_info = { 201 .channels = ad7606_channels_16bit, 202 .name = "ad7606-8", 203 .num_adc_channels = 8, 204 .num_channels = 9, 205 .oversampling_avail = ad7606_oversampling_avail, 206 .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), 207 .scale_setup_cb = ad7606_16bit_chan_scale_setup, 208 }; 209 EXPORT_SYMBOL_NS_GPL(ad7606_8_info, "IIO_AD7606"); 210 211 const struct ad7606_chip_info ad7606_6_info = { 212 .channels = ad7606_channels_16bit, 213 .name = "ad7606-6", 214 .num_adc_channels = 6, 215 .num_channels = 7, 216 .oversampling_avail = ad7606_oversampling_avail, 217 .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), 218 .scale_setup_cb = ad7606_16bit_chan_scale_setup, 219 }; 220 EXPORT_SYMBOL_NS_GPL(ad7606_6_info, "IIO_AD7606"); 221 222 const struct ad7606_chip_info ad7606_4_info = { 223 .channels = ad7606_channels_16bit, 224 .name = "ad7606-4", 225 .num_adc_channels = 4, 226 .num_channels = 5, 227 .oversampling_avail = ad7606_oversampling_avail, 228 .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), 229 .scale_setup_cb = ad7606_16bit_chan_scale_setup, 230 }; 231 EXPORT_SYMBOL_NS_GPL(ad7606_4_info, "IIO_AD7606"); 232 233 const struct ad7606_chip_info ad7606b_info = { 234 .channels = ad7606_channels_16bit, 235 .max_samplerate = 800 * KILO, 236 .name = "ad7606b", 237 .num_adc_channels = 8, 238 .num_channels = 9, 239 .oversampling_avail = ad7606_oversampling_avail, 240 .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), 241 .scale_setup_cb = ad7606_16bit_chan_scale_setup, 242 }; 243 EXPORT_SYMBOL_NS_GPL(ad7606b_info, "IIO_AD7606"); 244 245 const struct ad7606_chip_info ad7606c_16_info = { 246 .channels = ad7606_channels_16bit, 247 .name = "ad7606c16", 248 .num_adc_channels = 8, 249 .num_channels = 9, 250 .oversampling_avail = ad7606_oversampling_avail, 251 .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), 252 .scale_setup_cb = ad7606c_16bit_chan_scale_setup, 253 }; 254 EXPORT_SYMBOL_NS_GPL(ad7606c_16_info, "IIO_AD7606"); 255 256 const struct ad7606_chip_info ad7607_info = { 257 .channels = ad7607_channels, 258 .name = "ad7607", 259 .num_adc_channels = 8, 260 .num_channels = 9, 261 .oversampling_avail = ad7606_oversampling_avail, 262 .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), 263 .scale_setup_cb = ad7607_chan_scale_setup, 264 }; 265 EXPORT_SYMBOL_NS_GPL(ad7607_info, "IIO_AD7606"); 266 267 const struct ad7606_chip_info ad7608_info = { 268 .channels = ad7608_channels, 269 .name = "ad7608", 270 .num_adc_channels = 8, 271 .num_channels = 9, 272 .oversampling_avail = ad7606_oversampling_avail, 273 .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), 274 .scale_setup_cb = ad7608_chan_scale_setup, 275 }; 276 EXPORT_SYMBOL_NS_GPL(ad7608_info, "IIO_AD7606"); 277 278 const struct ad7606_chip_info ad7609_info = { 279 .channels = ad7608_channels, 280 .name = "ad7609", 281 .num_adc_channels = 8, 282 .num_channels = 9, 283 .oversampling_avail = ad7606_oversampling_avail, 284 .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), 285 .scale_setup_cb = ad7609_chan_scale_setup, 286 }; 287 EXPORT_SYMBOL_NS_GPL(ad7609_info, "IIO_AD7606"); 288 289 const struct ad7606_chip_info ad7606c_18_info = { 290 .channels = ad7606_channels_18bit, 291 .name = "ad7606c18", 292 .num_adc_channels = 8, 293 .num_channels = 9, 294 .oversampling_avail = ad7606_oversampling_avail, 295 .oversampling_num = ARRAY_SIZE(ad7606_oversampling_avail), 296 .scale_setup_cb = ad7606c_18bit_chan_scale_setup, 297 }; 298 EXPORT_SYMBOL_NS_GPL(ad7606c_18_info, "IIO_AD7606"); 299 300 const struct ad7606_chip_info ad7616_info = { 301 .channels = ad7616_channels, 302 .init_delay_ms = 15, 303 .name = "ad7616", 304 .num_adc_channels = 16, 305 .num_channels = 17, 306 .oversampling_avail = ad7616_oversampling_avail, 307 .oversampling_num = ARRAY_SIZE(ad7616_oversampling_avail), 308 .os_req_reset = true, 309 .scale_setup_cb = ad7606_16bit_chan_scale_setup, 310 }; 311 EXPORT_SYMBOL_NS_GPL(ad7616_info, "IIO_AD7606"); 312 313 int ad7606_reset(struct ad7606_state *st) 314 { 315 if (st->gpio_reset) { 316 gpiod_set_value(st->gpio_reset, 1); 317 ndelay(100); /* t_reset >= 100ns */ 318 gpiod_set_value(st->gpio_reset, 0); 319 return 0; 320 } 321 322 return -ENODEV; 323 } 324 EXPORT_SYMBOL_NS_GPL(ad7606_reset, "IIO_AD7606"); 325 326 static int ad7606_16bit_chan_scale_setup(struct iio_dev *indio_dev, 327 struct iio_chan_spec *chan, int ch) 328 { 329 struct ad7606_state *st = iio_priv(indio_dev); 330 struct ad7606_chan_scale *cs = &st->chan_scales[ch]; 331 332 if (!st->sw_mode_en) { 333 /* tied to logic low, analog input range is +/- 5V */ 334 cs->range = 0; 335 cs->scale_avail = ad7606_16bit_hw_scale_avail; 336 cs->num_scales = ARRAY_SIZE(ad7606_16bit_hw_scale_avail); 337 return 0; 338 } 339 340 /* Scale of 0.076293 is only available in sw mode */ 341 /* After reset, in software mode, ±10 V is set by default */ 342 cs->range = 2; 343 cs->scale_avail = ad7606_16bit_sw_scale_avail; 344 cs->num_scales = ARRAY_SIZE(ad7606_16bit_sw_scale_avail); 345 346 return 0; 347 } 348 349 static int ad7606_get_chan_config(struct iio_dev *indio_dev, int ch, 350 bool *bipolar, bool *differential) 351 { 352 struct ad7606_state *st = iio_priv(indio_dev); 353 unsigned int num_channels = st->chip_info->num_adc_channels; 354 unsigned int offset = indio_dev->num_channels - st->chip_info->num_adc_channels; 355 struct device *dev = st->dev; 356 int ret; 357 358 *bipolar = false; 359 *differential = false; 360 361 device_for_each_child_node_scoped(dev, child) { 362 u32 pins[2]; 363 int reg; 364 365 ret = fwnode_property_read_u32(child, "reg", ®); 366 if (ret) 367 continue; 368 369 /* channel number (here) is from 1 to num_channels */ 370 if (reg < offset || reg > num_channels) { 371 dev_warn(dev, 372 "Invalid channel number (ignoring): %d\n", reg); 373 continue; 374 } 375 376 if (reg != (ch + 1)) 377 continue; 378 379 *bipolar = fwnode_property_read_bool(child, "bipolar"); 380 381 ret = fwnode_property_read_u32_array(child, "diff-channels", 382 pins, ARRAY_SIZE(pins)); 383 /* Channel is differential, if pins are the same as 'reg' */ 384 if (ret == 0 && (pins[0] != reg || pins[1] != reg)) { 385 dev_err(dev, 386 "Differential pins must be the same as 'reg'"); 387 return -EINVAL; 388 } 389 390 *differential = (ret == 0); 391 392 if (*differential && !*bipolar) { 393 dev_err(dev, 394 "'bipolar' must be added for diff channel %d\n", 395 reg); 396 return -EINVAL; 397 } 398 399 return 0; 400 } 401 402 return 0; 403 } 404 405 static int ad7606c_18bit_chan_scale_setup(struct iio_dev *indio_dev, 406 struct iio_chan_spec *chan, int ch) 407 { 408 struct ad7606_state *st = iio_priv(indio_dev); 409 struct ad7606_chan_scale *cs = &st->chan_scales[ch]; 410 bool bipolar, differential; 411 int ret; 412 413 if (!st->sw_mode_en) { 414 cs->range = 0; 415 cs->scale_avail = ad7606_18bit_hw_scale_avail; 416 cs->num_scales = ARRAY_SIZE(ad7606_18bit_hw_scale_avail); 417 return 0; 418 } 419 420 ret = ad7606_get_chan_config(indio_dev, ch, &bipolar, &differential); 421 if (ret) 422 return ret; 423 424 if (differential) { 425 cs->scale_avail = ad7606c_18bit_differential_bipolar_scale_avail; 426 cs->num_scales = 427 ARRAY_SIZE(ad7606c_18bit_differential_bipolar_scale_avail); 428 /* Bipolar differential ranges start at 8 (b1000) */ 429 cs->reg_offset = 8; 430 cs->range = 1; 431 chan->differential = 1; 432 chan->channel2 = chan->channel; 433 434 return 0; 435 } 436 437 chan->differential = 0; 438 439 if (bipolar) { 440 cs->scale_avail = ad7606c_18bit_single_ended_bipolar_scale_avail; 441 cs->num_scales = 442 ARRAY_SIZE(ad7606c_18bit_single_ended_bipolar_scale_avail); 443 /* Bipolar single-ended ranges start at 0 (b0000) */ 444 cs->reg_offset = 0; 445 cs->range = 3; 446 chan->scan_type.sign = 's'; 447 448 return 0; 449 } 450 451 cs->scale_avail = ad7606c_18bit_single_ended_unipolar_scale_avail; 452 cs->num_scales = 453 ARRAY_SIZE(ad7606c_18bit_single_ended_unipolar_scale_avail); 454 /* Unipolar single-ended ranges start at 5 (b0101) */ 455 cs->reg_offset = 5; 456 cs->range = 1; 457 chan->scan_type.sign = 'u'; 458 459 return 0; 460 } 461 462 static int ad7606c_16bit_chan_scale_setup(struct iio_dev *indio_dev, 463 struct iio_chan_spec *chan, int ch) 464 { 465 struct ad7606_state *st = iio_priv(indio_dev); 466 struct ad7606_chan_scale *cs = &st->chan_scales[ch]; 467 bool bipolar, differential; 468 int ret; 469 470 if (!st->sw_mode_en) { 471 cs->range = 0; 472 cs->scale_avail = ad7606_16bit_hw_scale_avail; 473 cs->num_scales = ARRAY_SIZE(ad7606_16bit_hw_scale_avail); 474 return 0; 475 } 476 477 ret = ad7606_get_chan_config(indio_dev, ch, &bipolar, &differential); 478 if (ret) 479 return ret; 480 481 if (differential) { 482 cs->scale_avail = ad7606c_16bit_differential_bipolar_scale_avail; 483 cs->num_scales = 484 ARRAY_SIZE(ad7606c_16bit_differential_bipolar_scale_avail); 485 /* Bipolar differential ranges start at 8 (b1000) */ 486 cs->reg_offset = 8; 487 cs->range = 1; 488 chan->differential = 1; 489 chan->channel2 = chan->channel; 490 chan->scan_type.sign = 's'; 491 492 return 0; 493 } 494 495 chan->differential = 0; 496 497 if (bipolar) { 498 cs->scale_avail = ad7606c_16bit_single_ended_bipolar_scale_avail; 499 cs->num_scales = 500 ARRAY_SIZE(ad7606c_16bit_single_ended_bipolar_scale_avail); 501 /* Bipolar single-ended ranges start at 0 (b0000) */ 502 cs->reg_offset = 0; 503 cs->range = 3; 504 chan->scan_type.sign = 's'; 505 506 return 0; 507 } 508 509 cs->scale_avail = ad7606c_16bit_single_ended_unipolar_scale_avail; 510 cs->num_scales = 511 ARRAY_SIZE(ad7606c_16bit_single_ended_unipolar_scale_avail); 512 /* Unipolar single-ended ranges start at 5 (b0101) */ 513 cs->reg_offset = 5; 514 cs->range = 1; 515 chan->scan_type.sign = 'u'; 516 517 return 0; 518 } 519 520 static int ad7607_chan_scale_setup(struct iio_dev *indio_dev, 521 struct iio_chan_spec *chan, int ch) 522 { 523 struct ad7606_state *st = iio_priv(indio_dev); 524 struct ad7606_chan_scale *cs = &st->chan_scales[ch]; 525 526 cs->range = 0; 527 cs->scale_avail = ad7607_hw_scale_avail; 528 cs->num_scales = ARRAY_SIZE(ad7607_hw_scale_avail); 529 return 0; 530 } 531 532 static int ad7608_chan_scale_setup(struct iio_dev *indio_dev, 533 struct iio_chan_spec *chan, int ch) 534 { 535 struct ad7606_state *st = iio_priv(indio_dev); 536 struct ad7606_chan_scale *cs = &st->chan_scales[ch]; 537 538 cs->range = 0; 539 cs->scale_avail = ad7606_18bit_hw_scale_avail; 540 cs->num_scales = ARRAY_SIZE(ad7606_18bit_hw_scale_avail); 541 return 0; 542 } 543 544 static int ad7609_chan_scale_setup(struct iio_dev *indio_dev, 545 struct iio_chan_spec *chan, int ch) 546 { 547 struct ad7606_state *st = iio_priv(indio_dev); 548 struct ad7606_chan_scale *cs = &st->chan_scales[ch]; 549 550 cs->range = 0; 551 cs->scale_avail = ad7609_hw_scale_avail; 552 cs->num_scales = ARRAY_SIZE(ad7609_hw_scale_avail); 553 return 0; 554 } 555 556 static int ad7606_reg_access(struct iio_dev *indio_dev, 557 unsigned int reg, 558 unsigned int writeval, 559 unsigned int *readval) 560 { 561 struct ad7606_state *st = iio_priv(indio_dev); 562 int ret; 563 564 guard(mutex)(&st->lock); 565 566 if (readval) { 567 ret = st->bops->reg_read(st, reg); 568 if (ret < 0) 569 return ret; 570 *readval = ret; 571 return 0; 572 } else { 573 return st->bops->reg_write(st, reg, writeval); 574 } 575 } 576 577 static int ad7606_pwm_set_high(struct ad7606_state *st) 578 { 579 struct pwm_state cnvst_pwm_state; 580 int ret; 581 582 pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state); 583 cnvst_pwm_state.enabled = true; 584 cnvst_pwm_state.duty_cycle = cnvst_pwm_state.period; 585 586 ret = pwm_apply_might_sleep(st->cnvst_pwm, &cnvst_pwm_state); 587 588 return ret; 589 } 590 591 static int ad7606_pwm_set_low(struct ad7606_state *st) 592 { 593 struct pwm_state cnvst_pwm_state; 594 int ret; 595 596 pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state); 597 cnvst_pwm_state.enabled = true; 598 cnvst_pwm_state.duty_cycle = 0; 599 600 ret = pwm_apply_might_sleep(st->cnvst_pwm, &cnvst_pwm_state); 601 602 return ret; 603 } 604 605 static int ad7606_pwm_set_swing(struct ad7606_state *st) 606 { 607 struct pwm_state cnvst_pwm_state; 608 609 pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state); 610 cnvst_pwm_state.enabled = true; 611 cnvst_pwm_state.duty_cycle = cnvst_pwm_state.period / 2; 612 613 return pwm_apply_might_sleep(st->cnvst_pwm, &cnvst_pwm_state); 614 } 615 616 static bool ad7606_pwm_is_swinging(struct ad7606_state *st) 617 { 618 struct pwm_state cnvst_pwm_state; 619 620 pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state); 621 622 return cnvst_pwm_state.duty_cycle != cnvst_pwm_state.period && 623 cnvst_pwm_state.duty_cycle != 0; 624 } 625 626 static int ad7606_set_sampling_freq(struct ad7606_state *st, unsigned long freq) 627 { 628 struct pwm_state cnvst_pwm_state; 629 bool is_swinging = ad7606_pwm_is_swinging(st); 630 bool is_high; 631 632 if (freq == 0) 633 return -EINVAL; 634 635 /* Retrieve the previous state. */ 636 pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state); 637 is_high = cnvst_pwm_state.duty_cycle == cnvst_pwm_state.period; 638 639 cnvst_pwm_state.period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, freq); 640 cnvst_pwm_state.polarity = PWM_POLARITY_NORMAL; 641 if (is_high) 642 cnvst_pwm_state.duty_cycle = cnvst_pwm_state.period; 643 else if (is_swinging) 644 cnvst_pwm_state.duty_cycle = cnvst_pwm_state.period / 2; 645 else 646 cnvst_pwm_state.duty_cycle = 0; 647 648 return pwm_apply_might_sleep(st->cnvst_pwm, &cnvst_pwm_state); 649 } 650 651 static int ad7606_read_samples(struct ad7606_state *st) 652 { 653 unsigned int num = st->chip_info->num_adc_channels; 654 655 return st->bops->read_block(st->dev, num, &st->data); 656 } 657 658 static irqreturn_t ad7606_trigger_handler(int irq, void *p) 659 { 660 struct iio_poll_func *pf = p; 661 struct iio_dev *indio_dev = pf->indio_dev; 662 struct ad7606_state *st = iio_priv(indio_dev); 663 int ret; 664 665 guard(mutex)(&st->lock); 666 667 ret = ad7606_read_samples(st); 668 if (ret) 669 goto error_ret; 670 671 iio_push_to_buffers_with_timestamp(indio_dev, &st->data, 672 iio_get_time_ns(indio_dev)); 673 error_ret: 674 iio_trigger_notify_done(indio_dev->trig); 675 /* The rising edge of the CONVST signal starts a new conversion. */ 676 gpiod_set_value(st->gpio_convst, 1); 677 678 return IRQ_HANDLED; 679 } 680 681 static int ad7606_scan_direct(struct iio_dev *indio_dev, unsigned int ch, 682 int *val) 683 { 684 struct ad7606_state *st = iio_priv(indio_dev); 685 unsigned int realbits = st->chip_info->channels[1].scan_type.realbits; 686 const struct iio_chan_spec *chan; 687 int ret; 688 689 if (st->gpio_convst) { 690 gpiod_set_value(st->gpio_convst, 1); 691 } else { 692 ret = ad7606_pwm_set_high(st); 693 if (ret < 0) 694 return ret; 695 } 696 697 /* 698 * If no backend, wait for the interruption on busy pin, otherwise just add 699 * a delay to leave time for the data to be available. For now, the latter 700 * will not happen because IIO_CHAN_INFO_RAW is not supported for the backend. 701 * TODO: Add support for reading a single value when the backend is used. 702 */ 703 if (!st->back) { 704 ret = wait_for_completion_timeout(&st->completion, 705 msecs_to_jiffies(1000)); 706 if (!ret) { 707 ret = -ETIMEDOUT; 708 goto error_ret; 709 } 710 } else { 711 fsleep(1); 712 } 713 714 ret = ad7606_read_samples(st); 715 if (ret) 716 goto error_ret; 717 718 chan = &indio_dev->channels[ch + 1]; 719 if (chan->scan_type.sign == 'u') { 720 if (realbits > 16) 721 *val = st->data.buf32[ch]; 722 else 723 *val = st->data.buf16[ch]; 724 } else { 725 if (realbits > 16) 726 *val = sign_extend32(st->data.buf32[ch], realbits - 1); 727 else 728 *val = sign_extend32(st->data.buf16[ch], realbits - 1); 729 } 730 731 error_ret: 732 if (!st->gpio_convst) { 733 ret = ad7606_pwm_set_low(st); 734 if (ret < 0) 735 return ret; 736 } 737 gpiod_set_value(st->gpio_convst, 0); 738 739 return ret; 740 } 741 742 static int ad7606_read_raw(struct iio_dev *indio_dev, 743 struct iio_chan_spec const *chan, 744 int *val, 745 int *val2, 746 long m) 747 { 748 int ret, ch = 0; 749 struct ad7606_state *st = iio_priv(indio_dev); 750 struct ad7606_chan_scale *cs; 751 struct pwm_state cnvst_pwm_state; 752 753 switch (m) { 754 case IIO_CHAN_INFO_RAW: 755 iio_device_claim_direct_scoped(return -EBUSY, indio_dev) { 756 ret = ad7606_scan_direct(indio_dev, chan->address, val); 757 if (ret < 0) 758 return ret; 759 return IIO_VAL_INT; 760 } 761 unreachable(); 762 case IIO_CHAN_INFO_SCALE: 763 if (st->sw_mode_en) 764 ch = chan->address; 765 cs = &st->chan_scales[ch]; 766 *val = cs->scale_avail[cs->range][0]; 767 *val2 = cs->scale_avail[cs->range][1]; 768 return IIO_VAL_INT_PLUS_MICRO; 769 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 770 *val = st->oversampling; 771 return IIO_VAL_INT; 772 case IIO_CHAN_INFO_SAMP_FREQ: 773 /* 774 * TODO: return the real frequency intead of the requested one once 775 * pwm_get_state_hw comes upstream. 776 */ 777 pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state); 778 *val = DIV_ROUND_CLOSEST_ULL(NSEC_PER_SEC, cnvst_pwm_state.period); 779 return IIO_VAL_INT; 780 } 781 return -EINVAL; 782 } 783 784 static ssize_t in_voltage_scale_available_show(struct device *dev, 785 struct device_attribute *attr, 786 char *buf) 787 { 788 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 789 struct ad7606_state *st = iio_priv(indio_dev); 790 struct ad7606_chan_scale *cs = &st->chan_scales[0]; 791 const unsigned int (*vals)[2] = cs->scale_avail; 792 unsigned int i; 793 size_t len = 0; 794 795 for (i = 0; i < cs->num_scales; i++) 796 len += scnprintf(buf + len, PAGE_SIZE - len, "%u.%06u ", 797 vals[i][0], vals[i][1]); 798 buf[len - 1] = '\n'; 799 800 return len; 801 } 802 803 static IIO_DEVICE_ATTR_RO(in_voltage_scale_available, 0); 804 805 static int ad7606_write_scale_hw(struct iio_dev *indio_dev, int ch, int val) 806 { 807 struct ad7606_state *st = iio_priv(indio_dev); 808 809 gpiod_set_value(st->gpio_range, val); 810 811 return 0; 812 } 813 814 static int ad7606_write_os_hw(struct iio_dev *indio_dev, int val) 815 { 816 struct ad7606_state *st = iio_priv(indio_dev); 817 DECLARE_BITMAP(values, 3); 818 819 values[0] = val & GENMASK(2, 0); 820 821 gpiod_set_array_value(st->gpio_os->ndescs, st->gpio_os->desc, 822 st->gpio_os->info, values); 823 824 /* AD7616 requires a reset to update value */ 825 if (st->chip_info->os_req_reset) 826 ad7606_reset(st); 827 828 return 0; 829 } 830 831 static int ad7606_write_raw(struct iio_dev *indio_dev, 832 struct iio_chan_spec const *chan, 833 int val, 834 int val2, 835 long mask) 836 { 837 struct ad7606_state *st = iio_priv(indio_dev); 838 unsigned int scale_avail_uv[AD760X_MAX_SCALES]; 839 struct ad7606_chan_scale *cs; 840 int i, ret, ch = 0; 841 842 guard(mutex)(&st->lock); 843 844 switch (mask) { 845 case IIO_CHAN_INFO_SCALE: 846 if (st->sw_mode_en) 847 ch = chan->address; 848 cs = &st->chan_scales[ch]; 849 for (i = 0; i < cs->num_scales; i++) { 850 scale_avail_uv[i] = cs->scale_avail[i][0] * MICRO + 851 cs->scale_avail[i][1]; 852 } 853 val = (val * MICRO) + val2; 854 i = find_closest(val, scale_avail_uv, cs->num_scales); 855 ret = st->write_scale(indio_dev, ch, i + cs->reg_offset); 856 if (ret < 0) 857 return ret; 858 cs->range = i; 859 860 return 0; 861 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 862 if (val2) 863 return -EINVAL; 864 i = find_closest(val, st->oversampling_avail, 865 st->num_os_ratios); 866 ret = st->write_os(indio_dev, i); 867 if (ret < 0) 868 return ret; 869 st->oversampling = st->oversampling_avail[i]; 870 871 return 0; 872 case IIO_CHAN_INFO_SAMP_FREQ: 873 if (val < 0 && val2 != 0) 874 return -EINVAL; 875 return ad7606_set_sampling_freq(st, val); 876 default: 877 return -EINVAL; 878 } 879 } 880 881 static ssize_t ad7606_oversampling_ratio_avail(struct device *dev, 882 struct device_attribute *attr, 883 char *buf) 884 { 885 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 886 struct ad7606_state *st = iio_priv(indio_dev); 887 const unsigned int *vals = st->oversampling_avail; 888 unsigned int i; 889 size_t len = 0; 890 891 for (i = 0; i < st->num_os_ratios; i++) 892 len += scnprintf(buf + len, PAGE_SIZE - len, "%u ", vals[i]); 893 buf[len - 1] = '\n'; 894 895 return len; 896 } 897 898 static IIO_DEVICE_ATTR(oversampling_ratio_available, 0444, 899 ad7606_oversampling_ratio_avail, NULL, 0); 900 901 static struct attribute *ad7606_attributes_os_and_range[] = { 902 &iio_dev_attr_in_voltage_scale_available.dev_attr.attr, 903 &iio_dev_attr_oversampling_ratio_available.dev_attr.attr, 904 NULL, 905 }; 906 907 static const struct attribute_group ad7606_attribute_group_os_and_range = { 908 .attrs = ad7606_attributes_os_and_range, 909 }; 910 911 static struct attribute *ad7606_attributes_os[] = { 912 &iio_dev_attr_oversampling_ratio_available.dev_attr.attr, 913 NULL, 914 }; 915 916 static const struct attribute_group ad7606_attribute_group_os = { 917 .attrs = ad7606_attributes_os, 918 }; 919 920 static struct attribute *ad7606_attributes_range[] = { 921 &iio_dev_attr_in_voltage_scale_available.dev_attr.attr, 922 NULL, 923 }; 924 925 static const struct attribute_group ad7606_attribute_group_range = { 926 .attrs = ad7606_attributes_range, 927 }; 928 929 static int ad7606_request_gpios(struct ad7606_state *st) 930 { 931 struct device *dev = st->dev; 932 933 st->gpio_convst = devm_gpiod_get_optional(dev, "adi,conversion-start", 934 GPIOD_OUT_LOW); 935 936 if (IS_ERR(st->gpio_convst)) 937 return PTR_ERR(st->gpio_convst); 938 939 st->gpio_reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 940 if (IS_ERR(st->gpio_reset)) 941 return PTR_ERR(st->gpio_reset); 942 943 st->gpio_range = devm_gpiod_get_optional(dev, "adi,range", 944 GPIOD_OUT_LOW); 945 if (IS_ERR(st->gpio_range)) 946 return PTR_ERR(st->gpio_range); 947 948 st->gpio_standby = devm_gpiod_get_optional(dev, "standby", 949 GPIOD_OUT_LOW); 950 if (IS_ERR(st->gpio_standby)) 951 return PTR_ERR(st->gpio_standby); 952 953 st->gpio_frstdata = devm_gpiod_get_optional(dev, "adi,first-data", 954 GPIOD_IN); 955 if (IS_ERR(st->gpio_frstdata)) 956 return PTR_ERR(st->gpio_frstdata); 957 958 if (!st->chip_info->oversampling_num) 959 return 0; 960 961 st->gpio_os = devm_gpiod_get_array_optional(dev, 962 "adi,oversampling-ratio", 963 GPIOD_OUT_LOW); 964 return PTR_ERR_OR_ZERO(st->gpio_os); 965 } 966 967 /* 968 * The BUSY signal indicates when conversions are in progress, so when a rising 969 * edge of CONVST is applied, BUSY goes logic high and transitions low at the 970 * end of the entire conversion process. The falling edge of the BUSY signal 971 * triggers this interrupt. 972 */ 973 static irqreturn_t ad7606_interrupt(int irq, void *dev_id) 974 { 975 struct iio_dev *indio_dev = dev_id; 976 struct ad7606_state *st = iio_priv(indio_dev); 977 int ret; 978 979 if (iio_buffer_enabled(indio_dev)) { 980 if (st->gpio_convst) { 981 gpiod_set_value(st->gpio_convst, 0); 982 } else { 983 ret = ad7606_pwm_set_low(st); 984 if (ret < 0) { 985 dev_err(st->dev, "PWM set low failed"); 986 goto done; 987 } 988 } 989 iio_trigger_poll_nested(st->trig); 990 } else { 991 complete(&st->completion); 992 } 993 994 done: 995 return IRQ_HANDLED; 996 }; 997 998 static int ad7606_validate_trigger(struct iio_dev *indio_dev, 999 struct iio_trigger *trig) 1000 { 1001 struct ad7606_state *st = iio_priv(indio_dev); 1002 1003 if (st->trig != trig) 1004 return -EINVAL; 1005 1006 return 0; 1007 } 1008 1009 static int ad7606_buffer_postenable(struct iio_dev *indio_dev) 1010 { 1011 struct ad7606_state *st = iio_priv(indio_dev); 1012 1013 gpiod_set_value(st->gpio_convst, 1); 1014 1015 return 0; 1016 } 1017 1018 static int ad7606_buffer_predisable(struct iio_dev *indio_dev) 1019 { 1020 struct ad7606_state *st = iio_priv(indio_dev); 1021 1022 gpiod_set_value(st->gpio_convst, 0); 1023 1024 return 0; 1025 } 1026 1027 static int ad7606_read_avail(struct iio_dev *indio_dev, 1028 struct iio_chan_spec const *chan, 1029 const int **vals, int *type, int *length, 1030 long info) 1031 { 1032 struct ad7606_state *st = iio_priv(indio_dev); 1033 struct ad7606_chan_scale *cs; 1034 unsigned int ch = 0; 1035 1036 switch (info) { 1037 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1038 *vals = st->oversampling_avail; 1039 *length = st->num_os_ratios; 1040 *type = IIO_VAL_INT; 1041 1042 return IIO_AVAIL_LIST; 1043 1044 case IIO_CHAN_INFO_SCALE: 1045 if (st->sw_mode_en) 1046 ch = chan->address; 1047 1048 cs = &st->chan_scales[ch]; 1049 *vals = (int *)cs->scale_avail; 1050 *length = cs->num_scales; 1051 *type = IIO_VAL_INT_PLUS_MICRO; 1052 1053 return IIO_AVAIL_LIST; 1054 } 1055 return -EINVAL; 1056 } 1057 1058 static int ad7606_backend_buffer_postenable(struct iio_dev *indio_dev) 1059 { 1060 struct ad7606_state *st = iio_priv(indio_dev); 1061 1062 return ad7606_pwm_set_swing(st); 1063 } 1064 1065 static int ad7606_backend_buffer_predisable(struct iio_dev *indio_dev) 1066 { 1067 struct ad7606_state *st = iio_priv(indio_dev); 1068 1069 return ad7606_pwm_set_low(st); 1070 } 1071 1072 static int ad7606_update_scan_mode(struct iio_dev *indio_dev, 1073 const unsigned long *scan_mask) 1074 { 1075 struct ad7606_state *st = iio_priv(indio_dev); 1076 1077 /* 1078 * The update scan mode is only for iio backend compatible drivers. 1079 * If the specific update_scan_mode is not defined in the bus ops, 1080 * just do nothing and return 0. 1081 */ 1082 if (!st->bops->update_scan_mode) 1083 return 0; 1084 1085 return st->bops->update_scan_mode(indio_dev, scan_mask); 1086 } 1087 1088 static const struct iio_buffer_setup_ops ad7606_buffer_ops = { 1089 .postenable = &ad7606_buffer_postenable, 1090 .predisable = &ad7606_buffer_predisable, 1091 }; 1092 1093 static const struct iio_buffer_setup_ops ad7606_backend_buffer_ops = { 1094 .postenable = &ad7606_backend_buffer_postenable, 1095 .predisable = &ad7606_backend_buffer_predisable, 1096 }; 1097 1098 static const struct iio_info ad7606_info_no_os_or_range = { 1099 .read_raw = &ad7606_read_raw, 1100 .validate_trigger = &ad7606_validate_trigger, 1101 .update_scan_mode = &ad7606_update_scan_mode, 1102 }; 1103 1104 static const struct iio_info ad7606_info_os_and_range = { 1105 .read_raw = &ad7606_read_raw, 1106 .write_raw = &ad7606_write_raw, 1107 .attrs = &ad7606_attribute_group_os_and_range, 1108 .validate_trigger = &ad7606_validate_trigger, 1109 .update_scan_mode = &ad7606_update_scan_mode, 1110 }; 1111 1112 static const struct iio_info ad7606_info_sw_mode = { 1113 .read_raw = &ad7606_read_raw, 1114 .write_raw = &ad7606_write_raw, 1115 .read_avail = &ad7606_read_avail, 1116 .debugfs_reg_access = &ad7606_reg_access, 1117 .validate_trigger = &ad7606_validate_trigger, 1118 .update_scan_mode = &ad7606_update_scan_mode, 1119 }; 1120 1121 static const struct iio_info ad7606_info_os = { 1122 .read_raw = &ad7606_read_raw, 1123 .write_raw = &ad7606_write_raw, 1124 .attrs = &ad7606_attribute_group_os, 1125 .validate_trigger = &ad7606_validate_trigger, 1126 .update_scan_mode = &ad7606_update_scan_mode, 1127 }; 1128 1129 static const struct iio_info ad7606_info_range = { 1130 .read_raw = &ad7606_read_raw, 1131 .write_raw = &ad7606_write_raw, 1132 .attrs = &ad7606_attribute_group_range, 1133 .validate_trigger = &ad7606_validate_trigger, 1134 .update_scan_mode = &ad7606_update_scan_mode, 1135 }; 1136 1137 static const struct iio_trigger_ops ad7606_trigger_ops = { 1138 .validate_device = iio_trigger_validate_own_device, 1139 }; 1140 1141 static int ad7606_sw_mode_setup(struct iio_dev *indio_dev) 1142 { 1143 struct ad7606_state *st = iio_priv(indio_dev); 1144 1145 st->sw_mode_en = st->bops->sw_mode_config && 1146 device_property_present(st->dev, "adi,sw-mode"); 1147 if (!st->sw_mode_en) 1148 return 0; 1149 1150 indio_dev->info = &ad7606_info_sw_mode; 1151 1152 return st->bops->sw_mode_config(indio_dev); 1153 } 1154 1155 static int ad7606_chan_scales_setup(struct iio_dev *indio_dev) 1156 { 1157 struct ad7606_state *st = iio_priv(indio_dev); 1158 unsigned int offset = indio_dev->num_channels - st->chip_info->num_adc_channels; 1159 struct iio_chan_spec *chans; 1160 size_t size; 1161 int ch, ret; 1162 1163 /* Clone IIO channels, since some may be differential */ 1164 size = indio_dev->num_channels * sizeof(*indio_dev->channels); 1165 chans = devm_kzalloc(st->dev, size, GFP_KERNEL); 1166 if (!chans) 1167 return -ENOMEM; 1168 1169 memcpy(chans, indio_dev->channels, size); 1170 indio_dev->channels = chans; 1171 1172 for (ch = 0; ch < st->chip_info->num_adc_channels; ch++) { 1173 ret = st->chip_info->scale_setup_cb(indio_dev, &chans[ch + offset], ch); 1174 if (ret) 1175 return ret; 1176 } 1177 1178 return 0; 1179 } 1180 1181 static void ad7606_pwm_disable(void *data) 1182 { 1183 pwm_disable(data); 1184 } 1185 1186 int ad7606_probe(struct device *dev, int irq, void __iomem *base_address, 1187 const struct ad7606_chip_info *chip_info, 1188 const struct ad7606_bus_ops *bops) 1189 { 1190 struct ad7606_state *st; 1191 int ret; 1192 struct iio_dev *indio_dev; 1193 1194 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 1195 if (!indio_dev) 1196 return -ENOMEM; 1197 1198 st = iio_priv(indio_dev); 1199 dev_set_drvdata(dev, indio_dev); 1200 1201 st->dev = dev; 1202 mutex_init(&st->lock); 1203 st->bops = bops; 1204 st->base_address = base_address; 1205 st->oversampling = 1; 1206 1207 ret = devm_regulator_get_enable(dev, "avcc"); 1208 if (ret) 1209 return dev_err_probe(dev, ret, 1210 "Failed to enable specified AVcc supply\n"); 1211 1212 st->chip_info = chip_info; 1213 1214 if (st->chip_info->oversampling_num) { 1215 st->oversampling_avail = st->chip_info->oversampling_avail; 1216 st->num_os_ratios = st->chip_info->oversampling_num; 1217 } 1218 1219 ret = ad7606_request_gpios(st); 1220 if (ret) 1221 return ret; 1222 1223 if (st->gpio_os) { 1224 if (st->gpio_range) 1225 indio_dev->info = &ad7606_info_os_and_range; 1226 else 1227 indio_dev->info = &ad7606_info_os; 1228 } else { 1229 if (st->gpio_range) 1230 indio_dev->info = &ad7606_info_range; 1231 else 1232 indio_dev->info = &ad7606_info_no_os_or_range; 1233 } 1234 indio_dev->modes = INDIO_DIRECT_MODE; 1235 indio_dev->name = chip_info->name; 1236 indio_dev->channels = st->chip_info->channels; 1237 indio_dev->num_channels = st->chip_info->num_channels; 1238 1239 ret = ad7606_reset(st); 1240 if (ret) 1241 dev_warn(st->dev, "failed to RESET: no RESET GPIO specified\n"); 1242 1243 /* AD7616 requires al least 15ms to reconfigure after a reset */ 1244 if (st->chip_info->init_delay_ms) { 1245 if (msleep_interruptible(st->chip_info->init_delay_ms)) 1246 return -ERESTARTSYS; 1247 } 1248 1249 st->write_scale = ad7606_write_scale_hw; 1250 st->write_os = ad7606_write_os_hw; 1251 1252 ret = ad7606_sw_mode_setup(indio_dev); 1253 if (ret) 1254 return ret; 1255 1256 ret = ad7606_chan_scales_setup(indio_dev); 1257 if (ret) 1258 return ret; 1259 1260 /* If convst pin is not defined, setup PWM. */ 1261 if (!st->gpio_convst) { 1262 st->cnvst_pwm = devm_pwm_get(dev, NULL); 1263 if (IS_ERR(st->cnvst_pwm)) 1264 return PTR_ERR(st->cnvst_pwm); 1265 1266 /* The PWM is initialized at 1MHz to have a fast enough GPIO emulation. */ 1267 ret = ad7606_set_sampling_freq(st, 1 * MEGA); 1268 if (ret) 1269 return ret; 1270 1271 ret = ad7606_pwm_set_low(st); 1272 if (ret) 1273 return ret; 1274 1275 /* 1276 * PWM is not disabled when sampling stops, but instead its duty cycle is set 1277 * to 0% to be sure we have a "low" state. After we unload the driver, let's 1278 * disable the PWM. 1279 */ 1280 ret = devm_add_action_or_reset(dev, ad7606_pwm_disable, 1281 st->cnvst_pwm); 1282 if (ret) 1283 return ret; 1284 } 1285 1286 if (st->bops->iio_backend_config) { 1287 /* 1288 * If there is a backend, the PWM should not overpass the maximum sampling 1289 * frequency the chip supports. 1290 */ 1291 ret = ad7606_set_sampling_freq(st, 1292 chip_info->max_samplerate ? : 2 * KILO); 1293 if (ret) 1294 return ret; 1295 1296 ret = st->bops->iio_backend_config(dev, indio_dev); 1297 if (ret) 1298 return ret; 1299 1300 indio_dev->setup_ops = &ad7606_backend_buffer_ops; 1301 } else { 1302 1303 /* Reserve the PWM use only for backend (force gpio_convst definition) */ 1304 if (!st->gpio_convst) 1305 return dev_err_probe(dev, -EINVAL, 1306 "No backend, connect convst to a GPIO"); 1307 1308 init_completion(&st->completion); 1309 st->trig = devm_iio_trigger_alloc(dev, "%s-dev%d", 1310 indio_dev->name, 1311 iio_device_id(indio_dev)); 1312 if (!st->trig) 1313 return -ENOMEM; 1314 1315 st->trig->ops = &ad7606_trigger_ops; 1316 iio_trigger_set_drvdata(st->trig, indio_dev); 1317 ret = devm_iio_trigger_register(dev, st->trig); 1318 if (ret) 1319 return ret; 1320 1321 indio_dev->trig = iio_trigger_get(st->trig); 1322 1323 ret = devm_request_threaded_irq(dev, irq, NULL, &ad7606_interrupt, 1324 IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 1325 chip_info->name, indio_dev); 1326 if (ret) 1327 return ret; 1328 1329 ret = devm_iio_triggered_buffer_setup(dev, indio_dev, 1330 &iio_pollfunc_store_time, 1331 &ad7606_trigger_handler, 1332 &ad7606_buffer_ops); 1333 if (ret) 1334 return ret; 1335 } 1336 1337 return devm_iio_device_register(dev, indio_dev); 1338 } 1339 EXPORT_SYMBOL_NS_GPL(ad7606_probe, "IIO_AD7606"); 1340 1341 #ifdef CONFIG_PM_SLEEP 1342 1343 static int ad7606_suspend(struct device *dev) 1344 { 1345 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1346 struct ad7606_state *st = iio_priv(indio_dev); 1347 1348 if (st->gpio_standby) { 1349 gpiod_set_value(st->gpio_range, 1); 1350 gpiod_set_value(st->gpio_standby, 1); 1351 } 1352 1353 return 0; 1354 } 1355 1356 static int ad7606_resume(struct device *dev) 1357 { 1358 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1359 struct ad7606_state *st = iio_priv(indio_dev); 1360 1361 if (st->gpio_standby) { 1362 gpiod_set_value(st->gpio_range, st->chan_scales[0].range); 1363 gpiod_set_value(st->gpio_standby, 1); 1364 ad7606_reset(st); 1365 } 1366 1367 return 0; 1368 } 1369 1370 SIMPLE_DEV_PM_OPS(ad7606_pm_ops, ad7606_suspend, ad7606_resume); 1371 EXPORT_SYMBOL_NS_GPL(ad7606_pm_ops, "IIO_AD7606"); 1372 1373 #endif 1374 1375 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>"); 1376 MODULE_DESCRIPTION("Analog Devices AD7606 ADC"); 1377 MODULE_LICENSE("GPL v2"); 1378