xref: /linux/drivers/interconnect/qcom/sc7280.c (revision 83bd89291f5cc866f60d32c34e268896c7ba8a3d) 
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2021, The Linux Foundation. All rights reserved.
4  * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
5  *
6  */
7 
8 #include <linux/device.h>
9 #include <linux/interconnect.h>
10 #include <linux/interconnect-provider.h>
11 #include <linux/mod_devicetable.h>
12 #include <linux/module.h>
13 #include <linux/platform_device.h>
14 #include <dt-bindings/interconnect/qcom,sc7280.h>
15 
16 #include "bcm-voter.h"
17 #include "icc-rpmh.h"
18 
19 static struct qcom_icc_node qhm_qspi;
20 static struct qcom_icc_node qhm_qup0;
21 static struct qcom_icc_node qhm_qup1;
22 static struct qcom_icc_node qnm_a1noc_cfg;
23 static struct qcom_icc_node xm_sdc1;
24 static struct qcom_icc_node xm_sdc2;
25 static struct qcom_icc_node xm_sdc4;
26 static struct qcom_icc_node xm_ufs_mem;
27 static struct qcom_icc_node xm_usb2;
28 static struct qcom_icc_node xm_usb3_0;
29 static struct qcom_icc_node qhm_qdss_bam;
30 static struct qcom_icc_node qnm_a2noc_cfg;
31 static struct qcom_icc_node qnm_cnoc_datapath;
32 static struct qcom_icc_node qxm_crypto;
33 static struct qcom_icc_node qxm_ipa;
34 static struct qcom_icc_node xm_pcie3_0;
35 static struct qcom_icc_node xm_pcie3_1;
36 static struct qcom_icc_node xm_qdss_etr;
37 static struct qcom_icc_node qup0_core_master;
38 static struct qcom_icc_node qup1_core_master;
39 static struct qcom_icc_node qnm_cnoc3_cnoc2;
40 static struct qcom_icc_node xm_qdss_dap;
41 static struct qcom_icc_node qnm_cnoc2_cnoc3;
42 static struct qcom_icc_node qnm_gemnoc_cnoc;
43 static struct qcom_icc_node qnm_gemnoc_pcie;
44 static struct qcom_icc_node qnm_cnoc_dc_noc;
45 static struct qcom_icc_node alm_gpu_tcu;
46 static struct qcom_icc_node alm_sys_tcu;
47 static struct qcom_icc_node chm_apps;
48 static struct qcom_icc_node qnm_cmpnoc;
49 static struct qcom_icc_node qnm_gemnoc_cfg;
50 static struct qcom_icc_node qnm_gpu;
51 static struct qcom_icc_node qnm_mnoc_hf;
52 static struct qcom_icc_node qnm_mnoc_sf;
53 static struct qcom_icc_node qnm_pcie;
54 static struct qcom_icc_node qnm_snoc_gc;
55 static struct qcom_icc_node qnm_snoc_sf;
56 static struct qcom_icc_node qhm_config_noc;
57 static struct qcom_icc_node llcc_mc;
58 static struct qcom_icc_node qnm_mnoc_cfg;
59 static struct qcom_icc_node qnm_video0;
60 static struct qcom_icc_node qnm_video_cpu;
61 static struct qcom_icc_node qxm_camnoc_hf;
62 static struct qcom_icc_node qxm_camnoc_icp;
63 static struct qcom_icc_node qxm_camnoc_sf;
64 static struct qcom_icc_node qxm_mdp0;
65 static struct qcom_icc_node qhm_nsp_noc_config;
66 static struct qcom_icc_node qxm_nsp;
67 static struct qcom_icc_node qnm_aggre1_noc;
68 static struct qcom_icc_node qnm_aggre2_noc;
69 static struct qcom_icc_node qnm_snoc_cfg;
70 static struct qcom_icc_node qxm_pimem;
71 static struct qcom_icc_node xm_gic;
72 static struct qcom_icc_node qns_a1noc_snoc;
73 static struct qcom_icc_node srvc_aggre1_noc;
74 static struct qcom_icc_node qns_a2noc_snoc;
75 static struct qcom_icc_node qns_pcie_mem_noc;
76 static struct qcom_icc_node srvc_aggre2_noc;
77 static struct qcom_icc_node qup0_core_slave;
78 static struct qcom_icc_node qup1_core_slave;
79 static struct qcom_icc_node qhs_ahb2phy0;
80 static struct qcom_icc_node qhs_ahb2phy1;
81 static struct qcom_icc_node qhs_camera_cfg;
82 static struct qcom_icc_node qhs_clk_ctl;
83 static struct qcom_icc_node qhs_compute_cfg;
84 static struct qcom_icc_node qhs_cpr_cx;
85 static struct qcom_icc_node qhs_cpr_mx;
86 static struct qcom_icc_node qhs_crypto0_cfg;
87 static struct qcom_icc_node qhs_cx_rdpm;
88 static struct qcom_icc_node qhs_dcc_cfg;
89 static struct qcom_icc_node qhs_display_cfg;
90 static struct qcom_icc_node qhs_gpuss_cfg;
91 static struct qcom_icc_node qhs_hwkm;
92 static struct qcom_icc_node qhs_imem_cfg;
93 static struct qcom_icc_node qhs_ipa;
94 static struct qcom_icc_node qhs_ipc_router;
95 static struct qcom_icc_node qhs_lpass_cfg;
96 static struct qcom_icc_node qhs_mss_cfg;
97 static struct qcom_icc_node qhs_mx_rdpm;
98 static struct qcom_icc_node qhs_pcie0_cfg;
99 static struct qcom_icc_node qhs_pcie1_cfg;
100 static struct qcom_icc_node qhs_pdm;
101 static struct qcom_icc_node qhs_pimem_cfg;
102 static struct qcom_icc_node qhs_pka_wrapper_cfg;
103 static struct qcom_icc_node qhs_pmu_wrapper_cfg;
104 static struct qcom_icc_node qhs_qdss_cfg;
105 static struct qcom_icc_node qhs_qspi;
106 static struct qcom_icc_node qhs_qup0;
107 static struct qcom_icc_node qhs_qup1;
108 static struct qcom_icc_node qhs_sdc1;
109 static struct qcom_icc_node qhs_sdc2;
110 static struct qcom_icc_node qhs_sdc4;
111 static struct qcom_icc_node qhs_security;
112 static struct qcom_icc_node qhs_tcsr;
113 static struct qcom_icc_node qhs_tlmm;
114 static struct qcom_icc_node qhs_ufs_mem_cfg;
115 static struct qcom_icc_node qhs_usb2;
116 static struct qcom_icc_node qhs_usb3_0;
117 static struct qcom_icc_node qhs_venus_cfg;
118 static struct qcom_icc_node qhs_vsense_ctrl_cfg;
119 static struct qcom_icc_node qns_a1_noc_cfg;
120 static struct qcom_icc_node qns_a2_noc_cfg;
121 static struct qcom_icc_node qns_cnoc2_cnoc3;
122 static struct qcom_icc_node qns_mnoc_cfg;
123 static struct qcom_icc_node qns_snoc_cfg;
124 static struct qcom_icc_node qhs_aoss;
125 static struct qcom_icc_node qhs_apss;
126 static struct qcom_icc_node qns_cnoc3_cnoc2;
127 static struct qcom_icc_node qns_cnoc_a2noc;
128 static struct qcom_icc_node qns_ddrss_cfg;
129 static struct qcom_icc_node qxs_boot_imem;
130 static struct qcom_icc_node qxs_imem;
131 static struct qcom_icc_node qxs_pimem;
132 static struct qcom_icc_node xs_pcie_0;
133 static struct qcom_icc_node xs_pcie_1;
134 static struct qcom_icc_node xs_qdss_stm;
135 static struct qcom_icc_node xs_sys_tcu_cfg;
136 static struct qcom_icc_node qhs_llcc;
137 static struct qcom_icc_node qns_gemnoc;
138 static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg;
139 static struct qcom_icc_node qhs_modem_ms_mpu_cfg;
140 static struct qcom_icc_node qns_gem_noc_cnoc;
141 static struct qcom_icc_node qns_llcc;
142 static struct qcom_icc_node qns_pcie;
143 static struct qcom_icc_node srvc_even_gemnoc;
144 static struct qcom_icc_node srvc_odd_gemnoc;
145 static struct qcom_icc_node srvc_sys_gemnoc;
146 static struct qcom_icc_node qhs_lpass_core;
147 static struct qcom_icc_node qhs_lpass_lpi;
148 static struct qcom_icc_node qhs_lpass_mpu;
149 static struct qcom_icc_node qhs_lpass_top;
150 static struct qcom_icc_node srvc_niu_aml_noc;
151 static struct qcom_icc_node srvc_niu_lpass_agnoc;
152 static struct qcom_icc_node ebi;
153 static struct qcom_icc_node qns_mem_noc_hf;
154 static struct qcom_icc_node qns_mem_noc_sf;
155 static struct qcom_icc_node srvc_mnoc;
156 static struct qcom_icc_node qns_nsp_gemnoc;
157 static struct qcom_icc_node service_nsp_noc;
158 static struct qcom_icc_node qns_gemnoc_gc;
159 static struct qcom_icc_node qns_gemnoc_sf;
160 static struct qcom_icc_node srvc_snoc;
161 
162 static struct qcom_icc_node qhm_qspi = {
163 	.name = "qhm_qspi",
164 	.channels = 1,
165 	.buswidth = 4,
166 	.qosbox = &(const struct qcom_icc_qosbox) {
167 		.num_ports = 1,
168 		.port_offsets = { 0x7000 },
169 		.prio = 2,
170 		.urg_fwd = 0,
171 	},
172 	.num_links = 1,
173 	.link_nodes = { &qns_a1noc_snoc },
174 };
175 
176 static struct qcom_icc_node qhm_qup0 = {
177 	.name = "qhm_qup0",
178 	.channels = 1,
179 	.buswidth = 4,
180 	.qosbox = &(const struct qcom_icc_qosbox) {
181 		.num_ports = 1,
182 		.port_offsets = { 0x11000 },
183 		.prio = 2,
184 		.urg_fwd = 0,
185 	},
186 	.num_links = 1,
187 	.link_nodes = { &qns_a1noc_snoc },
188 };
189 
190 static struct qcom_icc_node qhm_qup1 = {
191 	.name = "qhm_qup1",
192 	.channels = 1,
193 	.buswidth = 4,
194 	.qosbox = &(const struct qcom_icc_qosbox) {
195 		.num_ports = 1,
196 		.port_offsets = { 0x8000 },
197 		.prio = 2,
198 		.urg_fwd = 0,
199 	},
200 	.num_links = 1,
201 	.link_nodes = { &qns_a1noc_snoc },
202 };
203 
204 static struct qcom_icc_node qnm_a1noc_cfg = {
205 	.name = "qnm_a1noc_cfg",
206 	.channels = 1,
207 	.buswidth = 4,
208 	.num_links = 1,
209 	.link_nodes = { &srvc_aggre1_noc },
210 };
211 
212 static struct qcom_icc_node xm_sdc1 = {
213 	.name = "xm_sdc1",
214 	.channels = 1,
215 	.buswidth = 8,
216 	.qosbox = &(const struct qcom_icc_qosbox) {
217 		.num_ports = 1,
218 		.port_offsets = { 0xc000 },
219 		.prio = 2,
220 		.urg_fwd = 0,
221 	},
222 	.num_links = 1,
223 	.link_nodes = { &qns_a1noc_snoc },
224 };
225 
226 static struct qcom_icc_node xm_sdc2 = {
227 	.name = "xm_sdc2",
228 	.channels = 1,
229 	.buswidth = 8,
230 	.qosbox = &(const struct qcom_icc_qosbox) {
231 		.num_ports = 1,
232 		.port_offsets = { 0xe000 },
233 		.prio = 2,
234 		.urg_fwd = 0,
235 	},
236 	.num_links = 1,
237 	.link_nodes = { &qns_a1noc_snoc },
238 };
239 
240 static struct qcom_icc_node xm_sdc4 = {
241 	.name = "xm_sdc4",
242 	.channels = 1,
243 	.buswidth = 8,
244 	.qosbox = &(const struct qcom_icc_qosbox) {
245 		.num_ports = 1,
246 		.port_offsets = { 0x9000 },
247 		.prio = 2,
248 		.urg_fwd = 0,
249 	},
250 	.num_links = 1,
251 	.link_nodes = { &qns_a1noc_snoc },
252 };
253 
254 static struct qcom_icc_node xm_ufs_mem = {
255 	.name = "xm_ufs_mem",
256 	.channels = 1,
257 	.buswidth = 8,
258 	.qosbox = &(const struct qcom_icc_qosbox) {
259 		.num_ports = 1,
260 		.port_offsets = { 0xa000 },
261 		.prio = 2,
262 		.urg_fwd = 0,
263 	},
264 	.num_links = 1,
265 	.link_nodes = { &qns_a1noc_snoc },
266 };
267 
268 static struct qcom_icc_node xm_usb2 = {
269 	.name = "xm_usb2",
270 	.channels = 1,
271 	.buswidth = 8,
272 	.num_links = 1,
273 	.link_nodes = { &qns_a1noc_snoc },
274 };
275 
276 static struct qcom_icc_node xm_usb3_0 = {
277 	.name = "xm_usb3_0",
278 	.channels = 1,
279 	.buswidth = 8,
280 	.qosbox = &(const struct qcom_icc_qosbox) {
281 		.num_ports = 1,
282 		.port_offsets = { 0xb000 },
283 		.prio = 2,
284 		.urg_fwd = 0,
285 	},
286 	.num_links = 1,
287 	.link_nodes = { &qns_a1noc_snoc },
288 };
289 
290 static struct qcom_icc_node qhm_qdss_bam = {
291 	.name = "qhm_qdss_bam",
292 	.channels = 1,
293 	.buswidth = 4,
294 	.qosbox = &(const struct qcom_icc_qosbox) {
295 		.num_ports = 1,
296 		.port_offsets = { 0x18000 },
297 		.prio = 2,
298 		.urg_fwd = 0,
299 	},
300 	.num_links = 1,
301 	.link_nodes = { &qns_a2noc_snoc },
302 };
303 
304 static struct qcom_icc_node qnm_a2noc_cfg = {
305 	.name = "qnm_a2noc_cfg",
306 	.channels = 1,
307 	.buswidth = 4,
308 	.num_links = 1,
309 	.link_nodes = { &srvc_aggre2_noc },
310 };
311 
312 static struct qcom_icc_node qnm_cnoc_datapath = {
313 	.name = "qnm_cnoc_datapath",
314 	.channels = 1,
315 	.buswidth = 8,
316 	.qosbox = &(const struct qcom_icc_qosbox) {
317 		.num_ports = 1,
318 		.port_offsets = { 0x1c000 },
319 		.prio = 2,
320 		.urg_fwd = 0,
321 	},
322 	.num_links = 1,
323 	.link_nodes = { &qns_a2noc_snoc },
324 };
325 
326 static struct qcom_icc_node qxm_crypto = {
327 	.name = "qxm_crypto",
328 	.channels = 1,
329 	.buswidth = 8,
330 	.qosbox = &(const struct qcom_icc_qosbox) {
331 		.num_ports = 1,
332 		.port_offsets = { 0x1d000 },
333 		.prio = 2,
334 		.urg_fwd = 0,
335 	},
336 	.num_links = 1,
337 	.link_nodes = { &qns_a2noc_snoc },
338 };
339 
340 static struct qcom_icc_node qxm_ipa = {
341 	.name = "qxm_ipa",
342 	.channels = 1,
343 	.buswidth = 8,
344 	.qosbox = &(const struct qcom_icc_qosbox) {
345 		.num_ports = 1,
346 		.port_offsets = { 0x10000 },
347 		.prio = 2,
348 		.urg_fwd = 0,
349 	},
350 	.num_links = 1,
351 	.link_nodes = { &qns_a2noc_snoc },
352 };
353 
354 static struct qcom_icc_node xm_pcie3_0 = {
355 	.name = "xm_pcie3_0",
356 	.channels = 1,
357 	.buswidth = 8,
358 	.num_links = 1,
359 	.link_nodes = { &qns_pcie_mem_noc },
360 };
361 
362 static struct qcom_icc_node xm_pcie3_1 = {
363 	.name = "xm_pcie3_1",
364 	.channels = 1,
365 	.buswidth = 8,
366 	.num_links = 1,
367 	.link_nodes = { &qns_pcie_mem_noc },
368 };
369 
370 static struct qcom_icc_node xm_qdss_etr = {
371 	.name = "xm_qdss_etr",
372 	.channels = 1,
373 	.buswidth = 8,
374 	.qosbox = &(const struct qcom_icc_qosbox) {
375 		.num_ports = 1,
376 		.port_offsets = { 0x15000 },
377 		.prio = 2,
378 		.urg_fwd = 0,
379 	},
380 	.num_links = 1,
381 	.link_nodes = { &qns_a2noc_snoc },
382 };
383 
384 static struct qcom_icc_node qup0_core_master = {
385 	.name = "qup0_core_master",
386 	.channels = 1,
387 	.buswidth = 4,
388 	.num_links = 1,
389 	.link_nodes = { &qup0_core_slave },
390 };
391 
392 static struct qcom_icc_node qup1_core_master = {
393 	.name = "qup1_core_master",
394 	.channels = 1,
395 	.buswidth = 4,
396 	.num_links = 1,
397 	.link_nodes = { &qup1_core_slave },
398 };
399 
400 static struct qcom_icc_node qnm_cnoc3_cnoc2 = {
401 	.name = "qnm_cnoc3_cnoc2",
402 	.channels = 1,
403 	.buswidth = 8,
404 	.num_links = 44,
405 	.link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1,
406 			&qhs_camera_cfg, &qhs_clk_ctl,
407 			&qhs_compute_cfg, &qhs_cpr_cx,
408 			&qhs_cpr_mx, &qhs_crypto0_cfg,
409 			&qhs_cx_rdpm, &qhs_dcc_cfg,
410 			&qhs_display_cfg, &qhs_gpuss_cfg,
411 			&qhs_hwkm, &qhs_imem_cfg,
412 			&qhs_ipa, &qhs_ipc_router,
413 			&qhs_lpass_cfg, &qhs_mss_cfg,
414 			&qhs_mx_rdpm, &qhs_pcie0_cfg,
415 			&qhs_pcie1_cfg, &qhs_pdm,
416 			&qhs_pimem_cfg, &qhs_pka_wrapper_cfg,
417 			&qhs_pmu_wrapper_cfg, &qhs_qdss_cfg,
418 			&qhs_qspi, &qhs_qup0,
419 			&qhs_qup1, &qhs_sdc1,
420 			&qhs_sdc2, &qhs_sdc4,
421 			&qhs_security, &qhs_tcsr,
422 			&qhs_tlmm, &qhs_ufs_mem_cfg,
423 			&qhs_usb2, &qhs_usb3_0,
424 			&qhs_venus_cfg, &qhs_vsense_ctrl_cfg,
425 			&qns_a1_noc_cfg, &qns_a2_noc_cfg,
426 			&qns_mnoc_cfg, &qns_snoc_cfg },
427 };
428 
429 static struct qcom_icc_node xm_qdss_dap = {
430 	.name = "xm_qdss_dap",
431 	.channels = 1,
432 	.buswidth = 8,
433 	.num_links = 45,
434 	.link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1,
435 			&qhs_camera_cfg, &qhs_clk_ctl,
436 			&qhs_compute_cfg, &qhs_cpr_cx,
437 			&qhs_cpr_mx, &qhs_crypto0_cfg,
438 			&qhs_cx_rdpm, &qhs_dcc_cfg,
439 			&qhs_display_cfg, &qhs_gpuss_cfg,
440 			&qhs_hwkm, &qhs_imem_cfg,
441 			&qhs_ipa, &qhs_ipc_router,
442 			&qhs_lpass_cfg, &qhs_mss_cfg,
443 			&qhs_mx_rdpm, &qhs_pcie0_cfg,
444 			&qhs_pcie1_cfg, &qhs_pdm,
445 			&qhs_pimem_cfg, &qhs_pka_wrapper_cfg,
446 			&qhs_pmu_wrapper_cfg, &qhs_qdss_cfg,
447 			&qhs_qspi, &qhs_qup0,
448 			&qhs_qup1, &qhs_sdc1,
449 			&qhs_sdc2, &qhs_sdc4,
450 			&qhs_security, &qhs_tcsr,
451 			&qhs_tlmm, &qhs_ufs_mem_cfg,
452 			&qhs_usb2, &qhs_usb3_0,
453 			&qhs_venus_cfg, &qhs_vsense_ctrl_cfg,
454 			&qns_a1_noc_cfg, &qns_a2_noc_cfg,
455 			&qns_cnoc2_cnoc3, &qns_mnoc_cfg,
456 			&qns_snoc_cfg },
457 };
458 
459 static struct qcom_icc_node qnm_cnoc2_cnoc3 = {
460 	.name = "qnm_cnoc2_cnoc3",
461 	.channels = 1,
462 	.buswidth = 8,
463 	.num_links = 9,
464 	.link_nodes = { &qhs_aoss, &qhs_apss,
465 			&qns_cnoc_a2noc, &qns_ddrss_cfg,
466 			&qxs_boot_imem, &qxs_imem,
467 			&qxs_pimem, &xs_qdss_stm,
468 			&xs_sys_tcu_cfg },
469 };
470 
471 static struct qcom_icc_node qnm_gemnoc_cnoc = {
472 	.name = "qnm_gemnoc_cnoc",
473 	.channels = 1,
474 	.buswidth = 16,
475 	.num_links = 9,
476 	.link_nodes = { &qhs_aoss, &qhs_apss,
477 			&qns_cnoc3_cnoc2, &qns_ddrss_cfg,
478 			&qxs_boot_imem, &qxs_imem,
479 			&qxs_pimem, &xs_qdss_stm,
480 			&xs_sys_tcu_cfg },
481 };
482 
483 static struct qcom_icc_node qnm_gemnoc_pcie = {
484 	.name = "qnm_gemnoc_pcie",
485 	.channels = 1,
486 	.buswidth = 8,
487 	.num_links = 2,
488 	.link_nodes = { &xs_pcie_0, &xs_pcie_1 },
489 };
490 
491 static struct qcom_icc_node qnm_cnoc_dc_noc = {
492 	.name = "qnm_cnoc_dc_noc",
493 	.channels = 1,
494 	.buswidth = 4,
495 	.num_links = 2,
496 	.link_nodes = { &qhs_llcc, &qns_gemnoc },
497 };
498 
499 static struct qcom_icc_node alm_gpu_tcu = {
500 	.name = "alm_gpu_tcu",
501 	.channels = 1,
502 	.buswidth = 8,
503 	.qosbox = &(const struct qcom_icc_qosbox) {
504 		.num_ports = 1,
505 		.port_offsets = { 0xd7000 },
506 		.prio = 2,
507 		.urg_fwd = 0,
508 	},
509 	.num_links = 2,
510 	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
511 };
512 
513 static struct qcom_icc_node alm_sys_tcu = {
514 	.name = "alm_sys_tcu",
515 	.channels = 1,
516 	.buswidth = 8,
517 	.qosbox = &(const struct qcom_icc_qosbox) {
518 		.num_ports = 1,
519 		.port_offsets = { 0xd6000 },
520 		.prio = 6,
521 		.urg_fwd = 0,
522 	},
523 	.num_links = 2,
524 	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
525 };
526 
527 static struct qcom_icc_node chm_apps = {
528 	.name = "chm_apps",
529 	.channels = 1,
530 	.buswidth = 32,
531 	.num_links = 3,
532 	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
533 			&qns_pcie },
534 };
535 
536 static struct qcom_icc_node qnm_cmpnoc = {
537 	.name = "qnm_cmpnoc",
538 	.channels = 2,
539 	.buswidth = 32,
540 	.qosbox = &(const struct qcom_icc_qosbox) {
541 		.num_ports = 2,
542 		.port_offsets = { 0x21000, 0x61000 },
543 		.prio = 0,
544 		.urg_fwd = 1,
545 	},
546 	.num_links = 2,
547 	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
548 };
549 
550 static struct qcom_icc_node qnm_gemnoc_cfg = {
551 	.name = "qnm_gemnoc_cfg",
552 	.channels = 1,
553 	.buswidth = 4,
554 	.num_links = 5,
555 	.link_nodes = { &qhs_mdsp_ms_mpu_cfg, &qhs_modem_ms_mpu_cfg,
556 			&srvc_even_gemnoc, &srvc_odd_gemnoc,
557 			&srvc_sys_gemnoc },
558 };
559 
560 static struct qcom_icc_node qnm_gpu = {
561 	.name = "qnm_gpu",
562 	.channels = 2,
563 	.buswidth = 32,
564 	.qosbox = &(const struct qcom_icc_qosbox) {
565 		.num_ports = 2,
566 		.port_offsets = { 0x22000, 0x62000 },
567 		.prio = 0,
568 		.urg_fwd = 0,
569 	},
570 	.num_links = 2,
571 	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
572 };
573 
574 static struct qcom_icc_node qnm_mnoc_hf = {
575 	.name = "qnm_mnoc_hf",
576 	.channels = 2,
577 	.buswidth = 32,
578 	.qosbox = &(const struct qcom_icc_qosbox) {
579 		.num_ports = 2,
580 		.port_offsets = { 0x23000, 0x63000 },
581 		.prio = 0,
582 		.urg_fwd = 1,
583 	},
584 	.num_links = 1,
585 	.link_nodes = { &qns_llcc },
586 };
587 
588 static struct qcom_icc_node qnm_mnoc_sf = {
589 	.name = "qnm_mnoc_sf",
590 	.channels = 1,
591 	.buswidth = 32,
592 	.qosbox = &(const struct qcom_icc_qosbox) {
593 		.num_ports = 1,
594 		.port_offsets = { 0xcf000 },
595 		.prio = 0,
596 		.urg_fwd = 1,
597 	},
598 	.num_links = 2,
599 	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
600 };
601 
602 static struct qcom_icc_node qnm_pcie = {
603 	.name = "qnm_pcie",
604 	.channels = 1,
605 	.buswidth = 16,
606 	.num_links = 2,
607 	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
608 };
609 
610 static struct qcom_icc_node qnm_snoc_gc = {
611 	.name = "qnm_snoc_gc",
612 	.channels = 1,
613 	.buswidth = 8,
614 	.qosbox = &(const struct qcom_icc_qosbox) {
615 		.num_ports = 1,
616 		.port_offsets = { 0xd3000 },
617 		.prio = 0,
618 		.urg_fwd = 1,
619 	},
620 	.num_links = 1,
621 	.link_nodes = { &qns_llcc },
622 };
623 
624 static struct qcom_icc_node qnm_snoc_sf = {
625 	.name = "qnm_snoc_sf",
626 	.channels = 1,
627 	.buswidth = 16,
628 	.qosbox = &(const struct qcom_icc_qosbox) {
629 		.num_ports = 1,
630 		.port_offsets = { 0xd4000 },
631 		.prio = 0,
632 		.urg_fwd = 1,
633 	},
634 	.num_links = 3,
635 	.link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
636 			&qns_pcie },
637 };
638 
639 static struct qcom_icc_node qhm_config_noc = {
640 	.name = "qhm_config_noc",
641 	.channels = 1,
642 	.buswidth = 4,
643 	.num_links = 6,
644 	.link_nodes = { &qhs_lpass_core, &qhs_lpass_lpi,
645 			&qhs_lpass_mpu, &qhs_lpass_top,
646 			&srvc_niu_aml_noc, &srvc_niu_lpass_agnoc },
647 };
648 
649 static struct qcom_icc_node llcc_mc = {
650 	.name = "llcc_mc",
651 	.channels = 2,
652 	.buswidth = 4,
653 	.num_links = 1,
654 	.link_nodes = { &ebi },
655 };
656 
657 static struct qcom_icc_node qnm_mnoc_cfg = {
658 	.name = "qnm_mnoc_cfg",
659 	.channels = 1,
660 	.buswidth = 4,
661 	.num_links = 1,
662 	.link_nodes = { &srvc_mnoc },
663 };
664 
665 static struct qcom_icc_node qnm_video0 = {
666 	.name = "qnm_video0",
667 	.channels = 1,
668 	.buswidth = 32,
669 	.qosbox = &(const struct qcom_icc_qosbox) {
670 		.num_ports = 1,
671 		.port_offsets = { 0x14000 },
672 		.prio = 0,
673 		.urg_fwd = 1,
674 	},
675 	.num_links = 1,
676 	.link_nodes = { &qns_mem_noc_sf },
677 };
678 
679 static struct qcom_icc_node qnm_video_cpu = {
680 	.name = "qnm_video_cpu",
681 	.channels = 1,
682 	.buswidth = 8,
683 	.qosbox = &(const struct qcom_icc_qosbox) {
684 		.num_ports = 1,
685 		.port_offsets = { 0x15000 },
686 		.prio = 0,
687 		.urg_fwd = 1,
688 	},
689 	.num_links = 1,
690 	.link_nodes = { &qns_mem_noc_sf },
691 };
692 
693 static struct qcom_icc_node qxm_camnoc_hf = {
694 	.name = "qxm_camnoc_hf",
695 	.channels = 2,
696 	.buswidth = 32,
697 	.qosbox = &(const struct qcom_icc_qosbox) {
698 		.num_ports = 2,
699 		.port_offsets = { 0x10000, 0x10180 },
700 		.prio = 0,
701 		.urg_fwd = 1,
702 	},
703 	.num_links = 1,
704 	.link_nodes = { &qns_mem_noc_hf },
705 };
706 
707 static struct qcom_icc_node qxm_camnoc_icp = {
708 	.name = "qxm_camnoc_icp",
709 	.channels = 1,
710 	.buswidth = 8,
711 	.qosbox = &(const struct qcom_icc_qosbox) {
712 		.num_ports = 1,
713 		.port_offsets = { 0x11000 },
714 		.prio = 0,
715 		.urg_fwd = 1,
716 	},
717 	.num_links = 1,
718 	.link_nodes = { &qns_mem_noc_sf },
719 };
720 
721 static struct qcom_icc_node qxm_camnoc_sf = {
722 	.name = "qxm_camnoc_sf",
723 	.channels = 1,
724 	.buswidth = 32,
725 	.qosbox = &(const struct qcom_icc_qosbox) {
726 		.num_ports = 1,
727 		.port_offsets = { 0x12000 },
728 		.prio = 0,
729 		.urg_fwd = 1,
730 	},
731 	.num_links = 1,
732 	.link_nodes = { &qns_mem_noc_sf },
733 };
734 
735 static struct qcom_icc_node qxm_mdp0 = {
736 	.name = "qxm_mdp0",
737 	.channels = 1,
738 	.buswidth = 32,
739 	.qosbox = &(const struct qcom_icc_qosbox) {
740 		.num_ports = 1,
741 		.port_offsets = { 0x16000 },
742 		.prio = 0,
743 		.urg_fwd = 1,
744 	},
745 	.num_links = 1,
746 	.link_nodes = { &qns_mem_noc_hf },
747 };
748 
749 static struct qcom_icc_node qhm_nsp_noc_config = {
750 	.name = "qhm_nsp_noc_config",
751 	.channels = 1,
752 	.buswidth = 4,
753 	.num_links = 1,
754 	.link_nodes = { &service_nsp_noc },
755 };
756 
757 static struct qcom_icc_node qxm_nsp = {
758 	.name = "qxm_nsp",
759 	.channels = 2,
760 	.buswidth = 32,
761 	.num_links = 1,
762 	.link_nodes = { &qns_nsp_gemnoc },
763 };
764 
765 static struct qcom_icc_node qnm_aggre1_noc = {
766 	.name = "qnm_aggre1_noc",
767 	.channels = 1,
768 	.buswidth = 16,
769 	.num_links = 1,
770 	.link_nodes = { &qns_gemnoc_sf },
771 };
772 
773 static struct qcom_icc_node qnm_aggre2_noc = {
774 	.name = "qnm_aggre2_noc",
775 	.channels = 1,
776 	.buswidth = 16,
777 	.num_links = 1,
778 	.link_nodes = { &qns_gemnoc_sf },
779 };
780 
781 static struct qcom_icc_node qnm_snoc_cfg = {
782 	.name = "qnm_snoc_cfg",
783 	.channels = 1,
784 	.buswidth = 4,
785 	.num_links = 1,
786 	.link_nodes = { &srvc_snoc },
787 };
788 
789 static struct qcom_icc_node qxm_pimem = {
790 	.name = "qxm_pimem",
791 	.channels = 1,
792 	.buswidth = 8,
793 	.qosbox = &(const struct qcom_icc_qosbox) {
794 		.num_ports = 1,
795 		.port_offsets = { 0x8000 },
796 		.prio = 2,
797 		.urg_fwd = 0,
798 	},
799 	.num_links = 1,
800 	.link_nodes = { &qns_gemnoc_gc },
801 };
802 
803 static struct qcom_icc_node xm_gic = {
804 	.name = "xm_gic",
805 	.channels = 1,
806 	.buswidth = 8,
807 	.qosbox = &(const struct qcom_icc_qosbox) {
808 		.num_ports = 1,
809 		.port_offsets = { 0xa000 },
810 		.prio = 2,
811 		.urg_fwd = 0,
812 	},
813 	.num_links = 1,
814 	.link_nodes = { &qns_gemnoc_gc },
815 };
816 
817 static struct qcom_icc_node qns_a1noc_snoc = {
818 	.name = "qns_a1noc_snoc",
819 	.channels = 1,
820 	.buswidth = 16,
821 	.num_links = 1,
822 	.link_nodes = { &qnm_aggre1_noc },
823 };
824 
825 static struct qcom_icc_node srvc_aggre1_noc = {
826 	.name = "srvc_aggre1_noc",
827 	.channels = 1,
828 	.buswidth = 4,
829 };
830 
831 static struct qcom_icc_node qns_a2noc_snoc = {
832 	.name = "qns_a2noc_snoc",
833 	.channels = 1,
834 	.buswidth = 16,
835 	.num_links = 1,
836 	.link_nodes = { &qnm_aggre2_noc },
837 };
838 
839 static struct qcom_icc_node qns_pcie_mem_noc = {
840 	.name = "qns_pcie_mem_noc",
841 	.channels = 1,
842 	.buswidth = 16,
843 	.num_links = 1,
844 	.link_nodes = { &qnm_pcie },
845 };
846 
847 static struct qcom_icc_node srvc_aggre2_noc = {
848 	.name = "srvc_aggre2_noc",
849 	.channels = 1,
850 	.buswidth = 4,
851 };
852 
853 static struct qcom_icc_node qup0_core_slave = {
854 	.name = "qup0_core_slave",
855 	.channels = 1,
856 	.buswidth = 4,
857 };
858 
859 static struct qcom_icc_node qup1_core_slave = {
860 	.name = "qup1_core_slave",
861 	.channels = 1,
862 	.buswidth = 4,
863 };
864 
865 static struct qcom_icc_node qhs_ahb2phy0 = {
866 	.name = "qhs_ahb2phy0",
867 	.channels = 1,
868 	.buswidth = 4,
869 };
870 
871 static struct qcom_icc_node qhs_ahb2phy1 = {
872 	.name = "qhs_ahb2phy1",
873 	.channels = 1,
874 	.buswidth = 4,
875 };
876 
877 static struct qcom_icc_node qhs_camera_cfg = {
878 	.name = "qhs_camera_cfg",
879 	.channels = 1,
880 	.buswidth = 4,
881 };
882 
883 static struct qcom_icc_node qhs_clk_ctl = {
884 	.name = "qhs_clk_ctl",
885 	.channels = 1,
886 	.buswidth = 4,
887 };
888 
889 static struct qcom_icc_node qhs_compute_cfg = {
890 	.name = "qhs_compute_cfg",
891 	.channels = 1,
892 	.buswidth = 4,
893 	.num_links = 1,
894 	.link_nodes = { &qhm_nsp_noc_config },
895 };
896 
897 static struct qcom_icc_node qhs_cpr_cx = {
898 	.name = "qhs_cpr_cx",
899 	.channels = 1,
900 	.buswidth = 4,
901 };
902 
903 static struct qcom_icc_node qhs_cpr_mx = {
904 	.name = "qhs_cpr_mx",
905 	.channels = 1,
906 	.buswidth = 4,
907 };
908 
909 static struct qcom_icc_node qhs_crypto0_cfg = {
910 	.name = "qhs_crypto0_cfg",
911 	.channels = 1,
912 	.buswidth = 4,
913 };
914 
915 static struct qcom_icc_node qhs_cx_rdpm = {
916 	.name = "qhs_cx_rdpm",
917 	.channels = 1,
918 	.buswidth = 4,
919 };
920 
921 static struct qcom_icc_node qhs_dcc_cfg = {
922 	.name = "qhs_dcc_cfg",
923 	.channels = 1,
924 	.buswidth = 4,
925 };
926 
927 static struct qcom_icc_node qhs_display_cfg = {
928 	.name = "qhs_display_cfg",
929 	.channels = 1,
930 	.buswidth = 4,
931 };
932 
933 static struct qcom_icc_node qhs_gpuss_cfg = {
934 	.name = "qhs_gpuss_cfg",
935 	.channels = 1,
936 	.buswidth = 8,
937 };
938 
939 static struct qcom_icc_node qhs_hwkm = {
940 	.name = "qhs_hwkm",
941 	.channels = 1,
942 	.buswidth = 4,
943 };
944 
945 static struct qcom_icc_node qhs_imem_cfg = {
946 	.name = "qhs_imem_cfg",
947 	.channels = 1,
948 	.buswidth = 4,
949 };
950 
951 static struct qcom_icc_node qhs_ipa = {
952 	.name = "qhs_ipa",
953 	.channels = 1,
954 	.buswidth = 4,
955 };
956 
957 static struct qcom_icc_node qhs_ipc_router = {
958 	.name = "qhs_ipc_router",
959 	.channels = 1,
960 	.buswidth = 4,
961 };
962 
963 static struct qcom_icc_node qhs_lpass_cfg = {
964 	.name = "qhs_lpass_cfg",
965 	.channels = 1,
966 	.buswidth = 4,
967 	.num_links = 1,
968 	.link_nodes = { &qhm_config_noc },
969 };
970 
971 static struct qcom_icc_node qhs_mss_cfg = {
972 	.name = "qhs_mss_cfg",
973 	.channels = 1,
974 	.buswidth = 4,
975 };
976 
977 static struct qcom_icc_node qhs_mx_rdpm = {
978 	.name = "qhs_mx_rdpm",
979 	.channels = 1,
980 	.buswidth = 4,
981 };
982 
983 static struct qcom_icc_node qhs_pcie0_cfg = {
984 	.name = "qhs_pcie0_cfg",
985 	.channels = 1,
986 	.buswidth = 4,
987 };
988 
989 static struct qcom_icc_node qhs_pcie1_cfg = {
990 	.name = "qhs_pcie1_cfg",
991 	.channels = 1,
992 	.buswidth = 4,
993 };
994 
995 static struct qcom_icc_node qhs_pdm = {
996 	.name = "qhs_pdm",
997 	.channels = 1,
998 	.buswidth = 4,
999 };
1000 
1001 static struct qcom_icc_node qhs_pimem_cfg = {
1002 	.name = "qhs_pimem_cfg",
1003 	.channels = 1,
1004 	.buswidth = 4,
1005 };
1006 
1007 static struct qcom_icc_node qhs_pka_wrapper_cfg = {
1008 	.name = "qhs_pka_wrapper_cfg",
1009 	.channels = 1,
1010 	.buswidth = 4,
1011 };
1012 
1013 static struct qcom_icc_node qhs_pmu_wrapper_cfg = {
1014 	.name = "qhs_pmu_wrapper_cfg",
1015 	.channels = 1,
1016 	.buswidth = 4,
1017 };
1018 
1019 static struct qcom_icc_node qhs_qdss_cfg = {
1020 	.name = "qhs_qdss_cfg",
1021 	.channels = 1,
1022 	.buswidth = 4,
1023 };
1024 
1025 static struct qcom_icc_node qhs_qspi = {
1026 	.name = "qhs_qspi",
1027 	.channels = 1,
1028 	.buswidth = 4,
1029 };
1030 
1031 static struct qcom_icc_node qhs_qup0 = {
1032 	.name = "qhs_qup0",
1033 	.channels = 1,
1034 	.buswidth = 4,
1035 };
1036 
1037 static struct qcom_icc_node qhs_qup1 = {
1038 	.name = "qhs_qup1",
1039 	.channels = 1,
1040 	.buswidth = 4,
1041 };
1042 
1043 static struct qcom_icc_node qhs_sdc1 = {
1044 	.name = "qhs_sdc1",
1045 	.channels = 1,
1046 	.buswidth = 4,
1047 };
1048 
1049 static struct qcom_icc_node qhs_sdc2 = {
1050 	.name = "qhs_sdc2",
1051 	.channels = 1,
1052 	.buswidth = 4,
1053 };
1054 
1055 static struct qcom_icc_node qhs_sdc4 = {
1056 	.name = "qhs_sdc4",
1057 	.channels = 1,
1058 	.buswidth = 4,
1059 };
1060 
1061 static struct qcom_icc_node qhs_security = {
1062 	.name = "qhs_security",
1063 	.channels = 1,
1064 	.buswidth = 4,
1065 };
1066 
1067 static struct qcom_icc_node qhs_tcsr = {
1068 	.name = "qhs_tcsr",
1069 	.channels = 1,
1070 	.buswidth = 4,
1071 };
1072 
1073 static struct qcom_icc_node qhs_tlmm = {
1074 	.name = "qhs_tlmm",
1075 	.channels = 1,
1076 	.buswidth = 4,
1077 };
1078 
1079 static struct qcom_icc_node qhs_ufs_mem_cfg = {
1080 	.name = "qhs_ufs_mem_cfg",
1081 	.channels = 1,
1082 	.buswidth = 4,
1083 };
1084 
1085 static struct qcom_icc_node qhs_usb2 = {
1086 	.name = "qhs_usb2",
1087 	.channels = 1,
1088 	.buswidth = 4,
1089 };
1090 
1091 static struct qcom_icc_node qhs_usb3_0 = {
1092 	.name = "qhs_usb3_0",
1093 	.channels = 1,
1094 	.buswidth = 4,
1095 };
1096 
1097 static struct qcom_icc_node qhs_venus_cfg = {
1098 	.name = "qhs_venus_cfg",
1099 	.channels = 1,
1100 	.buswidth = 4,
1101 };
1102 
1103 static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
1104 	.name = "qhs_vsense_ctrl_cfg",
1105 	.channels = 1,
1106 	.buswidth = 4,
1107 };
1108 
1109 static struct qcom_icc_node qns_a1_noc_cfg = {
1110 	.name = "qns_a1_noc_cfg",
1111 	.channels = 1,
1112 	.buswidth = 4,
1113 	.num_links = 1,
1114 	.link_nodes = { &qnm_a1noc_cfg },
1115 };
1116 
1117 static struct qcom_icc_node qns_a2_noc_cfg = {
1118 	.name = "qns_a2_noc_cfg",
1119 	.channels = 1,
1120 	.buswidth = 4,
1121 	.num_links = 1,
1122 	.link_nodes = { &qnm_a2noc_cfg },
1123 };
1124 
1125 static struct qcom_icc_node qns_cnoc2_cnoc3 = {
1126 	.name = "qns_cnoc2_cnoc3",
1127 	.channels = 1,
1128 	.buswidth = 8,
1129 	.num_links = 1,
1130 	.link_nodes = { &qnm_cnoc2_cnoc3 },
1131 };
1132 
1133 static struct qcom_icc_node qns_mnoc_cfg = {
1134 	.name = "qns_mnoc_cfg",
1135 	.channels = 1,
1136 	.buswidth = 4,
1137 	.num_links = 1,
1138 	.link_nodes = { &qnm_mnoc_cfg },
1139 };
1140 
1141 static struct qcom_icc_node qns_snoc_cfg = {
1142 	.name = "qns_snoc_cfg",
1143 	.channels = 1,
1144 	.buswidth = 4,
1145 	.num_links = 1,
1146 	.link_nodes = { &qnm_snoc_cfg },
1147 };
1148 
1149 static struct qcom_icc_node qhs_aoss = {
1150 	.name = "qhs_aoss",
1151 	.channels = 1,
1152 	.buswidth = 4,
1153 };
1154 
1155 static struct qcom_icc_node qhs_apss = {
1156 	.name = "qhs_apss",
1157 	.channels = 1,
1158 	.buswidth = 8,
1159 };
1160 
1161 static struct qcom_icc_node qns_cnoc3_cnoc2 = {
1162 	.name = "qns_cnoc3_cnoc2",
1163 	.channels = 1,
1164 	.buswidth = 8,
1165 	.num_links = 1,
1166 	.link_nodes = { &qnm_cnoc3_cnoc2 },
1167 };
1168 
1169 static struct qcom_icc_node qns_cnoc_a2noc = {
1170 	.name = "qns_cnoc_a2noc",
1171 	.channels = 1,
1172 	.buswidth = 8,
1173 	.num_links = 1,
1174 	.link_nodes = { &qnm_cnoc_datapath },
1175 };
1176 
1177 static struct qcom_icc_node qns_ddrss_cfg = {
1178 	.name = "qns_ddrss_cfg",
1179 	.channels = 1,
1180 	.buswidth = 4,
1181 	.num_links = 1,
1182 	.link_nodes = { &qnm_cnoc_dc_noc },
1183 };
1184 
1185 static struct qcom_icc_node qxs_boot_imem = {
1186 	.name = "qxs_boot_imem",
1187 	.channels = 1,
1188 	.buswidth = 8,
1189 };
1190 
1191 static struct qcom_icc_node qxs_imem = {
1192 	.name = "qxs_imem",
1193 	.channels = 1,
1194 	.buswidth = 8,
1195 };
1196 
1197 static struct qcom_icc_node qxs_pimem = {
1198 	.name = "qxs_pimem",
1199 	.channels = 1,
1200 	.buswidth = 8,
1201 };
1202 
1203 static struct qcom_icc_node xs_pcie_0 = {
1204 	.name = "xs_pcie_0",
1205 	.channels = 1,
1206 	.buswidth = 8,
1207 };
1208 
1209 static struct qcom_icc_node xs_pcie_1 = {
1210 	.name = "xs_pcie_1",
1211 	.channels = 1,
1212 	.buswidth = 8,
1213 };
1214 
1215 static struct qcom_icc_node xs_qdss_stm = {
1216 	.name = "xs_qdss_stm",
1217 	.channels = 1,
1218 	.buswidth = 4,
1219 };
1220 
1221 static struct qcom_icc_node xs_sys_tcu_cfg = {
1222 	.name = "xs_sys_tcu_cfg",
1223 	.channels = 1,
1224 	.buswidth = 8,
1225 };
1226 
1227 static struct qcom_icc_node qhs_llcc = {
1228 	.name = "qhs_llcc",
1229 	.channels = 1,
1230 	.buswidth = 4,
1231 };
1232 
1233 static struct qcom_icc_node qns_gemnoc = {
1234 	.name = "qns_gemnoc",
1235 	.channels = 1,
1236 	.buswidth = 4,
1237 	.num_links = 1,
1238 	.link_nodes = { &qnm_gemnoc_cfg },
1239 };
1240 
1241 static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = {
1242 	.name = "qhs_mdsp_ms_mpu_cfg",
1243 	.channels = 1,
1244 	.buswidth = 4,
1245 };
1246 
1247 static struct qcom_icc_node qhs_modem_ms_mpu_cfg = {
1248 	.name = "qhs_modem_ms_mpu_cfg",
1249 	.channels = 1,
1250 	.buswidth = 4,
1251 };
1252 
1253 static struct qcom_icc_node qns_gem_noc_cnoc = {
1254 	.name = "qns_gem_noc_cnoc",
1255 	.channels = 1,
1256 	.buswidth = 16,
1257 	.num_links = 1,
1258 	.link_nodes = { &qnm_gemnoc_cnoc },
1259 };
1260 
1261 static struct qcom_icc_node qns_llcc = {
1262 	.name = "qns_llcc",
1263 	.channels = 2,
1264 	.buswidth = 16,
1265 	.num_links = 1,
1266 	.link_nodes = { &llcc_mc },
1267 };
1268 
1269 static struct qcom_icc_node qns_pcie = {
1270 	.name = "qns_pcie",
1271 	.channels = 1,
1272 	.buswidth = 8,
1273 	.num_links = 1,
1274 	.link_nodes = { &qnm_gemnoc_pcie },
1275 };
1276 
1277 static struct qcom_icc_node srvc_even_gemnoc = {
1278 	.name = "srvc_even_gemnoc",
1279 	.channels = 1,
1280 	.buswidth = 4,
1281 };
1282 
1283 static struct qcom_icc_node srvc_odd_gemnoc = {
1284 	.name = "srvc_odd_gemnoc",
1285 	.channels = 1,
1286 	.buswidth = 4,
1287 };
1288 
1289 static struct qcom_icc_node srvc_sys_gemnoc = {
1290 	.name = "srvc_sys_gemnoc",
1291 	.channels = 1,
1292 	.buswidth = 4,
1293 };
1294 
1295 static struct qcom_icc_node qhs_lpass_core = {
1296 	.name = "qhs_lpass_core",
1297 	.channels = 1,
1298 	.buswidth = 4,
1299 };
1300 
1301 static struct qcom_icc_node qhs_lpass_lpi = {
1302 	.name = "qhs_lpass_lpi",
1303 	.channels = 1,
1304 	.buswidth = 4,
1305 };
1306 
1307 static struct qcom_icc_node qhs_lpass_mpu = {
1308 	.name = "qhs_lpass_mpu",
1309 	.channels = 1,
1310 	.buswidth = 4,
1311 };
1312 
1313 static struct qcom_icc_node qhs_lpass_top = {
1314 	.name = "qhs_lpass_top",
1315 	.channels = 1,
1316 	.buswidth = 4,
1317 };
1318 
1319 static struct qcom_icc_node srvc_niu_aml_noc = {
1320 	.name = "srvc_niu_aml_noc",
1321 	.channels = 1,
1322 	.buswidth = 4,
1323 };
1324 
1325 static struct qcom_icc_node srvc_niu_lpass_agnoc = {
1326 	.name = "srvc_niu_lpass_agnoc",
1327 	.channels = 1,
1328 	.buswidth = 4,
1329 };
1330 
1331 static struct qcom_icc_node ebi = {
1332 	.name = "ebi",
1333 	.channels = 2,
1334 	.buswidth = 4,
1335 };
1336 
1337 static struct qcom_icc_node qns_mem_noc_hf = {
1338 	.name = "qns_mem_noc_hf",
1339 	.channels = 2,
1340 	.buswidth = 32,
1341 	.num_links = 1,
1342 	.link_nodes = { &qnm_mnoc_hf },
1343 };
1344 
1345 static struct qcom_icc_node qns_mem_noc_sf = {
1346 	.name = "qns_mem_noc_sf",
1347 	.channels = 1,
1348 	.buswidth = 32,
1349 	.num_links = 1,
1350 	.link_nodes = { &qnm_mnoc_sf },
1351 };
1352 
1353 static struct qcom_icc_node srvc_mnoc = {
1354 	.name = "srvc_mnoc",
1355 	.channels = 1,
1356 	.buswidth = 4,
1357 };
1358 
1359 static struct qcom_icc_node qns_nsp_gemnoc = {
1360 	.name = "qns_nsp_gemnoc",
1361 	.channels = 2,
1362 	.buswidth = 32,
1363 	.num_links = 1,
1364 	.link_nodes = { &qnm_cmpnoc },
1365 };
1366 
1367 static struct qcom_icc_node service_nsp_noc = {
1368 	.name = "service_nsp_noc",
1369 	.channels = 1,
1370 	.buswidth = 4,
1371 };
1372 
1373 static struct qcom_icc_node qns_gemnoc_gc = {
1374 	.name = "qns_gemnoc_gc",
1375 	.channels = 1,
1376 	.buswidth = 8,
1377 	.num_links = 1,
1378 	.link_nodes = { &qnm_snoc_gc },
1379 };
1380 
1381 static struct qcom_icc_node qns_gemnoc_sf = {
1382 	.name = "qns_gemnoc_sf",
1383 	.channels = 1,
1384 	.buswidth = 16,
1385 	.num_links = 1,
1386 	.link_nodes = { &qnm_snoc_sf },
1387 };
1388 
1389 static struct qcom_icc_node srvc_snoc = {
1390 	.name = "srvc_snoc",
1391 	.channels = 1,
1392 	.buswidth = 4,
1393 };
1394 
1395 static struct qcom_icc_bcm bcm_acv = {
1396 	.name = "ACV",
1397 	.enable_mask = BIT(3),
1398 	.num_nodes = 1,
1399 	.nodes = { &ebi },
1400 };
1401 
1402 static struct qcom_icc_bcm bcm_ce0 = {
1403 	.name = "CE0",
1404 	.num_nodes = 1,
1405 	.nodes = { &qxm_crypto },
1406 };
1407 
1408 static struct qcom_icc_bcm bcm_cn0 = {
1409 	.name = "CN0",
1410 	.keepalive = true,
1411 	.num_nodes = 2,
1412 	.nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie },
1413 };
1414 
1415 static struct qcom_icc_bcm bcm_cn1 = {
1416 	.name = "CN1",
1417 	.num_nodes = 47,
1418 	.nodes = { &qnm_cnoc3_cnoc2, &xm_qdss_dap,
1419 		   &qhs_ahb2phy0, &qhs_ahb2phy1,
1420 		   &qhs_camera_cfg, &qhs_clk_ctl,
1421 		   &qhs_compute_cfg, &qhs_cpr_cx,
1422 		   &qhs_cpr_mx, &qhs_crypto0_cfg,
1423 		   &qhs_cx_rdpm, &qhs_dcc_cfg,
1424 		   &qhs_display_cfg, &qhs_gpuss_cfg,
1425 		   &qhs_hwkm, &qhs_imem_cfg,
1426 		   &qhs_ipa, &qhs_ipc_router,
1427 		   &qhs_mss_cfg, &qhs_mx_rdpm,
1428 		   &qhs_pcie0_cfg, &qhs_pcie1_cfg,
1429 		   &qhs_pimem_cfg, &qhs_pka_wrapper_cfg,
1430 		   &qhs_pmu_wrapper_cfg, &qhs_qdss_cfg,
1431 		   &qhs_qup0, &qhs_qup1,
1432 		   &qhs_security, &qhs_tcsr,
1433 		   &qhs_tlmm, &qhs_ufs_mem_cfg, &qhs_usb2,
1434 		   &qhs_usb3_0, &qhs_venus_cfg,
1435 		   &qhs_vsense_ctrl_cfg, &qns_a1_noc_cfg,
1436 		   &qns_a2_noc_cfg, &qns_cnoc2_cnoc3,
1437 		   &qns_mnoc_cfg, &qns_snoc_cfg,
1438 		   &qnm_cnoc2_cnoc3, &qhs_aoss,
1439 		   &qhs_apss, &qns_cnoc3_cnoc2,
1440 		   &qns_cnoc_a2noc, &qns_ddrss_cfg },
1441 };
1442 
1443 static struct qcom_icc_bcm bcm_cn2 = {
1444 	.name = "CN2",
1445 	.num_nodes = 6,
1446 	.nodes = { &qhs_lpass_cfg, &qhs_pdm,
1447 		   &qhs_qspi, &qhs_sdc1,
1448 		   &qhs_sdc2, &qhs_sdc4 },
1449 };
1450 
1451 static struct qcom_icc_bcm bcm_co0 = {
1452 	.name = "CO0",
1453 	.num_nodes = 1,
1454 	.nodes = { &qns_nsp_gemnoc },
1455 };
1456 
1457 static struct qcom_icc_bcm bcm_co3 = {
1458 	.name = "CO3",
1459 	.num_nodes = 1,
1460 	.nodes = { &qxm_nsp },
1461 };
1462 
1463 static struct qcom_icc_bcm bcm_mc0 = {
1464 	.name = "MC0",
1465 	.keepalive = true,
1466 	.num_nodes = 1,
1467 	.nodes = { &ebi },
1468 };
1469 
1470 static struct qcom_icc_bcm bcm_mm0 = {
1471 	.name = "MM0",
1472 	.keepalive = true,
1473 	.num_nodes = 1,
1474 	.nodes = { &qns_mem_noc_hf },
1475 };
1476 
1477 static struct qcom_icc_bcm bcm_mm1 = {
1478 	.name = "MM1",
1479 	.num_nodes = 2,
1480 	.nodes = { &qxm_camnoc_hf, &qxm_mdp0 },
1481 };
1482 
1483 static struct qcom_icc_bcm bcm_mm4 = {
1484 	.name = "MM4",
1485 	.num_nodes = 1,
1486 	.nodes = { &qns_mem_noc_sf },
1487 };
1488 
1489 static struct qcom_icc_bcm bcm_mm5 = {
1490 	.name = "MM5",
1491 	.num_nodes = 3,
1492 	.nodes = { &qnm_video0, &qxm_camnoc_icp,
1493 		   &qxm_camnoc_sf },
1494 };
1495 
1496 static struct qcom_icc_bcm bcm_qup0 = {
1497 	.name = "QUP0",
1498 	.vote_scale = 1,
1499 	.num_nodes = 1,
1500 	.nodes = { &qup0_core_slave },
1501 };
1502 
1503 static struct qcom_icc_bcm bcm_qup1 = {
1504 	.name = "QUP1",
1505 	.vote_scale = 1,
1506 	.num_nodes = 1,
1507 	.nodes = { &qup1_core_slave },
1508 };
1509 
1510 static struct qcom_icc_bcm bcm_sh0 = {
1511 	.name = "SH0",
1512 	.keepalive = true,
1513 	.num_nodes = 1,
1514 	.nodes = { &qns_llcc },
1515 };
1516 
1517 static struct qcom_icc_bcm bcm_sh2 = {
1518 	.name = "SH2",
1519 	.num_nodes = 2,
1520 	.nodes = { &alm_gpu_tcu, &alm_sys_tcu },
1521 };
1522 
1523 static struct qcom_icc_bcm bcm_sh3 = {
1524 	.name = "SH3",
1525 	.num_nodes = 1,
1526 	.nodes = { &qnm_cmpnoc },
1527 };
1528 
1529 static struct qcom_icc_bcm bcm_sh4 = {
1530 	.name = "SH4",
1531 	.num_nodes = 1,
1532 	.nodes = { &chm_apps },
1533 };
1534 
1535 static struct qcom_icc_bcm bcm_sn0 = {
1536 	.name = "SN0",
1537 	.keepalive = true,
1538 	.num_nodes = 1,
1539 	.nodes = { &qns_gemnoc_sf },
1540 };
1541 
1542 static struct qcom_icc_bcm bcm_sn2 = {
1543 	.name = "SN2",
1544 	.num_nodes = 1,
1545 	.nodes = { &qns_gemnoc_gc },
1546 };
1547 
1548 static struct qcom_icc_bcm bcm_sn3 = {
1549 	.name = "SN3",
1550 	.num_nodes = 1,
1551 	.nodes = { &qxs_pimem },
1552 };
1553 
1554 static struct qcom_icc_bcm bcm_sn4 = {
1555 	.name = "SN4",
1556 	.num_nodes = 1,
1557 	.nodes = { &xs_qdss_stm },
1558 };
1559 
1560 static struct qcom_icc_bcm bcm_sn5 = {
1561 	.name = "SN5",
1562 	.num_nodes = 1,
1563 	.nodes = { &xm_pcie3_0 },
1564 };
1565 
1566 static struct qcom_icc_bcm bcm_sn6 = {
1567 	.name = "SN6",
1568 	.num_nodes = 1,
1569 	.nodes = { &xm_pcie3_1 },
1570 };
1571 
1572 static struct qcom_icc_bcm bcm_sn7 = {
1573 	.name = "SN7",
1574 	.num_nodes = 1,
1575 	.nodes = { &qnm_aggre1_noc },
1576 };
1577 
1578 static struct qcom_icc_bcm bcm_sn8 = {
1579 	.name = "SN8",
1580 	.num_nodes = 1,
1581 	.nodes = { &qnm_aggre2_noc },
1582 };
1583 
1584 static struct qcom_icc_bcm bcm_sn14 = {
1585 	.name = "SN14",
1586 	.num_nodes = 1,
1587 	.nodes = { &qns_pcie_mem_noc },
1588 };
1589 
1590 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
1591 	&bcm_sn5,
1592 	&bcm_sn6,
1593 	&bcm_sn14,
1594 };
1595 
1596 static struct qcom_icc_node * const aggre1_noc_nodes[] = {
1597 	[MASTER_QSPI_0] = &qhm_qspi,
1598 	[MASTER_QUP_0] = &qhm_qup0,
1599 	[MASTER_QUP_1] = &qhm_qup1,
1600 	[MASTER_A1NOC_CFG] = &qnm_a1noc_cfg,
1601 	[MASTER_PCIE_0] = &xm_pcie3_0,
1602 	[MASTER_PCIE_1] = &xm_pcie3_1,
1603 	[MASTER_SDCC_1] = &xm_sdc1,
1604 	[MASTER_SDCC_2] = &xm_sdc2,
1605 	[MASTER_SDCC_4] = &xm_sdc4,
1606 	[MASTER_UFS_MEM] = &xm_ufs_mem,
1607 	[MASTER_USB2] = &xm_usb2,
1608 	[MASTER_USB3_0] = &xm_usb3_0,
1609 	[SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
1610 	[SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
1611 	[SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
1612 };
1613 
1614 static const struct regmap_config sc7280_aggre1_noc_regmap_config = {
1615 	.reg_bits = 32,
1616 	.reg_stride = 4,
1617 	.val_bits = 32,
1618 	.max_register = 0x1c080,
1619 	.fast_io = true,
1620 };
1621 
1622 static const struct qcom_icc_desc sc7280_aggre1_noc = {
1623 	.config = &sc7280_aggre1_noc_regmap_config,
1624 	.nodes = aggre1_noc_nodes,
1625 	.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
1626 	.bcms = aggre1_noc_bcms,
1627 	.num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
1628 	.qos_requires_clocks = true,
1629 };
1630 
1631 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
1632 	&bcm_ce0,
1633 };
1634 
1635 static const struct regmap_config sc7280_aggre2_noc_regmap_config = {
1636 	.reg_bits = 32,
1637 	.reg_stride = 4,
1638 	.val_bits = 32,
1639 	.max_register = 0x2b080,
1640 	.fast_io = true,
1641 };
1642 
1643 static struct qcom_icc_node * const aggre2_noc_nodes[] = {
1644 	[MASTER_QDSS_BAM] = &qhm_qdss_bam,
1645 	[MASTER_A2NOC_CFG] = &qnm_a2noc_cfg,
1646 	[MASTER_CNOC_A2NOC] = &qnm_cnoc_datapath,
1647 	[MASTER_CRYPTO] = &qxm_crypto,
1648 	[MASTER_IPA] = &qxm_ipa,
1649 	[MASTER_QDSS_ETR] = &xm_qdss_etr,
1650 	[SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
1651 	[SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
1652 };
1653 
1654 static const struct qcom_icc_desc sc7280_aggre2_noc = {
1655 	.config = &sc7280_aggre2_noc_regmap_config,
1656 	.nodes = aggre2_noc_nodes,
1657 	.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
1658 	.bcms = aggre2_noc_bcms,
1659 	.num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
1660 	.qos_requires_clocks = true,
1661 };
1662 
1663 static struct qcom_icc_bcm * const clk_virt_bcms[] = {
1664 	&bcm_qup0,
1665 	&bcm_qup1,
1666 };
1667 
1668 static struct qcom_icc_node * const clk_virt_nodes[] = {
1669 	[MASTER_QUP_CORE_0] = &qup0_core_master,
1670 	[MASTER_QUP_CORE_1] = &qup1_core_master,
1671 	[SLAVE_QUP_CORE_0] = &qup0_core_slave,
1672 	[SLAVE_QUP_CORE_1] = &qup1_core_slave,
1673 };
1674 
1675 static const struct qcom_icc_desc sc7280_clk_virt = {
1676 	.nodes = clk_virt_nodes,
1677 	.num_nodes = ARRAY_SIZE(clk_virt_nodes),
1678 	.bcms = clk_virt_bcms,
1679 	.num_bcms = ARRAY_SIZE(clk_virt_bcms),
1680 };
1681 
1682 static struct qcom_icc_bcm * const cnoc2_bcms[] = {
1683 	&bcm_cn1,
1684 	&bcm_cn2,
1685 };
1686 
1687 static struct qcom_icc_node * const cnoc2_nodes[] = {
1688 	[MASTER_CNOC3_CNOC2] = &qnm_cnoc3_cnoc2,
1689 	[MASTER_QDSS_DAP] = &xm_qdss_dap,
1690 	[SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
1691 	[SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1,
1692 	[SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
1693 	[SLAVE_CLK_CTL] = &qhs_clk_ctl,
1694 	[SLAVE_CDSP_CFG] = &qhs_compute_cfg,
1695 	[SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
1696 	[SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
1697 	[SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
1698 	[SLAVE_CX_RDPM] = &qhs_cx_rdpm,
1699 	[SLAVE_DCC_CFG] = &qhs_dcc_cfg,
1700 	[SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
1701 	[SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
1702 	[SLAVE_HWKM] = &qhs_hwkm,
1703 	[SLAVE_IMEM_CFG] = &qhs_imem_cfg,
1704 	[SLAVE_IPA_CFG] = &qhs_ipa,
1705 	[SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
1706 	[SLAVE_LPASS] = &qhs_lpass_cfg,
1707 	[SLAVE_CNOC_MSS] = &qhs_mss_cfg,
1708 	[SLAVE_MX_RDPM] = &qhs_mx_rdpm,
1709 	[SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
1710 	[SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
1711 	[SLAVE_PDM] = &qhs_pdm,
1712 	[SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
1713 	[SLAVE_PKA_WRAPPER_CFG] = &qhs_pka_wrapper_cfg,
1714 	[SLAVE_PMU_WRAPPER_CFG] = &qhs_pmu_wrapper_cfg,
1715 	[SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
1716 	[SLAVE_QSPI_0] = &qhs_qspi,
1717 	[SLAVE_QUP_0] = &qhs_qup0,
1718 	[SLAVE_QUP_1] = &qhs_qup1,
1719 	[SLAVE_SDCC_1] = &qhs_sdc1,
1720 	[SLAVE_SDCC_2] = &qhs_sdc2,
1721 	[SLAVE_SDCC_4] = &qhs_sdc4,
1722 	[SLAVE_SECURITY] = &qhs_security,
1723 	[SLAVE_TCSR] = &qhs_tcsr,
1724 	[SLAVE_TLMM] = &qhs_tlmm,
1725 	[SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
1726 	[SLAVE_USB2] = &qhs_usb2,
1727 	[SLAVE_USB3_0] = &qhs_usb3_0,
1728 	[SLAVE_VENUS_CFG] = &qhs_venus_cfg,
1729 	[SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
1730 	[SLAVE_A1NOC_CFG] = &qns_a1_noc_cfg,
1731 	[SLAVE_A2NOC_CFG] = &qns_a2_noc_cfg,
1732 	[SLAVE_CNOC2_CNOC3] = &qns_cnoc2_cnoc3,
1733 	[SLAVE_CNOC_MNOC_CFG] = &qns_mnoc_cfg,
1734 	[SLAVE_SNOC_CFG] = &qns_snoc_cfg,
1735 };
1736 
1737 static const struct regmap_config sc7280_cnoc2_regmap_config = {
1738 	.reg_bits = 32,
1739 	.reg_stride = 4,
1740 	.val_bits = 32,
1741 	.max_register = 0x1000,
1742 	.fast_io = true,
1743 };
1744 
1745 static const struct qcom_icc_desc sc7280_cnoc2 = {
1746 	.config = &sc7280_cnoc2_regmap_config,
1747 	.nodes = cnoc2_nodes,
1748 	.num_nodes = ARRAY_SIZE(cnoc2_nodes),
1749 	.bcms = cnoc2_bcms,
1750 	.num_bcms = ARRAY_SIZE(cnoc2_bcms),
1751 };
1752 
1753 static struct qcom_icc_bcm * const cnoc3_bcms[] = {
1754 	&bcm_cn0,
1755 	&bcm_cn1,
1756 	&bcm_sn3,
1757 	&bcm_sn4,
1758 };
1759 
1760 static struct qcom_icc_node * const cnoc3_nodes[] = {
1761 	[MASTER_CNOC2_CNOC3] = &qnm_cnoc2_cnoc3,
1762 	[MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
1763 	[MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
1764 	[SLAVE_AOSS] = &qhs_aoss,
1765 	[SLAVE_APPSS] = &qhs_apss,
1766 	[SLAVE_CNOC3_CNOC2] = &qns_cnoc3_cnoc2,
1767 	[SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc,
1768 	[SLAVE_DDRSS_CFG] = &qns_ddrss_cfg,
1769 	[SLAVE_BOOT_IMEM] = &qxs_boot_imem,
1770 	[SLAVE_IMEM] = &qxs_imem,
1771 	[SLAVE_PIMEM] = &qxs_pimem,
1772 	[SLAVE_PCIE_0] = &xs_pcie_0,
1773 	[SLAVE_PCIE_1] = &xs_pcie_1,
1774 	[SLAVE_QDSS_STM] = &xs_qdss_stm,
1775 	[SLAVE_TCU] = &xs_sys_tcu_cfg,
1776 };
1777 
1778 static const struct regmap_config sc7280_cnoc3_regmap_config = {
1779 	.reg_bits = 32,
1780 	.reg_stride = 4,
1781 	.val_bits = 32,
1782 	.max_register = 0x1000,
1783 	.fast_io = true,
1784 };
1785 
1786 static const struct qcom_icc_desc sc7280_cnoc3 = {
1787 	.config = &sc7280_cnoc3_regmap_config,
1788 	.nodes = cnoc3_nodes,
1789 	.num_nodes = ARRAY_SIZE(cnoc3_nodes),
1790 	.bcms = cnoc3_bcms,
1791 	.num_bcms = ARRAY_SIZE(cnoc3_bcms),
1792 };
1793 
1794 static struct qcom_icc_bcm * const dc_noc_bcms[] = {
1795 };
1796 
1797 static struct qcom_icc_node * const dc_noc_nodes[] = {
1798 	[MASTER_CNOC_DC_NOC] = &qnm_cnoc_dc_noc,
1799 	[SLAVE_LLCC_CFG] = &qhs_llcc,
1800 	[SLAVE_GEM_NOC_CFG] = &qns_gemnoc,
1801 };
1802 
1803 static const struct regmap_config sc7280_dc_noc_regmap_config = {
1804 	.reg_bits = 32,
1805 	.reg_stride = 4,
1806 	.val_bits = 32,
1807 	.max_register = 0x5080,
1808 	.fast_io = true,
1809 };
1810 
1811 static const struct qcom_icc_desc sc7280_dc_noc = {
1812 	.config = &sc7280_dc_noc_regmap_config,
1813 	.nodes = dc_noc_nodes,
1814 	.num_nodes = ARRAY_SIZE(dc_noc_nodes),
1815 	.bcms = dc_noc_bcms,
1816 	.num_bcms = ARRAY_SIZE(dc_noc_bcms),
1817 };
1818 
1819 static struct qcom_icc_bcm * const gem_noc_bcms[] = {
1820 	&bcm_sh0,
1821 	&bcm_sh2,
1822 	&bcm_sh3,
1823 	&bcm_sh4,
1824 };
1825 
1826 static struct qcom_icc_node * const gem_noc_nodes[] = {
1827 	[MASTER_GPU_TCU] = &alm_gpu_tcu,
1828 	[MASTER_SYS_TCU] = &alm_sys_tcu,
1829 	[MASTER_APPSS_PROC] = &chm_apps,
1830 	[MASTER_COMPUTE_NOC] = &qnm_cmpnoc,
1831 	[MASTER_GEM_NOC_CFG] = &qnm_gemnoc_cfg,
1832 	[MASTER_GFX3D] = &qnm_gpu,
1833 	[MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
1834 	[MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
1835 	[MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
1836 	[MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
1837 	[MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
1838 	[SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg,
1839 	[SLAVE_MCDMA_MS_MPU_CFG] = &qhs_modem_ms_mpu_cfg,
1840 	[SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
1841 	[SLAVE_LLCC] = &qns_llcc,
1842 	[SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
1843 	[SLAVE_SERVICE_GEM_NOC_1] = &srvc_even_gemnoc,
1844 	[SLAVE_SERVICE_GEM_NOC_2] = &srvc_odd_gemnoc,
1845 	[SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc,
1846 };
1847 
1848 static const struct regmap_config sc7280_gem_noc_regmap_config = {
1849 	.reg_bits = 32,
1850 	.reg_stride = 4,
1851 	.val_bits = 32,
1852 	.max_register = 0xe2200,
1853 	.fast_io = true,
1854 };
1855 
1856 static const struct qcom_icc_desc sc7280_gem_noc = {
1857 	.config = &sc7280_gem_noc_regmap_config,
1858 	.nodes = gem_noc_nodes,
1859 	.num_nodes = ARRAY_SIZE(gem_noc_nodes),
1860 	.bcms = gem_noc_bcms,
1861 	.num_bcms = ARRAY_SIZE(gem_noc_bcms),
1862 };
1863 
1864 static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = {
1865 };
1866 
1867 static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
1868 	[MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc,
1869 	[SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core,
1870 	[SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi,
1871 	[SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu,
1872 	[SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top,
1873 	[SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc,
1874 	[SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc,
1875 };
1876 
1877 static const struct regmap_config sc7280_lpass_ag_noc_regmap_config = {
1878 	.reg_bits = 32,
1879 	.reg_stride = 4,
1880 	.val_bits = 32,
1881 	.max_register = 0xf080,
1882 	.fast_io = true,
1883 };
1884 
1885 static const struct qcom_icc_desc sc7280_lpass_ag_noc = {
1886 	.config = &sc7280_lpass_ag_noc_regmap_config,
1887 	.nodes = lpass_ag_noc_nodes,
1888 	.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
1889 	.bcms = lpass_ag_noc_bcms,
1890 	.num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms),
1891 };
1892 
1893 static struct qcom_icc_bcm * const mc_virt_bcms[] = {
1894 	&bcm_acv,
1895 	&bcm_mc0,
1896 };
1897 
1898 static struct qcom_icc_node * const mc_virt_nodes[] = {
1899 	[MASTER_LLCC] = &llcc_mc,
1900 	[SLAVE_EBI1] = &ebi,
1901 };
1902 
1903 static const struct regmap_config sc7280_mc_virt_regmap_config = {
1904 	.reg_bits = 32,
1905 	.reg_stride = 4,
1906 	.val_bits = 32,
1907 	.max_register = 0x4,
1908 	.fast_io = true,
1909 };
1910 
1911 static const struct qcom_icc_desc sc7280_mc_virt = {
1912 	.config = &sc7280_mc_virt_regmap_config,
1913 	.nodes = mc_virt_nodes,
1914 	.num_nodes = ARRAY_SIZE(mc_virt_nodes),
1915 	.bcms = mc_virt_bcms,
1916 	.num_bcms = ARRAY_SIZE(mc_virt_bcms),
1917 };
1918 
1919 static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
1920 	&bcm_mm0,
1921 	&bcm_mm1,
1922 	&bcm_mm4,
1923 	&bcm_mm5,
1924 };
1925 
1926 static struct qcom_icc_node * const mmss_noc_nodes[] = {
1927 	[MASTER_CNOC_MNOC_CFG] = &qnm_mnoc_cfg,
1928 	[MASTER_VIDEO_P0] = &qnm_video0,
1929 	[MASTER_VIDEO_PROC] = &qnm_video_cpu,
1930 	[MASTER_CAMNOC_HF] = &qxm_camnoc_hf,
1931 	[MASTER_CAMNOC_ICP] = &qxm_camnoc_icp,
1932 	[MASTER_CAMNOC_SF] = &qxm_camnoc_sf,
1933 	[MASTER_MDP0] = &qxm_mdp0,
1934 	[SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
1935 	[SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
1936 	[SLAVE_SERVICE_MNOC] = &srvc_mnoc,
1937 };
1938 
1939 static const struct regmap_config sc7280_mmss_noc_regmap_config = {
1940 	.reg_bits = 32,
1941 	.reg_stride = 4,
1942 	.val_bits = 32,
1943 	.max_register = 0x1e080,
1944 	.fast_io = true,
1945 };
1946 
1947 static const struct qcom_icc_desc sc7280_mmss_noc = {
1948 	.config = &sc7280_mmss_noc_regmap_config,
1949 	.nodes = mmss_noc_nodes,
1950 	.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
1951 	.bcms = mmss_noc_bcms,
1952 	.num_bcms = ARRAY_SIZE(mmss_noc_bcms),
1953 };
1954 
1955 static struct qcom_icc_bcm * const nsp_noc_bcms[] = {
1956 	&bcm_co0,
1957 	&bcm_co3,
1958 };
1959 
1960 static struct qcom_icc_node * const nsp_noc_nodes[] = {
1961 	[MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config,
1962 	[MASTER_CDSP_PROC] = &qxm_nsp,
1963 	[SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc,
1964 	[SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc,
1965 };
1966 
1967 static const struct regmap_config sc7280_nsp_noc_regmap_config = {
1968 	.reg_bits = 32,
1969 	.reg_stride = 4,
1970 	.val_bits = 32,
1971 	.max_register = 0x10000,
1972 	.fast_io = true,
1973 };
1974 
1975 static const struct qcom_icc_desc sc7280_nsp_noc = {
1976 	.config = &sc7280_nsp_noc_regmap_config,
1977 	.nodes = nsp_noc_nodes,
1978 	.num_nodes = ARRAY_SIZE(nsp_noc_nodes),
1979 	.bcms = nsp_noc_bcms,
1980 	.num_bcms = ARRAY_SIZE(nsp_noc_bcms),
1981 };
1982 
1983 static struct qcom_icc_bcm * const system_noc_bcms[] = {
1984 	&bcm_sn0,
1985 	&bcm_sn2,
1986 	&bcm_sn7,
1987 	&bcm_sn8,
1988 };
1989 
1990 static struct qcom_icc_node * const system_noc_nodes[] = {
1991 	[MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
1992 	[MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
1993 	[MASTER_SNOC_CFG] = &qnm_snoc_cfg,
1994 	[MASTER_PIMEM] = &qxm_pimem,
1995 	[MASTER_GIC] = &xm_gic,
1996 	[SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
1997 	[SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
1998 	[SLAVE_SERVICE_SNOC] = &srvc_snoc,
1999 };
2000 
2001 static const struct regmap_config sc7280_system_noc_regmap_config = {
2002 	.reg_bits = 32,
2003 	.reg_stride = 4,
2004 	.val_bits = 32,
2005 	.max_register = 0x15480,
2006 	.fast_io = true,
2007 };
2008 
2009 static const struct qcom_icc_desc sc7280_system_noc = {
2010 	.config = &sc7280_system_noc_regmap_config,
2011 	.nodes = system_noc_nodes,
2012 	.num_nodes = ARRAY_SIZE(system_noc_nodes),
2013 	.bcms = system_noc_bcms,
2014 	.num_bcms = ARRAY_SIZE(system_noc_bcms),
2015 };
2016 
2017 static const struct of_device_id qnoc_of_match[] = {
2018 	{ .compatible = "qcom,sc7280-aggre1-noc",
2019 	  .data = &sc7280_aggre1_noc},
2020 	{ .compatible = "qcom,sc7280-aggre2-noc",
2021 	  .data = &sc7280_aggre2_noc},
2022 	{ .compatible = "qcom,sc7280-clk-virt",
2023 	  .data = &sc7280_clk_virt},
2024 	{ .compatible = "qcom,sc7280-cnoc2",
2025 	  .data = &sc7280_cnoc2},
2026 	{ .compatible = "qcom,sc7280-cnoc3",
2027 	  .data = &sc7280_cnoc3},
2028 	{ .compatible = "qcom,sc7280-dc-noc",
2029 	  .data = &sc7280_dc_noc},
2030 	{ .compatible = "qcom,sc7280-gem-noc",
2031 	  .data = &sc7280_gem_noc},
2032 	{ .compatible = "qcom,sc7280-lpass-ag-noc",
2033 	  .data = &sc7280_lpass_ag_noc},
2034 	{ .compatible = "qcom,sc7280-mc-virt",
2035 	  .data = &sc7280_mc_virt},
2036 	{ .compatible = "qcom,sc7280-mmss-noc",
2037 	  .data = &sc7280_mmss_noc},
2038 	{ .compatible = "qcom,sc7280-nsp-noc",
2039 	  .data = &sc7280_nsp_noc},
2040 	{ .compatible = "qcom,sc7280-system-noc",
2041 	  .data = &sc7280_system_noc},
2042 	{ }
2043 };
2044 MODULE_DEVICE_TABLE(of, qnoc_of_match);
2045 
2046 static struct platform_driver qnoc_driver = {
2047 	.probe = qcom_icc_rpmh_probe,
2048 	.remove = qcom_icc_rpmh_remove,
2049 	.driver = {
2050 		.name = "qnoc-sc7280",
2051 		.of_match_table = qnoc_of_match,
2052 		.sync_state = icc_sync_state,
2053 	},
2054 };
2055 module_platform_driver(qnoc_driver);
2056 
2057 MODULE_DESCRIPTION("SC7280 NoC driver");
2058 MODULE_LICENSE("GPL v2");
2059