1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 * 5 */ 6 7 #include <linux/device.h> 8 #include <linux/interconnect.h> 9 #include <linux/interconnect-provider.h> 10 #include <linux/mod_devicetable.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <dt-bindings/interconnect/qcom,sc7180.h> 14 15 #include "bcm-voter.h" 16 #include "icc-rpmh.h" 17 18 static struct qcom_icc_node qhm_a1noc_cfg; 19 static struct qcom_icc_node qhm_qspi; 20 static struct qcom_icc_node qhm_qup_0; 21 static struct qcom_icc_node xm_sdc2; 22 static struct qcom_icc_node xm_emmc; 23 static struct qcom_icc_node xm_ufs_mem; 24 static struct qcom_icc_node qhm_a2noc_cfg; 25 static struct qcom_icc_node qhm_qdss_bam; 26 static struct qcom_icc_node qhm_qup_1; 27 static struct qcom_icc_node qxm_crypto; 28 static struct qcom_icc_node qxm_ipa; 29 static struct qcom_icc_node xm_qdss_etr; 30 static struct qcom_icc_node qhm_usb3; 31 static struct qcom_icc_node qxm_camnoc_hf0_uncomp; 32 static struct qcom_icc_node qxm_camnoc_hf1_uncomp; 33 static struct qcom_icc_node qxm_camnoc_sf_uncomp; 34 static struct qcom_icc_node qnm_npu; 35 static struct qcom_icc_node qxm_npu_dsp; 36 static struct qcom_icc_node qnm_snoc; 37 static struct qcom_icc_node xm_qdss_dap; 38 static struct qcom_icc_node qhm_cnoc_dc_noc; 39 static struct qcom_icc_node acm_apps0; 40 static struct qcom_icc_node acm_sys_tcu; 41 static struct qcom_icc_node qhm_gemnoc_cfg; 42 static struct qcom_icc_node qnm_cmpnoc; 43 static struct qcom_icc_node qnm_mnoc_hf; 44 static struct qcom_icc_node qnm_mnoc_sf; 45 static struct qcom_icc_node qnm_snoc_gc; 46 static struct qcom_icc_node qnm_snoc_sf; 47 static struct qcom_icc_node qxm_gpu; 48 static struct qcom_icc_node llcc_mc; 49 static struct qcom_icc_node qhm_mnoc_cfg; 50 static struct qcom_icc_node qxm_camnoc_hf0; 51 static struct qcom_icc_node qxm_camnoc_hf1; 52 static struct qcom_icc_node qxm_camnoc_sf; 53 static struct qcom_icc_node qxm_mdp0; 54 static struct qcom_icc_node qxm_rot; 55 static struct qcom_icc_node qxm_venus0; 56 static struct qcom_icc_node qxm_venus_arm9; 57 static struct qcom_icc_node amm_npu_sys; 58 static struct qcom_icc_node qhm_npu_cfg; 59 static struct qcom_icc_node qup_core_master_1; 60 static struct qcom_icc_node qup_core_master_2; 61 static struct qcom_icc_node qhm_snoc_cfg; 62 static struct qcom_icc_node qnm_aggre1_noc; 63 static struct qcom_icc_node qnm_aggre2_noc; 64 static struct qcom_icc_node qnm_gemnoc; 65 static struct qcom_icc_node qxm_pimem; 66 static struct qcom_icc_node qns_a1noc_snoc; 67 static struct qcom_icc_node srvc_aggre1_noc; 68 static struct qcom_icc_node qns_a2noc_snoc; 69 static struct qcom_icc_node srvc_aggre2_noc; 70 static struct qcom_icc_node qns_camnoc_uncomp; 71 static struct qcom_icc_node qns_cdsp_gemnoc; 72 static struct qcom_icc_node qhs_a1_noc_cfg; 73 static struct qcom_icc_node qhs_a2_noc_cfg; 74 static struct qcom_icc_node qhs_ahb2phy0; 75 static struct qcom_icc_node qhs_ahb2phy2; 76 static struct qcom_icc_node qhs_aop; 77 static struct qcom_icc_node qhs_aoss; 78 static struct qcom_icc_node qhs_boot_rom; 79 static struct qcom_icc_node qhs_camera_cfg; 80 static struct qcom_icc_node qhs_camera_nrt_throttle_cfg; 81 static struct qcom_icc_node qhs_camera_rt_throttle_cfg; 82 static struct qcom_icc_node qhs_clk_ctl; 83 static struct qcom_icc_node qhs_cpr_cx; 84 static struct qcom_icc_node qhs_cpr_mx; 85 static struct qcom_icc_node qhs_crypto0_cfg; 86 static struct qcom_icc_node qhs_dcc_cfg; 87 static struct qcom_icc_node qhs_ddrss_cfg; 88 static struct qcom_icc_node qhs_display_cfg; 89 static struct qcom_icc_node qhs_display_rt_throttle_cfg; 90 static struct qcom_icc_node qhs_display_throttle_cfg; 91 static struct qcom_icc_node qhs_emmc_cfg; 92 static struct qcom_icc_node qhs_glm; 93 static struct qcom_icc_node qhs_gpuss_cfg; 94 static struct qcom_icc_node qhs_imem_cfg; 95 static struct qcom_icc_node qhs_ipa; 96 static struct qcom_icc_node qhs_mnoc_cfg; 97 static struct qcom_icc_node qhs_mss_cfg; 98 static struct qcom_icc_node qhs_npu_cfg; 99 static struct qcom_icc_node qhs_npu_dma_throttle_cfg; 100 static struct qcom_icc_node qhs_npu_dsp_throttle_cfg; 101 static struct qcom_icc_node qhs_pdm; 102 static struct qcom_icc_node qhs_pimem_cfg; 103 static struct qcom_icc_node qhs_prng; 104 static struct qcom_icc_node qhs_qdss_cfg; 105 static struct qcom_icc_node qhs_qm_cfg; 106 static struct qcom_icc_node qhs_qm_mpu_cfg; 107 static struct qcom_icc_node qhs_qspi; 108 static struct qcom_icc_node qhs_qup0; 109 static struct qcom_icc_node qhs_qup1; 110 static struct qcom_icc_node qhs_sdc2; 111 static struct qcom_icc_node qhs_security; 112 static struct qcom_icc_node qhs_snoc_cfg; 113 static struct qcom_icc_node qhs_tcsr; 114 static struct qcom_icc_node qhs_tlmm_1; 115 static struct qcom_icc_node qhs_tlmm_2; 116 static struct qcom_icc_node qhs_tlmm_3; 117 static struct qcom_icc_node qhs_ufs_mem_cfg; 118 static struct qcom_icc_node qhs_usb3; 119 static struct qcom_icc_node qhs_venus_cfg; 120 static struct qcom_icc_node qhs_venus_throttle_cfg; 121 static struct qcom_icc_node qhs_vsense_ctrl_cfg; 122 static struct qcom_icc_node srvc_cnoc; 123 static struct qcom_icc_node qhs_gemnoc; 124 static struct qcom_icc_node qhs_llcc; 125 static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg; 126 static struct qcom_icc_node qns_gem_noc_snoc; 127 static struct qcom_icc_node qns_llcc; 128 static struct qcom_icc_node srvc_gemnoc; 129 static struct qcom_icc_node ebi; 130 static struct qcom_icc_node qns_mem_noc_hf; 131 static struct qcom_icc_node qns_mem_noc_sf; 132 static struct qcom_icc_node srvc_mnoc; 133 static struct qcom_icc_node qhs_cal_dp0; 134 static struct qcom_icc_node qhs_cp; 135 static struct qcom_icc_node qhs_dma_bwmon; 136 static struct qcom_icc_node qhs_dpm; 137 static struct qcom_icc_node qhs_isense; 138 static struct qcom_icc_node qhs_llm; 139 static struct qcom_icc_node qhs_tcm; 140 static struct qcom_icc_node qns_npu_sys; 141 static struct qcom_icc_node srvc_noc; 142 static struct qcom_icc_node qup_core_slave_1; 143 static struct qcom_icc_node qup_core_slave_2; 144 static struct qcom_icc_node qhs_apss; 145 static struct qcom_icc_node qns_cnoc; 146 static struct qcom_icc_node qns_gemnoc_gc; 147 static struct qcom_icc_node qns_gemnoc_sf; 148 static struct qcom_icc_node qxs_imem; 149 static struct qcom_icc_node qxs_pimem; 150 static struct qcom_icc_node srvc_snoc; 151 static struct qcom_icc_node xs_qdss_stm; 152 static struct qcom_icc_node xs_sys_tcu_cfg; 153 154 static struct qcom_icc_node qhm_a1noc_cfg = { 155 .name = "qhm_a1noc_cfg", 156 .channels = 1, 157 .buswidth = 4, 158 .num_links = 1, 159 .link_nodes = { &srvc_aggre1_noc }, 160 }; 161 162 static struct qcom_icc_node qhm_qspi = { 163 .name = "qhm_qspi", 164 .channels = 1, 165 .buswidth = 4, 166 .num_links = 1, 167 .link_nodes = { &qns_a1noc_snoc }, 168 }; 169 170 static struct qcom_icc_node qhm_qup_0 = { 171 .name = "qhm_qup_0", 172 .channels = 1, 173 .buswidth = 4, 174 .num_links = 1, 175 .link_nodes = { &qns_a1noc_snoc }, 176 }; 177 178 static struct qcom_icc_node xm_sdc2 = { 179 .name = "xm_sdc2", 180 .channels = 1, 181 .buswidth = 8, 182 .num_links = 1, 183 .link_nodes = { &qns_a1noc_snoc }, 184 }; 185 186 static struct qcom_icc_node xm_emmc = { 187 .name = "xm_emmc", 188 .channels = 1, 189 .buswidth = 8, 190 .num_links = 1, 191 .link_nodes = { &qns_a1noc_snoc }, 192 }; 193 194 static struct qcom_icc_node xm_ufs_mem = { 195 .name = "xm_ufs_mem", 196 .channels = 1, 197 .buswidth = 8, 198 .num_links = 1, 199 .link_nodes = { &qns_a1noc_snoc }, 200 }; 201 202 static struct qcom_icc_node qhm_a2noc_cfg = { 203 .name = "qhm_a2noc_cfg", 204 .channels = 1, 205 .buswidth = 4, 206 .num_links = 1, 207 .link_nodes = { &srvc_aggre2_noc }, 208 }; 209 210 static struct qcom_icc_node qhm_qdss_bam = { 211 .name = "qhm_qdss_bam", 212 .channels = 1, 213 .buswidth = 4, 214 .num_links = 1, 215 .link_nodes = { &qns_a2noc_snoc }, 216 }; 217 218 static struct qcom_icc_node qhm_qup_1 = { 219 .name = "qhm_qup_1", 220 .channels = 1, 221 .buswidth = 4, 222 .num_links = 1, 223 .link_nodes = { &qns_a2noc_snoc }, 224 }; 225 226 static struct qcom_icc_node qxm_crypto = { 227 .name = "qxm_crypto", 228 .channels = 1, 229 .buswidth = 8, 230 .num_links = 1, 231 .link_nodes = { &qns_a2noc_snoc }, 232 }; 233 234 static struct qcom_icc_node qxm_ipa = { 235 .name = "qxm_ipa", 236 .channels = 1, 237 .buswidth = 8, 238 .num_links = 1, 239 .link_nodes = { &qns_a2noc_snoc }, 240 }; 241 242 static struct qcom_icc_node xm_qdss_etr = { 243 .name = "xm_qdss_etr", 244 .channels = 1, 245 .buswidth = 8, 246 .num_links = 1, 247 .link_nodes = { &qns_a2noc_snoc }, 248 }; 249 250 static struct qcom_icc_node qhm_usb3 = { 251 .name = "qhm_usb3", 252 .channels = 1, 253 .buswidth = 8, 254 .num_links = 1, 255 .link_nodes = { &qns_a2noc_snoc }, 256 }; 257 258 static struct qcom_icc_node qxm_camnoc_hf0_uncomp = { 259 .name = "qxm_camnoc_hf0_uncomp", 260 .channels = 1, 261 .buswidth = 32, 262 .num_links = 1, 263 .link_nodes = { &qns_camnoc_uncomp }, 264 }; 265 266 static struct qcom_icc_node qxm_camnoc_hf1_uncomp = { 267 .name = "qxm_camnoc_hf1_uncomp", 268 .channels = 1, 269 .buswidth = 32, 270 .num_links = 1, 271 .link_nodes = { &qns_camnoc_uncomp }, 272 }; 273 274 static struct qcom_icc_node qxm_camnoc_sf_uncomp = { 275 .name = "qxm_camnoc_sf_uncomp", 276 .channels = 1, 277 .buswidth = 32, 278 .num_links = 1, 279 .link_nodes = { &qns_camnoc_uncomp }, 280 }; 281 282 static struct qcom_icc_node qnm_npu = { 283 .name = "qnm_npu", 284 .channels = 2, 285 .buswidth = 32, 286 .num_links = 1, 287 .link_nodes = { &qns_cdsp_gemnoc }, 288 }; 289 290 static struct qcom_icc_node qxm_npu_dsp = { 291 .name = "qxm_npu_dsp", 292 .channels = 1, 293 .buswidth = 8, 294 .num_links = 1, 295 .link_nodes = { &qns_cdsp_gemnoc }, 296 }; 297 298 static struct qcom_icc_node qnm_snoc = { 299 .name = "qnm_snoc", 300 .channels = 1, 301 .buswidth = 8, 302 .num_links = 51, 303 .link_nodes = { &qhs_a1_noc_cfg, 304 &qhs_a2_noc_cfg, 305 &qhs_ahb2phy0, 306 &qhs_ahb2phy2, 307 &qhs_aop, 308 &qhs_aoss, 309 &qhs_boot_rom, 310 &qhs_camera_cfg, 311 &qhs_camera_nrt_throttle_cfg, 312 &qhs_camera_rt_throttle_cfg, 313 &qhs_clk_ctl, 314 &qhs_cpr_cx, 315 &qhs_cpr_mx, 316 &qhs_crypto0_cfg, 317 &qhs_dcc_cfg, 318 &qhs_ddrss_cfg, 319 &qhs_display_cfg, 320 &qhs_display_rt_throttle_cfg, 321 &qhs_display_throttle_cfg, 322 &qhs_emmc_cfg, 323 &qhs_glm, 324 &qhs_gpuss_cfg, 325 &qhs_imem_cfg, 326 &qhs_ipa, 327 &qhs_mnoc_cfg, 328 &qhs_mss_cfg, 329 &qhs_npu_cfg, 330 &qhs_npu_dma_throttle_cfg, 331 &qhs_npu_dsp_throttle_cfg, 332 &qhs_pdm, 333 &qhs_pimem_cfg, 334 &qhs_prng, 335 &qhs_qdss_cfg, 336 &qhs_qm_cfg, 337 &qhs_qm_mpu_cfg, 338 &qhs_qspi, 339 &qhs_qup0, 340 &qhs_qup1, 341 &qhs_sdc2, 342 &qhs_security, 343 &qhs_snoc_cfg, 344 &qhs_tcsr, 345 &qhs_tlmm_1, 346 &qhs_tlmm_2, 347 &qhs_tlmm_3, 348 &qhs_ufs_mem_cfg, 349 &qhs_usb3, 350 &qhs_venus_cfg, 351 &qhs_venus_throttle_cfg, 352 &qhs_vsense_ctrl_cfg, 353 &srvc_cnoc }, 354 }; 355 356 static struct qcom_icc_node xm_qdss_dap = { 357 .name = "xm_qdss_dap", 358 .channels = 1, 359 .buswidth = 8, 360 .num_links = 51, 361 .link_nodes = { &qhs_a1_noc_cfg, 362 &qhs_a2_noc_cfg, 363 &qhs_ahb2phy0, 364 &qhs_ahb2phy2, 365 &qhs_aop, 366 &qhs_aoss, 367 &qhs_boot_rom, 368 &qhs_camera_cfg, 369 &qhs_camera_nrt_throttle_cfg, 370 &qhs_camera_rt_throttle_cfg, 371 &qhs_clk_ctl, 372 &qhs_cpr_cx, 373 &qhs_cpr_mx, 374 &qhs_crypto0_cfg, 375 &qhs_dcc_cfg, 376 &qhs_ddrss_cfg, 377 &qhs_display_cfg, 378 &qhs_display_rt_throttle_cfg, 379 &qhs_display_throttle_cfg, 380 &qhs_emmc_cfg, 381 &qhs_glm, 382 &qhs_gpuss_cfg, 383 &qhs_imem_cfg, 384 &qhs_ipa, 385 &qhs_mnoc_cfg, 386 &qhs_mss_cfg, 387 &qhs_npu_cfg, 388 &qhs_npu_dma_throttle_cfg, 389 &qhs_npu_dsp_throttle_cfg, 390 &qhs_pdm, 391 &qhs_pimem_cfg, 392 &qhs_prng, 393 &qhs_qdss_cfg, 394 &qhs_qm_cfg, 395 &qhs_qm_mpu_cfg, 396 &qhs_qspi, 397 &qhs_qup0, 398 &qhs_qup1, 399 &qhs_sdc2, 400 &qhs_security, 401 &qhs_snoc_cfg, 402 &qhs_tcsr, 403 &qhs_tlmm_1, 404 &qhs_tlmm_2, 405 &qhs_tlmm_3, 406 &qhs_ufs_mem_cfg, 407 &qhs_usb3, 408 &qhs_venus_cfg, 409 &qhs_venus_throttle_cfg, 410 &qhs_vsense_ctrl_cfg, 411 &srvc_cnoc }, 412 }; 413 414 static struct qcom_icc_node qhm_cnoc_dc_noc = { 415 .name = "qhm_cnoc_dc_noc", 416 .channels = 1, 417 .buswidth = 4, 418 .num_links = 2, 419 .link_nodes = { &qhs_gemnoc, 420 &qhs_llcc }, 421 }; 422 423 static struct qcom_icc_node acm_apps0 = { 424 .name = "acm_apps0", 425 .channels = 1, 426 .buswidth = 16, 427 .num_links = 2, 428 .link_nodes = { &qns_gem_noc_snoc, 429 &qns_llcc }, 430 }; 431 432 static struct qcom_icc_node acm_sys_tcu = { 433 .name = "acm_sys_tcu", 434 .channels = 1, 435 .buswidth = 8, 436 .num_links = 2, 437 .link_nodes = { &qns_gem_noc_snoc, 438 &qns_llcc }, 439 }; 440 441 static struct qcom_icc_node qhm_gemnoc_cfg = { 442 .name = "qhm_gemnoc_cfg", 443 .channels = 1, 444 .buswidth = 4, 445 .num_links = 2, 446 .link_nodes = { &qhs_mdsp_ms_mpu_cfg, 447 &srvc_gemnoc }, 448 }; 449 450 static struct qcom_icc_node qnm_cmpnoc = { 451 .name = "qnm_cmpnoc", 452 .channels = 1, 453 .buswidth = 32, 454 .num_links = 2, 455 .link_nodes = { &qns_gem_noc_snoc, 456 &qns_llcc }, 457 }; 458 459 static struct qcom_icc_node qnm_mnoc_hf = { 460 .name = "qnm_mnoc_hf", 461 .channels = 1, 462 .buswidth = 32, 463 .num_links = 1, 464 .link_nodes = { &qns_llcc }, 465 }; 466 467 static struct qcom_icc_node qnm_mnoc_sf = { 468 .name = "qnm_mnoc_sf", 469 .channels = 1, 470 .buswidth = 32, 471 .num_links = 2, 472 .link_nodes = { &qns_gem_noc_snoc, 473 &qns_llcc }, 474 }; 475 476 static struct qcom_icc_node qnm_snoc_gc = { 477 .name = "qnm_snoc_gc", 478 .channels = 1, 479 .buswidth = 8, 480 .num_links = 1, 481 .link_nodes = { &qns_llcc }, 482 }; 483 484 static struct qcom_icc_node qnm_snoc_sf = { 485 .name = "qnm_snoc_sf", 486 .channels = 1, 487 .buswidth = 16, 488 .num_links = 1, 489 .link_nodes = { &qns_llcc }, 490 }; 491 492 static struct qcom_icc_node qxm_gpu = { 493 .name = "qxm_gpu", 494 .channels = 2, 495 .buswidth = 32, 496 .num_links = 2, 497 .link_nodes = { &qns_gem_noc_snoc, 498 &qns_llcc }, 499 }; 500 501 static struct qcom_icc_node llcc_mc = { 502 .name = "llcc_mc", 503 .channels = 2, 504 .buswidth = 4, 505 .num_links = 1, 506 .link_nodes = { &ebi }, 507 }; 508 509 static struct qcom_icc_node qhm_mnoc_cfg = { 510 .name = "qhm_mnoc_cfg", 511 .channels = 1, 512 .buswidth = 4, 513 .num_links = 1, 514 .link_nodes = { &srvc_mnoc }, 515 }; 516 517 static struct qcom_icc_node qxm_camnoc_hf0 = { 518 .name = "qxm_camnoc_hf0", 519 .channels = 2, 520 .buswidth = 32, 521 .num_links = 1, 522 .link_nodes = { &qns_mem_noc_hf }, 523 }; 524 525 static struct qcom_icc_node qxm_camnoc_hf1 = { 526 .name = "qxm_camnoc_hf1", 527 .channels = 2, 528 .buswidth = 32, 529 .num_links = 1, 530 .link_nodes = { &qns_mem_noc_hf }, 531 }; 532 533 static struct qcom_icc_node qxm_camnoc_sf = { 534 .name = "qxm_camnoc_sf", 535 .channels = 1, 536 .buswidth = 32, 537 .num_links = 1, 538 .link_nodes = { &qns_mem_noc_sf }, 539 }; 540 541 static struct qcom_icc_node qxm_mdp0 = { 542 .name = "qxm_mdp0", 543 .channels = 1, 544 .buswidth = 32, 545 .num_links = 1, 546 .link_nodes = { &qns_mem_noc_hf }, 547 }; 548 549 static struct qcom_icc_node qxm_rot = { 550 .name = "qxm_rot", 551 .channels = 1, 552 .buswidth = 16, 553 .num_links = 1, 554 .link_nodes = { &qns_mem_noc_sf }, 555 }; 556 557 static struct qcom_icc_node qxm_venus0 = { 558 .name = "qxm_venus0", 559 .channels = 1, 560 .buswidth = 32, 561 .num_links = 1, 562 .link_nodes = { &qns_mem_noc_sf }, 563 }; 564 565 static struct qcom_icc_node qxm_venus_arm9 = { 566 .name = "qxm_venus_arm9", 567 .channels = 1, 568 .buswidth = 8, 569 .num_links = 1, 570 .link_nodes = { &qns_mem_noc_sf }, 571 }; 572 573 static struct qcom_icc_node amm_npu_sys = { 574 .name = "amm_npu_sys", 575 .channels = 2, 576 .buswidth = 32, 577 .num_links = 1, 578 .link_nodes = { &qns_npu_sys }, 579 }; 580 581 static struct qcom_icc_node qhm_npu_cfg = { 582 .name = "qhm_npu_cfg", 583 .channels = 1, 584 .buswidth = 4, 585 .num_links = 8, 586 .link_nodes = { &qhs_cal_dp0, 587 &qhs_cp, 588 &qhs_dma_bwmon, 589 &qhs_dpm, 590 &qhs_isense, 591 &qhs_llm, 592 &qhs_tcm, 593 &srvc_noc }, 594 }; 595 596 static struct qcom_icc_node qup_core_master_1 = { 597 .name = "qup_core_master_1", 598 .channels = 1, 599 .buswidth = 4, 600 .num_links = 1, 601 .link_nodes = { &qup_core_slave_1 }, 602 }; 603 604 static struct qcom_icc_node qup_core_master_2 = { 605 .name = "qup_core_master_2", 606 .channels = 1, 607 .buswidth = 4, 608 .num_links = 1, 609 .link_nodes = { &qup_core_slave_2 }, 610 }; 611 612 static struct qcom_icc_node qhm_snoc_cfg = { 613 .name = "qhm_snoc_cfg", 614 .channels = 1, 615 .buswidth = 4, 616 .num_links = 1, 617 .link_nodes = { &srvc_snoc }, 618 }; 619 620 static struct qcom_icc_node qnm_aggre1_noc = { 621 .name = "qnm_aggre1_noc", 622 .channels = 1, 623 .buswidth = 16, 624 .num_links = 6, 625 .link_nodes = { &qhs_apss, 626 &qns_cnoc, 627 &qns_gemnoc_sf, 628 &qxs_imem, 629 &qxs_pimem, 630 &xs_qdss_stm }, 631 }; 632 633 static struct qcom_icc_node qnm_aggre2_noc = { 634 .name = "qnm_aggre2_noc", 635 .channels = 1, 636 .buswidth = 16, 637 .num_links = 7, 638 .link_nodes = { &qhs_apss, 639 &qns_cnoc, 640 &qns_gemnoc_sf, 641 &qxs_imem, 642 &qxs_pimem, 643 &xs_qdss_stm, 644 &xs_sys_tcu_cfg }, 645 }; 646 647 static struct qcom_icc_node qnm_gemnoc = { 648 .name = "qnm_gemnoc", 649 .channels = 1, 650 .buswidth = 8, 651 .num_links = 6, 652 .link_nodes = { &qhs_apss, 653 &qns_cnoc, 654 &qxs_imem, 655 &qxs_pimem, 656 &xs_qdss_stm, 657 &xs_sys_tcu_cfg }, 658 }; 659 660 static struct qcom_icc_node qxm_pimem = { 661 .name = "qxm_pimem", 662 .channels = 1, 663 .buswidth = 8, 664 .num_links = 2, 665 .link_nodes = { &qns_gemnoc_gc, 666 &qxs_imem }, 667 }; 668 669 static struct qcom_icc_node qns_a1noc_snoc = { 670 .name = "qns_a1noc_snoc", 671 .channels = 1, 672 .buswidth = 16, 673 .num_links = 1, 674 .link_nodes = { &qnm_aggre1_noc }, 675 }; 676 677 static struct qcom_icc_node srvc_aggre1_noc = { 678 .name = "srvc_aggre1_noc", 679 .channels = 1, 680 .buswidth = 4, 681 }; 682 683 static struct qcom_icc_node qns_a2noc_snoc = { 684 .name = "qns_a2noc_snoc", 685 .channels = 1, 686 .buswidth = 16, 687 .num_links = 1, 688 .link_nodes = { &qnm_aggre2_noc }, 689 }; 690 691 static struct qcom_icc_node srvc_aggre2_noc = { 692 .name = "srvc_aggre2_noc", 693 .channels = 1, 694 .buswidth = 4, 695 }; 696 697 static struct qcom_icc_node qns_camnoc_uncomp = { 698 .name = "qns_camnoc_uncomp", 699 .channels = 1, 700 .buswidth = 32, 701 }; 702 703 static struct qcom_icc_node qns_cdsp_gemnoc = { 704 .name = "qns_cdsp_gemnoc", 705 .channels = 1, 706 .buswidth = 32, 707 .num_links = 1, 708 .link_nodes = { &qnm_cmpnoc }, 709 }; 710 711 static struct qcom_icc_node qhs_a1_noc_cfg = { 712 .name = "qhs_a1_noc_cfg", 713 .channels = 1, 714 .buswidth = 4, 715 .num_links = 1, 716 .link_nodes = { &qhm_a1noc_cfg }, 717 }; 718 719 static struct qcom_icc_node qhs_a2_noc_cfg = { 720 .name = "qhs_a2_noc_cfg", 721 .channels = 1, 722 .buswidth = 4, 723 .num_links = 1, 724 .link_nodes = { &qhm_a2noc_cfg }, 725 }; 726 727 static struct qcom_icc_node qhs_ahb2phy0 = { 728 .name = "qhs_ahb2phy0", 729 .channels = 1, 730 .buswidth = 4, 731 }; 732 733 static struct qcom_icc_node qhs_ahb2phy2 = { 734 .name = "qhs_ahb2phy2", 735 .channels = 1, 736 .buswidth = 4, 737 }; 738 739 static struct qcom_icc_node qhs_aop = { 740 .name = "qhs_aop", 741 .channels = 1, 742 .buswidth = 4, 743 }; 744 745 static struct qcom_icc_node qhs_aoss = { 746 .name = "qhs_aoss", 747 .channels = 1, 748 .buswidth = 4, 749 }; 750 751 static struct qcom_icc_node qhs_boot_rom = { 752 .name = "qhs_boot_rom", 753 .channels = 1, 754 .buswidth = 4, 755 }; 756 757 static struct qcom_icc_node qhs_camera_cfg = { 758 .name = "qhs_camera_cfg", 759 .channels = 1, 760 .buswidth = 4, 761 }; 762 763 static struct qcom_icc_node qhs_camera_nrt_throttle_cfg = { 764 .name = "qhs_camera_nrt_throttle_cfg", 765 .channels = 1, 766 .buswidth = 4, 767 }; 768 769 static struct qcom_icc_node qhs_camera_rt_throttle_cfg = { 770 .name = "qhs_camera_rt_throttle_cfg", 771 .channels = 1, 772 .buswidth = 4, 773 }; 774 775 static struct qcom_icc_node qhs_clk_ctl = { 776 .name = "qhs_clk_ctl", 777 .channels = 1, 778 .buswidth = 4, 779 }; 780 781 static struct qcom_icc_node qhs_cpr_cx = { 782 .name = "qhs_cpr_cx", 783 .channels = 1, 784 .buswidth = 4, 785 }; 786 787 static struct qcom_icc_node qhs_cpr_mx = { 788 .name = "qhs_cpr_mx", 789 .channels = 1, 790 .buswidth = 4, 791 }; 792 793 static struct qcom_icc_node qhs_crypto0_cfg = { 794 .name = "qhs_crypto0_cfg", 795 .channels = 1, 796 .buswidth = 4, 797 }; 798 799 static struct qcom_icc_node qhs_dcc_cfg = { 800 .name = "qhs_dcc_cfg", 801 .channels = 1, 802 .buswidth = 4, 803 }; 804 805 static struct qcom_icc_node qhs_ddrss_cfg = { 806 .name = "qhs_ddrss_cfg", 807 .channels = 1, 808 .buswidth = 4, 809 .num_links = 1, 810 .link_nodes = { &qhm_cnoc_dc_noc }, 811 }; 812 813 static struct qcom_icc_node qhs_display_cfg = { 814 .name = "qhs_display_cfg", 815 .channels = 1, 816 .buswidth = 4, 817 }; 818 819 static struct qcom_icc_node qhs_display_rt_throttle_cfg = { 820 .name = "qhs_display_rt_throttle_cfg", 821 .channels = 1, 822 .buswidth = 4, 823 }; 824 825 static struct qcom_icc_node qhs_display_throttle_cfg = { 826 .name = "qhs_display_throttle_cfg", 827 .channels = 1, 828 .buswidth = 4, 829 }; 830 831 static struct qcom_icc_node qhs_emmc_cfg = { 832 .name = "qhs_emmc_cfg", 833 .channels = 1, 834 .buswidth = 4, 835 }; 836 837 static struct qcom_icc_node qhs_glm = { 838 .name = "qhs_glm", 839 .channels = 1, 840 .buswidth = 4, 841 }; 842 843 static struct qcom_icc_node qhs_gpuss_cfg = { 844 .name = "qhs_gpuss_cfg", 845 .channels = 1, 846 .buswidth = 8, 847 }; 848 849 static struct qcom_icc_node qhs_imem_cfg = { 850 .name = "qhs_imem_cfg", 851 .channels = 1, 852 .buswidth = 4, 853 }; 854 855 static struct qcom_icc_node qhs_ipa = { 856 .name = "qhs_ipa", 857 .channels = 1, 858 .buswidth = 4, 859 }; 860 861 static struct qcom_icc_node qhs_mnoc_cfg = { 862 .name = "qhs_mnoc_cfg", 863 .channels = 1, 864 .buswidth = 4, 865 .num_links = 1, 866 .link_nodes = { &qhm_mnoc_cfg }, 867 }; 868 869 static struct qcom_icc_node qhs_mss_cfg = { 870 .name = "qhs_mss_cfg", 871 .channels = 1, 872 .buswidth = 4, 873 }; 874 875 static struct qcom_icc_node qhs_npu_cfg = { 876 .name = "qhs_npu_cfg", 877 .channels = 1, 878 .buswidth = 4, 879 .num_links = 1, 880 .link_nodes = { &qhm_npu_cfg }, 881 }; 882 883 static struct qcom_icc_node qhs_npu_dma_throttle_cfg = { 884 .name = "qhs_npu_dma_throttle_cfg", 885 .channels = 1, 886 .buswidth = 4, 887 }; 888 889 static struct qcom_icc_node qhs_npu_dsp_throttle_cfg = { 890 .name = "qhs_npu_dsp_throttle_cfg", 891 .channels = 1, 892 .buswidth = 4, 893 }; 894 895 static struct qcom_icc_node qhs_pdm = { 896 .name = "qhs_pdm", 897 .channels = 1, 898 .buswidth = 4, 899 }; 900 901 static struct qcom_icc_node qhs_pimem_cfg = { 902 .name = "qhs_pimem_cfg", 903 .channels = 1, 904 .buswidth = 4, 905 }; 906 907 static struct qcom_icc_node qhs_prng = { 908 .name = "qhs_prng", 909 .channels = 1, 910 .buswidth = 4, 911 }; 912 913 static struct qcom_icc_node qhs_qdss_cfg = { 914 .name = "qhs_qdss_cfg", 915 .channels = 1, 916 .buswidth = 4, 917 }; 918 919 static struct qcom_icc_node qhs_qm_cfg = { 920 .name = "qhs_qm_cfg", 921 .channels = 1, 922 .buswidth = 4, 923 }; 924 925 static struct qcom_icc_node qhs_qm_mpu_cfg = { 926 .name = "qhs_qm_mpu_cfg", 927 .channels = 1, 928 .buswidth = 4, 929 }; 930 931 static struct qcom_icc_node qhs_qspi = { 932 .name = "qhs_qspi", 933 .channels = 1, 934 .buswidth = 4, 935 }; 936 937 static struct qcom_icc_node qhs_qup0 = { 938 .name = "qhs_qup0", 939 .channels = 1, 940 .buswidth = 4, 941 }; 942 943 static struct qcom_icc_node qhs_qup1 = { 944 .name = "qhs_qup1", 945 .channels = 1, 946 .buswidth = 4, 947 }; 948 949 static struct qcom_icc_node qhs_sdc2 = { 950 .name = "qhs_sdc2", 951 .channels = 1, 952 .buswidth = 4, 953 }; 954 955 static struct qcom_icc_node qhs_security = { 956 .name = "qhs_security", 957 .channels = 1, 958 .buswidth = 4, 959 }; 960 961 static struct qcom_icc_node qhs_snoc_cfg = { 962 .name = "qhs_snoc_cfg", 963 .channels = 1, 964 .buswidth = 4, 965 .num_links = 1, 966 .link_nodes = { &qhm_snoc_cfg }, 967 }; 968 969 static struct qcom_icc_node qhs_tcsr = { 970 .name = "qhs_tcsr", 971 .channels = 1, 972 .buswidth = 4, 973 }; 974 975 static struct qcom_icc_node qhs_tlmm_1 = { 976 .name = "qhs_tlmm_1", 977 .channels = 1, 978 .buswidth = 4, 979 }; 980 981 static struct qcom_icc_node qhs_tlmm_2 = { 982 .name = "qhs_tlmm_2", 983 .channels = 1, 984 .buswidth = 4, 985 }; 986 987 static struct qcom_icc_node qhs_tlmm_3 = { 988 .name = "qhs_tlmm_3", 989 .channels = 1, 990 .buswidth = 4, 991 }; 992 993 static struct qcom_icc_node qhs_ufs_mem_cfg = { 994 .name = "qhs_ufs_mem_cfg", 995 .channels = 1, 996 .buswidth = 4, 997 }; 998 999 static struct qcom_icc_node qhs_usb3 = { 1000 .name = "qhs_usb3", 1001 .channels = 1, 1002 .buswidth = 4, 1003 }; 1004 1005 static struct qcom_icc_node qhs_venus_cfg = { 1006 .name = "qhs_venus_cfg", 1007 .channels = 1, 1008 .buswidth = 4, 1009 }; 1010 1011 static struct qcom_icc_node qhs_venus_throttle_cfg = { 1012 .name = "qhs_venus_throttle_cfg", 1013 .channels = 1, 1014 .buswidth = 4, 1015 }; 1016 1017 static struct qcom_icc_node qhs_vsense_ctrl_cfg = { 1018 .name = "qhs_vsense_ctrl_cfg", 1019 .channels = 1, 1020 .buswidth = 4, 1021 }; 1022 1023 static struct qcom_icc_node srvc_cnoc = { 1024 .name = "srvc_cnoc", 1025 .channels = 1, 1026 .buswidth = 4, 1027 }; 1028 1029 static struct qcom_icc_node qhs_gemnoc = { 1030 .name = "qhs_gemnoc", 1031 .channels = 1, 1032 .buswidth = 4, 1033 .num_links = 1, 1034 .link_nodes = { &qhm_gemnoc_cfg }, 1035 }; 1036 1037 static struct qcom_icc_node qhs_llcc = { 1038 .name = "qhs_llcc", 1039 .channels = 1, 1040 .buswidth = 4, 1041 }; 1042 1043 static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = { 1044 .name = "qhs_mdsp_ms_mpu_cfg", 1045 .channels = 1, 1046 .buswidth = 4, 1047 }; 1048 1049 static struct qcom_icc_node qns_gem_noc_snoc = { 1050 .name = "qns_gem_noc_snoc", 1051 .channels = 1, 1052 .buswidth = 8, 1053 .num_links = 1, 1054 .link_nodes = { &qnm_gemnoc }, 1055 }; 1056 1057 static struct qcom_icc_node qns_llcc = { 1058 .name = "qns_llcc", 1059 .channels = 1, 1060 .buswidth = 16, 1061 .num_links = 1, 1062 .link_nodes = { &llcc_mc }, 1063 }; 1064 1065 static struct qcom_icc_node srvc_gemnoc = { 1066 .name = "srvc_gemnoc", 1067 .channels = 1, 1068 .buswidth = 4, 1069 }; 1070 1071 static struct qcom_icc_node ebi = { 1072 .name = "ebi", 1073 .channels = 2, 1074 .buswidth = 4, 1075 }; 1076 1077 static struct qcom_icc_node qns_mem_noc_hf = { 1078 .name = "qns_mem_noc_hf", 1079 .channels = 1, 1080 .buswidth = 32, 1081 .num_links = 1, 1082 .link_nodes = { &qnm_mnoc_hf }, 1083 }; 1084 1085 static struct qcom_icc_node qns_mem_noc_sf = { 1086 .name = "qns_mem_noc_sf", 1087 .channels = 1, 1088 .buswidth = 32, 1089 .num_links = 1, 1090 .link_nodes = { &qnm_mnoc_sf }, 1091 }; 1092 1093 static struct qcom_icc_node srvc_mnoc = { 1094 .name = "srvc_mnoc", 1095 .channels = 1, 1096 .buswidth = 4, 1097 }; 1098 1099 static struct qcom_icc_node qhs_cal_dp0 = { 1100 .name = "qhs_cal_dp0", 1101 .channels = 1, 1102 .buswidth = 4, 1103 }; 1104 1105 static struct qcom_icc_node qhs_cp = { 1106 .name = "qhs_cp", 1107 .channels = 1, 1108 .buswidth = 4, 1109 }; 1110 1111 static struct qcom_icc_node qhs_dma_bwmon = { 1112 .name = "qhs_dma_bwmon", 1113 .channels = 1, 1114 .buswidth = 4, 1115 }; 1116 1117 static struct qcom_icc_node qhs_dpm = { 1118 .name = "qhs_dpm", 1119 .channels = 1, 1120 .buswidth = 4, 1121 }; 1122 1123 static struct qcom_icc_node qhs_isense = { 1124 .name = "qhs_isense", 1125 .channels = 1, 1126 .buswidth = 4, 1127 }; 1128 1129 static struct qcom_icc_node qhs_llm = { 1130 .name = "qhs_llm", 1131 .channels = 1, 1132 .buswidth = 4, 1133 }; 1134 1135 static struct qcom_icc_node qhs_tcm = { 1136 .name = "qhs_tcm", 1137 .channels = 1, 1138 .buswidth = 4, 1139 }; 1140 1141 static struct qcom_icc_node qns_npu_sys = { 1142 .name = "qns_npu_sys", 1143 .channels = 2, 1144 .buswidth = 32, 1145 }; 1146 1147 static struct qcom_icc_node srvc_noc = { 1148 .name = "srvc_noc", 1149 .channels = 1, 1150 .buswidth = 4, 1151 }; 1152 1153 static struct qcom_icc_node qup_core_slave_1 = { 1154 .name = "qup_core_slave_1", 1155 .channels = 1, 1156 .buswidth = 4, 1157 }; 1158 1159 static struct qcom_icc_node qup_core_slave_2 = { 1160 .name = "qup_core_slave_2", 1161 .channels = 1, 1162 .buswidth = 4, 1163 }; 1164 1165 static struct qcom_icc_node qhs_apss = { 1166 .name = "qhs_apss", 1167 .channels = 1, 1168 .buswidth = 8, 1169 }; 1170 1171 static struct qcom_icc_node qns_cnoc = { 1172 .name = "qns_cnoc", 1173 .channels = 1, 1174 .buswidth = 8, 1175 .num_links = 1, 1176 .link_nodes = { &qnm_snoc }, 1177 }; 1178 1179 static struct qcom_icc_node qns_gemnoc_gc = { 1180 .name = "qns_gemnoc_gc", 1181 .channels = 1, 1182 .buswidth = 8, 1183 .num_links = 1, 1184 .link_nodes = { &qnm_snoc_gc }, 1185 }; 1186 1187 static struct qcom_icc_node qns_gemnoc_sf = { 1188 .name = "qns_gemnoc_sf", 1189 .channels = 1, 1190 .buswidth = 16, 1191 .num_links = 1, 1192 .link_nodes = { &qnm_snoc_sf }, 1193 }; 1194 1195 static struct qcom_icc_node qxs_imem = { 1196 .name = "qxs_imem", 1197 .channels = 1, 1198 .buswidth = 8, 1199 }; 1200 1201 static struct qcom_icc_node qxs_pimem = { 1202 .name = "qxs_pimem", 1203 .channels = 1, 1204 .buswidth = 8, 1205 }; 1206 1207 static struct qcom_icc_node srvc_snoc = { 1208 .name = "srvc_snoc", 1209 .channels = 1, 1210 .buswidth = 4, 1211 }; 1212 1213 static struct qcom_icc_node xs_qdss_stm = { 1214 .name = "xs_qdss_stm", 1215 .channels = 1, 1216 .buswidth = 4, 1217 }; 1218 1219 static struct qcom_icc_node xs_sys_tcu_cfg = { 1220 .name = "xs_sys_tcu_cfg", 1221 .channels = 1, 1222 .buswidth = 8, 1223 }; 1224 1225 static struct qcom_icc_bcm bcm_acv = { 1226 .name = "ACV", 1227 .enable_mask = BIT(3), 1228 .keepalive = false, 1229 .num_nodes = 1, 1230 .nodes = { &ebi }, 1231 }; 1232 1233 static struct qcom_icc_bcm bcm_mc0 = { 1234 .name = "MC0", 1235 .keepalive = true, 1236 .num_nodes = 1, 1237 .nodes = { &ebi }, 1238 }; 1239 1240 static struct qcom_icc_bcm bcm_sh0 = { 1241 .name = "SH0", 1242 .keepalive = true, 1243 .num_nodes = 1, 1244 .nodes = { &qns_llcc }, 1245 }; 1246 1247 static struct qcom_icc_bcm bcm_mm0 = { 1248 .name = "MM0", 1249 .keepalive = false, 1250 .num_nodes = 1, 1251 .nodes = { &qns_mem_noc_hf }, 1252 }; 1253 1254 static struct qcom_icc_bcm bcm_ce0 = { 1255 .name = "CE0", 1256 .keepalive = false, 1257 .num_nodes = 1, 1258 .nodes = { &qxm_crypto }, 1259 }; 1260 1261 static struct qcom_icc_bcm bcm_cn0 = { 1262 .name = "CN0", 1263 .keepalive = true, 1264 .num_nodes = 48, 1265 .nodes = { &qnm_snoc, 1266 &xm_qdss_dap, 1267 &qhs_a1_noc_cfg, 1268 &qhs_a2_noc_cfg, 1269 &qhs_ahb2phy0, 1270 &qhs_aop, 1271 &qhs_aoss, 1272 &qhs_boot_rom, 1273 &qhs_camera_cfg, 1274 &qhs_camera_nrt_throttle_cfg, 1275 &qhs_camera_rt_throttle_cfg, 1276 &qhs_clk_ctl, 1277 &qhs_cpr_cx, 1278 &qhs_cpr_mx, 1279 &qhs_crypto0_cfg, 1280 &qhs_dcc_cfg, 1281 &qhs_ddrss_cfg, 1282 &qhs_display_cfg, 1283 &qhs_display_rt_throttle_cfg, 1284 &qhs_display_throttle_cfg, 1285 &qhs_glm, 1286 &qhs_gpuss_cfg, 1287 &qhs_imem_cfg, 1288 &qhs_ipa, 1289 &qhs_mnoc_cfg, 1290 &qhs_mss_cfg, 1291 &qhs_npu_cfg, 1292 &qhs_npu_dma_throttle_cfg, 1293 &qhs_npu_dsp_throttle_cfg, 1294 &qhs_pimem_cfg, 1295 &qhs_prng, 1296 &qhs_qdss_cfg, 1297 &qhs_qm_cfg, 1298 &qhs_qm_mpu_cfg, 1299 &qhs_qup0, 1300 &qhs_qup1, 1301 &qhs_security, 1302 &qhs_snoc_cfg, 1303 &qhs_tcsr, 1304 &qhs_tlmm_1, 1305 &qhs_tlmm_2, 1306 &qhs_tlmm_3, 1307 &qhs_ufs_mem_cfg, 1308 &qhs_usb3, 1309 &qhs_venus_cfg, 1310 &qhs_venus_throttle_cfg, 1311 &qhs_vsense_ctrl_cfg, 1312 &srvc_cnoc 1313 }, 1314 }; 1315 1316 static struct qcom_icc_bcm bcm_mm1 = { 1317 .name = "MM1", 1318 .keepalive = false, 1319 .num_nodes = 8, 1320 .nodes = { &qxm_camnoc_hf0_uncomp, 1321 &qxm_camnoc_hf1_uncomp, 1322 &qxm_camnoc_sf_uncomp, 1323 &qhm_mnoc_cfg, 1324 &qxm_mdp0, 1325 &qxm_rot, 1326 &qxm_venus0, 1327 &qxm_venus_arm9 1328 }, 1329 }; 1330 1331 static struct qcom_icc_bcm bcm_sh2 = { 1332 .name = "SH2", 1333 .keepalive = false, 1334 .num_nodes = 1, 1335 .nodes = { &acm_sys_tcu }, 1336 }; 1337 1338 static struct qcom_icc_bcm bcm_mm2 = { 1339 .name = "MM2", 1340 .keepalive = false, 1341 .num_nodes = 1, 1342 .nodes = { &qns_mem_noc_sf }, 1343 }; 1344 1345 static struct qcom_icc_bcm bcm_qup0 = { 1346 .name = "QUP0", 1347 .keepalive = false, 1348 .num_nodes = 2, 1349 .nodes = { &qup_core_master_1, &qup_core_master_2 }, 1350 }; 1351 1352 static struct qcom_icc_bcm bcm_sh3 = { 1353 .name = "SH3", 1354 .keepalive = false, 1355 .num_nodes = 1, 1356 .nodes = { &qnm_cmpnoc }, 1357 }; 1358 1359 static struct qcom_icc_bcm bcm_sh4 = { 1360 .name = "SH4", 1361 .keepalive = false, 1362 .num_nodes = 1, 1363 .nodes = { &acm_apps0 }, 1364 }; 1365 1366 static struct qcom_icc_bcm bcm_sn0 = { 1367 .name = "SN0", 1368 .keepalive = true, 1369 .num_nodes = 1, 1370 .nodes = { &qns_gemnoc_sf }, 1371 }; 1372 1373 static struct qcom_icc_bcm bcm_co0 = { 1374 .name = "CO0", 1375 .keepalive = false, 1376 .num_nodes = 1, 1377 .nodes = { &qns_cdsp_gemnoc }, 1378 }; 1379 1380 static struct qcom_icc_bcm bcm_sn1 = { 1381 .name = "SN1", 1382 .keepalive = false, 1383 .num_nodes = 1, 1384 .nodes = { &qxs_imem }, 1385 }; 1386 1387 static struct qcom_icc_bcm bcm_cn1 = { 1388 .name = "CN1", 1389 .keepalive = false, 1390 .num_nodes = 8, 1391 .nodes = { &qhm_qspi, 1392 &xm_sdc2, 1393 &xm_emmc, 1394 &qhs_ahb2phy2, 1395 &qhs_emmc_cfg, 1396 &qhs_pdm, 1397 &qhs_qspi, 1398 &qhs_sdc2 1399 }, 1400 }; 1401 1402 static struct qcom_icc_bcm bcm_sn2 = { 1403 .name = "SN2", 1404 .keepalive = false, 1405 .num_nodes = 2, 1406 .nodes = { &qxm_pimem, &qns_gemnoc_gc }, 1407 }; 1408 1409 static struct qcom_icc_bcm bcm_co2 = { 1410 .name = "CO2", 1411 .keepalive = false, 1412 .num_nodes = 1, 1413 .nodes = { &qnm_npu }, 1414 }; 1415 1416 static struct qcom_icc_bcm bcm_sn3 = { 1417 .name = "SN3", 1418 .keepalive = false, 1419 .num_nodes = 1, 1420 .nodes = { &qxs_pimem }, 1421 }; 1422 1423 static struct qcom_icc_bcm bcm_co3 = { 1424 .name = "CO3", 1425 .keepalive = false, 1426 .num_nodes = 1, 1427 .nodes = { &qxm_npu_dsp }, 1428 }; 1429 1430 static struct qcom_icc_bcm bcm_sn4 = { 1431 .name = "SN4", 1432 .keepalive = false, 1433 .num_nodes = 1, 1434 .nodes = { &xs_qdss_stm }, 1435 }; 1436 1437 static struct qcom_icc_bcm bcm_sn7 = { 1438 .name = "SN7", 1439 .keepalive = false, 1440 .num_nodes = 1, 1441 .nodes = { &qnm_aggre1_noc }, 1442 }; 1443 1444 static struct qcom_icc_bcm bcm_sn9 = { 1445 .name = "SN9", 1446 .keepalive = false, 1447 .num_nodes = 1, 1448 .nodes = { &qnm_aggre2_noc }, 1449 }; 1450 1451 static struct qcom_icc_bcm bcm_sn12 = { 1452 .name = "SN12", 1453 .keepalive = false, 1454 .num_nodes = 1, 1455 .nodes = { &qnm_gemnoc }, 1456 }; 1457 1458 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { 1459 &bcm_cn1, 1460 }; 1461 1462 static struct qcom_icc_node * const aggre1_noc_nodes[] = { 1463 [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg, 1464 [MASTER_QSPI] = &qhm_qspi, 1465 [MASTER_QUP_0] = &qhm_qup_0, 1466 [MASTER_SDCC_2] = &xm_sdc2, 1467 [MASTER_EMMC] = &xm_emmc, 1468 [MASTER_UFS_MEM] = &xm_ufs_mem, 1469 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, 1470 [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, 1471 }; 1472 1473 static const struct qcom_icc_desc sc7180_aggre1_noc = { 1474 .nodes = aggre1_noc_nodes, 1475 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), 1476 .bcms = aggre1_noc_bcms, 1477 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), 1478 }; 1479 1480 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { 1481 &bcm_ce0, 1482 }; 1483 1484 static struct qcom_icc_node * const aggre2_noc_nodes[] = { 1485 [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg, 1486 [MASTER_QDSS_BAM] = &qhm_qdss_bam, 1487 [MASTER_QUP_1] = &qhm_qup_1, 1488 [MASTER_USB3] = &qhm_usb3, 1489 [MASTER_CRYPTO] = &qxm_crypto, 1490 [MASTER_IPA] = &qxm_ipa, 1491 [MASTER_QDSS_ETR] = &xm_qdss_etr, 1492 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, 1493 [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, 1494 }; 1495 1496 static const struct qcom_icc_desc sc7180_aggre2_noc = { 1497 .nodes = aggre2_noc_nodes, 1498 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), 1499 .bcms = aggre2_noc_bcms, 1500 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), 1501 }; 1502 1503 static struct qcom_icc_bcm * const camnoc_virt_bcms[] = { 1504 &bcm_mm1, 1505 }; 1506 1507 static struct qcom_icc_node * const camnoc_virt_nodes[] = { 1508 [MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp, 1509 [MASTER_CAMNOC_HF1_UNCOMP] = &qxm_camnoc_hf1_uncomp, 1510 [MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp, 1511 [SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp, 1512 }; 1513 1514 static const struct qcom_icc_desc sc7180_camnoc_virt = { 1515 .nodes = camnoc_virt_nodes, 1516 .num_nodes = ARRAY_SIZE(camnoc_virt_nodes), 1517 .bcms = camnoc_virt_bcms, 1518 .num_bcms = ARRAY_SIZE(camnoc_virt_bcms), 1519 }; 1520 1521 static struct qcom_icc_bcm * const compute_noc_bcms[] = { 1522 &bcm_co0, 1523 &bcm_co2, 1524 &bcm_co3, 1525 }; 1526 1527 static struct qcom_icc_node * const compute_noc_nodes[] = { 1528 [MASTER_NPU] = &qnm_npu, 1529 [MASTER_NPU_PROC] = &qxm_npu_dsp, 1530 [SLAVE_CDSP_GEM_NOC] = &qns_cdsp_gemnoc, 1531 }; 1532 1533 static const struct qcom_icc_desc sc7180_compute_noc = { 1534 .nodes = compute_noc_nodes, 1535 .num_nodes = ARRAY_SIZE(compute_noc_nodes), 1536 .bcms = compute_noc_bcms, 1537 .num_bcms = ARRAY_SIZE(compute_noc_bcms), 1538 }; 1539 1540 static struct qcom_icc_bcm * const config_noc_bcms[] = { 1541 &bcm_cn0, 1542 &bcm_cn1, 1543 }; 1544 1545 static struct qcom_icc_node * const config_noc_nodes[] = { 1546 [MASTER_SNOC_CNOC] = &qnm_snoc, 1547 [MASTER_QDSS_DAP] = &xm_qdss_dap, 1548 [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg, 1549 [SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg, 1550 [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0, 1551 [SLAVE_AHB2PHY_CENTER] = &qhs_ahb2phy2, 1552 [SLAVE_AOP] = &qhs_aop, 1553 [SLAVE_AOSS] = &qhs_aoss, 1554 [SLAVE_BOOT_ROM] = &qhs_boot_rom, 1555 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, 1556 [SLAVE_CAMERA_NRT_THROTTLE_CFG] = &qhs_camera_nrt_throttle_cfg, 1557 [SLAVE_CAMERA_RT_THROTTLE_CFG] = &qhs_camera_rt_throttle_cfg, 1558 [SLAVE_CLK_CTL] = &qhs_clk_ctl, 1559 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, 1560 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx, 1561 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, 1562 [SLAVE_DCC_CFG] = &qhs_dcc_cfg, 1563 [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg, 1564 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, 1565 [SLAVE_DISPLAY_RT_THROTTLE_CFG] = &qhs_display_rt_throttle_cfg, 1566 [SLAVE_DISPLAY_THROTTLE_CFG] = &qhs_display_throttle_cfg, 1567 [SLAVE_EMMC_CFG] = &qhs_emmc_cfg, 1568 [SLAVE_GLM] = &qhs_glm, 1569 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg, 1570 [SLAVE_IMEM_CFG] = &qhs_imem_cfg, 1571 [SLAVE_IPA_CFG] = &qhs_ipa, 1572 [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg, 1573 [SLAVE_CNOC_MSS] = &qhs_mss_cfg, 1574 [SLAVE_NPU_CFG] = &qhs_npu_cfg, 1575 [SLAVE_NPU_DMA_BWMON_CFG] = &qhs_npu_dma_throttle_cfg, 1576 [SLAVE_NPU_PROC_BWMON_CFG] = &qhs_npu_dsp_throttle_cfg, 1577 [SLAVE_PDM] = &qhs_pdm, 1578 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, 1579 [SLAVE_PRNG] = &qhs_prng, 1580 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, 1581 [SLAVE_QM_CFG] = &qhs_qm_cfg, 1582 [SLAVE_QM_MPU_CFG] = &qhs_qm_mpu_cfg, 1583 [SLAVE_QSPI_0] = &qhs_qspi, 1584 [SLAVE_QUP_0] = &qhs_qup0, 1585 [SLAVE_QUP_1] = &qhs_qup1, 1586 [SLAVE_SDCC_2] = &qhs_sdc2, 1587 [SLAVE_SECURITY] = &qhs_security, 1588 [SLAVE_SNOC_CFG] = &qhs_snoc_cfg, 1589 [SLAVE_TCSR] = &qhs_tcsr, 1590 [SLAVE_TLMM_WEST] = &qhs_tlmm_1, 1591 [SLAVE_TLMM_NORTH] = &qhs_tlmm_2, 1592 [SLAVE_TLMM_SOUTH] = &qhs_tlmm_3, 1593 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, 1594 [SLAVE_USB3] = &qhs_usb3, 1595 [SLAVE_VENUS_CFG] = &qhs_venus_cfg, 1596 [SLAVE_VENUS_THROTTLE_CFG] = &qhs_venus_throttle_cfg, 1597 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, 1598 [SLAVE_SERVICE_CNOC] = &srvc_cnoc, 1599 }; 1600 1601 static const struct qcom_icc_desc sc7180_config_noc = { 1602 .nodes = config_noc_nodes, 1603 .num_nodes = ARRAY_SIZE(config_noc_nodes), 1604 .bcms = config_noc_bcms, 1605 .num_bcms = ARRAY_SIZE(config_noc_bcms), 1606 }; 1607 1608 static struct qcom_icc_node * const dc_noc_nodes[] = { 1609 [MASTER_CNOC_DC_NOC] = &qhm_cnoc_dc_noc, 1610 [SLAVE_GEM_NOC_CFG] = &qhs_gemnoc, 1611 [SLAVE_LLCC_CFG] = &qhs_llcc, 1612 }; 1613 1614 static const struct qcom_icc_desc sc7180_dc_noc = { 1615 .nodes = dc_noc_nodes, 1616 .num_nodes = ARRAY_SIZE(dc_noc_nodes), 1617 }; 1618 1619 static struct qcom_icc_bcm * const gem_noc_bcms[] = { 1620 &bcm_sh0, 1621 &bcm_sh2, 1622 &bcm_sh3, 1623 &bcm_sh4, 1624 }; 1625 1626 static struct qcom_icc_node * const gem_noc_nodes[] = { 1627 [MASTER_APPSS_PROC] = &acm_apps0, 1628 [MASTER_SYS_TCU] = &acm_sys_tcu, 1629 [MASTER_GEM_NOC_CFG] = &qhm_gemnoc_cfg, 1630 [MASTER_COMPUTE_NOC] = &qnm_cmpnoc, 1631 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, 1632 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, 1633 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, 1634 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, 1635 [MASTER_GFX3D] = &qxm_gpu, 1636 [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg, 1637 [SLAVE_GEM_NOC_SNOC] = &qns_gem_noc_snoc, 1638 [SLAVE_LLCC] = &qns_llcc, 1639 [SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc, 1640 }; 1641 1642 static const struct qcom_icc_desc sc7180_gem_noc = { 1643 .nodes = gem_noc_nodes, 1644 .num_nodes = ARRAY_SIZE(gem_noc_nodes), 1645 .bcms = gem_noc_bcms, 1646 .num_bcms = ARRAY_SIZE(gem_noc_bcms), 1647 }; 1648 1649 static struct qcom_icc_bcm * const mc_virt_bcms[] = { 1650 &bcm_acv, 1651 &bcm_mc0, 1652 }; 1653 1654 static struct qcom_icc_node * const mc_virt_nodes[] = { 1655 [MASTER_LLCC] = &llcc_mc, 1656 [SLAVE_EBI1] = &ebi, 1657 }; 1658 1659 static const struct qcom_icc_desc sc7180_mc_virt = { 1660 .nodes = mc_virt_nodes, 1661 .num_nodes = ARRAY_SIZE(mc_virt_nodes), 1662 .bcms = mc_virt_bcms, 1663 .num_bcms = ARRAY_SIZE(mc_virt_bcms), 1664 }; 1665 1666 static struct qcom_icc_bcm * const mmss_noc_bcms[] = { 1667 &bcm_mm0, 1668 &bcm_mm1, 1669 &bcm_mm2, 1670 }; 1671 1672 static struct qcom_icc_node * const mmss_noc_nodes[] = { 1673 [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg, 1674 [MASTER_CAMNOC_HF0] = &qxm_camnoc_hf0, 1675 [MASTER_CAMNOC_HF1] = &qxm_camnoc_hf1, 1676 [MASTER_CAMNOC_SF] = &qxm_camnoc_sf, 1677 [MASTER_MDP0] = &qxm_mdp0, 1678 [MASTER_ROTATOR] = &qxm_rot, 1679 [MASTER_VIDEO_P0] = &qxm_venus0, 1680 [MASTER_VIDEO_PROC] = &qxm_venus_arm9, 1681 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, 1682 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf, 1683 [SLAVE_SERVICE_MNOC] = &srvc_mnoc, 1684 }; 1685 1686 static const struct qcom_icc_desc sc7180_mmss_noc = { 1687 .nodes = mmss_noc_nodes, 1688 .num_nodes = ARRAY_SIZE(mmss_noc_nodes), 1689 .bcms = mmss_noc_bcms, 1690 .num_bcms = ARRAY_SIZE(mmss_noc_bcms), 1691 }; 1692 1693 static struct qcom_icc_node * const npu_noc_nodes[] = { 1694 [MASTER_NPU_SYS] = &amm_npu_sys, 1695 [MASTER_NPU_NOC_CFG] = &qhm_npu_cfg, 1696 [SLAVE_NPU_CAL_DP0] = &qhs_cal_dp0, 1697 [SLAVE_NPU_CP] = &qhs_cp, 1698 [SLAVE_NPU_INT_DMA_BWMON_CFG] = &qhs_dma_bwmon, 1699 [SLAVE_NPU_DPM] = &qhs_dpm, 1700 [SLAVE_ISENSE_CFG] = &qhs_isense, 1701 [SLAVE_NPU_LLM_CFG] = &qhs_llm, 1702 [SLAVE_NPU_TCM] = &qhs_tcm, 1703 [SLAVE_NPU_COMPUTE_NOC] = &qns_npu_sys, 1704 [SLAVE_SERVICE_NPU_NOC] = &srvc_noc, 1705 }; 1706 1707 static const struct qcom_icc_desc sc7180_npu_noc = { 1708 .nodes = npu_noc_nodes, 1709 .num_nodes = ARRAY_SIZE(npu_noc_nodes), 1710 }; 1711 1712 static struct qcom_icc_bcm * const qup_virt_bcms[] = { 1713 &bcm_qup0, 1714 }; 1715 1716 static struct qcom_icc_node * const qup_virt_nodes[] = { 1717 [MASTER_QUP_CORE_0] = &qup_core_master_1, 1718 [MASTER_QUP_CORE_1] = &qup_core_master_2, 1719 [SLAVE_QUP_CORE_0] = &qup_core_slave_1, 1720 [SLAVE_QUP_CORE_1] = &qup_core_slave_2, 1721 }; 1722 1723 static const struct qcom_icc_desc sc7180_qup_virt = { 1724 .nodes = qup_virt_nodes, 1725 .num_nodes = ARRAY_SIZE(qup_virt_nodes), 1726 .bcms = qup_virt_bcms, 1727 .num_bcms = ARRAY_SIZE(qup_virt_bcms), 1728 }; 1729 1730 static struct qcom_icc_bcm * const system_noc_bcms[] = { 1731 &bcm_sn0, 1732 &bcm_sn1, 1733 &bcm_sn2, 1734 &bcm_sn3, 1735 &bcm_sn4, 1736 &bcm_sn7, 1737 &bcm_sn9, 1738 &bcm_sn12, 1739 }; 1740 1741 static struct qcom_icc_node * const system_noc_nodes[] = { 1742 [MASTER_SNOC_CFG] = &qhm_snoc_cfg, 1743 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, 1744 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, 1745 [MASTER_GEM_NOC_SNOC] = &qnm_gemnoc, 1746 [MASTER_PIMEM] = &qxm_pimem, 1747 [SLAVE_APPSS] = &qhs_apss, 1748 [SLAVE_SNOC_CNOC] = &qns_cnoc, 1749 [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc, 1750 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, 1751 [SLAVE_IMEM] = &qxs_imem, 1752 [SLAVE_PIMEM] = &qxs_pimem, 1753 [SLAVE_SERVICE_SNOC] = &srvc_snoc, 1754 [SLAVE_QDSS_STM] = &xs_qdss_stm, 1755 [SLAVE_TCU] = &xs_sys_tcu_cfg, 1756 }; 1757 1758 static const struct qcom_icc_desc sc7180_system_noc = { 1759 .nodes = system_noc_nodes, 1760 .num_nodes = ARRAY_SIZE(system_noc_nodes), 1761 .bcms = system_noc_bcms, 1762 .num_bcms = ARRAY_SIZE(system_noc_bcms), 1763 }; 1764 1765 static const struct of_device_id qnoc_of_match[] = { 1766 { .compatible = "qcom,sc7180-aggre1-noc", 1767 .data = &sc7180_aggre1_noc}, 1768 { .compatible = "qcom,sc7180-aggre2-noc", 1769 .data = &sc7180_aggre2_noc}, 1770 { .compatible = "qcom,sc7180-camnoc-virt", 1771 .data = &sc7180_camnoc_virt}, 1772 { .compatible = "qcom,sc7180-compute-noc", 1773 .data = &sc7180_compute_noc}, 1774 { .compatible = "qcom,sc7180-config-noc", 1775 .data = &sc7180_config_noc}, 1776 { .compatible = "qcom,sc7180-dc-noc", 1777 .data = &sc7180_dc_noc}, 1778 { .compatible = "qcom,sc7180-gem-noc", 1779 .data = &sc7180_gem_noc}, 1780 { .compatible = "qcom,sc7180-mc-virt", 1781 .data = &sc7180_mc_virt}, 1782 { .compatible = "qcom,sc7180-mmss-noc", 1783 .data = &sc7180_mmss_noc}, 1784 { .compatible = "qcom,sc7180-npu-noc", 1785 .data = &sc7180_npu_noc}, 1786 { .compatible = "qcom,sc7180-qup-virt", 1787 .data = &sc7180_qup_virt}, 1788 { .compatible = "qcom,sc7180-system-noc", 1789 .data = &sc7180_system_noc}, 1790 { } 1791 }; 1792 MODULE_DEVICE_TABLE(of, qnoc_of_match); 1793 1794 static struct platform_driver qnoc_driver = { 1795 .probe = qcom_icc_rpmh_probe, 1796 .remove = qcom_icc_rpmh_remove, 1797 .driver = { 1798 .name = "qnoc-sc7180", 1799 .of_match_table = qnoc_of_match, 1800 .sync_state = icc_sync_state, 1801 }, 1802 }; 1803 module_platform_driver(qnoc_driver); 1804 1805 MODULE_DESCRIPTION("Qualcomm SC7180 NoC driver"); 1806 MODULE_LICENSE("GPL v2"); 1807