1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * SC16IS7xx tty serial driver - common code
4 *
5 * Copyright (C) 2014 GridPoint
6 * Author: Jon Ringle <jringle@gridpoint.com>
7 * Based on max310x.c, by Alexander Shiyan <shc_work@mail.ru>
8 */
9
10 #undef DEFAULT_SYMBOL_NAMESPACE
11 #define DEFAULT_SYMBOL_NAMESPACE "SERIAL_NXP_SC16IS7XX"
12
13 #include <linux/bits.h>
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/device.h>
17 #include <linux/export.h>
18 #include <linux/gpio/consumer.h>
19 #include <linux/gpio/driver.h>
20 #include <linux/idr.h>
21 #include <linux/kthread.h>
22 #include <linux/mod_devicetable.h>
23 #include <linux/module.h>
24 #include <linux/property.h>
25 #include <linux/regmap.h>
26 #include <linux/sched.h>
27 #include <linux/serial_core.h>
28 #include <linux/serial.h>
29 #include <linux/string.h>
30 #include <linux/tty.h>
31 #include <linux/tty_flip.h>
32 #include <linux/uaccess.h>
33 #include <linux/units.h>
34
35 #include "sc16is7xx.h"
36
37 #define SC16IS7XX_MAX_DEVS 8
38
39 /* SC16IS7XX register definitions */
40 #define SC16IS7XX_RHR_REG (0x00) /* RX FIFO */
41 #define SC16IS7XX_THR_REG (0x00) /* TX FIFO */
42 #define SC16IS7XX_IER_REG (0x01) /* Interrupt enable */
43 #define SC16IS7XX_IIR_REG (0x02) /* Interrupt Identification */
44 #define SC16IS7XX_FCR_REG (0x02) /* FIFO control */
45 #define SC16IS7XX_LCR_REG (0x03) /* Line Control */
46 #define SC16IS7XX_MCR_REG (0x04) /* Modem Control */
47 #define SC16IS7XX_LSR_REG (0x05) /* Line Status */
48 #define SC16IS7XX_MSR_REG (0x06) /* Modem Status */
49 #define SC16IS7XX_SPR_REG (0x07) /* Scratch Pad */
50 #define SC16IS7XX_TXLVL_REG (0x08) /* TX FIFO level */
51 #define SC16IS7XX_RXLVL_REG (0x09) /* RX FIFO level */
52 #define SC16IS7XX_IODIR_REG (0x0a) /* I/O Direction
53 * - only on 75x/76x
54 */
55 #define SC16IS7XX_IOSTATE_REG (0x0b) /* I/O State
56 * - only on 75x/76x
57 */
58 #define SC16IS7XX_IOINTENA_REG (0x0c) /* I/O Interrupt Enable
59 * - only on 75x/76x
60 */
61 #define SC16IS7XX_IOCONTROL_REG (0x0e) /* I/O Control
62 * - only on 75x/76x
63 */
64 #define SC16IS7XX_EFCR_REG (0x0f) /* Extra Features Control */
65
66 /* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */
67 #define SC16IS7XX_TCR_REG (0x06) /* Transmit control */
68 #define SC16IS7XX_TLR_REG (0x07) /* Trigger level */
69
70 /* Special Register set: Only if ((LCR[7] == 1) && (LCR != 0xBF)) */
71 #define SC16IS7XX_DLL_REG (0x00) /* Divisor Latch Low */
72 #define SC16IS7XX_DLH_REG (0x01) /* Divisor Latch High */
73
74 /* Enhanced Register set: Only if (LCR == 0xBF) */
75 #define SC16IS7XX_EFR_REG (0x02) /* Enhanced Features */
76 #define SC16IS7XX_XON1_REG (0x04) /* Xon1 word */
77 #define SC16IS7XX_XON2_REG (0x05) /* Xon2 word */
78 #define SC16IS7XX_XOFF1_REG (0x06) /* Xoff1 word */
79 #define SC16IS7XX_XOFF2_REG (0x07) /* Xoff2 word */
80
81 /* IER register bits */
82 #define SC16IS7XX_IER_RDI_BIT BIT(0) /* Enable RX data interrupt */
83 #define SC16IS7XX_IER_THRI_BIT BIT(1) /* Enable TX holding register
84 * interrupt */
85 #define SC16IS7XX_IER_RLSI_BIT BIT(2) /* Enable RX line status
86 * interrupt */
87 #define SC16IS7XX_IER_MSI_BIT BIT(3) /* Enable Modem status
88 * interrupt */
89
90 /* IER register bits - write only if (EFR[4] == 1) */
91 #define SC16IS7XX_IER_SLEEP_BIT BIT(4) /* Enable Sleep mode */
92 #define SC16IS7XX_IER_XOFFI_BIT BIT(5) /* Enable Xoff interrupt */
93 #define SC16IS7XX_IER_RTSI_BIT BIT(6) /* Enable nRTS interrupt */
94 #define SC16IS7XX_IER_CTSI_BIT BIT(7) /* Enable nCTS interrupt */
95
96 /* FCR register bits */
97 #define SC16IS7XX_FCR_FIFO_BIT BIT(0) /* Enable FIFO */
98 #define SC16IS7XX_FCR_RXRESET_BIT BIT(1) /* Reset RX FIFO */
99 #define SC16IS7XX_FCR_TXRESET_BIT BIT(2) /* Reset TX FIFO */
100 #define SC16IS7XX_FCR_RXLVLL_BIT BIT(6) /* RX Trigger level LSB */
101 #define SC16IS7XX_FCR_RXLVLH_BIT BIT(7) /* RX Trigger level MSB */
102
103 /* FCR register bits - write only if (EFR[4] == 1) */
104 #define SC16IS7XX_FCR_TXLVLL_BIT BIT(4) /* TX Trigger level LSB */
105 #define SC16IS7XX_FCR_TXLVLH_BIT BIT(5) /* TX Trigger level MSB */
106
107 /* IIR register bits */
108 #define SC16IS7XX_IIR_NO_INT_BIT 0x01 /* No interrupts pending */
109 #define SC16IS7XX_IIR_ID_MASK GENMASK(5, 1) /* Mask for the interrupt ID */
110 #define SC16IS7XX_IIR_THRI_SRC 0x02 /* TX holding register empty */
111 #define SC16IS7XX_IIR_RDI_SRC 0x04 /* RX data interrupt */
112 #define SC16IS7XX_IIR_RLSE_SRC 0x06 /* RX line status error */
113 #define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */
114 #define SC16IS7XX_IIR_MSI_SRC 0x00 /* Modem status interrupt
115 * - only on 75x/76x
116 */
117 #define SC16IS7XX_IIR_INPIN_SRC 0x30 /* Input pin change of state
118 * - only on 75x/76x
119 */
120 #define SC16IS7XX_IIR_XOFFI_SRC 0x10 /* Received Xoff */
121 #define SC16IS7XX_IIR_CTSRTS_SRC 0x20 /* nCTS,nRTS change of state
122 * from active (LOW)
123 * to inactive (HIGH)
124 */
125 /* LCR register bits */
126 #define SC16IS7XX_LCR_LENGTH0_BIT BIT(0) /* Word length bit 0 */
127 #define SC16IS7XX_LCR_LENGTH1_BIT BIT(1) /* Word length bit 1
128 *
129 * Word length bits table:
130 * 00 -> 5 bit words
131 * 01 -> 6 bit words
132 * 10 -> 7 bit words
133 * 11 -> 8 bit words
134 */
135 #define SC16IS7XX_LCR_STOPLEN_BIT BIT(2) /* STOP length bit
136 *
137 * STOP length bit table:
138 * 0 -> 1 stop bit
139 * 1 -> 1-1.5 stop bits if
140 * word length is 5,
141 * 2 stop bits otherwise
142 */
143 #define SC16IS7XX_LCR_PARITY_BIT BIT(3) /* Parity bit enable */
144 #define SC16IS7XX_LCR_EVENPARITY_BIT BIT(4) /* Even parity bit enable */
145 #define SC16IS7XX_LCR_FORCEPARITY_BIT BIT(5) /* 9-bit multidrop parity */
146 #define SC16IS7XX_LCR_TXBREAK_BIT BIT(6) /* TX break enable */
147 #define SC16IS7XX_LCR_DLAB_BIT BIT(7) /* Divisor Latch enable */
148 #define SC16IS7XX_LCR_WORD_LEN_5 (0x00)
149 #define SC16IS7XX_LCR_WORD_LEN_6 (0x01)
150 #define SC16IS7XX_LCR_WORD_LEN_7 (0x02)
151 #define SC16IS7XX_LCR_WORD_LEN_8 (0x03)
152 #define SC16IS7XX_LCR_CONF_MODE_A SC16IS7XX_LCR_DLAB_BIT /* Special
153 * reg set */
154 #define SC16IS7XX_LCR_CONF_MODE_B 0xBF /* Enhanced
155 * reg set */
156
157 /* MCR register bits */
158 #define SC16IS7XX_MCR_DTR_BIT BIT(0) /* DTR complement
159 * - only on 75x/76x
160 */
161 #define SC16IS7XX_MCR_RTS_BIT BIT(1) /* RTS complement */
162 #define SC16IS7XX_MCR_TCRTLR_BIT BIT(2) /* TCR/TLR register enable */
163 #define SC16IS7XX_MCR_LOOP_BIT BIT(4) /* Enable loopback test mode */
164 #define SC16IS7XX_MCR_XONANY_BIT BIT(5) /* Enable Xon Any
165 * - write enabled
166 * if (EFR[4] == 1)
167 */
168 #define SC16IS7XX_MCR_IRDA_BIT BIT(6) /* Enable IrDA mode
169 * - write enabled
170 * if (EFR[4] == 1)
171 */
172 #define SC16IS7XX_MCR_CLKSEL_BIT BIT(7) /* Divide clock by 4
173 * - write enabled
174 * if (EFR[4] == 1)
175 */
176
177 /* LSR register bits */
178 #define SC16IS7XX_LSR_DR_BIT BIT(0) /* Receiver data ready */
179 #define SC16IS7XX_LSR_OE_BIT BIT(1) /* Overrun Error */
180 #define SC16IS7XX_LSR_PE_BIT BIT(2) /* Parity Error */
181 #define SC16IS7XX_LSR_FE_BIT BIT(3) /* Frame Error */
182 #define SC16IS7XX_LSR_BI_BIT BIT(4) /* Break Interrupt */
183 #define SC16IS7XX_LSR_BRK_ERROR_MASK \
184 (SC16IS7XX_LSR_OE_BIT | \
185 SC16IS7XX_LSR_PE_BIT | \
186 SC16IS7XX_LSR_FE_BIT | \
187 SC16IS7XX_LSR_BI_BIT)
188
189 #define SC16IS7XX_LSR_THRE_BIT BIT(5) /* TX holding register empty */
190 #define SC16IS7XX_LSR_TEMT_BIT BIT(6) /* Transmitter empty */
191 #define SC16IS7XX_LSR_FIFOE_BIT BIT(7) /* Fifo Error */
192
193 /* MSR register bits */
194 #define SC16IS7XX_MSR_DCTS_BIT BIT(0) /* Delta CTS Clear To Send */
195 #define SC16IS7XX_MSR_DDSR_BIT BIT(1) /* Delta DSR Data Set Ready
196 * or (IO4)
197 * - only on 75x/76x
198 */
199 #define SC16IS7XX_MSR_DRI_BIT BIT(2) /* Delta RI Ring Indicator
200 * or (IO7)
201 * - only on 75x/76x
202 */
203 #define SC16IS7XX_MSR_DCD_BIT BIT(3) /* Delta CD Carrier Detect
204 * or (IO6)
205 * - only on 75x/76x
206 */
207 #define SC16IS7XX_MSR_CTS_BIT BIT(4) /* CTS */
208 #define SC16IS7XX_MSR_DSR_BIT BIT(5) /* DSR (IO4)
209 * - only on 75x/76x
210 */
211 #define SC16IS7XX_MSR_RI_BIT BIT(6) /* RI (IO7)
212 * - only on 75x/76x
213 */
214 #define SC16IS7XX_MSR_CD_BIT BIT(7) /* CD (IO6)
215 * - only on 75x/76x
216 */
217
218 /*
219 * TCR register bits
220 * TCR trigger levels are available from 0 to 60 characters with a granularity
221 * of four.
222 * The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is
223 * no built-in hardware check to make sure this condition is met. Also, the TCR
224 * must be programmed with this condition before auto RTS or software flow
225 * control is enabled to avoid spurious operation of the device.
226 */
227 #define SC16IS7XX_TCR_RX_HALT(words) ((((words) / 4) & 0x0f) << 0)
228 #define SC16IS7XX_TCR_RX_RESUME(words) ((((words) / 4) & 0x0f) << 4)
229
230 /*
231 * TLR register bits
232 * If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the
233 * FIFO Control Register (FCR) are used for the transmit and receive FIFO
234 * trigger levels. Trigger levels from 4 characters to 60 characters are
235 * available with a granularity of four.
236 *
237 * When the trigger level setting in TLR is zero, the SC16IS74x/75x/76x uses the
238 * trigger level setting defined in FCR. If TLR has non-zero trigger level value
239 * the trigger level defined in FCR is discarded. This applies to both transmit
240 * FIFO and receive FIFO trigger level setting.
241 *
242 * When TLR is used for RX trigger level control, FCR[7:6] should be left at the
243 * default state, that is, '00'.
244 */
245 #define SC16IS7XX_TLR_TX_TRIGGER(words) ((((words) / 4) & 0x0f) << 0)
246 #define SC16IS7XX_TLR_RX_TRIGGER(words) ((((words) / 4) & 0x0f) << 4)
247
248 /* IOControl register bits (Only 75x/76x) */
249 #define SC16IS7XX_IOCONTROL_LATCH_BIT BIT(0) /* Enable input latching */
250 #define SC16IS7XX_IOCONTROL_MODEM_A_BIT BIT(1) /* Enable GPIO[7:4] as modem A pins */
251 #define SC16IS7XX_IOCONTROL_MODEM_B_BIT BIT(2) /* Enable GPIO[3:0] as modem B pins */
252 #define SC16IS7XX_IOCONTROL_SRESET_BIT BIT(3) /* Software Reset */
253
254 /* EFCR register bits */
255 #define SC16IS7XX_EFCR_9BIT_MODE_BIT BIT(0) /* Enable 9-bit or Multidrop
256 * mode (RS485) */
257 #define SC16IS7XX_EFCR_RXDISABLE_BIT BIT(1) /* Disable receiver */
258 #define SC16IS7XX_EFCR_TXDISABLE_BIT BIT(2) /* Disable transmitter */
259 #define SC16IS7XX_EFCR_AUTO_RS485_BIT BIT(4) /* Auto RS485 RTS direction */
260 #define SC16IS7XX_EFCR_RTS_INVERT_BIT BIT(5) /* RTS output inversion */
261 #define SC16IS7XX_EFCR_IRDA_MODE_BIT BIT(7) /* IrDA mode
262 * 0 = rate upto 115.2 kbit/s
263 * - Only 75x/76x
264 * 1 = rate upto 1.152 Mbit/s
265 * - Only 76x
266 */
267
268 /* EFR register bits */
269 #define SC16IS7XX_EFR_AUTORTS_BIT BIT(6) /* Auto RTS flow ctrl enable */
270 #define SC16IS7XX_EFR_AUTOCTS_BIT BIT(7) /* Auto CTS flow ctrl enable */
271 #define SC16IS7XX_EFR_XOFF2_DETECT_BIT BIT(5) /* Enable Xoff2 detection */
272 #define SC16IS7XX_EFR_ENABLE_BIT BIT(4) /* Enable enhanced functions
273 * and writing to IER[7:4],
274 * FCR[5:4], MCR[7:5]
275 */
276 #define SC16IS7XX_EFR_SWFLOW3_BIT BIT(3)
277 #define SC16IS7XX_EFR_SWFLOW2_BIT BIT(2)
278 /*
279 * SWFLOW bits 3 & 2 table:
280 * 00 -> no transmitter flow
281 * control
282 * 01 -> transmitter generates
283 * XON2 and XOFF2
284 * 10 -> transmitter generates
285 * XON1 and XOFF1
286 * 11 -> transmitter generates
287 * XON1, XON2, XOFF1 and
288 * XOFF2
289 */
290 #define SC16IS7XX_EFR_SWFLOW1_BIT BIT(1)
291 #define SC16IS7XX_EFR_SWFLOW0_BIT BIT(0)
292 /*
293 * SWFLOW bits 1 & 0 table:
294 * 00 -> no received flow
295 * control
296 * 01 -> receiver compares
297 * XON2 and XOFF2
298 * 10 -> receiver compares
299 * XON1 and XOFF1
300 * 11 -> receiver compares
301 * XON1, XON2, XOFF1 and
302 * XOFF2
303 */
304 #define SC16IS7XX_EFR_FLOWCTRL_BITS (SC16IS7XX_EFR_AUTORTS_BIT | \
305 SC16IS7XX_EFR_AUTOCTS_BIT | \
306 SC16IS7XX_EFR_XOFF2_DETECT_BIT | \
307 SC16IS7XX_EFR_SWFLOW3_BIT | \
308 SC16IS7XX_EFR_SWFLOW2_BIT | \
309 SC16IS7XX_EFR_SWFLOW1_BIT | \
310 SC16IS7XX_EFR_SWFLOW0_BIT)
311
312
313 /* Misc definitions */
314 #define SC16IS7XX_FIFO_SIZE (64)
315 #define SC16IS7XX_GPIOS_PER_BANK 4
316
317 #define SC16IS7XX_POLL_PERIOD_MS 10
318 #define SC16IS7XX_RECONF_MD BIT(0)
319 #define SC16IS7XX_RECONF_IER BIT(1)
320 #define SC16IS7XX_RECONF_RS485 BIT(2)
321
322 struct sc16is7xx_one_config {
323 unsigned int flags;
324 u8 ier_mask;
325 u8 ier_val;
326 };
327
328 struct sc16is7xx_one {
329 struct uart_port port;
330 struct regmap *regmap;
331 struct mutex efr_lock; /* EFR registers access */
332 struct kthread_work tx_work;
333 struct kthread_work reg_work;
334 struct kthread_delayed_work ms_work;
335 struct sc16is7xx_one_config config;
336 unsigned char buf[SC16IS7XX_FIFO_SIZE]; /* Rx buffer. */
337 unsigned int old_mctrl;
338 u8 old_lcr; /* Value before EFR access. */
339 bool irda_mode;
340 };
341
342 struct sc16is7xx_port {
343 const struct sc16is7xx_devtype *devtype;
344 struct clk *clk;
345 #ifdef CONFIG_GPIOLIB
346 struct gpio_chip gpio;
347 unsigned long gpio_valid_mask;
348 #endif
349 u8 mctrl_mask;
350 struct kthread_worker kworker;
351 struct task_struct *kworker_task;
352 struct kthread_delayed_work poll_work;
353 bool polling;
354 struct sc16is7xx_one p[];
355 };
356
357 static DEFINE_IDA(sc16is7xx_lines);
358
359 static struct uart_driver sc16is7xx_uart = {
360 .owner = THIS_MODULE,
361 .driver_name = SC16IS7XX_NAME,
362 .dev_name = "ttySC",
363 .nr = SC16IS7XX_MAX_DEVS,
364 };
365
366 #define to_sc16is7xx_one(p,e) ((container_of((p), struct sc16is7xx_one, e)))
367
sc16is7xx_port_read(struct uart_port * port,u8 reg)368 static u8 sc16is7xx_port_read(struct uart_port *port, u8 reg)
369 {
370 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
371 unsigned int val = 0;
372
373 regmap_read(one->regmap, reg, &val);
374
375 return val;
376 }
377
sc16is7xx_port_write(struct uart_port * port,u8 reg,u8 val)378 static void sc16is7xx_port_write(struct uart_port *port, u8 reg, u8 val)
379 {
380 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
381
382 regmap_write(one->regmap, reg, val);
383 }
384
sc16is7xx_fifo_read(struct uart_port * port,u8 * rxbuf,unsigned int rxlen)385 static void sc16is7xx_fifo_read(struct uart_port *port, u8 *rxbuf, unsigned int rxlen)
386 {
387 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
388
389 regmap_noinc_read(one->regmap, SC16IS7XX_RHR_REG, rxbuf, rxlen);
390 }
391
sc16is7xx_fifo_write(struct uart_port * port,u8 * txbuf,u8 to_send)392 static void sc16is7xx_fifo_write(struct uart_port *port, u8 *txbuf, u8 to_send)
393 {
394 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
395
396 /*
397 * Don't send zero-length data, at least on SPI it confuses the chip
398 * delivering wrong TXLVL data.
399 */
400 if (unlikely(!to_send))
401 return;
402
403 regmap_noinc_write(one->regmap, SC16IS7XX_THR_REG, txbuf, to_send);
404 }
405
sc16is7xx_port_update(struct uart_port * port,u8 reg,u8 mask,u8 val)406 static void sc16is7xx_port_update(struct uart_port *port, u8 reg,
407 u8 mask, u8 val)
408 {
409 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
410
411 regmap_update_bits(one->regmap, reg, mask, val);
412 }
413
sc16is7xx_power(struct uart_port * port,int on)414 static void sc16is7xx_power(struct uart_port *port, int on)
415 {
416 sc16is7xx_port_update(port, SC16IS7XX_IER_REG,
417 SC16IS7XX_IER_SLEEP_BIT,
418 on ? 0 : SC16IS7XX_IER_SLEEP_BIT);
419 }
420
421 /*
422 * In an amazing feat of design, the Enhanced Features Register (EFR)
423 * shares the address of the Interrupt Identification Register (IIR).
424 * Access to EFR is switched on by writing a magic value (0xbf) to the
425 * Line Control Register (LCR). Any interrupt firing during this time will
426 * see the EFR where it expects the IIR to be, leading to
427 * "Unexpected interrupt" messages.
428 *
429 * Prevent this possibility by claiming a mutex while accessing the EFR,
430 * and claiming the same mutex from within the interrupt handler. This is
431 * similar to disabling the interrupt, but that doesn't work because the
432 * bulk of the interrupt processing is run as a workqueue job in thread
433 * context.
434 */
sc16is7xx_efr_lock(struct uart_port * port)435 static void sc16is7xx_efr_lock(struct uart_port *port)
436 {
437 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
438
439 mutex_lock(&one->efr_lock);
440
441 /* Backup content of LCR. */
442 one->old_lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG);
443
444 /* Enable access to Enhanced register set */
445 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_CONF_MODE_B);
446
447 /* Disable cache updates when writing to EFR registers */
448 regcache_cache_bypass(one->regmap, true);
449 }
450
sc16is7xx_efr_unlock(struct uart_port * port)451 static void sc16is7xx_efr_unlock(struct uart_port *port)
452 {
453 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
454
455 /* Re-enable cache updates when writing to normal registers */
456 regcache_cache_bypass(one->regmap, false);
457
458 /* Restore original content of LCR */
459 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, one->old_lcr);
460
461 mutex_unlock(&one->efr_lock);
462 }
463
sc16is7xx_ier_clear(struct uart_port * port,u8 bit)464 static void sc16is7xx_ier_clear(struct uart_port *port, u8 bit)
465 {
466 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
467 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
468
469 lockdep_assert_held_once(&port->lock);
470
471 one->config.flags |= SC16IS7XX_RECONF_IER;
472 one->config.ier_mask |= bit;
473 one->config.ier_val &= ~bit;
474 kthread_queue_work(&s->kworker, &one->reg_work);
475 }
476
sc16is7xx_ier_set(struct uart_port * port,u8 bit)477 static void sc16is7xx_ier_set(struct uart_port *port, u8 bit)
478 {
479 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
480 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
481
482 lockdep_assert_held_once(&port->lock);
483
484 one->config.flags |= SC16IS7XX_RECONF_IER;
485 one->config.ier_mask |= bit;
486 one->config.ier_val |= bit;
487 kthread_queue_work(&s->kworker, &one->reg_work);
488 }
489
sc16is7xx_stop_tx(struct uart_port * port)490 static void sc16is7xx_stop_tx(struct uart_port *port)
491 {
492 sc16is7xx_ier_clear(port, SC16IS7XX_IER_THRI_BIT);
493 }
494
sc16is7xx_stop_rx(struct uart_port * port)495 static void sc16is7xx_stop_rx(struct uart_port *port)
496 {
497 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT);
498 }
499
500 const struct sc16is7xx_devtype sc16is74x_devtype = {
501 .name = "SC16IS74X",
502 .nr_gpio = 0,
503 .nr_uart = 1,
504 };
505 EXPORT_SYMBOL_GPL(sc16is74x_devtype);
506
507 const struct sc16is7xx_devtype sc16is750_devtype = {
508 .name = "SC16IS750",
509 .nr_gpio = 8,
510 .nr_uart = 1,
511 };
512 EXPORT_SYMBOL_GPL(sc16is750_devtype);
513
514 const struct sc16is7xx_devtype sc16is752_devtype = {
515 .name = "SC16IS752",
516 .nr_gpio = 8,
517 .nr_uart = 2,
518 };
519 EXPORT_SYMBOL_GPL(sc16is752_devtype);
520
521 const struct sc16is7xx_devtype sc16is760_devtype = {
522 .name = "SC16IS760",
523 .nr_gpio = 8,
524 .nr_uart = 1,
525 };
526 EXPORT_SYMBOL_GPL(sc16is760_devtype);
527
528 const struct sc16is7xx_devtype sc16is762_devtype = {
529 .name = "SC16IS762",
530 .nr_gpio = 8,
531 .nr_uart = 2,
532 };
533 EXPORT_SYMBOL_GPL(sc16is762_devtype);
534
sc16is7xx_regmap_volatile(struct device * dev,unsigned int reg)535 static bool sc16is7xx_regmap_volatile(struct device *dev, unsigned int reg)
536 {
537 switch (reg) {
538 case SC16IS7XX_RHR_REG:
539 case SC16IS7XX_IIR_REG:
540 case SC16IS7XX_LSR_REG:
541 case SC16IS7XX_MSR_REG:
542 case SC16IS7XX_TXLVL_REG:
543 case SC16IS7XX_RXLVL_REG:
544 case SC16IS7XX_IOSTATE_REG:
545 case SC16IS7XX_IOCONTROL_REG:
546 return true;
547 default:
548 return false;
549 }
550 }
551
sc16is7xx_regmap_precious(struct device * dev,unsigned int reg)552 static bool sc16is7xx_regmap_precious(struct device *dev, unsigned int reg)
553 {
554 switch (reg) {
555 case SC16IS7XX_RHR_REG:
556 return true;
557 default:
558 return false;
559 }
560 }
561
sc16is7xx_regmap_noinc(struct device * dev,unsigned int reg)562 static bool sc16is7xx_regmap_noinc(struct device *dev, unsigned int reg)
563 {
564 return reg == SC16IS7XX_RHR_REG;
565 }
566
567 /*
568 * Configure programmable baud rate generator (divisor) according to the
569 * desired baud rate.
570 *
571 * From the datasheet, the divisor is computed according to:
572 *
573 * XTAL1 input frequency
574 * -----------------------
575 * prescaler
576 * divisor = ---------------------------
577 * baud-rate x sampling-rate
578 */
sc16is7xx_set_baud(struct uart_port * port,int baud)579 static int sc16is7xx_set_baud(struct uart_port *port, int baud)
580 {
581 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
582 u8 lcr;
583 unsigned int prescaler = 1;
584 unsigned long clk = port->uartclk, div = clk / 16 / baud;
585
586 if (div >= BIT(16)) {
587 prescaler = 4;
588 div /= prescaler;
589 }
590
591 /* If bit MCR_CLKSEL is set, the divide by 4 prescaler is activated. */
592 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
593 SC16IS7XX_MCR_CLKSEL_BIT,
594 prescaler == 1 ? 0 : SC16IS7XX_MCR_CLKSEL_BIT);
595
596 mutex_lock(&one->efr_lock);
597
598 /* Backup LCR and access special register set (DLL/DLH) */
599 lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG);
600 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
601 SC16IS7XX_LCR_CONF_MODE_A);
602
603 /* Write the new divisor */
604 regcache_cache_bypass(one->regmap, true);
605 sc16is7xx_port_write(port, SC16IS7XX_DLH_REG, div / 256);
606 sc16is7xx_port_write(port, SC16IS7XX_DLL_REG, div % 256);
607 regcache_cache_bypass(one->regmap, false);
608
609 /* Restore LCR and access to general register set */
610 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
611
612 mutex_unlock(&one->efr_lock);
613
614 return DIV_ROUND_CLOSEST((clk / prescaler) / 16, div);
615 }
616
sc16is7xx_handle_rx(struct uart_port * port,unsigned int rxlen,unsigned int iir)617 static void sc16is7xx_handle_rx(struct uart_port *port, unsigned int rxlen,
618 unsigned int iir)
619 {
620 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
621 unsigned int lsr = 0, bytes_read, i;
622 bool read_lsr = (iir == SC16IS7XX_IIR_RLSE_SRC);
623 u8 ch, flag;
624
625 if (unlikely(rxlen >= sizeof(one->buf))) {
626 dev_warn_ratelimited(port->dev,
627 "ttySC%i: Possible RX FIFO overrun: %d\n",
628 port->line, rxlen);
629 port->icount.buf_overrun++;
630 /* Ensure sanity of RX level */
631 rxlen = sizeof(one->buf);
632 }
633
634 while (rxlen) {
635 /* Only read lsr if there are possible errors in FIFO */
636 if (read_lsr) {
637 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
638 if (!(lsr & SC16IS7XX_LSR_FIFOE_BIT))
639 read_lsr = false; /* No errors left in FIFO */
640 } else
641 lsr = 0;
642
643 if (read_lsr) {
644 one->buf[0] = sc16is7xx_port_read(port, SC16IS7XX_RHR_REG);
645 bytes_read = 1;
646 } else {
647 sc16is7xx_fifo_read(port, one->buf, rxlen);
648 bytes_read = rxlen;
649 }
650
651 lsr &= SC16IS7XX_LSR_BRK_ERROR_MASK;
652
653 port->icount.rx++;
654 flag = TTY_NORMAL;
655
656 if (unlikely(lsr)) {
657 if (lsr & SC16IS7XX_LSR_BI_BIT) {
658 port->icount.brk++;
659 if (uart_handle_break(port))
660 continue;
661 } else if (lsr & SC16IS7XX_LSR_PE_BIT)
662 port->icount.parity++;
663 else if (lsr & SC16IS7XX_LSR_FE_BIT)
664 port->icount.frame++;
665 else if (lsr & SC16IS7XX_LSR_OE_BIT)
666 port->icount.overrun++;
667
668 lsr &= port->read_status_mask;
669 if (lsr & SC16IS7XX_LSR_BI_BIT)
670 flag = TTY_BREAK;
671 else if (lsr & SC16IS7XX_LSR_PE_BIT)
672 flag = TTY_PARITY;
673 else if (lsr & SC16IS7XX_LSR_FE_BIT)
674 flag = TTY_FRAME;
675 else if (lsr & SC16IS7XX_LSR_OE_BIT)
676 flag = TTY_OVERRUN;
677 }
678
679 for (i = 0; i < bytes_read; ++i) {
680 ch = one->buf[i];
681 if (uart_handle_sysrq_char(port, ch))
682 continue;
683
684 if (lsr & port->ignore_status_mask)
685 continue;
686
687 uart_insert_char(port, lsr, SC16IS7XX_LSR_OE_BIT, ch,
688 flag);
689 }
690 rxlen -= bytes_read;
691 }
692
693 tty_flip_buffer_push(&port->state->port);
694 }
695
sc16is7xx_handle_tx(struct uart_port * port)696 static void sc16is7xx_handle_tx(struct uart_port *port)
697 {
698 struct tty_port *tport = &port->state->port;
699 unsigned long flags;
700 unsigned int txlen;
701 unsigned char *tail;
702
703 if (unlikely(port->x_char)) {
704 sc16is7xx_port_write(port, SC16IS7XX_THR_REG, port->x_char);
705 port->icount.tx++;
706 port->x_char = 0;
707 return;
708 }
709
710 if (kfifo_is_empty(&tport->xmit_fifo) || uart_tx_stopped(port)) {
711 uart_port_lock_irqsave(port, &flags);
712 sc16is7xx_stop_tx(port);
713 uart_port_unlock_irqrestore(port, flags);
714 return;
715 }
716
717 /* Limit to space available in TX FIFO */
718 txlen = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG);
719 if (txlen > SC16IS7XX_FIFO_SIZE) {
720 dev_err_ratelimited(port->dev,
721 "chip reports %d free bytes in TX fifo, but it only has %d",
722 txlen, SC16IS7XX_FIFO_SIZE);
723 txlen = 0;
724 }
725
726 txlen = kfifo_out_linear_ptr(&tport->xmit_fifo, &tail, txlen);
727 sc16is7xx_fifo_write(port, tail, txlen);
728 uart_xmit_advance(port, txlen);
729
730 uart_port_lock_irqsave(port, &flags);
731 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
732 uart_write_wakeup(port);
733
734 if (kfifo_is_empty(&tport->xmit_fifo))
735 sc16is7xx_stop_tx(port);
736 else
737 sc16is7xx_ier_set(port, SC16IS7XX_IER_THRI_BIT);
738 uart_port_unlock_irqrestore(port, flags);
739 }
740
sc16is7xx_get_hwmctrl(struct uart_port * port)741 static unsigned int sc16is7xx_get_hwmctrl(struct uart_port *port)
742 {
743 u8 msr = sc16is7xx_port_read(port, SC16IS7XX_MSR_REG);
744 unsigned int mctrl = 0;
745
746 mctrl |= (msr & SC16IS7XX_MSR_CTS_BIT) ? TIOCM_CTS : 0;
747 mctrl |= (msr & SC16IS7XX_MSR_DSR_BIT) ? TIOCM_DSR : 0;
748 mctrl |= (msr & SC16IS7XX_MSR_CD_BIT) ? TIOCM_CAR : 0;
749 mctrl |= (msr & SC16IS7XX_MSR_RI_BIT) ? TIOCM_RNG : 0;
750 return mctrl;
751 }
752
sc16is7xx_update_mlines(struct sc16is7xx_one * one)753 static void sc16is7xx_update_mlines(struct sc16is7xx_one *one)
754 {
755 struct uart_port *port = &one->port;
756 unsigned long flags;
757 unsigned int status, changed;
758
759 lockdep_assert_held_once(&one->efr_lock);
760
761 status = sc16is7xx_get_hwmctrl(port);
762 changed = status ^ one->old_mctrl;
763
764 if (changed == 0)
765 return;
766
767 one->old_mctrl = status;
768
769 uart_port_lock_irqsave(port, &flags);
770 if ((changed & TIOCM_RNG) && (status & TIOCM_RNG))
771 port->icount.rng++;
772 if (changed & TIOCM_DSR)
773 port->icount.dsr++;
774 if (changed & TIOCM_CAR)
775 uart_handle_dcd_change(port, status & TIOCM_CAR);
776 if (changed & TIOCM_CTS)
777 uart_handle_cts_change(port, status & TIOCM_CTS);
778
779 wake_up_interruptible(&port->state->port.delta_msr_wait);
780 uart_port_unlock_irqrestore(port, flags);
781 }
782
sc16is7xx_port_irq(struct sc16is7xx_port * s,int portno)783 static bool sc16is7xx_port_irq(struct sc16is7xx_port *s, int portno)
784 {
785 bool rc = true;
786 unsigned int iir, rxlen;
787 struct uart_port *port = &s->p[portno].port;
788 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
789
790 mutex_lock(&one->efr_lock);
791
792 iir = sc16is7xx_port_read(port, SC16IS7XX_IIR_REG);
793 if (iir & SC16IS7XX_IIR_NO_INT_BIT) {
794 rc = false;
795 goto out_port_irq;
796 }
797
798 iir &= SC16IS7XX_IIR_ID_MASK;
799
800 switch (iir) {
801 case SC16IS7XX_IIR_RDI_SRC:
802 case SC16IS7XX_IIR_RLSE_SRC:
803 case SC16IS7XX_IIR_RTOI_SRC:
804 case SC16IS7XX_IIR_XOFFI_SRC:
805 rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG);
806
807 /*
808 * There is a silicon bug that makes the chip report a
809 * time-out interrupt but no data in the FIFO. This is
810 * described in errata section 18.1.4.
811 *
812 * When this happens, read one byte from the FIFO to
813 * clear the interrupt.
814 */
815 if (iir == SC16IS7XX_IIR_RTOI_SRC && !rxlen)
816 rxlen = 1;
817
818 if (rxlen)
819 sc16is7xx_handle_rx(port, rxlen, iir);
820 break;
821 /* CTSRTS interrupt comes only when CTS goes inactive */
822 case SC16IS7XX_IIR_CTSRTS_SRC:
823 case SC16IS7XX_IIR_MSI_SRC:
824 sc16is7xx_update_mlines(one);
825 break;
826 case SC16IS7XX_IIR_THRI_SRC:
827 sc16is7xx_handle_tx(port);
828 break;
829 default:
830 dev_err_ratelimited(port->dev,
831 "ttySC%i: Unexpected interrupt: %x",
832 port->line, iir);
833 break;
834 }
835
836 out_port_irq:
837 mutex_unlock(&one->efr_lock);
838
839 return rc;
840 }
841
sc16is7xx_irq(int irq,void * dev_id)842 static irqreturn_t sc16is7xx_irq(int irq, void *dev_id)
843 {
844 bool keep_polling;
845
846 struct sc16is7xx_port *s = (struct sc16is7xx_port *)dev_id;
847
848 do {
849 int i;
850
851 keep_polling = false;
852
853 for (i = 0; i < s->devtype->nr_uart; ++i)
854 keep_polling |= sc16is7xx_port_irq(s, i);
855 } while (keep_polling);
856
857 return IRQ_HANDLED;
858 }
859
sc16is7xx_poll_proc(struct kthread_work * ws)860 static void sc16is7xx_poll_proc(struct kthread_work *ws)
861 {
862 struct sc16is7xx_port *s = container_of(ws, struct sc16is7xx_port, poll_work.work);
863
864 /* Reuse standard IRQ handler. Interrupt ID is unused in this context. */
865 sc16is7xx_irq(0, s);
866
867 /* Setup delay based on SC16IS7XX_POLL_PERIOD_MS */
868 kthread_queue_delayed_work(&s->kworker, &s->poll_work,
869 msecs_to_jiffies(SC16IS7XX_POLL_PERIOD_MS));
870 }
871
sc16is7xx_tx_proc(struct kthread_work * ws)872 static void sc16is7xx_tx_proc(struct kthread_work *ws)
873 {
874 struct uart_port *port = &(to_sc16is7xx_one(ws, tx_work)->port);
875 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
876
877 if ((port->rs485.flags & SER_RS485_ENABLED) &&
878 (port->rs485.delay_rts_before_send > 0))
879 msleep(port->rs485.delay_rts_before_send);
880
881 mutex_lock(&one->efr_lock);
882 sc16is7xx_handle_tx(port);
883 mutex_unlock(&one->efr_lock);
884 }
885
sc16is7xx_reconf_rs485(struct uart_port * port)886 static void sc16is7xx_reconf_rs485(struct uart_port *port)
887 {
888 const u32 mask = SC16IS7XX_EFCR_AUTO_RS485_BIT |
889 SC16IS7XX_EFCR_RTS_INVERT_BIT;
890 u32 efcr = 0;
891 struct serial_rs485 *rs485 = &port->rs485;
892 unsigned long irqflags;
893
894 uart_port_lock_irqsave(port, &irqflags);
895 if (rs485->flags & SER_RS485_ENABLED) {
896 efcr |= SC16IS7XX_EFCR_AUTO_RS485_BIT;
897
898 if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
899 efcr |= SC16IS7XX_EFCR_RTS_INVERT_BIT;
900 }
901 uart_port_unlock_irqrestore(port, irqflags);
902
903 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, mask, efcr);
904 }
905
sc16is7xx_reg_proc(struct kthread_work * ws)906 static void sc16is7xx_reg_proc(struct kthread_work *ws)
907 {
908 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, reg_work);
909 struct sc16is7xx_one_config config;
910 unsigned long irqflags;
911
912 uart_port_lock_irqsave(&one->port, &irqflags);
913 config = one->config;
914 memset(&one->config, 0, sizeof(one->config));
915 uart_port_unlock_irqrestore(&one->port, irqflags);
916
917 if (config.flags & SC16IS7XX_RECONF_MD) {
918 u8 mcr = 0;
919
920 /* Device ignores RTS setting when hardware flow is enabled */
921 if (one->port.mctrl & TIOCM_RTS)
922 mcr |= SC16IS7XX_MCR_RTS_BIT;
923
924 if (one->port.mctrl & TIOCM_DTR)
925 mcr |= SC16IS7XX_MCR_DTR_BIT;
926
927 if (one->port.mctrl & TIOCM_LOOP)
928 mcr |= SC16IS7XX_MCR_LOOP_BIT;
929 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG,
930 SC16IS7XX_MCR_RTS_BIT |
931 SC16IS7XX_MCR_DTR_BIT |
932 SC16IS7XX_MCR_LOOP_BIT,
933 mcr);
934 }
935
936 if (config.flags & SC16IS7XX_RECONF_IER)
937 sc16is7xx_port_update(&one->port, SC16IS7XX_IER_REG,
938 config.ier_mask, config.ier_val);
939
940 if (config.flags & SC16IS7XX_RECONF_RS485)
941 sc16is7xx_reconf_rs485(&one->port);
942 }
943
sc16is7xx_ms_proc(struct kthread_work * ws)944 static void sc16is7xx_ms_proc(struct kthread_work *ws)
945 {
946 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, ms_work.work);
947 struct sc16is7xx_port *s = dev_get_drvdata(one->port.dev);
948
949 if (one->port.state) {
950 mutex_lock(&one->efr_lock);
951 sc16is7xx_update_mlines(one);
952 mutex_unlock(&one->efr_lock);
953
954 kthread_queue_delayed_work(&s->kworker, &one->ms_work, HZ);
955 }
956 }
957
sc16is7xx_enable_ms(struct uart_port * port)958 static void sc16is7xx_enable_ms(struct uart_port *port)
959 {
960 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
961 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
962
963 lockdep_assert_held_once(&port->lock);
964
965 kthread_queue_delayed_work(&s->kworker, &one->ms_work, 0);
966 }
967
sc16is7xx_start_tx(struct uart_port * port)968 static void sc16is7xx_start_tx(struct uart_port *port)
969 {
970 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
971 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
972
973 kthread_queue_work(&s->kworker, &one->tx_work);
974 }
975
sc16is7xx_throttle(struct uart_port * port)976 static void sc16is7xx_throttle(struct uart_port *port)
977 {
978 unsigned long flags;
979
980 /*
981 * Hardware flow control is enabled and thus the device ignores RTS
982 * value set in MCR register. Stop reading data from RX FIFO so the
983 * AutoRTS feature will de-activate RTS output.
984 */
985 uart_port_lock_irqsave(port, &flags);
986 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT);
987 uart_port_unlock_irqrestore(port, flags);
988 }
989
sc16is7xx_unthrottle(struct uart_port * port)990 static void sc16is7xx_unthrottle(struct uart_port *port)
991 {
992 unsigned long flags;
993
994 uart_port_lock_irqsave(port, &flags);
995 sc16is7xx_ier_set(port, SC16IS7XX_IER_RDI_BIT);
996 uart_port_unlock_irqrestore(port, flags);
997 }
998
sc16is7xx_tx_empty(struct uart_port * port)999 static unsigned int sc16is7xx_tx_empty(struct uart_port *port)
1000 {
1001 unsigned int lsr;
1002
1003 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
1004
1005 return (lsr & SC16IS7XX_LSR_TEMT_BIT) ? TIOCSER_TEMT : 0;
1006 }
1007
sc16is7xx_get_mctrl(struct uart_port * port)1008 static unsigned int sc16is7xx_get_mctrl(struct uart_port *port)
1009 {
1010 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
1011
1012 /* Called with port lock taken so we can only return cached value */
1013 return one->old_mctrl;
1014 }
1015
sc16is7xx_set_mctrl(struct uart_port * port,unsigned int mctrl)1016 static void sc16is7xx_set_mctrl(struct uart_port *port, unsigned int mctrl)
1017 {
1018 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1019 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
1020
1021 one->config.flags |= SC16IS7XX_RECONF_MD;
1022 kthread_queue_work(&s->kworker, &one->reg_work);
1023 }
1024
sc16is7xx_break_ctl(struct uart_port * port,int break_state)1025 static void sc16is7xx_break_ctl(struct uart_port *port, int break_state)
1026 {
1027 sc16is7xx_port_update(port, SC16IS7XX_LCR_REG,
1028 SC16IS7XX_LCR_TXBREAK_BIT,
1029 break_state ? SC16IS7XX_LCR_TXBREAK_BIT : 0);
1030 }
1031
sc16is7xx_set_termios(struct uart_port * port,struct ktermios * termios,const struct ktermios * old)1032 static void sc16is7xx_set_termios(struct uart_port *port,
1033 struct ktermios *termios,
1034 const struct ktermios *old)
1035 {
1036 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
1037 unsigned int lcr, flow = 0;
1038 int baud;
1039 unsigned long flags;
1040
1041 kthread_cancel_delayed_work_sync(&one->ms_work);
1042
1043 /* Mask termios capabilities we don't support */
1044 termios->c_cflag &= ~CMSPAR;
1045
1046 /* Word size */
1047 switch (termios->c_cflag & CSIZE) {
1048 case CS5:
1049 lcr = SC16IS7XX_LCR_WORD_LEN_5;
1050 break;
1051 case CS6:
1052 lcr = SC16IS7XX_LCR_WORD_LEN_6;
1053 break;
1054 case CS7:
1055 lcr = SC16IS7XX_LCR_WORD_LEN_7;
1056 break;
1057 case CS8:
1058 lcr = SC16IS7XX_LCR_WORD_LEN_8;
1059 break;
1060 default:
1061 lcr = SC16IS7XX_LCR_WORD_LEN_8;
1062 termios->c_cflag &= ~CSIZE;
1063 termios->c_cflag |= CS8;
1064 break;
1065 }
1066
1067 /* Parity */
1068 if (termios->c_cflag & PARENB) {
1069 lcr |= SC16IS7XX_LCR_PARITY_BIT;
1070 if (!(termios->c_cflag & PARODD))
1071 lcr |= SC16IS7XX_LCR_EVENPARITY_BIT;
1072 }
1073
1074 /* Stop bits */
1075 if (termios->c_cflag & CSTOPB)
1076 lcr |= SC16IS7XX_LCR_STOPLEN_BIT; /* 2 stops */
1077
1078 /* Set read status mask */
1079 port->read_status_mask = SC16IS7XX_LSR_OE_BIT;
1080 if (termios->c_iflag & INPCK)
1081 port->read_status_mask |= SC16IS7XX_LSR_PE_BIT |
1082 SC16IS7XX_LSR_FE_BIT;
1083 if (termios->c_iflag & (BRKINT | PARMRK))
1084 port->read_status_mask |= SC16IS7XX_LSR_BI_BIT;
1085
1086 /* Set status ignore mask */
1087 port->ignore_status_mask = 0;
1088 if (termios->c_iflag & IGNBRK)
1089 port->ignore_status_mask |= SC16IS7XX_LSR_BI_BIT;
1090 if (!(termios->c_cflag & CREAD))
1091 port->ignore_status_mask |= SC16IS7XX_LSR_BRK_ERROR_MASK;
1092
1093 /* Configure flow control */
1094 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
1095 if (termios->c_cflag & CRTSCTS) {
1096 flow |= SC16IS7XX_EFR_AUTOCTS_BIT |
1097 SC16IS7XX_EFR_AUTORTS_BIT;
1098 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
1099 }
1100 if (termios->c_iflag & IXON)
1101 flow |= SC16IS7XX_EFR_SWFLOW3_BIT;
1102 if (termios->c_iflag & IXOFF)
1103 flow |= SC16IS7XX_EFR_SWFLOW1_BIT;
1104
1105 /* Update LCR register */
1106 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
1107
1108 /* Update EFR registers */
1109 sc16is7xx_efr_lock(port);
1110 sc16is7xx_port_write(port, SC16IS7XX_XON1_REG, termios->c_cc[VSTART]);
1111 sc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, termios->c_cc[VSTOP]);
1112 sc16is7xx_port_update(port, SC16IS7XX_EFR_REG,
1113 SC16IS7XX_EFR_FLOWCTRL_BITS, flow);
1114 sc16is7xx_efr_unlock(port);
1115
1116 /* Get baud rate generator configuration */
1117 baud = uart_get_baud_rate(port, termios, old,
1118 port->uartclk / 16 / 4 / 0xffff,
1119 port->uartclk / 16);
1120
1121 /* Setup baudrate generator */
1122 baud = sc16is7xx_set_baud(port, baud);
1123
1124 uart_port_lock_irqsave(port, &flags);
1125
1126 /* Update timeout according to new baud rate */
1127 uart_update_timeout(port, termios->c_cflag, baud);
1128
1129 if (UART_ENABLE_MS(port, termios->c_cflag))
1130 sc16is7xx_enable_ms(port);
1131
1132 uart_port_unlock_irqrestore(port, flags);
1133 }
1134
sc16is7xx_config_rs485(struct uart_port * port,struct ktermios * termios,struct serial_rs485 * rs485)1135 static int sc16is7xx_config_rs485(struct uart_port *port, struct ktermios *termios,
1136 struct serial_rs485 *rs485)
1137 {
1138 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1139 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
1140
1141 if (rs485->flags & SER_RS485_ENABLED) {
1142 /*
1143 * RTS signal is handled by HW, it's timing can't be influenced.
1144 * However, it's sometimes useful to delay TX even without RTS
1145 * control therefore we try to handle .delay_rts_before_send.
1146 */
1147 if (rs485->delay_rts_after_send)
1148 return -EINVAL;
1149 }
1150
1151 one->config.flags |= SC16IS7XX_RECONF_RS485;
1152 kthread_queue_work(&s->kworker, &one->reg_work);
1153
1154 return 0;
1155 }
1156
sc16is7xx_startup(struct uart_port * port)1157 static int sc16is7xx_startup(struct uart_port *port)
1158 {
1159 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
1160 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1161 unsigned int val;
1162 unsigned long flags;
1163
1164 sc16is7xx_power(port, 1);
1165
1166 /* Reset FIFOs*/
1167 val = SC16IS7XX_FCR_RXRESET_BIT | SC16IS7XX_FCR_TXRESET_BIT;
1168 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, val);
1169 udelay(5);
1170 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG,
1171 SC16IS7XX_FCR_FIFO_BIT);
1172
1173 /* Enable TCR/TLR */
1174 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
1175 SC16IS7XX_MCR_TCRTLR_BIT,
1176 SC16IS7XX_MCR_TCRTLR_BIT);
1177
1178 /* Configure flow control levels */
1179 /* Flow control halt level 48, resume level 24 */
1180 sc16is7xx_port_write(port, SC16IS7XX_TCR_REG,
1181 SC16IS7XX_TCR_RX_RESUME(24) |
1182 SC16IS7XX_TCR_RX_HALT(48));
1183
1184 /* Disable TCR/TLR access */
1185 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, SC16IS7XX_MCR_TCRTLR_BIT, 0);
1186
1187 /* Now, initialize the UART */
1188 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_WORD_LEN_8);
1189
1190 /* Enable IrDA mode if requested in DT */
1191 /* This bit must be written with LCR[7] = 0 */
1192 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
1193 SC16IS7XX_MCR_IRDA_BIT,
1194 one->irda_mode ?
1195 SC16IS7XX_MCR_IRDA_BIT : 0);
1196
1197 /* Enable the Rx and Tx FIFO */
1198 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
1199 SC16IS7XX_EFCR_RXDISABLE_BIT |
1200 SC16IS7XX_EFCR_TXDISABLE_BIT,
1201 0);
1202
1203 /* Enable RX, CTS change and modem lines interrupts */
1204 val = SC16IS7XX_IER_RDI_BIT | SC16IS7XX_IER_CTSI_BIT |
1205 SC16IS7XX_IER_MSI_BIT;
1206 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val);
1207
1208 /* Enable modem status polling */
1209 uart_port_lock_irqsave(port, &flags);
1210 sc16is7xx_enable_ms(port);
1211 uart_port_unlock_irqrestore(port, flags);
1212
1213 if (s->polling)
1214 kthread_queue_delayed_work(&s->kworker, &s->poll_work,
1215 msecs_to_jiffies(SC16IS7XX_POLL_PERIOD_MS));
1216
1217 return 0;
1218 }
1219
sc16is7xx_shutdown(struct uart_port * port)1220 static void sc16is7xx_shutdown(struct uart_port *port)
1221 {
1222 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1223 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
1224
1225 kthread_cancel_delayed_work_sync(&one->ms_work);
1226
1227 /* Disable all interrupts */
1228 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0);
1229 /* Disable TX/RX */
1230 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
1231 SC16IS7XX_EFCR_RXDISABLE_BIT |
1232 SC16IS7XX_EFCR_TXDISABLE_BIT,
1233 SC16IS7XX_EFCR_RXDISABLE_BIT |
1234 SC16IS7XX_EFCR_TXDISABLE_BIT);
1235
1236 sc16is7xx_power(port, 0);
1237
1238 if (s->polling)
1239 kthread_cancel_delayed_work_sync(&s->poll_work);
1240
1241 kthread_flush_worker(&s->kworker);
1242 }
1243
sc16is7xx_type(struct uart_port * port)1244 static const char *sc16is7xx_type(struct uart_port *port)
1245 {
1246 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1247
1248 return (port->type == PORT_SC16IS7XX) ? s->devtype->name : NULL;
1249 }
1250
sc16is7xx_request_port(struct uart_port * port)1251 static int sc16is7xx_request_port(struct uart_port *port)
1252 {
1253 /* Do nothing */
1254 return 0;
1255 }
1256
sc16is7xx_config_port(struct uart_port * port,int flags)1257 static void sc16is7xx_config_port(struct uart_port *port, int flags)
1258 {
1259 if (flags & UART_CONFIG_TYPE)
1260 port->type = PORT_SC16IS7XX;
1261 }
1262
sc16is7xx_verify_port(struct uart_port * port,struct serial_struct * s)1263 static int sc16is7xx_verify_port(struct uart_port *port,
1264 struct serial_struct *s)
1265 {
1266 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_SC16IS7XX))
1267 return -EINVAL;
1268 if (s->irq != port->irq)
1269 return -EINVAL;
1270
1271 return 0;
1272 }
1273
sc16is7xx_pm(struct uart_port * port,unsigned int state,unsigned int oldstate)1274 static void sc16is7xx_pm(struct uart_port *port, unsigned int state,
1275 unsigned int oldstate)
1276 {
1277 sc16is7xx_power(port, (state == UART_PM_STATE_ON) ? 1 : 0);
1278 }
1279
sc16is7xx_null_void(struct uart_port * port)1280 static void sc16is7xx_null_void(struct uart_port *port)
1281 {
1282 /* Do nothing */
1283 }
1284
1285 static const struct uart_ops sc16is7xx_ops = {
1286 .tx_empty = sc16is7xx_tx_empty,
1287 .set_mctrl = sc16is7xx_set_mctrl,
1288 .get_mctrl = sc16is7xx_get_mctrl,
1289 .stop_tx = sc16is7xx_stop_tx,
1290 .start_tx = sc16is7xx_start_tx,
1291 .throttle = sc16is7xx_throttle,
1292 .unthrottle = sc16is7xx_unthrottle,
1293 .stop_rx = sc16is7xx_stop_rx,
1294 .enable_ms = sc16is7xx_enable_ms,
1295 .break_ctl = sc16is7xx_break_ctl,
1296 .startup = sc16is7xx_startup,
1297 .shutdown = sc16is7xx_shutdown,
1298 .set_termios = sc16is7xx_set_termios,
1299 .type = sc16is7xx_type,
1300 .request_port = sc16is7xx_request_port,
1301 .release_port = sc16is7xx_null_void,
1302 .config_port = sc16is7xx_config_port,
1303 .verify_port = sc16is7xx_verify_port,
1304 .pm = sc16is7xx_pm,
1305 };
1306
1307 #ifdef CONFIG_GPIOLIB
sc16is7xx_gpio_get(struct gpio_chip * chip,unsigned offset)1308 static int sc16is7xx_gpio_get(struct gpio_chip *chip, unsigned offset)
1309 {
1310 unsigned int val;
1311 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1312 struct uart_port *port = &s->p[0].port;
1313
1314 val = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG);
1315
1316 return !!(val & BIT(offset));
1317 }
1318
sc16is7xx_gpio_set(struct gpio_chip * chip,unsigned int offset,int val)1319 static int sc16is7xx_gpio_set(struct gpio_chip *chip, unsigned int offset,
1320 int val)
1321 {
1322 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1323 struct uart_port *port = &s->p[0].port;
1324
1325 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset),
1326 val ? BIT(offset) : 0);
1327
1328 return 0;
1329 }
1330
sc16is7xx_gpio_direction_input(struct gpio_chip * chip,unsigned offset)1331 static int sc16is7xx_gpio_direction_input(struct gpio_chip *chip,
1332 unsigned offset)
1333 {
1334 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1335 struct uart_port *port = &s->p[0].port;
1336
1337 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 0);
1338
1339 return 0;
1340 }
1341
sc16is7xx_gpio_direction_output(struct gpio_chip * chip,unsigned offset,int val)1342 static int sc16is7xx_gpio_direction_output(struct gpio_chip *chip,
1343 unsigned offset, int val)
1344 {
1345 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1346 struct uart_port *port = &s->p[0].port;
1347 u8 state = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG);
1348
1349 if (val)
1350 state |= BIT(offset);
1351 else
1352 state &= ~BIT(offset);
1353
1354 /*
1355 * If we write IOSTATE first, and then IODIR, the output value is not
1356 * transferred to the corresponding I/O pin.
1357 * The datasheet states that each register bit will be transferred to
1358 * the corresponding I/O pin programmed as output when writing to
1359 * IOSTATE. Therefore, configure direction first with IODIR, and then
1360 * set value after with IOSTATE.
1361 */
1362 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset),
1363 BIT(offset));
1364 sc16is7xx_port_write(port, SC16IS7XX_IOSTATE_REG, state);
1365
1366 return 0;
1367 }
1368
sc16is7xx_gpio_init_valid_mask(struct gpio_chip * chip,unsigned long * valid_mask,unsigned int ngpios)1369 static int sc16is7xx_gpio_init_valid_mask(struct gpio_chip *chip,
1370 unsigned long *valid_mask,
1371 unsigned int ngpios)
1372 {
1373 struct sc16is7xx_port *s = gpiochip_get_data(chip);
1374
1375 *valid_mask = s->gpio_valid_mask;
1376
1377 return 0;
1378 }
1379
sc16is7xx_setup_gpio_chip(struct sc16is7xx_port * s)1380 static int sc16is7xx_setup_gpio_chip(struct sc16is7xx_port *s)
1381 {
1382 struct device *dev = s->p[0].port.dev;
1383
1384 if (!s->devtype->nr_gpio)
1385 return 0;
1386
1387 switch (s->mctrl_mask) {
1388 case 0:
1389 s->gpio_valid_mask = GENMASK(7, 0);
1390 break;
1391 case SC16IS7XX_IOCONTROL_MODEM_A_BIT:
1392 s->gpio_valid_mask = GENMASK(3, 0);
1393 break;
1394 case SC16IS7XX_IOCONTROL_MODEM_B_BIT:
1395 s->gpio_valid_mask = GENMASK(7, 4);
1396 break;
1397 default:
1398 break;
1399 }
1400
1401 if (s->gpio_valid_mask == 0)
1402 return 0;
1403
1404 s->gpio.owner = THIS_MODULE;
1405 s->gpio.parent = dev;
1406 s->gpio.label = dev_name(dev);
1407 s->gpio.init_valid_mask = sc16is7xx_gpio_init_valid_mask;
1408 s->gpio.direction_input = sc16is7xx_gpio_direction_input;
1409 s->gpio.get = sc16is7xx_gpio_get;
1410 s->gpio.direction_output = sc16is7xx_gpio_direction_output;
1411 s->gpio.set = sc16is7xx_gpio_set;
1412 s->gpio.base = -1;
1413 s->gpio.ngpio = s->devtype->nr_gpio;
1414 s->gpio.can_sleep = 1;
1415
1416 return gpiochip_add_data(&s->gpio, s);
1417 }
1418 #endif
1419
sc16is7xx_setup_irda_ports(struct sc16is7xx_port * s)1420 static void sc16is7xx_setup_irda_ports(struct sc16is7xx_port *s)
1421 {
1422 int i;
1423 int ret;
1424 int count;
1425 u32 irda_port[SC16IS7XX_MAX_PORTS];
1426 struct device *dev = s->p[0].port.dev;
1427
1428 count = device_property_count_u32(dev, "irda-mode-ports");
1429 if (count < 0 || count > ARRAY_SIZE(irda_port))
1430 return;
1431
1432 ret = device_property_read_u32_array(dev, "irda-mode-ports",
1433 irda_port, count);
1434 if (ret)
1435 return;
1436
1437 for (i = 0; i < count; i++) {
1438 if (irda_port[i] < s->devtype->nr_uart)
1439 s->p[irda_port[i]].irda_mode = true;
1440 }
1441 }
1442
1443 /*
1444 * Configure ports designated to operate as modem control lines.
1445 */
sc16is7xx_setup_mctrl_ports(struct sc16is7xx_port * s,struct regmap * regmap)1446 static int sc16is7xx_setup_mctrl_ports(struct sc16is7xx_port *s,
1447 struct regmap *regmap)
1448 {
1449 int i;
1450 int ret;
1451 int count;
1452 u32 mctrl_port[SC16IS7XX_MAX_PORTS];
1453 struct device *dev = s->p[0].port.dev;
1454
1455 count = device_property_count_u32(dev, "nxp,modem-control-line-ports");
1456 if (count < 0 || count > ARRAY_SIZE(mctrl_port))
1457 return 0;
1458
1459 ret = device_property_read_u32_array(dev, "nxp,modem-control-line-ports",
1460 mctrl_port, count);
1461 if (ret)
1462 return ret;
1463
1464 s->mctrl_mask = 0;
1465
1466 for (i = 0; i < count; i++) {
1467 /* Use GPIO lines as modem control lines */
1468 if (mctrl_port[i] == 0)
1469 s->mctrl_mask |= SC16IS7XX_IOCONTROL_MODEM_A_BIT;
1470 else if (mctrl_port[i] == 1)
1471 s->mctrl_mask |= SC16IS7XX_IOCONTROL_MODEM_B_BIT;
1472 }
1473
1474 if (s->mctrl_mask)
1475 regmap_update_bits(
1476 regmap,
1477 SC16IS7XX_IOCONTROL_REG,
1478 SC16IS7XX_IOCONTROL_MODEM_A_BIT |
1479 SC16IS7XX_IOCONTROL_MODEM_B_BIT, s->mctrl_mask);
1480
1481 return 0;
1482 }
1483
1484 static const struct serial_rs485 sc16is7xx_rs485_supported = {
1485 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND,
1486 .delay_rts_before_send = 1,
1487 .delay_rts_after_send = 1, /* Not supported but keep returning -EINVAL */
1488 };
1489
1490 /* Reset device, purging any pending irq / data */
sc16is7xx_reset(struct device * dev,struct regmap * regmap)1491 static int sc16is7xx_reset(struct device *dev, struct regmap *regmap)
1492 {
1493 struct gpio_desc *reset_gpio;
1494
1495 /* Assert reset GPIO if defined and valid. */
1496 reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
1497 if (IS_ERR(reset_gpio))
1498 return dev_err_probe(dev, PTR_ERR(reset_gpio), "Failed to get reset GPIO\n");
1499
1500 if (reset_gpio) {
1501 /* The minimum reset pulse width is 3 us. */
1502 fsleep(5);
1503 gpiod_set_value_cansleep(reset_gpio, 0); /* Deassert GPIO */
1504 } else {
1505 /* Software reset */
1506 regmap_write(regmap, SC16IS7XX_IOCONTROL_REG,
1507 SC16IS7XX_IOCONTROL_SRESET_BIT);
1508 }
1509
1510 return 0;
1511 }
1512
sc16is7xx_probe(struct device * dev,const struct sc16is7xx_devtype * devtype,struct regmap * regmaps[],int irq)1513 int sc16is7xx_probe(struct device *dev, const struct sc16is7xx_devtype *devtype,
1514 struct regmap *regmaps[], int irq)
1515 {
1516 unsigned long freq = 0, *pfreq = dev_get_platdata(dev);
1517 unsigned int val;
1518 u32 uartclk = 0;
1519 int i, ret;
1520 struct sc16is7xx_port *s;
1521 bool port_registered[SC16IS7XX_MAX_PORTS];
1522
1523 for (i = 0; i < devtype->nr_uart; i++)
1524 if (IS_ERR(regmaps[i]))
1525 return PTR_ERR(regmaps[i]);
1526
1527 /*
1528 * This device does not have an identification register that would
1529 * tell us if we are really connected to the correct device.
1530 * The best we can do is to check if communication is at all possible.
1531 *
1532 * Note: regmap[0] is used in the probe function to access registers
1533 * common to all channels/ports, as it is guaranteed to be present on
1534 * all variants.
1535 */
1536 ret = regmap_read(regmaps[0], SC16IS7XX_LSR_REG, &val);
1537 if (ret < 0)
1538 return -EPROBE_DEFER;
1539
1540 /* Alloc port structure */
1541 s = devm_kzalloc(dev, struct_size(s, p, devtype->nr_uart), GFP_KERNEL);
1542 if (!s) {
1543 dev_err(dev, "Error allocating port structure\n");
1544 return -ENOMEM;
1545 }
1546
1547 /* Always ask for fixed clock rate from a property. */
1548 device_property_read_u32(dev, "clock-frequency", &uartclk);
1549
1550 s->polling = (irq <= 0);
1551 if (s->polling)
1552 dev_dbg(dev,
1553 "No interrupt pin definition, falling back to polling mode\n");
1554
1555 s->clk = devm_clk_get_optional(dev, NULL);
1556 if (IS_ERR(s->clk))
1557 return PTR_ERR(s->clk);
1558
1559 ret = clk_prepare_enable(s->clk);
1560 if (ret)
1561 return ret;
1562
1563 freq = clk_get_rate(s->clk);
1564 if (freq == 0) {
1565 if (uartclk)
1566 freq = uartclk;
1567 if (pfreq)
1568 freq = *pfreq;
1569 if (freq)
1570 dev_dbg(dev, "Clock frequency: %luHz\n", freq);
1571 else
1572 return -EINVAL;
1573 }
1574
1575 s->devtype = devtype;
1576 dev_set_drvdata(dev, s);
1577
1578 kthread_init_worker(&s->kworker);
1579 s->kworker_task = kthread_run(kthread_worker_fn, &s->kworker,
1580 "sc16is7xx");
1581 if (IS_ERR(s->kworker_task)) {
1582 ret = PTR_ERR(s->kworker_task);
1583 goto out_clk;
1584 }
1585 sched_set_fifo(s->kworker_task);
1586
1587 ret = sc16is7xx_reset(dev, regmaps[0]);
1588 if (ret)
1589 goto out_kthread;
1590
1591 /* Mark each port line and status as uninitialised. */
1592 for (i = 0; i < devtype->nr_uart; ++i) {
1593 s->p[i].port.line = SC16IS7XX_MAX_DEVS;
1594 port_registered[i] = false;
1595 }
1596
1597 for (i = 0; i < devtype->nr_uart; ++i) {
1598 ret = ida_alloc_max(&sc16is7xx_lines,
1599 SC16IS7XX_MAX_DEVS - 1, GFP_KERNEL);
1600 if (ret < 0)
1601 goto out_ports;
1602
1603 s->p[i].port.line = ret;
1604
1605 /* Initialize port data */
1606 s->p[i].port.dev = dev;
1607 s->p[i].port.irq = irq;
1608 s->p[i].port.type = PORT_SC16IS7XX;
1609 s->p[i].port.fifosize = SC16IS7XX_FIFO_SIZE;
1610 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY;
1611 s->p[i].port.iobase = i;
1612 /*
1613 * Use all ones as membase to make sure uart_configure_port() in
1614 * serial_core.c does not abort for SPI/I2C devices where the
1615 * membase address is not applicable.
1616 */
1617 s->p[i].port.membase = (void __iomem *)~0;
1618 s->p[i].port.iotype = UPIO_PORT;
1619 s->p[i].port.uartclk = freq;
1620 s->p[i].port.rs485_config = sc16is7xx_config_rs485;
1621 s->p[i].port.rs485_supported = sc16is7xx_rs485_supported;
1622 s->p[i].port.ops = &sc16is7xx_ops;
1623 s->p[i].old_mctrl = 0;
1624 s->p[i].regmap = regmaps[i];
1625
1626 mutex_init(&s->p[i].efr_lock);
1627
1628 ret = uart_get_rs485_mode(&s->p[i].port);
1629 if (ret)
1630 goto out_ports;
1631
1632 /* Disable all interrupts */
1633 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_IER_REG, 0);
1634 /* Disable TX/RX */
1635 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFCR_REG,
1636 SC16IS7XX_EFCR_RXDISABLE_BIT |
1637 SC16IS7XX_EFCR_TXDISABLE_BIT);
1638
1639 /* Initialize kthread work structs */
1640 kthread_init_work(&s->p[i].tx_work, sc16is7xx_tx_proc);
1641 kthread_init_work(&s->p[i].reg_work, sc16is7xx_reg_proc);
1642 kthread_init_delayed_work(&s->p[i].ms_work, sc16is7xx_ms_proc);
1643
1644 /* Register port */
1645 ret = uart_add_one_port(&sc16is7xx_uart, &s->p[i].port);
1646 if (ret)
1647 goto out_ports;
1648
1649 port_registered[i] = true;
1650
1651 /* Enable EFR */
1652 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG,
1653 SC16IS7XX_LCR_CONF_MODE_B);
1654
1655 regcache_cache_bypass(regmaps[i], true);
1656
1657 /* Enable write access to enhanced features */
1658 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFR_REG,
1659 SC16IS7XX_EFR_ENABLE_BIT);
1660
1661 regcache_cache_bypass(regmaps[i], false);
1662
1663 /* Restore access to general registers */
1664 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG, 0x00);
1665
1666 /* Go to suspend mode */
1667 sc16is7xx_power(&s->p[i].port, 0);
1668 }
1669
1670 sc16is7xx_setup_irda_ports(s);
1671
1672 ret = sc16is7xx_setup_mctrl_ports(s, regmaps[0]);
1673 if (ret)
1674 goto out_ports;
1675
1676 #ifdef CONFIG_GPIOLIB
1677 ret = sc16is7xx_setup_gpio_chip(s);
1678 if (ret)
1679 goto out_ports;
1680 #endif
1681
1682 if (s->polling) {
1683 /* Initialize kernel thread for polling */
1684 kthread_init_delayed_work(&s->poll_work, sc16is7xx_poll_proc);
1685 return 0;
1686 }
1687
1688 /*
1689 * Setup interrupt. We first try to acquire the IRQ line as level IRQ.
1690 * If that succeeds, we can allow sharing the interrupt as well.
1691 * In case the interrupt controller doesn't support that, we fall
1692 * back to a non-shared falling-edge trigger.
1693 */
1694 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq,
1695 IRQF_TRIGGER_LOW | IRQF_SHARED |
1696 IRQF_ONESHOT,
1697 dev_name(dev), s);
1698 if (!ret)
1699 return 0;
1700
1701 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq,
1702 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1703 dev_name(dev), s);
1704 if (!ret)
1705 return 0;
1706
1707 #ifdef CONFIG_GPIOLIB
1708 if (s->gpio_valid_mask)
1709 gpiochip_remove(&s->gpio);
1710 #endif
1711
1712 out_ports:
1713 for (i = 0; i < devtype->nr_uart; i++) {
1714 if (s->p[i].port.line < SC16IS7XX_MAX_DEVS)
1715 ida_free(&sc16is7xx_lines, s->p[i].port.line);
1716 if (port_registered[i])
1717 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port);
1718 }
1719
1720 out_kthread:
1721 kthread_stop(s->kworker_task);
1722
1723 out_clk:
1724 clk_disable_unprepare(s->clk);
1725
1726 return ret;
1727 }
1728 EXPORT_SYMBOL_GPL(sc16is7xx_probe);
1729
sc16is7xx_remove(struct device * dev)1730 void sc16is7xx_remove(struct device *dev)
1731 {
1732 struct sc16is7xx_port *s = dev_get_drvdata(dev);
1733 int i;
1734
1735 #ifdef CONFIG_GPIOLIB
1736 if (s->gpio_valid_mask)
1737 gpiochip_remove(&s->gpio);
1738 #endif
1739
1740 for (i = 0; i < s->devtype->nr_uart; i++) {
1741 kthread_cancel_delayed_work_sync(&s->p[i].ms_work);
1742 ida_free(&sc16is7xx_lines, s->p[i].port.line);
1743 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port);
1744 sc16is7xx_power(&s->p[i].port, 0);
1745 }
1746
1747 if (s->polling)
1748 kthread_cancel_delayed_work_sync(&s->poll_work);
1749
1750 kthread_flush_worker(&s->kworker);
1751 kthread_stop(s->kworker_task);
1752
1753 clk_disable_unprepare(s->clk);
1754 }
1755 EXPORT_SYMBOL_GPL(sc16is7xx_remove);
1756
1757 const struct of_device_id __maybe_unused sc16is7xx_dt_ids[] = {
1758 { .compatible = "nxp,sc16is740", .data = &sc16is74x_devtype, },
1759 { .compatible = "nxp,sc16is741", .data = &sc16is74x_devtype, },
1760 { .compatible = "nxp,sc16is750", .data = &sc16is750_devtype, },
1761 { .compatible = "nxp,sc16is752", .data = &sc16is752_devtype, },
1762 { .compatible = "nxp,sc16is760", .data = &sc16is760_devtype, },
1763 { .compatible = "nxp,sc16is762", .data = &sc16is762_devtype, },
1764 { }
1765 };
1766 EXPORT_SYMBOL_GPL(sc16is7xx_dt_ids);
1767 MODULE_DEVICE_TABLE(of, sc16is7xx_dt_ids);
1768
1769 const struct regmap_config sc16is7xx_regcfg = {
1770 .reg_bits = 5,
1771 .pad_bits = 3,
1772 .val_bits = 8,
1773 .cache_type = REGCACHE_MAPLE,
1774 .volatile_reg = sc16is7xx_regmap_volatile,
1775 .precious_reg = sc16is7xx_regmap_precious,
1776 .writeable_noinc_reg = sc16is7xx_regmap_noinc,
1777 .readable_noinc_reg = sc16is7xx_regmap_noinc,
1778 .max_raw_read = SC16IS7XX_FIFO_SIZE,
1779 .max_raw_write = SC16IS7XX_FIFO_SIZE,
1780 .max_register = SC16IS7XX_EFCR_REG,
1781 };
1782 EXPORT_SYMBOL_GPL(sc16is7xx_regcfg);
1783
sc16is7xx_regmap_name(u8 port_id)1784 const char *sc16is7xx_regmap_name(u8 port_id)
1785 {
1786 switch (port_id) {
1787 case 0: return "port0";
1788 case 1: return "port1";
1789 default:
1790 WARN_ON(true);
1791 return NULL;
1792 }
1793 }
1794 EXPORT_SYMBOL_GPL(sc16is7xx_regmap_name);
1795
sc16is7xx_regmap_port_mask(unsigned int port_id)1796 unsigned int sc16is7xx_regmap_port_mask(unsigned int port_id)
1797 {
1798 /* CH1,CH0 are at bits 2:1. */
1799 return port_id << 1;
1800 }
1801 EXPORT_SYMBOL_GPL(sc16is7xx_regmap_port_mask);
1802
sc16is7xx_init(void)1803 static int __init sc16is7xx_init(void)
1804 {
1805 return uart_register_driver(&sc16is7xx_uart);
1806 }
1807 module_init(sc16is7xx_init);
1808
sc16is7xx_exit(void)1809 static void __exit sc16is7xx_exit(void)
1810 {
1811 uart_unregister_driver(&sc16is7xx_uart);
1812 }
1813 module_exit(sc16is7xx_exit);
1814
1815 MODULE_LICENSE("GPL");
1816 MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>");
1817 MODULE_DESCRIPTION("SC16IS7xx tty serial core driver");
1818