1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2001,2002,2003,2004 Broadcom Corporation 4 * Copyright (c) 2006, 2007 Maciej W. Rozycki 5 * 6 * This driver is designed for the Broadcom SiByte SOC built-in 7 * Ethernet controllers. Written by Mitch Lichtenberg at Broadcom Corp. 8 * 9 * Updated to the driver model and the PHY abstraction layer 10 * by Maciej W. Rozycki. 11 */ 12 13 #include <linux/bug.h> 14 #include <linux/module.h> 15 #include <linux/kernel.h> 16 #include <linux/string.h> 17 #include <linux/timer.h> 18 #include <linux/errno.h> 19 #include <linux/ioport.h> 20 #include <linux/slab.h> 21 #include <linux/interrupt.h> 22 #include <linux/netdevice.h> 23 #include <linux/etherdevice.h> 24 #include <linux/skbuff.h> 25 #include <linux/bitops.h> 26 #include <linux/err.h> 27 #include <linux/ethtool.h> 28 #include <linux/mii.h> 29 #include <linux/phy.h> 30 #include <linux/platform_device.h> 31 #include <linux/prefetch.h> 32 33 #include <asm/cache.h> 34 #include <asm/io.h> 35 #include <asm/processor.h> /* Processor type for cache alignment. */ 36 37 /* Operational parameters that usually are not changed. */ 38 39 #define CONFIG_SBMAC_COALESCE 40 41 /* Time in jiffies before concluding the transmitter is hung. */ 42 #define TX_TIMEOUT (2*HZ) 43 44 45 MODULE_AUTHOR("Mitch Lichtenberg (Broadcom Corp.)"); 46 MODULE_DESCRIPTION("Broadcom SiByte SOC GB Ethernet driver"); 47 48 /* A few user-configurable values which may be modified when a driver 49 module is loaded. */ 50 51 /* 1 normal messages, 0 quiet .. 7 verbose. */ 52 static int debug = 1; 53 module_param(debug, int, 0444); 54 MODULE_PARM_DESC(debug, "Debug messages"); 55 56 #ifdef CONFIG_SBMAC_COALESCE 57 static int int_pktcnt_tx = 255; 58 module_param(int_pktcnt_tx, int, 0444); 59 MODULE_PARM_DESC(int_pktcnt_tx, "TX packet count"); 60 61 static int int_timeout_tx = 255; 62 module_param(int_timeout_tx, int, 0444); 63 MODULE_PARM_DESC(int_timeout_tx, "TX timeout value"); 64 65 static int int_pktcnt_rx = 64; 66 module_param(int_pktcnt_rx, int, 0444); 67 MODULE_PARM_DESC(int_pktcnt_rx, "RX packet count"); 68 69 static int int_timeout_rx = 64; 70 module_param(int_timeout_rx, int, 0444); 71 MODULE_PARM_DESC(int_timeout_rx, "RX timeout value"); 72 #endif 73 74 #include <asm/sibyte/board.h> 75 #include <asm/sibyte/sb1250.h> 76 #if defined(CONFIG_SIBYTE_BCM1x80) 77 #include <asm/sibyte/bcm1480_regs.h> 78 #include <asm/sibyte/bcm1480_int.h> 79 #define R_MAC_DMA_OODPKTLOST_RX R_MAC_DMA_OODPKTLOST 80 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X) 81 #include <asm/sibyte/sb1250_regs.h> 82 #include <asm/sibyte/sb1250_int.h> 83 #else 84 #error invalid SiByte MAC configuration 85 #endif 86 #include <asm/sibyte/sb1250_scd.h> 87 #include <asm/sibyte/sb1250_mac.h> 88 #include <asm/sibyte/sb1250_dma.h> 89 90 #if defined(CONFIG_SIBYTE_BCM1x80) 91 #define UNIT_INT(n) (K_BCM1480_INT_MAC_0 + ((n) * 2)) 92 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X) 93 #define UNIT_INT(n) (K_INT_MAC_0 + (n)) 94 #else 95 #error invalid SiByte MAC configuration 96 #endif 97 98 #ifdef K_INT_PHY 99 #define SBMAC_PHY_INT K_INT_PHY 100 #else 101 #define SBMAC_PHY_INT PHY_POLL 102 #endif 103 104 /********************************************************************** 105 * Simple types 106 ********************************************************************* */ 107 108 enum sbmac_speed { 109 sbmac_speed_none = 0, 110 sbmac_speed_10 = SPEED_10, 111 sbmac_speed_100 = SPEED_100, 112 sbmac_speed_1000 = SPEED_1000, 113 }; 114 115 enum sbmac_duplex { 116 sbmac_duplex_none = -1, 117 sbmac_duplex_half = DUPLEX_HALF, 118 sbmac_duplex_full = DUPLEX_FULL, 119 }; 120 121 enum sbmac_fc { 122 sbmac_fc_none, 123 sbmac_fc_disabled, 124 sbmac_fc_frame, 125 sbmac_fc_collision, 126 sbmac_fc_carrier, 127 }; 128 129 enum sbmac_state { 130 sbmac_state_uninit, 131 sbmac_state_off, 132 sbmac_state_on, 133 sbmac_state_broken, 134 }; 135 136 137 /********************************************************************** 138 * Macros 139 ********************************************************************* */ 140 141 142 #define SBDMA_NEXTBUF(d,f) ((((d)->f+1) == (d)->sbdma_dscrtable_end) ? \ 143 (d)->sbdma_dscrtable : (d)->f+1) 144 145 146 #define NUMCACHEBLKS(x) DIV_ROUND_UP(x, SMP_CACHE_BYTES) 147 148 #define SBMAC_MAX_TXDESCR 256 149 #define SBMAC_MAX_RXDESCR 256 150 151 #define ENET_PACKET_SIZE 1518 152 /*#define ENET_PACKET_SIZE 9216 */ 153 154 /********************************************************************** 155 * DMA Descriptor structure 156 ********************************************************************* */ 157 158 struct sbdmadscr { 159 uint64_t dscr_a; 160 uint64_t dscr_b; 161 }; 162 163 /********************************************************************** 164 * DMA Controller structure 165 ********************************************************************* */ 166 167 struct sbmacdma { 168 169 /* 170 * This stuff is used to identify the channel and the registers 171 * associated with it. 172 */ 173 struct sbmac_softc *sbdma_eth; /* back pointer to associated 174 MAC */ 175 int sbdma_channel; /* channel number */ 176 int sbdma_txdir; /* direction (1=transmit) */ 177 int sbdma_maxdescr; /* total # of descriptors 178 in ring */ 179 #ifdef CONFIG_SBMAC_COALESCE 180 int sbdma_int_pktcnt; 181 /* # descriptors rx/tx 182 before interrupt */ 183 int sbdma_int_timeout; 184 /* # usec rx/tx interrupt */ 185 #endif 186 void __iomem *sbdma_config0; /* DMA config register 0 */ 187 void __iomem *sbdma_config1; /* DMA config register 1 */ 188 void __iomem *sbdma_dscrbase; 189 /* descriptor base address */ 190 void __iomem *sbdma_dscrcnt; /* descriptor count register */ 191 void __iomem *sbdma_curdscr; /* current descriptor 192 address */ 193 void __iomem *sbdma_oodpktlost; 194 /* pkt drop (rx only) */ 195 196 /* 197 * This stuff is for maintenance of the ring 198 */ 199 void *sbdma_dscrtable_unaligned; 200 struct sbdmadscr *sbdma_dscrtable; 201 /* base of descriptor table */ 202 struct sbdmadscr *sbdma_dscrtable_end; 203 /* end of descriptor table */ 204 struct sk_buff **sbdma_ctxtable; 205 /* context table, one 206 per descr */ 207 dma_addr_t sbdma_dscrtable_phys; 208 /* and also the phys addr */ 209 struct sbdmadscr *sbdma_addptr; /* next dscr for sw to add */ 210 struct sbdmadscr *sbdma_remptr; /* next dscr for sw 211 to remove */ 212 }; 213 214 215 /********************************************************************** 216 * Ethernet softc structure 217 ********************************************************************* */ 218 219 struct sbmac_softc { 220 221 /* 222 * Linux-specific things 223 */ 224 struct net_device *sbm_dev; /* pointer to linux device */ 225 struct napi_struct napi; 226 struct phy_device *phy_dev; /* the associated PHY device */ 227 struct mii_bus *mii_bus; /* the MII bus */ 228 spinlock_t sbm_lock; /* spin lock */ 229 int sbm_devflags; /* current device flags */ 230 231 /* 232 * Controller-specific things 233 */ 234 void __iomem *sbm_base; /* MAC's base address */ 235 enum sbmac_state sbm_state; /* current state */ 236 237 void __iomem *sbm_macenable; /* MAC Enable Register */ 238 void __iomem *sbm_maccfg; /* MAC Config Register */ 239 void __iomem *sbm_fifocfg; /* FIFO Config Register */ 240 void __iomem *sbm_framecfg; /* Frame Config Register */ 241 void __iomem *sbm_rxfilter; /* Receive Filter Register */ 242 void __iomem *sbm_isr; /* Interrupt Status Register */ 243 void __iomem *sbm_imr; /* Interrupt Mask Register */ 244 void __iomem *sbm_mdio; /* MDIO Register */ 245 246 enum sbmac_speed sbm_speed; /* current speed */ 247 enum sbmac_duplex sbm_duplex; /* current duplex */ 248 enum sbmac_fc sbm_fc; /* cur. flow control setting */ 249 int sbm_pause; /* current pause setting */ 250 int sbm_link; /* current link state */ 251 252 unsigned char sbm_hwaddr[ETH_ALEN]; 253 254 struct sbmacdma sbm_txdma; /* only channel 0 for now */ 255 struct sbmacdma sbm_rxdma; 256 int rx_hw_checksum; 257 int sbe_idx; 258 }; 259 260 261 /********************************************************************** 262 * Externs 263 ********************************************************************* */ 264 265 /********************************************************************** 266 * Prototypes 267 ********************************************************************* */ 268 269 static void sbdma_initctx(struct sbmacdma *d, struct sbmac_softc *s, int chan, 270 int txrx, int maxdescr); 271 static void sbdma_channel_start(struct sbmacdma *d, int rxtx); 272 static int sbdma_add_rcvbuffer(struct sbmac_softc *sc, struct sbmacdma *d, 273 struct sk_buff *m); 274 static int sbdma_add_txbuffer(struct sbmacdma *d, struct sk_buff *m); 275 static void sbdma_emptyring(struct sbmacdma *d); 276 static void sbdma_fillring(struct sbmac_softc *sc, struct sbmacdma *d); 277 static int sbdma_rx_process(struct sbmac_softc *sc, struct sbmacdma *d, 278 int work_to_do, int poll); 279 static void sbdma_tx_process(struct sbmac_softc *sc, struct sbmacdma *d, 280 int poll); 281 static int sbmac_initctx(struct sbmac_softc *s); 282 static void sbmac_channel_start(struct sbmac_softc *s); 283 static void sbmac_channel_stop(struct sbmac_softc *s); 284 static enum sbmac_state sbmac_set_channel_state(struct sbmac_softc *, 285 enum sbmac_state); 286 static void sbmac_promiscuous_mode(struct sbmac_softc *sc, int onoff); 287 static uint64_t sbmac_addr2reg(unsigned char *ptr); 288 static irqreturn_t sbmac_intr(int irq, void *dev_instance); 289 static netdev_tx_t sbmac_start_tx(struct sk_buff *skb, struct net_device *dev); 290 static void sbmac_setmulti(struct sbmac_softc *sc); 291 static int sbmac_init(struct platform_device *pldev, long long base); 292 static int sbmac_set_speed(struct sbmac_softc *s, enum sbmac_speed speed); 293 static int sbmac_set_duplex(struct sbmac_softc *s, enum sbmac_duplex duplex, 294 enum sbmac_fc fc); 295 296 static int sbmac_open(struct net_device *dev); 297 static void sbmac_tx_timeout (struct net_device *dev, unsigned int txqueue); 298 static void sbmac_set_rx_mode(struct net_device *dev); 299 static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); 300 static int sbmac_close(struct net_device *dev); 301 static int sbmac_poll(struct napi_struct *napi, int budget); 302 303 static void sbmac_mii_poll(struct net_device *dev); 304 static int sbmac_mii_probe(struct net_device *dev); 305 306 static void sbmac_mii_sync(void __iomem *sbm_mdio); 307 static void sbmac_mii_senddata(void __iomem *sbm_mdio, unsigned int data, 308 int bitcnt); 309 static int sbmac_mii_read(struct mii_bus *bus, int phyaddr, int regidx); 310 static int sbmac_mii_write(struct mii_bus *bus, int phyaddr, int regidx, 311 u16 val); 312 313 314 /********************************************************************** 315 * Globals 316 ********************************************************************* */ 317 318 static char sbmac_string[] = "sb1250-mac"; 319 320 static char sbmac_mdio_string[] = "sb1250-mac-mdio"; 321 322 323 /********************************************************************** 324 * MDIO constants 325 ********************************************************************* */ 326 327 #define MII_COMMAND_START 0x01 328 #define MII_COMMAND_READ 0x02 329 #define MII_COMMAND_WRITE 0x01 330 #define MII_COMMAND_ACK 0x02 331 332 #define M_MAC_MDIO_DIR_OUTPUT 0 /* for clarity */ 333 334 #define ENABLE 1 335 #define DISABLE 0 336 337 /********************************************************************** 338 * SBMAC_MII_SYNC(sbm_mdio) 339 * 340 * Synchronize with the MII - send a pattern of bits to the MII 341 * that will guarantee that it is ready to accept a command. 342 * 343 * Input parameters: 344 * sbm_mdio - address of the MAC's MDIO register 345 * 346 * Return value: 347 * nothing 348 ********************************************************************* */ 349 350 static void sbmac_mii_sync(void __iomem *sbm_mdio) 351 { 352 int cnt; 353 uint64_t bits; 354 int mac_mdio_genc; 355 356 mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC; 357 358 bits = M_MAC_MDIO_DIR_OUTPUT | M_MAC_MDIO_OUT; 359 360 __raw_writeq(bits | mac_mdio_genc, sbm_mdio); 361 362 for (cnt = 0; cnt < 32; cnt++) { 363 __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, sbm_mdio); 364 __raw_writeq(bits | mac_mdio_genc, sbm_mdio); 365 } 366 } 367 368 /********************************************************************** 369 * SBMAC_MII_SENDDATA(sbm_mdio, data, bitcnt) 370 * 371 * Send some bits to the MII. The bits to be sent are right- 372 * justified in the 'data' parameter. 373 * 374 * Input parameters: 375 * sbm_mdio - address of the MAC's MDIO register 376 * data - data to send 377 * bitcnt - number of bits to send 378 ********************************************************************* */ 379 380 static void sbmac_mii_senddata(void __iomem *sbm_mdio, unsigned int data, 381 int bitcnt) 382 { 383 int i; 384 uint64_t bits; 385 unsigned int curmask; 386 int mac_mdio_genc; 387 388 mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC; 389 390 bits = M_MAC_MDIO_DIR_OUTPUT; 391 __raw_writeq(bits | mac_mdio_genc, sbm_mdio); 392 393 curmask = 1 << (bitcnt - 1); 394 395 for (i = 0; i < bitcnt; i++) { 396 if (data & curmask) 397 bits |= M_MAC_MDIO_OUT; 398 else bits &= ~M_MAC_MDIO_OUT; 399 __raw_writeq(bits | mac_mdio_genc, sbm_mdio); 400 __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, sbm_mdio); 401 __raw_writeq(bits | mac_mdio_genc, sbm_mdio); 402 curmask >>= 1; 403 } 404 } 405 406 407 408 /********************************************************************** 409 * SBMAC_MII_READ(bus, phyaddr, regidx) 410 * Read a PHY register. 411 * 412 * Input parameters: 413 * bus - MDIO bus handle 414 * phyaddr - PHY's address 415 * regnum - index of register to read 416 * 417 * Return value: 418 * value read, or 0xffff if an error occurred. 419 ********************************************************************* */ 420 421 static int sbmac_mii_read(struct mii_bus *bus, int phyaddr, int regidx) 422 { 423 struct sbmac_softc *sc = (struct sbmac_softc *)bus->priv; 424 void __iomem *sbm_mdio = sc->sbm_mdio; 425 int idx; 426 int error; 427 int regval; 428 int mac_mdio_genc; 429 430 /* 431 * Synchronize ourselves so that the PHY knows the next 432 * thing coming down is a command 433 */ 434 sbmac_mii_sync(sbm_mdio); 435 436 /* 437 * Send the data to the PHY. The sequence is 438 * a "start" command (2 bits) 439 * a "read" command (2 bits) 440 * the PHY addr (5 bits) 441 * the register index (5 bits) 442 */ 443 sbmac_mii_senddata(sbm_mdio, MII_COMMAND_START, 2); 444 sbmac_mii_senddata(sbm_mdio, MII_COMMAND_READ, 2); 445 sbmac_mii_senddata(sbm_mdio, phyaddr, 5); 446 sbmac_mii_senddata(sbm_mdio, regidx, 5); 447 448 mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC; 449 450 /* 451 * Switch the port around without a clock transition. 452 */ 453 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio); 454 455 /* 456 * Send out a clock pulse to signal we want the status 457 */ 458 __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc, 459 sbm_mdio); 460 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio); 461 462 /* 463 * If an error occurred, the PHY will signal '1' back 464 */ 465 error = __raw_readq(sbm_mdio) & M_MAC_MDIO_IN; 466 467 /* 468 * Issue an 'idle' clock pulse, but keep the direction 469 * the same. 470 */ 471 __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc, 472 sbm_mdio); 473 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio); 474 475 regval = 0; 476 477 for (idx = 0; idx < 16; idx++) { 478 regval <<= 1; 479 480 if (error == 0) { 481 if (__raw_readq(sbm_mdio) & M_MAC_MDIO_IN) 482 regval |= 1; 483 } 484 485 __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc, 486 sbm_mdio); 487 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio); 488 } 489 490 /* Switch back to output */ 491 __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, sbm_mdio); 492 493 if (error == 0) 494 return regval; 495 return 0xffff; 496 } 497 498 499 /********************************************************************** 500 * SBMAC_MII_WRITE(bus, phyaddr, regidx, regval) 501 * 502 * Write a value to a PHY register. 503 * 504 * Input parameters: 505 * bus - MDIO bus handle 506 * phyaddr - PHY to use 507 * regidx - register within the PHY 508 * regval - data to write to register 509 * 510 * Return value: 511 * 0 for success 512 ********************************************************************* */ 513 514 static int sbmac_mii_write(struct mii_bus *bus, int phyaddr, int regidx, 515 u16 regval) 516 { 517 struct sbmac_softc *sc = (struct sbmac_softc *)bus->priv; 518 void __iomem *sbm_mdio = sc->sbm_mdio; 519 int mac_mdio_genc; 520 521 sbmac_mii_sync(sbm_mdio); 522 523 sbmac_mii_senddata(sbm_mdio, MII_COMMAND_START, 2); 524 sbmac_mii_senddata(sbm_mdio, MII_COMMAND_WRITE, 2); 525 sbmac_mii_senddata(sbm_mdio, phyaddr, 5); 526 sbmac_mii_senddata(sbm_mdio, regidx, 5); 527 sbmac_mii_senddata(sbm_mdio, MII_COMMAND_ACK, 2); 528 sbmac_mii_senddata(sbm_mdio, regval, 16); 529 530 mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC; 531 532 __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, sbm_mdio); 533 534 return 0; 535 } 536 537 538 539 /********************************************************************** 540 * SBDMA_INITCTX(d,s,chan,txrx,maxdescr) 541 * 542 * Initialize a DMA channel context. Since there are potentially 543 * eight DMA channels per MAC, it's nice to do this in a standard 544 * way. 545 * 546 * Input parameters: 547 * d - struct sbmacdma (DMA channel context) 548 * s - struct sbmac_softc (pointer to a MAC) 549 * chan - channel number (0..1 right now) 550 * txrx - Identifies DMA_TX or DMA_RX for channel direction 551 * maxdescr - number of descriptors 552 * 553 * Return value: 554 * nothing 555 ********************************************************************* */ 556 557 static void sbdma_initctx(struct sbmacdma *d, struct sbmac_softc *s, int chan, 558 int txrx, int maxdescr) 559 { 560 #ifdef CONFIG_SBMAC_COALESCE 561 int int_pktcnt, int_timeout; 562 #endif 563 564 /* 565 * Save away interesting stuff in the structure 566 */ 567 568 d->sbdma_eth = s; 569 d->sbdma_channel = chan; 570 d->sbdma_txdir = txrx; 571 572 #if 0 573 /* RMON clearing */ 574 s->sbe_idx =(s->sbm_base - A_MAC_BASE_0)/MAC_SPACING; 575 #endif 576 577 __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_BYTES); 578 __raw_writeq(0, s->sbm_base + R_MAC_RMON_COLLISIONS); 579 __raw_writeq(0, s->sbm_base + R_MAC_RMON_LATE_COL); 580 __raw_writeq(0, s->sbm_base + R_MAC_RMON_EX_COL); 581 __raw_writeq(0, s->sbm_base + R_MAC_RMON_FCS_ERROR); 582 __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_ABORT); 583 __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_BAD); 584 __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_GOOD); 585 __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_RUNT); 586 __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_OVERSIZE); 587 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_BYTES); 588 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_MCAST); 589 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_BCAST); 590 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_BAD); 591 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_GOOD); 592 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_RUNT); 593 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_OVERSIZE); 594 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_FCS_ERROR); 595 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_LENGTH_ERROR); 596 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_CODE_ERROR); 597 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_ALIGN_ERROR); 598 599 /* 600 * initialize register pointers 601 */ 602 603 d->sbdma_config0 = 604 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG0); 605 d->sbdma_config1 = 606 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG1); 607 d->sbdma_dscrbase = 608 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_BASE); 609 d->sbdma_dscrcnt = 610 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_CNT); 611 d->sbdma_curdscr = 612 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CUR_DSCRADDR); 613 if (d->sbdma_txdir) 614 d->sbdma_oodpktlost = NULL; 615 else 616 d->sbdma_oodpktlost = 617 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_OODPKTLOST_RX); 618 619 /* 620 * Allocate memory for the ring 621 */ 622 623 d->sbdma_maxdescr = maxdescr; 624 625 d->sbdma_dscrtable_unaligned = kzalloc_objs(*d->sbdma_dscrtable, 626 d->sbdma_maxdescr + 1); 627 628 /* 629 * The descriptor table must be aligned to at least 16 bytes or the 630 * MAC will corrupt it. 631 */ 632 d->sbdma_dscrtable = (struct sbdmadscr *) 633 ALIGN((unsigned long)d->sbdma_dscrtable_unaligned, 634 sizeof(*d->sbdma_dscrtable)); 635 636 d->sbdma_dscrtable_end = d->sbdma_dscrtable + d->sbdma_maxdescr; 637 638 d->sbdma_dscrtable_phys = virt_to_phys(d->sbdma_dscrtable); 639 640 /* 641 * And context table 642 */ 643 644 d->sbdma_ctxtable = kzalloc_objs(*d->sbdma_ctxtable, d->sbdma_maxdescr); 645 646 #ifdef CONFIG_SBMAC_COALESCE 647 /* 648 * Setup Rx/Tx DMA coalescing defaults 649 */ 650 651 int_pktcnt = (txrx == DMA_TX) ? int_pktcnt_tx : int_pktcnt_rx; 652 if ( int_pktcnt ) { 653 d->sbdma_int_pktcnt = int_pktcnt; 654 } else { 655 d->sbdma_int_pktcnt = 1; 656 } 657 658 int_timeout = (txrx == DMA_TX) ? int_timeout_tx : int_timeout_rx; 659 if ( int_timeout ) { 660 d->sbdma_int_timeout = int_timeout; 661 } else { 662 d->sbdma_int_timeout = 0; 663 } 664 #endif 665 666 } 667 668 /********************************************************************** 669 * SBDMA_CHANNEL_START(d) 670 * 671 * Initialize the hardware registers for a DMA channel. 672 * 673 * Input parameters: 674 * d - DMA channel to init (context must be previously init'd 675 * rxtx - DMA_RX or DMA_TX depending on what type of channel 676 * 677 * Return value: 678 * nothing 679 ********************************************************************* */ 680 681 static void sbdma_channel_start(struct sbmacdma *d, int rxtx) 682 { 683 /* 684 * Turn on the DMA channel 685 */ 686 687 #ifdef CONFIG_SBMAC_COALESCE 688 __raw_writeq(V_DMA_INT_TIMEOUT(d->sbdma_int_timeout) | 689 0, d->sbdma_config1); 690 __raw_writeq(M_DMA_EOP_INT_EN | 691 V_DMA_RINGSZ(d->sbdma_maxdescr) | 692 V_DMA_INT_PKTCNT(d->sbdma_int_pktcnt) | 693 0, d->sbdma_config0); 694 #else 695 __raw_writeq(0, d->sbdma_config1); 696 __raw_writeq(V_DMA_RINGSZ(d->sbdma_maxdescr) | 697 0, d->sbdma_config0); 698 #endif 699 700 __raw_writeq(d->sbdma_dscrtable_phys, d->sbdma_dscrbase); 701 702 /* 703 * Initialize ring pointers 704 */ 705 706 d->sbdma_addptr = d->sbdma_dscrtable; 707 d->sbdma_remptr = d->sbdma_dscrtable; 708 } 709 710 /********************************************************************** 711 * SBDMA_CHANNEL_STOP(d) 712 * 713 * Initialize the hardware registers for a DMA channel. 714 * 715 * Input parameters: 716 * d - DMA channel to init (context must be previously init'd 717 * 718 * Return value: 719 * nothing 720 ********************************************************************* */ 721 722 static void sbdma_channel_stop(struct sbmacdma *d) 723 { 724 /* 725 * Turn off the DMA channel 726 */ 727 728 __raw_writeq(0, d->sbdma_config1); 729 730 __raw_writeq(0, d->sbdma_dscrbase); 731 732 __raw_writeq(0, d->sbdma_config0); 733 734 /* 735 * Zero ring pointers 736 */ 737 738 d->sbdma_addptr = NULL; 739 d->sbdma_remptr = NULL; 740 } 741 742 static inline void sbdma_align_skb(struct sk_buff *skb, 743 unsigned int power2, unsigned int offset) 744 { 745 unsigned char *addr = skb->data; 746 unsigned char *newaddr = PTR_ALIGN(addr, power2); 747 748 skb_reserve(skb, newaddr - addr + offset); 749 } 750 751 752 /********************************************************************** 753 * SBDMA_ADD_RCVBUFFER(d,sb) 754 * 755 * Add a buffer to the specified DMA channel. For receive channels, 756 * this queues a buffer for inbound packets. 757 * 758 * Input parameters: 759 * sc - softc structure 760 * d - DMA channel descriptor 761 * sb - sk_buff to add, or NULL if we should allocate one 762 * 763 * Return value: 764 * 0 if buffer could not be added (ring is full) 765 * 1 if buffer added successfully 766 ********************************************************************* */ 767 768 769 static int sbdma_add_rcvbuffer(struct sbmac_softc *sc, struct sbmacdma *d, 770 struct sk_buff *sb) 771 { 772 struct net_device *dev = sc->sbm_dev; 773 struct sbdmadscr *dsc; 774 struct sbdmadscr *nextdsc; 775 struct sk_buff *sb_new = NULL; 776 int pktsize = ENET_PACKET_SIZE; 777 778 /* get pointer to our current place in the ring */ 779 780 dsc = d->sbdma_addptr; 781 nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr); 782 783 /* 784 * figure out if the ring is full - if the next descriptor 785 * is the same as the one that we're going to remove from 786 * the ring, the ring is full 787 */ 788 789 if (nextdsc == d->sbdma_remptr) { 790 return -ENOSPC; 791 } 792 793 /* 794 * Allocate a sk_buff if we don't already have one. 795 * If we do have an sk_buff, reset it so that it's empty. 796 * 797 * Note: sk_buffs don't seem to be guaranteed to have any sort 798 * of alignment when they are allocated. Therefore, allocate enough 799 * extra space to make sure that: 800 * 801 * 1. the data does not start in the middle of a cache line. 802 * 2. The data does not end in the middle of a cache line 803 * 3. The buffer can be aligned such that the IP addresses are 804 * naturally aligned. 805 * 806 * Remember, the SOCs MAC writes whole cache lines at a time, 807 * without reading the old contents first. So, if the sk_buff's 808 * data portion starts in the middle of a cache line, the SOC 809 * DMA will trash the beginning (and ending) portions. 810 */ 811 812 if (sb == NULL) { 813 sb_new = netdev_alloc_skb(dev, ENET_PACKET_SIZE + 814 SMP_CACHE_BYTES * 2 + 815 NET_IP_ALIGN); 816 if (sb_new == NULL) 817 return -ENOBUFS; 818 819 sbdma_align_skb(sb_new, SMP_CACHE_BYTES, NET_IP_ALIGN); 820 } 821 else { 822 sb_new = sb; 823 /* 824 * nothing special to reinit buffer, it's already aligned 825 * and sb->data already points to a good place. 826 */ 827 } 828 829 /* 830 * fill in the descriptor 831 */ 832 833 #ifdef CONFIG_SBMAC_COALESCE 834 /* 835 * Do not interrupt per DMA transfer. 836 */ 837 dsc->dscr_a = virt_to_phys(sb_new->data) | 838 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize + NET_IP_ALIGN)) | 0; 839 #else 840 dsc->dscr_a = virt_to_phys(sb_new->data) | 841 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize + NET_IP_ALIGN)) | 842 M_DMA_DSCRA_INTERRUPT; 843 #endif 844 845 /* receiving: no options */ 846 dsc->dscr_b = 0; 847 848 /* 849 * fill in the context 850 */ 851 852 d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb_new; 853 854 /* 855 * point at next packet 856 */ 857 858 d->sbdma_addptr = nextdsc; 859 860 /* 861 * Give the buffer to the DMA engine. 862 */ 863 864 __raw_writeq(1, d->sbdma_dscrcnt); 865 866 return 0; /* we did it */ 867 } 868 869 /********************************************************************** 870 * SBDMA_ADD_TXBUFFER(d,sb) 871 * 872 * Add a transmit buffer to the specified DMA channel, causing a 873 * transmit to start. 874 * 875 * Input parameters: 876 * d - DMA channel descriptor 877 * sb - sk_buff to add 878 * 879 * Return value: 880 * 0 transmit queued successfully 881 * otherwise error code 882 ********************************************************************* */ 883 884 885 static int sbdma_add_txbuffer(struct sbmacdma *d, struct sk_buff *sb) 886 { 887 struct sbdmadscr *dsc; 888 struct sbdmadscr *nextdsc; 889 uint64_t phys; 890 uint64_t ncb; 891 int length; 892 893 /* get pointer to our current place in the ring */ 894 895 dsc = d->sbdma_addptr; 896 nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr); 897 898 /* 899 * figure out if the ring is full - if the next descriptor 900 * is the same as the one that we're going to remove from 901 * the ring, the ring is full 902 */ 903 904 if (nextdsc == d->sbdma_remptr) { 905 return -ENOSPC; 906 } 907 908 /* 909 * Under Linux, it's not necessary to copy/coalesce buffers 910 * like it is on NetBSD. We think they're all contiguous, 911 * but that may not be true for GBE. 912 */ 913 914 length = sb->len; 915 916 /* 917 * fill in the descriptor. Note that the number of cache 918 * blocks in the descriptor is the number of blocks 919 * *spanned*, so we need to add in the offset (if any) 920 * while doing the calculation. 921 */ 922 923 phys = virt_to_phys(sb->data); 924 ncb = NUMCACHEBLKS(length+(phys & (SMP_CACHE_BYTES - 1))); 925 926 dsc->dscr_a = phys | 927 V_DMA_DSCRA_A_SIZE(ncb) | 928 #ifndef CONFIG_SBMAC_COALESCE 929 M_DMA_DSCRA_INTERRUPT | 930 #endif 931 M_DMA_ETHTX_SOP; 932 933 /* transmitting: set outbound options and length */ 934 935 dsc->dscr_b = V_DMA_DSCRB_OPTIONS(K_DMA_ETHTX_APPENDCRC_APPENDPAD) | 936 V_DMA_DSCRB_PKT_SIZE(length); 937 938 /* 939 * fill in the context 940 */ 941 942 d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb; 943 944 /* 945 * point at next packet 946 */ 947 948 d->sbdma_addptr = nextdsc; 949 950 /* 951 * Give the buffer to the DMA engine. 952 */ 953 954 __raw_writeq(1, d->sbdma_dscrcnt); 955 956 return 0; /* we did it */ 957 } 958 959 960 961 962 /********************************************************************** 963 * SBDMA_EMPTYRING(d) 964 * 965 * Free all allocated sk_buffs on the specified DMA channel; 966 * 967 * Input parameters: 968 * d - DMA channel 969 * 970 * Return value: 971 * nothing 972 ********************************************************************* */ 973 974 static void sbdma_emptyring(struct sbmacdma *d) 975 { 976 int idx; 977 struct sk_buff *sb; 978 979 for (idx = 0; idx < d->sbdma_maxdescr; idx++) { 980 sb = d->sbdma_ctxtable[idx]; 981 if (sb) { 982 dev_kfree_skb(sb); 983 d->sbdma_ctxtable[idx] = NULL; 984 } 985 } 986 } 987 988 989 /********************************************************************** 990 * SBDMA_FILLRING(d) 991 * 992 * Fill the specified DMA channel (must be receive channel) 993 * with sk_buffs 994 * 995 * Input parameters: 996 * sc - softc structure 997 * d - DMA channel 998 * 999 * Return value: 1000 * nothing 1001 ********************************************************************* */ 1002 1003 static void sbdma_fillring(struct sbmac_softc *sc, struct sbmacdma *d) 1004 { 1005 int idx; 1006 1007 for (idx = 0; idx < SBMAC_MAX_RXDESCR - 1; idx++) { 1008 if (sbdma_add_rcvbuffer(sc, d, NULL) != 0) 1009 break; 1010 } 1011 } 1012 1013 #ifdef CONFIG_NET_POLL_CONTROLLER 1014 static void sbmac_netpoll(struct net_device *netdev) 1015 { 1016 struct sbmac_softc *sc = netdev_priv(netdev); 1017 int irq = sc->sbm_dev->irq; 1018 1019 __raw_writeq(0, sc->sbm_imr); 1020 1021 sbmac_intr(irq, netdev); 1022 1023 #ifdef CONFIG_SBMAC_COALESCE 1024 __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) | 1025 ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0), 1026 sc->sbm_imr); 1027 #else 1028 __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) | 1029 (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), sc->sbm_imr); 1030 #endif 1031 } 1032 #endif 1033 1034 /********************************************************************** 1035 * SBDMA_RX_PROCESS(sc,d,work_to_do,poll) 1036 * 1037 * Process "completed" receive buffers on the specified DMA channel. 1038 * 1039 * Input parameters: 1040 * sc - softc structure 1041 * d - DMA channel context 1042 * work_to_do - no. of packets to process before enabling interrupt 1043 * again (for NAPI) 1044 * poll - 1: using polling (for NAPI) 1045 * 1046 * Return value: 1047 * nothing 1048 ********************************************************************* */ 1049 1050 static int sbdma_rx_process(struct sbmac_softc *sc, struct sbmacdma *d, 1051 int work_to_do, int poll) 1052 { 1053 struct net_device *dev = sc->sbm_dev; 1054 int curidx; 1055 int hwidx; 1056 struct sbdmadscr *dsc; 1057 struct sk_buff *sb; 1058 int len; 1059 int work_done = 0; 1060 int dropped = 0; 1061 1062 prefetch(d); 1063 1064 again: 1065 /* Check if the HW dropped any frames */ 1066 dev->stats.rx_fifo_errors 1067 += __raw_readq(sc->sbm_rxdma.sbdma_oodpktlost) & 0xffff; 1068 __raw_writeq(0, sc->sbm_rxdma.sbdma_oodpktlost); 1069 1070 while (work_to_do-- > 0) { 1071 /* 1072 * figure out where we are (as an index) and where 1073 * the hardware is (also as an index) 1074 * 1075 * This could be done faster if (for example) the 1076 * descriptor table was page-aligned and contiguous in 1077 * both virtual and physical memory -- you could then 1078 * just compare the low-order bits of the virtual address 1079 * (sbdma_remptr) and the physical address (sbdma_curdscr CSR) 1080 */ 1081 1082 dsc = d->sbdma_remptr; 1083 curidx = dsc - d->sbdma_dscrtable; 1084 1085 prefetch(dsc); 1086 prefetch(&d->sbdma_ctxtable[curidx]); 1087 1088 hwidx = ((__raw_readq(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) - 1089 d->sbdma_dscrtable_phys) / 1090 sizeof(*d->sbdma_dscrtable); 1091 1092 /* 1093 * If they're the same, that means we've processed all 1094 * of the descriptors up to (but not including) the one that 1095 * the hardware is working on right now. 1096 */ 1097 1098 if (curidx == hwidx) 1099 goto done; 1100 1101 /* 1102 * Otherwise, get the packet's sk_buff ptr back 1103 */ 1104 1105 sb = d->sbdma_ctxtable[curidx]; 1106 d->sbdma_ctxtable[curidx] = NULL; 1107 1108 len = (int)G_DMA_DSCRB_PKT_SIZE(dsc->dscr_b) - 4; 1109 1110 /* 1111 * Check packet status. If good, process it. 1112 * If not, silently drop it and put it back on the 1113 * receive ring. 1114 */ 1115 1116 if (likely (!(dsc->dscr_a & M_DMA_ETHRX_BAD))) { 1117 1118 /* 1119 * Add a new buffer to replace the old one. If we fail 1120 * to allocate a buffer, we're going to drop this 1121 * packet and put it right back on the receive ring. 1122 */ 1123 1124 if (unlikely(sbdma_add_rcvbuffer(sc, d, NULL) == 1125 -ENOBUFS)) { 1126 dev->stats.rx_dropped++; 1127 /* Re-add old buffer */ 1128 sbdma_add_rcvbuffer(sc, d, sb); 1129 /* No point in continuing at the moment */ 1130 printk(KERN_ERR "dropped packet (1)\n"); 1131 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr); 1132 goto done; 1133 } else { 1134 /* 1135 * Set length into the packet 1136 */ 1137 skb_put(sb,len); 1138 1139 /* 1140 * Buffer has been replaced on the 1141 * receive ring. Pass the buffer to 1142 * the kernel 1143 */ 1144 sb->protocol = eth_type_trans(sb,d->sbdma_eth->sbm_dev); 1145 /* Check hw IPv4/TCP checksum if supported */ 1146 if (sc->rx_hw_checksum == ENABLE) { 1147 if (!((dsc->dscr_a) & M_DMA_ETHRX_BADIP4CS) && 1148 !((dsc->dscr_a) & M_DMA_ETHRX_BADTCPCS)) { 1149 sb->ip_summed = CHECKSUM_UNNECESSARY; 1150 /* don't need to set sb->csum */ 1151 } else { 1152 skb_checksum_none_assert(sb); 1153 } 1154 } 1155 prefetch(sb->data); 1156 prefetch((const void *)(((char *)sb->data)+32)); 1157 if (poll) 1158 dropped = netif_receive_skb(sb); 1159 else 1160 dropped = netif_rx(sb); 1161 1162 if (dropped == NET_RX_DROP) { 1163 dev->stats.rx_dropped++; 1164 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr); 1165 goto done; 1166 } 1167 else { 1168 dev->stats.rx_bytes += len; 1169 dev->stats.rx_packets++; 1170 } 1171 } 1172 } else { 1173 /* 1174 * Packet was mangled somehow. Just drop it and 1175 * put it back on the receive ring. 1176 */ 1177 dev->stats.rx_errors++; 1178 sbdma_add_rcvbuffer(sc, d, sb); 1179 } 1180 1181 1182 /* 1183 * .. and advance to the next buffer. 1184 */ 1185 1186 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr); 1187 work_done++; 1188 } 1189 if (!poll) { 1190 work_to_do = 32; 1191 goto again; /* collect fifo drop statistics again */ 1192 } 1193 done: 1194 return work_done; 1195 } 1196 1197 /********************************************************************** 1198 * SBDMA_TX_PROCESS(sc,d) 1199 * 1200 * Process "completed" transmit buffers on the specified DMA channel. 1201 * This is normally called within the interrupt service routine. 1202 * Note that this isn't really ideal for priority channels, since 1203 * it processes all of the packets on a given channel before 1204 * returning. 1205 * 1206 * Input parameters: 1207 * sc - softc structure 1208 * d - DMA channel context 1209 * poll - 1: using polling (for NAPI) 1210 * 1211 * Return value: 1212 * nothing 1213 ********************************************************************* */ 1214 1215 static void sbdma_tx_process(struct sbmac_softc *sc, struct sbmacdma *d, 1216 int poll) 1217 { 1218 struct net_device *dev = sc->sbm_dev; 1219 int curidx; 1220 int hwidx; 1221 struct sbdmadscr *dsc; 1222 struct sk_buff *sb; 1223 unsigned long flags; 1224 int packets_handled = 0; 1225 1226 spin_lock_irqsave(&(sc->sbm_lock), flags); 1227 1228 if (d->sbdma_remptr == d->sbdma_addptr) 1229 goto end_unlock; 1230 1231 hwidx = ((__raw_readq(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) - 1232 d->sbdma_dscrtable_phys) / sizeof(*d->sbdma_dscrtable); 1233 1234 for (;;) { 1235 /* 1236 * figure out where we are (as an index) and where 1237 * the hardware is (also as an index) 1238 * 1239 * This could be done faster if (for example) the 1240 * descriptor table was page-aligned and contiguous in 1241 * both virtual and physical memory -- you could then 1242 * just compare the low-order bits of the virtual address 1243 * (sbdma_remptr) and the physical address (sbdma_curdscr CSR) 1244 */ 1245 1246 curidx = d->sbdma_remptr - d->sbdma_dscrtable; 1247 1248 /* 1249 * If they're the same, that means we've processed all 1250 * of the descriptors up to (but not including) the one that 1251 * the hardware is working on right now. 1252 */ 1253 1254 if (curidx == hwidx) 1255 break; 1256 1257 /* 1258 * Otherwise, get the packet's sk_buff ptr back 1259 */ 1260 1261 dsc = &(d->sbdma_dscrtable[curidx]); 1262 sb = d->sbdma_ctxtable[curidx]; 1263 d->sbdma_ctxtable[curidx] = NULL; 1264 1265 /* 1266 * Stats 1267 */ 1268 1269 dev->stats.tx_bytes += sb->len; 1270 dev->stats.tx_packets++; 1271 1272 /* 1273 * for transmits, we just free buffers. 1274 */ 1275 1276 dev_consume_skb_irq(sb); 1277 1278 /* 1279 * .. and advance to the next buffer. 1280 */ 1281 1282 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr); 1283 1284 packets_handled++; 1285 1286 } 1287 1288 /* 1289 * Decide if we should wake up the protocol or not. 1290 * Other drivers seem to do this when we reach a low 1291 * watermark on the transmit queue. 1292 */ 1293 1294 if (packets_handled) 1295 netif_wake_queue(d->sbdma_eth->sbm_dev); 1296 1297 end_unlock: 1298 spin_unlock_irqrestore(&(sc->sbm_lock), flags); 1299 1300 } 1301 1302 1303 1304 /********************************************************************** 1305 * SBMAC_INITCTX(s) 1306 * 1307 * Initialize an Ethernet context structure - this is called 1308 * once per MAC on the 1250. Memory is allocated here, so don't 1309 * call it again from inside the ioctl routines that bring the 1310 * interface up/down 1311 * 1312 * Input parameters: 1313 * s - sbmac context structure 1314 * 1315 * Return value: 1316 * 0 1317 ********************************************************************* */ 1318 1319 static int sbmac_initctx(struct sbmac_softc *s) 1320 { 1321 1322 /* 1323 * figure out the addresses of some ports 1324 */ 1325 1326 s->sbm_macenable = s->sbm_base + R_MAC_ENABLE; 1327 s->sbm_maccfg = s->sbm_base + R_MAC_CFG; 1328 s->sbm_fifocfg = s->sbm_base + R_MAC_THRSH_CFG; 1329 s->sbm_framecfg = s->sbm_base + R_MAC_FRAMECFG; 1330 s->sbm_rxfilter = s->sbm_base + R_MAC_ADFILTER_CFG; 1331 s->sbm_isr = s->sbm_base + R_MAC_STATUS; 1332 s->sbm_imr = s->sbm_base + R_MAC_INT_MASK; 1333 s->sbm_mdio = s->sbm_base + R_MAC_MDIO; 1334 1335 /* 1336 * Initialize the DMA channels. Right now, only one per MAC is used 1337 * Note: Only do this _once_, as it allocates memory from the kernel! 1338 */ 1339 1340 sbdma_initctx(&(s->sbm_txdma),s,0,DMA_TX,SBMAC_MAX_TXDESCR); 1341 sbdma_initctx(&(s->sbm_rxdma),s,0,DMA_RX,SBMAC_MAX_RXDESCR); 1342 1343 /* 1344 * initial state is OFF 1345 */ 1346 1347 s->sbm_state = sbmac_state_off; 1348 1349 return 0; 1350 } 1351 1352 1353 static void sbdma_uninitctx(struct sbmacdma *d) 1354 { 1355 kfree(d->sbdma_dscrtable_unaligned); 1356 d->sbdma_dscrtable_unaligned = d->sbdma_dscrtable = NULL; 1357 1358 kfree(d->sbdma_ctxtable); 1359 d->sbdma_ctxtable = NULL; 1360 } 1361 1362 1363 static void sbmac_uninitctx(struct sbmac_softc *sc) 1364 { 1365 sbdma_uninitctx(&(sc->sbm_txdma)); 1366 sbdma_uninitctx(&(sc->sbm_rxdma)); 1367 } 1368 1369 1370 /********************************************************************** 1371 * SBMAC_CHANNEL_START(s) 1372 * 1373 * Start packet processing on this MAC. 1374 * 1375 * Input parameters: 1376 * s - sbmac structure 1377 * 1378 * Return value: 1379 * nothing 1380 ********************************************************************* */ 1381 1382 static void sbmac_channel_start(struct sbmac_softc *s) 1383 { 1384 uint64_t reg; 1385 void __iomem *port; 1386 uint64_t cfg,fifo,framecfg; 1387 int idx, th_value; 1388 1389 /* 1390 * Don't do this if running 1391 */ 1392 1393 if (s->sbm_state == sbmac_state_on) 1394 return; 1395 1396 /* 1397 * Bring the controller out of reset, but leave it off. 1398 */ 1399 1400 __raw_writeq(0, s->sbm_macenable); 1401 1402 /* 1403 * Ignore all received packets 1404 */ 1405 1406 __raw_writeq(0, s->sbm_rxfilter); 1407 1408 /* 1409 * Calculate values for various control registers. 1410 */ 1411 1412 cfg = M_MAC_RETRY_EN | 1413 M_MAC_TX_HOLD_SOP_EN | 1414 V_MAC_TX_PAUSE_CNT_16K | 1415 M_MAC_AP_STAT_EN | 1416 M_MAC_FAST_SYNC | 1417 M_MAC_SS_EN | 1418 0; 1419 1420 /* 1421 * Be sure that RD_THRSH+WR_THRSH <= 32 for pass1 pars 1422 * and make sure that RD_THRSH + WR_THRSH <=128 for pass2 and above 1423 * Use a larger RD_THRSH for gigabit 1424 */ 1425 if (soc_type == K_SYS_SOC_TYPE_BCM1250 && periph_rev < 2) 1426 th_value = 28; 1427 else 1428 th_value = 64; 1429 1430 fifo = V_MAC_TX_WR_THRSH(4) | /* Must be '4' or '8' */ 1431 ((s->sbm_speed == sbmac_speed_1000) 1432 ? V_MAC_TX_RD_THRSH(th_value) : V_MAC_TX_RD_THRSH(4)) | 1433 V_MAC_TX_RL_THRSH(4) | 1434 V_MAC_RX_PL_THRSH(4) | 1435 V_MAC_RX_RD_THRSH(4) | /* Must be '4' */ 1436 V_MAC_RX_RL_THRSH(8) | 1437 0; 1438 1439 framecfg = V_MAC_MIN_FRAMESZ_DEFAULT | 1440 V_MAC_MAX_FRAMESZ_DEFAULT | 1441 V_MAC_BACKOFF_SEL(1); 1442 1443 /* 1444 * Clear out the hash address map 1445 */ 1446 1447 port = s->sbm_base + R_MAC_HASH_BASE; 1448 for (idx = 0; idx < MAC_HASH_COUNT; idx++) { 1449 __raw_writeq(0, port); 1450 port += sizeof(uint64_t); 1451 } 1452 1453 /* 1454 * Clear out the exact-match table 1455 */ 1456 1457 port = s->sbm_base + R_MAC_ADDR_BASE; 1458 for (idx = 0; idx < MAC_ADDR_COUNT; idx++) { 1459 __raw_writeq(0, port); 1460 port += sizeof(uint64_t); 1461 } 1462 1463 /* 1464 * Clear out the DMA Channel mapping table registers 1465 */ 1466 1467 port = s->sbm_base + R_MAC_CHUP0_BASE; 1468 for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) { 1469 __raw_writeq(0, port); 1470 port += sizeof(uint64_t); 1471 } 1472 1473 1474 port = s->sbm_base + R_MAC_CHLO0_BASE; 1475 for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) { 1476 __raw_writeq(0, port); 1477 port += sizeof(uint64_t); 1478 } 1479 1480 /* 1481 * Program the hardware address. It goes into the hardware-address 1482 * register as well as the first filter register. 1483 */ 1484 1485 reg = sbmac_addr2reg(s->sbm_hwaddr); 1486 1487 port = s->sbm_base + R_MAC_ADDR_BASE; 1488 __raw_writeq(reg, port); 1489 port = s->sbm_base + R_MAC_ETHERNET_ADDR; 1490 1491 __raw_writeq(reg, port); 1492 1493 /* 1494 * Set the receive filter for no packets, and write values 1495 * to the various config registers 1496 */ 1497 1498 __raw_writeq(0, s->sbm_rxfilter); 1499 __raw_writeq(0, s->sbm_imr); 1500 __raw_writeq(framecfg, s->sbm_framecfg); 1501 __raw_writeq(fifo, s->sbm_fifocfg); 1502 __raw_writeq(cfg, s->sbm_maccfg); 1503 1504 /* 1505 * Initialize DMA channels (rings should be ok now) 1506 */ 1507 1508 sbdma_channel_start(&(s->sbm_rxdma), DMA_RX); 1509 sbdma_channel_start(&(s->sbm_txdma), DMA_TX); 1510 1511 /* 1512 * Configure the speed, duplex, and flow control 1513 */ 1514 1515 sbmac_set_speed(s,s->sbm_speed); 1516 sbmac_set_duplex(s,s->sbm_duplex,s->sbm_fc); 1517 1518 /* 1519 * Fill the receive ring 1520 */ 1521 1522 sbdma_fillring(s, &(s->sbm_rxdma)); 1523 1524 /* 1525 * Turn on the rest of the bits in the enable register 1526 */ 1527 1528 #if defined(CONFIG_SIBYTE_BCM1x80) 1529 __raw_writeq(M_MAC_RXDMA_EN0 | 1530 M_MAC_TXDMA_EN0, s->sbm_macenable); 1531 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X) 1532 __raw_writeq(M_MAC_RXDMA_EN0 | 1533 M_MAC_TXDMA_EN0 | 1534 M_MAC_RX_ENABLE | 1535 M_MAC_TX_ENABLE, s->sbm_macenable); 1536 #else 1537 #error invalid SiByte MAC configuration 1538 #endif 1539 1540 #ifdef CONFIG_SBMAC_COALESCE 1541 __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) | 1542 ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0), s->sbm_imr); 1543 #else 1544 __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) | 1545 (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), s->sbm_imr); 1546 #endif 1547 1548 /* 1549 * Enable receiving unicasts and broadcasts 1550 */ 1551 1552 __raw_writeq(M_MAC_UCAST_EN | M_MAC_BCAST_EN, s->sbm_rxfilter); 1553 1554 /* 1555 * we're running now. 1556 */ 1557 1558 s->sbm_state = sbmac_state_on; 1559 1560 /* 1561 * Program multicast addresses 1562 */ 1563 1564 sbmac_setmulti(s); 1565 1566 /* 1567 * If channel was in promiscuous mode before, turn that on 1568 */ 1569 1570 if (s->sbm_devflags & IFF_PROMISC) { 1571 sbmac_promiscuous_mode(s,1); 1572 } 1573 1574 } 1575 1576 1577 /********************************************************************** 1578 * SBMAC_CHANNEL_STOP(s) 1579 * 1580 * Stop packet processing on this MAC. 1581 * 1582 * Input parameters: 1583 * s - sbmac structure 1584 * 1585 * Return value: 1586 * nothing 1587 ********************************************************************* */ 1588 1589 static void sbmac_channel_stop(struct sbmac_softc *s) 1590 { 1591 /* don't do this if already stopped */ 1592 1593 if (s->sbm_state == sbmac_state_off) 1594 return; 1595 1596 /* don't accept any packets, disable all interrupts */ 1597 1598 __raw_writeq(0, s->sbm_rxfilter); 1599 __raw_writeq(0, s->sbm_imr); 1600 1601 /* Turn off ticker */ 1602 1603 /* XXX */ 1604 1605 /* turn off receiver and transmitter */ 1606 1607 __raw_writeq(0, s->sbm_macenable); 1608 1609 /* We're stopped now. */ 1610 1611 s->sbm_state = sbmac_state_off; 1612 1613 /* 1614 * Stop DMA channels (rings should be ok now) 1615 */ 1616 1617 sbdma_channel_stop(&(s->sbm_rxdma)); 1618 sbdma_channel_stop(&(s->sbm_txdma)); 1619 1620 /* Empty the receive and transmit rings */ 1621 1622 sbdma_emptyring(&(s->sbm_rxdma)); 1623 sbdma_emptyring(&(s->sbm_txdma)); 1624 1625 } 1626 1627 /********************************************************************** 1628 * SBMAC_SET_CHANNEL_STATE(state) 1629 * 1630 * Set the channel's state ON or OFF 1631 * 1632 * Input parameters: 1633 * state - new state 1634 * 1635 * Return value: 1636 * old state 1637 ********************************************************************* */ 1638 static enum sbmac_state sbmac_set_channel_state(struct sbmac_softc *sc, 1639 enum sbmac_state state) 1640 { 1641 enum sbmac_state oldstate = sc->sbm_state; 1642 1643 /* 1644 * If same as previous state, return 1645 */ 1646 1647 if (state == oldstate) { 1648 return oldstate; 1649 } 1650 1651 /* 1652 * If new state is ON, turn channel on 1653 */ 1654 1655 if (state == sbmac_state_on) { 1656 sbmac_channel_start(sc); 1657 } 1658 else { 1659 sbmac_channel_stop(sc); 1660 } 1661 1662 /* 1663 * Return previous state 1664 */ 1665 1666 return oldstate; 1667 } 1668 1669 1670 /********************************************************************** 1671 * SBMAC_PROMISCUOUS_MODE(sc,onoff) 1672 * 1673 * Turn on or off promiscuous mode 1674 * 1675 * Input parameters: 1676 * sc - softc 1677 * onoff - 1 to turn on, 0 to turn off 1678 * 1679 * Return value: 1680 * nothing 1681 ********************************************************************* */ 1682 1683 static void sbmac_promiscuous_mode(struct sbmac_softc *sc,int onoff) 1684 { 1685 uint64_t reg; 1686 1687 if (sc->sbm_state != sbmac_state_on) 1688 return; 1689 1690 if (onoff) { 1691 reg = __raw_readq(sc->sbm_rxfilter); 1692 reg |= M_MAC_ALLPKT_EN; 1693 __raw_writeq(reg, sc->sbm_rxfilter); 1694 } 1695 else { 1696 reg = __raw_readq(sc->sbm_rxfilter); 1697 reg &= ~M_MAC_ALLPKT_EN; 1698 __raw_writeq(reg, sc->sbm_rxfilter); 1699 } 1700 } 1701 1702 /********************************************************************** 1703 * SBMAC_SETIPHDR_OFFSET(sc,onoff) 1704 * 1705 * Set the iphdr offset as 15 assuming ethernet encapsulation 1706 * 1707 * Input parameters: 1708 * sc - softc 1709 * 1710 * Return value: 1711 * nothing 1712 ********************************************************************* */ 1713 1714 static void sbmac_set_iphdr_offset(struct sbmac_softc *sc) 1715 { 1716 uint64_t reg; 1717 1718 /* Hard code the off set to 15 for now */ 1719 reg = __raw_readq(sc->sbm_rxfilter); 1720 reg &= ~M_MAC_IPHDR_OFFSET | V_MAC_IPHDR_OFFSET(15); 1721 __raw_writeq(reg, sc->sbm_rxfilter); 1722 1723 /* BCM1250 pass1 didn't have hardware checksum. Everything 1724 later does. */ 1725 if (soc_type == K_SYS_SOC_TYPE_BCM1250 && periph_rev < 2) { 1726 sc->rx_hw_checksum = DISABLE; 1727 } else { 1728 sc->rx_hw_checksum = ENABLE; 1729 } 1730 } 1731 1732 1733 /********************************************************************** 1734 * SBMAC_ADDR2REG(ptr) 1735 * 1736 * Convert six bytes into the 64-bit register value that 1737 * we typically write into the SBMAC's address/mcast registers 1738 * 1739 * Input parameters: 1740 * ptr - pointer to 6 bytes 1741 * 1742 * Return value: 1743 * register value 1744 ********************************************************************* */ 1745 1746 static uint64_t sbmac_addr2reg(unsigned char *ptr) 1747 { 1748 uint64_t reg = 0; 1749 1750 ptr += 6; 1751 1752 reg |= (uint64_t) *(--ptr); 1753 reg <<= 8; 1754 reg |= (uint64_t) *(--ptr); 1755 reg <<= 8; 1756 reg |= (uint64_t) *(--ptr); 1757 reg <<= 8; 1758 reg |= (uint64_t) *(--ptr); 1759 reg <<= 8; 1760 reg |= (uint64_t) *(--ptr); 1761 reg <<= 8; 1762 reg |= (uint64_t) *(--ptr); 1763 1764 return reg; 1765 } 1766 1767 1768 /********************************************************************** 1769 * SBMAC_SET_SPEED(s,speed) 1770 * 1771 * Configure LAN speed for the specified MAC. 1772 * Warning: must be called when MAC is off! 1773 * 1774 * Input parameters: 1775 * s - sbmac structure 1776 * speed - speed to set MAC to (see enum sbmac_speed) 1777 * 1778 * Return value: 1779 * 1 if successful 1780 * 0 indicates invalid parameters 1781 ********************************************************************* */ 1782 1783 static int sbmac_set_speed(struct sbmac_softc *s, enum sbmac_speed speed) 1784 { 1785 uint64_t cfg; 1786 uint64_t framecfg; 1787 1788 /* 1789 * Save new current values 1790 */ 1791 1792 s->sbm_speed = speed; 1793 1794 if (s->sbm_state == sbmac_state_on) 1795 return 0; /* save for next restart */ 1796 1797 /* 1798 * Read current register values 1799 */ 1800 1801 cfg = __raw_readq(s->sbm_maccfg); 1802 framecfg = __raw_readq(s->sbm_framecfg); 1803 1804 /* 1805 * Mask out the stuff we want to change 1806 */ 1807 1808 cfg &= ~(M_MAC_BURST_EN | M_MAC_SPEED_SEL); 1809 framecfg &= ~(M_MAC_IFG_RX | M_MAC_IFG_TX | M_MAC_IFG_THRSH | 1810 M_MAC_SLOT_SIZE); 1811 1812 /* 1813 * Now add in the new bits 1814 */ 1815 1816 switch (speed) { 1817 case sbmac_speed_10: 1818 framecfg |= V_MAC_IFG_RX_10 | 1819 V_MAC_IFG_TX_10 | 1820 K_MAC_IFG_THRSH_10 | 1821 V_MAC_SLOT_SIZE_10; 1822 cfg |= V_MAC_SPEED_SEL_10MBPS; 1823 break; 1824 1825 case sbmac_speed_100: 1826 framecfg |= V_MAC_IFG_RX_100 | 1827 V_MAC_IFG_TX_100 | 1828 V_MAC_IFG_THRSH_100 | 1829 V_MAC_SLOT_SIZE_100; 1830 cfg |= V_MAC_SPEED_SEL_100MBPS ; 1831 break; 1832 1833 case sbmac_speed_1000: 1834 framecfg |= V_MAC_IFG_RX_1000 | 1835 V_MAC_IFG_TX_1000 | 1836 V_MAC_IFG_THRSH_1000 | 1837 V_MAC_SLOT_SIZE_1000; 1838 cfg |= V_MAC_SPEED_SEL_1000MBPS | M_MAC_BURST_EN; 1839 break; 1840 1841 default: 1842 return 0; 1843 } 1844 1845 /* 1846 * Send the bits back to the hardware 1847 */ 1848 1849 __raw_writeq(framecfg, s->sbm_framecfg); 1850 __raw_writeq(cfg, s->sbm_maccfg); 1851 1852 return 1; 1853 } 1854 1855 /********************************************************************** 1856 * SBMAC_SET_DUPLEX(s,duplex,fc) 1857 * 1858 * Set Ethernet duplex and flow control options for this MAC 1859 * Warning: must be called when MAC is off! 1860 * 1861 * Input parameters: 1862 * s - sbmac structure 1863 * duplex - duplex setting (see enum sbmac_duplex) 1864 * fc - flow control setting (see enum sbmac_fc) 1865 * 1866 * Return value: 1867 * 1 if ok 1868 * 0 if an invalid parameter combination was specified 1869 ********************************************************************* */ 1870 1871 static int sbmac_set_duplex(struct sbmac_softc *s, enum sbmac_duplex duplex, 1872 enum sbmac_fc fc) 1873 { 1874 uint64_t cfg; 1875 1876 /* 1877 * Save new current values 1878 */ 1879 1880 s->sbm_duplex = duplex; 1881 s->sbm_fc = fc; 1882 1883 if (s->sbm_state == sbmac_state_on) 1884 return 0; /* save for next restart */ 1885 1886 /* 1887 * Read current register values 1888 */ 1889 1890 cfg = __raw_readq(s->sbm_maccfg); 1891 1892 /* 1893 * Mask off the stuff we're about to change 1894 */ 1895 1896 cfg &= ~(M_MAC_FC_SEL | M_MAC_FC_CMD | M_MAC_HDX_EN); 1897 1898 1899 switch (duplex) { 1900 case sbmac_duplex_half: 1901 switch (fc) { 1902 case sbmac_fc_disabled: 1903 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_DISABLED; 1904 break; 1905 1906 case sbmac_fc_collision: 1907 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENABLED; 1908 break; 1909 1910 case sbmac_fc_carrier: 1911 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENAB_FALSECARR; 1912 break; 1913 1914 case sbmac_fc_frame: /* not valid in half duplex */ 1915 default: /* invalid selection */ 1916 return 0; 1917 } 1918 break; 1919 1920 case sbmac_duplex_full: 1921 switch (fc) { 1922 case sbmac_fc_disabled: 1923 cfg |= V_MAC_FC_CMD_DISABLED; 1924 break; 1925 1926 case sbmac_fc_frame: 1927 cfg |= V_MAC_FC_CMD_ENABLED; 1928 break; 1929 1930 case sbmac_fc_collision: /* not valid in full duplex */ 1931 case sbmac_fc_carrier: /* not valid in full duplex */ 1932 default: 1933 return 0; 1934 } 1935 break; 1936 default: 1937 return 0; 1938 } 1939 1940 /* 1941 * Send the bits back to the hardware 1942 */ 1943 1944 __raw_writeq(cfg, s->sbm_maccfg); 1945 1946 return 1; 1947 } 1948 1949 1950 1951 1952 /********************************************************************** 1953 * SBMAC_INTR() 1954 * 1955 * Interrupt handler for MAC interrupts 1956 * 1957 * Input parameters: 1958 * MAC structure 1959 * 1960 * Return value: 1961 * nothing 1962 ********************************************************************* */ 1963 static irqreturn_t sbmac_intr(int irq,void *dev_instance) 1964 { 1965 struct net_device *dev = (struct net_device *) dev_instance; 1966 struct sbmac_softc *sc = netdev_priv(dev); 1967 uint64_t isr; 1968 int handled = 0; 1969 1970 /* 1971 * Read the ISR (this clears the bits in the real 1972 * register, except for counter addr) 1973 */ 1974 1975 isr = __raw_readq(sc->sbm_isr) & ~M_MAC_COUNTER_ADDR; 1976 1977 if (isr == 0) 1978 return IRQ_RETVAL(0); 1979 handled = 1; 1980 1981 /* 1982 * Transmits on channel 0 1983 */ 1984 1985 if (isr & (M_MAC_INT_CHANNEL << S_MAC_TX_CH0)) 1986 sbdma_tx_process(sc,&(sc->sbm_txdma), 0); 1987 1988 if (isr & (M_MAC_INT_CHANNEL << S_MAC_RX_CH0)) { 1989 if (napi_schedule_prep(&sc->napi)) { 1990 __raw_writeq(0, sc->sbm_imr); 1991 __napi_schedule(&sc->napi); 1992 /* Depend on the exit from poll to reenable intr */ 1993 } 1994 else { 1995 /* may leave some packets behind */ 1996 sbdma_rx_process(sc,&(sc->sbm_rxdma), 1997 SBMAC_MAX_RXDESCR * 2, 0); 1998 } 1999 } 2000 return IRQ_RETVAL(handled); 2001 } 2002 2003 /********************************************************************** 2004 * SBMAC_START_TX(skb,dev) 2005 * 2006 * Start output on the specified interface. Basically, we 2007 * queue as many buffers as we can until the ring fills up, or 2008 * we run off the end of the queue, whichever comes first. 2009 * 2010 * Input parameters: 2011 * 2012 * 2013 * Return value: 2014 * nothing 2015 ********************************************************************* */ 2016 static netdev_tx_t sbmac_start_tx(struct sk_buff *skb, struct net_device *dev) 2017 { 2018 struct sbmac_softc *sc = netdev_priv(dev); 2019 unsigned long flags; 2020 2021 /* lock eth irq */ 2022 spin_lock_irqsave(&sc->sbm_lock, flags); 2023 2024 /* 2025 * Put the buffer on the transmit ring. If we 2026 * don't have room, stop the queue. 2027 */ 2028 2029 if (sbdma_add_txbuffer(&(sc->sbm_txdma),skb)) { 2030 /* XXX save skb that we could not send */ 2031 netif_stop_queue(dev); 2032 spin_unlock_irqrestore(&sc->sbm_lock, flags); 2033 2034 return NETDEV_TX_BUSY; 2035 } 2036 2037 spin_unlock_irqrestore(&sc->sbm_lock, flags); 2038 2039 return NETDEV_TX_OK; 2040 } 2041 2042 /********************************************************************** 2043 * SBMAC_SETMULTI(sc) 2044 * 2045 * Reprogram the multicast table into the hardware, given 2046 * the list of multicasts associated with the interface 2047 * structure. 2048 * 2049 * Input parameters: 2050 * sc - softc 2051 * 2052 * Return value: 2053 * nothing 2054 ********************************************************************* */ 2055 2056 static void sbmac_setmulti(struct sbmac_softc *sc) 2057 { 2058 uint64_t reg; 2059 void __iomem *port; 2060 int idx; 2061 struct netdev_hw_addr *ha; 2062 struct net_device *dev = sc->sbm_dev; 2063 2064 /* 2065 * Clear out entire multicast table. We do this by nuking 2066 * the entire hash table and all the direct matches except 2067 * the first one, which is used for our station address 2068 */ 2069 2070 for (idx = 1; idx < MAC_ADDR_COUNT; idx++) { 2071 port = sc->sbm_base + R_MAC_ADDR_BASE+(idx*sizeof(uint64_t)); 2072 __raw_writeq(0, port); 2073 } 2074 2075 for (idx = 0; idx < MAC_HASH_COUNT; idx++) { 2076 port = sc->sbm_base + R_MAC_HASH_BASE+(idx*sizeof(uint64_t)); 2077 __raw_writeq(0, port); 2078 } 2079 2080 /* 2081 * Clear the filter to say we don't want any multicasts. 2082 */ 2083 2084 reg = __raw_readq(sc->sbm_rxfilter); 2085 reg &= ~(M_MAC_MCAST_INV | M_MAC_MCAST_EN); 2086 __raw_writeq(reg, sc->sbm_rxfilter); 2087 2088 if (dev->flags & IFF_ALLMULTI) { 2089 /* 2090 * Enable ALL multicasts. Do this by inverting the 2091 * multicast enable bit. 2092 */ 2093 reg = __raw_readq(sc->sbm_rxfilter); 2094 reg |= (M_MAC_MCAST_INV | M_MAC_MCAST_EN); 2095 __raw_writeq(reg, sc->sbm_rxfilter); 2096 return; 2097 } 2098 2099 2100 /* 2101 * Progam new multicast entries. For now, only use the 2102 * perfect filter. In the future we'll need to use the 2103 * hash filter if the perfect filter overflows 2104 */ 2105 2106 /* XXX only using perfect filter for now, need to use hash 2107 * XXX if the table overflows */ 2108 2109 idx = 1; /* skip station address */ 2110 netdev_for_each_mc_addr(ha, dev) { 2111 if (idx == MAC_ADDR_COUNT) 2112 break; 2113 reg = sbmac_addr2reg(ha->addr); 2114 port = sc->sbm_base + R_MAC_ADDR_BASE+(idx * sizeof(uint64_t)); 2115 __raw_writeq(reg, port); 2116 idx++; 2117 } 2118 2119 /* 2120 * Enable the "accept multicast bits" if we programmed at least one 2121 * multicast. 2122 */ 2123 2124 if (idx > 1) { 2125 reg = __raw_readq(sc->sbm_rxfilter); 2126 reg |= M_MAC_MCAST_EN; 2127 __raw_writeq(reg, sc->sbm_rxfilter); 2128 } 2129 } 2130 2131 static const struct net_device_ops sbmac_netdev_ops = { 2132 .ndo_open = sbmac_open, 2133 .ndo_stop = sbmac_close, 2134 .ndo_start_xmit = sbmac_start_tx, 2135 .ndo_set_rx_mode = sbmac_set_rx_mode, 2136 .ndo_tx_timeout = sbmac_tx_timeout, 2137 .ndo_eth_ioctl = sbmac_mii_ioctl, 2138 .ndo_validate_addr = eth_validate_addr, 2139 .ndo_set_mac_address = eth_mac_addr, 2140 #ifdef CONFIG_NET_POLL_CONTROLLER 2141 .ndo_poll_controller = sbmac_netpoll, 2142 #endif 2143 }; 2144 2145 /********************************************************************** 2146 * SBMAC_INIT(dev) 2147 * 2148 * Attach routine - init hardware and hook ourselves into linux 2149 * 2150 * Input parameters: 2151 * dev - net_device structure 2152 * 2153 * Return value: 2154 * status 2155 ********************************************************************* */ 2156 2157 static int sbmac_init(struct platform_device *pldev, long long base) 2158 { 2159 struct net_device *dev = platform_get_drvdata(pldev); 2160 int idx = pldev->id; 2161 struct sbmac_softc *sc = netdev_priv(dev); 2162 unsigned char *eaddr; 2163 uint64_t ea_reg; 2164 int i; 2165 int err; 2166 2167 sc->sbm_dev = dev; 2168 sc->sbe_idx = idx; 2169 2170 eaddr = sc->sbm_hwaddr; 2171 2172 /* 2173 * Read the ethernet address. The firmware left this programmed 2174 * for us in the ethernet address register for each mac. 2175 */ 2176 2177 ea_reg = __raw_readq(sc->sbm_base + R_MAC_ETHERNET_ADDR); 2178 __raw_writeq(0, sc->sbm_base + R_MAC_ETHERNET_ADDR); 2179 for (i = 0; i < 6; i++) { 2180 eaddr[i] = (uint8_t) (ea_reg & 0xFF); 2181 ea_reg >>= 8; 2182 } 2183 2184 eth_hw_addr_set(dev, eaddr); 2185 2186 /* 2187 * Initialize context (get pointers to registers and stuff), then 2188 * allocate the memory for the descriptor tables. 2189 */ 2190 2191 sbmac_initctx(sc); 2192 2193 /* 2194 * Set up Linux device callins 2195 */ 2196 2197 spin_lock_init(&(sc->sbm_lock)); 2198 2199 dev->netdev_ops = &sbmac_netdev_ops; 2200 dev->watchdog_timeo = TX_TIMEOUT; 2201 dev->min_mtu = 0; 2202 dev->max_mtu = ENET_PACKET_SIZE; 2203 2204 netif_napi_add_weight(dev, &sc->napi, sbmac_poll, 16); 2205 2206 dev->irq = UNIT_INT(idx); 2207 2208 /* This is needed for PASS2 for Rx H/W checksum feature */ 2209 sbmac_set_iphdr_offset(sc); 2210 2211 sc->mii_bus = mdiobus_alloc(); 2212 if (sc->mii_bus == NULL) { 2213 err = -ENOMEM; 2214 goto uninit_ctx; 2215 } 2216 2217 sc->mii_bus->name = sbmac_mdio_string; 2218 snprintf(sc->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2219 pldev->name, idx); 2220 sc->mii_bus->priv = sc; 2221 sc->mii_bus->read = sbmac_mii_read; 2222 sc->mii_bus->write = sbmac_mii_write; 2223 2224 sc->mii_bus->parent = &pldev->dev; 2225 /* 2226 * Probe PHY address 2227 */ 2228 err = mdiobus_register(sc->mii_bus); 2229 if (err) { 2230 printk(KERN_ERR "%s: unable to register MDIO bus\n", 2231 dev->name); 2232 goto free_mdio; 2233 } 2234 platform_set_drvdata(pldev, sc->mii_bus); 2235 2236 err = register_netdev(dev); 2237 if (err) { 2238 printk(KERN_ERR "%s.%d: unable to register netdev\n", 2239 sbmac_string, idx); 2240 goto unreg_mdio; 2241 } 2242 2243 pr_info("%s.%d: registered as %s\n", sbmac_string, idx, dev->name); 2244 2245 if (sc->rx_hw_checksum == ENABLE) 2246 pr_info("%s: enabling TCP rcv checksum\n", dev->name); 2247 2248 /* 2249 * Display Ethernet address (this is called during the config 2250 * process so we need to finish off the config message that 2251 * was being displayed) 2252 */ 2253 pr_info("%s: SiByte Ethernet at 0x%08Lx, address: %pM\n", 2254 dev->name, base, eaddr); 2255 2256 return 0; 2257 unreg_mdio: 2258 mdiobus_unregister(sc->mii_bus); 2259 free_mdio: 2260 mdiobus_free(sc->mii_bus); 2261 uninit_ctx: 2262 sbmac_uninitctx(sc); 2263 return err; 2264 } 2265 2266 2267 static int sbmac_open(struct net_device *dev) 2268 { 2269 struct sbmac_softc *sc = netdev_priv(dev); 2270 int err; 2271 2272 if (debug > 1) 2273 pr_debug("%s: sbmac_open() irq %d.\n", dev->name, dev->irq); 2274 2275 /* 2276 * map/route interrupt (clear status first, in case something 2277 * weird is pending; we haven't initialized the mac registers 2278 * yet) 2279 */ 2280 2281 __raw_readq(sc->sbm_isr); 2282 err = request_irq(dev->irq, sbmac_intr, IRQF_SHARED, dev->name, dev); 2283 if (err) { 2284 printk(KERN_ERR "%s: unable to get IRQ %d\n", dev->name, 2285 dev->irq); 2286 goto out_err; 2287 } 2288 2289 sc->sbm_speed = sbmac_speed_none; 2290 sc->sbm_duplex = sbmac_duplex_none; 2291 sc->sbm_fc = sbmac_fc_none; 2292 sc->sbm_pause = -1; 2293 sc->sbm_link = 0; 2294 2295 /* 2296 * Attach to the PHY 2297 */ 2298 err = sbmac_mii_probe(dev); 2299 if (err) 2300 goto out_unregister; 2301 2302 /* 2303 * Turn on the channel 2304 */ 2305 2306 sbmac_set_channel_state(sc,sbmac_state_on); 2307 2308 netif_start_queue(dev); 2309 2310 sbmac_set_rx_mode(dev); 2311 2312 phy_start(sc->phy_dev); 2313 2314 napi_enable(&sc->napi); 2315 2316 return 0; 2317 2318 out_unregister: 2319 free_irq(dev->irq, dev); 2320 out_err: 2321 return err; 2322 } 2323 2324 static int sbmac_mii_probe(struct net_device *dev) 2325 { 2326 struct sbmac_softc *sc = netdev_priv(dev); 2327 struct phy_device *phy_dev; 2328 2329 phy_dev = phy_find_first(sc->mii_bus); 2330 if (!phy_dev) { 2331 printk(KERN_ERR "%s: no PHY found\n", dev->name); 2332 return -ENXIO; 2333 } 2334 2335 phy_dev = phy_connect(dev, dev_name(&phy_dev->mdio.dev), 2336 &sbmac_mii_poll, PHY_INTERFACE_MODE_GMII); 2337 if (IS_ERR(phy_dev)) { 2338 printk(KERN_ERR "%s: could not attach to PHY\n", dev->name); 2339 return PTR_ERR(phy_dev); 2340 } 2341 2342 /* Remove any features not supported by the controller */ 2343 phy_set_max_speed(phy_dev, SPEED_1000); 2344 phy_support_asym_pause(phy_dev); 2345 2346 phy_attached_info(phy_dev); 2347 2348 sc->phy_dev = phy_dev; 2349 2350 return 0; 2351 } 2352 2353 2354 static void sbmac_mii_poll(struct net_device *dev) 2355 { 2356 struct sbmac_softc *sc = netdev_priv(dev); 2357 struct phy_device *phy_dev = sc->phy_dev; 2358 unsigned long flags; 2359 enum sbmac_fc fc; 2360 int link_chg, speed_chg, duplex_chg, pause_chg, fc_chg; 2361 2362 link_chg = (sc->sbm_link != phy_dev->link); 2363 speed_chg = (sc->sbm_speed != phy_dev->speed); 2364 duplex_chg = (sc->sbm_duplex != phy_dev->duplex); 2365 pause_chg = (sc->sbm_pause != phy_dev->pause); 2366 2367 if (!link_chg && !speed_chg && !duplex_chg && !pause_chg) 2368 return; /* Hmmm... */ 2369 2370 if (!phy_dev->link) { 2371 if (link_chg) { 2372 sc->sbm_link = phy_dev->link; 2373 sc->sbm_speed = sbmac_speed_none; 2374 sc->sbm_duplex = sbmac_duplex_none; 2375 sc->sbm_fc = sbmac_fc_disabled; 2376 sc->sbm_pause = -1; 2377 pr_info("%s: link unavailable\n", dev->name); 2378 } 2379 return; 2380 } 2381 2382 if (phy_dev->duplex == DUPLEX_FULL) { 2383 if (phy_dev->pause) 2384 fc = sbmac_fc_frame; 2385 else 2386 fc = sbmac_fc_disabled; 2387 } else 2388 fc = sbmac_fc_collision; 2389 fc_chg = (sc->sbm_fc != fc); 2390 2391 pr_info("%s: link available: %dbase-%cD\n", dev->name, phy_dev->speed, 2392 phy_dev->duplex == DUPLEX_FULL ? 'F' : 'H'); 2393 2394 spin_lock_irqsave(&sc->sbm_lock, flags); 2395 2396 sc->sbm_speed = phy_dev->speed; 2397 sc->sbm_duplex = phy_dev->duplex; 2398 sc->sbm_fc = fc; 2399 sc->sbm_pause = phy_dev->pause; 2400 sc->sbm_link = phy_dev->link; 2401 2402 if ((speed_chg || duplex_chg || fc_chg) && 2403 sc->sbm_state != sbmac_state_off) { 2404 /* 2405 * something changed, restart the channel 2406 */ 2407 if (debug > 1) 2408 pr_debug("%s: restarting channel " 2409 "because PHY state changed\n", dev->name); 2410 sbmac_channel_stop(sc); 2411 sbmac_channel_start(sc); 2412 } 2413 2414 spin_unlock_irqrestore(&sc->sbm_lock, flags); 2415 } 2416 2417 2418 static void sbmac_tx_timeout (struct net_device *dev, unsigned int txqueue) 2419 { 2420 struct sbmac_softc *sc = netdev_priv(dev); 2421 unsigned long flags; 2422 2423 spin_lock_irqsave(&sc->sbm_lock, flags); 2424 2425 2426 netif_trans_update(dev); /* prevent tx timeout */ 2427 dev->stats.tx_errors++; 2428 2429 spin_unlock_irqrestore(&sc->sbm_lock, flags); 2430 2431 printk (KERN_WARNING "%s: Transmit timed out\n",dev->name); 2432 } 2433 2434 2435 2436 2437 static void sbmac_set_rx_mode(struct net_device *dev) 2438 { 2439 unsigned long flags; 2440 struct sbmac_softc *sc = netdev_priv(dev); 2441 2442 spin_lock_irqsave(&sc->sbm_lock, flags); 2443 if ((dev->flags ^ sc->sbm_devflags) & IFF_PROMISC) { 2444 /* 2445 * Promiscuous changed. 2446 */ 2447 2448 if (dev->flags & IFF_PROMISC) { 2449 sbmac_promiscuous_mode(sc,1); 2450 } 2451 else { 2452 sbmac_promiscuous_mode(sc,0); 2453 } 2454 } 2455 spin_unlock_irqrestore(&sc->sbm_lock, flags); 2456 2457 /* 2458 * Program the multicasts. Do this every time. 2459 */ 2460 2461 sbmac_setmulti(sc); 2462 2463 } 2464 2465 static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 2466 { 2467 struct sbmac_softc *sc = netdev_priv(dev); 2468 2469 if (!netif_running(dev) || !sc->phy_dev) 2470 return -EINVAL; 2471 2472 return phy_mii_ioctl(sc->phy_dev, rq, cmd); 2473 } 2474 2475 static int sbmac_close(struct net_device *dev) 2476 { 2477 struct sbmac_softc *sc = netdev_priv(dev); 2478 2479 napi_disable(&sc->napi); 2480 2481 phy_stop(sc->phy_dev); 2482 2483 sbmac_set_channel_state(sc, sbmac_state_off); 2484 2485 netif_stop_queue(dev); 2486 2487 if (debug > 1) 2488 pr_debug("%s: Shutting down ethercard\n", dev->name); 2489 2490 phy_disconnect(sc->phy_dev); 2491 sc->phy_dev = NULL; 2492 free_irq(dev->irq, dev); 2493 2494 sbdma_emptyring(&(sc->sbm_txdma)); 2495 sbdma_emptyring(&(sc->sbm_rxdma)); 2496 2497 return 0; 2498 } 2499 2500 static int sbmac_poll(struct napi_struct *napi, int budget) 2501 { 2502 struct sbmac_softc *sc = container_of(napi, struct sbmac_softc, napi); 2503 int work_done; 2504 2505 work_done = sbdma_rx_process(sc, &(sc->sbm_rxdma), budget, 1); 2506 sbdma_tx_process(sc, &(sc->sbm_txdma), 1); 2507 2508 if (work_done < budget) { 2509 napi_complete_done(napi, work_done); 2510 2511 #ifdef CONFIG_SBMAC_COALESCE 2512 __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) | 2513 ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0), 2514 sc->sbm_imr); 2515 #else 2516 __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) | 2517 (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), sc->sbm_imr); 2518 #endif 2519 } 2520 2521 return work_done; 2522 } 2523 2524 2525 static int sbmac_probe(struct platform_device *pldev) 2526 { 2527 struct net_device *dev; 2528 struct sbmac_softc *sc; 2529 void __iomem *sbm_base; 2530 struct resource *res; 2531 u64 sbmac_orig_hwaddr; 2532 int err; 2533 2534 res = platform_get_resource(pldev, IORESOURCE_MEM, 0); 2535 if (!res) { 2536 printk(KERN_ERR "%s: failed to get resource\n", 2537 dev_name(&pldev->dev)); 2538 err = -EINVAL; 2539 goto out_out; 2540 } 2541 sbm_base = ioremap(res->start, resource_size(res)); 2542 if (!sbm_base) { 2543 printk(KERN_ERR "%s: unable to map device registers\n", 2544 dev_name(&pldev->dev)); 2545 err = -ENOMEM; 2546 goto out_out; 2547 } 2548 2549 /* 2550 * The R_MAC_ETHERNET_ADDR register will be set to some nonzero 2551 * value for us by the firmware if we're going to use this MAC. 2552 * If we find a zero, skip this MAC. 2553 */ 2554 sbmac_orig_hwaddr = __raw_readq(sbm_base + R_MAC_ETHERNET_ADDR); 2555 pr_debug("%s: %sconfiguring MAC at 0x%08Lx\n", dev_name(&pldev->dev), 2556 sbmac_orig_hwaddr ? "" : "not ", (long long)res->start); 2557 if (sbmac_orig_hwaddr == 0) { 2558 err = 0; 2559 goto out_unmap; 2560 } 2561 2562 /* 2563 * Okay, cool. Initialize this MAC. 2564 */ 2565 dev = alloc_etherdev(sizeof(struct sbmac_softc)); 2566 if (!dev) { 2567 err = -ENOMEM; 2568 goto out_unmap; 2569 } 2570 2571 platform_set_drvdata(pldev, dev); 2572 SET_NETDEV_DEV(dev, &pldev->dev); 2573 2574 sc = netdev_priv(dev); 2575 sc->sbm_base = sbm_base; 2576 2577 err = sbmac_init(pldev, res->start); 2578 if (err) 2579 goto out_kfree; 2580 2581 return 0; 2582 2583 out_kfree: 2584 free_netdev(dev); 2585 __raw_writeq(sbmac_orig_hwaddr, sbm_base + R_MAC_ETHERNET_ADDR); 2586 2587 out_unmap: 2588 iounmap(sbm_base); 2589 2590 out_out: 2591 return err; 2592 } 2593 2594 static void sbmac_remove(struct platform_device *pldev) 2595 { 2596 struct net_device *dev = platform_get_drvdata(pldev); 2597 struct sbmac_softc *sc = netdev_priv(dev); 2598 2599 unregister_netdev(dev); 2600 sbmac_uninitctx(sc); 2601 mdiobus_unregister(sc->mii_bus); 2602 mdiobus_free(sc->mii_bus); 2603 iounmap(sc->sbm_base); 2604 free_netdev(dev); 2605 } 2606 2607 static struct platform_driver sbmac_driver = { 2608 .probe = sbmac_probe, 2609 .remove = sbmac_remove, 2610 .driver = { 2611 .name = sbmac_string, 2612 }, 2613 }; 2614 2615 module_platform_driver(sbmac_driver); 2616 MODULE_LICENSE("GPL"); 2617