1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Check for KVM_GET_REG_LIST regressions. 4 * 5 * Copyright (c) 2023 Intel Corporation 6 * 7 */ 8 #include <stdio.h> 9 #include "kvm_util.h" 10 #include "test_util.h" 11 #include "processor.h" 12 13 #define REG_MASK (KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK) 14 15 enum { 16 VCPU_FEATURE_ISA_EXT = 0, 17 VCPU_FEATURE_SBI_EXT, 18 }; 19 20 enum { 21 KVM_RISC_V_REG_OFFSET_VSTART = 0, 22 KVM_RISC_V_REG_OFFSET_VL, 23 KVM_RISC_V_REG_OFFSET_VTYPE, 24 KVM_RISC_V_REG_OFFSET_VCSR, 25 KVM_RISC_V_REG_OFFSET_VLENB, 26 KVM_RISC_V_REG_OFFSET_MAX, 27 }; 28 29 static bool isa_ext_cant_disable[KVM_RISCV_ISA_EXT_MAX]; 30 31 bool filter_reg(__u64 reg) 32 { 33 switch (reg & ~REG_MASK) { 34 /* 35 * Same set of ISA_EXT registers are not present on all host because 36 * ISA_EXT registers are visible to the KVM user space based on the 37 * ISA extensions available on the host. Also, disabling an ISA 38 * extension using corresponding ISA_EXT register does not affect 39 * the visibility of the ISA_EXT register itself. 40 * 41 * Based on above, we should filter-out all ISA_EXT registers. 42 * 43 * Note: The below list is alphabetically sorted. 44 */ 45 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_A: 46 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_C: 47 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_D: 48 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_F: 49 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_H: 50 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_I: 51 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_M: 52 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_V: 53 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SMNPM: 54 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SMSTATEEN: 55 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSAIA: 56 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSCOFPMF: 57 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSNPM: 58 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSTC: 59 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVADE: 60 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVADU: 61 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVINVAL: 62 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVNAPOT: 63 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVPBMT: 64 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVVPTC: 65 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZAAMO: 66 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZABHA: 67 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZACAS: 68 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZALRSC: 69 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZAWRS: 70 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBA: 71 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBB: 72 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBC: 73 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBKB: 74 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBKC: 75 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBKX: 76 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBS: 77 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCA: 78 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCB: 79 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCD: 80 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCF: 81 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCMOP: 82 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFA: 83 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFBFMIN: 84 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFH: 85 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFHMIN: 86 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOM: 87 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOP: 88 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOZ: 89 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICCRSE: 90 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICNTR: 91 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICOND: 92 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICSR: 93 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZIFENCEI: 94 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZIHINTNTL: 95 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZIHINTPAUSE: 96 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZIHPM: 97 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZIMOP: 98 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKND: 99 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKNE: 100 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKNH: 101 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKR: 102 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKSED: 103 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKSH: 104 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKT: 105 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZTSO: 106 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVBB: 107 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVBC: 108 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVFBFMIN: 109 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVFBFWMA: 110 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVFH: 111 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVFHMIN: 112 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKB: 113 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKG: 114 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKNED: 115 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKNHA: 116 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKNHB: 117 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKSED: 118 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKSH: 119 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKT: 120 /* 121 * Like ISA_EXT registers, SBI_EXT registers are only visible when the 122 * host supports them and disabling them does not affect the visibility 123 * of the SBI_EXT register itself. 124 */ 125 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_V01: 126 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_TIME: 127 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_IPI: 128 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_RFENCE: 129 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_SRST: 130 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_HSM: 131 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_PMU: 132 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_DBCN: 133 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_SUSP: 134 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_STA: 135 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_FWFT: 136 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_EXPERIMENTAL: 137 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_VENDOR: 138 return true; 139 /* AIA registers are always available when Ssaia can't be disabled */ 140 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siselect): 141 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio1): 142 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio2): 143 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(sieh): 144 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siph): 145 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio1h): 146 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio2h): 147 return isa_ext_cant_disable[KVM_RISCV_ISA_EXT_SSAIA]; 148 default: 149 break; 150 } 151 152 return false; 153 } 154 155 bool check_reject_set(int err) 156 { 157 return err == EINVAL; 158 } 159 160 static int override_vector_reg_size(struct kvm_vcpu *vcpu, struct vcpu_reg_sublist *s, 161 uint64_t feature) 162 { 163 unsigned long vlenb_reg = 0; 164 int rc; 165 u64 reg, size; 166 167 /* Enable V extension so that we can get the vlenb register */ 168 rc = __vcpu_set_reg(vcpu, feature, 1); 169 if (rc) 170 return rc; 171 172 vlenb_reg = vcpu_get_reg(vcpu, s->regs[KVM_RISC_V_REG_OFFSET_VLENB]); 173 if (!vlenb_reg) { 174 TEST_FAIL("Can't compute vector register size from zero vlenb\n"); 175 return -EPERM; 176 } 177 178 size = __builtin_ctzl(vlenb_reg); 179 size <<= KVM_REG_SIZE_SHIFT; 180 181 for (int i = 0; i < 32; i++) { 182 reg = KVM_REG_RISCV | KVM_REG_RISCV_VECTOR | size | KVM_REG_RISCV_VECTOR_REG(i); 183 s->regs[KVM_RISC_V_REG_OFFSET_MAX + i] = reg; 184 } 185 186 /* We should assert if disabling failed here while enabling succeeded before */ 187 vcpu_set_reg(vcpu, feature, 0); 188 189 return 0; 190 } 191 192 void finalize_vcpu(struct kvm_vcpu *vcpu, struct vcpu_reg_list *c) 193 { 194 unsigned long isa_ext_state[KVM_RISCV_ISA_EXT_MAX] = { 0 }; 195 struct vcpu_reg_sublist *s; 196 uint64_t feature; 197 int rc; 198 199 for (int i = 0; i < KVM_RISCV_ISA_EXT_MAX; i++) 200 __vcpu_get_reg(vcpu, RISCV_ISA_EXT_REG(i), &isa_ext_state[i]); 201 202 /* 203 * Disable all extensions which were enabled by default 204 * if they were available in the risc-v host. 205 */ 206 for (int i = 0; i < KVM_RISCV_ISA_EXT_MAX; i++) { 207 rc = __vcpu_set_reg(vcpu, RISCV_ISA_EXT_REG(i), 0); 208 if (rc && isa_ext_state[i]) 209 isa_ext_cant_disable[i] = true; 210 } 211 212 for (int i = 0; i < KVM_RISCV_SBI_EXT_MAX; i++) { 213 rc = __vcpu_set_reg(vcpu, RISCV_SBI_EXT_REG(i), 0); 214 TEST_ASSERT(!rc || (rc == -1 && errno == ENOENT), "Unexpected error"); 215 } 216 217 for_each_sublist(c, s) { 218 if (!s->feature) 219 continue; 220 221 if (s->feature == KVM_RISCV_ISA_EXT_V) { 222 feature = RISCV_ISA_EXT_REG(s->feature); 223 rc = override_vector_reg_size(vcpu, s, feature); 224 if (rc) 225 goto skip; 226 } 227 228 switch (s->feature_type) { 229 case VCPU_FEATURE_ISA_EXT: 230 feature = RISCV_ISA_EXT_REG(s->feature); 231 break; 232 case VCPU_FEATURE_SBI_EXT: 233 feature = RISCV_SBI_EXT_REG(s->feature); 234 break; 235 default: 236 TEST_FAIL("Unknown feature type"); 237 } 238 239 /* Try to enable the desired extension */ 240 __vcpu_set_reg(vcpu, feature, 1); 241 242 skip: 243 /* Double check whether the desired extension was enabled */ 244 __TEST_REQUIRE(__vcpu_has_ext(vcpu, feature), 245 "%s not available, skipping tests", s->name); 246 } 247 } 248 249 static const char *config_id_to_str(const char *prefix, __u64 id) 250 { 251 /* reg_off is the offset into struct kvm_riscv_config */ 252 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CONFIG); 253 254 assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CONFIG); 255 256 switch (reg_off) { 257 case KVM_REG_RISCV_CONFIG_REG(isa): 258 return "KVM_REG_RISCV_CONFIG_REG(isa)"; 259 case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size): 260 return "KVM_REG_RISCV_CONFIG_REG(zicbom_block_size)"; 261 case KVM_REG_RISCV_CONFIG_REG(zicboz_block_size): 262 return "KVM_REG_RISCV_CONFIG_REG(zicboz_block_size)"; 263 case KVM_REG_RISCV_CONFIG_REG(zicbop_block_size): 264 return "KVM_REG_RISCV_CONFIG_REG(zicbop_block_size)"; 265 case KVM_REG_RISCV_CONFIG_REG(mvendorid): 266 return "KVM_REG_RISCV_CONFIG_REG(mvendorid)"; 267 case KVM_REG_RISCV_CONFIG_REG(marchid): 268 return "KVM_REG_RISCV_CONFIG_REG(marchid)"; 269 case KVM_REG_RISCV_CONFIG_REG(mimpid): 270 return "KVM_REG_RISCV_CONFIG_REG(mimpid)"; 271 case KVM_REG_RISCV_CONFIG_REG(satp_mode): 272 return "KVM_REG_RISCV_CONFIG_REG(satp_mode)"; 273 } 274 275 return strdup_printf("%lld /* UNKNOWN */", reg_off); 276 } 277 278 static const char *core_id_to_str(const char *prefix, __u64 id) 279 { 280 /* reg_off is the offset into struct kvm_riscv_core */ 281 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CORE); 282 283 assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CORE); 284 285 switch (reg_off) { 286 case KVM_REG_RISCV_CORE_REG(regs.pc): 287 return "KVM_REG_RISCV_CORE_REG(regs.pc)"; 288 case KVM_REG_RISCV_CORE_REG(regs.ra): 289 return "KVM_REG_RISCV_CORE_REG(regs.ra)"; 290 case KVM_REG_RISCV_CORE_REG(regs.sp): 291 return "KVM_REG_RISCV_CORE_REG(regs.sp)"; 292 case KVM_REG_RISCV_CORE_REG(regs.gp): 293 return "KVM_REG_RISCV_CORE_REG(regs.gp)"; 294 case KVM_REG_RISCV_CORE_REG(regs.tp): 295 return "KVM_REG_RISCV_CORE_REG(regs.tp)"; 296 case KVM_REG_RISCV_CORE_REG(regs.t0) ... KVM_REG_RISCV_CORE_REG(regs.t2): 297 return strdup_printf("KVM_REG_RISCV_CORE_REG(regs.t%lld)", 298 reg_off - KVM_REG_RISCV_CORE_REG(regs.t0)); 299 case KVM_REG_RISCV_CORE_REG(regs.s0) ... KVM_REG_RISCV_CORE_REG(regs.s1): 300 return strdup_printf("KVM_REG_RISCV_CORE_REG(regs.s%lld)", 301 reg_off - KVM_REG_RISCV_CORE_REG(regs.s0)); 302 case KVM_REG_RISCV_CORE_REG(regs.a0) ... KVM_REG_RISCV_CORE_REG(regs.a7): 303 return strdup_printf("KVM_REG_RISCV_CORE_REG(regs.a%lld)", 304 reg_off - KVM_REG_RISCV_CORE_REG(regs.a0)); 305 case KVM_REG_RISCV_CORE_REG(regs.s2) ... KVM_REG_RISCV_CORE_REG(regs.s11): 306 return strdup_printf("KVM_REG_RISCV_CORE_REG(regs.s%lld)", 307 reg_off - KVM_REG_RISCV_CORE_REG(regs.s2) + 2); 308 case KVM_REG_RISCV_CORE_REG(regs.t3) ... KVM_REG_RISCV_CORE_REG(regs.t6): 309 return strdup_printf("KVM_REG_RISCV_CORE_REG(regs.t%lld)", 310 reg_off - KVM_REG_RISCV_CORE_REG(regs.t3) + 3); 311 case KVM_REG_RISCV_CORE_REG(mode): 312 return "KVM_REG_RISCV_CORE_REG(mode)"; 313 } 314 315 return strdup_printf("%lld /* UNKNOWN */", reg_off); 316 } 317 318 #define RISCV_CSR_GENERAL(csr) \ 319 "KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(" #csr ")" 320 #define RISCV_CSR_AIA(csr) \ 321 "KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_REG(" #csr ")" 322 #define RISCV_CSR_SMSTATEEN(csr) \ 323 "KVM_REG_RISCV_CSR_SMSTATEEN | KVM_REG_RISCV_CSR_REG(" #csr ")" 324 325 static const char *general_csr_id_to_str(__u64 reg_off) 326 { 327 /* reg_off is the offset into struct kvm_riscv_csr */ 328 switch (reg_off) { 329 case KVM_REG_RISCV_CSR_REG(sstatus): 330 return RISCV_CSR_GENERAL(sstatus); 331 case KVM_REG_RISCV_CSR_REG(sie): 332 return RISCV_CSR_GENERAL(sie); 333 case KVM_REG_RISCV_CSR_REG(stvec): 334 return RISCV_CSR_GENERAL(stvec); 335 case KVM_REG_RISCV_CSR_REG(sscratch): 336 return RISCV_CSR_GENERAL(sscratch); 337 case KVM_REG_RISCV_CSR_REG(sepc): 338 return RISCV_CSR_GENERAL(sepc); 339 case KVM_REG_RISCV_CSR_REG(scause): 340 return RISCV_CSR_GENERAL(scause); 341 case KVM_REG_RISCV_CSR_REG(stval): 342 return RISCV_CSR_GENERAL(stval); 343 case KVM_REG_RISCV_CSR_REG(sip): 344 return RISCV_CSR_GENERAL(sip); 345 case KVM_REG_RISCV_CSR_REG(satp): 346 return RISCV_CSR_GENERAL(satp); 347 case KVM_REG_RISCV_CSR_REG(scounteren): 348 return RISCV_CSR_GENERAL(scounteren); 349 case KVM_REG_RISCV_CSR_REG(senvcfg): 350 return RISCV_CSR_GENERAL(senvcfg); 351 } 352 353 return strdup_printf("KVM_REG_RISCV_CSR_GENERAL | %lld /* UNKNOWN */", reg_off); 354 } 355 356 static const char *aia_csr_id_to_str(__u64 reg_off) 357 { 358 /* reg_off is the offset into struct kvm_riscv_aia_csr */ 359 switch (reg_off) { 360 case KVM_REG_RISCV_CSR_AIA_REG(siselect): 361 return RISCV_CSR_AIA(siselect); 362 case KVM_REG_RISCV_CSR_AIA_REG(iprio1): 363 return RISCV_CSR_AIA(iprio1); 364 case KVM_REG_RISCV_CSR_AIA_REG(iprio2): 365 return RISCV_CSR_AIA(iprio2); 366 case KVM_REG_RISCV_CSR_AIA_REG(sieh): 367 return RISCV_CSR_AIA(sieh); 368 case KVM_REG_RISCV_CSR_AIA_REG(siph): 369 return RISCV_CSR_AIA(siph); 370 case KVM_REG_RISCV_CSR_AIA_REG(iprio1h): 371 return RISCV_CSR_AIA(iprio1h); 372 case KVM_REG_RISCV_CSR_AIA_REG(iprio2h): 373 return RISCV_CSR_AIA(iprio2h); 374 } 375 376 return strdup_printf("KVM_REG_RISCV_CSR_AIA | %lld /* UNKNOWN */", reg_off); 377 } 378 379 static const char *smstateen_csr_id_to_str(__u64 reg_off) 380 { 381 /* reg_off is the offset into struct kvm_riscv_smstateen_csr */ 382 switch (reg_off) { 383 case KVM_REG_RISCV_CSR_SMSTATEEN_REG(sstateen0): 384 return RISCV_CSR_SMSTATEEN(sstateen0); 385 } 386 387 TEST_FAIL("Unknown smstateen csr reg: 0x%llx", reg_off); 388 return NULL; 389 } 390 391 static const char *csr_id_to_str(const char *prefix, __u64 id) 392 { 393 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CSR); 394 __u64 reg_subtype = reg_off & KVM_REG_RISCV_SUBTYPE_MASK; 395 396 assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CSR); 397 398 reg_off &= ~KVM_REG_RISCV_SUBTYPE_MASK; 399 400 switch (reg_subtype) { 401 case KVM_REG_RISCV_CSR_GENERAL: 402 return general_csr_id_to_str(reg_off); 403 case KVM_REG_RISCV_CSR_AIA: 404 return aia_csr_id_to_str(reg_off); 405 case KVM_REG_RISCV_CSR_SMSTATEEN: 406 return smstateen_csr_id_to_str(reg_off); 407 } 408 409 return strdup_printf("%lld | %lld /* UNKNOWN */", reg_subtype, reg_off); 410 } 411 412 static const char *timer_id_to_str(const char *prefix, __u64 id) 413 { 414 /* reg_off is the offset into struct kvm_riscv_timer */ 415 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_TIMER); 416 417 assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_TIMER); 418 419 switch (reg_off) { 420 case KVM_REG_RISCV_TIMER_REG(frequency): 421 return "KVM_REG_RISCV_TIMER_REG(frequency)"; 422 case KVM_REG_RISCV_TIMER_REG(time): 423 return "KVM_REG_RISCV_TIMER_REG(time)"; 424 case KVM_REG_RISCV_TIMER_REG(compare): 425 return "KVM_REG_RISCV_TIMER_REG(compare)"; 426 case KVM_REG_RISCV_TIMER_REG(state): 427 return "KVM_REG_RISCV_TIMER_REG(state)"; 428 } 429 430 return strdup_printf("%lld /* UNKNOWN */", reg_off); 431 } 432 433 static const char *fp_f_id_to_str(const char *prefix, __u64 id) 434 { 435 /* reg_off is the offset into struct __riscv_f_ext_state */ 436 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_FP_F); 437 438 assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_F); 439 440 switch (reg_off) { 441 case KVM_REG_RISCV_FP_F_REG(f[0]) ... 442 KVM_REG_RISCV_FP_F_REG(f[31]): 443 return strdup_printf("KVM_REG_RISCV_FP_F_REG(f[%lld])", reg_off); 444 case KVM_REG_RISCV_FP_F_REG(fcsr): 445 return "KVM_REG_RISCV_FP_F_REG(fcsr)"; 446 } 447 448 return strdup_printf("%lld /* UNKNOWN */", reg_off); 449 } 450 451 static const char *fp_d_id_to_str(const char *prefix, __u64 id) 452 { 453 /* reg_off is the offset into struct __riscv_d_ext_state */ 454 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_FP_D); 455 456 assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_D); 457 458 switch (reg_off) { 459 case KVM_REG_RISCV_FP_D_REG(f[0]) ... 460 KVM_REG_RISCV_FP_D_REG(f[31]): 461 return strdup_printf("KVM_REG_RISCV_FP_D_REG(f[%lld])", reg_off); 462 case KVM_REG_RISCV_FP_D_REG(fcsr): 463 return "KVM_REG_RISCV_FP_D_REG(fcsr)"; 464 } 465 466 return strdup_printf("%lld /* UNKNOWN */", reg_off); 467 } 468 469 static const char *vector_id_to_str(const char *prefix, __u64 id) 470 { 471 /* reg_off is the offset into struct __riscv_v_ext_state */ 472 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_VECTOR); 473 int reg_index = 0; 474 475 assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_VECTOR); 476 477 if (reg_off >= KVM_REG_RISCV_VECTOR_REG(0)) 478 reg_index = reg_off - KVM_REG_RISCV_VECTOR_REG(0); 479 switch (reg_off) { 480 case KVM_REG_RISCV_VECTOR_REG(0) ... 481 KVM_REG_RISCV_VECTOR_REG(31): 482 return strdup_printf("KVM_REG_RISCV_VECTOR_REG(%d)", reg_index); 483 case KVM_REG_RISCV_VECTOR_CSR_REG(vstart): 484 return "KVM_REG_RISCV_VECTOR_CSR_REG(vstart)"; 485 case KVM_REG_RISCV_VECTOR_CSR_REG(vl): 486 return "KVM_REG_RISCV_VECTOR_CSR_REG(vl)"; 487 case KVM_REG_RISCV_VECTOR_CSR_REG(vtype): 488 return "KVM_REG_RISCV_VECTOR_CSR_REG(vtype)"; 489 case KVM_REG_RISCV_VECTOR_CSR_REG(vcsr): 490 return "KVM_REG_RISCV_VECTOR_CSR_REG(vcsr)"; 491 case KVM_REG_RISCV_VECTOR_CSR_REG(vlenb): 492 return "KVM_REG_RISCV_VECTOR_CSR_REG(vlenb)"; 493 } 494 495 return strdup_printf("%lld /* UNKNOWN */", reg_off); 496 } 497 498 #define KVM_ISA_EXT_ARR(ext) \ 499 [KVM_RISCV_ISA_EXT_##ext] = "KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_" #ext 500 501 static const char *isa_ext_single_id_to_str(__u64 reg_off) 502 { 503 static const char * const kvm_isa_ext_reg_name[] = { 504 KVM_ISA_EXT_ARR(A), 505 KVM_ISA_EXT_ARR(C), 506 KVM_ISA_EXT_ARR(D), 507 KVM_ISA_EXT_ARR(F), 508 KVM_ISA_EXT_ARR(H), 509 KVM_ISA_EXT_ARR(I), 510 KVM_ISA_EXT_ARR(M), 511 KVM_ISA_EXT_ARR(V), 512 KVM_ISA_EXT_ARR(SMNPM), 513 KVM_ISA_EXT_ARR(SMSTATEEN), 514 KVM_ISA_EXT_ARR(SSAIA), 515 KVM_ISA_EXT_ARR(SSCOFPMF), 516 KVM_ISA_EXT_ARR(SSNPM), 517 KVM_ISA_EXT_ARR(SSTC), 518 KVM_ISA_EXT_ARR(SVADE), 519 KVM_ISA_EXT_ARR(SVADU), 520 KVM_ISA_EXT_ARR(SVINVAL), 521 KVM_ISA_EXT_ARR(SVNAPOT), 522 KVM_ISA_EXT_ARR(SVPBMT), 523 KVM_ISA_EXT_ARR(SVVPTC), 524 KVM_ISA_EXT_ARR(ZAAMO), 525 KVM_ISA_EXT_ARR(ZABHA), 526 KVM_ISA_EXT_ARR(ZACAS), 527 KVM_ISA_EXT_ARR(ZALRSC), 528 KVM_ISA_EXT_ARR(ZAWRS), 529 KVM_ISA_EXT_ARR(ZBA), 530 KVM_ISA_EXT_ARR(ZBB), 531 KVM_ISA_EXT_ARR(ZBC), 532 KVM_ISA_EXT_ARR(ZBKB), 533 KVM_ISA_EXT_ARR(ZBKC), 534 KVM_ISA_EXT_ARR(ZBKX), 535 KVM_ISA_EXT_ARR(ZBS), 536 KVM_ISA_EXT_ARR(ZCA), 537 KVM_ISA_EXT_ARR(ZCB), 538 KVM_ISA_EXT_ARR(ZCD), 539 KVM_ISA_EXT_ARR(ZCF), 540 KVM_ISA_EXT_ARR(ZCMOP), 541 KVM_ISA_EXT_ARR(ZFA), 542 KVM_ISA_EXT_ARR(ZFBFMIN), 543 KVM_ISA_EXT_ARR(ZFH), 544 KVM_ISA_EXT_ARR(ZFHMIN), 545 KVM_ISA_EXT_ARR(ZICBOM), 546 KVM_ISA_EXT_ARR(ZICBOP), 547 KVM_ISA_EXT_ARR(ZICBOZ), 548 KVM_ISA_EXT_ARR(ZICCRSE), 549 KVM_ISA_EXT_ARR(ZICNTR), 550 KVM_ISA_EXT_ARR(ZICOND), 551 KVM_ISA_EXT_ARR(ZICSR), 552 KVM_ISA_EXT_ARR(ZIFENCEI), 553 KVM_ISA_EXT_ARR(ZIHINTNTL), 554 KVM_ISA_EXT_ARR(ZIHINTPAUSE), 555 KVM_ISA_EXT_ARR(ZIHPM), 556 KVM_ISA_EXT_ARR(ZIMOP), 557 KVM_ISA_EXT_ARR(ZKND), 558 KVM_ISA_EXT_ARR(ZKNE), 559 KVM_ISA_EXT_ARR(ZKNH), 560 KVM_ISA_EXT_ARR(ZKR), 561 KVM_ISA_EXT_ARR(ZKSED), 562 KVM_ISA_EXT_ARR(ZKSH), 563 KVM_ISA_EXT_ARR(ZKT), 564 KVM_ISA_EXT_ARR(ZTSO), 565 KVM_ISA_EXT_ARR(ZVBB), 566 KVM_ISA_EXT_ARR(ZVBC), 567 KVM_ISA_EXT_ARR(ZVFBFMIN), 568 KVM_ISA_EXT_ARR(ZVFBFWMA), 569 KVM_ISA_EXT_ARR(ZVFH), 570 KVM_ISA_EXT_ARR(ZVFHMIN), 571 KVM_ISA_EXT_ARR(ZVKB), 572 KVM_ISA_EXT_ARR(ZVKG), 573 KVM_ISA_EXT_ARR(ZVKNED), 574 KVM_ISA_EXT_ARR(ZVKNHA), 575 KVM_ISA_EXT_ARR(ZVKNHB), 576 KVM_ISA_EXT_ARR(ZVKSED), 577 KVM_ISA_EXT_ARR(ZVKSH), 578 KVM_ISA_EXT_ARR(ZVKT), 579 }; 580 581 if (reg_off >= ARRAY_SIZE(kvm_isa_ext_reg_name)) 582 return strdup_printf("KVM_REG_RISCV_ISA_SINGLE | %lld /* UNKNOWN */", reg_off); 583 584 return kvm_isa_ext_reg_name[reg_off]; 585 } 586 587 static const char *isa_ext_multi_id_to_str(__u64 reg_subtype, __u64 reg_off) 588 { 589 const char *unknown = ""; 590 591 if (reg_off > KVM_REG_RISCV_ISA_MULTI_REG_LAST) 592 unknown = " /* UNKNOWN */"; 593 594 switch (reg_subtype) { 595 case KVM_REG_RISCV_ISA_MULTI_EN: 596 return strdup_printf("KVM_REG_RISCV_ISA_MULTI_EN | %lld%s", reg_off, unknown); 597 case KVM_REG_RISCV_ISA_MULTI_DIS: 598 return strdup_printf("KVM_REG_RISCV_ISA_MULTI_DIS | %lld%s", reg_off, unknown); 599 } 600 601 return strdup_printf("%lld | %lld /* UNKNOWN */", reg_subtype, reg_off); 602 } 603 604 static const char *isa_ext_id_to_str(const char *prefix, __u64 id) 605 { 606 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_ISA_EXT); 607 __u64 reg_subtype = reg_off & KVM_REG_RISCV_SUBTYPE_MASK; 608 609 assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_ISA_EXT); 610 611 reg_off &= ~KVM_REG_RISCV_SUBTYPE_MASK; 612 613 switch (reg_subtype) { 614 case KVM_REG_RISCV_ISA_SINGLE: 615 return isa_ext_single_id_to_str(reg_off); 616 case KVM_REG_RISCV_ISA_MULTI_EN: 617 case KVM_REG_RISCV_ISA_MULTI_DIS: 618 return isa_ext_multi_id_to_str(reg_subtype, reg_off); 619 } 620 621 return strdup_printf("%lld | %lld /* UNKNOWN */", reg_subtype, reg_off); 622 } 623 624 #define KVM_SBI_EXT_ARR(ext) \ 625 [ext] = "KVM_REG_RISCV_SBI_SINGLE | " #ext 626 627 static const char *sbi_ext_single_id_to_str(__u64 reg_off) 628 { 629 /* reg_off is KVM_RISCV_SBI_EXT_ID */ 630 static const char * const kvm_sbi_ext_reg_name[] = { 631 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_V01), 632 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_TIME), 633 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_IPI), 634 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_RFENCE), 635 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_SRST), 636 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_HSM), 637 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_PMU), 638 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_DBCN), 639 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_SUSP), 640 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_STA), 641 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_FWFT), 642 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_EXPERIMENTAL), 643 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_VENDOR), 644 }; 645 646 if (reg_off >= ARRAY_SIZE(kvm_sbi_ext_reg_name)) 647 return strdup_printf("KVM_REG_RISCV_SBI_SINGLE | %lld /* UNKNOWN */", reg_off); 648 649 return kvm_sbi_ext_reg_name[reg_off]; 650 } 651 652 static const char *sbi_ext_multi_id_to_str(__u64 reg_subtype, __u64 reg_off) 653 { 654 const char *unknown = ""; 655 656 if (reg_off > KVM_REG_RISCV_SBI_MULTI_REG_LAST) 657 unknown = " /* UNKNOWN */"; 658 659 switch (reg_subtype) { 660 case KVM_REG_RISCV_SBI_MULTI_EN: 661 return strdup_printf("KVM_REG_RISCV_SBI_MULTI_EN | %lld%s", reg_off, unknown); 662 case KVM_REG_RISCV_SBI_MULTI_DIS: 663 return strdup_printf("KVM_REG_RISCV_SBI_MULTI_DIS | %lld%s", reg_off, unknown); 664 } 665 666 return strdup_printf("%lld | %lld /* UNKNOWN */", reg_subtype, reg_off); 667 } 668 669 static const char *sbi_ext_id_to_str(const char *prefix, __u64 id) 670 { 671 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_SBI_EXT); 672 __u64 reg_subtype = reg_off & KVM_REG_RISCV_SUBTYPE_MASK; 673 674 assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_SBI_EXT); 675 676 reg_off &= ~KVM_REG_RISCV_SUBTYPE_MASK; 677 678 switch (reg_subtype) { 679 case KVM_REG_RISCV_SBI_SINGLE: 680 return sbi_ext_single_id_to_str(reg_off); 681 case KVM_REG_RISCV_SBI_MULTI_EN: 682 case KVM_REG_RISCV_SBI_MULTI_DIS: 683 return sbi_ext_multi_id_to_str(reg_subtype, reg_off); 684 } 685 686 return strdup_printf("%lld | %lld /* UNKNOWN */", reg_subtype, reg_off); 687 } 688 689 static const char *sbi_sta_id_to_str(__u64 reg_off) 690 { 691 switch (reg_off) { 692 case 0: return "KVM_REG_RISCV_SBI_STA | KVM_REG_RISCV_SBI_STA_REG(shmem_lo)"; 693 case 1: return "KVM_REG_RISCV_SBI_STA | KVM_REG_RISCV_SBI_STA_REG(shmem_hi)"; 694 } 695 return strdup_printf("KVM_REG_RISCV_SBI_STA | %lld /* UNKNOWN */", reg_off); 696 } 697 698 static const char *sbi_fwft_id_to_str(__u64 reg_off) 699 { 700 switch (reg_off) { 701 case 0: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(misaligned_deleg.enable)"; 702 case 1: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(misaligned_deleg.flags)"; 703 case 2: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(misaligned_deleg.value)"; 704 case 3: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.enable)"; 705 case 4: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.flags)"; 706 case 5: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.value)"; 707 } 708 return strdup_printf("KVM_REG_RISCV_SBI_FWFT | %lld /* UNKNOWN */", reg_off); 709 } 710 711 static const char *sbi_id_to_str(const char *prefix, __u64 id) 712 { 713 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_SBI_STATE); 714 __u64 reg_subtype = reg_off & KVM_REG_RISCV_SUBTYPE_MASK; 715 716 assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_SBI_STATE); 717 718 reg_off &= ~KVM_REG_RISCV_SUBTYPE_MASK; 719 720 switch (reg_subtype) { 721 case KVM_REG_RISCV_SBI_STA: 722 return sbi_sta_id_to_str(reg_off); 723 case KVM_REG_RISCV_SBI_FWFT: 724 return sbi_fwft_id_to_str(reg_off); 725 } 726 727 return strdup_printf("%lld | %lld /* UNKNOWN */", reg_subtype, reg_off); 728 } 729 730 void print_reg(const char *prefix, __u64 id) 731 { 732 const char *reg_size = NULL; 733 734 TEST_ASSERT((id & KVM_REG_ARCH_MASK) == KVM_REG_RISCV, 735 "%s: KVM_REG_RISCV missing in reg id: 0x%llx", prefix, id); 736 737 switch (id & KVM_REG_SIZE_MASK) { 738 case KVM_REG_SIZE_U32: 739 reg_size = "KVM_REG_SIZE_U32"; 740 break; 741 case KVM_REG_SIZE_U64: 742 reg_size = "KVM_REG_SIZE_U64"; 743 break; 744 case KVM_REG_SIZE_U128: 745 reg_size = "KVM_REG_SIZE_U128"; 746 break; 747 case KVM_REG_SIZE_U256: 748 reg_size = "KVM_REG_SIZE_U256"; 749 break; 750 default: 751 printf("\tKVM_REG_RISCV | (%lld << KVM_REG_SIZE_SHIFT) | 0x%llx /* UNKNOWN */,\n", 752 (id & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT, id & ~REG_MASK); 753 return; 754 } 755 756 switch (id & KVM_REG_RISCV_TYPE_MASK) { 757 case KVM_REG_RISCV_CONFIG: 758 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_CONFIG | %s,\n", 759 reg_size, config_id_to_str(prefix, id)); 760 break; 761 case KVM_REG_RISCV_CORE: 762 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_CORE | %s,\n", 763 reg_size, core_id_to_str(prefix, id)); 764 break; 765 case KVM_REG_RISCV_CSR: 766 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_CSR | %s,\n", 767 reg_size, csr_id_to_str(prefix, id)); 768 break; 769 case KVM_REG_RISCV_TIMER: 770 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_TIMER | %s,\n", 771 reg_size, timer_id_to_str(prefix, id)); 772 break; 773 case KVM_REG_RISCV_FP_F: 774 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_FP_F | %s,\n", 775 reg_size, fp_f_id_to_str(prefix, id)); 776 break; 777 case KVM_REG_RISCV_FP_D: 778 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_FP_D | %s,\n", 779 reg_size, fp_d_id_to_str(prefix, id)); 780 break; 781 case KVM_REG_RISCV_VECTOR: 782 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_VECTOR | %s,\n", 783 reg_size, vector_id_to_str(prefix, id)); 784 break; 785 case KVM_REG_RISCV_ISA_EXT: 786 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_ISA_EXT | %s,\n", 787 reg_size, isa_ext_id_to_str(prefix, id)); 788 break; 789 case KVM_REG_RISCV_SBI_EXT: 790 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_SBI_EXT | %s,\n", 791 reg_size, sbi_ext_id_to_str(prefix, id)); 792 break; 793 case KVM_REG_RISCV_SBI_STATE: 794 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_SBI_STATE | %s,\n", 795 reg_size, sbi_id_to_str(prefix, id)); 796 break; 797 default: 798 printf("\tKVM_REG_RISCV | %s | 0x%llx /* UNKNOWN */,\n", 799 reg_size, id & ~REG_MASK); 800 return; 801 } 802 } 803 804 /* 805 * The current blessed list was primed with the output of kernel version 806 * v6.5-rc3 and then later updated with new registers. 807 */ 808 static __u64 base_regs[] = { 809 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(isa), 810 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(zicbom_block_size), 811 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(mvendorid), 812 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(marchid), 813 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(mimpid), 814 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(zicboz_block_size), 815 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(satp_mode), 816 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(zicbop_block_size), 817 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.pc), 818 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.ra), 819 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.sp), 820 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.gp), 821 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.tp), 822 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.t0), 823 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.t1), 824 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.t2), 825 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s0), 826 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s1), 827 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a0), 828 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a1), 829 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a2), 830 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a3), 831 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a4), 832 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a5), 833 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a6), 834 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a7), 835 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s2), 836 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s3), 837 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s4), 838 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s5), 839 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s6), 840 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s7), 841 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s8), 842 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s9), 843 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s10), 844 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s11), 845 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.t3), 846 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.t4), 847 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.t5), 848 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.t6), 849 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(mode), 850 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(sstatus), 851 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(sie), 852 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(stvec), 853 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(sscratch), 854 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(sepc), 855 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(scause), 856 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(stval), 857 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(sip), 858 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(satp), 859 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(scounteren), 860 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(senvcfg), 861 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(frequency), 862 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(time), 863 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(compare), 864 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(state), 865 }; 866 867 /* 868 * The skips_set list registers that should skip set test. 869 * - KVM_REG_RISCV_TIMER_REG(state): set would fail if it was not initialized properly. 870 */ 871 static __u64 base_skips_set[] = { 872 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(state), 873 }; 874 875 static __u64 sbi_base_regs[] = { 876 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_V01, 877 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_TIME, 878 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_IPI, 879 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_RFENCE, 880 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_SRST, 881 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_HSM, 882 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_EXPERIMENTAL, 883 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_VENDOR, 884 }; 885 886 static __u64 sbi_sta_regs[] = { 887 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_STA, 888 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_STA | KVM_REG_RISCV_SBI_STA_REG(shmem_lo), 889 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_STA | KVM_REG_RISCV_SBI_STA_REG(shmem_hi), 890 }; 891 892 static __u64 sbi_fwft_regs[] = { 893 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_FWFT, 894 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(misaligned_deleg.enable), 895 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(misaligned_deleg.flags), 896 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(misaligned_deleg.value), 897 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.enable), 898 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.flags), 899 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.value), 900 }; 901 902 static __u64 zicbom_regs[] = { 903 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(zicbom_block_size), 904 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOM, 905 }; 906 907 static __u64 zicbop_regs[] = { 908 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(zicbop_block_size), 909 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOP, 910 }; 911 912 static __u64 zicboz_regs[] = { 913 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(zicboz_block_size), 914 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOZ, 915 }; 916 917 static __u64 aia_regs[] = { 918 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siselect), 919 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio1), 920 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio2), 921 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(sieh), 922 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siph), 923 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio1h), 924 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio2h), 925 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSAIA, 926 }; 927 928 static __u64 smstateen_regs[] = { 929 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_SMSTATEEN | KVM_REG_RISCV_CSR_SMSTATEEN_REG(sstateen0), 930 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SMSTATEEN, 931 }; 932 933 static __u64 fp_f_regs[] = { 934 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[0]), 935 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[1]), 936 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[2]), 937 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[3]), 938 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[4]), 939 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[5]), 940 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[6]), 941 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[7]), 942 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[8]), 943 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[9]), 944 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[10]), 945 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[11]), 946 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[12]), 947 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[13]), 948 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[14]), 949 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[15]), 950 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[16]), 951 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[17]), 952 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[18]), 953 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[19]), 954 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[20]), 955 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[21]), 956 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[22]), 957 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[23]), 958 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[24]), 959 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[25]), 960 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[26]), 961 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[27]), 962 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[28]), 963 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[29]), 964 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[30]), 965 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[31]), 966 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(fcsr), 967 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_F, 968 }; 969 970 static __u64 fp_d_regs[] = { 971 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[0]), 972 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[1]), 973 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[2]), 974 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[3]), 975 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[4]), 976 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[5]), 977 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[6]), 978 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[7]), 979 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[8]), 980 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[9]), 981 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[10]), 982 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[11]), 983 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[12]), 984 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[13]), 985 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[14]), 986 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[15]), 987 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[16]), 988 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[17]), 989 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[18]), 990 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[19]), 991 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[20]), 992 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[21]), 993 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[22]), 994 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[23]), 995 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[24]), 996 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[25]), 997 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[26]), 998 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[27]), 999 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[28]), 1000 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[29]), 1001 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[30]), 1002 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[31]), 1003 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(fcsr), 1004 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_D, 1005 }; 1006 1007 /* Define a default vector registers with length. This will be overwritten at runtime */ 1008 static __u64 vector_regs[] = { 1009 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_CSR_REG(vstart), 1010 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_CSR_REG(vl), 1011 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_CSR_REG(vtype), 1012 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_CSR_REG(vcsr), 1013 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_CSR_REG(vlenb), 1014 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(0), 1015 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(1), 1016 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(2), 1017 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(3), 1018 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(4), 1019 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(5), 1020 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(6), 1021 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(7), 1022 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(8), 1023 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(9), 1024 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(10), 1025 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(11), 1026 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(12), 1027 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(13), 1028 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(14), 1029 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(15), 1030 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(16), 1031 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(17), 1032 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(18), 1033 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(19), 1034 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(20), 1035 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(21), 1036 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(22), 1037 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(23), 1038 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(24), 1039 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(25), 1040 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(26), 1041 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(27), 1042 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(28), 1043 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(29), 1044 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(30), 1045 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(31), 1046 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_V, 1047 }; 1048 1049 #define SUBLIST_BASE \ 1050 {"base", .regs = base_regs, .regs_n = ARRAY_SIZE(base_regs), \ 1051 .skips_set = base_skips_set, .skips_set_n = ARRAY_SIZE(base_skips_set),} 1052 #define SUBLIST_SBI_BASE \ 1053 {"sbi-base", .feature_type = VCPU_FEATURE_SBI_EXT, .feature = KVM_RISCV_SBI_EXT_V01, \ 1054 .regs = sbi_base_regs, .regs_n = ARRAY_SIZE(sbi_base_regs),} 1055 #define SUBLIST_SBI_STA \ 1056 {"sbi-sta", .feature_type = VCPU_FEATURE_SBI_EXT, .feature = KVM_RISCV_SBI_EXT_STA, \ 1057 .regs = sbi_sta_regs, .regs_n = ARRAY_SIZE(sbi_sta_regs),} 1058 #define SUBLIST_SBI_FWFT \ 1059 {"sbi-fwft", .feature_type = VCPU_FEATURE_SBI_EXT, .feature = KVM_RISCV_SBI_EXT_FWFT, \ 1060 .regs = sbi_fwft_regs, .regs_n = ARRAY_SIZE(sbi_fwft_regs),} 1061 #define SUBLIST_ZICBOM \ 1062 {"zicbom", .feature = KVM_RISCV_ISA_EXT_ZICBOM, .regs = zicbom_regs, .regs_n = ARRAY_SIZE(zicbom_regs),} 1063 #define SUBLIST_ZICBOP \ 1064 {"zicbop", .feature = KVM_RISCV_ISA_EXT_ZICBOP, .regs = zicbop_regs, .regs_n = ARRAY_SIZE(zicbop_regs),} 1065 #define SUBLIST_ZICBOZ \ 1066 {"zicboz", .feature = KVM_RISCV_ISA_EXT_ZICBOZ, .regs = zicboz_regs, .regs_n = ARRAY_SIZE(zicboz_regs),} 1067 #define SUBLIST_AIA \ 1068 {"aia", .feature = KVM_RISCV_ISA_EXT_SSAIA, .regs = aia_regs, .regs_n = ARRAY_SIZE(aia_regs),} 1069 #define SUBLIST_SMSTATEEN \ 1070 {"smstateen", .feature = KVM_RISCV_ISA_EXT_SMSTATEEN, .regs = smstateen_regs, .regs_n = ARRAY_SIZE(smstateen_regs),} 1071 #define SUBLIST_FP_F \ 1072 {"fp_f", .feature = KVM_RISCV_ISA_EXT_F, .regs = fp_f_regs, \ 1073 .regs_n = ARRAY_SIZE(fp_f_regs),} 1074 #define SUBLIST_FP_D \ 1075 {"fp_d", .feature = KVM_RISCV_ISA_EXT_D, .regs = fp_d_regs, \ 1076 .regs_n = ARRAY_SIZE(fp_d_regs),} 1077 1078 #define SUBLIST_V \ 1079 {"v", .feature = KVM_RISCV_ISA_EXT_V, .regs = vector_regs, .regs_n = ARRAY_SIZE(vector_regs),} 1080 1081 #define KVM_ISA_EXT_SIMPLE_CONFIG(ext, extu) \ 1082 static __u64 regs_##ext[] = { \ 1083 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | \ 1084 KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | \ 1085 KVM_RISCV_ISA_EXT_##extu, \ 1086 }; \ 1087 static struct vcpu_reg_list config_##ext = { \ 1088 .sublists = { \ 1089 SUBLIST_BASE, \ 1090 { \ 1091 .name = #ext, \ 1092 .feature = KVM_RISCV_ISA_EXT_##extu, \ 1093 .regs = regs_##ext, \ 1094 .regs_n = ARRAY_SIZE(regs_##ext), \ 1095 }, \ 1096 {0}, \ 1097 }, \ 1098 } \ 1099 1100 #define KVM_SBI_EXT_SIMPLE_CONFIG(ext, extu) \ 1101 static __u64 regs_sbi_##ext[] = { \ 1102 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | \ 1103 KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | \ 1104 KVM_RISCV_SBI_EXT_##extu, \ 1105 }; \ 1106 static struct vcpu_reg_list config_sbi_##ext = { \ 1107 .sublists = { \ 1108 SUBLIST_BASE, \ 1109 { \ 1110 .name = "sbi-"#ext, \ 1111 .feature_type = VCPU_FEATURE_SBI_EXT, \ 1112 .feature = KVM_RISCV_SBI_EXT_##extu, \ 1113 .regs = regs_sbi_##ext, \ 1114 .regs_n = ARRAY_SIZE(regs_sbi_##ext), \ 1115 }, \ 1116 {0}, \ 1117 }, \ 1118 } \ 1119 1120 #define KVM_ISA_EXT_SUBLIST_CONFIG(ext, extu) \ 1121 static struct vcpu_reg_list config_##ext = { \ 1122 .sublists = { \ 1123 SUBLIST_BASE, \ 1124 SUBLIST_##extu, \ 1125 {0}, \ 1126 }, \ 1127 } \ 1128 1129 #define KVM_SBI_EXT_SUBLIST_CONFIG(ext, extu) \ 1130 static struct vcpu_reg_list config_sbi_##ext = { \ 1131 .sublists = { \ 1132 SUBLIST_BASE, \ 1133 SUBLIST_SBI_##extu, \ 1134 {0}, \ 1135 }, \ 1136 } \ 1137 1138 /* Note: The below list is alphabetically sorted. */ 1139 1140 KVM_SBI_EXT_SUBLIST_CONFIG(base, BASE); 1141 KVM_SBI_EXT_SUBLIST_CONFIG(sta, STA); 1142 KVM_SBI_EXT_SIMPLE_CONFIG(pmu, PMU); 1143 KVM_SBI_EXT_SIMPLE_CONFIG(dbcn, DBCN); 1144 KVM_SBI_EXT_SIMPLE_CONFIG(susp, SUSP); 1145 KVM_SBI_EXT_SUBLIST_CONFIG(fwft, FWFT); 1146 1147 KVM_ISA_EXT_SUBLIST_CONFIG(aia, AIA); 1148 KVM_ISA_EXT_SUBLIST_CONFIG(fp_f, FP_F); 1149 KVM_ISA_EXT_SUBLIST_CONFIG(fp_d, FP_D); 1150 KVM_ISA_EXT_SUBLIST_CONFIG(v, V); 1151 KVM_ISA_EXT_SIMPLE_CONFIG(h, H); 1152 KVM_ISA_EXT_SIMPLE_CONFIG(smnpm, SMNPM); 1153 KVM_ISA_EXT_SUBLIST_CONFIG(smstateen, SMSTATEEN); 1154 KVM_ISA_EXT_SIMPLE_CONFIG(sscofpmf, SSCOFPMF); 1155 KVM_ISA_EXT_SIMPLE_CONFIG(ssnpm, SSNPM); 1156 KVM_ISA_EXT_SIMPLE_CONFIG(sstc, SSTC); 1157 KVM_ISA_EXT_SIMPLE_CONFIG(svade, SVADE); 1158 KVM_ISA_EXT_SIMPLE_CONFIG(svadu, SVADU); 1159 KVM_ISA_EXT_SIMPLE_CONFIG(svinval, SVINVAL); 1160 KVM_ISA_EXT_SIMPLE_CONFIG(svnapot, SVNAPOT); 1161 KVM_ISA_EXT_SIMPLE_CONFIG(svpbmt, SVPBMT); 1162 KVM_ISA_EXT_SIMPLE_CONFIG(svvptc, SVVPTC); 1163 KVM_ISA_EXT_SIMPLE_CONFIG(zaamo, ZAAMO); 1164 KVM_ISA_EXT_SIMPLE_CONFIG(zabha, ZABHA); 1165 KVM_ISA_EXT_SIMPLE_CONFIG(zacas, ZACAS); 1166 KVM_ISA_EXT_SIMPLE_CONFIG(zalrsc, ZALRSC); 1167 KVM_ISA_EXT_SIMPLE_CONFIG(zawrs, ZAWRS); 1168 KVM_ISA_EXT_SIMPLE_CONFIG(zba, ZBA); 1169 KVM_ISA_EXT_SIMPLE_CONFIG(zbb, ZBB); 1170 KVM_ISA_EXT_SIMPLE_CONFIG(zbc, ZBC); 1171 KVM_ISA_EXT_SIMPLE_CONFIG(zbkb, ZBKB); 1172 KVM_ISA_EXT_SIMPLE_CONFIG(zbkc, ZBKC); 1173 KVM_ISA_EXT_SIMPLE_CONFIG(zbkx, ZBKX); 1174 KVM_ISA_EXT_SIMPLE_CONFIG(zbs, ZBS); 1175 KVM_ISA_EXT_SIMPLE_CONFIG(zca, ZCA); 1176 KVM_ISA_EXT_SIMPLE_CONFIG(zcb, ZCB); 1177 KVM_ISA_EXT_SIMPLE_CONFIG(zcd, ZCD); 1178 KVM_ISA_EXT_SIMPLE_CONFIG(zcf, ZCF); 1179 KVM_ISA_EXT_SIMPLE_CONFIG(zcmop, ZCMOP); 1180 KVM_ISA_EXT_SIMPLE_CONFIG(zfa, ZFA); 1181 KVM_ISA_EXT_SIMPLE_CONFIG(zfbfmin, ZFBFMIN); 1182 KVM_ISA_EXT_SIMPLE_CONFIG(zfh, ZFH); 1183 KVM_ISA_EXT_SIMPLE_CONFIG(zfhmin, ZFHMIN); 1184 KVM_ISA_EXT_SUBLIST_CONFIG(zicbom, ZICBOM); 1185 KVM_ISA_EXT_SUBLIST_CONFIG(zicbop, ZICBOP); 1186 KVM_ISA_EXT_SUBLIST_CONFIG(zicboz, ZICBOZ); 1187 KVM_ISA_EXT_SIMPLE_CONFIG(ziccrse, ZICCRSE); 1188 KVM_ISA_EXT_SIMPLE_CONFIG(zicntr, ZICNTR); 1189 KVM_ISA_EXT_SIMPLE_CONFIG(zicond, ZICOND); 1190 KVM_ISA_EXT_SIMPLE_CONFIG(zicsr, ZICSR); 1191 KVM_ISA_EXT_SIMPLE_CONFIG(zifencei, ZIFENCEI); 1192 KVM_ISA_EXT_SIMPLE_CONFIG(zihintntl, ZIHINTNTL); 1193 KVM_ISA_EXT_SIMPLE_CONFIG(zihintpause, ZIHINTPAUSE); 1194 KVM_ISA_EXT_SIMPLE_CONFIG(zihpm, ZIHPM); 1195 KVM_ISA_EXT_SIMPLE_CONFIG(zimop, ZIMOP); 1196 KVM_ISA_EXT_SIMPLE_CONFIG(zknd, ZKND); 1197 KVM_ISA_EXT_SIMPLE_CONFIG(zkne, ZKNE); 1198 KVM_ISA_EXT_SIMPLE_CONFIG(zknh, ZKNH); 1199 KVM_ISA_EXT_SIMPLE_CONFIG(zkr, ZKR); 1200 KVM_ISA_EXT_SIMPLE_CONFIG(zksed, ZKSED); 1201 KVM_ISA_EXT_SIMPLE_CONFIG(zksh, ZKSH); 1202 KVM_ISA_EXT_SIMPLE_CONFIG(zkt, ZKT); 1203 KVM_ISA_EXT_SIMPLE_CONFIG(ztso, ZTSO); 1204 KVM_ISA_EXT_SIMPLE_CONFIG(zvbb, ZVBB); 1205 KVM_ISA_EXT_SIMPLE_CONFIG(zvbc, ZVBC); 1206 KVM_ISA_EXT_SIMPLE_CONFIG(zvfbfmin, ZVFBFMIN); 1207 KVM_ISA_EXT_SIMPLE_CONFIG(zvfbfwma, ZVFBFWMA); 1208 KVM_ISA_EXT_SIMPLE_CONFIG(zvfh, ZVFH); 1209 KVM_ISA_EXT_SIMPLE_CONFIG(zvfhmin, ZVFHMIN); 1210 KVM_ISA_EXT_SIMPLE_CONFIG(zvkb, ZVKB); 1211 KVM_ISA_EXT_SIMPLE_CONFIG(zvkg, ZVKG); 1212 KVM_ISA_EXT_SIMPLE_CONFIG(zvkned, ZVKNED); 1213 KVM_ISA_EXT_SIMPLE_CONFIG(zvknha, ZVKNHA); 1214 KVM_ISA_EXT_SIMPLE_CONFIG(zvknhb, ZVKNHB); 1215 KVM_ISA_EXT_SIMPLE_CONFIG(zvksed, ZVKSED); 1216 KVM_ISA_EXT_SIMPLE_CONFIG(zvksh, ZVKSH); 1217 KVM_ISA_EXT_SIMPLE_CONFIG(zvkt, ZVKT); 1218 1219 struct vcpu_reg_list *vcpu_configs[] = { 1220 &config_sbi_base, 1221 &config_sbi_sta, 1222 &config_sbi_pmu, 1223 &config_sbi_dbcn, 1224 &config_sbi_susp, 1225 &config_sbi_fwft, 1226 &config_aia, 1227 &config_fp_f, 1228 &config_fp_d, 1229 &config_h, 1230 &config_v, 1231 &config_smnpm, 1232 &config_smstateen, 1233 &config_sscofpmf, 1234 &config_ssnpm, 1235 &config_sstc, 1236 &config_svade, 1237 &config_svadu, 1238 &config_svinval, 1239 &config_svnapot, 1240 &config_svpbmt, 1241 &config_svvptc, 1242 &config_zaamo, 1243 &config_zabha, 1244 &config_zacas, 1245 &config_zalrsc, 1246 &config_zawrs, 1247 &config_zba, 1248 &config_zbb, 1249 &config_zbc, 1250 &config_zbkb, 1251 &config_zbkc, 1252 &config_zbkx, 1253 &config_zbs, 1254 &config_zca, 1255 &config_zcb, 1256 &config_zcd, 1257 &config_zcf, 1258 &config_zcmop, 1259 &config_zfa, 1260 &config_zfbfmin, 1261 &config_zfh, 1262 &config_zfhmin, 1263 &config_zicbom, 1264 &config_zicbop, 1265 &config_zicboz, 1266 &config_ziccrse, 1267 &config_zicntr, 1268 &config_zicond, 1269 &config_zicsr, 1270 &config_zifencei, 1271 &config_zihintntl, 1272 &config_zihintpause, 1273 &config_zihpm, 1274 &config_zimop, 1275 &config_zknd, 1276 &config_zkne, 1277 &config_zknh, 1278 &config_zkr, 1279 &config_zksed, 1280 &config_zksh, 1281 &config_zkt, 1282 &config_ztso, 1283 &config_zvbb, 1284 &config_zvbc, 1285 &config_zvfbfmin, 1286 &config_zvfbfwma, 1287 &config_zvfh, 1288 &config_zvfhmin, 1289 &config_zvkb, 1290 &config_zvkg, 1291 &config_zvkned, 1292 &config_zvknha, 1293 &config_zvknhb, 1294 &config_zvksed, 1295 &config_zvksh, 1296 &config_zvkt, 1297 }; 1298 int vcpu_configs_n = ARRAY_SIZE(vcpu_configs); 1299