1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Compaq Hot Plug Controller Driver 4 * 5 * Copyright (C) 1995,2001 Compaq Computer Corporation 6 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com) 7 * Copyright (C) 2001 IBM Corp. 8 * 9 * All rights reserved. 10 * 11 * Send feedback to <greg@kroah.com> 12 * 13 */ 14 15 #define pr_fmt(fmt) "cpqphp: " fmt 16 17 #include <linux/module.h> 18 #include <linux/kernel.h> 19 #include <linux/printk.h> 20 #include <linux/types.h> 21 #include <linux/slab.h> 22 #include <linux/workqueue.h> 23 #include <linux/proc_fs.h> 24 #include <linux/pci.h> 25 #include <linux/pci_hotplug.h> 26 #include "../pci.h" 27 #include "cpqphp.h" 28 #include "cpqphp_nvram.h" 29 30 31 u8 cpqhp_nic_irq; 32 u8 cpqhp_disk_irq; 33 34 static u16 unused_IRQ; 35 36 /* 37 * detect_HRT_floating_pointer 38 * 39 * find the Hot Plug Resource Table in the specified region of memory. 40 * 41 */ 42 static void __iomem *detect_HRT_floating_pointer(void __iomem *begin, void __iomem *end) 43 { 44 void __iomem *fp; 45 void __iomem *endp; 46 u8 temp1, temp2, temp3, temp4; 47 int status = 0; 48 49 endp = (end - sizeof(struct hrt) + 1); 50 51 for (fp = begin; fp <= endp; fp += 16) { 52 temp1 = readb(fp + SIG0); 53 temp2 = readb(fp + SIG1); 54 temp3 = readb(fp + SIG2); 55 temp4 = readb(fp + SIG3); 56 if (temp1 == '$' && 57 temp2 == 'H' && 58 temp3 == 'R' && 59 temp4 == 'T') { 60 status = 1; 61 break; 62 } 63 } 64 65 if (!status) 66 fp = NULL; 67 68 dbg("Discovered Hotplug Resource Table at %p\n", fp); 69 return fp; 70 } 71 72 73 int cpqhp_configure_device(struct controller *ctrl, struct pci_func *func) 74 { 75 struct pci_bus *child; 76 int num; 77 78 pci_lock_rescan_remove(); 79 80 if (func->pci_dev == NULL) 81 func->pci_dev = pci_get_domain_bus_and_slot(0, func->bus, 82 PCI_DEVFN(func->device, 83 func->function)); 84 85 /* No pci device, we need to create it then */ 86 if (func->pci_dev == NULL) { 87 dbg("INFO: pci_dev still null\n"); 88 89 num = pci_scan_slot(ctrl->pci_dev->bus, PCI_DEVFN(func->device, func->function)); 90 if (num) 91 pci_bus_add_devices(ctrl->pci_dev->bus); 92 93 func->pci_dev = pci_get_domain_bus_and_slot(0, func->bus, 94 PCI_DEVFN(func->device, 95 func->function)); 96 if (func->pci_dev == NULL) { 97 dbg("ERROR: pci_dev still null\n"); 98 goto out; 99 } 100 } 101 102 if (func->pci_dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { 103 pci_hp_add_bridge(func->pci_dev); 104 child = func->pci_dev->subordinate; 105 if (child) 106 pci_bus_add_devices(child); 107 } 108 109 pci_dev_put(func->pci_dev); 110 111 out: 112 pci_unlock_rescan_remove(); 113 return 0; 114 } 115 116 117 int cpqhp_unconfigure_device(struct pci_func *func) 118 { 119 int j; 120 121 dbg("%s: bus/dev/func = %x/%x/%x\n", __func__, func->bus, func->device, func->function); 122 123 pci_lock_rescan_remove(); 124 for (j = 0; j < 8 ; j++) { 125 struct pci_dev *temp = pci_get_domain_bus_and_slot(0, 126 func->bus, 127 PCI_DEVFN(func->device, 128 j)); 129 if (temp) { 130 pci_dev_put(temp); 131 pci_stop_and_remove_bus_device(temp); 132 } 133 } 134 pci_unlock_rescan_remove(); 135 return 0; 136 } 137 138 /* 139 * cpqhp_set_irq 140 * 141 * @bus_num: bus number of PCI device 142 * @dev_num: device number of PCI device 143 * @slot: pointer to u8 where slot number will be returned 144 */ 145 int cpqhp_set_irq(u8 bus_num, u8 dev_num, u8 int_pin, u8 irq_num) 146 { 147 int rc = 0; 148 149 if (cpqhp_legacy_mode) { 150 struct pci_dev *fakedev; 151 struct pci_bus *fakebus; 152 u16 temp_word; 153 154 fakedev = kmalloc_obj(*fakedev); 155 fakebus = kmalloc_obj(*fakebus); 156 if (!fakedev || !fakebus) { 157 kfree(fakedev); 158 kfree(fakebus); 159 return -ENOMEM; 160 } 161 162 fakedev->devfn = dev_num << 3; 163 fakedev->bus = fakebus; 164 fakebus->number = bus_num; 165 dbg("%s: dev %d, bus %d, pin %d, num %d\n", 166 __func__, dev_num, bus_num, int_pin, irq_num); 167 rc = pcibios_set_irq_routing(fakedev, int_pin - 1, irq_num); 168 kfree(fakedev); 169 kfree(fakebus); 170 dbg("%s: rc %d\n", __func__, rc); 171 if (!rc) 172 return !rc; 173 174 /* set the Edge Level Control Register (ELCR) */ 175 temp_word = inb(0x4d0); 176 temp_word |= inb(0x4d1) << 8; 177 178 temp_word |= 0x01 << irq_num; 179 180 /* This should only be for x86 as it sets the Edge Level 181 * Control Register 182 */ 183 outb((u8)(temp_word & 0xFF), 0x4d0); 184 outb((u8)((temp_word & 0xFF00) >> 8), 0x4d1); 185 rc = 0; 186 } 187 188 return rc; 189 } 190 191 192 static int PCI_ScanBusForNonBridge(struct controller *ctrl, u8 bus_num, u8 *dev_num) 193 { 194 u16 tdevice; 195 u32 work; 196 int ret = -1; 197 198 ctrl->pci_bus->number = bus_num; 199 200 for (tdevice = 0; tdevice < 0xFF; tdevice++) { 201 /* Scan for access first */ 202 if (!pci_bus_read_dev_vendor_id(ctrl->pci_bus, tdevice, &work, 0)) 203 continue; 204 ret = pci_bus_read_config_dword(ctrl->pci_bus, tdevice, PCI_CLASS_REVISION, &work); 205 if (ret) 206 continue; 207 dbg("Looking for nonbridge bus_num %d dev_num %d\n", bus_num, tdevice); 208 /* Yep we got one. Not a bridge ? */ 209 if ((work >> 8) != PCI_TO_PCI_BRIDGE_CLASS) { 210 *dev_num = tdevice; 211 dbg("found it !\n"); 212 return 0; 213 } else { 214 /* 215 * XXX: Code whose debug printout indicated 216 * recursion to buses underneath bridges might be 217 * necessary was removed because it never did 218 * any recursion. 219 */ 220 ret = 0; 221 pr_warn("missing feature: bridge scan recursion not implemented\n"); 222 } 223 } 224 225 226 return ret; 227 } 228 229 230 static int PCI_GetBusDevHelper(struct controller *ctrl, u8 *bus_num, u8 *dev_num, u8 slot, u8 nobridge) 231 { 232 int loop, len; 233 u32 work; 234 u8 tbus, tdevice, tslot; 235 236 len = cpqhp_routing_table_length(); 237 for (loop = 0; loop < len; ++loop) { 238 tbus = cpqhp_routing_table->slots[loop].bus; 239 tdevice = cpqhp_routing_table->slots[loop].devfn; 240 tslot = cpqhp_routing_table->slots[loop].slot; 241 242 if (tslot == slot) { 243 *bus_num = tbus; 244 *dev_num = tdevice; 245 ctrl->pci_bus->number = tbus; 246 pci_bus_read_config_dword(ctrl->pci_bus, *dev_num, PCI_VENDOR_ID, &work); 247 if (!nobridge || PCI_POSSIBLE_ERROR(work)) 248 return 0; 249 250 dbg("bus_num %d devfn %d\n", *bus_num, *dev_num); 251 pci_bus_read_config_dword(ctrl->pci_bus, *dev_num, PCI_CLASS_REVISION, &work); 252 dbg("work >> 8 (%x) = BRIDGE (%x)\n", work >> 8, PCI_TO_PCI_BRIDGE_CLASS); 253 254 if ((work >> 8) == PCI_TO_PCI_BRIDGE_CLASS) { 255 pci_bus_read_config_byte(ctrl->pci_bus, *dev_num, PCI_SECONDARY_BUS, &tbus); 256 dbg("Scan bus for Non Bridge: bus %d\n", tbus); 257 if (PCI_ScanBusForNonBridge(ctrl, tbus, dev_num) == 0) { 258 *bus_num = tbus; 259 return 0; 260 } 261 } else 262 return 0; 263 } 264 } 265 return -1; 266 } 267 268 269 int cpqhp_get_bus_dev(struct controller *ctrl, u8 *bus_num, u8 *dev_num, u8 slot) 270 { 271 /* plain (bridges allowed) */ 272 return PCI_GetBusDevHelper(ctrl, bus_num, dev_num, slot, 0); 273 } 274 275 276 /* More PCI configuration routines; this time centered around hotplug 277 * controller 278 */ 279 280 281 /* 282 * cpqhp_save_config 283 * 284 * Reads configuration for all slots in a PCI bus and saves info. 285 * 286 * Note: For non-hot plug buses, the slot # saved is the device # 287 * 288 * returns 0 if success 289 */ 290 int cpqhp_save_config(struct controller *ctrl, int busnumber, int is_hot_plug) 291 { 292 long rc; 293 u8 class_code; 294 u8 header_type; 295 u32 ID; 296 u8 secondary_bus; 297 struct pci_func *new_slot; 298 int sub_bus; 299 int FirstSupported; 300 int LastSupported; 301 int max_functions; 302 int function; 303 u8 DevError; 304 int device = 0; 305 int cloop = 0; 306 int stop_it; 307 int index; 308 u16 devfn; 309 310 /* Decide which slots are supported */ 311 312 if (is_hot_plug) { 313 /* 314 * is_hot_plug is the slot mask 315 */ 316 FirstSupported = is_hot_plug >> 4; 317 LastSupported = FirstSupported + (is_hot_plug & 0x0F) - 1; 318 } else { 319 FirstSupported = 0; 320 LastSupported = 0x1F; 321 } 322 323 /* Save PCI configuration space for all devices in supported slots */ 324 ctrl->pci_bus->number = busnumber; 325 for (device = FirstSupported; device <= LastSupported; device++) { 326 ID = 0xFFFFFFFF; 327 rc = pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(device, 0), PCI_VENDOR_ID, &ID); 328 329 if (ID == 0xFFFFFFFF) { 330 if (is_hot_plug) { 331 /* Setup slot structure with entry for empty 332 * slot 333 */ 334 new_slot = cpqhp_slot_create(busnumber); 335 if (new_slot == NULL) 336 return 1; 337 338 new_slot->bus = (u8) busnumber; 339 new_slot->device = (u8) device; 340 new_slot->function = 0; 341 new_slot->is_a_board = 0; 342 new_slot->presence_save = 0; 343 new_slot->switch_save = 0; 344 } 345 continue; 346 } 347 348 rc = pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(device, 0), 0x0B, &class_code); 349 if (rc) 350 return rc; 351 352 rc = pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(device, 0), PCI_HEADER_TYPE, &header_type); 353 if (rc) 354 return rc; 355 356 /* If multi-function device, set max_functions to 8 */ 357 if (header_type & PCI_HEADER_TYPE_MFD) 358 max_functions = 8; 359 else 360 max_functions = 1; 361 362 function = 0; 363 364 do { 365 DevError = 0; 366 if ((header_type & PCI_HEADER_TYPE_MASK) == PCI_HEADER_TYPE_BRIDGE) { 367 /* Recurse the subordinate bus 368 * get the subordinate bus number 369 */ 370 rc = pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(device, function), PCI_SECONDARY_BUS, &secondary_bus); 371 if (rc) { 372 return rc; 373 } else { 374 sub_bus = (int) secondary_bus; 375 376 /* Save secondary bus cfg spc 377 * with this recursive call. 378 */ 379 rc = cpqhp_save_config(ctrl, sub_bus, 0); 380 if (rc) 381 return rc; 382 ctrl->pci_bus->number = busnumber; 383 } 384 } 385 386 index = 0; 387 new_slot = cpqhp_slot_find(busnumber, device, index++); 388 while (new_slot && 389 (new_slot->function != (u8) function)) 390 new_slot = cpqhp_slot_find(busnumber, device, index++); 391 392 if (!new_slot) { 393 /* Setup slot structure. */ 394 new_slot = cpqhp_slot_create(busnumber); 395 if (new_slot == NULL) 396 return 1; 397 } 398 399 new_slot->bus = (u8) busnumber; 400 new_slot->device = (u8) device; 401 new_slot->function = (u8) function; 402 new_slot->is_a_board = 1; 403 new_slot->switch_save = 0x10; 404 /* In case of unsupported board */ 405 new_slot->status = DevError; 406 devfn = (new_slot->device << 3) | new_slot->function; 407 new_slot->pci_dev = pci_get_domain_bus_and_slot(0, 408 new_slot->bus, devfn); 409 410 for (cloop = 0; cloop < 0x20; cloop++) { 411 rc = pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(device, function), cloop << 2, (u32 *) &(new_slot->config_space[cloop])); 412 if (rc) 413 return rc; 414 } 415 416 pci_dev_put(new_slot->pci_dev); 417 418 function++; 419 420 stop_it = 0; 421 422 /* this loop skips to the next present function 423 * reading in Class Code and Header type. 424 */ 425 while ((function < max_functions) && (!stop_it)) { 426 rc = pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(device, function), PCI_VENDOR_ID, &ID); 427 if (ID == 0xFFFFFFFF) { 428 function++; 429 continue; 430 } 431 rc = pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(device, function), 0x0B, &class_code); 432 if (rc) 433 return rc; 434 435 rc = pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(device, function), PCI_HEADER_TYPE, &header_type); 436 if (rc) 437 return rc; 438 439 stop_it++; 440 } 441 442 } while (function < max_functions); 443 } /* End of FOR loop */ 444 445 return 0; 446 } 447 448 449 /* 450 * cpqhp_save_slot_config 451 * 452 * Saves configuration info for all PCI devices in a given slot 453 * including subordinate buses. 454 * 455 * returns 0 if success 456 */ 457 int cpqhp_save_slot_config(struct controller *ctrl, struct pci_func *new_slot) 458 { 459 long rc; 460 u8 class_code; 461 u8 header_type; 462 u32 ID; 463 u8 secondary_bus; 464 int sub_bus; 465 int max_functions; 466 int function = 0; 467 int cloop; 468 int stop_it; 469 470 ID = 0xFFFFFFFF; 471 472 ctrl->pci_bus->number = new_slot->bus; 473 pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(new_slot->device, 0), PCI_VENDOR_ID, &ID); 474 475 if (ID == 0xFFFFFFFF) 476 return 2; 477 478 pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, 0), 0x0B, &class_code); 479 pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, 0), PCI_HEADER_TYPE, &header_type); 480 481 if (header_type & PCI_HEADER_TYPE_MFD) 482 max_functions = 8; 483 else 484 max_functions = 1; 485 486 while (function < max_functions) { 487 if ((header_type & PCI_HEADER_TYPE_MASK) == PCI_HEADER_TYPE_BRIDGE) { 488 /* Recurse the subordinate bus */ 489 pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), PCI_SECONDARY_BUS, &secondary_bus); 490 491 sub_bus = (int) secondary_bus; 492 493 /* Save the config headers for the secondary 494 * bus. 495 */ 496 rc = cpqhp_save_config(ctrl, sub_bus, 0); 497 if (rc) 498 return(rc); 499 ctrl->pci_bus->number = new_slot->bus; 500 501 } 502 503 new_slot->status = 0; 504 505 for (cloop = 0; cloop < 0x20; cloop++) 506 pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), cloop << 2, (u32 *) &(new_slot->config_space[cloop])); 507 508 function++; 509 510 stop_it = 0; 511 512 /* this loop skips to the next present function 513 * reading in the Class Code and the Header type. 514 */ 515 while ((function < max_functions) && (!stop_it)) { 516 pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), PCI_VENDOR_ID, &ID); 517 518 if (ID == 0xFFFFFFFF) 519 function++; 520 else { 521 pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), 0x0B, &class_code); 522 pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), PCI_HEADER_TYPE, &header_type); 523 stop_it++; 524 } 525 } 526 527 } 528 529 return 0; 530 } 531 532 533 /* 534 * cpqhp_save_base_addr_length 535 * 536 * Saves the length of all base address registers for the 537 * specified slot. this is for hot plug REPLACE 538 * 539 * returns 0 if success 540 */ 541 int cpqhp_save_base_addr_length(struct controller *ctrl, struct pci_func *func) 542 { 543 u8 cloop; 544 u8 header_type; 545 u8 secondary_bus; 546 u8 type; 547 int sub_bus; 548 u32 temp_register; 549 u32 base; 550 u32 rc; 551 struct pci_func *next; 552 int index = 0; 553 struct pci_bus *pci_bus = ctrl->pci_bus; 554 unsigned int devfn; 555 556 func = cpqhp_slot_find(func->bus, func->device, index++); 557 558 while (func != NULL) { 559 pci_bus->number = func->bus; 560 devfn = PCI_DEVFN(func->device, func->function); 561 562 /* Check for Bridge */ 563 pci_bus_read_config_byte(pci_bus, devfn, PCI_HEADER_TYPE, &header_type); 564 565 if ((header_type & PCI_HEADER_TYPE_MASK) == PCI_HEADER_TYPE_BRIDGE) { 566 pci_bus_read_config_byte(pci_bus, devfn, PCI_SECONDARY_BUS, &secondary_bus); 567 568 sub_bus = (int) secondary_bus; 569 570 next = cpqhp_slot_list[sub_bus]; 571 572 while (next != NULL) { 573 rc = cpqhp_save_base_addr_length(ctrl, next); 574 if (rc) 575 return rc; 576 577 next = next->next; 578 } 579 pci_bus->number = func->bus; 580 581 /* FIXME: this loop is duplicated in the non-bridge 582 * case. The two could be rolled together Figure out 583 * IO and memory base lengths 584 */ 585 for (cloop = 0x10; cloop <= 0x14; cloop += 4) { 586 temp_register = 0xFFFFFFFF; 587 pci_bus_write_config_dword(pci_bus, devfn, cloop, temp_register); 588 pci_bus_read_config_dword(pci_bus, devfn, cloop, &base); 589 /* If this register is implemented */ 590 if (base) { 591 if (base & 0x01L) { 592 /* IO base 593 * set base = amount of IO space 594 * requested 595 */ 596 base = base & 0xFFFFFFFE; 597 base = (~base) + 1; 598 599 type = 1; 600 } else { 601 /* memory base */ 602 base = base & 0xFFFFFFF0; 603 base = (~base) + 1; 604 605 type = 0; 606 } 607 } else { 608 base = 0x0L; 609 type = 0; 610 } 611 612 /* Save information in slot structure */ 613 func->base_length[(cloop - 0x10) >> 2] = 614 base; 615 func->base_type[(cloop - 0x10) >> 2] = type; 616 617 } /* End of base register loop */ 618 619 } else if ((header_type & PCI_HEADER_TYPE_MASK) == PCI_HEADER_TYPE_NORMAL) { 620 /* Figure out IO and memory base lengths */ 621 for (cloop = 0x10; cloop <= 0x24; cloop += 4) { 622 temp_register = 0xFFFFFFFF; 623 pci_bus_write_config_dword(pci_bus, devfn, cloop, temp_register); 624 pci_bus_read_config_dword(pci_bus, devfn, cloop, &base); 625 626 /* If this register is implemented */ 627 if (base) { 628 if (base & 0x01L) { 629 /* IO base 630 * base = amount of IO space 631 * requested 632 */ 633 base = base & 0xFFFFFFFE; 634 base = (~base) + 1; 635 636 type = 1; 637 } else { 638 /* memory base 639 * base = amount of memory 640 * space requested 641 */ 642 base = base & 0xFFFFFFF0; 643 base = (~base) + 1; 644 645 type = 0; 646 } 647 } else { 648 base = 0x0L; 649 type = 0; 650 } 651 652 /* Save information in slot structure */ 653 func->base_length[(cloop - 0x10) >> 2] = base; 654 func->base_type[(cloop - 0x10) >> 2] = type; 655 656 } /* End of base register loop */ 657 658 } else { /* Some other unknown header type */ 659 } 660 661 /* find the next device in this slot */ 662 func = cpqhp_slot_find(func->bus, func->device, index++); 663 } 664 665 return(0); 666 } 667 668 669 /* 670 * cpqhp_save_used_resources 671 * 672 * Stores used resource information for existing boards. this is 673 * for boards that were in the system when this driver was loaded. 674 * this function is for hot plug ADD 675 * 676 * returns 0 if success 677 */ 678 int cpqhp_save_used_resources(struct controller *ctrl, struct pci_func *func) 679 { 680 u8 cloop; 681 u8 header_type; 682 u8 secondary_bus; 683 u8 temp_byte; 684 u8 b_base; 685 u8 b_length; 686 u16 command; 687 u16 save_command; 688 u16 w_base; 689 u16 w_length; 690 u32 temp_register; 691 u32 save_base; 692 u32 base; 693 int index = 0; 694 struct pci_resource *mem_node; 695 struct pci_resource *p_mem_node; 696 struct pci_resource *io_node; 697 struct pci_resource *bus_node; 698 struct pci_bus *pci_bus = ctrl->pci_bus; 699 unsigned int devfn; 700 701 func = cpqhp_slot_find(func->bus, func->device, index++); 702 703 while ((func != NULL) && func->is_a_board) { 704 pci_bus->number = func->bus; 705 devfn = PCI_DEVFN(func->device, func->function); 706 707 /* Save the command register */ 708 pci_bus_read_config_word(pci_bus, devfn, PCI_COMMAND, &save_command); 709 710 /* disable card */ 711 command = 0x00; 712 pci_bus_write_config_word(pci_bus, devfn, PCI_COMMAND, command); 713 714 /* Check for Bridge */ 715 pci_bus_read_config_byte(pci_bus, devfn, PCI_HEADER_TYPE, &header_type); 716 717 if ((header_type & PCI_HEADER_TYPE_MASK) == PCI_HEADER_TYPE_BRIDGE) { 718 /* Clear Bridge Control Register */ 719 command = 0x00; 720 pci_bus_write_config_word(pci_bus, devfn, PCI_BRIDGE_CONTROL, command); 721 pci_bus_read_config_byte(pci_bus, devfn, PCI_SECONDARY_BUS, &secondary_bus); 722 pci_bus_read_config_byte(pci_bus, devfn, PCI_SUBORDINATE_BUS, &temp_byte); 723 724 bus_node = kmalloc_obj(*bus_node); 725 if (!bus_node) 726 return -ENOMEM; 727 728 bus_node->base = secondary_bus; 729 bus_node->length = temp_byte - secondary_bus + 1; 730 731 bus_node->next = func->bus_head; 732 func->bus_head = bus_node; 733 734 /* Save IO base and Limit registers */ 735 pci_bus_read_config_byte(pci_bus, devfn, PCI_IO_BASE, &b_base); 736 pci_bus_read_config_byte(pci_bus, devfn, PCI_IO_LIMIT, &b_length); 737 738 if ((b_base <= b_length) && (save_command & 0x01)) { 739 io_node = kmalloc_obj(*io_node); 740 if (!io_node) 741 return -ENOMEM; 742 743 io_node->base = (b_base & 0xF0) << 8; 744 io_node->length = (b_length - b_base + 0x10) << 8; 745 746 io_node->next = func->io_head; 747 func->io_head = io_node; 748 } 749 750 /* Save memory base and Limit registers */ 751 pci_bus_read_config_word(pci_bus, devfn, PCI_MEMORY_BASE, &w_base); 752 pci_bus_read_config_word(pci_bus, devfn, PCI_MEMORY_LIMIT, &w_length); 753 754 if ((w_base <= w_length) && (save_command & 0x02)) { 755 mem_node = kmalloc_obj(*mem_node); 756 if (!mem_node) 757 return -ENOMEM; 758 759 mem_node->base = w_base << 16; 760 mem_node->length = (w_length - w_base + 0x10) << 16; 761 762 mem_node->next = func->mem_head; 763 func->mem_head = mem_node; 764 } 765 766 /* Save prefetchable memory base and Limit registers */ 767 pci_bus_read_config_word(pci_bus, devfn, PCI_PREF_MEMORY_BASE, &w_base); 768 pci_bus_read_config_word(pci_bus, devfn, PCI_PREF_MEMORY_LIMIT, &w_length); 769 770 if ((w_base <= w_length) && (save_command & 0x02)) { 771 p_mem_node = kmalloc_obj(*p_mem_node); 772 if (!p_mem_node) 773 return -ENOMEM; 774 775 p_mem_node->base = w_base << 16; 776 p_mem_node->length = (w_length - w_base + 0x10) << 16; 777 778 p_mem_node->next = func->p_mem_head; 779 func->p_mem_head = p_mem_node; 780 } 781 /* Figure out IO and memory base lengths */ 782 for (cloop = 0x10; cloop <= 0x14; cloop += 4) { 783 pci_bus_read_config_dword(pci_bus, devfn, cloop, &save_base); 784 785 temp_register = 0xFFFFFFFF; 786 pci_bus_write_config_dword(pci_bus, devfn, cloop, temp_register); 787 pci_bus_read_config_dword(pci_bus, devfn, cloop, &base); 788 789 temp_register = base; 790 791 /* If this register is implemented */ 792 if (base) { 793 if (((base & 0x03L) == 0x01) 794 && (save_command & 0x01)) { 795 /* IO base 796 * set temp_register = amount 797 * of IO space requested 798 */ 799 temp_register = base & 0xFFFFFFFE; 800 temp_register = (~temp_register) + 1; 801 802 io_node = kmalloc_obj(*io_node); 803 if (!io_node) 804 return -ENOMEM; 805 806 io_node->base = 807 save_base & (~0x03L); 808 io_node->length = temp_register; 809 810 io_node->next = func->io_head; 811 func->io_head = io_node; 812 } else 813 if (((base & 0x0BL) == 0x08) 814 && (save_command & 0x02)) { 815 /* prefetchable memory base */ 816 temp_register = base & 0xFFFFFFF0; 817 temp_register = (~temp_register) + 1; 818 819 p_mem_node = kmalloc_obj(*p_mem_node); 820 if (!p_mem_node) 821 return -ENOMEM; 822 823 p_mem_node->base = save_base & (~0x0FL); 824 p_mem_node->length = temp_register; 825 826 p_mem_node->next = func->p_mem_head; 827 func->p_mem_head = p_mem_node; 828 } else 829 if (((base & 0x0BL) == 0x00) 830 && (save_command & 0x02)) { 831 /* prefetchable memory base */ 832 temp_register = base & 0xFFFFFFF0; 833 temp_register = (~temp_register) + 1; 834 835 mem_node = kmalloc_obj(*mem_node); 836 if (!mem_node) 837 return -ENOMEM; 838 839 mem_node->base = save_base & (~0x0FL); 840 mem_node->length = temp_register; 841 842 mem_node->next = func->mem_head; 843 func->mem_head = mem_node; 844 } else 845 return(1); 846 } 847 } /* End of base register loop */ 848 /* Standard header */ 849 } else if ((header_type & PCI_HEADER_TYPE_MASK) == PCI_HEADER_TYPE_NORMAL) { 850 /* Figure out IO and memory base lengths */ 851 for (cloop = 0x10; cloop <= 0x24; cloop += 4) { 852 pci_bus_read_config_dword(pci_bus, devfn, cloop, &save_base); 853 854 temp_register = 0xFFFFFFFF; 855 pci_bus_write_config_dword(pci_bus, devfn, cloop, temp_register); 856 pci_bus_read_config_dword(pci_bus, devfn, cloop, &base); 857 858 temp_register = base; 859 860 /* If this register is implemented */ 861 if (base) { 862 if (((base & 0x03L) == 0x01) 863 && (save_command & 0x01)) { 864 /* IO base 865 * set temp_register = amount 866 * of IO space requested 867 */ 868 temp_register = base & 0xFFFFFFFE; 869 temp_register = (~temp_register) + 1; 870 871 io_node = kmalloc_obj(*io_node); 872 if (!io_node) 873 return -ENOMEM; 874 875 io_node->base = save_base & (~0x01L); 876 io_node->length = temp_register; 877 878 io_node->next = func->io_head; 879 func->io_head = io_node; 880 } else 881 if (((base & 0x0BL) == 0x08) 882 && (save_command & 0x02)) { 883 /* prefetchable memory base */ 884 temp_register = base & 0xFFFFFFF0; 885 temp_register = (~temp_register) + 1; 886 887 p_mem_node = kmalloc_obj(*p_mem_node); 888 if (!p_mem_node) 889 return -ENOMEM; 890 891 p_mem_node->base = save_base & (~0x0FL); 892 p_mem_node->length = temp_register; 893 894 p_mem_node->next = func->p_mem_head; 895 func->p_mem_head = p_mem_node; 896 } else 897 if (((base & 0x0BL) == 0x00) 898 && (save_command & 0x02)) { 899 /* prefetchable memory base */ 900 temp_register = base & 0xFFFFFFF0; 901 temp_register = (~temp_register) + 1; 902 903 mem_node = kmalloc_obj(*mem_node); 904 if (!mem_node) 905 return -ENOMEM; 906 907 mem_node->base = save_base & (~0x0FL); 908 mem_node->length = temp_register; 909 910 mem_node->next = func->mem_head; 911 func->mem_head = mem_node; 912 } else 913 return(1); 914 } 915 } /* End of base register loop */ 916 } 917 918 /* find the next device in this slot */ 919 func = cpqhp_slot_find(func->bus, func->device, index++); 920 } 921 922 return 0; 923 } 924 925 926 /* 927 * cpqhp_configure_board 928 * 929 * Copies saved configuration information to one slot. 930 * this is called recursively for bridge devices. 931 * this is for hot plug REPLACE! 932 * 933 * returns 0 if success 934 */ 935 int cpqhp_configure_board(struct controller *ctrl, struct pci_func *func) 936 { 937 int cloop; 938 u8 header_type; 939 u8 secondary_bus; 940 int sub_bus; 941 struct pci_func *next; 942 u32 temp; 943 u32 rc; 944 int index = 0; 945 struct pci_bus *pci_bus = ctrl->pci_bus; 946 unsigned int devfn; 947 948 func = cpqhp_slot_find(func->bus, func->device, index++); 949 950 while (func != NULL) { 951 pci_bus->number = func->bus; 952 devfn = PCI_DEVFN(func->device, func->function); 953 954 /* Start at the top of config space so that the control 955 * registers are programmed last 956 */ 957 for (cloop = 0x3C; cloop > 0; cloop -= 4) 958 pci_bus_write_config_dword(pci_bus, devfn, cloop, func->config_space[cloop >> 2]); 959 960 pci_bus_read_config_byte(pci_bus, devfn, PCI_HEADER_TYPE, &header_type); 961 962 /* If this is a bridge device, restore subordinate devices */ 963 if ((header_type & PCI_HEADER_TYPE_MASK) == PCI_HEADER_TYPE_BRIDGE) { 964 pci_bus_read_config_byte(pci_bus, devfn, PCI_SECONDARY_BUS, &secondary_bus); 965 966 sub_bus = (int) secondary_bus; 967 968 next = cpqhp_slot_list[sub_bus]; 969 970 while (next != NULL) { 971 rc = cpqhp_configure_board(ctrl, next); 972 if (rc) 973 return rc; 974 975 next = next->next; 976 } 977 } else { 978 979 /* Check all the base Address Registers to make sure 980 * they are the same. If not, the board is different. 981 */ 982 983 for (cloop = 16; cloop < 40; cloop += 4) { 984 pci_bus_read_config_dword(pci_bus, devfn, cloop, &temp); 985 986 if (temp != func->config_space[cloop >> 2]) { 987 dbg("Config space compare failure!!! offset = %x\n", cloop); 988 dbg("bus = %x, device = %x, function = %x\n", func->bus, func->device, func->function); 989 dbg("temp = %x, config space = %x\n\n", temp, func->config_space[cloop >> 2]); 990 return 1; 991 } 992 } 993 } 994 995 func->configured = 1; 996 997 func = cpqhp_slot_find(func->bus, func->device, index++); 998 } 999 1000 return 0; 1001 } 1002 1003 1004 /* 1005 * cpqhp_valid_replace 1006 * 1007 * this function checks to see if a board is the same as the 1008 * one it is replacing. this check will detect if the device's 1009 * vendor or device id's are the same 1010 * 1011 * returns 0 if the board is the same nonzero otherwise 1012 */ 1013 int cpqhp_valid_replace(struct controller *ctrl, struct pci_func *func) 1014 { 1015 u8 cloop; 1016 u8 header_type; 1017 u8 secondary_bus; 1018 u8 type; 1019 u32 temp_register = 0; 1020 u32 base; 1021 u32 rc; 1022 struct pci_func *next; 1023 int index = 0; 1024 struct pci_bus *pci_bus = ctrl->pci_bus; 1025 unsigned int devfn; 1026 1027 if (!func->is_a_board) 1028 return(ADD_NOT_SUPPORTED); 1029 1030 func = cpqhp_slot_find(func->bus, func->device, index++); 1031 1032 while (func != NULL) { 1033 pci_bus->number = func->bus; 1034 devfn = PCI_DEVFN(func->device, func->function); 1035 1036 pci_bus_read_config_dword(pci_bus, devfn, PCI_VENDOR_ID, &temp_register); 1037 1038 /* No adapter present */ 1039 if (temp_register == 0xFFFFFFFF) 1040 return(NO_ADAPTER_PRESENT); 1041 1042 if (temp_register != func->config_space[0]) 1043 return(ADAPTER_NOT_SAME); 1044 1045 /* Check for same revision number and class code */ 1046 pci_bus_read_config_dword(pci_bus, devfn, PCI_CLASS_REVISION, &temp_register); 1047 1048 /* Adapter not the same */ 1049 if (temp_register != func->config_space[0x08 >> 2]) 1050 return(ADAPTER_NOT_SAME); 1051 1052 /* Check for Bridge */ 1053 pci_bus_read_config_byte(pci_bus, devfn, PCI_HEADER_TYPE, &header_type); 1054 1055 if ((header_type & PCI_HEADER_TYPE_MASK) == PCI_HEADER_TYPE_BRIDGE) { 1056 /* In order to continue checking, we must program the 1057 * bus registers in the bridge to respond to accesses 1058 * for its subordinate bus(es) 1059 */ 1060 1061 temp_register = func->config_space[0x18 >> 2]; 1062 pci_bus_write_config_dword(pci_bus, devfn, PCI_PRIMARY_BUS, temp_register); 1063 1064 secondary_bus = (temp_register >> 8) & 0xFF; 1065 1066 next = cpqhp_slot_list[secondary_bus]; 1067 1068 while (next != NULL) { 1069 rc = cpqhp_valid_replace(ctrl, next); 1070 if (rc) 1071 return rc; 1072 1073 next = next->next; 1074 } 1075 1076 } 1077 /* Check to see if it is a standard config header */ 1078 else if ((header_type & PCI_HEADER_TYPE_MASK) == PCI_HEADER_TYPE_NORMAL) { 1079 /* Check subsystem vendor and ID */ 1080 pci_bus_read_config_dword(pci_bus, devfn, PCI_SUBSYSTEM_VENDOR_ID, &temp_register); 1081 1082 if (temp_register != func->config_space[0x2C >> 2]) { 1083 /* If it's a SMART-2 and the register isn't 1084 * filled in, ignore the difference because 1085 * they just have an old rev of the firmware 1086 */ 1087 if (!((func->config_space[0] == 0xAE100E11) 1088 && (temp_register == 0x00L))) 1089 return(ADAPTER_NOT_SAME); 1090 } 1091 /* Figure out IO and memory base lengths */ 1092 for (cloop = 0x10; cloop <= 0x24; cloop += 4) { 1093 temp_register = 0xFFFFFFFF; 1094 pci_bus_write_config_dword(pci_bus, devfn, cloop, temp_register); 1095 pci_bus_read_config_dword(pci_bus, devfn, cloop, &base); 1096 1097 /* If this register is implemented */ 1098 if (base) { 1099 if (base & 0x01L) { 1100 /* IO base 1101 * set base = amount of IO 1102 * space requested 1103 */ 1104 base = base & 0xFFFFFFFE; 1105 base = (~base) + 1; 1106 1107 type = 1; 1108 } else { 1109 /* memory base */ 1110 base = base & 0xFFFFFFF0; 1111 base = (~base) + 1; 1112 1113 type = 0; 1114 } 1115 } else { 1116 base = 0x0L; 1117 type = 0; 1118 } 1119 1120 /* Check information in slot structure */ 1121 if (func->base_length[(cloop - 0x10) >> 2] != base) 1122 return(ADAPTER_NOT_SAME); 1123 1124 if (func->base_type[(cloop - 0x10) >> 2] != type) 1125 return(ADAPTER_NOT_SAME); 1126 1127 } /* End of base register loop */ 1128 1129 } /* End of (type 0 config space) else */ 1130 else { 1131 /* this is not a type 0 or 1 config space header so 1132 * we don't know how to do it 1133 */ 1134 return(DEVICE_TYPE_NOT_SUPPORTED); 1135 } 1136 1137 /* Get the next function */ 1138 func = cpqhp_slot_find(func->bus, func->device, index++); 1139 } 1140 1141 1142 return 0; 1143 } 1144 1145 1146 /* 1147 * cpqhp_find_available_resources 1148 * 1149 * Finds available memory, IO, and IRQ resources for programming 1150 * devices which may be added to the system 1151 * this function is for hot plug ADD! 1152 * 1153 * returns 0 if success 1154 */ 1155 int cpqhp_find_available_resources(struct controller *ctrl, void __iomem *rom_start) 1156 { 1157 u8 temp; 1158 u8 populated_slot; 1159 u8 bridged_slot; 1160 void __iomem *one_slot; 1161 void __iomem *rom_resource_table; 1162 struct pci_func *func = NULL; 1163 int i = 10, index; 1164 u32 temp_dword, rc; 1165 struct pci_resource *mem_node; 1166 struct pci_resource *p_mem_node; 1167 struct pci_resource *io_node; 1168 struct pci_resource *bus_node; 1169 1170 rom_resource_table = detect_HRT_floating_pointer(rom_start, rom_start+0xffff); 1171 dbg("rom_resource_table = %p\n", rom_resource_table); 1172 1173 if (rom_resource_table == NULL) 1174 return -ENODEV; 1175 1176 /* Sum all resources and setup resource maps */ 1177 unused_IRQ = readl(rom_resource_table + UNUSED_IRQ); 1178 dbg("unused_IRQ = %x\n", unused_IRQ); 1179 1180 temp = 0; 1181 while (unused_IRQ) { 1182 if (unused_IRQ & 1) { 1183 cpqhp_disk_irq = temp; 1184 break; 1185 } 1186 unused_IRQ = unused_IRQ >> 1; 1187 temp++; 1188 } 1189 1190 dbg("cpqhp_disk_irq= %d\n", cpqhp_disk_irq); 1191 unused_IRQ = unused_IRQ >> 1; 1192 temp++; 1193 1194 while (unused_IRQ) { 1195 if (unused_IRQ & 1) { 1196 cpqhp_nic_irq = temp; 1197 break; 1198 } 1199 unused_IRQ = unused_IRQ >> 1; 1200 temp++; 1201 } 1202 1203 dbg("cpqhp_nic_irq= %d\n", cpqhp_nic_irq); 1204 unused_IRQ = readl(rom_resource_table + PCIIRQ); 1205 1206 temp = 0; 1207 1208 if (!cpqhp_nic_irq) 1209 cpqhp_nic_irq = ctrl->cfgspc_irq; 1210 1211 if (!cpqhp_disk_irq) 1212 cpqhp_disk_irq = ctrl->cfgspc_irq; 1213 1214 dbg("cpqhp_disk_irq, cpqhp_nic_irq= %d, %d\n", cpqhp_disk_irq, cpqhp_nic_irq); 1215 1216 rc = compaq_nvram_load(rom_start, ctrl); 1217 if (rc) 1218 return rc; 1219 1220 one_slot = rom_resource_table + sizeof(struct hrt); 1221 1222 i = readb(rom_resource_table + NUMBER_OF_ENTRIES); 1223 dbg("number_of_entries = %d\n", i); 1224 1225 if (!readb(one_slot + SECONDARY_BUS)) 1226 return 1; 1227 1228 dbg("dev|IO base|length|Mem base|length|Pre base|length|PB SB MB\n"); 1229 1230 while (i && readb(one_slot + SECONDARY_BUS)) { 1231 u8 dev_func = readb(one_slot + DEV_FUNC); 1232 u8 primary_bus = readb(one_slot + PRIMARY_BUS); 1233 u8 secondary_bus = readb(one_slot + SECONDARY_BUS); 1234 u8 max_bus = readb(one_slot + MAX_BUS); 1235 u16 io_base = readw(one_slot + IO_BASE); 1236 u16 io_length = readw(one_slot + IO_LENGTH); 1237 u16 mem_base = readw(one_slot + MEM_BASE); 1238 u16 mem_length = readw(one_slot + MEM_LENGTH); 1239 u16 pre_mem_base = readw(one_slot + PRE_MEM_BASE); 1240 u16 pre_mem_length = readw(one_slot + PRE_MEM_LENGTH); 1241 1242 dbg("%2.2x | %4.4x | %4.4x | %4.4x | %4.4x | %4.4x | %4.4x |%2.2x %2.2x %2.2x\n", 1243 dev_func, io_base, io_length, mem_base, mem_length, pre_mem_base, pre_mem_length, 1244 primary_bus, secondary_bus, max_bus); 1245 1246 /* If this entry isn't for our controller's bus, ignore it */ 1247 if (primary_bus != ctrl->bus) { 1248 i--; 1249 one_slot += sizeof(struct slot_rt); 1250 continue; 1251 } 1252 /* find out if this entry is for an occupied slot */ 1253 ctrl->pci_bus->number = primary_bus; 1254 pci_bus_read_config_dword(ctrl->pci_bus, dev_func, PCI_VENDOR_ID, &temp_dword); 1255 dbg("temp_D_word = %x\n", temp_dword); 1256 1257 if (temp_dword != 0xFFFFFFFF) { 1258 index = 0; 1259 func = cpqhp_slot_find(primary_bus, dev_func >> 3, 0); 1260 1261 while (func && (func->function != (dev_func & 0x07))) { 1262 dbg("func = %p (bus, dev, fun) = (%d, %d, %d)\n", func, primary_bus, dev_func >> 3, index); 1263 func = cpqhp_slot_find(primary_bus, dev_func >> 3, index++); 1264 } 1265 1266 /* If we can't find a match, skip this table entry */ 1267 if (!func) { 1268 i--; 1269 one_slot += sizeof(struct slot_rt); 1270 continue; 1271 } 1272 /* this may not work and shouldn't be used */ 1273 if (secondary_bus != primary_bus) 1274 bridged_slot = 1; 1275 else 1276 bridged_slot = 0; 1277 1278 populated_slot = 1; 1279 } else { 1280 populated_slot = 0; 1281 bridged_slot = 0; 1282 } 1283 1284 1285 /* If we've got a valid IO base, use it */ 1286 1287 temp_dword = io_base + io_length; 1288 1289 if ((io_base) && (temp_dword < 0x10000)) { 1290 io_node = kmalloc_obj(*io_node); 1291 if (!io_node) 1292 return -ENOMEM; 1293 1294 io_node->base = io_base; 1295 io_node->length = io_length; 1296 1297 dbg("found io_node(base, length) = %x, %x\n", 1298 io_node->base, io_node->length); 1299 dbg("populated slot = %d\n", populated_slot); 1300 if (!populated_slot) { 1301 io_node->next = ctrl->io_head; 1302 ctrl->io_head = io_node; 1303 } else { 1304 io_node->next = func->io_head; 1305 func->io_head = io_node; 1306 } 1307 } 1308 1309 /* If we've got a valid memory base, use it */ 1310 temp_dword = mem_base + mem_length; 1311 if ((mem_base) && (temp_dword < 0x10000)) { 1312 mem_node = kmalloc_obj(*mem_node); 1313 if (!mem_node) 1314 return -ENOMEM; 1315 1316 mem_node->base = mem_base << 16; 1317 1318 mem_node->length = mem_length << 16; 1319 1320 dbg("found mem_node(base, length) = %x, %x\n", 1321 mem_node->base, mem_node->length); 1322 dbg("populated slot = %d\n", populated_slot); 1323 if (!populated_slot) { 1324 mem_node->next = ctrl->mem_head; 1325 ctrl->mem_head = mem_node; 1326 } else { 1327 mem_node->next = func->mem_head; 1328 func->mem_head = mem_node; 1329 } 1330 } 1331 1332 /* If we've got a valid prefetchable memory base, and 1333 * the base + length isn't greater than 0xFFFF 1334 */ 1335 temp_dword = pre_mem_base + pre_mem_length; 1336 if ((pre_mem_base) && (temp_dword < 0x10000)) { 1337 p_mem_node = kmalloc_obj(*p_mem_node); 1338 if (!p_mem_node) 1339 return -ENOMEM; 1340 1341 p_mem_node->base = pre_mem_base << 16; 1342 1343 p_mem_node->length = pre_mem_length << 16; 1344 dbg("found p_mem_node(base, length) = %x, %x\n", 1345 p_mem_node->base, p_mem_node->length); 1346 dbg("populated slot = %d\n", populated_slot); 1347 1348 if (!populated_slot) { 1349 p_mem_node->next = ctrl->p_mem_head; 1350 ctrl->p_mem_head = p_mem_node; 1351 } else { 1352 p_mem_node->next = func->p_mem_head; 1353 func->p_mem_head = p_mem_node; 1354 } 1355 } 1356 1357 /* If we've got a valid bus number, use it 1358 * The second condition is to ignore bus numbers on 1359 * populated slots that don't have PCI-PCI bridges 1360 */ 1361 if (secondary_bus && (secondary_bus != primary_bus)) { 1362 bus_node = kmalloc_obj(*bus_node); 1363 if (!bus_node) 1364 return -ENOMEM; 1365 1366 bus_node->base = secondary_bus; 1367 bus_node->length = max_bus - secondary_bus + 1; 1368 dbg("found bus_node(base, length) = %x, %x\n", 1369 bus_node->base, bus_node->length); 1370 dbg("populated slot = %d\n", populated_slot); 1371 if (!populated_slot) { 1372 bus_node->next = ctrl->bus_head; 1373 ctrl->bus_head = bus_node; 1374 } else { 1375 bus_node->next = func->bus_head; 1376 func->bus_head = bus_node; 1377 } 1378 } 1379 1380 i--; 1381 one_slot += sizeof(struct slot_rt); 1382 } 1383 1384 /* If all of the following fail, we don't have any resources for 1385 * hot plug add 1386 */ 1387 rc = 1; 1388 rc &= cpqhp_resource_sort_and_combine(&(ctrl->mem_head)); 1389 rc &= cpqhp_resource_sort_and_combine(&(ctrl->p_mem_head)); 1390 rc &= cpqhp_resource_sort_and_combine(&(ctrl->io_head)); 1391 rc &= cpqhp_resource_sort_and_combine(&(ctrl->bus_head)); 1392 1393 return rc; 1394 } 1395 1396 1397 /* 1398 * cpqhp_return_board_resources 1399 * 1400 * this routine returns all resources allocated to a board to 1401 * the available pool. 1402 * 1403 * returns 0 if success 1404 */ 1405 int cpqhp_return_board_resources(struct pci_func *func, struct resource_lists *resources) 1406 { 1407 int rc = 0; 1408 struct pci_resource *node; 1409 struct pci_resource *t_node; 1410 dbg("%s\n", __func__); 1411 1412 if (!func) 1413 return 1; 1414 1415 node = func->io_head; 1416 func->io_head = NULL; 1417 while (node) { 1418 t_node = node->next; 1419 return_resource(&(resources->io_head), node); 1420 node = t_node; 1421 } 1422 1423 node = func->mem_head; 1424 func->mem_head = NULL; 1425 while (node) { 1426 t_node = node->next; 1427 return_resource(&(resources->mem_head), node); 1428 node = t_node; 1429 } 1430 1431 node = func->p_mem_head; 1432 func->p_mem_head = NULL; 1433 while (node) { 1434 t_node = node->next; 1435 return_resource(&(resources->p_mem_head), node); 1436 node = t_node; 1437 } 1438 1439 node = func->bus_head; 1440 func->bus_head = NULL; 1441 while (node) { 1442 t_node = node->next; 1443 return_resource(&(resources->bus_head), node); 1444 node = t_node; 1445 } 1446 1447 rc |= cpqhp_resource_sort_and_combine(&(resources->mem_head)); 1448 rc |= cpqhp_resource_sort_and_combine(&(resources->p_mem_head)); 1449 rc |= cpqhp_resource_sort_and_combine(&(resources->io_head)); 1450 rc |= cpqhp_resource_sort_and_combine(&(resources->bus_head)); 1451 1452 return rc; 1453 } 1454 1455 1456 /* 1457 * cpqhp_destroy_resource_list 1458 * 1459 * Puts node back in the resource list pointed to by head 1460 */ 1461 void cpqhp_destroy_resource_list(struct resource_lists *resources) 1462 { 1463 struct pci_resource *res, *tres; 1464 1465 res = resources->io_head; 1466 resources->io_head = NULL; 1467 1468 while (res) { 1469 tres = res; 1470 res = res->next; 1471 kfree(tres); 1472 } 1473 1474 res = resources->mem_head; 1475 resources->mem_head = NULL; 1476 1477 while (res) { 1478 tres = res; 1479 res = res->next; 1480 kfree(tres); 1481 } 1482 1483 res = resources->p_mem_head; 1484 resources->p_mem_head = NULL; 1485 1486 while (res) { 1487 tres = res; 1488 res = res->next; 1489 kfree(tres); 1490 } 1491 1492 res = resources->bus_head; 1493 resources->bus_head = NULL; 1494 1495 while (res) { 1496 tres = res; 1497 res = res->next; 1498 kfree(tres); 1499 } 1500 } 1501 1502 1503 /* 1504 * cpqhp_destroy_board_resources 1505 * 1506 * Puts node back in the resource list pointed to by head 1507 */ 1508 void cpqhp_destroy_board_resources(struct pci_func *func) 1509 { 1510 struct pci_resource *res, *tres; 1511 1512 res = func->io_head; 1513 func->io_head = NULL; 1514 1515 while (res) { 1516 tres = res; 1517 res = res->next; 1518 kfree(tres); 1519 } 1520 1521 res = func->mem_head; 1522 func->mem_head = NULL; 1523 1524 while (res) { 1525 tres = res; 1526 res = res->next; 1527 kfree(tres); 1528 } 1529 1530 res = func->p_mem_head; 1531 func->p_mem_head = NULL; 1532 1533 while (res) { 1534 tres = res; 1535 res = res->next; 1536 kfree(tres); 1537 } 1538 1539 res = func->bus_head; 1540 func->bus_head = NULL; 1541 1542 while (res) { 1543 tres = res; 1544 res = res->next; 1545 kfree(tres); 1546 } 1547 } 1548