1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * STM32 ALSA SoC Digital Audio Interface (SAI) driver. 4 * 5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved 6 * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/clk-provider.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/of_irq.h> 14 #include <linux/of_platform.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/regmap.h> 17 18 #include <sound/asoundef.h> 19 #include <sound/core.h> 20 #include <sound/dmaengine_pcm.h> 21 #include <sound/pcm_params.h> 22 23 #include "stm32_sai.h" 24 25 #define SAI_FREE_PROTOCOL 0x0 26 #define SAI_SPDIF_PROTOCOL 0x1 27 28 #define SAI_SLOT_SIZE_AUTO 0x0 29 #define SAI_SLOT_SIZE_16 0x1 30 #define SAI_SLOT_SIZE_32 0x2 31 32 #define SAI_DATASIZE_8 0x2 33 #define SAI_DATASIZE_10 0x3 34 #define SAI_DATASIZE_16 0x4 35 #define SAI_DATASIZE_20 0x5 36 #define SAI_DATASIZE_24 0x6 37 #define SAI_DATASIZE_32 0x7 38 39 #define STM_SAI_DAI_NAME_SIZE 15 40 41 #define STM_SAI_IS_PLAYBACK(ip) ((ip)->dir == SNDRV_PCM_STREAM_PLAYBACK) 42 #define STM_SAI_IS_CAPTURE(ip) ((ip)->dir == SNDRV_PCM_STREAM_CAPTURE) 43 44 #define STM_SAI_A_ID 0x0 45 #define STM_SAI_B_ID 0x1 46 47 #define STM_SAI_IS_SUB_A(x) ((x)->id == STM_SAI_A_ID) 48 49 #define SAI_SYNC_NONE 0x0 50 #define SAI_SYNC_INTERNAL 0x1 51 #define SAI_SYNC_EXTERNAL 0x2 52 53 #define STM_SAI_PROTOCOL_IS_SPDIF(ip) ((ip)->spdif) 54 #define STM_SAI_HAS_SPDIF(x) ((x)->pdata->conf.has_spdif_pdm) 55 #define STM_SAI_HAS_PDM(x) ((x)->pdata->conf.has_spdif_pdm) 56 #define STM_SAI_HAS_EXT_SYNC(x) (!STM_SAI_IS_F4((x)->pdata)) 57 58 #define SAI_IEC60958_BLOCK_FRAMES 192 59 #define SAI_IEC60958_STATUS_BYTES 24 60 61 #define SAI_MCLK_NAME_LEN 32 62 #define SAI_RATE_11K 11025 63 #define SAI_MAX_SAMPLE_RATE_8K 192000 64 #define SAI_MAX_SAMPLE_RATE_11K 176400 65 #define SAI_CK_RATE_TOLERANCE 1000 /* ppm */ 66 67 /** 68 * struct stm32_sai_sub_data - private data of SAI sub block (block A or B) 69 * @pdev: device data pointer 70 * @regmap: SAI register map pointer 71 * @regmap_config: SAI sub block register map configuration pointer 72 * @dma_params: dma configuration data for rx or tx channel 73 * @cpu_dai_drv: DAI driver data pointer 74 * @cpu_dai: DAI runtime data pointer 75 * @substream: PCM substream data pointer 76 * @pdata: SAI block parent data pointer 77 * @np_sync_provider: synchronization provider node 78 * @sai_ck: kernel clock feeding the SAI clock generator 79 * @sai_mclk: master clock from SAI mclk provider 80 * @phys_addr: SAI registers physical base address 81 * @mclk_rate: SAI block master clock frequency (Hz). set at init 82 * @id: SAI sub block id corresponding to sub-block A or B 83 * @dir: SAI block direction (playback or capture). set at init 84 * @master: SAI block mode flag. (true=master, false=slave) set at init 85 * @spdif: SAI S/PDIF iec60958 mode flag. set at init 86 * @sai_ck_used: flag set while exclusivity on SAI kernel clock is active 87 * @fmt: SAI block format. relevant only for custom protocols. set at init 88 * @sync: SAI block synchronization mode. (none, internal or external) 89 * @synco: SAI block ext sync source (provider setting). (none, sub-block A/B) 90 * @synci: SAI block ext sync source (client setting). (SAI sync provider index) 91 * @fs_length: frame synchronization length. depends on protocol settings 92 * @slots: rx or tx slot number 93 * @slot_width: rx or tx slot width in bits 94 * @slot_mask: rx or tx active slots mask. set at init or at runtime 95 * @data_size: PCM data width. corresponds to PCM substream width. 96 * @spdif_frm_cnt: S/PDIF playback frame counter 97 * @iec958: iec958 data 98 * @ctrl_lock: control lock 99 * @irq_lock: prevent race condition with IRQ 100 * @set_sai_ck_rate: set SAI kernel clock rate 101 * @put_sai_ck_rate: put SAI kernel clock rate 102 */ 103 struct stm32_sai_sub_data { 104 struct platform_device *pdev; 105 struct regmap *regmap; 106 const struct regmap_config *regmap_config; 107 struct snd_dmaengine_dai_dma_data dma_params; 108 struct snd_soc_dai_driver cpu_dai_drv; 109 struct snd_soc_dai *cpu_dai; 110 struct snd_pcm_substream *substream; 111 struct stm32_sai_data *pdata; 112 struct device_node *np_sync_provider; 113 struct clk *sai_ck; 114 struct clk *sai_mclk; 115 dma_addr_t phys_addr; 116 unsigned int mclk_rate; 117 unsigned int id; 118 int dir; 119 bool master; 120 bool spdif; 121 bool sai_ck_used; 122 int fmt; 123 int sync; 124 int synco; 125 int synci; 126 int fs_length; 127 int slots; 128 int slot_width; 129 int slot_mask; 130 int data_size; 131 unsigned int spdif_frm_cnt; 132 struct snd_aes_iec958 iec958; 133 struct mutex ctrl_lock; /* protect resources accessed by controls */ 134 spinlock_t irq_lock; /* used to prevent race condition with IRQ */ 135 int (*set_sai_ck_rate)(struct stm32_sai_sub_data *sai, unsigned int rate); 136 void (*put_sai_ck_rate)(struct stm32_sai_sub_data *sai); 137 }; 138 139 enum stm32_sai_fifo_th { 140 STM_SAI_FIFO_TH_EMPTY, 141 STM_SAI_FIFO_TH_QUARTER, 142 STM_SAI_FIFO_TH_HALF, 143 STM_SAI_FIFO_TH_3_QUARTER, 144 STM_SAI_FIFO_TH_FULL, 145 }; 146 147 static bool stm32_sai_sub_readable_reg(struct device *dev, unsigned int reg) 148 { 149 switch (reg) { 150 case STM_SAI_CR1_REGX: 151 case STM_SAI_CR2_REGX: 152 case STM_SAI_FRCR_REGX: 153 case STM_SAI_SLOTR_REGX: 154 case STM_SAI_IMR_REGX: 155 case STM_SAI_SR_REGX: 156 case STM_SAI_CLRFR_REGX: 157 case STM_SAI_DR_REGX: 158 case STM_SAI_PDMCR_REGX: 159 case STM_SAI_PDMLY_REGX: 160 return true; 161 default: 162 return false; 163 } 164 } 165 166 static bool stm32_sai_sub_volatile_reg(struct device *dev, unsigned int reg) 167 { 168 switch (reg) { 169 case STM_SAI_DR_REGX: 170 case STM_SAI_SR_REGX: 171 return true; 172 default: 173 return false; 174 } 175 } 176 177 static bool stm32_sai_sub_writeable_reg(struct device *dev, unsigned int reg) 178 { 179 switch (reg) { 180 case STM_SAI_CR1_REGX: 181 case STM_SAI_CR2_REGX: 182 case STM_SAI_FRCR_REGX: 183 case STM_SAI_SLOTR_REGX: 184 case STM_SAI_IMR_REGX: 185 case STM_SAI_CLRFR_REGX: 186 case STM_SAI_DR_REGX: 187 case STM_SAI_PDMCR_REGX: 188 case STM_SAI_PDMLY_REGX: 189 return true; 190 default: 191 return false; 192 } 193 } 194 195 static int stm32_sai_sub_reg_up(struct stm32_sai_sub_data *sai, 196 unsigned int reg, unsigned int mask, 197 unsigned int val) 198 { 199 int ret; 200 201 ret = clk_enable(sai->pdata->pclk); 202 if (ret < 0) 203 return ret; 204 205 ret = regmap_update_bits(sai->regmap, reg, mask, val); 206 207 clk_disable(sai->pdata->pclk); 208 209 return ret; 210 } 211 212 static int stm32_sai_sub_reg_wr(struct stm32_sai_sub_data *sai, 213 unsigned int reg, unsigned int mask, 214 unsigned int val) 215 { 216 int ret; 217 218 ret = clk_enable(sai->pdata->pclk); 219 if (ret < 0) 220 return ret; 221 222 ret = regmap_write_bits(sai->regmap, reg, mask, val); 223 224 clk_disable(sai->pdata->pclk); 225 226 return ret; 227 } 228 229 static int stm32_sai_sub_reg_rd(struct stm32_sai_sub_data *sai, 230 unsigned int reg, unsigned int *val) 231 { 232 int ret; 233 234 ret = clk_enable(sai->pdata->pclk); 235 if (ret < 0) 236 return ret; 237 238 ret = regmap_read(sai->regmap, reg, val); 239 240 clk_disable(sai->pdata->pclk); 241 242 return ret; 243 } 244 245 static const struct regmap_config stm32_sai_sub_regmap_config_f4 = { 246 .reg_bits = 32, 247 .reg_stride = 4, 248 .val_bits = 32, 249 .max_register = STM_SAI_DR_REGX, 250 .readable_reg = stm32_sai_sub_readable_reg, 251 .volatile_reg = stm32_sai_sub_volatile_reg, 252 .writeable_reg = stm32_sai_sub_writeable_reg, 253 .fast_io = true, 254 .cache_type = REGCACHE_FLAT, 255 }; 256 257 static const struct regmap_config stm32_sai_sub_regmap_config_h7 = { 258 .reg_bits = 32, 259 .reg_stride = 4, 260 .val_bits = 32, 261 .max_register = STM_SAI_PDMLY_REGX, 262 .readable_reg = stm32_sai_sub_readable_reg, 263 .volatile_reg = stm32_sai_sub_volatile_reg, 264 .writeable_reg = stm32_sai_sub_writeable_reg, 265 .fast_io = true, 266 .cache_type = REGCACHE_FLAT, 267 }; 268 269 static int snd_pcm_iec958_info(struct snd_kcontrol *kcontrol, 270 struct snd_ctl_elem_info *uinfo) 271 { 272 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 273 uinfo->count = 1; 274 275 return 0; 276 } 277 278 static int snd_pcm_iec958_get(struct snd_kcontrol *kcontrol, 279 struct snd_ctl_elem_value *uctl) 280 { 281 struct stm32_sai_sub_data *sai = snd_kcontrol_chip(kcontrol); 282 283 guard(mutex)(&sai->ctrl_lock); 284 memcpy(uctl->value.iec958.status, sai->iec958.status, 4); 285 286 return 0; 287 } 288 289 static int snd_pcm_iec958_put(struct snd_kcontrol *kcontrol, 290 struct snd_ctl_elem_value *uctl) 291 { 292 struct stm32_sai_sub_data *sai = snd_kcontrol_chip(kcontrol); 293 294 guard(mutex)(&sai->ctrl_lock); 295 memcpy(sai->iec958.status, uctl->value.iec958.status, 4); 296 297 return 0; 298 } 299 300 static const struct snd_kcontrol_new iec958_ctls = { 301 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE | 302 SNDRV_CTL_ELEM_ACCESS_VOLATILE), 303 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 304 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), 305 .info = snd_pcm_iec958_info, 306 .get = snd_pcm_iec958_get, 307 .put = snd_pcm_iec958_put, 308 }; 309 310 struct stm32_sai_mclk_data { 311 struct clk_hw hw; 312 unsigned long freq; 313 struct stm32_sai_sub_data *sai_data; 314 }; 315 316 #define to_mclk_data(_hw) container_of(_hw, struct stm32_sai_mclk_data, hw) 317 #define STM32_SAI_MAX_CLKS 1 318 319 static int stm32_sai_get_clk_div(struct stm32_sai_sub_data *sai, 320 unsigned long input_rate, 321 unsigned long output_rate) 322 { 323 int version = sai->pdata->conf.version; 324 int div; 325 326 div = DIV_ROUND_CLOSEST(input_rate, output_rate); 327 if (div > SAI_XCR1_MCKDIV_MAX(version) || div <= 0) { 328 dev_err(&sai->pdev->dev, "Divider %d out of range\n", div); 329 return -EINVAL; 330 } 331 dev_dbg(&sai->pdev->dev, "SAI divider %d\n", div); 332 333 if (input_rate % div) 334 dev_dbg(&sai->pdev->dev, 335 "Rate not accurate. requested (%ld), actual (%ld)\n", 336 output_rate, input_rate / div); 337 338 return div; 339 } 340 341 static int stm32_sai_set_clk_div(struct stm32_sai_sub_data *sai, 342 unsigned int div) 343 { 344 int version = sai->pdata->conf.version; 345 int ret, cr1, mask; 346 347 if (div > SAI_XCR1_MCKDIV_MAX(version)) { 348 dev_err(&sai->pdev->dev, "Divider %d out of range\n", div); 349 return -EINVAL; 350 } 351 352 mask = SAI_XCR1_MCKDIV_MASK(SAI_XCR1_MCKDIV_WIDTH(version)); 353 cr1 = SAI_XCR1_MCKDIV_SET(div); 354 ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, mask, cr1); 355 if (ret < 0) 356 dev_err(&sai->pdev->dev, "Failed to update CR1 register\n"); 357 358 return ret; 359 } 360 361 static bool stm32_sai_rate_accurate(unsigned int max_rate, unsigned int rate) 362 { 363 u64 delta, dividend; 364 int ratio; 365 366 ratio = DIV_ROUND_CLOSEST(max_rate, rate); 367 if (!ratio) 368 return false; 369 370 dividend = mul_u32_u32(1000000, abs(max_rate - (ratio * rate))); 371 delta = div_u64(dividend, max_rate); 372 373 if (delta <= SAI_CK_RATE_TOLERANCE) 374 return true; 375 376 return false; 377 } 378 379 static int stm32_sai_set_parent_clk(struct stm32_sai_sub_data *sai, 380 unsigned int rate) 381 { 382 struct platform_device *pdev = sai->pdev; 383 struct clk *parent_clk = sai->pdata->clk_x8k; 384 int ret; 385 386 if (!(rate % SAI_RATE_11K)) 387 parent_clk = sai->pdata->clk_x11k; 388 389 ret = clk_set_parent(sai->sai_ck, parent_clk); 390 if (ret) 391 dev_err(&pdev->dev, " Error %d setting sai_ck parent clock. %s", 392 ret, ret == -EBUSY ? 393 "Active stream rates conflict\n" : "\n"); 394 395 return ret; 396 } 397 398 static void stm32_sai_put_parent_rate(struct stm32_sai_sub_data *sai) 399 { 400 if (sai->sai_ck_used) { 401 sai->sai_ck_used = false; 402 clk_rate_exclusive_put(sai->sai_ck); 403 } 404 } 405 406 static int stm32_sai_set_parent_rate(struct stm32_sai_sub_data *sai, 407 unsigned int rate) 408 { 409 struct platform_device *pdev = sai->pdev; 410 unsigned int sai_ck_rate, sai_ck_max_rate, sai_ck_min_rate, sai_curr_rate, sai_new_rate; 411 int div, ret; 412 413 /* 414 * Set minimum and maximum expected kernel clock frequency 415 * - mclk on or spdif: 416 * f_sai_ck = MCKDIV * mclk-fs * fs 417 * Here typical 256 ratio is assumed for mclk-fs 418 * - mclk off: 419 * f_sai_ck = MCKDIV * FRL * fs 420 * Where FRL=[8..256], MCKDIV=[1..n] (n depends on SAI version) 421 * Set constraint MCKDIV * FRL <= 256, to ensure MCKDIV is in available range 422 * f_sai_ck = sai_ck_max_rate * pow_of_two(FRL) / 256 423 */ 424 sai_ck_min_rate = rate * 256; 425 if (!(rate % SAI_RATE_11K)) 426 sai_ck_max_rate = SAI_MAX_SAMPLE_RATE_11K * 256; 427 else 428 sai_ck_max_rate = SAI_MAX_SAMPLE_RATE_8K * 256; 429 430 if (!sai->sai_mclk && !STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 431 sai_ck_min_rate = rate * sai->fs_length; 432 sai_ck_max_rate /= DIV_ROUND_CLOSEST(256, roundup_pow_of_two(sai->fs_length)); 433 } 434 435 /* 436 * Request exclusivity, as the clock is shared by SAI sub-blocks and by 437 * some SAI instances. This allows to ensure that the rate cannot be 438 * changed while one or more SAIs are using the clock. 439 */ 440 clk_rate_exclusive_get(sai->sai_ck); 441 sai->sai_ck_used = true; 442 443 /* 444 * Check current kernel clock rate. If it gives the expected accuracy 445 * return immediately. 446 */ 447 sai_curr_rate = clk_get_rate(sai->sai_ck); 448 dev_dbg(&pdev->dev, "kernel clock rate: min [%u], max [%u], current [%u]", 449 sai_ck_min_rate, sai_ck_max_rate, sai_curr_rate); 450 if (stm32_sai_rate_accurate(sai_ck_max_rate, sai_curr_rate) && 451 sai_curr_rate >= sai_ck_min_rate) 452 return 0; 453 454 /* 455 * Otherwise try to set the maximum rate and check the new actual rate. 456 * If the new rate does not give the expected accuracy, try to set 457 * lower rates for the kernel clock. 458 */ 459 sai_ck_rate = sai_ck_max_rate; 460 div = 1; 461 do { 462 /* Check new rate accuracy. Return if ok */ 463 sai_new_rate = clk_round_rate(sai->sai_ck, sai_ck_rate); 464 if (stm32_sai_rate_accurate(sai_ck_rate, sai_new_rate)) { 465 ret = clk_set_rate(sai->sai_ck, sai_ck_rate); 466 if (ret) { 467 dev_err(&pdev->dev, "Error %d setting sai_ck rate. %s", 468 ret, ret == -EBUSY ? 469 "Active stream rates may be in conflict\n" : "\n"); 470 goto err; 471 } 472 473 return 0; 474 } 475 476 /* Try a lower frequency */ 477 div++; 478 sai_ck_rate = sai_ck_max_rate / div; 479 } while (sai_ck_rate >= sai_ck_min_rate); 480 481 /* No accurate rate found */ 482 dev_err(&pdev->dev, "Failed to find an accurate rate"); 483 484 err: 485 stm32_sai_put_parent_rate(sai); 486 487 return -EINVAL; 488 } 489 490 static int stm32_sai_mclk_determine_rate(struct clk_hw *hw, 491 struct clk_rate_request *req) 492 { 493 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 494 struct stm32_sai_sub_data *sai = mclk->sai_data; 495 int div; 496 497 div = stm32_sai_get_clk_div(sai, req->best_parent_rate, req->rate); 498 if (div <= 0) 499 return -EINVAL; 500 501 mclk->freq = req->best_parent_rate / div; 502 503 req->rate = mclk->freq; 504 505 return 0; 506 } 507 508 static unsigned long stm32_sai_mclk_recalc_rate(struct clk_hw *hw, 509 unsigned long parent_rate) 510 { 511 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 512 513 return mclk->freq; 514 } 515 516 static int stm32_sai_mclk_set_rate(struct clk_hw *hw, unsigned long rate, 517 unsigned long parent_rate) 518 { 519 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 520 struct stm32_sai_sub_data *sai = mclk->sai_data; 521 int div, ret; 522 523 div = stm32_sai_get_clk_div(sai, parent_rate, rate); 524 if (div < 0) 525 return div; 526 527 ret = stm32_sai_set_clk_div(sai, div); 528 if (ret) 529 return ret; 530 531 mclk->freq = rate; 532 533 return 0; 534 } 535 536 static int stm32_sai_mclk_enable(struct clk_hw *hw) 537 { 538 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 539 struct stm32_sai_sub_data *sai = mclk->sai_data; 540 541 dev_dbg(&sai->pdev->dev, "Enable master clock\n"); 542 543 return stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, 544 SAI_XCR1_MCKEN, SAI_XCR1_MCKEN); 545 } 546 547 static void stm32_sai_mclk_disable(struct clk_hw *hw) 548 { 549 struct stm32_sai_mclk_data *mclk = to_mclk_data(hw); 550 struct stm32_sai_sub_data *sai = mclk->sai_data; 551 552 dev_dbg(&sai->pdev->dev, "Disable master clock\n"); 553 554 stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, SAI_XCR1_MCKEN, 0); 555 } 556 557 static const struct clk_ops mclk_ops = { 558 .enable = stm32_sai_mclk_enable, 559 .disable = stm32_sai_mclk_disable, 560 .recalc_rate = stm32_sai_mclk_recalc_rate, 561 .determine_rate = stm32_sai_mclk_determine_rate, 562 .set_rate = stm32_sai_mclk_set_rate, 563 }; 564 565 static int stm32_sai_add_mclk_provider(struct stm32_sai_sub_data *sai) 566 { 567 struct clk_hw *hw; 568 struct stm32_sai_mclk_data *mclk; 569 struct device *dev = &sai->pdev->dev; 570 const char *pname = __clk_get_name(sai->sai_ck); 571 char *mclk_name, *p, *s = (char *)pname; 572 int ret, i = 0; 573 574 mclk = devm_kzalloc(dev, sizeof(*mclk), GFP_KERNEL); 575 if (!mclk) 576 return -ENOMEM; 577 578 mclk_name = devm_kcalloc(dev, sizeof(char), 579 SAI_MCLK_NAME_LEN, GFP_KERNEL); 580 if (!mclk_name) 581 return -ENOMEM; 582 583 /* 584 * Forge mclk clock name from parent clock name and suffix. 585 * String after "_" char is stripped in parent name. 586 */ 587 p = mclk_name; 588 while (*s && *s != '_' && (i < (SAI_MCLK_NAME_LEN - 7))) { 589 *p++ = *s++; 590 i++; 591 } 592 STM_SAI_IS_SUB_A(sai) ? strcat(p, "a_mclk") : strcat(p, "b_mclk"); 593 594 mclk->hw.init = CLK_HW_INIT(mclk_name, pname, &mclk_ops, 0); 595 mclk->sai_data = sai; 596 hw = &mclk->hw; 597 598 dev_dbg(dev, "Register master clock %s\n", mclk_name); 599 ret = devm_clk_hw_register(&sai->pdev->dev, hw); 600 if (ret) { 601 dev_err(dev, "mclk register returned %d\n", ret); 602 return ret; 603 } 604 sai->sai_mclk = hw->clk; 605 606 /* register mclk provider */ 607 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw); 608 } 609 610 static irqreturn_t stm32_sai_isr(int irq, void *devid) 611 { 612 struct stm32_sai_sub_data *sai = (struct stm32_sai_sub_data *)devid; 613 struct platform_device *pdev = sai->pdev; 614 unsigned int sr, imr, flags; 615 snd_pcm_state_t status = SNDRV_PCM_STATE_RUNNING; 616 617 stm32_sai_sub_reg_rd(sai, STM_SAI_IMR_REGX, &imr); 618 stm32_sai_sub_reg_rd(sai, STM_SAI_SR_REGX, &sr); 619 620 flags = sr & imr; 621 if (!flags) 622 return IRQ_NONE; 623 624 stm32_sai_sub_reg_wr(sai, STM_SAI_CLRFR_REGX, SAI_XCLRFR_MASK, 625 SAI_XCLRFR_MASK); 626 627 if (!sai->substream) { 628 dev_err(&pdev->dev, "Device stopped. Spurious IRQ 0x%x\n", sr); 629 return IRQ_NONE; 630 } 631 632 if (flags & SAI_XIMR_OVRUDRIE) { 633 dev_err(&pdev->dev, "IRQ %s\n", 634 STM_SAI_IS_PLAYBACK(sai) ? "underrun" : "overrun"); 635 status = SNDRV_PCM_STATE_XRUN; 636 } 637 638 if (flags & SAI_XIMR_MUTEDETIE) 639 dev_dbg(&pdev->dev, "IRQ mute detected\n"); 640 641 if (flags & SAI_XIMR_WCKCFGIE) { 642 dev_err(&pdev->dev, "IRQ wrong clock configuration\n"); 643 status = SNDRV_PCM_STATE_DISCONNECTED; 644 } 645 646 if (flags & SAI_XIMR_CNRDYIE) 647 dev_err(&pdev->dev, "IRQ Codec not ready\n"); 648 649 if (flags & SAI_XIMR_AFSDETIE) { 650 dev_err(&pdev->dev, "IRQ Anticipated frame synchro\n"); 651 status = SNDRV_PCM_STATE_XRUN; 652 } 653 654 if (flags & SAI_XIMR_LFSDETIE) { 655 dev_err(&pdev->dev, "IRQ Late frame synchro\n"); 656 status = SNDRV_PCM_STATE_XRUN; 657 } 658 659 scoped_guard(spinlock, &sai->irq_lock) { 660 if (status != SNDRV_PCM_STATE_RUNNING && sai->substream) 661 snd_pcm_stop_xrun(sai->substream); 662 } 663 664 return IRQ_HANDLED; 665 } 666 667 static int stm32_sai_set_sysclk(struct snd_soc_dai *cpu_dai, 668 int clk_id, unsigned int freq, int dir) 669 { 670 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 671 int ret; 672 673 /* 674 * The mclk rate is determined at runtime from the audio stream rate. 675 * Skip calls to the set_sysclk callback that are not relevant during the 676 * initialization phase. 677 */ 678 if (!snd_soc_card_is_instantiated(cpu_dai->component->card)) 679 return 0; 680 681 if (dir == SND_SOC_CLOCK_OUT && sai->sai_mclk) { 682 ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, 683 SAI_XCR1_NODIV, 684 freq ? 0 : SAI_XCR1_NODIV); 685 if (ret < 0) 686 return ret; 687 688 /* Assume shutdown if requested frequency is 0Hz */ 689 if (!freq) { 690 /* Release mclk rate only if rate was actually set */ 691 if (sai->mclk_rate) { 692 clk_rate_exclusive_put(sai->sai_mclk); 693 sai->mclk_rate = 0; 694 } 695 696 if (sai->put_sai_ck_rate) 697 sai->put_sai_ck_rate(sai); 698 699 return 0; 700 } 701 702 /* If master clock is used, configure SAI kernel clock now */ 703 ret = sai->set_sai_ck_rate(sai, freq); 704 if (ret) 705 return ret; 706 707 ret = clk_set_rate_exclusive(sai->sai_mclk, freq); 708 if (ret) { 709 dev_err(cpu_dai->dev, 710 ret == -EBUSY ? 711 "Active streams have incompatible rates" : 712 "Could not set mclk rate\n"); 713 return ret; 714 } 715 716 dev_dbg(cpu_dai->dev, "SAI MCLK frequency is %uHz\n", freq); 717 sai->mclk_rate = freq; 718 } 719 720 return 0; 721 } 722 723 static int stm32_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, 724 u32 rx_mask, int slots, int slot_width) 725 { 726 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 727 int slotr, slotr_mask, slot_size; 728 729 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 730 dev_warn(cpu_dai->dev, "Slot setting relevant only for TDM\n"); 731 return 0; 732 } 733 734 dev_dbg(cpu_dai->dev, "Masks tx/rx:%#x/%#x, slots:%d, width:%d\n", 735 tx_mask, rx_mask, slots, slot_width); 736 737 switch (slot_width) { 738 case 16: 739 slot_size = SAI_SLOT_SIZE_16; 740 break; 741 case 32: 742 slot_size = SAI_SLOT_SIZE_32; 743 break; 744 default: 745 slot_size = SAI_SLOT_SIZE_AUTO; 746 break; 747 } 748 749 slotr = SAI_XSLOTR_SLOTSZ_SET(slot_size) | 750 SAI_XSLOTR_NBSLOT_SET(slots - 1); 751 slotr_mask = SAI_XSLOTR_SLOTSZ_MASK | SAI_XSLOTR_NBSLOT_MASK; 752 753 /* tx/rx mask set in machine init, if slot number defined in DT */ 754 if (STM_SAI_IS_PLAYBACK(sai)) { 755 sai->slot_mask = tx_mask; 756 slotr |= SAI_XSLOTR_SLOTEN_SET(tx_mask); 757 } 758 759 if (STM_SAI_IS_CAPTURE(sai)) { 760 sai->slot_mask = rx_mask; 761 slotr |= SAI_XSLOTR_SLOTEN_SET(rx_mask); 762 } 763 764 slotr_mask |= SAI_XSLOTR_SLOTEN_MASK; 765 766 stm32_sai_sub_reg_up(sai, STM_SAI_SLOTR_REGX, slotr_mask, slotr); 767 768 sai->slot_width = slot_width; 769 sai->slots = slots; 770 771 return 0; 772 } 773 774 static int stm32_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 775 { 776 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 777 int cr1, frcr = 0; 778 int cr1_mask, frcr_mask = 0; 779 int ret; 780 781 dev_dbg(cpu_dai->dev, "fmt %x\n", fmt); 782 783 /* Do not generate master by default */ 784 cr1 = SAI_XCR1_NODIV; 785 cr1_mask = SAI_XCR1_NODIV; 786 787 cr1_mask |= SAI_XCR1_PRTCFG_MASK; 788 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 789 cr1 |= SAI_XCR1_PRTCFG_SET(SAI_SPDIF_PROTOCOL); 790 goto conf_update; 791 } 792 793 cr1 |= SAI_XCR1_PRTCFG_SET(SAI_FREE_PROTOCOL); 794 795 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 796 /* SCK active high for all protocols */ 797 case SND_SOC_DAIFMT_I2S: 798 cr1 |= SAI_XCR1_CKSTR; 799 frcr |= SAI_XFRCR_FSOFF | SAI_XFRCR_FSDEF; 800 break; 801 /* Left justified */ 802 case SND_SOC_DAIFMT_MSB: 803 cr1 |= SAI_XCR1_CKSTR; 804 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF; 805 break; 806 /* Right justified */ 807 case SND_SOC_DAIFMT_LSB: 808 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSDEF; 809 break; 810 case SND_SOC_DAIFMT_DSP_A: 811 cr1 |= SAI_XCR1_CKSTR; 812 frcr |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF; 813 break; 814 case SND_SOC_DAIFMT_DSP_B: 815 cr1 |= SAI_XCR1_CKSTR; 816 frcr |= SAI_XFRCR_FSPOL; 817 break; 818 default: 819 dev_err(cpu_dai->dev, "Unsupported protocol %#x\n", 820 fmt & SND_SOC_DAIFMT_FORMAT_MASK); 821 return -EINVAL; 822 } 823 824 cr1_mask |= SAI_XCR1_CKSTR; 825 frcr_mask |= SAI_XFRCR_FSPOL | SAI_XFRCR_FSOFF | 826 SAI_XFRCR_FSDEF; 827 828 /* DAI clock strobing. Invert setting previously set */ 829 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 830 case SND_SOC_DAIFMT_NB_NF: 831 break; 832 case SND_SOC_DAIFMT_IB_NF: 833 cr1 ^= SAI_XCR1_CKSTR; 834 break; 835 case SND_SOC_DAIFMT_NB_IF: 836 frcr ^= SAI_XFRCR_FSPOL; 837 break; 838 case SND_SOC_DAIFMT_IB_IF: 839 /* Invert fs & sck */ 840 cr1 ^= SAI_XCR1_CKSTR; 841 frcr ^= SAI_XFRCR_FSPOL; 842 break; 843 default: 844 dev_err(cpu_dai->dev, "Unsupported strobing %#x\n", 845 fmt & SND_SOC_DAIFMT_INV_MASK); 846 return -EINVAL; 847 } 848 cr1_mask |= SAI_XCR1_CKSTR; 849 frcr_mask |= SAI_XFRCR_FSPOL; 850 851 stm32_sai_sub_reg_up(sai, STM_SAI_FRCR_REGX, frcr_mask, frcr); 852 853 /* DAI clock master masks */ 854 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 855 case SND_SOC_DAIFMT_BC_FC: 856 /* codec is master */ 857 cr1 |= SAI_XCR1_SLAVE; 858 sai->master = false; 859 break; 860 case SND_SOC_DAIFMT_BP_FP: 861 sai->master = true; 862 break; 863 default: 864 dev_err(cpu_dai->dev, "Unsupported mode %#x\n", 865 fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK); 866 return -EINVAL; 867 } 868 869 /* Set slave mode if sub-block is synchronized with another SAI */ 870 if (sai->sync) { 871 dev_dbg(cpu_dai->dev, "Synchronized SAI configured as slave\n"); 872 cr1 |= SAI_XCR1_SLAVE; 873 sai->master = false; 874 } 875 876 cr1_mask |= SAI_XCR1_SLAVE; 877 878 conf_update: 879 ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, cr1_mask, cr1); 880 if (ret < 0) { 881 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 882 return ret; 883 } 884 885 sai->fmt = fmt; 886 887 return 0; 888 } 889 890 static int stm32_sai_startup(struct snd_pcm_substream *substream, 891 struct snd_soc_dai *cpu_dai) 892 { 893 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 894 int imr, cr2, ret; 895 896 scoped_guard(spinlock_irqsave, &sai->irq_lock) 897 sai->substream = substream; 898 899 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 900 snd_pcm_hw_constraint_mask64(substream->runtime, 901 SNDRV_PCM_HW_PARAM_FORMAT, 902 SNDRV_PCM_FMTBIT_S32_LE); 903 snd_pcm_hw_constraint_single(substream->runtime, 904 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 905 } 906 907 ret = clk_prepare_enable(sai->sai_ck); 908 if (ret < 0) { 909 dev_err(cpu_dai->dev, "Failed to enable clock: %d\n", ret); 910 return ret; 911 } 912 913 /* Enable ITs */ 914 stm32_sai_sub_reg_wr(sai, STM_SAI_CLRFR_REGX, 915 SAI_XCLRFR_MASK, SAI_XCLRFR_MASK); 916 917 imr = SAI_XIMR_OVRUDRIE; 918 if (STM_SAI_IS_CAPTURE(sai)) { 919 stm32_sai_sub_reg_rd(sai, STM_SAI_CR2_REGX, &cr2); 920 if (cr2 & SAI_XCR2_MUTECNT_MASK) 921 imr |= SAI_XIMR_MUTEDETIE; 922 } 923 924 if (sai->master) 925 imr |= SAI_XIMR_WCKCFGIE; 926 else 927 imr |= SAI_XIMR_AFSDETIE | SAI_XIMR_LFSDETIE; 928 929 stm32_sai_sub_reg_up(sai, STM_SAI_IMR_REGX, 930 SAI_XIMR_MASK, imr); 931 932 return 0; 933 } 934 935 static int stm32_sai_set_config(struct snd_soc_dai *cpu_dai, 936 struct snd_pcm_substream *substream, 937 struct snd_pcm_hw_params *params) 938 { 939 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 940 int cr1, cr1_mask, ret; 941 942 /* 943 * DMA bursts increment is set to 4 words. 944 * SAI fifo threshold is set to half fifo, to keep enough space 945 * for DMA incoming bursts. 946 */ 947 stm32_sai_sub_reg_wr(sai, STM_SAI_CR2_REGX, 948 SAI_XCR2_FFLUSH | SAI_XCR2_FTH_MASK, 949 SAI_XCR2_FFLUSH | 950 SAI_XCR2_FTH_SET(STM_SAI_FIFO_TH_HALF)); 951 952 /* DS bits in CR1 not set for SPDIF (size forced to 24 bits).*/ 953 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 954 sai->spdif_frm_cnt = 0; 955 return 0; 956 } 957 958 /* Mode, data format and channel config */ 959 cr1_mask = SAI_XCR1_DS_MASK; 960 switch (params_format(params)) { 961 case SNDRV_PCM_FORMAT_S8: 962 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_8); 963 break; 964 case SNDRV_PCM_FORMAT_S16_LE: 965 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_16); 966 break; 967 case SNDRV_PCM_FORMAT_S32_LE: 968 cr1 = SAI_XCR1_DS_SET(SAI_DATASIZE_32); 969 break; 970 default: 971 dev_err(cpu_dai->dev, "Data format not supported\n"); 972 return -EINVAL; 973 } 974 975 cr1_mask |= SAI_XCR1_MONO; 976 if ((sai->slots == 2) && (params_channels(params) == 1)) 977 cr1 |= SAI_XCR1_MONO; 978 979 ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, cr1_mask, cr1); 980 if (ret < 0) { 981 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 982 return ret; 983 } 984 985 return 0; 986 } 987 988 static int stm32_sai_set_slots(struct snd_soc_dai *cpu_dai) 989 { 990 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 991 int slotr, slot_sz; 992 993 stm32_sai_sub_reg_rd(sai, STM_SAI_SLOTR_REGX, &slotr); 994 995 /* 996 * If SLOTSZ is set to auto in SLOTR, align slot width on data size 997 * By default slot width = data size, if not forced from DT 998 */ 999 slot_sz = slotr & SAI_XSLOTR_SLOTSZ_MASK; 1000 if (slot_sz == SAI_XSLOTR_SLOTSZ_SET(SAI_SLOT_SIZE_AUTO)) 1001 sai->slot_width = sai->data_size; 1002 1003 if (sai->slot_width < sai->data_size) { 1004 dev_err(cpu_dai->dev, 1005 "Data size %d larger than slot width\n", 1006 sai->data_size); 1007 return -EINVAL; 1008 } 1009 1010 /* Slot number is set to 2, if not specified in DT */ 1011 if (!sai->slots) 1012 sai->slots = 2; 1013 1014 /* The number of slots in the audio frame is equal to NBSLOT[3:0] + 1*/ 1015 stm32_sai_sub_reg_up(sai, STM_SAI_SLOTR_REGX, 1016 SAI_XSLOTR_NBSLOT_MASK, 1017 SAI_XSLOTR_NBSLOT_SET((sai->slots - 1))); 1018 1019 /* Set default slots mask if not already set from DT */ 1020 if (!(slotr & SAI_XSLOTR_SLOTEN_MASK)) { 1021 sai->slot_mask = (1 << sai->slots) - 1; 1022 stm32_sai_sub_reg_up(sai, 1023 STM_SAI_SLOTR_REGX, SAI_XSLOTR_SLOTEN_MASK, 1024 SAI_XSLOTR_SLOTEN_SET(sai->slot_mask)); 1025 } 1026 1027 dev_dbg(cpu_dai->dev, "Slots %d, slot width %d\n", 1028 sai->slots, sai->slot_width); 1029 1030 return 0; 1031 } 1032 1033 static void stm32_sai_set_frame(struct snd_soc_dai *cpu_dai) 1034 { 1035 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 1036 int fs_active, offset, format; 1037 int frcr, frcr_mask; 1038 1039 format = sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK; 1040 sai->fs_length = sai->slot_width * sai->slots; 1041 1042 fs_active = sai->fs_length / 2; 1043 if ((format == SND_SOC_DAIFMT_DSP_A) || 1044 (format == SND_SOC_DAIFMT_DSP_B)) 1045 fs_active = 1; 1046 1047 frcr = SAI_XFRCR_FRL_SET((sai->fs_length - 1)); 1048 frcr |= SAI_XFRCR_FSALL_SET((fs_active - 1)); 1049 frcr_mask = SAI_XFRCR_FRL_MASK | SAI_XFRCR_FSALL_MASK; 1050 1051 dev_dbg(cpu_dai->dev, "Frame length %d, frame active %d\n", 1052 sai->fs_length, fs_active); 1053 1054 stm32_sai_sub_reg_up(sai, STM_SAI_FRCR_REGX, frcr_mask, frcr); 1055 1056 if ((sai->fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_LSB) { 1057 offset = sai->slot_width - sai->data_size; 1058 1059 stm32_sai_sub_reg_up(sai, STM_SAI_SLOTR_REGX, 1060 SAI_XSLOTR_FBOFF_MASK, 1061 SAI_XSLOTR_FBOFF_SET(offset)); 1062 } 1063 } 1064 1065 static void stm32_sai_init_iec958_status(struct stm32_sai_sub_data *sai) 1066 { 1067 unsigned char *cs = sai->iec958.status; 1068 1069 cs[0] = IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_NONE; 1070 cs[1] = IEC958_AES1_CON_GENERAL; 1071 cs[2] = IEC958_AES2_CON_SOURCE_UNSPEC | IEC958_AES2_CON_CHANNEL_UNSPEC; 1072 cs[3] = IEC958_AES3_CON_CLOCK_1000PPM | IEC958_AES3_CON_FS_NOTID; 1073 } 1074 1075 static void stm32_sai_set_iec958_status(struct stm32_sai_sub_data *sai, 1076 struct snd_pcm_runtime *runtime) 1077 { 1078 if (!runtime) 1079 return; 1080 1081 /* Force the sample rate according to runtime rate */ 1082 guard(mutex)(&sai->ctrl_lock); 1083 switch (runtime->rate) { 1084 case 22050: 1085 sai->iec958.status[3] = IEC958_AES3_CON_FS_22050; 1086 break; 1087 case 44100: 1088 sai->iec958.status[3] = IEC958_AES3_CON_FS_44100; 1089 break; 1090 case 88200: 1091 sai->iec958.status[3] = IEC958_AES3_CON_FS_88200; 1092 break; 1093 case 176400: 1094 sai->iec958.status[3] = IEC958_AES3_CON_FS_176400; 1095 break; 1096 case 24000: 1097 sai->iec958.status[3] = IEC958_AES3_CON_FS_24000; 1098 break; 1099 case 48000: 1100 sai->iec958.status[3] = IEC958_AES3_CON_FS_48000; 1101 break; 1102 case 96000: 1103 sai->iec958.status[3] = IEC958_AES3_CON_FS_96000; 1104 break; 1105 case 192000: 1106 sai->iec958.status[3] = IEC958_AES3_CON_FS_192000; 1107 break; 1108 case 32000: 1109 sai->iec958.status[3] = IEC958_AES3_CON_FS_32000; 1110 break; 1111 default: 1112 sai->iec958.status[3] = IEC958_AES3_CON_FS_NOTID; 1113 break; 1114 } 1115 } 1116 1117 static int stm32_sai_configure_clock(struct snd_soc_dai *cpu_dai, 1118 struct snd_pcm_hw_params *params) 1119 { 1120 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 1121 int div = 0, cr1 = 0; 1122 int sai_clk_rate, mclk_ratio, den; 1123 unsigned int rate = params_rate(params); 1124 int ret; 1125 1126 if (!sai->sai_mclk) { 1127 ret = sai->set_sai_ck_rate(sai, rate); 1128 if (ret) 1129 return ret; 1130 } 1131 sai_clk_rate = clk_get_rate(sai->sai_ck); 1132 1133 if (STM_SAI_IS_F4(sai->pdata)) { 1134 /* mclk on (NODIV=0) 1135 * mclk_rate = 256 * fs 1136 * MCKDIV = 0 if sai_ck < 3/2 * mclk_rate 1137 * MCKDIV = sai_ck / (2 * mclk_rate) otherwise 1138 * mclk off (NODIV=1) 1139 * MCKDIV ignored. sck = sai_ck 1140 */ 1141 if (!sai->mclk_rate) 1142 return 0; 1143 1144 if (2 * sai_clk_rate >= 3 * sai->mclk_rate) { 1145 div = stm32_sai_get_clk_div(sai, sai_clk_rate, 1146 2 * sai->mclk_rate); 1147 if (div < 0) 1148 return div; 1149 } 1150 } else { 1151 /* 1152 * TDM mode : 1153 * mclk on 1154 * MCKDIV = sai_ck / (ws x 256) (NOMCK=0. OSR=0) 1155 * MCKDIV = sai_ck / (ws x 512) (NOMCK=0. OSR=1) 1156 * mclk off 1157 * MCKDIV = sai_ck / (frl x ws) (NOMCK=1) 1158 * Note: NOMCK/NODIV correspond to same bit. 1159 */ 1160 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 1161 div = stm32_sai_get_clk_div(sai, sai_clk_rate, 1162 rate * 128); 1163 if (div < 0) 1164 return div; 1165 } else { 1166 if (sai->mclk_rate) { 1167 mclk_ratio = sai->mclk_rate / rate; 1168 if (mclk_ratio == 512) { 1169 cr1 = SAI_XCR1_OSR; 1170 } else if (mclk_ratio != 256) { 1171 dev_err(cpu_dai->dev, 1172 "Wrong mclk ratio %d\n", 1173 mclk_ratio); 1174 return -EINVAL; 1175 } 1176 1177 stm32_sai_sub_reg_up(sai, 1178 STM_SAI_CR1_REGX, 1179 SAI_XCR1_OSR, cr1); 1180 1181 div = stm32_sai_get_clk_div(sai, sai_clk_rate, 1182 sai->mclk_rate); 1183 if (div < 0) 1184 return div; 1185 } else { 1186 /* mclk-fs not set, master clock not active */ 1187 den = sai->fs_length * params_rate(params); 1188 div = stm32_sai_get_clk_div(sai, sai_clk_rate, 1189 den); 1190 if (div < 0) 1191 return div; 1192 } 1193 } 1194 } 1195 1196 return stm32_sai_set_clk_div(sai, div); 1197 } 1198 1199 static int stm32_sai_hw_params(struct snd_pcm_substream *substream, 1200 struct snd_pcm_hw_params *params, 1201 struct snd_soc_dai *cpu_dai) 1202 { 1203 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 1204 int ret; 1205 1206 sai->data_size = params_width(params); 1207 1208 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 1209 /* Rate not already set in runtime structure */ 1210 substream->runtime->rate = params_rate(params); 1211 stm32_sai_set_iec958_status(sai, substream->runtime); 1212 } else { 1213 ret = stm32_sai_set_slots(cpu_dai); 1214 if (ret < 0) 1215 return ret; 1216 stm32_sai_set_frame(cpu_dai); 1217 } 1218 1219 ret = stm32_sai_set_config(cpu_dai, substream, params); 1220 if (ret) 1221 return ret; 1222 1223 if (sai->master) 1224 ret = stm32_sai_configure_clock(cpu_dai, params); 1225 1226 return ret; 1227 } 1228 1229 static int stm32_sai_trigger(struct snd_pcm_substream *substream, int cmd, 1230 struct snd_soc_dai *cpu_dai) 1231 { 1232 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 1233 int ret; 1234 1235 switch (cmd) { 1236 case SNDRV_PCM_TRIGGER_START: 1237 case SNDRV_PCM_TRIGGER_RESUME: 1238 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1239 dev_dbg(cpu_dai->dev, "Enable DMA and SAI\n"); 1240 1241 stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, 1242 SAI_XCR1_DMAEN, SAI_XCR1_DMAEN); 1243 1244 /* Enable SAI */ 1245 ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, 1246 SAI_XCR1_SAIEN, SAI_XCR1_SAIEN); 1247 if (ret < 0) 1248 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 1249 break; 1250 case SNDRV_PCM_TRIGGER_SUSPEND: 1251 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1252 case SNDRV_PCM_TRIGGER_STOP: 1253 dev_dbg(cpu_dai->dev, "Disable DMA and SAI\n"); 1254 1255 stm32_sai_sub_reg_up(sai, STM_SAI_IMR_REGX, 1256 SAI_XIMR_MASK, 0); 1257 1258 stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, 1259 SAI_XCR1_SAIEN, 1260 (unsigned int)~SAI_XCR1_SAIEN); 1261 1262 ret = stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, 1263 SAI_XCR1_DMAEN, 1264 (unsigned int)~SAI_XCR1_DMAEN); 1265 if (ret < 0) 1266 dev_err(cpu_dai->dev, "Failed to update CR1 register\n"); 1267 1268 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) 1269 sai->spdif_frm_cnt = 0; 1270 break; 1271 default: 1272 return -EINVAL; 1273 } 1274 1275 return ret; 1276 } 1277 1278 static void stm32_sai_shutdown(struct snd_pcm_substream *substream, 1279 struct snd_soc_dai *cpu_dai) 1280 { 1281 struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai); 1282 1283 stm32_sai_sub_reg_up(sai, STM_SAI_IMR_REGX, SAI_XIMR_MASK, 0); 1284 1285 clk_disable_unprepare(sai->sai_ck); 1286 1287 /* 1288 * Release kernel clock if following conditions are fulfilled 1289 * - Master clock is not used. Kernel clock won't be released trough sysclk 1290 * - Put handler is defined. Involve that clock is managed exclusively 1291 */ 1292 if (!sai->sai_mclk && sai->put_sai_ck_rate) 1293 sai->put_sai_ck_rate(sai); 1294 1295 scoped_guard(spinlock_irqsave, &sai->irq_lock) 1296 sai->substream = NULL; 1297 } 1298 1299 static int stm32_sai_pcm_new(struct snd_soc_pcm_runtime *rtd, 1300 struct snd_soc_dai *cpu_dai) 1301 { 1302 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev); 1303 struct snd_kcontrol_new knew = iec958_ctls; 1304 1305 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) { 1306 dev_dbg(&sai->pdev->dev, "%s: register iec controls", __func__); 1307 knew.device = rtd->pcm->device; 1308 return snd_ctl_add(rtd->pcm->card, snd_ctl_new1(&knew, sai)); 1309 } 1310 1311 return 0; 1312 } 1313 1314 static int stm32_sai_dai_probe(struct snd_soc_dai *cpu_dai) 1315 { 1316 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev); 1317 int cr1 = 0, cr1_mask, ret; 1318 1319 sai->cpu_dai = cpu_dai; 1320 1321 sai->dma_params.addr = (dma_addr_t)(sai->phys_addr + STM_SAI_DR_REGX); 1322 /* 1323 * DMA supports 4, 8 or 16 burst sizes. Burst size 4 is the best choice, 1324 * as it allows bytes, half-word and words transfers. (See DMA fifos 1325 * constraints). 1326 */ 1327 sai->dma_params.maxburst = 4; 1328 if (sai->pdata->conf.fifo_size < 8 || sai->pdata->conf.no_dma_burst) 1329 sai->dma_params.maxburst = 1; 1330 /* Buswidth will be set by framework at runtime */ 1331 sai->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 1332 1333 if (STM_SAI_IS_PLAYBACK(sai)) 1334 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params, NULL); 1335 else 1336 snd_soc_dai_init_dma_data(cpu_dai, NULL, &sai->dma_params); 1337 1338 /* Next settings are not relevant for spdif mode */ 1339 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) 1340 return 0; 1341 1342 cr1_mask = SAI_XCR1_RX_TX; 1343 if (STM_SAI_IS_CAPTURE(sai)) 1344 cr1 |= SAI_XCR1_RX_TX; 1345 1346 /* Configure synchronization */ 1347 if (sai->sync == SAI_SYNC_EXTERNAL) { 1348 /* Configure synchro client and provider */ 1349 ret = sai->pdata->set_sync(sai->pdata, sai->np_sync_provider, 1350 sai->synco, sai->synci); 1351 if (ret) 1352 return ret; 1353 } 1354 1355 cr1_mask |= SAI_XCR1_SYNCEN_MASK; 1356 cr1 |= SAI_XCR1_SYNCEN_SET(sai->sync); 1357 1358 return stm32_sai_sub_reg_up(sai, STM_SAI_CR1_REGX, cr1_mask, cr1); 1359 } 1360 1361 static const struct snd_soc_dai_ops stm32_sai_pcm_dai_ops = { 1362 .probe = stm32_sai_dai_probe, 1363 .set_sysclk = stm32_sai_set_sysclk, 1364 .set_fmt = stm32_sai_set_dai_fmt, 1365 .set_tdm_slot = stm32_sai_set_dai_tdm_slot, 1366 .startup = stm32_sai_startup, 1367 .hw_params = stm32_sai_hw_params, 1368 .trigger = stm32_sai_trigger, 1369 .shutdown = stm32_sai_shutdown, 1370 .pcm_new = stm32_sai_pcm_new, 1371 }; 1372 1373 static const struct snd_soc_dai_ops stm32_sai_pcm_dai_ops2 = { 1374 .probe = stm32_sai_dai_probe, 1375 .set_sysclk = stm32_sai_set_sysclk, 1376 .set_fmt = stm32_sai_set_dai_fmt, 1377 .set_tdm_slot = stm32_sai_set_dai_tdm_slot, 1378 .startup = stm32_sai_startup, 1379 .hw_params = stm32_sai_hw_params, 1380 .trigger = stm32_sai_trigger, 1381 .shutdown = stm32_sai_shutdown, 1382 }; 1383 1384 static int stm32_sai_pcm_process_spdif(struct snd_pcm_substream *substream, 1385 int channel, unsigned long hwoff, 1386 unsigned long bytes) 1387 { 1388 struct snd_pcm_runtime *runtime = substream->runtime; 1389 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 1390 struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0); 1391 struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev); 1392 int *ptr = (int *)(runtime->dma_area + hwoff + 1393 channel * (runtime->dma_bytes / runtime->channels)); 1394 ssize_t cnt = bytes_to_samples(runtime, bytes); 1395 unsigned int frm_cnt = sai->spdif_frm_cnt; 1396 unsigned int byte; 1397 unsigned int mask; 1398 1399 do { 1400 *ptr = ((*ptr >> 8) & 0x00ffffff); 1401 1402 /* Set channel status bit */ 1403 byte = frm_cnt >> 3; 1404 mask = 1 << (frm_cnt - (byte << 3)); 1405 if (sai->iec958.status[byte] & mask) 1406 *ptr |= 0x04000000; 1407 ptr++; 1408 1409 if (!(cnt % 2)) 1410 frm_cnt++; 1411 1412 if (frm_cnt == SAI_IEC60958_BLOCK_FRAMES) 1413 frm_cnt = 0; 1414 } while (--cnt); 1415 sai->spdif_frm_cnt = frm_cnt; 1416 1417 return 0; 1418 } 1419 1420 /* No support of mmap in S/PDIF mode */ 1421 static const struct snd_pcm_hardware stm32_sai_pcm_hw_spdif = { 1422 .info = SNDRV_PCM_INFO_INTERLEAVED, 1423 .buffer_bytes_max = 8 * PAGE_SIZE, 1424 .period_bytes_min = 1024, 1425 .period_bytes_max = PAGE_SIZE, 1426 .periods_min = 2, 1427 .periods_max = 8, 1428 }; 1429 1430 static const struct snd_pcm_hardware stm32_sai_pcm_hw = { 1431 .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP, 1432 .buffer_bytes_max = 8 * PAGE_SIZE, 1433 .period_bytes_min = 1024, /* 5ms at 48kHz */ 1434 .period_bytes_max = PAGE_SIZE, 1435 .periods_min = 2, 1436 .periods_max = 8, 1437 }; 1438 1439 static struct snd_soc_dai_driver stm32_sai_playback_dai = { 1440 .id = 1, /* avoid call to fmt_single_name() */ 1441 .playback = { 1442 .channels_min = 1, 1443 .channels_max = 16, 1444 .rate_min = 8000, 1445 .rate_max = 192000, 1446 .rates = SNDRV_PCM_RATE_CONTINUOUS, 1447 /* DMA does not support 24 bits transfers */ 1448 .formats = 1449 SNDRV_PCM_FMTBIT_S8 | 1450 SNDRV_PCM_FMTBIT_S16_LE | 1451 SNDRV_PCM_FMTBIT_S32_LE, 1452 }, 1453 .ops = &stm32_sai_pcm_dai_ops, 1454 }; 1455 1456 static struct snd_soc_dai_driver stm32_sai_capture_dai = { 1457 .id = 1, /* avoid call to fmt_single_name() */ 1458 .capture = { 1459 .channels_min = 1, 1460 .channels_max = 16, 1461 .rate_min = 8000, 1462 .rate_max = 192000, 1463 .rates = SNDRV_PCM_RATE_CONTINUOUS, 1464 /* DMA does not support 24 bits transfers */ 1465 .formats = 1466 SNDRV_PCM_FMTBIT_S8 | 1467 SNDRV_PCM_FMTBIT_S16_LE | 1468 SNDRV_PCM_FMTBIT_S32_LE, 1469 }, 1470 .ops = &stm32_sai_pcm_dai_ops2, 1471 }; 1472 1473 static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config = { 1474 .pcm_hardware = &stm32_sai_pcm_hw, 1475 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 1476 }; 1477 1478 static const struct snd_dmaengine_pcm_config stm32_sai_pcm_config_spdif = { 1479 .pcm_hardware = &stm32_sai_pcm_hw_spdif, 1480 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 1481 .process = stm32_sai_pcm_process_spdif, 1482 }; 1483 1484 static const struct snd_soc_component_driver stm32_component = { 1485 .name = "stm32-sai", 1486 .legacy_dai_naming = 1, 1487 }; 1488 1489 static const struct of_device_id stm32_sai_sub_ids[] = { 1490 { .compatible = "st,stm32-sai-sub-a", 1491 .data = (void *)STM_SAI_A_ID}, 1492 { .compatible = "st,stm32-sai-sub-b", 1493 .data = (void *)STM_SAI_B_ID}, 1494 {} 1495 }; 1496 MODULE_DEVICE_TABLE(of, stm32_sai_sub_ids); 1497 1498 static int stm32_sai_sub_parse_of(struct platform_device *pdev, 1499 struct stm32_sai_sub_data *sai) 1500 { 1501 struct device_node *np = pdev->dev.of_node; 1502 struct resource *res; 1503 void __iomem *base; 1504 struct of_phandle_args args; 1505 int ret; 1506 1507 if (!np) 1508 return -ENODEV; 1509 1510 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1511 if (IS_ERR(base)) 1512 return PTR_ERR(base); 1513 1514 sai->phys_addr = res->start; 1515 1516 sai->regmap_config = &stm32_sai_sub_regmap_config_f4; 1517 /* Note: PDM registers not available for sub-block B */ 1518 if (STM_SAI_HAS_PDM(sai) && STM_SAI_IS_SUB_A(sai)) 1519 sai->regmap_config = &stm32_sai_sub_regmap_config_h7; 1520 1521 /* 1522 * Do not manage peripheral clock through regmap framework as this 1523 * can lead to circular locking issue with sai master clock provider. 1524 * Manage peripheral clock directly in driver instead. 1525 */ 1526 sai->regmap = devm_regmap_init_mmio(&pdev->dev, base, 1527 sai->regmap_config); 1528 if (IS_ERR(sai->regmap)) 1529 return dev_err_probe(&pdev->dev, PTR_ERR(sai->regmap), 1530 "Regmap init error\n"); 1531 1532 /* Get direction property */ 1533 if (of_property_match_string(np, "dma-names", "tx") >= 0) { 1534 sai->dir = SNDRV_PCM_STREAM_PLAYBACK; 1535 } else if (of_property_match_string(np, "dma-names", "rx") >= 0) { 1536 sai->dir = SNDRV_PCM_STREAM_CAPTURE; 1537 } else { 1538 dev_err(&pdev->dev, "Unsupported direction\n"); 1539 return -EINVAL; 1540 } 1541 1542 /* Get spdif iec60958 property */ 1543 sai->spdif = false; 1544 if (of_property_present(np, "st,iec60958")) { 1545 if (!STM_SAI_HAS_SPDIF(sai) || 1546 sai->dir == SNDRV_PCM_STREAM_CAPTURE) { 1547 dev_err(&pdev->dev, "S/PDIF IEC60958 not supported\n"); 1548 return -EINVAL; 1549 } 1550 stm32_sai_init_iec958_status(sai); 1551 sai->spdif = true; 1552 sai->master = true; 1553 } 1554 1555 /* Get synchronization property */ 1556 args.np = NULL; 1557 ret = of_parse_phandle_with_fixed_args(np, "st,sync", 1, 0, &args); 1558 if (ret < 0 && ret != -ENOENT) { 1559 dev_err(&pdev->dev, "Failed to get st,sync property\n"); 1560 return ret; 1561 } 1562 1563 sai->sync = SAI_SYNC_NONE; 1564 if (args.np) { 1565 if (args.np == np) { 1566 dev_err(&pdev->dev, "%pOFn sync own reference\n", np); 1567 of_node_put(args.np); 1568 return -EINVAL; 1569 } 1570 1571 sai->np_sync_provider = of_get_parent(args.np); 1572 if (!sai->np_sync_provider) { 1573 dev_err(&pdev->dev, "%pOFn parent node not found\n", 1574 np); 1575 of_node_put(args.np); 1576 return -ENODEV; 1577 } 1578 1579 sai->sync = SAI_SYNC_INTERNAL; 1580 if (sai->np_sync_provider != sai->pdata->pdev->dev.of_node) { 1581 if (!STM_SAI_HAS_EXT_SYNC(sai)) { 1582 dev_err(&pdev->dev, 1583 "External synchro not supported\n"); 1584 of_node_put(args.np); 1585 ret = -EINVAL; 1586 goto err_put_sync_provider; 1587 } 1588 sai->sync = SAI_SYNC_EXTERNAL; 1589 1590 sai->synci = args.args[0]; 1591 if (sai->synci < 1 || 1592 (sai->synci > (SAI_GCR_SYNCIN_MAX + 1))) { 1593 dev_err(&pdev->dev, "Wrong SAI index\n"); 1594 of_node_put(args.np); 1595 ret = -EINVAL; 1596 goto err_put_sync_provider; 1597 } 1598 1599 if (of_property_match_string(args.np, "compatible", 1600 "st,stm32-sai-sub-a") >= 0) 1601 sai->synco = STM_SAI_SYNC_OUT_A; 1602 1603 if (of_property_match_string(args.np, "compatible", 1604 "st,stm32-sai-sub-b") >= 0) 1605 sai->synco = STM_SAI_SYNC_OUT_B; 1606 1607 if (!sai->synco) { 1608 dev_err(&pdev->dev, "Unknown SAI sub-block\n"); 1609 of_node_put(args.np); 1610 ret = -EINVAL; 1611 goto err_put_sync_provider; 1612 } 1613 } 1614 1615 dev_dbg(&pdev->dev, "%s synchronized with %s\n", 1616 pdev->name, args.np->full_name); 1617 } 1618 1619 of_node_put(args.np); 1620 sai->sai_ck = devm_clk_get(&pdev->dev, "sai_ck"); 1621 if (IS_ERR(sai->sai_ck)) { 1622 ret = dev_err_probe(&pdev->dev, PTR_ERR(sai->sai_ck), 1623 "Missing kernel clock sai_ck\n"); 1624 goto err_put_sync_provider; 1625 } 1626 1627 ret = clk_prepare(sai->pdata->pclk); 1628 if (ret < 0) 1629 goto err_put_sync_provider; 1630 1631 if (STM_SAI_IS_F4(sai->pdata)) 1632 return 0; 1633 1634 /* Register mclk provider if requested */ 1635 if (of_property_present(np, "#clock-cells")) { 1636 ret = stm32_sai_add_mclk_provider(sai); 1637 if (ret < 0) 1638 goto err_unprepare_pclk; 1639 } else { 1640 sai->sai_mclk = devm_clk_get_optional(&pdev->dev, "MCLK"); 1641 if (IS_ERR(sai->sai_mclk)) { 1642 ret = PTR_ERR(sai->sai_mclk); 1643 goto err_unprepare_pclk; 1644 } 1645 } 1646 1647 return 0; 1648 1649 err_unprepare_pclk: 1650 clk_unprepare(sai->pdata->pclk); 1651 err_put_sync_provider: 1652 of_node_put(sai->np_sync_provider); 1653 1654 return ret; 1655 } 1656 1657 static int stm32_sai_sub_probe(struct platform_device *pdev) 1658 { 1659 struct stm32_sai_sub_data *sai; 1660 const struct snd_dmaengine_pcm_config *conf = &stm32_sai_pcm_config; 1661 int ret; 1662 1663 sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL); 1664 if (!sai) 1665 return -ENOMEM; 1666 1667 sai->id = (uintptr_t)device_get_match_data(&pdev->dev); 1668 1669 sai->pdev = pdev; 1670 mutex_init(&sai->ctrl_lock); 1671 spin_lock_init(&sai->irq_lock); 1672 platform_set_drvdata(pdev, sai); 1673 1674 sai->pdata = dev_get_drvdata(pdev->dev.parent); 1675 if (!sai->pdata) { 1676 dev_err(&pdev->dev, "Parent device data not available\n"); 1677 return -EINVAL; 1678 } 1679 1680 if (sai->pdata->conf.get_sai_ck_parent) { 1681 sai->set_sai_ck_rate = stm32_sai_set_parent_clk; 1682 } else { 1683 sai->set_sai_ck_rate = stm32_sai_set_parent_rate; 1684 sai->put_sai_ck_rate = stm32_sai_put_parent_rate; 1685 } 1686 1687 ret = stm32_sai_sub_parse_of(pdev, sai); 1688 if (ret) 1689 return ret; 1690 1691 if (STM_SAI_IS_PLAYBACK(sai)) 1692 sai->cpu_dai_drv = stm32_sai_playback_dai; 1693 else 1694 sai->cpu_dai_drv = stm32_sai_capture_dai; 1695 sai->cpu_dai_drv.name = dev_name(&pdev->dev); 1696 1697 ret = devm_request_irq(&pdev->dev, sai->pdata->irq, stm32_sai_isr, 1698 IRQF_SHARED, dev_name(&pdev->dev), sai); 1699 if (ret) { 1700 dev_err(&pdev->dev, "IRQ request returned %d\n", ret); 1701 goto err_unprepare_pclk; 1702 } 1703 1704 if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) 1705 conf = &stm32_sai_pcm_config_spdif; 1706 1707 ret = snd_dmaengine_pcm_register(&pdev->dev, conf, 0); 1708 if (ret) { 1709 ret = dev_err_probe(&pdev->dev, ret, "Could not register pcm dma\n"); 1710 goto err_unprepare_pclk; 1711 } 1712 1713 ret = snd_soc_register_component(&pdev->dev, &stm32_component, 1714 &sai->cpu_dai_drv, 1); 1715 if (ret) 1716 goto err_deregister_pcm_dma; 1717 1718 pm_runtime_enable(&pdev->dev); 1719 1720 return 0; 1721 1722 err_deregister_pcm_dma: 1723 snd_dmaengine_pcm_unregister(&pdev->dev); 1724 err_unprepare_pclk: 1725 clk_unprepare(sai->pdata->pclk); 1726 of_node_put(sai->np_sync_provider); 1727 1728 return ret; 1729 } 1730 1731 static void stm32_sai_sub_remove(struct platform_device *pdev) 1732 { 1733 struct stm32_sai_sub_data *sai = dev_get_drvdata(&pdev->dev); 1734 1735 clk_unprepare(sai->pdata->pclk); 1736 snd_dmaengine_pcm_unregister(&pdev->dev); 1737 snd_soc_unregister_component(&pdev->dev); 1738 pm_runtime_disable(&pdev->dev); 1739 of_node_put(sai->np_sync_provider); 1740 } 1741 1742 static int stm32_sai_sub_suspend(struct device *dev) 1743 { 1744 struct stm32_sai_sub_data *sai = dev_get_drvdata(dev); 1745 int ret; 1746 1747 ret = clk_enable(sai->pdata->pclk); 1748 if (ret < 0) 1749 return ret; 1750 1751 regcache_cache_only(sai->regmap, true); 1752 regcache_mark_dirty(sai->regmap); 1753 1754 clk_disable(sai->pdata->pclk); 1755 1756 return 0; 1757 } 1758 1759 static int stm32_sai_sub_resume(struct device *dev) 1760 { 1761 struct stm32_sai_sub_data *sai = dev_get_drvdata(dev); 1762 int ret; 1763 1764 ret = clk_enable(sai->pdata->pclk); 1765 if (ret < 0) 1766 return ret; 1767 1768 regcache_cache_only(sai->regmap, false); 1769 ret = regcache_sync(sai->regmap); 1770 1771 clk_disable(sai->pdata->pclk); 1772 1773 return ret; 1774 } 1775 1776 static const struct dev_pm_ops stm32_sai_sub_pm_ops = { 1777 SYSTEM_SLEEP_PM_OPS(stm32_sai_sub_suspend, stm32_sai_sub_resume) 1778 }; 1779 1780 static struct platform_driver stm32_sai_sub_driver = { 1781 .driver = { 1782 .name = "st,stm32-sai-sub", 1783 .of_match_table = stm32_sai_sub_ids, 1784 .pm = pm_ptr(&stm32_sai_sub_pm_ops), 1785 }, 1786 .probe = stm32_sai_sub_probe, 1787 .remove = stm32_sai_sub_remove, 1788 }; 1789 1790 module_platform_driver(stm32_sai_sub_driver); 1791 1792 MODULE_DESCRIPTION("STM32 Soc SAI sub-block Interface"); 1793 MODULE_AUTHOR("Olivier Moysan <olivier.moysan@st.com>"); 1794 MODULE_ALIAS("platform:st,stm32-sai-sub"); 1795 MODULE_LICENSE("GPL v2"); 1796