1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * linux/arch/arm/mach-sa1100/gpio.c
4 *
5 * Generic SA-1100 GPIO handling
6 */
7 #include <linux/gpio/driver.h>
8 #include <linux/init.h>
9 #include <linux/module.h>
10 #include <linux/io.h>
11 #include <linux/syscore_ops.h>
12 #include <soc/sa1100/pwer.h>
13 #include <mach/hardware.h>
14 #include <mach/irqs.h>
15 #include <mach/generic.h>
16
17 struct sa1100_gpio_chip {
18 struct gpio_chip chip;
19 void __iomem *membase;
20 int irqbase;
21 u32 irqmask;
22 u32 irqrising;
23 u32 irqfalling;
24 u32 irqwake;
25 };
26
27 #define sa1100_gpio_chip(x) container_of(x, struct sa1100_gpio_chip, chip)
28
29 enum {
30 R_GPLR = 0x00,
31 R_GPDR = 0x04,
32 R_GPSR = 0x08,
33 R_GPCR = 0x0c,
34 R_GRER = 0x10,
35 R_GFER = 0x14,
36 R_GEDR = 0x18,
37 R_GAFR = 0x1c,
38 };
39
sa1100_gpio_get(struct gpio_chip * chip,unsigned offset)40 static int sa1100_gpio_get(struct gpio_chip *chip, unsigned offset)
41 {
42 return readl_relaxed(sa1100_gpio_chip(chip)->membase + R_GPLR) &
43 BIT(offset);
44 }
45
sa1100_gpio_set(struct gpio_chip * chip,unsigned offset,int value)46 static void sa1100_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
47 {
48 int reg = value ? R_GPSR : R_GPCR;
49
50 writel_relaxed(BIT(offset), sa1100_gpio_chip(chip)->membase + reg);
51 }
52
sa1100_get_direction(struct gpio_chip * chip,unsigned offset)53 static int sa1100_get_direction(struct gpio_chip *chip, unsigned offset)
54 {
55 void __iomem *gpdr = sa1100_gpio_chip(chip)->membase + R_GPDR;
56
57 if (readl_relaxed(gpdr) & BIT(offset))
58 return GPIO_LINE_DIRECTION_OUT;
59
60 return GPIO_LINE_DIRECTION_IN;
61 }
62
sa1100_direction_input(struct gpio_chip * chip,unsigned offset)63 static int sa1100_direction_input(struct gpio_chip *chip, unsigned offset)
64 {
65 void __iomem *gpdr = sa1100_gpio_chip(chip)->membase + R_GPDR;
66 unsigned long flags;
67
68 local_irq_save(flags);
69 writel_relaxed(readl_relaxed(gpdr) & ~BIT(offset), gpdr);
70 local_irq_restore(flags);
71
72 return 0;
73 }
74
sa1100_direction_output(struct gpio_chip * chip,unsigned offset,int value)75 static int sa1100_direction_output(struct gpio_chip *chip, unsigned offset, int value)
76 {
77 void __iomem *gpdr = sa1100_gpio_chip(chip)->membase + R_GPDR;
78 unsigned long flags;
79
80 local_irq_save(flags);
81 sa1100_gpio_set(chip, offset, value);
82 writel_relaxed(readl_relaxed(gpdr) | BIT(offset), gpdr);
83 local_irq_restore(flags);
84
85 return 0;
86 }
87
sa1100_to_irq(struct gpio_chip * chip,unsigned offset)88 static int sa1100_to_irq(struct gpio_chip *chip, unsigned offset)
89 {
90 return sa1100_gpio_chip(chip)->irqbase + offset;
91 }
92
93 static struct sa1100_gpio_chip sa1100_gpio_chip = {
94 .chip = {
95 .label = "gpio",
96 .get_direction = sa1100_get_direction,
97 .direction_input = sa1100_direction_input,
98 .direction_output = sa1100_direction_output,
99 .set = sa1100_gpio_set,
100 .get = sa1100_gpio_get,
101 .to_irq = sa1100_to_irq,
102 .base = 0,
103 .ngpio = GPIO_MAX + 1,
104 },
105 .membase = (void *)&GPLR,
106 .irqbase = IRQ_GPIO0,
107 };
108
109 /*
110 * SA1100 GPIO edge detection for IRQs:
111 * IRQs are generated on Falling-Edge, Rising-Edge, or both.
112 * Use this instead of directly setting GRER/GFER.
113 */
sa1100_update_edge_regs(struct sa1100_gpio_chip * sgc)114 static void sa1100_update_edge_regs(struct sa1100_gpio_chip *sgc)
115 {
116 void *base = sgc->membase;
117 u32 grer, gfer;
118
119 grer = sgc->irqrising & sgc->irqmask;
120 gfer = sgc->irqfalling & sgc->irqmask;
121
122 writel_relaxed(grer, base + R_GRER);
123 writel_relaxed(gfer, base + R_GFER);
124 }
125
sa1100_gpio_type(struct irq_data * d,unsigned int type)126 static int sa1100_gpio_type(struct irq_data *d, unsigned int type)
127 {
128 struct sa1100_gpio_chip *sgc = irq_data_get_irq_chip_data(d);
129 unsigned int mask = BIT(d->hwirq);
130
131 if (type == IRQ_TYPE_PROBE) {
132 if ((sgc->irqrising | sgc->irqfalling) & mask)
133 return 0;
134 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
135 }
136
137 if (type & IRQ_TYPE_EDGE_RISING)
138 sgc->irqrising |= mask;
139 else
140 sgc->irqrising &= ~mask;
141 if (type & IRQ_TYPE_EDGE_FALLING)
142 sgc->irqfalling |= mask;
143 else
144 sgc->irqfalling &= ~mask;
145
146 sa1100_update_edge_regs(sgc);
147
148 return 0;
149 }
150
151 /*
152 * GPIO IRQs must be acknowledged.
153 */
sa1100_gpio_ack(struct irq_data * d)154 static void sa1100_gpio_ack(struct irq_data *d)
155 {
156 struct sa1100_gpio_chip *sgc = irq_data_get_irq_chip_data(d);
157
158 writel_relaxed(BIT(d->hwirq), sgc->membase + R_GEDR);
159 }
160
sa1100_gpio_mask(struct irq_data * d)161 static void sa1100_gpio_mask(struct irq_data *d)
162 {
163 struct sa1100_gpio_chip *sgc = irq_data_get_irq_chip_data(d);
164 unsigned int mask = BIT(d->hwirq);
165
166 sgc->irqmask &= ~mask;
167
168 sa1100_update_edge_regs(sgc);
169 }
170
sa1100_gpio_unmask(struct irq_data * d)171 static void sa1100_gpio_unmask(struct irq_data *d)
172 {
173 struct sa1100_gpio_chip *sgc = irq_data_get_irq_chip_data(d);
174 unsigned int mask = BIT(d->hwirq);
175
176 sgc->irqmask |= mask;
177
178 sa1100_update_edge_regs(sgc);
179 }
180
sa1100_gpio_wake(struct irq_data * d,unsigned int on)181 static int sa1100_gpio_wake(struct irq_data *d, unsigned int on)
182 {
183 struct sa1100_gpio_chip *sgc = irq_data_get_irq_chip_data(d);
184 int ret = sa11x0_gpio_set_wake(d->hwirq, on);
185 if (!ret) {
186 if (on)
187 sgc->irqwake |= BIT(d->hwirq);
188 else
189 sgc->irqwake &= ~BIT(d->hwirq);
190 }
191 return ret;
192 }
193
194 /*
195 * This is for GPIO IRQs
196 */
197 static struct irq_chip sa1100_gpio_irq_chip = {
198 .name = "GPIO",
199 .irq_ack = sa1100_gpio_ack,
200 .irq_mask = sa1100_gpio_mask,
201 .irq_unmask = sa1100_gpio_unmask,
202 .irq_set_type = sa1100_gpio_type,
203 .irq_set_wake = sa1100_gpio_wake,
204 };
205
sa1100_gpio_irqdomain_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hwirq)206 static int sa1100_gpio_irqdomain_map(struct irq_domain *d,
207 unsigned int irq, irq_hw_number_t hwirq)
208 {
209 struct sa1100_gpio_chip *sgc = d->host_data;
210
211 irq_set_chip_data(irq, sgc);
212 irq_set_chip_and_handler(irq, &sa1100_gpio_irq_chip, handle_edge_irq);
213 irq_set_probe(irq);
214
215 return 0;
216 }
217
218 static const struct irq_domain_ops sa1100_gpio_irqdomain_ops = {
219 .map = sa1100_gpio_irqdomain_map,
220 .xlate = irq_domain_xlate_onetwocell,
221 };
222
223 static struct irq_domain *sa1100_gpio_irqdomain;
224
225 /*
226 * IRQ 0-11 (GPIO) handler. We enter here with the
227 * irq_controller_lock held, and IRQs disabled. Decode the IRQ
228 * and call the handler.
229 */
sa1100_gpio_handler(struct irq_desc * desc)230 static void sa1100_gpio_handler(struct irq_desc *desc)
231 {
232 struct sa1100_gpio_chip *sgc = irq_desc_get_handler_data(desc);
233 unsigned int irq, mask;
234 void __iomem *gedr = sgc->membase + R_GEDR;
235
236 mask = readl_relaxed(gedr);
237 do {
238 /*
239 * clear down all currently active IRQ sources.
240 * We will be processing them all.
241 */
242 writel_relaxed(mask, gedr);
243
244 irq = sgc->irqbase;
245 do {
246 if (mask & 1)
247 generic_handle_irq(irq);
248 mask >>= 1;
249 irq++;
250 } while (mask);
251
252 mask = readl_relaxed(gedr);
253 } while (mask);
254 }
255
sa1100_gpio_suspend(void)256 static int sa1100_gpio_suspend(void)
257 {
258 struct sa1100_gpio_chip *sgc = &sa1100_gpio_chip;
259
260 /*
261 * Set the appropriate edges for wakeup.
262 */
263 writel_relaxed(sgc->irqwake & sgc->irqrising, sgc->membase + R_GRER);
264 writel_relaxed(sgc->irqwake & sgc->irqfalling, sgc->membase + R_GFER);
265
266 /*
267 * Clear any pending GPIO interrupts.
268 */
269 writel_relaxed(readl_relaxed(sgc->membase + R_GEDR),
270 sgc->membase + R_GEDR);
271
272 return 0;
273 }
274
sa1100_gpio_resume(void)275 static void sa1100_gpio_resume(void)
276 {
277 sa1100_update_edge_regs(&sa1100_gpio_chip);
278 }
279
280 static struct syscore_ops sa1100_gpio_syscore_ops = {
281 .suspend = sa1100_gpio_suspend,
282 .resume = sa1100_gpio_resume,
283 };
284
sa1100_gpio_init_devicefs(void)285 static int __init sa1100_gpio_init_devicefs(void)
286 {
287 register_syscore_ops(&sa1100_gpio_syscore_ops);
288 return 0;
289 }
290
291 device_initcall(sa1100_gpio_init_devicefs);
292
293 static const int sa1100_gpio_irqs[] __initconst = {
294 /* Install handlers for GPIO 0-10 edge detect interrupts */
295 IRQ_GPIO0_SC,
296 IRQ_GPIO1_SC,
297 IRQ_GPIO2_SC,
298 IRQ_GPIO3_SC,
299 IRQ_GPIO4_SC,
300 IRQ_GPIO5_SC,
301 IRQ_GPIO6_SC,
302 IRQ_GPIO7_SC,
303 IRQ_GPIO8_SC,
304 IRQ_GPIO9_SC,
305 IRQ_GPIO10_SC,
306 /* Install handler for GPIO 11-27 edge detect interrupts */
307 IRQ_GPIO11_27,
308 };
309
sa1100_init_gpio(void)310 void __init sa1100_init_gpio(void)
311 {
312 struct sa1100_gpio_chip *sgc = &sa1100_gpio_chip;
313 int i;
314
315 /* clear all GPIO edge detects */
316 writel_relaxed(0, sgc->membase + R_GFER);
317 writel_relaxed(0, sgc->membase + R_GRER);
318 writel_relaxed(-1, sgc->membase + R_GEDR);
319
320 gpiochip_add_data(&sa1100_gpio_chip.chip, NULL);
321
322 sa1100_gpio_irqdomain = irq_domain_add_simple(NULL,
323 28, IRQ_GPIO0,
324 &sa1100_gpio_irqdomain_ops, sgc);
325
326 for (i = 0; i < ARRAY_SIZE(sa1100_gpio_irqs); i++)
327 irq_set_chained_handler_and_data(sa1100_gpio_irqs[i],
328 sa1100_gpio_handler, sgc);
329 }
330