xref: /linux/arch/arm/mm/proc-sa1100.S (revision 4853f1f6ace32c68a04287353e428c4cfc3fa8ed) 
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 *  linux/arch/arm/mm/proc-sa1100.S
4 *
5 *  Copyright (C) 1997-2002 Russell King
6 *  hacked for non-paged-MM by Hyok S. Choi, 2003.
7 *
8 *  MMU functions for SA110
9 *
10 *  These are the low level assembler for performing cache and TLB
11 *  functions on the StrongARM-1100 and StrongARM-1110.
12 *
13 *  Note that SA1100 and SA1110 share everything but their name and CPU ID.
14 *
15 *  12-jun-2000, Erik Mouw (J.A.K.Mouw@its.tudelft.nl):
16 *    Flush the read buffer at context switches
17 */
18#include <linux/linkage.h>
19#include <linux/init.h>
20#include <linux/cfi_types.h>
21#include <linux/pgtable.h>
22#include <asm/assembler.h>
23#include <asm/asm-offsets.h>
24#include <asm/hwcap.h>
25#include <mach/hardware.h>
26#include <asm/pgtable-hwdef.h>
27
28#include "proc-macros.S"
29
30/*
31 * the cache line size of the I and D cache
32 */
33#define DCACHELINESIZE	32
34
35	.section .text
36
37/*
38 * cpu_sa1100_proc_init()
39 */
40SYM_TYPED_FUNC_START(cpu_sa1100_proc_init)
41	mov	r0, #0
42	mcr	p15, 0, r0, c15, c1, 2		@ Enable clock switching
43	mcr	p15, 0, r0, c9, c0, 5		@ Allow read-buffer operations from userland
44	ret	lr
45SYM_FUNC_END(cpu_sa1100_proc_init)
46
47/*
48 * cpu_sa1100_proc_fin()
49 *
50 * Prepare the CPU for reset:
51 *  - Disable interrupts
52 *  - Clean and turn off caches.
53 */
54SYM_TYPED_FUNC_START(cpu_sa1100_proc_fin)
55	mcr	p15, 0, ip, c15, c2, 2		@ Disable clock switching
56	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
57	bic	r0, r0, #0x1000			@ ...i............
58	bic	r0, r0, #0x000e			@ ............wca.
59	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
60	ret	lr
61SYM_FUNC_END(cpu_sa1100_proc_fin)
62
63/*
64 * cpu_sa1100_reset(loc)
65 *
66 * Perform a soft reset of the system.  Put the CPU into the
67 * same state as it would be if it had been reset, and branch
68 * to what would be the reset vector.
69 *
70 * loc: location to jump to for soft reset
71 */
72	.align	5
73	.pushsection	.idmap.text, "ax"
74SYM_TYPED_FUNC_START(cpu_sa1100_reset)
75	mov	ip, #0
76	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches
77	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
78#ifdef CONFIG_MMU
79	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
80#endif
81	mrc	p15, 0, ip, c1, c0, 0		@ ctrl register
82	bic	ip, ip, #0x000f			@ ............wcam
83	bic	ip, ip, #0x1100			@ ...i...s........
84	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
85	ret	r0
86SYM_FUNC_END(cpu_sa1100_reset)
87	.popsection
88
89/*
90 * cpu_sa1100_do_idle(type)
91 *
92 * Cause the processor to idle
93 *
94 * type: call type:
95 *   0 = slow idle
96 *   1 = fast idle
97 *   2 = switch to slow processor clock
98 *   3 = switch to fast processor clock
99 */
100	.align	5
101SYM_TYPED_FUNC_START(cpu_sa1100_do_idle)
102	mov	r0, r0				@ 4 nop padding
103	mov	r0, r0
104	mov	r0, r0
105	mov	r0, r0				@ 4 nop padding
106	mov	r0, r0
107	mov	r0, r0
108	mov	r0, #0
109	ldr	r1, =UNCACHEABLE_ADDR		@ ptr to uncacheable address
110	@ --- aligned to a cache line
111	mcr	p15, 0, r0, c15, c2, 2		@ disable clock switching
112	ldr	r1, [r1, #0]			@ force switch to MCLK
113	mcr	p15, 0, r0, c15, c8, 2		@ wait for interrupt
114	mov	r0, r0				@ safety
115	mcr	p15, 0, r0, c15, c1, 2		@ enable clock switching
116	ret	lr
117SYM_FUNC_END(cpu_sa1100_do_idle)
118
119/* ================================= CACHE ================================ */
120
121/*
122 * cpu_sa1100_dcache_clean_area(addr,sz)
123 *
124 * Clean the specified entry of any caches such that the MMU
125 * translation fetches will obtain correct data.
126 *
127 * addr: cache-unaligned virtual address
128 */
129	.align	5
130SYM_TYPED_FUNC_START(cpu_sa1100_dcache_clean_area)
1311:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
132	add	r0, r0, #DCACHELINESIZE
133	subs	r1, r1, #DCACHELINESIZE
134	bhi	1b
135	ret	lr
136SYM_FUNC_END(cpu_sa1100_dcache_clean_area)
137
138/* =============================== PageTable ============================== */
139
140/*
141 * cpu_sa1100_switch_mm(pgd)
142 *
143 * Set the translation base pointer to be as described by pgd.
144 *
145 * pgd: new page tables
146 */
147	.align	5
148SYM_TYPED_FUNC_START(cpu_sa1100_switch_mm)
149#ifdef CONFIG_MMU
150	str	lr, [sp, #-4]!
151	bl	v4wb_flush_kern_cache_all	@ clears IP
152	mcr	p15, 0, ip, c9, c0, 0		@ invalidate RB
153	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer
154	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
155	ldr	pc, [sp], #4
156#else
157	ret	lr
158#endif
159SYM_FUNC_END(cpu_sa1100_switch_mm)
160
161/*
162 * cpu_sa1100_set_pte_ext(ptep, pte, ext)
163 *
164 * Set a PTE and flush it out
165 */
166	.align	5
167SYM_TYPED_FUNC_START(cpu_sa1100_set_pte_ext)
168#ifdef CONFIG_MMU
169	armv3_set_pte_ext wc_disable=0
170	mov	r0, r0
171	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
172	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
173#endif
174	ret	lr
175SYM_FUNC_END(cpu_sa1100_set_pte_ext)
176
177.globl	cpu_sa1100_suspend_size
178.equ	cpu_sa1100_suspend_size, 4 * 3
179#ifdef CONFIG_ARM_CPU_SUSPEND
180SYM_TYPED_FUNC_START(cpu_sa1100_do_suspend)
181	stmfd	sp!, {r4 - r6, lr}
182	mrc	p15, 0, r4, c3, c0, 0		@ domain ID
183	mrc	p15, 0, r5, c13, c0, 0		@ PID
184	mrc	p15, 0, r6, c1, c0, 0		@ control reg
185	stmia	r0, {r4 - r6}			@ store cp regs
186	ldmfd	sp!, {r4 - r6, pc}
187SYM_FUNC_END(cpu_sa1100_do_suspend)
188
189SYM_TYPED_FUNC_START(cpu_sa1100_do_resume)
190	ldmia	r0, {r4 - r6}			@ load cp regs
191	mov	ip, #0
192	mcr	p15, 0, ip, c8, c7, 0		@ flush I+D TLBs
193	mcr	p15, 0, ip, c7, c7, 0		@ flush I&D cache
194	mcr	p15, 0, ip, c9, c0, 0		@ invalidate RB
195	mcr	p15, 0, ip, c9, c0, 5		@ allow user space to use RB
196
197	mcr	p15, 0, r4, c3, c0, 0		@ domain ID
198	mcr	p15, 0, r1, c2, c0, 0		@ translation table base addr
199	mcr	p15, 0, r5, c13, c0, 0		@ PID
200	mov	r0, r6				@ control register
201	b	cpu_resume_mmu
202SYM_FUNC_END(cpu_sa1100_do_resume)
203#endif
204
205	.type	__sa1100_setup, #function
206__sa1100_setup:
207	mov	r0, #0
208	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4
209	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer on v4
210#ifdef CONFIG_MMU
211	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4
212#endif
213	adr	r5, sa1100_crval
214	ldmia	r5, {r5, r6}
215	mrc	p15, 0, r0, c1, c0		@ get control register v4
216	bic	r0, r0, r5
217	orr	r0, r0, r6
218	ret	lr
219	.size	__sa1100_setup, . - __sa1100_setup
220
221	/*
222	 *  R
223	 * .RVI ZFRS BLDP WCAM
224	 * ..11 0001 ..11 1101
225	 *
226	 */
227	.type	sa1100_crval, #object
228sa1100_crval:
229	crval	clear=0x00003f3f, mmuset=0x0000313d, ucset=0x00001130
230
231	__INITDATA
232
233/*
234 * SA1100 and SA1110 share the same function calls
235 */
236
237	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
238	define_processor_functions sa1100, dabort=v4_early_abort, pabort=legacy_pabort, suspend=1
239
240	.section ".rodata"
241
242	string	cpu_arch_name, "armv4"
243	string	cpu_elf_name, "v4"
244	string	cpu_sa1100_name, "StrongARM-1100"
245	string	cpu_sa1110_name, "StrongARM-1110"
246
247	.align
248
249	.section ".proc.info.init", "a"
250
251.macro sa1100_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req
252	.type	__\name\()_proc_info,#object
253__\name\()_proc_info:
254	.long	\cpu_val
255	.long	\cpu_mask
256	.long   PMD_TYPE_SECT | \
257		PMD_SECT_BUFFERABLE | \
258		PMD_SECT_CACHEABLE | \
259		PMD_SECT_AP_WRITE | \
260		PMD_SECT_AP_READ
261	.long   PMD_TYPE_SECT | \
262		PMD_SECT_AP_WRITE | \
263		PMD_SECT_AP_READ
264	initfn	__sa1100_setup, __\name\()_proc_info
265	.long	cpu_arch_name
266	.long	cpu_elf_name
267	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT | HWCAP_FAST_MULT
268	.long	\cpu_name
269	.long	sa1100_processor_functions
270	.long	v4wb_tlb_fns
271	.long	v4_mc_user_fns
272	.long	v4wb_cache_fns
273	.size	__\name\()_proc_info, . - __\name\()_proc_info
274.endm
275
276	sa1100_proc_info sa1100, 0x4401a110, 0xfffffff0, cpu_sa1100_name
277	sa1100_proc_info sa1110, 0x6901b110, 0xfffffff0, cpu_sa1110_name
278