1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // Copyright (c) 2013-2014 Samsung Electronics Co., Ltd
4 // http://www.samsung.com
5 //
6 // Copyright (C) 2013 Google, Inc
7
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
10 #include <linux/module.h>
11 #include <linux/i2c.h>
12 #include <linux/bcd.h>
13 #include <linux/reboot.h>
14 #include <linux/regmap.h>
15 #include <linux/rtc.h>
16 #include <linux/platform_device.h>
17 #include <linux/mfd/samsung/core.h>
18 #include <linux/mfd/samsung/irq.h>
19 #include <linux/mfd/samsung/rtc.h>
20 #include <linux/mfd/samsung/s2mps14.h>
21
22 /*
23 * Maximum number of retries for checking changes in UDR field
24 * of S5M_RTC_UDR_CON register (to limit possible endless loop).
25 *
26 * After writing to RTC registers (setting time or alarm) read the UDR field
27 * in S5M_RTC_UDR_CON register. UDR is auto-cleared when data have
28 * been transferred.
29 */
30 #define UDR_READ_RETRY_CNT 5
31
32 enum {
33 RTC_SEC = 0,
34 RTC_MIN,
35 RTC_HOUR,
36 RTC_WEEKDAY,
37 RTC_DATE,
38 RTC_MONTH,
39 RTC_YEAR1,
40 RTC_YEAR2,
41 /* Make sure this is always the last enum name. */
42 RTC_MAX_NUM_TIME_REGS
43 };
44
45 /*
46 * Registers used by the driver which are different between chipsets.
47 *
48 * Operations like read time and write alarm/time require updating
49 * specific fields in UDR register. These fields usually are auto-cleared
50 * (with some exceptions).
51 *
52 * Table of operations per device:
53 *
54 * Device | Write time | Read time | Write alarm
55 * =================================================
56 * S5M8767 | UDR + TIME | | UDR
57 * S2MPG10 | WUDR | RUDR | AUDR
58 * S2MPS11/14 | WUDR | RUDR | WUDR + RUDR
59 * S2MPS13 | WUDR | RUDR | WUDR + AUDR
60 * S2MPS15 | WUDR | RUDR | AUDR
61 */
62 struct s5m_rtc_reg_config {
63 /* Number of registers used for setting time/alarm0/alarm1 */
64 unsigned int regs_count;
65 /* First register for time, seconds */
66 unsigned int time;
67 /* RTC control register */
68 unsigned int ctrl;
69 /* First register for alarm 0, seconds */
70 unsigned int alarm0;
71 /* First register for alarm 1, seconds */
72 unsigned int alarm1;
73 /*
74 * Register for update flag (UDR). Typically setting UDR field to 1
75 * will enable update of time or alarm register. Then it will be
76 * auto-cleared after successful update.
77 */
78 unsigned int udr_update;
79 /* Auto-cleared mask in UDR field for writing time and alarm */
80 unsigned int autoclear_udr_mask;
81 /*
82 * Masks in UDR field for time and alarm operations.
83 * The read time mask can be 0. Rest should not.
84 */
85 unsigned int read_time_udr_mask;
86 unsigned int write_time_udr_mask;
87 unsigned int write_alarm_udr_mask;
88 };
89
90 /* Register map for S5M8767 */
91 static const struct s5m_rtc_reg_config s5m_rtc_regs = {
92 .regs_count = 8,
93 .time = S5M_RTC_SEC,
94 .ctrl = S5M_ALARM1_CONF,
95 .alarm0 = S5M_ALARM0_SEC,
96 .alarm1 = S5M_ALARM1_SEC,
97 .udr_update = S5M_RTC_UDR_CON,
98 .autoclear_udr_mask = S5M_RTC_UDR_MASK,
99 .read_time_udr_mask = 0, /* Not needed */
100 .write_time_udr_mask = S5M_RTC_UDR_MASK | S5M_RTC_TIME_EN_MASK,
101 .write_alarm_udr_mask = S5M_RTC_UDR_MASK,
102 };
103
104 /* Register map for S2MPG10 */
105 static const struct s5m_rtc_reg_config s2mpg10_rtc_regs = {
106 .regs_count = 7,
107 .time = S2MPG10_RTC_SEC,
108 .ctrl = S2MPG10_RTC_CTRL,
109 .alarm0 = S2MPG10_RTC_A0SEC,
110 .alarm1 = S2MPG10_RTC_A1SEC,
111 .udr_update = S2MPG10_RTC_UPDATE,
112 .autoclear_udr_mask = S2MPS15_RTC_WUDR_MASK | S2MPS15_RTC_AUDR_MASK,
113 .read_time_udr_mask = S2MPS_RTC_RUDR_MASK,
114 .write_time_udr_mask = S2MPS15_RTC_WUDR_MASK,
115 .write_alarm_udr_mask = S2MPS15_RTC_AUDR_MASK,
116 };
117
118 /* Register map for S2MPS13 */
119 static const struct s5m_rtc_reg_config s2mps13_rtc_regs = {
120 .regs_count = 7,
121 .time = S2MPS_RTC_SEC,
122 .ctrl = S2MPS_RTC_CTRL,
123 .alarm0 = S2MPS_ALARM0_SEC,
124 .alarm1 = S2MPS_ALARM1_SEC,
125 .udr_update = S2MPS_RTC_UDR_CON,
126 .autoclear_udr_mask = S2MPS_RTC_WUDR_MASK,
127 .read_time_udr_mask = S2MPS_RTC_RUDR_MASK,
128 .write_time_udr_mask = S2MPS_RTC_WUDR_MASK,
129 .write_alarm_udr_mask = S2MPS_RTC_WUDR_MASK | S2MPS13_RTC_AUDR_MASK,
130 };
131
132 /* Register map for S2MPS11/14 */
133 static const struct s5m_rtc_reg_config s2mps14_rtc_regs = {
134 .regs_count = 7,
135 .time = S2MPS_RTC_SEC,
136 .ctrl = S2MPS_RTC_CTRL,
137 .alarm0 = S2MPS_ALARM0_SEC,
138 .alarm1 = S2MPS_ALARM1_SEC,
139 .udr_update = S2MPS_RTC_UDR_CON,
140 .autoclear_udr_mask = S2MPS_RTC_WUDR_MASK,
141 .read_time_udr_mask = S2MPS_RTC_RUDR_MASK,
142 .write_time_udr_mask = S2MPS_RTC_WUDR_MASK,
143 .write_alarm_udr_mask = S2MPS_RTC_WUDR_MASK | S2MPS_RTC_RUDR_MASK,
144 };
145
146 /*
147 * Register map for S2MPS15 - in comparison to S2MPS14 the WUDR and AUDR bits
148 * are swapped.
149 */
150 static const struct s5m_rtc_reg_config s2mps15_rtc_regs = {
151 .regs_count = 7,
152 .time = S2MPS_RTC_SEC,
153 .ctrl = S2MPS_RTC_CTRL,
154 .alarm0 = S2MPS_ALARM0_SEC,
155 .alarm1 = S2MPS_ALARM1_SEC,
156 .udr_update = S2MPS_RTC_UDR_CON,
157 .autoclear_udr_mask = S2MPS_RTC_WUDR_MASK,
158 .read_time_udr_mask = S2MPS_RTC_RUDR_MASK,
159 .write_time_udr_mask = S2MPS15_RTC_WUDR_MASK,
160 .write_alarm_udr_mask = S2MPS15_RTC_AUDR_MASK,
161 };
162
163 struct s5m_rtc_info {
164 struct device *dev;
165 struct sec_pmic_dev *s5m87xx;
166 struct regmap *regmap;
167 struct rtc_device *rtc_dev;
168 int irq;
169 enum sec_device_type device_type;
170 int rtc_24hr_mode;
171 const struct s5m_rtc_reg_config *regs;
172 };
173
174 static const struct regmap_config s5m_rtc_regmap_config = {
175 .reg_bits = 8,
176 .val_bits = 8,
177
178 .max_register = S5M_RTC_REG_MAX,
179 };
180
181 static const struct regmap_config s2mps14_rtc_regmap_config = {
182 .reg_bits = 8,
183 .val_bits = 8,
184
185 .max_register = S2MPS_RTC_REG_MAX,
186 };
187
s5m8767_data_to_tm(u8 * data,struct rtc_time * tm,int rtc_24hr_mode)188 static void s5m8767_data_to_tm(u8 *data, struct rtc_time *tm,
189 int rtc_24hr_mode)
190 {
191 tm->tm_sec = data[RTC_SEC] & 0x7f;
192 tm->tm_min = data[RTC_MIN] & 0x7f;
193 if (rtc_24hr_mode) {
194 tm->tm_hour = data[RTC_HOUR] & 0x1f;
195 } else {
196 tm->tm_hour = data[RTC_HOUR] & 0x0f;
197 if (data[RTC_HOUR] & HOUR_PM_MASK)
198 tm->tm_hour += 12;
199 }
200
201 tm->tm_wday = ffs(data[RTC_WEEKDAY] & 0x7f);
202 tm->tm_mday = data[RTC_DATE] & 0x1f;
203 tm->tm_mon = (data[RTC_MONTH] & 0x0f) - 1;
204 tm->tm_year = (data[RTC_YEAR1] & 0x7f) + 100;
205 tm->tm_yday = 0;
206 tm->tm_isdst = 0;
207 }
208
s5m8767_tm_to_data(struct rtc_time * tm,u8 * data)209 static int s5m8767_tm_to_data(struct rtc_time *tm, u8 *data)
210 {
211 data[RTC_SEC] = tm->tm_sec;
212 data[RTC_MIN] = tm->tm_min;
213
214 if (tm->tm_hour >= 12)
215 data[RTC_HOUR] = tm->tm_hour | HOUR_PM_MASK;
216 else
217 data[RTC_HOUR] = tm->tm_hour & ~HOUR_PM_MASK;
218
219 data[RTC_WEEKDAY] = 1 << tm->tm_wday;
220 data[RTC_DATE] = tm->tm_mday;
221 data[RTC_MONTH] = tm->tm_mon + 1;
222 data[RTC_YEAR1] = tm->tm_year - 100;
223
224 return 0;
225 }
226
227 /*
228 * Read RTC_UDR_CON register and wait till UDR field is cleared.
229 * This indicates that time/alarm update ended.
230 */
s5m8767_wait_for_udr_update(struct s5m_rtc_info * info)231 static int s5m8767_wait_for_udr_update(struct s5m_rtc_info *info)
232 {
233 int ret, retry = UDR_READ_RETRY_CNT;
234 unsigned int data;
235
236 do {
237 ret = regmap_read(info->regmap, info->regs->udr_update, &data);
238 } while (--retry && (data & info->regs->autoclear_udr_mask) && !ret);
239
240 if (!retry)
241 dev_err(info->dev, "waiting for UDR update, reached max number of retries\n");
242
243 return ret;
244 }
245
s5m_check_pending_alarm_interrupt(struct s5m_rtc_info * info,struct rtc_wkalrm * alarm)246 static int s5m_check_pending_alarm_interrupt(struct s5m_rtc_info *info,
247 struct rtc_wkalrm *alarm)
248 {
249 int ret;
250 unsigned int val;
251
252 switch (info->device_type) {
253 case S5M8767X:
254 ret = regmap_read(info->regmap, S5M_RTC_STATUS, &val);
255 val &= S5M_ALARM0_STATUS;
256 break;
257 case S2MPG10:
258 case S2MPS15X:
259 case S2MPS14X:
260 case S2MPS13X:
261 ret = regmap_read(info->s5m87xx->regmap_pmic, S2MPS14_REG_ST2,
262 &val);
263 val &= S2MPS_ALARM0_STATUS;
264 break;
265 default:
266 return -EINVAL;
267 }
268 if (ret < 0)
269 return ret;
270
271 if (val)
272 alarm->pending = 1;
273 else
274 alarm->pending = 0;
275
276 return 0;
277 }
278
s5m8767_rtc_set_time_reg(struct s5m_rtc_info * info)279 static int s5m8767_rtc_set_time_reg(struct s5m_rtc_info *info)
280 {
281 int ret;
282
283 ret = regmap_set_bits(info->regmap, info->regs->udr_update,
284 info->regs->write_time_udr_mask);
285 if (ret < 0) {
286 dev_err(info->dev, "failed to write update reg(%d)\n", ret);
287 return ret;
288 }
289
290 ret = s5m8767_wait_for_udr_update(info);
291
292 return ret;
293 }
294
s5m8767_rtc_set_alarm_reg(struct s5m_rtc_info * info)295 static int s5m8767_rtc_set_alarm_reg(struct s5m_rtc_info *info)
296 {
297 int ret;
298 unsigned int udr_mask;
299
300 udr_mask = info->regs->write_alarm_udr_mask;
301 switch (info->device_type) {
302 case S5M8767X:
303 udr_mask |= S5M_RTC_TIME_EN_MASK;
304 break;
305 case S2MPG10:
306 case S2MPS15X:
307 case S2MPS14X:
308 case S2MPS13X:
309 /* No exceptions needed */
310 break;
311 default:
312 return -EINVAL;
313 }
314
315 ret = regmap_update_bits(info->regmap, info->regs->udr_update,
316 udr_mask, info->regs->write_alarm_udr_mask);
317 if (ret < 0) {
318 dev_err(info->dev, "%s: fail to write update reg(%d)\n",
319 __func__, ret);
320 return ret;
321 }
322
323 ret = s5m8767_wait_for_udr_update(info);
324
325 /* On S2MPS13 the AUDR is not auto-cleared */
326 if (info->device_type == S2MPS13X)
327 regmap_clear_bits(info->regmap, info->regs->udr_update,
328 S2MPS13_RTC_AUDR_MASK);
329
330 return ret;
331 }
332
s5m_rtc_read_time(struct device * dev,struct rtc_time * tm)333 static int s5m_rtc_read_time(struct device *dev, struct rtc_time *tm)
334 {
335 struct s5m_rtc_info *info = dev_get_drvdata(dev);
336 u8 data[RTC_MAX_NUM_TIME_REGS];
337 int ret;
338
339 if (info->regs->read_time_udr_mask) {
340 ret = regmap_set_bits(info->regmap, info->regs->udr_update,
341 info->regs->read_time_udr_mask);
342 if (ret) {
343 dev_err(dev,
344 "Failed to prepare registers for time reading: %d\n",
345 ret);
346 return ret;
347 }
348 }
349 ret = regmap_bulk_read(info->regmap, info->regs->time, data,
350 info->regs->regs_count);
351 if (ret < 0)
352 return ret;
353
354 switch (info->device_type) {
355 case S5M8767X:
356 case S2MPG10:
357 case S2MPS15X:
358 case S2MPS14X:
359 case S2MPS13X:
360 s5m8767_data_to_tm(data, tm, info->rtc_24hr_mode);
361 break;
362
363 default:
364 return -EINVAL;
365 }
366
367 dev_dbg(dev, "%s: %ptR(%d)\n", __func__, tm, tm->tm_wday);
368
369 return 0;
370 }
371
s5m_rtc_set_time(struct device * dev,struct rtc_time * tm)372 static int s5m_rtc_set_time(struct device *dev, struct rtc_time *tm)
373 {
374 struct s5m_rtc_info *info = dev_get_drvdata(dev);
375 u8 data[RTC_MAX_NUM_TIME_REGS];
376 int ret = 0;
377
378 switch (info->device_type) {
379 case S5M8767X:
380 case S2MPG10:
381 case S2MPS15X:
382 case S2MPS14X:
383 case S2MPS13X:
384 ret = s5m8767_tm_to_data(tm, data);
385 break;
386 default:
387 return -EINVAL;
388 }
389
390 if (ret < 0)
391 return ret;
392
393 dev_dbg(dev, "%s: %ptR(%d)\n", __func__, tm, tm->tm_wday);
394
395 ret = regmap_raw_write(info->regmap, info->regs->time, data,
396 info->regs->regs_count);
397 if (ret < 0)
398 return ret;
399
400 ret = s5m8767_rtc_set_time_reg(info);
401
402 return ret;
403 }
404
s5m_rtc_read_alarm(struct device * dev,struct rtc_wkalrm * alrm)405 static int s5m_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
406 {
407 struct s5m_rtc_info *info = dev_get_drvdata(dev);
408 u8 data[RTC_MAX_NUM_TIME_REGS];
409 int ret, i;
410
411 ret = regmap_bulk_read(info->regmap, info->regs->alarm0, data,
412 info->regs->regs_count);
413 if (ret < 0)
414 return ret;
415
416 switch (info->device_type) {
417 case S5M8767X:
418 case S2MPG10:
419 case S2MPS15X:
420 case S2MPS14X:
421 case S2MPS13X:
422 s5m8767_data_to_tm(data, &alrm->time, info->rtc_24hr_mode);
423 alrm->enabled = 0;
424 for (i = 0; i < info->regs->regs_count; i++) {
425 if (data[i] & ALARM_ENABLE_MASK) {
426 alrm->enabled = 1;
427 break;
428 }
429 }
430 break;
431
432 default:
433 return -EINVAL;
434 }
435
436 dev_dbg(dev, "%s: %ptR(%d)\n", __func__, &alrm->time, alrm->time.tm_wday);
437
438 return s5m_check_pending_alarm_interrupt(info, alrm);
439 }
440
s5m_rtc_stop_alarm(struct s5m_rtc_info * info)441 static int s5m_rtc_stop_alarm(struct s5m_rtc_info *info)
442 {
443 u8 data[RTC_MAX_NUM_TIME_REGS];
444 int ret, i;
445 struct rtc_time tm;
446
447 ret = regmap_bulk_read(info->regmap, info->regs->alarm0, data,
448 info->regs->regs_count);
449 if (ret < 0)
450 return ret;
451
452 s5m8767_data_to_tm(data, &tm, info->rtc_24hr_mode);
453 dev_dbg(info->dev, "%s: %ptR(%d)\n", __func__, &tm, tm.tm_wday);
454
455 switch (info->device_type) {
456 case S5M8767X:
457 case S2MPG10:
458 case S2MPS15X:
459 case S2MPS14X:
460 case S2MPS13X:
461 for (i = 0; i < info->regs->regs_count; i++)
462 data[i] &= ~ALARM_ENABLE_MASK;
463
464 ret = regmap_raw_write(info->regmap, info->regs->alarm0, data,
465 info->regs->regs_count);
466 if (ret < 0)
467 return ret;
468
469 ret = s5m8767_rtc_set_alarm_reg(info);
470
471 break;
472
473 default:
474 return -EINVAL;
475 }
476
477 return ret;
478 }
479
s5m_rtc_start_alarm(struct s5m_rtc_info * info)480 static int s5m_rtc_start_alarm(struct s5m_rtc_info *info)
481 {
482 int ret;
483 u8 data[RTC_MAX_NUM_TIME_REGS];
484 struct rtc_time tm;
485
486 ret = regmap_bulk_read(info->regmap, info->regs->alarm0, data,
487 info->regs->regs_count);
488 if (ret < 0)
489 return ret;
490
491 s5m8767_data_to_tm(data, &tm, info->rtc_24hr_mode);
492 dev_dbg(info->dev, "%s: %ptR(%d)\n", __func__, &tm, tm.tm_wday);
493
494 switch (info->device_type) {
495 case S5M8767X:
496 case S2MPG10:
497 case S2MPS15X:
498 case S2MPS14X:
499 case S2MPS13X:
500 data[RTC_SEC] |= ALARM_ENABLE_MASK;
501 data[RTC_MIN] |= ALARM_ENABLE_MASK;
502 data[RTC_HOUR] |= ALARM_ENABLE_MASK;
503 data[RTC_WEEKDAY] &= ~ALARM_ENABLE_MASK;
504 if (data[RTC_DATE] & 0x1f)
505 data[RTC_DATE] |= ALARM_ENABLE_MASK;
506 if (data[RTC_MONTH] & 0xf)
507 data[RTC_MONTH] |= ALARM_ENABLE_MASK;
508 if (data[RTC_YEAR1] & 0x7f)
509 data[RTC_YEAR1] |= ALARM_ENABLE_MASK;
510
511 ret = regmap_raw_write(info->regmap, info->regs->alarm0, data,
512 info->regs->regs_count);
513 if (ret < 0)
514 return ret;
515 ret = s5m8767_rtc_set_alarm_reg(info);
516
517 break;
518
519 default:
520 return -EINVAL;
521 }
522
523 return ret;
524 }
525
s5m_rtc_set_alarm(struct device * dev,struct rtc_wkalrm * alrm)526 static int s5m_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
527 {
528 struct s5m_rtc_info *info = dev_get_drvdata(dev);
529 u8 data[RTC_MAX_NUM_TIME_REGS];
530 int ret;
531
532 switch (info->device_type) {
533 case S5M8767X:
534 case S2MPG10:
535 case S2MPS15X:
536 case S2MPS14X:
537 case S2MPS13X:
538 s5m8767_tm_to_data(&alrm->time, data);
539 break;
540
541 default:
542 return -EINVAL;
543 }
544
545 dev_dbg(dev, "%s: %ptR(%d)\n", __func__, &alrm->time, alrm->time.tm_wday);
546
547 ret = s5m_rtc_stop_alarm(info);
548 if (ret < 0)
549 return ret;
550
551 ret = regmap_raw_write(info->regmap, info->regs->alarm0, data,
552 info->regs->regs_count);
553 if (ret < 0)
554 return ret;
555
556 ret = s5m8767_rtc_set_alarm_reg(info);
557 if (ret < 0)
558 return ret;
559
560 if (alrm->enabled)
561 ret = s5m_rtc_start_alarm(info);
562
563 return ret;
564 }
565
s5m_rtc_alarm_irq_enable(struct device * dev,unsigned int enabled)566 static int s5m_rtc_alarm_irq_enable(struct device *dev,
567 unsigned int enabled)
568 {
569 struct s5m_rtc_info *info = dev_get_drvdata(dev);
570
571 if (enabled)
572 return s5m_rtc_start_alarm(info);
573 else
574 return s5m_rtc_stop_alarm(info);
575 }
576
s5m_rtc_alarm_irq(int irq,void * data)577 static irqreturn_t s5m_rtc_alarm_irq(int irq, void *data)
578 {
579 struct s5m_rtc_info *info = data;
580
581 rtc_update_irq(info->rtc_dev, 1, RTC_IRQF | RTC_AF);
582
583 return IRQ_HANDLED;
584 }
585
586 static const struct rtc_class_ops s5m_rtc_ops = {
587 .read_time = s5m_rtc_read_time,
588 .set_time = s5m_rtc_set_time,
589 .read_alarm = s5m_rtc_read_alarm,
590 .set_alarm = s5m_rtc_set_alarm,
591 .alarm_irq_enable = s5m_rtc_alarm_irq_enable,
592 };
593
s5m8767_rtc_init_reg(struct s5m_rtc_info * info)594 static int s5m8767_rtc_init_reg(struct s5m_rtc_info *info)
595 {
596 u8 data[2];
597 int ret;
598
599 switch (info->device_type) {
600 case S5M8767X:
601 /* UDR update time. Default of 7.32 ms is too long. */
602 ret = regmap_update_bits(info->regmap, S5M_RTC_UDR_CON,
603 S5M_RTC_UDR_T_MASK, S5M_RTC_UDR_T_450_US);
604 if (ret < 0)
605 dev_err(info->dev, "%s: fail to change UDR time: %d\n",
606 __func__, ret);
607
608 /* Set RTC control register : Binary mode, 24hour mode */
609 data[0] = (1 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT);
610 data[1] = (0 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT);
611
612 ret = regmap_raw_write(info->regmap, S5M_ALARM0_CONF, data, 2);
613 break;
614
615 case S2MPG10:
616 case S2MPS15X:
617 case S2MPS14X:
618 case S2MPS13X:
619 data[0] = (0 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT);
620 ret = regmap_write(info->regmap, info->regs->ctrl, data[0]);
621 if (ret < 0)
622 break;
623
624 /*
625 * Should set WUDR & (RUDR or AUDR) bits to high after writing
626 * RTC_CTRL register like writing Alarm registers. We can't find
627 * the description from datasheet but vendor code does that
628 * really.
629 */
630 ret = s5m8767_rtc_set_alarm_reg(info);
631 break;
632
633 default:
634 return -EINVAL;
635 }
636
637 info->rtc_24hr_mode = 1;
638 if (ret < 0)
639 return dev_err_probe(info->dev, ret,
640 "%s: fail to write controlm reg\n",
641 __func__);
642
643 return ret;
644 }
645
s5m_rtc_restart_s2mpg10(struct sys_off_data * data)646 static int s5m_rtc_restart_s2mpg10(struct sys_off_data *data)
647 {
648 struct s5m_rtc_info *info = data->cb_data;
649 int ret;
650
651 if (data->mode != REBOOT_COLD && data->mode != REBOOT_HARD)
652 return NOTIFY_DONE;
653
654 /*
655 * Arm watchdog with maximum timeout (2 seconds), and perform full reset
656 * on expiry.
657 */
658 ret = regmap_set_bits(info->regmap, S2MPG10_RTC_WTSR,
659 (S2MPG10_WTSR_COLDTIMER | S2MPG10_WTSR_COLDRST
660 | S2MPG10_WTSR_WTSRT | S2MPG10_WTSR_WTSR_EN));
661
662 return ret ? NOTIFY_BAD : NOTIFY_DONE;
663 }
664
s5m_rtc_probe(struct platform_device * pdev)665 static int s5m_rtc_probe(struct platform_device *pdev)
666 {
667 struct sec_pmic_dev *s5m87xx = dev_get_drvdata(pdev->dev.parent);
668 enum sec_device_type device_type =
669 platform_get_device_id(pdev)->driver_data;
670 struct s5m_rtc_info *info;
671 int ret, alarm_irq;
672
673 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
674 if (!info)
675 return -ENOMEM;
676
677 info->regmap = dev_get_regmap(pdev->dev.parent, "rtc");
678 if (!info->regmap) {
679 const struct regmap_config *regmap_cfg;
680 struct i2c_client *i2c;
681
682 switch (device_type) {
683 case S2MPS15X:
684 regmap_cfg = &s2mps14_rtc_regmap_config;
685 info->regs = &s2mps15_rtc_regs;
686 alarm_irq = S2MPS14_IRQ_RTCA0;
687 break;
688 case S2MPS14X:
689 regmap_cfg = &s2mps14_rtc_regmap_config;
690 info->regs = &s2mps14_rtc_regs;
691 alarm_irq = S2MPS14_IRQ_RTCA0;
692 break;
693 case S2MPS13X:
694 regmap_cfg = &s2mps14_rtc_regmap_config;
695 info->regs = &s2mps13_rtc_regs;
696 alarm_irq = S2MPS14_IRQ_RTCA0;
697 break;
698 case S5M8767X:
699 regmap_cfg = &s5m_rtc_regmap_config;
700 info->regs = &s5m_rtc_regs;
701 alarm_irq = S5M8767_IRQ_RTCA1;
702 break;
703 default:
704 return dev_err_probe(&pdev->dev, -ENODEV,
705 "Unsupported device type %d\n",
706 device_type);
707 }
708
709 i2c = devm_i2c_new_dummy_device(&pdev->dev,
710 s5m87xx->i2c->adapter,
711 RTC_I2C_ADDR);
712 if (IS_ERR(i2c))
713 return dev_err_probe(&pdev->dev, PTR_ERR(i2c),
714 "Failed to allocate I2C\n");
715
716 info->regmap = devm_regmap_init_i2c(i2c, regmap_cfg);
717 if (IS_ERR(info->regmap))
718 return dev_err_probe(&pdev->dev, PTR_ERR(info->regmap),
719 "Failed to allocate regmap\n");
720 } else if (device_type == S2MPG10) {
721 info->regs = &s2mpg10_rtc_regs;
722 alarm_irq = S2MPG10_IRQ_RTCA0;
723 } else {
724 return dev_err_probe(&pdev->dev, -ENODEV,
725 "Unsupported device type %d\n",
726 device_type);
727 }
728
729 info->dev = &pdev->dev;
730 info->s5m87xx = s5m87xx;
731 info->device_type = device_type;
732
733 if (s5m87xx->irq_data) {
734 info->irq = regmap_irq_get_virq(s5m87xx->irq_data, alarm_irq);
735 if (info->irq <= 0)
736 return dev_err_probe(&pdev->dev, -EINVAL,
737 "Failed to get virtual IRQ %d\n",
738 alarm_irq);
739 }
740
741 platform_set_drvdata(pdev, info);
742
743 ret = s5m8767_rtc_init_reg(info);
744 if (ret)
745 return ret;
746
747 info->rtc_dev = devm_rtc_allocate_device(&pdev->dev);
748 if (IS_ERR(info->rtc_dev))
749 return PTR_ERR(info->rtc_dev);
750
751 info->rtc_dev->ops = &s5m_rtc_ops;
752
753 info->rtc_dev->range_min = RTC_TIMESTAMP_BEGIN_2000;
754 info->rtc_dev->range_max = RTC_TIMESTAMP_END_2099;
755
756 if (!info->irq) {
757 clear_bit(RTC_FEATURE_ALARM, info->rtc_dev->features);
758 } else {
759 ret = devm_request_threaded_irq(&pdev->dev, info->irq, NULL,
760 s5m_rtc_alarm_irq, 0, "rtc-alarm0",
761 info);
762 if (ret < 0)
763 return dev_err_probe(&pdev->dev, ret,
764 "Failed to request alarm IRQ %d\n",
765 info->irq);
766
767 ret = devm_device_init_wakeup(&pdev->dev);
768 if (ret < 0)
769 return dev_err_probe(&pdev->dev, ret,
770 "Failed to init wakeup\n");
771 }
772
773 if (of_device_is_system_power_controller(pdev->dev.parent->of_node) &&
774 info->device_type == S2MPG10) {
775 ret = devm_register_sys_off_handler(&pdev->dev,
776 SYS_OFF_MODE_RESTART,
777 SYS_OFF_PRIO_HIGH + 1,
778 s5m_rtc_restart_s2mpg10,
779 info);
780 if (ret)
781 return dev_err_probe(&pdev->dev, ret,
782 "Failed to register restart handler\n");
783 }
784
785 return devm_rtc_register_device(info->rtc_dev);
786 }
787
788 #ifdef CONFIG_PM_SLEEP
s5m_rtc_resume(struct device * dev)789 static int s5m_rtc_resume(struct device *dev)
790 {
791 struct s5m_rtc_info *info = dev_get_drvdata(dev);
792 int ret = 0;
793
794 if (info->irq && device_may_wakeup(dev))
795 ret = disable_irq_wake(info->irq);
796
797 return ret;
798 }
799
s5m_rtc_suspend(struct device * dev)800 static int s5m_rtc_suspend(struct device *dev)
801 {
802 struct s5m_rtc_info *info = dev_get_drvdata(dev);
803 int ret = 0;
804
805 if (info->irq && device_may_wakeup(dev))
806 ret = enable_irq_wake(info->irq);
807
808 return ret;
809 }
810 #endif /* CONFIG_PM_SLEEP */
811
812 static SIMPLE_DEV_PM_OPS(s5m_rtc_pm_ops, s5m_rtc_suspend, s5m_rtc_resume);
813
814 static const struct platform_device_id s5m_rtc_id[] = {
815 { "s5m-rtc", S5M8767X },
816 { "s2mpg10-rtc", S2MPG10 },
817 { "s2mps13-rtc", S2MPS13X },
818 { "s2mps14-rtc", S2MPS14X },
819 { "s2mps15-rtc", S2MPS15X },
820 { },
821 };
822 MODULE_DEVICE_TABLE(platform, s5m_rtc_id);
823
824 static struct platform_driver s5m_rtc_driver = {
825 .driver = {
826 .name = "s5m-rtc",
827 .pm = &s5m_rtc_pm_ops,
828 },
829 .probe = s5m_rtc_probe,
830 .id_table = s5m_rtc_id,
831 };
832
833 module_platform_driver(s5m_rtc_driver);
834
835 /* Module information */
836 MODULE_AUTHOR("Sangbeom Kim <sbkim73@samsung.com>");
837 MODULE_DESCRIPTION("Samsung S5M/S2MPS14 RTC driver");
838 MODULE_LICENSE("GPL");
839