1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT) 2 /* 3 * Amlogic S4 Peripherals Clock Controller Driver 4 * 5 * Copyright (c) 2022-2023 Amlogic, inc. All rights reserved 6 * Author: Yu Tu <yu.tu@amlogic.com> 7 */ 8 9 #include <linux/clk-provider.h> 10 #include <linux/of_device.h> 11 #include <linux/platform_device.h> 12 13 #include "clk-regmap.h" 14 #include "vid-pll-div.h" 15 #include "clk-dualdiv.h" 16 #include "meson-clkc-utils.h" 17 #include <dt-bindings/clock/amlogic,s4-peripherals-clkc.h> 18 19 #define CLKCTRL_RTC_BY_OSCIN_CTRL0 0x008 20 #define CLKCTRL_RTC_BY_OSCIN_CTRL1 0x00c 21 #define CLKCTRL_RTC_CTRL 0x010 22 #define CLKCTRL_SYS_CLK_CTRL0 0x040 23 #define CLKCTRL_SYS_CLK_EN0_REG0 0x044 24 #define CLKCTRL_SYS_CLK_EN0_REG1 0x048 25 #define CLKCTRL_SYS_CLK_EN0_REG2 0x04c 26 #define CLKCTRL_SYS_CLK_EN0_REG3 0x050 27 #define CLKCTRL_CECA_CTRL0 0x088 28 #define CLKCTRL_CECA_CTRL1 0x08c 29 #define CLKCTRL_CECB_CTRL0 0x090 30 #define CLKCTRL_CECB_CTRL1 0x094 31 #define CLKCTRL_SC_CLK_CTRL 0x098 32 #define CLKCTRL_CLK12_24_CTRL 0x0a8 33 #define CLKCTRL_VID_CLK_CTRL 0x0c0 34 #define CLKCTRL_VID_CLK_CTRL2 0x0c4 35 #define CLKCTRL_VID_CLK_DIV 0x0c8 36 #define CLKCTRL_VIID_CLK_DIV 0x0cc 37 #define CLKCTRL_VIID_CLK_CTRL 0x0d0 38 #define CLKCTRL_HDMI_CLK_CTRL 0x0e0 39 #define CLKCTRL_VID_PLL_CLK_DIV 0x0e4 40 #define CLKCTRL_VPU_CLK_CTRL 0x0e8 41 #define CLKCTRL_VPU_CLKB_CTRL 0x0ec 42 #define CLKCTRL_VPU_CLKC_CTRL 0x0f0 43 #define CLKCTRL_VID_LOCK_CLK_CTRL 0x0f4 44 #define CLKCTRL_VDIN_MEAS_CLK_CTRL 0x0f8 45 #define CLKCTRL_VAPBCLK_CTRL 0x0fc 46 #define CLKCTRL_HDCP22_CTRL 0x100 47 #define CLKCTRL_VDEC_CLK_CTRL 0x140 48 #define CLKCTRL_VDEC2_CLK_CTRL 0x144 49 #define CLKCTRL_VDEC3_CLK_CTRL 0x148 50 #define CLKCTRL_VDEC4_CLK_CTRL 0x14c 51 #define CLKCTRL_TS_CLK_CTRL 0x158 52 #define CLKCTRL_MALI_CLK_CTRL 0x15c 53 #define CLKCTRL_NAND_CLK_CTRL 0x168 54 #define CLKCTRL_SD_EMMC_CLK_CTRL 0x16c 55 #define CLKCTRL_SPICC_CLK_CTRL 0x174 56 #define CLKCTRL_GEN_CLK_CTRL 0x178 57 #define CLKCTRL_SAR_CLK_CTRL 0x17c 58 #define CLKCTRL_PWM_CLK_AB_CTRL 0x180 59 #define CLKCTRL_PWM_CLK_CD_CTRL 0x184 60 #define CLKCTRL_PWM_CLK_EF_CTRL 0x188 61 #define CLKCTRL_PWM_CLK_GH_CTRL 0x18c 62 #define CLKCTRL_PWM_CLK_IJ_CTRL 0x190 63 #define CLKCTRL_DEMOD_CLK_CTRL 0x200 64 65 #define S4_COMP_SEL(_name, _reg, _shift, _mask, _pdata) \ 66 MESON_COMP_SEL(s4_, _name, _reg, _shift, _mask, _pdata, NULL, 0, 0) 67 68 #define S4_COMP_DIV(_name, _reg, _shift, _width) \ 69 MESON_COMP_DIV(s4_, _name, _reg, _shift, _width, 0, CLK_SET_RATE_PARENT) 70 71 #define S4_COMP_GATE(_name, _reg, _bit) \ 72 MESON_COMP_GATE(s4_, _name, _reg, _bit, CLK_SET_RATE_PARENT) 73 74 static struct clk_regmap s4_rtc_32k_by_oscin_clkin = { 75 .data = &(struct clk_regmap_gate_data){ 76 .offset = CLKCTRL_RTC_BY_OSCIN_CTRL0, 77 .bit_idx = 31, 78 }, 79 .hw.init = &(struct clk_init_data) { 80 .name = "rtc_32k_by_oscin_clkin", 81 .ops = &clk_regmap_gate_ops, 82 .parent_data = (const struct clk_parent_data []) { 83 { .fw_name = "xtal", } 84 }, 85 .num_parents = 1, 86 }, 87 }; 88 89 static const struct meson_clk_dualdiv_param s4_32k_div_table[] = { 90 { 91 .dual = 1, 92 .n1 = 733, 93 .m1 = 8, 94 .n2 = 732, 95 .m2 = 11, 96 }, 97 {} 98 }; 99 100 static struct clk_regmap s4_rtc_32k_by_oscin_div = { 101 .data = &(struct meson_clk_dualdiv_data){ 102 .n1 = { 103 .reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL0, 104 .shift = 0, 105 .width = 12, 106 }, 107 .n2 = { 108 .reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL0, 109 .shift = 12, 110 .width = 12, 111 }, 112 .m1 = { 113 .reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL1, 114 .shift = 0, 115 .width = 12, 116 }, 117 .m2 = { 118 .reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL1, 119 .shift = 12, 120 .width = 12, 121 }, 122 .dual = { 123 .reg_off = CLKCTRL_RTC_BY_OSCIN_CTRL0, 124 .shift = 28, 125 .width = 1, 126 }, 127 .table = s4_32k_div_table, 128 }, 129 .hw.init = &(struct clk_init_data){ 130 .name = "rtc_32k_by_oscin_div", 131 .ops = &meson_clk_dualdiv_ops, 132 .parent_hws = (const struct clk_hw *[]) { 133 &s4_rtc_32k_by_oscin_clkin.hw 134 }, 135 .num_parents = 1, 136 }, 137 }; 138 139 static struct clk_regmap s4_rtc_32k_by_oscin_sel = { 140 .data = &(struct clk_regmap_mux_data) { 141 .offset = CLKCTRL_RTC_BY_OSCIN_CTRL1, 142 .mask = 0x1, 143 .shift = 24, 144 .flags = CLK_MUX_ROUND_CLOSEST, 145 }, 146 .hw.init = &(struct clk_init_data){ 147 .name = "rtc_32k_by_oscin_sel", 148 .ops = &clk_regmap_mux_ops, 149 .parent_hws = (const struct clk_hw *[]) { 150 &s4_rtc_32k_by_oscin_div.hw, 151 &s4_rtc_32k_by_oscin_clkin.hw, 152 }, 153 .num_parents = 2, 154 .flags = CLK_SET_RATE_PARENT, 155 }, 156 }; 157 158 static struct clk_regmap s4_rtc_32k_by_oscin = { 159 .data = &(struct clk_regmap_gate_data){ 160 .offset = CLKCTRL_RTC_BY_OSCIN_CTRL0, 161 .bit_idx = 30, 162 }, 163 .hw.init = &(struct clk_init_data) { 164 .name = "rtc_32k_by_oscin", 165 .ops = &clk_regmap_gate_ops, 166 .parent_hws = (const struct clk_hw *[]) { 167 &s4_rtc_32k_by_oscin_sel.hw 168 }, 169 .num_parents = 1, 170 .flags = CLK_SET_RATE_PARENT, 171 }, 172 }; 173 174 static struct clk_regmap s4_rtc_clk = { 175 .data = &(struct clk_regmap_mux_data) { 176 .offset = CLKCTRL_RTC_CTRL, 177 .mask = 0x3, 178 .shift = 0, 179 .flags = CLK_MUX_ROUND_CLOSEST, 180 }, 181 .hw.init = &(struct clk_init_data){ 182 .name = "rtc_clk_sel", 183 .ops = &clk_regmap_mux_ops, 184 .parent_hws = (const struct clk_hw *[]) { 185 &s4_rtc_32k_by_oscin.hw, 186 &s4_rtc_32k_by_oscin_div.hw, 187 }, 188 .num_parents = 2, 189 .flags = CLK_SET_RATE_PARENT, 190 }, 191 }; 192 193 /* The index 5 is AXI_CLK, which is dedicated to AXI. So skip it. */ 194 static u32 s4_sysclk_parents_val_table[] = { 0, 1, 2, 3, 4, 6, 7 }; 195 static const struct clk_parent_data s4_sysclk_parents[] = { 196 { .fw_name = "xtal" }, 197 { .fw_name = "fclk_div2" }, 198 { .fw_name = "fclk_div3" }, 199 { .fw_name = "fclk_div4" }, 200 { .fw_name = "fclk_div5" }, 201 { .fw_name = "fclk_div7" }, 202 { .hw = &s4_rtc_clk.hw } 203 }; 204 205 /* 206 * This clock is initialized by ROMcode. 207 * The chip was changed SYS CLK for security reasons. SYS CLK registers are not writable 208 * in the kernel phase. Write of SYS related register will cause the system to crash. 209 * Meanwhile, these clock won't ever change at runtime. 210 * For the above reasons, we can only use ro_ops for SYS related clocks. 211 */ 212 static struct clk_regmap s4_sysclk_b_sel = { 213 .data = &(struct clk_regmap_mux_data){ 214 .offset = CLKCTRL_SYS_CLK_CTRL0, 215 .mask = 0x7, 216 .shift = 26, 217 .table = s4_sysclk_parents_val_table, 218 }, 219 .hw.init = &(struct clk_init_data){ 220 .name = "sysclk_b_sel", 221 .ops = &clk_regmap_mux_ro_ops, 222 .parent_data = s4_sysclk_parents, 223 .num_parents = ARRAY_SIZE(s4_sysclk_parents), 224 }, 225 }; 226 227 static struct clk_regmap s4_sysclk_b_div = { 228 .data = &(struct clk_regmap_div_data){ 229 .offset = CLKCTRL_SYS_CLK_CTRL0, 230 .shift = 16, 231 .width = 10, 232 }, 233 .hw.init = &(struct clk_init_data){ 234 .name = "sysclk_b_div", 235 .ops = &clk_regmap_divider_ro_ops, 236 .parent_hws = (const struct clk_hw *[]) { 237 &s4_sysclk_b_sel.hw 238 }, 239 .num_parents = 1, 240 }, 241 }; 242 243 static struct clk_regmap s4_sysclk_b = { 244 .data = &(struct clk_regmap_gate_data){ 245 .offset = CLKCTRL_SYS_CLK_CTRL0, 246 .bit_idx = 29, 247 }, 248 .hw.init = &(struct clk_init_data) { 249 .name = "sysclk_b", 250 .ops = &clk_regmap_gate_ro_ops, 251 .parent_hws = (const struct clk_hw *[]) { 252 &s4_sysclk_b_div.hw 253 }, 254 .num_parents = 1, 255 }, 256 }; 257 258 static struct clk_regmap s4_sysclk_a_sel = { 259 .data = &(struct clk_regmap_mux_data){ 260 .offset = CLKCTRL_SYS_CLK_CTRL0, 261 .mask = 0x7, 262 .shift = 10, 263 .table = s4_sysclk_parents_val_table, 264 }, 265 .hw.init = &(struct clk_init_data){ 266 .name = "sysclk_a_sel", 267 .ops = &clk_regmap_mux_ro_ops, 268 .parent_data = s4_sysclk_parents, 269 .num_parents = ARRAY_SIZE(s4_sysclk_parents), 270 }, 271 }; 272 273 static struct clk_regmap s4_sysclk_a_div = { 274 .data = &(struct clk_regmap_div_data){ 275 .offset = CLKCTRL_SYS_CLK_CTRL0, 276 .shift = 0, 277 .width = 10, 278 }, 279 .hw.init = &(struct clk_init_data){ 280 .name = "sysclk_a_div", 281 .ops = &clk_regmap_divider_ro_ops, 282 .parent_hws = (const struct clk_hw *[]) { 283 &s4_sysclk_a_sel.hw 284 }, 285 .num_parents = 1, 286 }, 287 }; 288 289 static struct clk_regmap s4_sysclk_a = { 290 .data = &(struct clk_regmap_gate_data){ 291 .offset = CLKCTRL_SYS_CLK_CTRL0, 292 .bit_idx = 13, 293 }, 294 .hw.init = &(struct clk_init_data) { 295 .name = "sysclk_a", 296 .ops = &clk_regmap_gate_ro_ops, 297 .parent_hws = (const struct clk_hw *[]) { 298 &s4_sysclk_a_div.hw 299 }, 300 .num_parents = 1, 301 }, 302 }; 303 304 static struct clk_regmap s4_sys_clk = { 305 .data = &(struct clk_regmap_mux_data){ 306 .offset = CLKCTRL_SYS_CLK_CTRL0, 307 .mask = 0x1, 308 .shift = 31, 309 }, 310 .hw.init = &(struct clk_init_data){ 311 .name = "sys_clk", 312 .ops = &clk_regmap_mux_ro_ops, 313 .parent_hws = (const struct clk_hw *[]) { 314 &s4_sysclk_a.hw, 315 &s4_sysclk_b.hw 316 }, 317 .num_parents = 2, 318 }, 319 }; 320 321 static struct clk_regmap s4_ceca_32k_clkin = { 322 .data = &(struct clk_regmap_gate_data){ 323 .offset = CLKCTRL_CECA_CTRL0, 324 .bit_idx = 31, 325 }, 326 .hw.init = &(struct clk_init_data) { 327 .name = "ceca_32k_clkin", 328 .ops = &clk_regmap_gate_ops, 329 .parent_data = (const struct clk_parent_data []) { 330 { .fw_name = "xtal", } 331 }, 332 .num_parents = 1, 333 }, 334 }; 335 336 static struct clk_regmap s4_ceca_32k_div = { 337 .data = &(struct meson_clk_dualdiv_data){ 338 .n1 = { 339 .reg_off = CLKCTRL_CECA_CTRL0, 340 .shift = 0, 341 .width = 12, 342 }, 343 .n2 = { 344 .reg_off = CLKCTRL_CECA_CTRL0, 345 .shift = 12, 346 .width = 12, 347 }, 348 .m1 = { 349 .reg_off = CLKCTRL_CECA_CTRL1, 350 .shift = 0, 351 .width = 12, 352 }, 353 .m2 = { 354 .reg_off = CLKCTRL_CECA_CTRL1, 355 .shift = 12, 356 .width = 12, 357 }, 358 .dual = { 359 .reg_off = CLKCTRL_CECA_CTRL0, 360 .shift = 28, 361 .width = 1, 362 }, 363 .table = s4_32k_div_table, 364 }, 365 .hw.init = &(struct clk_init_data){ 366 .name = "ceca_32k_div", 367 .ops = &meson_clk_dualdiv_ops, 368 .parent_hws = (const struct clk_hw *[]) { 369 &s4_ceca_32k_clkin.hw 370 }, 371 .num_parents = 1, 372 }, 373 }; 374 375 static struct clk_regmap s4_ceca_32k_sel_pre = { 376 .data = &(struct clk_regmap_mux_data) { 377 .offset = CLKCTRL_CECA_CTRL1, 378 .mask = 0x1, 379 .shift = 24, 380 .flags = CLK_MUX_ROUND_CLOSEST, 381 }, 382 .hw.init = &(struct clk_init_data){ 383 .name = "ceca_32k_sel_pre", 384 .ops = &clk_regmap_mux_ops, 385 .parent_hws = (const struct clk_hw *[]) { 386 &s4_ceca_32k_div.hw, 387 &s4_ceca_32k_clkin.hw 388 }, 389 .num_parents = 2, 390 .flags = CLK_SET_RATE_PARENT, 391 }, 392 }; 393 394 static struct clk_regmap s4_ceca_32k_sel = { 395 .data = &(struct clk_regmap_mux_data) { 396 .offset = CLKCTRL_CECA_CTRL1, 397 .mask = 0x1, 398 .shift = 31, 399 .flags = CLK_MUX_ROUND_CLOSEST, 400 }, 401 .hw.init = &(struct clk_init_data){ 402 .name = "ceca_32k_sel", 403 .ops = &clk_regmap_mux_ops, 404 .parent_hws = (const struct clk_hw *[]) { 405 &s4_ceca_32k_sel_pre.hw, 406 &s4_rtc_clk.hw 407 }, 408 .num_parents = 2, 409 }, 410 }; 411 412 static struct clk_regmap s4_ceca_32k_clkout = { 413 .data = &(struct clk_regmap_gate_data){ 414 .offset = CLKCTRL_CECA_CTRL0, 415 .bit_idx = 30, 416 }, 417 .hw.init = &(struct clk_init_data){ 418 .name = "ceca_32k_clkout", 419 .ops = &clk_regmap_gate_ops, 420 .parent_hws = (const struct clk_hw *[]) { 421 &s4_ceca_32k_sel.hw 422 }, 423 .num_parents = 1, 424 .flags = CLK_SET_RATE_PARENT, 425 }, 426 }; 427 428 static struct clk_regmap s4_cecb_32k_clkin = { 429 .data = &(struct clk_regmap_gate_data){ 430 .offset = CLKCTRL_CECB_CTRL0, 431 .bit_idx = 31, 432 }, 433 .hw.init = &(struct clk_init_data) { 434 .name = "cecb_32k_clkin", 435 .ops = &clk_regmap_gate_ops, 436 .parent_data = (const struct clk_parent_data []) { 437 { .fw_name = "xtal", } 438 }, 439 .num_parents = 1, 440 }, 441 }; 442 443 static struct clk_regmap s4_cecb_32k_div = { 444 .data = &(struct meson_clk_dualdiv_data){ 445 .n1 = { 446 .reg_off = CLKCTRL_CECB_CTRL0, 447 .shift = 0, 448 .width = 12, 449 }, 450 .n2 = { 451 .reg_off = CLKCTRL_CECB_CTRL0, 452 .shift = 12, 453 .width = 12, 454 }, 455 .m1 = { 456 .reg_off = CLKCTRL_CECB_CTRL1, 457 .shift = 0, 458 .width = 12, 459 }, 460 .m2 = { 461 .reg_off = CLKCTRL_CECB_CTRL1, 462 .shift = 12, 463 .width = 12, 464 }, 465 .dual = { 466 .reg_off = CLKCTRL_CECB_CTRL0, 467 .shift = 28, 468 .width = 1, 469 }, 470 .table = s4_32k_div_table, 471 }, 472 .hw.init = &(struct clk_init_data){ 473 .name = "cecb_32k_div", 474 .ops = &meson_clk_dualdiv_ops, 475 .parent_hws = (const struct clk_hw *[]) { 476 &s4_cecb_32k_clkin.hw 477 }, 478 .num_parents = 1, 479 }, 480 }; 481 482 static struct clk_regmap s4_cecb_32k_sel_pre = { 483 .data = &(struct clk_regmap_mux_data) { 484 .offset = CLKCTRL_CECB_CTRL1, 485 .mask = 0x1, 486 .shift = 24, 487 .flags = CLK_MUX_ROUND_CLOSEST, 488 }, 489 .hw.init = &(struct clk_init_data){ 490 .name = "cecb_32k_sel_pre", 491 .ops = &clk_regmap_mux_ops, 492 .parent_hws = (const struct clk_hw *[]) { 493 &s4_cecb_32k_div.hw, 494 &s4_cecb_32k_clkin.hw 495 }, 496 .num_parents = 2, 497 .flags = CLK_SET_RATE_PARENT, 498 }, 499 }; 500 501 static struct clk_regmap s4_cecb_32k_sel = { 502 .data = &(struct clk_regmap_mux_data) { 503 .offset = CLKCTRL_CECB_CTRL1, 504 .mask = 0x1, 505 .shift = 31, 506 .flags = CLK_MUX_ROUND_CLOSEST, 507 }, 508 .hw.init = &(struct clk_init_data){ 509 .name = "cecb_32k_sel", 510 .ops = &clk_regmap_mux_ops, 511 .parent_hws = (const struct clk_hw *[]) { 512 &s4_cecb_32k_sel_pre.hw, 513 &s4_rtc_clk.hw 514 }, 515 .num_parents = 2, 516 }, 517 }; 518 519 static struct clk_regmap s4_cecb_32k_clkout = { 520 .data = &(struct clk_regmap_gate_data){ 521 .offset = CLKCTRL_CECB_CTRL0, 522 .bit_idx = 30, 523 }, 524 .hw.init = &(struct clk_init_data){ 525 .name = "cecb_32k_clkout", 526 .ops = &clk_regmap_gate_ops, 527 .parent_hws = (const struct clk_hw *[]) { 528 &s4_cecb_32k_sel.hw 529 }, 530 .num_parents = 1, 531 .flags = CLK_SET_RATE_PARENT, 532 }, 533 }; 534 535 static const struct clk_parent_data s4_sc_clk_parents[] = { 536 { .fw_name = "fclk_div4" }, 537 { .fw_name = "fclk_div3" }, 538 { .fw_name = "fclk_div5" }, 539 { .fw_name = "xtal", } 540 }; 541 542 static struct clk_regmap s4_sc_clk_sel = { 543 .data = &(struct clk_regmap_mux_data){ 544 .offset = CLKCTRL_SC_CLK_CTRL, 545 .mask = 0x3, 546 .shift = 9, 547 }, 548 .hw.init = &(struct clk_init_data) { 549 .name = "sc_clk_sel", 550 .ops = &clk_regmap_mux_ops, 551 .parent_data = s4_sc_clk_parents, 552 .num_parents = ARRAY_SIZE(s4_sc_clk_parents), 553 .flags = CLK_SET_RATE_PARENT, 554 }, 555 }; 556 557 static struct clk_regmap s4_sc_clk_div = { 558 .data = &(struct clk_regmap_div_data){ 559 .offset = CLKCTRL_SC_CLK_CTRL, 560 .shift = 0, 561 .width = 8, 562 }, 563 .hw.init = &(struct clk_init_data) { 564 .name = "sc_clk_div", 565 .ops = &clk_regmap_divider_ops, 566 .parent_hws = (const struct clk_hw *[]) { 567 &s4_sc_clk_sel.hw 568 }, 569 .num_parents = 1, 570 .flags = CLK_SET_RATE_PARENT, 571 }, 572 }; 573 574 static struct clk_regmap s4_sc_clk = { 575 .data = &(struct clk_regmap_gate_data){ 576 .offset = CLKCTRL_SC_CLK_CTRL, 577 .bit_idx = 8, 578 }, 579 .hw.init = &(struct clk_init_data){ 580 .name = "sc_clk", 581 .ops = &clk_regmap_gate_ops, 582 .parent_hws = (const struct clk_hw *[]) { 583 &s4_sc_clk_div.hw 584 }, 585 .num_parents = 1, 586 .flags = CLK_SET_RATE_PARENT, 587 }, 588 }; 589 590 static struct clk_regmap s4_12_24M = { 591 .data = &(struct clk_regmap_gate_data){ 592 .offset = CLKCTRL_CLK12_24_CTRL, 593 .bit_idx = 11, 594 }, 595 .hw.init = &(struct clk_init_data) { 596 .name = "12_24M", 597 .ops = &clk_regmap_gate_ops, 598 .parent_data = (const struct clk_parent_data []) { 599 { .fw_name = "xtal", } 600 }, 601 .num_parents = 1, 602 }, 603 }; 604 605 static struct clk_fixed_factor s4_12M_div = { 606 .mult = 1, 607 .div = 2, 608 .hw.init = &(struct clk_init_data){ 609 .name = "12M_div", 610 .ops = &clk_fixed_factor_ops, 611 .parent_hws = (const struct clk_hw *[]) { 612 &s4_12_24M.hw 613 }, 614 .num_parents = 1, 615 .flags = CLK_SET_RATE_PARENT, 616 }, 617 }; 618 619 static struct clk_regmap s4_12_24M_sel = { 620 .data = &(struct clk_regmap_mux_data){ 621 .offset = CLKCTRL_CLK12_24_CTRL, 622 .mask = 0x1, 623 .shift = 10, 624 }, 625 .hw.init = &(struct clk_init_data) { 626 .name = "12_24M_sel", 627 .ops = &clk_regmap_mux_ops, 628 .parent_hws = (const struct clk_hw *[]) { 629 &s4_12_24M.hw, 630 &s4_12M_div.hw, 631 }, 632 .num_parents = 2, 633 .flags = CLK_SET_RATE_PARENT, 634 }, 635 }; 636 637 /* Video Clocks */ 638 static struct clk_regmap s4_vid_pll_div = { 639 .data = &(struct meson_vid_pll_div_data){ 640 .val = { 641 .reg_off = CLKCTRL_VID_PLL_CLK_DIV, 642 .shift = 0, 643 .width = 15, 644 }, 645 .sel = { 646 .reg_off = CLKCTRL_VID_PLL_CLK_DIV, 647 .shift = 16, 648 .width = 2, 649 }, 650 }, 651 .hw.init = &(struct clk_init_data) { 652 .name = "vid_pll_div", 653 /* 654 * TODO meson_vid_pll_div_ro_ops to meson_vid_pll_div_ops 655 */ 656 .ops = &meson_vid_pll_div_ro_ops, 657 .parent_data = (const struct clk_parent_data []) { 658 { .fw_name = "hdmi_pll", } 659 }, 660 .num_parents = 1, 661 .flags = CLK_SET_RATE_PARENT, 662 }, 663 }; 664 665 static struct clk_regmap s4_vid_pll_sel = { 666 .data = &(struct clk_regmap_mux_data){ 667 .offset = CLKCTRL_VID_PLL_CLK_DIV, 668 .mask = 0x1, 669 .shift = 18, 670 }, 671 .hw.init = &(struct clk_init_data){ 672 .name = "vid_pll_sel", 673 .ops = &clk_regmap_mux_ops, 674 .parent_data = (const struct clk_parent_data []) { 675 { .hw = &s4_vid_pll_div.hw }, 676 { .fw_name = "hdmi_pll", } 677 }, 678 .num_parents = 2, 679 .flags = CLK_SET_RATE_PARENT, 680 }, 681 }; 682 683 static struct clk_regmap s4_vid_pll = { 684 .data = &(struct clk_regmap_gate_data){ 685 .offset = CLKCTRL_VID_PLL_CLK_DIV, 686 .bit_idx = 19, 687 }, 688 .hw.init = &(struct clk_init_data) { 689 .name = "vid_pll", 690 .ops = &clk_regmap_gate_ops, 691 .parent_hws = (const struct clk_hw *[]) { 692 &s4_vid_pll_sel.hw 693 }, 694 .num_parents = 1, 695 .flags = CLK_SET_RATE_PARENT, 696 }, 697 }; 698 699 static const struct clk_parent_data s4_vclk_parents[] = { 700 { .hw = &s4_vid_pll.hw }, 701 { .fw_name = "gp0_pll", }, 702 { .fw_name = "hifi_pll", }, 703 { .fw_name = "mpll1", }, 704 { .fw_name = "fclk_div3", }, 705 { .fw_name = "fclk_div4", }, 706 { .fw_name = "fclk_div5", }, 707 { .fw_name = "fclk_div7", }, 708 }; 709 710 static struct clk_regmap s4_vclk_sel = { 711 .data = &(struct clk_regmap_mux_data){ 712 .offset = CLKCTRL_VID_CLK_CTRL, 713 .mask = 0x7, 714 .shift = 16, 715 }, 716 .hw.init = &(struct clk_init_data){ 717 .name = "vclk_sel", 718 .ops = &clk_regmap_mux_ops, 719 .parent_data = s4_vclk_parents, 720 .num_parents = ARRAY_SIZE(s4_vclk_parents), 721 .flags = 0, 722 }, 723 }; 724 725 static struct clk_regmap s4_vclk2_sel = { 726 .data = &(struct clk_regmap_mux_data){ 727 .offset = CLKCTRL_VIID_CLK_CTRL, 728 .mask = 0x7, 729 .shift = 16, 730 }, 731 .hw.init = &(struct clk_init_data){ 732 .name = "vclk2_sel", 733 .ops = &clk_regmap_mux_ops, 734 .parent_data = s4_vclk_parents, 735 .num_parents = ARRAY_SIZE(s4_vclk_parents), 736 .flags = 0, 737 }, 738 }; 739 740 static struct clk_regmap s4_vclk_input = { 741 .data = &(struct clk_regmap_gate_data){ 742 .offset = CLKCTRL_VID_CLK_DIV, 743 .bit_idx = 16, 744 }, 745 .hw.init = &(struct clk_init_data) { 746 .name = "vclk_input", 747 .ops = &clk_regmap_gate_ops, 748 .parent_hws = (const struct clk_hw *[]) { &s4_vclk_sel.hw }, 749 .num_parents = 1, 750 .flags = CLK_SET_RATE_PARENT, 751 }, 752 }; 753 754 static struct clk_regmap s4_vclk2_input = { 755 .data = &(struct clk_regmap_gate_data){ 756 .offset = CLKCTRL_VIID_CLK_DIV, 757 .bit_idx = 16, 758 }, 759 .hw.init = &(struct clk_init_data) { 760 .name = "vclk2_input", 761 .ops = &clk_regmap_gate_ops, 762 .parent_hws = (const struct clk_hw *[]) { &s4_vclk2_sel.hw }, 763 .num_parents = 1, 764 .flags = CLK_SET_RATE_PARENT, 765 }, 766 }; 767 768 static struct clk_regmap s4_vclk_div = { 769 .data = &(struct clk_regmap_div_data){ 770 .offset = CLKCTRL_VID_CLK_DIV, 771 .shift = 0, 772 .width = 8, 773 }, 774 .hw.init = &(struct clk_init_data){ 775 .name = "vclk_div", 776 .ops = &clk_regmap_divider_ops, 777 .parent_hws = (const struct clk_hw *[]) { 778 &s4_vclk_input.hw 779 }, 780 .num_parents = 1, 781 .flags = CLK_SET_RATE_PARENT, 782 }, 783 }; 784 785 static struct clk_regmap s4_vclk2_div = { 786 .data = &(struct clk_regmap_div_data){ 787 .offset = CLKCTRL_VIID_CLK_DIV, 788 .shift = 0, 789 .width = 8, 790 }, 791 .hw.init = &(struct clk_init_data){ 792 .name = "vclk2_div", 793 .ops = &clk_regmap_divider_ops, 794 .parent_hws = (const struct clk_hw *[]) { 795 &s4_vclk2_input.hw 796 }, 797 .num_parents = 1, 798 .flags = CLK_SET_RATE_PARENT, 799 }, 800 }; 801 802 static struct clk_regmap s4_vclk = { 803 .data = &(struct clk_regmap_gate_data){ 804 .offset = CLKCTRL_VID_CLK_CTRL, 805 .bit_idx = 19, 806 }, 807 .hw.init = &(struct clk_init_data) { 808 .name = "vclk", 809 .ops = &clk_regmap_gate_ops, 810 .parent_hws = (const struct clk_hw *[]) { &s4_vclk_div.hw }, 811 .num_parents = 1, 812 .flags = CLK_SET_RATE_PARENT, 813 }, 814 }; 815 816 static struct clk_regmap s4_vclk2 = { 817 .data = &(struct clk_regmap_gate_data){ 818 .offset = CLKCTRL_VIID_CLK_CTRL, 819 .bit_idx = 19, 820 }, 821 .hw.init = &(struct clk_init_data) { 822 .name = "vclk2", 823 .ops = &clk_regmap_gate_ops, 824 .parent_hws = (const struct clk_hw *[]) { &s4_vclk2_div.hw }, 825 .num_parents = 1, 826 .flags = CLK_SET_RATE_PARENT, 827 }, 828 }; 829 830 static struct clk_regmap s4_vclk_div1 = { 831 .data = &(struct clk_regmap_gate_data){ 832 .offset = CLKCTRL_VID_CLK_CTRL, 833 .bit_idx = 0, 834 }, 835 .hw.init = &(struct clk_init_data) { 836 .name = "vclk_div1", 837 .ops = &clk_regmap_gate_ops, 838 .parent_hws = (const struct clk_hw *[]) { &s4_vclk.hw }, 839 .num_parents = 1, 840 .flags = CLK_SET_RATE_PARENT, 841 }, 842 }; 843 844 static struct clk_regmap s4_vclk_div2_en = { 845 .data = &(struct clk_regmap_gate_data){ 846 .offset = CLKCTRL_VID_CLK_CTRL, 847 .bit_idx = 1, 848 }, 849 .hw.init = &(struct clk_init_data) { 850 .name = "vclk_div2_en", 851 .ops = &clk_regmap_gate_ops, 852 .parent_hws = (const struct clk_hw *[]) { &s4_vclk.hw }, 853 .num_parents = 1, 854 .flags = CLK_SET_RATE_PARENT, 855 }, 856 }; 857 858 static struct clk_regmap s4_vclk_div4_en = { 859 .data = &(struct clk_regmap_gate_data){ 860 .offset = CLKCTRL_VID_CLK_CTRL, 861 .bit_idx = 2, 862 }, 863 .hw.init = &(struct clk_init_data) { 864 .name = "vclk_div4_en", 865 .ops = &clk_regmap_gate_ops, 866 .parent_hws = (const struct clk_hw *[]) { &s4_vclk.hw }, 867 .num_parents = 1, 868 .flags = CLK_SET_RATE_PARENT, 869 }, 870 }; 871 872 static struct clk_regmap s4_vclk_div6_en = { 873 .data = &(struct clk_regmap_gate_data){ 874 .offset = CLKCTRL_VID_CLK_CTRL, 875 .bit_idx = 3, 876 }, 877 .hw.init = &(struct clk_init_data) { 878 .name = "vclk_div6_en", 879 .ops = &clk_regmap_gate_ops, 880 .parent_hws = (const struct clk_hw *[]) { &s4_vclk.hw }, 881 .num_parents = 1, 882 .flags = CLK_SET_RATE_PARENT, 883 }, 884 }; 885 886 static struct clk_regmap s4_vclk_div12_en = { 887 .data = &(struct clk_regmap_gate_data){ 888 .offset = CLKCTRL_VID_CLK_CTRL, 889 .bit_idx = 4, 890 }, 891 .hw.init = &(struct clk_init_data) { 892 .name = "vclk_div12_en", 893 .ops = &clk_regmap_gate_ops, 894 .parent_hws = (const struct clk_hw *[]) { &s4_vclk.hw }, 895 .num_parents = 1, 896 .flags = CLK_SET_RATE_PARENT, 897 }, 898 }; 899 900 static struct clk_regmap s4_vclk2_div1 = { 901 .data = &(struct clk_regmap_gate_data){ 902 .offset = CLKCTRL_VIID_CLK_CTRL, 903 .bit_idx = 0, 904 }, 905 .hw.init = &(struct clk_init_data) { 906 .name = "vclk2_div1", 907 .ops = &clk_regmap_gate_ops, 908 .parent_hws = (const struct clk_hw *[]) { &s4_vclk2.hw }, 909 .num_parents = 1, 910 .flags = CLK_SET_RATE_PARENT, 911 }, 912 }; 913 914 static struct clk_regmap s4_vclk2_div2_en = { 915 .data = &(struct clk_regmap_gate_data){ 916 .offset = CLKCTRL_VIID_CLK_CTRL, 917 .bit_idx = 1, 918 }, 919 .hw.init = &(struct clk_init_data) { 920 .name = "vclk2_div2_en", 921 .ops = &clk_regmap_gate_ops, 922 .parent_hws = (const struct clk_hw *[]) { &s4_vclk2.hw }, 923 .num_parents = 1, 924 .flags = CLK_SET_RATE_PARENT, 925 }, 926 }; 927 928 static struct clk_regmap s4_vclk2_div4_en = { 929 .data = &(struct clk_regmap_gate_data){ 930 .offset = CLKCTRL_VIID_CLK_CTRL, 931 .bit_idx = 2, 932 }, 933 .hw.init = &(struct clk_init_data) { 934 .name = "vclk2_div4_en", 935 .ops = &clk_regmap_gate_ops, 936 .parent_hws = (const struct clk_hw *[]) { &s4_vclk2.hw }, 937 .num_parents = 1, 938 .flags = CLK_SET_RATE_PARENT, 939 }, 940 }; 941 942 static struct clk_regmap s4_vclk2_div6_en = { 943 .data = &(struct clk_regmap_gate_data){ 944 .offset = CLKCTRL_VIID_CLK_CTRL, 945 .bit_idx = 3, 946 }, 947 .hw.init = &(struct clk_init_data) { 948 .name = "vclk2_div6_en", 949 .ops = &clk_regmap_gate_ops, 950 .parent_hws = (const struct clk_hw *[]) { &s4_vclk2.hw }, 951 .num_parents = 1, 952 .flags = CLK_SET_RATE_PARENT, 953 }, 954 }; 955 956 static struct clk_regmap s4_vclk2_div12_en = { 957 .data = &(struct clk_regmap_gate_data){ 958 .offset = CLKCTRL_VIID_CLK_CTRL, 959 .bit_idx = 4, 960 }, 961 .hw.init = &(struct clk_init_data) { 962 .name = "vclk2_div12_en", 963 .ops = &clk_regmap_gate_ops, 964 .parent_hws = (const struct clk_hw *[]) { &s4_vclk2.hw }, 965 .num_parents = 1, 966 .flags = CLK_SET_RATE_PARENT, 967 }, 968 }; 969 970 static struct clk_fixed_factor s4_vclk_div2 = { 971 .mult = 1, 972 .div = 2, 973 .hw.init = &(struct clk_init_data){ 974 .name = "vclk_div2", 975 .ops = &clk_fixed_factor_ops, 976 .parent_hws = (const struct clk_hw *[]) { 977 &s4_vclk_div2_en.hw 978 }, 979 .num_parents = 1, 980 .flags = CLK_SET_RATE_PARENT, 981 }, 982 }; 983 984 static struct clk_fixed_factor s4_vclk_div4 = { 985 .mult = 1, 986 .div = 4, 987 .hw.init = &(struct clk_init_data){ 988 .name = "vclk_div4", 989 .ops = &clk_fixed_factor_ops, 990 .parent_hws = (const struct clk_hw *[]) { 991 &s4_vclk_div4_en.hw 992 }, 993 .num_parents = 1, 994 .flags = CLK_SET_RATE_PARENT, 995 }, 996 }; 997 998 static struct clk_fixed_factor s4_vclk_div6 = { 999 .mult = 1, 1000 .div = 6, 1001 .hw.init = &(struct clk_init_data){ 1002 .name = "vclk_div6", 1003 .ops = &clk_fixed_factor_ops, 1004 .parent_hws = (const struct clk_hw *[]) { 1005 &s4_vclk_div6_en.hw 1006 }, 1007 .num_parents = 1, 1008 .flags = CLK_SET_RATE_PARENT, 1009 }, 1010 }; 1011 1012 static struct clk_fixed_factor s4_vclk_div12 = { 1013 .mult = 1, 1014 .div = 12, 1015 .hw.init = &(struct clk_init_data){ 1016 .name = "vclk_div12", 1017 .ops = &clk_fixed_factor_ops, 1018 .parent_hws = (const struct clk_hw *[]) { 1019 &s4_vclk_div12_en.hw 1020 }, 1021 .num_parents = 1, 1022 .flags = CLK_SET_RATE_PARENT, 1023 }, 1024 }; 1025 1026 static struct clk_fixed_factor s4_vclk2_div2 = { 1027 .mult = 1, 1028 .div = 2, 1029 .hw.init = &(struct clk_init_data){ 1030 .name = "vclk2_div2", 1031 .ops = &clk_fixed_factor_ops, 1032 .parent_hws = (const struct clk_hw *[]) { 1033 &s4_vclk2_div2_en.hw 1034 }, 1035 .num_parents = 1, 1036 .flags = CLK_SET_RATE_PARENT, 1037 }, 1038 }; 1039 1040 static struct clk_fixed_factor s4_vclk2_div4 = { 1041 .mult = 1, 1042 .div = 4, 1043 .hw.init = &(struct clk_init_data){ 1044 .name = "vclk2_div4", 1045 .ops = &clk_fixed_factor_ops, 1046 .parent_hws = (const struct clk_hw *[]) { 1047 &s4_vclk2_div4_en.hw 1048 }, 1049 .num_parents = 1, 1050 .flags = CLK_SET_RATE_PARENT, 1051 }, 1052 }; 1053 1054 static struct clk_fixed_factor s4_vclk2_div6 = { 1055 .mult = 1, 1056 .div = 6, 1057 .hw.init = &(struct clk_init_data){ 1058 .name = "vclk2_div6", 1059 .ops = &clk_fixed_factor_ops, 1060 .parent_hws = (const struct clk_hw *[]) { 1061 &s4_vclk2_div6_en.hw 1062 }, 1063 .num_parents = 1, 1064 .flags = CLK_SET_RATE_PARENT, 1065 }, 1066 }; 1067 1068 static struct clk_fixed_factor s4_vclk2_div12 = { 1069 .mult = 1, 1070 .div = 12, 1071 .hw.init = &(struct clk_init_data){ 1072 .name = "vclk2_div12", 1073 .ops = &clk_fixed_factor_ops, 1074 .parent_hws = (const struct clk_hw *[]) { 1075 &s4_vclk2_div12_en.hw 1076 }, 1077 .num_parents = 1, 1078 .flags = CLK_SET_RATE_PARENT, 1079 }, 1080 }; 1081 1082 /* The 5,6,7 indexes corresponds to no real clock, so there are not used. */ 1083 static u32 s4_cts_parents_val_table[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 }; 1084 static const struct clk_hw *s4_cts_parents[] = { 1085 &s4_vclk_div1.hw, 1086 &s4_vclk_div2.hw, 1087 &s4_vclk_div4.hw, 1088 &s4_vclk_div6.hw, 1089 &s4_vclk_div12.hw, 1090 &s4_vclk2_div1.hw, 1091 &s4_vclk2_div2.hw, 1092 &s4_vclk2_div4.hw, 1093 &s4_vclk2_div6.hw, 1094 &s4_vclk2_div12.hw 1095 }; 1096 1097 static struct clk_regmap s4_cts_enci_sel = { 1098 .data = &(struct clk_regmap_mux_data){ 1099 .offset = CLKCTRL_VID_CLK_DIV, 1100 .mask = 0xf, 1101 .shift = 28, 1102 .table = s4_cts_parents_val_table, 1103 }, 1104 .hw.init = &(struct clk_init_data){ 1105 .name = "cts_enci_sel", 1106 .ops = &clk_regmap_mux_ops, 1107 .parent_hws = s4_cts_parents, 1108 .num_parents = ARRAY_SIZE(s4_cts_parents), 1109 .flags = CLK_SET_RATE_PARENT, 1110 }, 1111 }; 1112 1113 static struct clk_regmap s4_cts_encp_sel = { 1114 .data = &(struct clk_regmap_mux_data){ 1115 .offset = CLKCTRL_VID_CLK_DIV, 1116 .mask = 0xf, 1117 .shift = 20, 1118 .table = s4_cts_parents_val_table, 1119 }, 1120 .hw.init = &(struct clk_init_data){ 1121 .name = "cts_encp_sel", 1122 .ops = &clk_regmap_mux_ops, 1123 .parent_hws = s4_cts_parents, 1124 .num_parents = ARRAY_SIZE(s4_cts_parents), 1125 .flags = CLK_SET_RATE_PARENT, 1126 }, 1127 }; 1128 1129 static struct clk_regmap s4_cts_vdac_sel = { 1130 .data = &(struct clk_regmap_mux_data){ 1131 .offset = CLKCTRL_VIID_CLK_DIV, 1132 .mask = 0xf, 1133 .shift = 28, 1134 .table = s4_cts_parents_val_table, 1135 }, 1136 .hw.init = &(struct clk_init_data){ 1137 .name = "cts_vdac_sel", 1138 .ops = &clk_regmap_mux_ops, 1139 .parent_hws = s4_cts_parents, 1140 .num_parents = ARRAY_SIZE(s4_cts_parents), 1141 .flags = CLK_SET_RATE_PARENT, 1142 }, 1143 }; 1144 1145 /* The 5,6,7 indexes corresponds to no real clock, so there are not used. */ 1146 static u32 s4_hdmi_tx_parents_val_table[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 }; 1147 static const struct clk_hw *s4_hdmi_tx_parents[] = { 1148 &s4_vclk_div1.hw, 1149 &s4_vclk_div2.hw, 1150 &s4_vclk_div4.hw, 1151 &s4_vclk_div6.hw, 1152 &s4_vclk_div12.hw, 1153 &s4_vclk2_div1.hw, 1154 &s4_vclk2_div2.hw, 1155 &s4_vclk2_div4.hw, 1156 &s4_vclk2_div6.hw, 1157 &s4_vclk2_div12.hw 1158 }; 1159 1160 static struct clk_regmap s4_hdmi_tx_sel = { 1161 .data = &(struct clk_regmap_mux_data){ 1162 .offset = CLKCTRL_HDMI_CLK_CTRL, 1163 .mask = 0xf, 1164 .shift = 16, 1165 .table = s4_hdmi_tx_parents_val_table, 1166 }, 1167 .hw.init = &(struct clk_init_data){ 1168 .name = "hdmi_tx_sel", 1169 .ops = &clk_regmap_mux_ops, 1170 .parent_hws = s4_hdmi_tx_parents, 1171 .num_parents = ARRAY_SIZE(s4_hdmi_tx_parents), 1172 .flags = CLK_SET_RATE_PARENT, 1173 }, 1174 }; 1175 1176 static struct clk_regmap s4_cts_enci = { 1177 .data = &(struct clk_regmap_gate_data){ 1178 .offset = CLKCTRL_VID_CLK_CTRL2, 1179 .bit_idx = 0, 1180 }, 1181 .hw.init = &(struct clk_init_data) { 1182 .name = "cts_enci", 1183 .ops = &clk_regmap_gate_ops, 1184 .parent_hws = (const struct clk_hw *[]) { 1185 &s4_cts_enci_sel.hw 1186 }, 1187 .num_parents = 1, 1188 .flags = CLK_SET_RATE_PARENT, 1189 }, 1190 }; 1191 1192 static struct clk_regmap s4_cts_encp = { 1193 .data = &(struct clk_regmap_gate_data){ 1194 .offset = CLKCTRL_VID_CLK_CTRL2, 1195 .bit_idx = 2, 1196 }, 1197 .hw.init = &(struct clk_init_data) { 1198 .name = "cts_encp", 1199 .ops = &clk_regmap_gate_ops, 1200 .parent_hws = (const struct clk_hw *[]) { 1201 &s4_cts_encp_sel.hw 1202 }, 1203 .num_parents = 1, 1204 .flags = CLK_SET_RATE_PARENT, 1205 }, 1206 }; 1207 1208 static struct clk_regmap s4_cts_vdac = { 1209 .data = &(struct clk_regmap_gate_data){ 1210 .offset = CLKCTRL_VID_CLK_CTRL2, 1211 .bit_idx = 4, 1212 }, 1213 .hw.init = &(struct clk_init_data) { 1214 .name = "cts_vdac", 1215 .ops = &clk_regmap_gate_ops, 1216 .parent_hws = (const struct clk_hw *[]) { 1217 &s4_cts_vdac_sel.hw 1218 }, 1219 .num_parents = 1, 1220 .flags = CLK_SET_RATE_PARENT, 1221 }, 1222 }; 1223 1224 static struct clk_regmap s4_hdmi_tx = { 1225 .data = &(struct clk_regmap_gate_data){ 1226 .offset = CLKCTRL_VID_CLK_CTRL2, 1227 .bit_idx = 5, 1228 }, 1229 .hw.init = &(struct clk_init_data) { 1230 .name = "hdmi_tx", 1231 .ops = &clk_regmap_gate_ops, 1232 .parent_hws = (const struct clk_hw *[]) { 1233 &s4_hdmi_tx_sel.hw 1234 }, 1235 .num_parents = 1, 1236 .flags = CLK_SET_RATE_PARENT, 1237 }, 1238 }; 1239 1240 /* HDMI Clocks */ 1241 static const struct clk_parent_data s4_hdmi_parents[] = { 1242 { .fw_name = "xtal", }, 1243 { .fw_name = "fclk_div4", }, 1244 { .fw_name = "fclk_div3", }, 1245 { .fw_name = "fclk_div5", } 1246 }; 1247 1248 static struct clk_regmap s4_hdmi_sel = { 1249 .data = &(struct clk_regmap_mux_data){ 1250 .offset = CLKCTRL_HDMI_CLK_CTRL, 1251 .mask = 0x3, 1252 .shift = 9, 1253 .flags = CLK_MUX_ROUND_CLOSEST, 1254 }, 1255 .hw.init = &(struct clk_init_data){ 1256 .name = "hdmi_sel", 1257 .ops = &clk_regmap_mux_ops, 1258 .parent_data = s4_hdmi_parents, 1259 .num_parents = ARRAY_SIZE(s4_hdmi_parents), 1260 .flags = CLK_SET_RATE_PARENT, 1261 }, 1262 }; 1263 1264 static struct clk_regmap s4_hdmi_div = { 1265 .data = &(struct clk_regmap_div_data){ 1266 .offset = CLKCTRL_HDMI_CLK_CTRL, 1267 .shift = 0, 1268 .width = 7, 1269 }, 1270 .hw.init = &(struct clk_init_data){ 1271 .name = "hdmi_div", 1272 .ops = &clk_regmap_divider_ops, 1273 .parent_hws = (const struct clk_hw *[]) { &s4_hdmi_sel.hw }, 1274 .num_parents = 1, 1275 .flags = CLK_SET_RATE_PARENT, 1276 }, 1277 }; 1278 1279 static struct clk_regmap s4_hdmi = { 1280 .data = &(struct clk_regmap_gate_data){ 1281 .offset = CLKCTRL_HDMI_CLK_CTRL, 1282 .bit_idx = 8, 1283 }, 1284 .hw.init = &(struct clk_init_data) { 1285 .name = "hdmi", 1286 .ops = &clk_regmap_gate_ops, 1287 .parent_hws = (const struct clk_hw *[]) { &s4_hdmi_div.hw }, 1288 .num_parents = 1, 1289 .flags = CLK_SET_RATE_PARENT, 1290 }, 1291 }; 1292 1293 static struct clk_regmap s4_ts_clk_div = { 1294 .data = &(struct clk_regmap_div_data){ 1295 .offset = CLKCTRL_TS_CLK_CTRL, 1296 .shift = 0, 1297 .width = 8, 1298 }, 1299 .hw.init = &(struct clk_init_data){ 1300 .name = "ts_clk_div", 1301 .ops = &clk_regmap_divider_ops, 1302 .parent_data = &(const struct clk_parent_data) { 1303 .fw_name = "xtal", 1304 }, 1305 .num_parents = 1, 1306 .flags = CLK_SET_RATE_PARENT, 1307 }, 1308 }; 1309 1310 static struct clk_regmap s4_ts_clk = { 1311 .data = &(struct clk_regmap_gate_data){ 1312 .offset = CLKCTRL_TS_CLK_CTRL, 1313 .bit_idx = 8, 1314 }, 1315 .hw.init = &(struct clk_init_data){ 1316 .name = "ts_clk", 1317 .ops = &clk_regmap_gate_ops, 1318 .parent_hws = (const struct clk_hw *[]) { 1319 &s4_ts_clk_div.hw 1320 }, 1321 .num_parents = 1, 1322 .flags = CLK_SET_RATE_PARENT, 1323 }, 1324 }; 1325 1326 /* 1327 * The MALI IP is clocked by two identical clocks (mali_0 and mali_1) 1328 * muxed by a glitch-free switch. The CCF can manage this glitch-free 1329 * mux because it does top-to-bottom updates the each clock tree and 1330 * switches to the "inactive" one when CLK_SET_RATE_GATE is set. 1331 */ 1332 static const struct clk_parent_data s4_mali_parents[] = { 1333 { .fw_name = "xtal", }, 1334 { .fw_name = "gp0_pll", }, 1335 { .fw_name = "hifi_pll", }, 1336 { .fw_name = "fclk_div2p5", }, 1337 { .fw_name = "fclk_div3", }, 1338 { .fw_name = "fclk_div4", }, 1339 { .fw_name = "fclk_div5", }, 1340 { .fw_name = "fclk_div7", } 1341 }; 1342 1343 static struct clk_regmap s4_mali_0_sel = { 1344 .data = &(struct clk_regmap_mux_data){ 1345 .offset = CLKCTRL_MALI_CLK_CTRL, 1346 .mask = 0x7, 1347 .shift = 9, 1348 }, 1349 .hw.init = &(struct clk_init_data){ 1350 .name = "mali_0_sel", 1351 .ops = &clk_regmap_mux_ops, 1352 .parent_data = s4_mali_parents, 1353 .num_parents = ARRAY_SIZE(s4_mali_parents), 1354 /* 1355 * Don't request the parent to change the rate because 1356 * all GPU frequencies can be derived from the fclk_* 1357 * clocks and one special GP0_PLL setting. This is 1358 * important because we need the HIFI PLL clock for audio. 1359 */ 1360 .flags = 0, 1361 }, 1362 }; 1363 1364 static struct clk_regmap s4_mali_0_div = { 1365 .data = &(struct clk_regmap_div_data){ 1366 .offset = CLKCTRL_MALI_CLK_CTRL, 1367 .shift = 0, 1368 .width = 7, 1369 }, 1370 .hw.init = &(struct clk_init_data){ 1371 .name = "mali_0_div", 1372 .ops = &clk_regmap_divider_ops, 1373 .parent_hws = (const struct clk_hw *[]) { 1374 &s4_mali_0_sel.hw 1375 }, 1376 .num_parents = 1, 1377 .flags = CLK_SET_RATE_PARENT, 1378 }, 1379 }; 1380 1381 static struct clk_regmap s4_mali_0 = { 1382 .data = &(struct clk_regmap_gate_data){ 1383 .offset = CLKCTRL_MALI_CLK_CTRL, 1384 .bit_idx = 8, 1385 }, 1386 .hw.init = &(struct clk_init_data){ 1387 .name = "mali_0", 1388 .ops = &clk_regmap_gate_ops, 1389 .parent_hws = (const struct clk_hw *[]) { 1390 &s4_mali_0_div.hw 1391 }, 1392 .num_parents = 1, 1393 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, 1394 }, 1395 }; 1396 1397 static struct clk_regmap s4_mali_1_sel = { 1398 .data = &(struct clk_regmap_mux_data){ 1399 .offset = CLKCTRL_MALI_CLK_CTRL, 1400 .mask = 0x7, 1401 .shift = 25, 1402 }, 1403 .hw.init = &(struct clk_init_data){ 1404 .name = "mali_1_sel", 1405 .ops = &clk_regmap_mux_ops, 1406 .parent_data = s4_mali_parents, 1407 .num_parents = ARRAY_SIZE(s4_mali_parents), 1408 .flags = 0, 1409 }, 1410 }; 1411 1412 static struct clk_regmap s4_mali_1_div = { 1413 .data = &(struct clk_regmap_div_data){ 1414 .offset = CLKCTRL_MALI_CLK_CTRL, 1415 .shift = 16, 1416 .width = 7, 1417 }, 1418 .hw.init = &(struct clk_init_data){ 1419 .name = "mali_1_div", 1420 .ops = &clk_regmap_divider_ops, 1421 .parent_hws = (const struct clk_hw *[]) { 1422 &s4_mali_1_sel.hw 1423 }, 1424 .num_parents = 1, 1425 .flags = CLK_SET_RATE_PARENT, 1426 }, 1427 }; 1428 1429 static struct clk_regmap s4_mali_1 = { 1430 .data = &(struct clk_regmap_gate_data){ 1431 .offset = CLKCTRL_MALI_CLK_CTRL, 1432 .bit_idx = 24, 1433 }, 1434 .hw.init = &(struct clk_init_data){ 1435 .name = "mali_1", 1436 .ops = &clk_regmap_gate_ops, 1437 .parent_hws = (const struct clk_hw *[]) { 1438 &s4_mali_1_div.hw 1439 }, 1440 .num_parents = 1, 1441 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, 1442 }, 1443 }; 1444 1445 static struct clk_regmap s4_mali_sel = { 1446 .data = &(struct clk_regmap_mux_data){ 1447 .offset = CLKCTRL_MALI_CLK_CTRL, 1448 .mask = 1, 1449 .shift = 31, 1450 }, 1451 .hw.init = &(struct clk_init_data){ 1452 .name = "mali_sel", 1453 .ops = &clk_regmap_mux_ops, 1454 .parent_hws = (const struct clk_hw *[]) { 1455 &s4_mali_0.hw, 1456 &s4_mali_1.hw, 1457 }, 1458 .num_parents = 2, 1459 .flags = CLK_SET_RATE_PARENT, 1460 }, 1461 }; 1462 1463 /* VDEC clocks */ 1464 static const struct clk_parent_data s4_dec_parents[] = { 1465 { .fw_name = "fclk_div2p5", }, 1466 { .fw_name = "fclk_div3", }, 1467 { .fw_name = "fclk_div4", }, 1468 { .fw_name = "fclk_div5", }, 1469 { .fw_name = "fclk_div7", }, 1470 { .fw_name = "hifi_pll", }, 1471 { .fw_name = "gp0_pll", }, 1472 { .fw_name = "xtal", } 1473 }; 1474 1475 static struct clk_regmap s4_vdec_p0_sel = { 1476 .data = &(struct clk_regmap_mux_data){ 1477 .offset = CLKCTRL_VDEC_CLK_CTRL, 1478 .mask = 0x7, 1479 .shift = 9, 1480 .flags = CLK_MUX_ROUND_CLOSEST, 1481 }, 1482 .hw.init = &(struct clk_init_data) { 1483 .name = "vdec_p0_sel", 1484 .ops = &clk_regmap_mux_ops, 1485 .parent_data = s4_dec_parents, 1486 .num_parents = ARRAY_SIZE(s4_dec_parents), 1487 .flags = 0, 1488 }, 1489 }; 1490 1491 static struct clk_regmap s4_vdec_p0_div = { 1492 .data = &(struct clk_regmap_div_data){ 1493 .offset = CLKCTRL_VDEC_CLK_CTRL, 1494 .shift = 0, 1495 .width = 7, 1496 .flags = CLK_DIVIDER_ROUND_CLOSEST, 1497 }, 1498 .hw.init = &(struct clk_init_data) { 1499 .name = "vdec_p0_div", 1500 .ops = &clk_regmap_divider_ops, 1501 .parent_hws = (const struct clk_hw *[]) { 1502 &s4_vdec_p0_sel.hw 1503 }, 1504 .num_parents = 1, 1505 .flags = CLK_SET_RATE_PARENT, 1506 }, 1507 }; 1508 1509 static struct clk_regmap s4_vdec_p0 = { 1510 .data = &(struct clk_regmap_gate_data){ 1511 .offset = CLKCTRL_VDEC_CLK_CTRL, 1512 .bit_idx = 8, 1513 }, 1514 .hw.init = &(struct clk_init_data){ 1515 .name = "vdec_p0", 1516 .ops = &clk_regmap_gate_ops, 1517 .parent_hws = (const struct clk_hw *[]) { 1518 &s4_vdec_p0_div.hw 1519 }, 1520 .num_parents = 1, 1521 .flags = CLK_SET_RATE_PARENT, 1522 }, 1523 }; 1524 1525 static struct clk_regmap s4_vdec_p1_sel = { 1526 .data = &(struct clk_regmap_mux_data){ 1527 .offset = CLKCTRL_VDEC3_CLK_CTRL, 1528 .mask = 0x7, 1529 .shift = 9, 1530 .flags = CLK_MUX_ROUND_CLOSEST, 1531 }, 1532 .hw.init = &(struct clk_init_data) { 1533 .name = "vdec_p1_sel", 1534 .ops = &clk_regmap_mux_ops, 1535 .parent_data = s4_dec_parents, 1536 .num_parents = ARRAY_SIZE(s4_dec_parents), 1537 .flags = 0, 1538 }, 1539 }; 1540 1541 static struct clk_regmap s4_vdec_p1_div = { 1542 .data = &(struct clk_regmap_div_data){ 1543 .offset = CLKCTRL_VDEC3_CLK_CTRL, 1544 .shift = 0, 1545 .width = 7, 1546 .flags = CLK_DIVIDER_ROUND_CLOSEST, 1547 }, 1548 .hw.init = &(struct clk_init_data) { 1549 .name = "vdec_p1_div", 1550 .ops = &clk_regmap_divider_ops, 1551 .parent_hws = (const struct clk_hw *[]) { 1552 &s4_vdec_p1_sel.hw 1553 }, 1554 .num_parents = 1, 1555 .flags = CLK_SET_RATE_PARENT, 1556 }, 1557 }; 1558 1559 static struct clk_regmap s4_vdec_p1 = { 1560 .data = &(struct clk_regmap_gate_data){ 1561 .offset = CLKCTRL_VDEC3_CLK_CTRL, 1562 .bit_idx = 8, 1563 }, 1564 .hw.init = &(struct clk_init_data){ 1565 .name = "vdec_p1", 1566 .ops = &clk_regmap_gate_ops, 1567 .parent_hws = (const struct clk_hw *[]) { 1568 &s4_vdec_p1_div.hw 1569 }, 1570 .num_parents = 1, 1571 .flags = CLK_SET_RATE_PARENT, 1572 }, 1573 }; 1574 1575 static struct clk_regmap s4_vdec_sel = { 1576 .data = &(struct clk_regmap_mux_data){ 1577 .offset = CLKCTRL_VDEC3_CLK_CTRL, 1578 .mask = 0x1, 1579 .shift = 15, 1580 }, 1581 .hw.init = &(struct clk_init_data) { 1582 .name = "vdec_sel", 1583 .ops = &clk_regmap_mux_ops, 1584 .parent_hws = (const struct clk_hw *[]) { 1585 &s4_vdec_p0.hw, 1586 &s4_vdec_p1.hw, 1587 }, 1588 .num_parents = 2, 1589 .flags = CLK_SET_RATE_PARENT, 1590 }, 1591 }; 1592 1593 static struct clk_regmap s4_hevcf_p0_sel = { 1594 .data = &(struct clk_regmap_mux_data){ 1595 .offset = CLKCTRL_VDEC2_CLK_CTRL, 1596 .mask = 0x7, 1597 .shift = 9, 1598 .flags = CLK_MUX_ROUND_CLOSEST, 1599 }, 1600 .hw.init = &(struct clk_init_data) { 1601 .name = "hevcf_p0_sel", 1602 .ops = &clk_regmap_mux_ops, 1603 .parent_data = s4_dec_parents, 1604 .num_parents = ARRAY_SIZE(s4_dec_parents), 1605 .flags = 0, 1606 }, 1607 }; 1608 1609 static struct clk_regmap s4_hevcf_p0_div = { 1610 .data = &(struct clk_regmap_div_data){ 1611 .offset = CLKCTRL_VDEC2_CLK_CTRL, 1612 .shift = 0, 1613 .width = 7, 1614 .flags = CLK_DIVIDER_ROUND_CLOSEST, 1615 }, 1616 .hw.init = &(struct clk_init_data) { 1617 .name = "hevcf_p0_div", 1618 .ops = &clk_regmap_divider_ops, 1619 .parent_hws = (const struct clk_hw *[]) { 1620 &s4_hevcf_p0_sel.hw 1621 }, 1622 .num_parents = 1, 1623 .flags = CLK_SET_RATE_PARENT, 1624 }, 1625 }; 1626 1627 static struct clk_regmap s4_hevcf_p0 = { 1628 .data = &(struct clk_regmap_gate_data){ 1629 .offset = CLKCTRL_VDEC2_CLK_CTRL, 1630 .bit_idx = 8, 1631 }, 1632 .hw.init = &(struct clk_init_data){ 1633 .name = "hevcf_p0", 1634 .ops = &clk_regmap_gate_ops, 1635 .parent_hws = (const struct clk_hw *[]) { 1636 &s4_hevcf_p0_div.hw 1637 }, 1638 .num_parents = 1, 1639 .flags = CLK_SET_RATE_PARENT, 1640 }, 1641 }; 1642 1643 static struct clk_regmap s4_hevcf_p1_sel = { 1644 .data = &(struct clk_regmap_mux_data){ 1645 .offset = CLKCTRL_VDEC4_CLK_CTRL, 1646 .mask = 0x7, 1647 .shift = 9, 1648 .flags = CLK_MUX_ROUND_CLOSEST, 1649 }, 1650 .hw.init = &(struct clk_init_data) { 1651 .name = "hevcf_p1_sel", 1652 .ops = &clk_regmap_mux_ops, 1653 .parent_data = s4_dec_parents, 1654 .num_parents = ARRAY_SIZE(s4_dec_parents), 1655 .flags = 0, 1656 }, 1657 }; 1658 1659 static struct clk_regmap s4_hevcf_p1_div = { 1660 .data = &(struct clk_regmap_div_data){ 1661 .offset = CLKCTRL_VDEC4_CLK_CTRL, 1662 .shift = 0, 1663 .width = 7, 1664 .flags = CLK_DIVIDER_ROUND_CLOSEST, 1665 }, 1666 .hw.init = &(struct clk_init_data) { 1667 .name = "hevcf_p1_div", 1668 .ops = &clk_regmap_divider_ops, 1669 .parent_hws = (const struct clk_hw *[]) { 1670 &s4_hevcf_p1_sel.hw 1671 }, 1672 .num_parents = 1, 1673 .flags = CLK_SET_RATE_PARENT, 1674 }, 1675 }; 1676 1677 static struct clk_regmap s4_hevcf_p1 = { 1678 .data = &(struct clk_regmap_gate_data){ 1679 .offset = CLKCTRL_VDEC4_CLK_CTRL, 1680 .bit_idx = 8, 1681 }, 1682 .hw.init = &(struct clk_init_data){ 1683 .name = "hevcf_p1", 1684 .ops = &clk_regmap_gate_ops, 1685 .parent_hws = (const struct clk_hw *[]) { 1686 &s4_hevcf_p1_div.hw 1687 }, 1688 .num_parents = 1, 1689 .flags = CLK_SET_RATE_PARENT, 1690 }, 1691 }; 1692 1693 static struct clk_regmap s4_hevcf_sel = { 1694 .data = &(struct clk_regmap_mux_data){ 1695 .offset = CLKCTRL_VDEC4_CLK_CTRL, 1696 .mask = 0x1, 1697 .shift = 15, 1698 }, 1699 .hw.init = &(struct clk_init_data) { 1700 .name = "hevcf_sel", 1701 .ops = &clk_regmap_mux_ops, 1702 .parent_hws = (const struct clk_hw *[]) { 1703 &s4_hevcf_p0.hw, 1704 &s4_hevcf_p1.hw, 1705 }, 1706 .num_parents = 2, 1707 .flags = CLK_SET_RATE_PARENT, 1708 }, 1709 }; 1710 1711 /* VPU Clock */ 1712 static const struct clk_parent_data s4_vpu_parents[] = { 1713 { .fw_name = "fclk_div3", }, 1714 { .fw_name = "fclk_div4", }, 1715 { .fw_name = "fclk_div5", }, 1716 { .fw_name = "fclk_div7", }, 1717 { .fw_name = "mpll1", }, 1718 { .hw = &s4_vid_pll.hw }, 1719 { .fw_name = "hifi_pll", }, 1720 { .fw_name = "gp0_pll", }, 1721 }; 1722 1723 static struct clk_regmap s4_vpu_0_sel = { 1724 .data = &(struct clk_regmap_mux_data){ 1725 .offset = CLKCTRL_VPU_CLK_CTRL, 1726 .mask = 0x7, 1727 .shift = 9, 1728 }, 1729 .hw.init = &(struct clk_init_data){ 1730 .name = "vpu_0_sel", 1731 .ops = &clk_regmap_mux_ops, 1732 .parent_data = s4_vpu_parents, 1733 .num_parents = ARRAY_SIZE(s4_vpu_parents), 1734 .flags = 0, 1735 }, 1736 }; 1737 1738 static struct clk_regmap s4_vpu_0_div = { 1739 .data = &(struct clk_regmap_div_data){ 1740 .offset = CLKCTRL_VPU_CLK_CTRL, 1741 .shift = 0, 1742 .width = 7, 1743 }, 1744 .hw.init = &(struct clk_init_data){ 1745 .name = "vpu_0_div", 1746 .ops = &clk_regmap_divider_ops, 1747 .parent_hws = (const struct clk_hw *[]) { &s4_vpu_0_sel.hw }, 1748 .num_parents = 1, 1749 .flags = CLK_SET_RATE_PARENT, 1750 }, 1751 }; 1752 1753 static struct clk_regmap s4_vpu_0 = { 1754 .data = &(struct clk_regmap_gate_data){ 1755 .offset = CLKCTRL_VPU_CLK_CTRL, 1756 .bit_idx = 8, 1757 }, 1758 .hw.init = &(struct clk_init_data) { 1759 .name = "vpu_0", 1760 .ops = &clk_regmap_gate_ops, 1761 .parent_hws = (const struct clk_hw *[]) { &s4_vpu_0_div.hw }, 1762 .num_parents = 1, 1763 .flags = CLK_SET_RATE_PARENT, 1764 }, 1765 }; 1766 1767 static struct clk_regmap s4_vpu_1_sel = { 1768 .data = &(struct clk_regmap_mux_data){ 1769 .offset = CLKCTRL_VPU_CLK_CTRL, 1770 .mask = 0x7, 1771 .shift = 25, 1772 }, 1773 .hw.init = &(struct clk_init_data){ 1774 .name = "vpu_1_sel", 1775 .ops = &clk_regmap_mux_ops, 1776 .parent_data = s4_vpu_parents, 1777 .num_parents = ARRAY_SIZE(s4_vpu_parents), 1778 .flags = 0, 1779 }, 1780 }; 1781 1782 static struct clk_regmap s4_vpu_1_div = { 1783 .data = &(struct clk_regmap_div_data){ 1784 .offset = CLKCTRL_VPU_CLK_CTRL, 1785 .shift = 16, 1786 .width = 7, 1787 }, 1788 .hw.init = &(struct clk_init_data){ 1789 .name = "vpu_1_div", 1790 .ops = &clk_regmap_divider_ops, 1791 .parent_hws = (const struct clk_hw *[]) { &s4_vpu_1_sel.hw }, 1792 .num_parents = 1, 1793 .flags = CLK_SET_RATE_PARENT, 1794 }, 1795 }; 1796 1797 static struct clk_regmap s4_vpu_1 = { 1798 .data = &(struct clk_regmap_gate_data){ 1799 .offset = CLKCTRL_VPU_CLK_CTRL, 1800 .bit_idx = 24, 1801 }, 1802 .hw.init = &(struct clk_init_data) { 1803 .name = "vpu_1", 1804 .ops = &clk_regmap_gate_ops, 1805 .parent_hws = (const struct clk_hw *[]) { &s4_vpu_1_div.hw }, 1806 .num_parents = 1, 1807 .flags = CLK_SET_RATE_PARENT, 1808 }, 1809 }; 1810 1811 static struct clk_regmap s4_vpu = { 1812 .data = &(struct clk_regmap_mux_data){ 1813 .offset = CLKCTRL_VPU_CLK_CTRL, 1814 .mask = 1, 1815 .shift = 31, 1816 }, 1817 .hw.init = &(struct clk_init_data){ 1818 .name = "vpu", 1819 .ops = &clk_regmap_mux_ops, 1820 .parent_hws = (const struct clk_hw *[]) { 1821 &s4_vpu_0.hw, 1822 &s4_vpu_1.hw, 1823 }, 1824 .num_parents = 2, 1825 .flags = CLK_SET_RATE_PARENT, 1826 }, 1827 }; 1828 1829 static const struct clk_parent_data vpu_clkb_tmp_parents[] = { 1830 { .hw = &s4_vpu.hw }, 1831 { .fw_name = "fclk_div4", }, 1832 { .fw_name = "fclk_div5", }, 1833 { .fw_name = "fclk_div7", } 1834 }; 1835 1836 static struct clk_regmap s4_vpu_clkb_tmp_sel = { 1837 .data = &(struct clk_regmap_mux_data){ 1838 .offset = CLKCTRL_VPU_CLKB_CTRL, 1839 .mask = 0x3, 1840 .shift = 20, 1841 }, 1842 .hw.init = &(struct clk_init_data) { 1843 .name = "vpu_clkb_tmp_sel", 1844 .ops = &clk_regmap_mux_ops, 1845 .parent_data = vpu_clkb_tmp_parents, 1846 .num_parents = ARRAY_SIZE(vpu_clkb_tmp_parents), 1847 .flags = CLK_SET_RATE_PARENT, 1848 }, 1849 }; 1850 1851 static struct clk_regmap s4_vpu_clkb_tmp_div = { 1852 .data = &(struct clk_regmap_div_data){ 1853 .offset = CLKCTRL_VPU_CLKB_CTRL, 1854 .shift = 16, 1855 .width = 4, 1856 }, 1857 .hw.init = &(struct clk_init_data) { 1858 .name = "vpu_clkb_tmp_div", 1859 .ops = &clk_regmap_divider_ops, 1860 .parent_hws = (const struct clk_hw *[]) { 1861 &s4_vpu_clkb_tmp_sel.hw 1862 }, 1863 .num_parents = 1, 1864 .flags = CLK_SET_RATE_PARENT, 1865 }, 1866 }; 1867 1868 static struct clk_regmap s4_vpu_clkb_tmp = { 1869 .data = &(struct clk_regmap_gate_data){ 1870 .offset = CLKCTRL_VPU_CLKB_CTRL, 1871 .bit_idx = 24, 1872 }, 1873 .hw.init = &(struct clk_init_data){ 1874 .name = "vpu_clkb_tmp", 1875 .ops = &clk_regmap_gate_ops, 1876 .parent_hws = (const struct clk_hw *[]) { 1877 &s4_vpu_clkb_tmp_div.hw 1878 }, 1879 .num_parents = 1, 1880 .flags = CLK_SET_RATE_PARENT, 1881 }, 1882 }; 1883 1884 static struct clk_regmap s4_vpu_clkb_div = { 1885 .data = &(struct clk_regmap_div_data){ 1886 .offset = CLKCTRL_VPU_CLKB_CTRL, 1887 .shift = 0, 1888 .width = 8, 1889 }, 1890 .hw.init = &(struct clk_init_data) { 1891 .name = "vpu_clkb_div", 1892 .ops = &clk_regmap_divider_ops, 1893 .parent_hws = (const struct clk_hw *[]) { 1894 &s4_vpu_clkb_tmp.hw 1895 }, 1896 .num_parents = 1, 1897 .flags = CLK_SET_RATE_PARENT, 1898 }, 1899 }; 1900 1901 static struct clk_regmap s4_vpu_clkb = { 1902 .data = &(struct clk_regmap_gate_data){ 1903 .offset = CLKCTRL_VPU_CLKB_CTRL, 1904 .bit_idx = 8, 1905 }, 1906 .hw.init = &(struct clk_init_data){ 1907 .name = "vpu_clkb", 1908 .ops = &clk_regmap_gate_ops, 1909 .parent_hws = (const struct clk_hw *[]) { 1910 &s4_vpu_clkb_div.hw 1911 }, 1912 .num_parents = 1, 1913 .flags = CLK_SET_RATE_PARENT, 1914 }, 1915 }; 1916 1917 static const struct clk_parent_data s4_vpu_clkc_parents[] = { 1918 { .fw_name = "fclk_div4", }, 1919 { .fw_name = "fclk_div3", }, 1920 { .fw_name = "fclk_div5", }, 1921 { .fw_name = "fclk_div7", }, 1922 { .fw_name = "mpll1", }, 1923 { .hw = &s4_vid_pll.hw }, 1924 { .fw_name = "mpll2", }, 1925 { .fw_name = "gp0_pll", }, 1926 }; 1927 1928 static struct clk_regmap s4_vpu_clkc_p0_sel = { 1929 .data = &(struct clk_regmap_mux_data){ 1930 .offset = CLKCTRL_VPU_CLKC_CTRL, 1931 .mask = 0x7, 1932 .shift = 9, 1933 }, 1934 .hw.init = &(struct clk_init_data) { 1935 .name = "vpu_clkc_p0_sel", 1936 .ops = &clk_regmap_mux_ops, 1937 .parent_data = s4_vpu_clkc_parents, 1938 .num_parents = ARRAY_SIZE(s4_vpu_clkc_parents), 1939 .flags = 0, 1940 }, 1941 }; 1942 1943 static struct clk_regmap s4_vpu_clkc_p0_div = { 1944 .data = &(struct clk_regmap_div_data){ 1945 .offset = CLKCTRL_VPU_CLKC_CTRL, 1946 .shift = 0, 1947 .width = 7, 1948 }, 1949 .hw.init = &(struct clk_init_data) { 1950 .name = "vpu_clkc_p0_div", 1951 .ops = &clk_regmap_divider_ops, 1952 .parent_hws = (const struct clk_hw *[]) { 1953 &s4_vpu_clkc_p0_sel.hw 1954 }, 1955 .num_parents = 1, 1956 .flags = CLK_SET_RATE_PARENT, 1957 }, 1958 }; 1959 1960 static struct clk_regmap s4_vpu_clkc_p0 = { 1961 .data = &(struct clk_regmap_gate_data){ 1962 .offset = CLKCTRL_VPU_CLKC_CTRL, 1963 .bit_idx = 8, 1964 }, 1965 .hw.init = &(struct clk_init_data){ 1966 .name = "vpu_clkc_p0", 1967 .ops = &clk_regmap_gate_ops, 1968 .parent_hws = (const struct clk_hw *[]) { 1969 &s4_vpu_clkc_p0_div.hw 1970 }, 1971 .num_parents = 1, 1972 .flags = CLK_SET_RATE_PARENT, 1973 }, 1974 }; 1975 1976 static struct clk_regmap s4_vpu_clkc_p1_sel = { 1977 .data = &(struct clk_regmap_mux_data){ 1978 .offset = CLKCTRL_VPU_CLKC_CTRL, 1979 .mask = 0x7, 1980 .shift = 25, 1981 }, 1982 .hw.init = &(struct clk_init_data) { 1983 .name = "vpu_clkc_p1_sel", 1984 .ops = &clk_regmap_mux_ops, 1985 .parent_data = s4_vpu_clkc_parents, 1986 .num_parents = ARRAY_SIZE(s4_vpu_clkc_parents), 1987 .flags = 0, 1988 }, 1989 }; 1990 1991 static struct clk_regmap s4_vpu_clkc_p1_div = { 1992 .data = &(struct clk_regmap_div_data){ 1993 .offset = CLKCTRL_VPU_CLKC_CTRL, 1994 .shift = 16, 1995 .width = 7, 1996 }, 1997 .hw.init = &(struct clk_init_data) { 1998 .name = "vpu_clkc_p1_div", 1999 .ops = &clk_regmap_divider_ops, 2000 .parent_hws = (const struct clk_hw *[]) { 2001 &s4_vpu_clkc_p1_sel.hw 2002 }, 2003 .num_parents = 1, 2004 .flags = CLK_SET_RATE_PARENT, 2005 }, 2006 }; 2007 2008 static struct clk_regmap s4_vpu_clkc_p1 = { 2009 .data = &(struct clk_regmap_gate_data){ 2010 .offset = CLKCTRL_VPU_CLKC_CTRL, 2011 .bit_idx = 24, 2012 }, 2013 .hw.init = &(struct clk_init_data){ 2014 .name = "vpu_clkc_p1", 2015 .ops = &clk_regmap_gate_ops, 2016 .parent_hws = (const struct clk_hw *[]) { 2017 &s4_vpu_clkc_p1_div.hw 2018 }, 2019 .num_parents = 1, 2020 .flags = CLK_SET_RATE_PARENT, 2021 }, 2022 }; 2023 2024 static struct clk_regmap s4_vpu_clkc_sel = { 2025 .data = &(struct clk_regmap_mux_data){ 2026 .offset = CLKCTRL_VPU_CLKC_CTRL, 2027 .mask = 0x1, 2028 .shift = 31, 2029 }, 2030 .hw.init = &(struct clk_init_data) { 2031 .name = "vpu_clkc_sel", 2032 .ops = &clk_regmap_mux_ops, 2033 .parent_hws = (const struct clk_hw *[]) { 2034 &s4_vpu_clkc_p0.hw, 2035 &s4_vpu_clkc_p1.hw, 2036 }, 2037 .num_parents = 2, 2038 .flags = CLK_SET_RATE_PARENT, 2039 }, 2040 }; 2041 2042 /* VAPB Clock */ 2043 static const struct clk_parent_data s4_vapb_parents[] = { 2044 { .fw_name = "fclk_div4", }, 2045 { .fw_name = "fclk_div3", }, 2046 { .fw_name = "fclk_div5", }, 2047 { .fw_name = "fclk_div7", }, 2048 { .fw_name = "mpll1", }, 2049 { .hw = &s4_vid_pll.hw }, 2050 { .fw_name = "mpll2", }, 2051 { .fw_name = "fclk_div2p5", }, 2052 }; 2053 2054 static struct clk_regmap s4_vapb_0_sel = { 2055 .data = &(struct clk_regmap_mux_data){ 2056 .offset = CLKCTRL_VAPBCLK_CTRL, 2057 .mask = 0x7, 2058 .shift = 9, 2059 }, 2060 .hw.init = &(struct clk_init_data){ 2061 .name = "vapb_0_sel", 2062 .ops = &clk_regmap_mux_ops, 2063 .parent_data = s4_vapb_parents, 2064 .num_parents = ARRAY_SIZE(s4_vapb_parents), 2065 .flags = 0, 2066 }, 2067 }; 2068 2069 static struct clk_regmap s4_vapb_0_div = { 2070 .data = &(struct clk_regmap_div_data){ 2071 .offset = CLKCTRL_VAPBCLK_CTRL, 2072 .shift = 0, 2073 .width = 7, 2074 }, 2075 .hw.init = &(struct clk_init_data){ 2076 .name = "vapb_0_div", 2077 .ops = &clk_regmap_divider_ops, 2078 .parent_hws = (const struct clk_hw *[]) { 2079 &s4_vapb_0_sel.hw 2080 }, 2081 .num_parents = 1, 2082 .flags = CLK_SET_RATE_PARENT, 2083 }, 2084 }; 2085 2086 static struct clk_regmap s4_vapb_0 = { 2087 .data = &(struct clk_regmap_gate_data){ 2088 .offset = CLKCTRL_VAPBCLK_CTRL, 2089 .bit_idx = 8, 2090 }, 2091 .hw.init = &(struct clk_init_data) { 2092 .name = "vapb_0", 2093 .ops = &clk_regmap_gate_ops, 2094 .parent_hws = (const struct clk_hw *[]) { 2095 &s4_vapb_0_div.hw 2096 }, 2097 .num_parents = 1, 2098 .flags = CLK_SET_RATE_PARENT, 2099 }, 2100 }; 2101 2102 static struct clk_regmap s4_vapb_1_sel = { 2103 .data = &(struct clk_regmap_mux_data){ 2104 .offset = CLKCTRL_VAPBCLK_CTRL, 2105 .mask = 0x7, 2106 .shift = 25, 2107 }, 2108 .hw.init = &(struct clk_init_data){ 2109 .name = "vapb_1_sel", 2110 .ops = &clk_regmap_mux_ops, 2111 .parent_data = s4_vapb_parents, 2112 .num_parents = ARRAY_SIZE(s4_vapb_parents), 2113 .flags = 0, 2114 }, 2115 }; 2116 2117 static struct clk_regmap s4_vapb_1_div = { 2118 .data = &(struct clk_regmap_div_data){ 2119 .offset = CLKCTRL_VAPBCLK_CTRL, 2120 .shift = 16, 2121 .width = 7, 2122 }, 2123 .hw.init = &(struct clk_init_data){ 2124 .name = "vapb_1_div", 2125 .ops = &clk_regmap_divider_ops, 2126 .parent_hws = (const struct clk_hw *[]) { 2127 &s4_vapb_1_sel.hw 2128 }, 2129 .num_parents = 1, 2130 .flags = CLK_SET_RATE_PARENT, 2131 }, 2132 }; 2133 2134 static struct clk_regmap s4_vapb_1 = { 2135 .data = &(struct clk_regmap_gate_data){ 2136 .offset = CLKCTRL_VAPBCLK_CTRL, 2137 .bit_idx = 24, 2138 }, 2139 .hw.init = &(struct clk_init_data) { 2140 .name = "vapb_1", 2141 .ops = &clk_regmap_gate_ops, 2142 .parent_hws = (const struct clk_hw *[]) { 2143 &s4_vapb_1_div.hw 2144 }, 2145 .num_parents = 1, 2146 .flags = CLK_SET_RATE_PARENT, 2147 }, 2148 }; 2149 2150 static struct clk_regmap s4_vapb = { 2151 .data = &(struct clk_regmap_mux_data){ 2152 .offset = CLKCTRL_VAPBCLK_CTRL, 2153 .mask = 1, 2154 .shift = 31, 2155 }, 2156 .hw.init = &(struct clk_init_data){ 2157 .name = "vapb_sel", 2158 .ops = &clk_regmap_mux_ops, 2159 .parent_hws = (const struct clk_hw *[]) { 2160 &s4_vapb_0.hw, 2161 &s4_vapb_1.hw 2162 }, 2163 .num_parents = 2, 2164 .flags = CLK_SET_RATE_PARENT, 2165 }, 2166 }; 2167 2168 static struct clk_regmap s4_ge2d = { 2169 .data = &(struct clk_regmap_gate_data){ 2170 .offset = CLKCTRL_VAPBCLK_CTRL, 2171 .bit_idx = 30, 2172 }, 2173 .hw.init = &(struct clk_init_data) { 2174 .name = "ge2d", 2175 .ops = &clk_regmap_gate_ops, 2176 .parent_hws = (const struct clk_hw *[]) { &s4_vapb.hw }, 2177 .num_parents = 1, 2178 .flags = CLK_SET_RATE_PARENT, 2179 }, 2180 }; 2181 2182 static const struct clk_parent_data s4_hdcp22_esmclk_parents[] = { 2183 { .fw_name = "fclk_div7", }, 2184 { .fw_name = "fclk_div4", }, 2185 { .fw_name = "fclk_div3", }, 2186 { .fw_name = "fclk_div5", }, 2187 }; 2188 2189 static struct clk_regmap s4_hdcp22_esmclk_sel = { 2190 .data = &(struct clk_regmap_mux_data){ 2191 .offset = CLKCTRL_HDCP22_CTRL, 2192 .mask = 0x3, 2193 .shift = 9, 2194 }, 2195 .hw.init = &(struct clk_init_data) { 2196 .name = "hdcp22_esmclk_sel", 2197 .ops = &clk_regmap_mux_ops, 2198 .parent_data = s4_hdcp22_esmclk_parents, 2199 .num_parents = ARRAY_SIZE(s4_hdcp22_esmclk_parents), 2200 .flags = CLK_SET_RATE_PARENT, 2201 }, 2202 }; 2203 2204 static struct clk_regmap s4_hdcp22_esmclk_div = { 2205 .data = &(struct clk_regmap_div_data){ 2206 .offset = CLKCTRL_HDCP22_CTRL, 2207 .shift = 0, 2208 .width = 7, 2209 }, 2210 .hw.init = &(struct clk_init_data) { 2211 .name = "hdcp22_esmclk_div", 2212 .ops = &clk_regmap_divider_ops, 2213 .parent_hws = (const struct clk_hw *[]) { 2214 &s4_hdcp22_esmclk_sel.hw 2215 }, 2216 .num_parents = 1, 2217 .flags = CLK_SET_RATE_PARENT, 2218 }, 2219 }; 2220 2221 static struct clk_regmap s4_hdcp22_esmclk = { 2222 .data = &(struct clk_regmap_gate_data){ 2223 .offset = CLKCTRL_HDCP22_CTRL, 2224 .bit_idx = 8, 2225 }, 2226 .hw.init = &(struct clk_init_data){ 2227 .name = "hdcp22_esmclk", 2228 .ops = &clk_regmap_gate_ops, 2229 .parent_hws = (const struct clk_hw *[]) { 2230 &s4_hdcp22_esmclk_div.hw 2231 }, 2232 .num_parents = 1, 2233 .flags = CLK_SET_RATE_PARENT, 2234 }, 2235 }; 2236 2237 static const struct clk_parent_data s4_hdcp22_skpclk_parents[] = { 2238 { .fw_name = "xtal", }, 2239 { .fw_name = "fclk_div4", }, 2240 { .fw_name = "fclk_div3", }, 2241 { .fw_name = "fclk_div5", }, 2242 }; 2243 2244 static struct clk_regmap s4_hdcp22_skpclk_sel = { 2245 .data = &(struct clk_regmap_mux_data){ 2246 .offset = CLKCTRL_HDCP22_CTRL, 2247 .mask = 0x3, 2248 .shift = 25, 2249 }, 2250 .hw.init = &(struct clk_init_data) { 2251 .name = "hdcp22_skpclk_sel", 2252 .ops = &clk_regmap_mux_ops, 2253 .parent_data = s4_hdcp22_skpclk_parents, 2254 .num_parents = ARRAY_SIZE(s4_hdcp22_skpclk_parents), 2255 .flags = CLK_SET_RATE_PARENT, 2256 }, 2257 }; 2258 2259 static struct clk_regmap s4_hdcp22_skpclk_div = { 2260 .data = &(struct clk_regmap_div_data){ 2261 .offset = CLKCTRL_HDCP22_CTRL, 2262 .shift = 16, 2263 .width = 7, 2264 }, 2265 .hw.init = &(struct clk_init_data) { 2266 .name = "hdcp22_skpclk_div", 2267 .ops = &clk_regmap_divider_ops, 2268 .parent_hws = (const struct clk_hw *[]) { 2269 &s4_hdcp22_skpclk_sel.hw 2270 }, 2271 .num_parents = 1, 2272 .flags = CLK_SET_RATE_PARENT, 2273 }, 2274 }; 2275 2276 static struct clk_regmap s4_hdcp22_skpclk = { 2277 .data = &(struct clk_regmap_gate_data){ 2278 .offset = CLKCTRL_HDCP22_CTRL, 2279 .bit_idx = 24, 2280 }, 2281 .hw.init = &(struct clk_init_data){ 2282 .name = "hdcp22_skpclk", 2283 .ops = &clk_regmap_gate_ops, 2284 .parent_hws = (const struct clk_hw *[]) { 2285 &s4_hdcp22_skpclk_div.hw 2286 }, 2287 .num_parents = 1, 2288 .flags = CLK_SET_RATE_PARENT, 2289 }, 2290 }; 2291 2292 static const struct clk_parent_data s4_vdin_parents[] = { 2293 { .fw_name = "xtal", }, 2294 { .fw_name = "fclk_div4", }, 2295 { .fw_name = "fclk_div3", }, 2296 { .fw_name = "fclk_div5", }, 2297 { .hw = &s4_vid_pll.hw } 2298 }; 2299 2300 static struct clk_regmap s4_vdin_meas_sel = { 2301 .data = &(struct clk_regmap_mux_data){ 2302 .offset = CLKCTRL_VDIN_MEAS_CLK_CTRL, 2303 .mask = 0x7, 2304 .shift = 9, 2305 }, 2306 .hw.init = &(struct clk_init_data) { 2307 .name = "vdin_meas_sel", 2308 .ops = &clk_regmap_mux_ops, 2309 .parent_data = s4_vdin_parents, 2310 .num_parents = ARRAY_SIZE(s4_vdin_parents), 2311 .flags = CLK_SET_RATE_PARENT, 2312 }, 2313 }; 2314 2315 static struct clk_regmap s4_vdin_meas_div = { 2316 .data = &(struct clk_regmap_div_data){ 2317 .offset = CLKCTRL_VDIN_MEAS_CLK_CTRL, 2318 .shift = 0, 2319 .width = 7, 2320 }, 2321 .hw.init = &(struct clk_init_data) { 2322 .name = "vdin_meas_div", 2323 .ops = &clk_regmap_divider_ops, 2324 .parent_hws = (const struct clk_hw *[]) { 2325 &s4_vdin_meas_sel.hw 2326 }, 2327 .num_parents = 1, 2328 .flags = CLK_SET_RATE_PARENT, 2329 }, 2330 }; 2331 2332 static struct clk_regmap s4_vdin_meas = { 2333 .data = &(struct clk_regmap_gate_data){ 2334 .offset = CLKCTRL_VDIN_MEAS_CLK_CTRL, 2335 .bit_idx = 8, 2336 }, 2337 .hw.init = &(struct clk_init_data){ 2338 .name = "vdin_meas", 2339 .ops = &clk_regmap_gate_ops, 2340 .parent_hws = (const struct clk_hw *[]) { 2341 &s4_vdin_meas_div.hw 2342 }, 2343 .num_parents = 1, 2344 .flags = CLK_SET_RATE_PARENT, 2345 }, 2346 }; 2347 2348 /* EMMC/NAND clock */ 2349 static const struct clk_parent_data s4_sd_emmc_clk0_parents[] = { 2350 { .fw_name = "xtal", }, 2351 { .fw_name = "fclk_div2", }, 2352 { .fw_name = "fclk_div3", }, 2353 { .fw_name = "hifi_pll", }, 2354 { .fw_name = "fclk_div2p5", }, 2355 { .fw_name = "mpll2", }, 2356 { .fw_name = "mpll3", }, 2357 { .fw_name = "gp0_pll", }, 2358 }; 2359 2360 static struct clk_regmap s4_sd_emmc_c_clk0_sel = { 2361 .data = &(struct clk_regmap_mux_data){ 2362 .offset = CLKCTRL_NAND_CLK_CTRL, 2363 .mask = 0x7, 2364 .shift = 9, 2365 }, 2366 .hw.init = &(struct clk_init_data) { 2367 .name = "sd_emmc_c_clk0_sel", 2368 .ops = &clk_regmap_mux_ops, 2369 .parent_data = s4_sd_emmc_clk0_parents, 2370 .num_parents = ARRAY_SIZE(s4_sd_emmc_clk0_parents), 2371 .flags = 0, 2372 }, 2373 }; 2374 2375 static struct clk_regmap s4_sd_emmc_c_clk0_div = { 2376 .data = &(struct clk_regmap_div_data){ 2377 .offset = CLKCTRL_NAND_CLK_CTRL, 2378 .shift = 0, 2379 .width = 7, 2380 }, 2381 .hw.init = &(struct clk_init_data) { 2382 .name = "sd_emmc_c_clk0_div", 2383 .ops = &clk_regmap_divider_ops, 2384 .parent_hws = (const struct clk_hw *[]) { 2385 &s4_sd_emmc_c_clk0_sel.hw 2386 }, 2387 .num_parents = 1, 2388 .flags = CLK_SET_RATE_PARENT, 2389 }, 2390 }; 2391 2392 static struct clk_regmap s4_sd_emmc_c_clk0 = { 2393 .data = &(struct clk_regmap_gate_data){ 2394 .offset = CLKCTRL_NAND_CLK_CTRL, 2395 .bit_idx = 7, 2396 }, 2397 .hw.init = &(struct clk_init_data){ 2398 .name = "sd_emmc_c_clk0", 2399 .ops = &clk_regmap_gate_ops, 2400 .parent_hws = (const struct clk_hw *[]) { 2401 &s4_sd_emmc_c_clk0_div.hw 2402 }, 2403 .num_parents = 1, 2404 .flags = CLK_SET_RATE_PARENT, 2405 }, 2406 }; 2407 2408 static struct clk_regmap s4_sd_emmc_a_clk0_sel = { 2409 .data = &(struct clk_regmap_mux_data){ 2410 .offset = CLKCTRL_SD_EMMC_CLK_CTRL, 2411 .mask = 0x7, 2412 .shift = 9, 2413 }, 2414 .hw.init = &(struct clk_init_data) { 2415 .name = "sd_emmc_a_clk0_sel", 2416 .ops = &clk_regmap_mux_ops, 2417 .parent_data = s4_sd_emmc_clk0_parents, 2418 .num_parents = ARRAY_SIZE(s4_sd_emmc_clk0_parents), 2419 .flags = 0, 2420 }, 2421 }; 2422 2423 static struct clk_regmap s4_sd_emmc_a_clk0_div = { 2424 .data = &(struct clk_regmap_div_data){ 2425 .offset = CLKCTRL_SD_EMMC_CLK_CTRL, 2426 .shift = 0, 2427 .width = 7, 2428 }, 2429 .hw.init = &(struct clk_init_data) { 2430 .name = "sd_emmc_a_clk0_div", 2431 .ops = &clk_regmap_divider_ops, 2432 .parent_hws = (const struct clk_hw *[]) { 2433 &s4_sd_emmc_a_clk0_sel.hw 2434 }, 2435 .num_parents = 1, 2436 .flags = CLK_SET_RATE_PARENT, 2437 }, 2438 }; 2439 2440 static struct clk_regmap s4_sd_emmc_a_clk0 = { 2441 .data = &(struct clk_regmap_gate_data){ 2442 .offset = CLKCTRL_SD_EMMC_CLK_CTRL, 2443 .bit_idx = 7, 2444 }, 2445 .hw.init = &(struct clk_init_data){ 2446 .name = "sd_emmc_a_clk0", 2447 .ops = &clk_regmap_gate_ops, 2448 .parent_hws = (const struct clk_hw *[]) { 2449 &s4_sd_emmc_a_clk0_div.hw 2450 }, 2451 .num_parents = 1, 2452 .flags = CLK_SET_RATE_PARENT, 2453 }, 2454 }; 2455 2456 static struct clk_regmap s4_sd_emmc_b_clk0_sel = { 2457 .data = &(struct clk_regmap_mux_data){ 2458 .offset = CLKCTRL_SD_EMMC_CLK_CTRL, 2459 .mask = 0x7, 2460 .shift = 25, 2461 }, 2462 .hw.init = &(struct clk_init_data) { 2463 .name = "sd_emmc_b_clk0_sel", 2464 .ops = &clk_regmap_mux_ops, 2465 .parent_data = s4_sd_emmc_clk0_parents, 2466 .num_parents = ARRAY_SIZE(s4_sd_emmc_clk0_parents), 2467 .flags = 0, 2468 }, 2469 }; 2470 2471 static struct clk_regmap s4_sd_emmc_b_clk0_div = { 2472 .data = &(struct clk_regmap_div_data){ 2473 .offset = CLKCTRL_SD_EMMC_CLK_CTRL, 2474 .shift = 16, 2475 .width = 7, 2476 }, 2477 .hw.init = &(struct clk_init_data) { 2478 .name = "sd_emmc_b_clk0_div", 2479 .ops = &clk_regmap_divider_ops, 2480 .parent_hws = (const struct clk_hw *[]) { 2481 &s4_sd_emmc_b_clk0_sel.hw 2482 }, 2483 .num_parents = 1, 2484 .flags = CLK_SET_RATE_PARENT, 2485 }, 2486 }; 2487 2488 static struct clk_regmap s4_sd_emmc_b_clk0 = { 2489 .data = &(struct clk_regmap_gate_data){ 2490 .offset = CLKCTRL_SD_EMMC_CLK_CTRL, 2491 .bit_idx = 23, 2492 }, 2493 .hw.init = &(struct clk_init_data){ 2494 .name = "sd_emmc_b_clk0", 2495 .ops = &clk_regmap_gate_ops, 2496 .parent_hws = (const struct clk_hw *[]) { 2497 &s4_sd_emmc_b_clk0_div.hw 2498 }, 2499 .num_parents = 1, 2500 .flags = CLK_SET_RATE_PARENT, 2501 }, 2502 }; 2503 2504 /* SPICC Clock */ 2505 static const struct clk_parent_data s4_spicc_parents[] = { 2506 { .fw_name = "xtal", }, 2507 { .hw = &s4_sys_clk.hw }, 2508 { .fw_name = "fclk_div4", }, 2509 { .fw_name = "fclk_div3", }, 2510 { .fw_name = "fclk_div2", }, 2511 { .fw_name = "fclk_div5", }, 2512 { .fw_name = "fclk_div7", }, 2513 }; 2514 2515 static struct clk_regmap s4_spicc0_sel = { 2516 .data = &(struct clk_regmap_mux_data){ 2517 .offset = CLKCTRL_SPICC_CLK_CTRL, 2518 .mask = 0x7, 2519 .shift = 7, 2520 }, 2521 .hw.init = &(struct clk_init_data) { 2522 .name = "spicc0_sel", 2523 .ops = &clk_regmap_mux_ops, 2524 .parent_data = s4_spicc_parents, 2525 .num_parents = ARRAY_SIZE(s4_spicc_parents), 2526 .flags = CLK_SET_RATE_PARENT, 2527 }, 2528 }; 2529 2530 static struct clk_regmap s4_spicc0_div = { 2531 .data = &(struct clk_regmap_div_data){ 2532 .offset = CLKCTRL_SPICC_CLK_CTRL, 2533 .shift = 0, 2534 .width = 6, 2535 }, 2536 .hw.init = &(struct clk_init_data) { 2537 .name = "spicc0_div", 2538 .ops = &clk_regmap_divider_ops, 2539 .parent_hws = (const struct clk_hw *[]) { 2540 &s4_spicc0_sel.hw 2541 }, 2542 .num_parents = 1, 2543 .flags = CLK_SET_RATE_PARENT, 2544 }, 2545 }; 2546 2547 static struct clk_regmap s4_spicc0_en = { 2548 .data = &(struct clk_regmap_gate_data){ 2549 .offset = CLKCTRL_SPICC_CLK_CTRL, 2550 .bit_idx = 6, 2551 }, 2552 .hw.init = &(struct clk_init_data){ 2553 .name = "spicc0_en", 2554 .ops = &clk_regmap_gate_ops, 2555 .parent_hws = (const struct clk_hw *[]) { 2556 &s4_spicc0_div.hw 2557 }, 2558 .num_parents = 1, 2559 .flags = CLK_SET_RATE_PARENT, 2560 }, 2561 }; 2562 2563 /* PWM Clock */ 2564 static const struct clk_parent_data s4_pwm_parents[] = { 2565 { .fw_name = "xtal", }, 2566 { .hw = &s4_vid_pll.hw }, 2567 { .fw_name = "fclk_div4", }, 2568 { .fw_name = "fclk_div3", }, 2569 }; 2570 2571 static S4_COMP_SEL(pwm_a, CLKCTRL_PWM_CLK_AB_CTRL, 9, 0x3, s4_pwm_parents); 2572 static S4_COMP_DIV(pwm_a, CLKCTRL_PWM_CLK_AB_CTRL, 0, 8); 2573 static S4_COMP_GATE(pwm_a, CLKCTRL_PWM_CLK_AB_CTRL, 8); 2574 2575 static S4_COMP_SEL(pwm_b, CLKCTRL_PWM_CLK_AB_CTRL, 25, 0x3, s4_pwm_parents); 2576 static S4_COMP_DIV(pwm_b, CLKCTRL_PWM_CLK_AB_CTRL, 16, 8); 2577 static S4_COMP_GATE(pwm_b, CLKCTRL_PWM_CLK_AB_CTRL, 24); 2578 2579 static S4_COMP_SEL(pwm_c, CLKCTRL_PWM_CLK_CD_CTRL, 9, 0x3, s4_pwm_parents); 2580 static S4_COMP_DIV(pwm_c, CLKCTRL_PWM_CLK_CD_CTRL, 0, 8); 2581 static S4_COMP_GATE(pwm_c, CLKCTRL_PWM_CLK_CD_CTRL, 8); 2582 2583 static S4_COMP_SEL(pwm_d, CLKCTRL_PWM_CLK_CD_CTRL, 25, 0x3, s4_pwm_parents); 2584 static S4_COMP_DIV(pwm_d, CLKCTRL_PWM_CLK_CD_CTRL, 16, 8); 2585 static S4_COMP_GATE(pwm_d, CLKCTRL_PWM_CLK_CD_CTRL, 24); 2586 2587 static S4_COMP_SEL(pwm_e, CLKCTRL_PWM_CLK_EF_CTRL, 9, 0x3, s4_pwm_parents); 2588 static S4_COMP_DIV(pwm_e, CLKCTRL_PWM_CLK_EF_CTRL, 0, 8); 2589 static S4_COMP_GATE(pwm_e, CLKCTRL_PWM_CLK_EF_CTRL, 8); 2590 2591 static S4_COMP_SEL(pwm_f, CLKCTRL_PWM_CLK_EF_CTRL, 25, 0x3, s4_pwm_parents); 2592 static S4_COMP_DIV(pwm_f, CLKCTRL_PWM_CLK_EF_CTRL, 16, 8); 2593 static S4_COMP_GATE(pwm_f, CLKCTRL_PWM_CLK_EF_CTRL, 24); 2594 2595 static S4_COMP_SEL(pwm_g, CLKCTRL_PWM_CLK_GH_CTRL, 9, 0x3, s4_pwm_parents); 2596 static S4_COMP_DIV(pwm_g, CLKCTRL_PWM_CLK_GH_CTRL, 0, 8); 2597 static S4_COMP_GATE(pwm_g, CLKCTRL_PWM_CLK_GH_CTRL, 8); 2598 2599 static S4_COMP_SEL(pwm_h, CLKCTRL_PWM_CLK_GH_CTRL, 25, 0x3, s4_pwm_parents); 2600 static S4_COMP_DIV(pwm_h, CLKCTRL_PWM_CLK_GH_CTRL, 16, 8); 2601 static S4_COMP_GATE(pwm_h, CLKCTRL_PWM_CLK_GH_CTRL, 24); 2602 2603 static S4_COMP_SEL(pwm_i, CLKCTRL_PWM_CLK_IJ_CTRL, 9, 0x3, s4_pwm_parents); 2604 static S4_COMP_DIV(pwm_i, CLKCTRL_PWM_CLK_IJ_CTRL, 0, 8); 2605 static S4_COMP_GATE(pwm_i, CLKCTRL_PWM_CLK_IJ_CTRL, 8); 2606 2607 static S4_COMP_SEL(pwm_j, CLKCTRL_PWM_CLK_IJ_CTRL, 25, 0x3, s4_pwm_parents); 2608 static S4_COMP_DIV(pwm_j, CLKCTRL_PWM_CLK_IJ_CTRL, 16, 8); 2609 static S4_COMP_GATE(pwm_j, CLKCTRL_PWM_CLK_IJ_CTRL, 24); 2610 2611 static struct clk_regmap s4_saradc_sel = { 2612 .data = &(struct clk_regmap_mux_data) { 2613 .offset = CLKCTRL_SAR_CLK_CTRL, 2614 .mask = 0x3, 2615 .shift = 9, 2616 }, 2617 .hw.init = &(struct clk_init_data){ 2618 .name = "saradc_sel", 2619 .ops = &clk_regmap_mux_ops, 2620 .parent_data = (const struct clk_parent_data []) { 2621 { .fw_name = "xtal", }, 2622 { .hw = &s4_sys_clk.hw }, 2623 }, 2624 .num_parents = 2, 2625 .flags = CLK_SET_RATE_PARENT, 2626 }, 2627 }; 2628 2629 static struct clk_regmap s4_saradc_div = { 2630 .data = &(struct clk_regmap_div_data) { 2631 .offset = CLKCTRL_SAR_CLK_CTRL, 2632 .shift = 0, 2633 .width = 8, 2634 }, 2635 .hw.init = &(struct clk_init_data){ 2636 .name = "saradc_div", 2637 .ops = &clk_regmap_divider_ops, 2638 .parent_hws = (const struct clk_hw *[]) { 2639 &s4_saradc_sel.hw 2640 }, 2641 .num_parents = 1, 2642 .flags = CLK_SET_RATE_PARENT, 2643 }, 2644 }; 2645 2646 static struct clk_regmap s4_saradc = { 2647 .data = &(struct clk_regmap_gate_data) { 2648 .offset = CLKCTRL_SAR_CLK_CTRL, 2649 .bit_idx = 8, 2650 }, 2651 .hw.init = &(struct clk_init_data){ 2652 .name = "saradc", 2653 .ops = &clk_regmap_gate_ops, 2654 .parent_hws = (const struct clk_hw *[]) { 2655 &s4_saradc_div.hw 2656 }, 2657 .num_parents = 1, 2658 .flags = CLK_SET_RATE_PARENT, 2659 }, 2660 }; 2661 2662 /* 2663 * gen clk is designed for debug/monitor some internal clock quality. Some of the 2664 * corresponding clock sources are not described in the clock tree and internal clock 2665 * for debug, so they are skipped. 2666 */ 2667 static u32 s4_gen_clk_parents_val_table[] = { 0, 4, 5, 7, 19, 21, 22, 23, 24, 25, 26, 27, 28 }; 2668 static const struct clk_parent_data s4_gen_clk_parents[] = { 2669 { .fw_name = "xtal", }, 2670 { .hw = &s4_vid_pll.hw }, 2671 { .fw_name = "gp0_pll", }, 2672 { .fw_name = "hifi_pll", }, 2673 { .fw_name = "fclk_div2", }, 2674 { .fw_name = "fclk_div3", }, 2675 { .fw_name = "fclk_div4", }, 2676 { .fw_name = "fclk_div5", }, 2677 { .fw_name = "fclk_div7", }, 2678 { .fw_name = "mpll0", }, 2679 { .fw_name = "mpll1", }, 2680 { .fw_name = "mpll2", }, 2681 { .fw_name = "mpll3", }, 2682 }; 2683 2684 static struct clk_regmap s4_gen_clk_sel = { 2685 .data = &(struct clk_regmap_mux_data){ 2686 .offset = CLKCTRL_GEN_CLK_CTRL, 2687 .mask = 0x1f, 2688 .shift = 12, 2689 .table = s4_gen_clk_parents_val_table, 2690 }, 2691 .hw.init = &(struct clk_init_data){ 2692 .name = "gen_clk_sel", 2693 .ops = &clk_regmap_mux_ops, 2694 .parent_data = s4_gen_clk_parents, 2695 .num_parents = ARRAY_SIZE(s4_gen_clk_parents), 2696 /* 2697 * Because the GEN clock can be connected to an external pad 2698 * and may be set up directly from the device tree. Don't 2699 * really want to automatically reparent. 2700 */ 2701 .flags = CLK_SET_RATE_NO_REPARENT, 2702 }, 2703 }; 2704 2705 static struct clk_regmap s4_gen_clk_div = { 2706 .data = &(struct clk_regmap_div_data){ 2707 .offset = CLKCTRL_GEN_CLK_CTRL, 2708 .shift = 0, 2709 .width = 11, 2710 }, 2711 .hw.init = &(struct clk_init_data){ 2712 .name = "gen_clk_div", 2713 .ops = &clk_regmap_divider_ops, 2714 .parent_hws = (const struct clk_hw *[]) { 2715 &s4_gen_clk_sel.hw 2716 }, 2717 .num_parents = 1, 2718 .flags = CLK_SET_RATE_PARENT, 2719 }, 2720 }; 2721 2722 static struct clk_regmap s4_gen_clk = { 2723 .data = &(struct clk_regmap_gate_data){ 2724 .offset = CLKCTRL_GEN_CLK_CTRL, 2725 .bit_idx = 11, 2726 }, 2727 .hw.init = &(struct clk_init_data) { 2728 .name = "gen_clk", 2729 .ops = &clk_regmap_gate_ops, 2730 .parent_hws = (const struct clk_hw *[]) { 2731 &s4_gen_clk_div.hw 2732 }, 2733 .num_parents = 1, 2734 .flags = CLK_SET_RATE_PARENT, 2735 }, 2736 }; 2737 2738 static const struct clk_parent_data s4_pclk_parents = { .hw = &s4_sys_clk.hw }; 2739 2740 #define S4_PCLK(_name, _reg, _bit, _flags) \ 2741 MESON_PCLK(_name, _reg, _bit, &s4_pclk_parents, _flags) 2742 2743 /* 2744 * NOTE: The gates below are marked with CLK_IGNORE_UNUSED for historic reasons 2745 * Users are encouraged to test without it and submit changes to: 2746 * - remove the flag if not necessary 2747 * - replace the flag with something more adequate, such as CLK_IS_CRITICAL, 2748 * if appropriate. 2749 * - add a comment explaining why the use of CLK_IGNORE_UNUSED is desirable 2750 * for a particular clock. 2751 */ 2752 static S4_PCLK(s4_ddr, CLKCTRL_SYS_CLK_EN0_REG0, 0, CLK_IGNORE_UNUSED); 2753 static S4_PCLK(s4_dos, CLKCTRL_SYS_CLK_EN0_REG0, 1, CLK_IGNORE_UNUSED); 2754 static S4_PCLK(s4_ethphy, CLKCTRL_SYS_CLK_EN0_REG0, 4, CLK_IGNORE_UNUSED); 2755 static S4_PCLK(s4_mali, CLKCTRL_SYS_CLK_EN0_REG0, 6, CLK_IGNORE_UNUSED); 2756 static S4_PCLK(s4_aocpu, CLKCTRL_SYS_CLK_EN0_REG0, 13, CLK_IGNORE_UNUSED); 2757 static S4_PCLK(s4_aucpu, CLKCTRL_SYS_CLK_EN0_REG0, 14, CLK_IGNORE_UNUSED); 2758 static S4_PCLK(s4_cec, CLKCTRL_SYS_CLK_EN0_REG0, 16, CLK_IGNORE_UNUSED); 2759 static S4_PCLK(s4_sdemmca, CLKCTRL_SYS_CLK_EN0_REG0, 24, CLK_IGNORE_UNUSED); 2760 static S4_PCLK(s4_sdemmcb, CLKCTRL_SYS_CLK_EN0_REG0, 25, CLK_IGNORE_UNUSED); 2761 static S4_PCLK(s4_nand, CLKCTRL_SYS_CLK_EN0_REG0, 26, CLK_IGNORE_UNUSED); 2762 static S4_PCLK(s4_smartcard, CLKCTRL_SYS_CLK_EN0_REG0, 27, CLK_IGNORE_UNUSED); 2763 static S4_PCLK(s4_acodec, CLKCTRL_SYS_CLK_EN0_REG0, 28, CLK_IGNORE_UNUSED); 2764 static S4_PCLK(s4_spifc, CLKCTRL_SYS_CLK_EN0_REG0, 29, CLK_IGNORE_UNUSED); 2765 static S4_PCLK(s4_msr_clk, CLKCTRL_SYS_CLK_EN0_REG0, 30, CLK_IGNORE_UNUSED); 2766 static S4_PCLK(s4_ir_ctrl, CLKCTRL_SYS_CLK_EN0_REG0, 31, CLK_IGNORE_UNUSED); 2767 2768 static S4_PCLK(s4_audio, CLKCTRL_SYS_CLK_EN0_REG1, 0, CLK_IGNORE_UNUSED); 2769 static S4_PCLK(s4_eth, CLKCTRL_SYS_CLK_EN0_REG1, 3, CLK_IGNORE_UNUSED); 2770 static S4_PCLK(s4_uart_a, CLKCTRL_SYS_CLK_EN0_REG1, 5, CLK_IGNORE_UNUSED); 2771 static S4_PCLK(s4_uart_b, CLKCTRL_SYS_CLK_EN0_REG1, 6, CLK_IGNORE_UNUSED); 2772 static S4_PCLK(s4_uart_c, CLKCTRL_SYS_CLK_EN0_REG1, 7, CLK_IGNORE_UNUSED); 2773 static S4_PCLK(s4_uart_d, CLKCTRL_SYS_CLK_EN0_REG1, 8, CLK_IGNORE_UNUSED); 2774 static S4_PCLK(s4_uart_e, CLKCTRL_SYS_CLK_EN0_REG1, 9, CLK_IGNORE_UNUSED); 2775 static S4_PCLK(s4_aififo, CLKCTRL_SYS_CLK_EN0_REG1, 11, CLK_IGNORE_UNUSED); 2776 static S4_PCLK(s4_ts_ddr, CLKCTRL_SYS_CLK_EN0_REG1, 15, CLK_IGNORE_UNUSED); 2777 static S4_PCLK(s4_ts_pll, CLKCTRL_SYS_CLK_EN0_REG1, 16, CLK_IGNORE_UNUSED); 2778 static S4_PCLK(s4_g2d, CLKCTRL_SYS_CLK_EN0_REG1, 20, CLK_IGNORE_UNUSED); 2779 static S4_PCLK(s4_spicc0, CLKCTRL_SYS_CLK_EN0_REG1, 21, CLK_IGNORE_UNUSED); 2780 static S4_PCLK(s4_usb, CLKCTRL_SYS_CLK_EN0_REG1, 26, CLK_IGNORE_UNUSED); 2781 static S4_PCLK(s4_i2c_m_a, CLKCTRL_SYS_CLK_EN0_REG1, 30, CLK_IGNORE_UNUSED); 2782 static S4_PCLK(s4_i2c_m_b, CLKCTRL_SYS_CLK_EN0_REG1, 31, CLK_IGNORE_UNUSED); 2783 2784 static S4_PCLK(s4_i2c_m_c, CLKCTRL_SYS_CLK_EN0_REG2, 0, CLK_IGNORE_UNUSED); 2785 static S4_PCLK(s4_i2c_m_d, CLKCTRL_SYS_CLK_EN0_REG2, 1, CLK_IGNORE_UNUSED); 2786 static S4_PCLK(s4_i2c_m_e, CLKCTRL_SYS_CLK_EN0_REG2, 2, CLK_IGNORE_UNUSED); 2787 static S4_PCLK(s4_hdmitx_apb, CLKCTRL_SYS_CLK_EN0_REG2, 4, CLK_IGNORE_UNUSED); 2788 static S4_PCLK(s4_i2c_s_a, CLKCTRL_SYS_CLK_EN0_REG2, 5, CLK_IGNORE_UNUSED); 2789 static S4_PCLK(s4_usb1_to_ddr, CLKCTRL_SYS_CLK_EN0_REG2, 8, CLK_IGNORE_UNUSED); 2790 static S4_PCLK(s4_hdcp22, CLKCTRL_SYS_CLK_EN0_REG2, 10, CLK_IGNORE_UNUSED); 2791 static S4_PCLK(s4_mmc_apb, CLKCTRL_SYS_CLK_EN0_REG2, 11, CLK_IGNORE_UNUSED); 2792 static S4_PCLK(s4_rsa, CLKCTRL_SYS_CLK_EN0_REG2, 18, CLK_IGNORE_UNUSED); 2793 static S4_PCLK(s4_cpu_debug, CLKCTRL_SYS_CLK_EN0_REG2, 19, CLK_IGNORE_UNUSED); 2794 static S4_PCLK(s4_vpu_intr, CLKCTRL_SYS_CLK_EN0_REG2, 25, CLK_IGNORE_UNUSED); 2795 static S4_PCLK(s4_demod, CLKCTRL_SYS_CLK_EN0_REG2, 27, CLK_IGNORE_UNUSED); 2796 static S4_PCLK(s4_sar_adc, CLKCTRL_SYS_CLK_EN0_REG2, 28, CLK_IGNORE_UNUSED); 2797 static S4_PCLK(s4_gic, CLKCTRL_SYS_CLK_EN0_REG2, 30, CLK_IGNORE_UNUSED); 2798 2799 static S4_PCLK(s4_pwm_ab, CLKCTRL_SYS_CLK_EN0_REG3, 7, CLK_IGNORE_UNUSED); 2800 static S4_PCLK(s4_pwm_cd, CLKCTRL_SYS_CLK_EN0_REG3, 8, CLK_IGNORE_UNUSED); 2801 static S4_PCLK(s4_pwm_ef, CLKCTRL_SYS_CLK_EN0_REG3, 9, CLK_IGNORE_UNUSED); 2802 static S4_PCLK(s4_pwm_gh, CLKCTRL_SYS_CLK_EN0_REG3, 10, CLK_IGNORE_UNUSED); 2803 static S4_PCLK(s4_pwm_ij, CLKCTRL_SYS_CLK_EN0_REG3, 11, CLK_IGNORE_UNUSED); 2804 2805 /* Array of all clocks provided by this provider */ 2806 static struct clk_hw *s4_peripherals_hw_clks[] = { 2807 [CLKID_RTC_32K_CLKIN] = &s4_rtc_32k_by_oscin_clkin.hw, 2808 [CLKID_RTC_32K_DIV] = &s4_rtc_32k_by_oscin_div.hw, 2809 [CLKID_RTC_32K_SEL] = &s4_rtc_32k_by_oscin_sel.hw, 2810 [CLKID_RTC_32K_XATL] = &s4_rtc_32k_by_oscin.hw, 2811 [CLKID_RTC] = &s4_rtc_clk.hw, 2812 [CLKID_SYS_CLK_B_SEL] = &s4_sysclk_b_sel.hw, 2813 [CLKID_SYS_CLK_B_DIV] = &s4_sysclk_b_div.hw, 2814 [CLKID_SYS_CLK_B] = &s4_sysclk_b.hw, 2815 [CLKID_SYS_CLK_A_SEL] = &s4_sysclk_a_sel.hw, 2816 [CLKID_SYS_CLK_A_DIV] = &s4_sysclk_a_div.hw, 2817 [CLKID_SYS_CLK_A] = &s4_sysclk_a.hw, 2818 [CLKID_SYS] = &s4_sys_clk.hw, 2819 [CLKID_CECA_32K_CLKIN] = &s4_ceca_32k_clkin.hw, 2820 [CLKID_CECA_32K_DIV] = &s4_ceca_32k_div.hw, 2821 [CLKID_CECA_32K_SEL_PRE] = &s4_ceca_32k_sel_pre.hw, 2822 [CLKID_CECA_32K_SEL] = &s4_ceca_32k_sel.hw, 2823 [CLKID_CECA_32K_CLKOUT] = &s4_ceca_32k_clkout.hw, 2824 [CLKID_CECB_32K_CLKIN] = &s4_cecb_32k_clkin.hw, 2825 [CLKID_CECB_32K_DIV] = &s4_cecb_32k_div.hw, 2826 [CLKID_CECB_32K_SEL_PRE] = &s4_cecb_32k_sel_pre.hw, 2827 [CLKID_CECB_32K_SEL] = &s4_cecb_32k_sel.hw, 2828 [CLKID_CECB_32K_CLKOUT] = &s4_cecb_32k_clkout.hw, 2829 [CLKID_SC_CLK_SEL] = &s4_sc_clk_sel.hw, 2830 [CLKID_SC_CLK_DIV] = &s4_sc_clk_div.hw, 2831 [CLKID_SC] = &s4_sc_clk.hw, 2832 [CLKID_12_24M] = &s4_12_24M.hw, 2833 [CLKID_12M_CLK_DIV] = &s4_12M_div.hw, 2834 [CLKID_12_24M_CLK_SEL] = &s4_12_24M_sel.hw, 2835 [CLKID_VID_PLL_DIV] = &s4_vid_pll_div.hw, 2836 [CLKID_VID_PLL_SEL] = &s4_vid_pll_sel.hw, 2837 [CLKID_VID_PLL] = &s4_vid_pll.hw, 2838 [CLKID_VCLK_SEL] = &s4_vclk_sel.hw, 2839 [CLKID_VCLK2_SEL] = &s4_vclk2_sel.hw, 2840 [CLKID_VCLK_INPUT] = &s4_vclk_input.hw, 2841 [CLKID_VCLK2_INPUT] = &s4_vclk2_input.hw, 2842 [CLKID_VCLK_DIV] = &s4_vclk_div.hw, 2843 [CLKID_VCLK2_DIV] = &s4_vclk2_div.hw, 2844 [CLKID_VCLK] = &s4_vclk.hw, 2845 [CLKID_VCLK2] = &s4_vclk2.hw, 2846 [CLKID_VCLK_DIV1] = &s4_vclk_div1.hw, 2847 [CLKID_VCLK_DIV2_EN] = &s4_vclk_div2_en.hw, 2848 [CLKID_VCLK_DIV4_EN] = &s4_vclk_div4_en.hw, 2849 [CLKID_VCLK_DIV6_EN] = &s4_vclk_div6_en.hw, 2850 [CLKID_VCLK_DIV12_EN] = &s4_vclk_div12_en.hw, 2851 [CLKID_VCLK2_DIV1] = &s4_vclk2_div1.hw, 2852 [CLKID_VCLK2_DIV2_EN] = &s4_vclk2_div2_en.hw, 2853 [CLKID_VCLK2_DIV4_EN] = &s4_vclk2_div4_en.hw, 2854 [CLKID_VCLK2_DIV6_EN] = &s4_vclk2_div6_en.hw, 2855 [CLKID_VCLK2_DIV12_EN] = &s4_vclk2_div12_en.hw, 2856 [CLKID_VCLK_DIV2] = &s4_vclk_div2.hw, 2857 [CLKID_VCLK_DIV4] = &s4_vclk_div4.hw, 2858 [CLKID_VCLK_DIV6] = &s4_vclk_div6.hw, 2859 [CLKID_VCLK_DIV12] = &s4_vclk_div12.hw, 2860 [CLKID_VCLK2_DIV2] = &s4_vclk2_div2.hw, 2861 [CLKID_VCLK2_DIV4] = &s4_vclk2_div4.hw, 2862 [CLKID_VCLK2_DIV6] = &s4_vclk2_div6.hw, 2863 [CLKID_VCLK2_DIV12] = &s4_vclk2_div12.hw, 2864 [CLKID_CTS_ENCI_SEL] = &s4_cts_enci_sel.hw, 2865 [CLKID_CTS_ENCP_SEL] = &s4_cts_encp_sel.hw, 2866 [CLKID_CTS_VDAC_SEL] = &s4_cts_vdac_sel.hw, 2867 [CLKID_HDMI_TX_SEL] = &s4_hdmi_tx_sel.hw, 2868 [CLKID_CTS_ENCI] = &s4_cts_enci.hw, 2869 [CLKID_CTS_ENCP] = &s4_cts_encp.hw, 2870 [CLKID_CTS_VDAC] = &s4_cts_vdac.hw, 2871 [CLKID_HDMI_TX] = &s4_hdmi_tx.hw, 2872 [CLKID_HDMI_SEL] = &s4_hdmi_sel.hw, 2873 [CLKID_HDMI_DIV] = &s4_hdmi_div.hw, 2874 [CLKID_HDMI] = &s4_hdmi.hw, 2875 [CLKID_TS_CLK_DIV] = &s4_ts_clk_div.hw, 2876 [CLKID_TS] = &s4_ts_clk.hw, 2877 [CLKID_MALI_0_SEL] = &s4_mali_0_sel.hw, 2878 [CLKID_MALI_0_DIV] = &s4_mali_0_div.hw, 2879 [CLKID_MALI_0] = &s4_mali_0.hw, 2880 [CLKID_MALI_1_SEL] = &s4_mali_1_sel.hw, 2881 [CLKID_MALI_1_DIV] = &s4_mali_1_div.hw, 2882 [CLKID_MALI_1] = &s4_mali_1.hw, 2883 [CLKID_MALI_SEL] = &s4_mali_sel.hw, 2884 [CLKID_VDEC_P0_SEL] = &s4_vdec_p0_sel.hw, 2885 [CLKID_VDEC_P0_DIV] = &s4_vdec_p0_div.hw, 2886 [CLKID_VDEC_P0] = &s4_vdec_p0.hw, 2887 [CLKID_VDEC_P1_SEL] = &s4_vdec_p1_sel.hw, 2888 [CLKID_VDEC_P1_DIV] = &s4_vdec_p1_div.hw, 2889 [CLKID_VDEC_P1] = &s4_vdec_p1.hw, 2890 [CLKID_VDEC_SEL] = &s4_vdec_sel.hw, 2891 [CLKID_HEVCF_P0_SEL] = &s4_hevcf_p0_sel.hw, 2892 [CLKID_HEVCF_P0_DIV] = &s4_hevcf_p0_div.hw, 2893 [CLKID_HEVCF_P0] = &s4_hevcf_p0.hw, 2894 [CLKID_HEVCF_P1_SEL] = &s4_hevcf_p1_sel.hw, 2895 [CLKID_HEVCF_P1_DIV] = &s4_hevcf_p1_div.hw, 2896 [CLKID_HEVCF_P1] = &s4_hevcf_p1.hw, 2897 [CLKID_HEVCF_SEL] = &s4_hevcf_sel.hw, 2898 [CLKID_VPU_0_SEL] = &s4_vpu_0_sel.hw, 2899 [CLKID_VPU_0_DIV] = &s4_vpu_0_div.hw, 2900 [CLKID_VPU_0] = &s4_vpu_0.hw, 2901 [CLKID_VPU_1_SEL] = &s4_vpu_1_sel.hw, 2902 [CLKID_VPU_1_DIV] = &s4_vpu_1_div.hw, 2903 [CLKID_VPU_1] = &s4_vpu_1.hw, 2904 [CLKID_VPU] = &s4_vpu.hw, 2905 [CLKID_VPU_CLKB_TMP_SEL] = &s4_vpu_clkb_tmp_sel.hw, 2906 [CLKID_VPU_CLKB_TMP_DIV] = &s4_vpu_clkb_tmp_div.hw, 2907 [CLKID_VPU_CLKB_TMP] = &s4_vpu_clkb_tmp.hw, 2908 [CLKID_VPU_CLKB_DIV] = &s4_vpu_clkb_div.hw, 2909 [CLKID_VPU_CLKB] = &s4_vpu_clkb.hw, 2910 [CLKID_VPU_CLKC_P0_SEL] = &s4_vpu_clkc_p0_sel.hw, 2911 [CLKID_VPU_CLKC_P0_DIV] = &s4_vpu_clkc_p0_div.hw, 2912 [CLKID_VPU_CLKC_P0] = &s4_vpu_clkc_p0.hw, 2913 [CLKID_VPU_CLKC_P1_SEL] = &s4_vpu_clkc_p1_sel.hw, 2914 [CLKID_VPU_CLKC_P1_DIV] = &s4_vpu_clkc_p1_div.hw, 2915 [CLKID_VPU_CLKC_P1] = &s4_vpu_clkc_p1.hw, 2916 [CLKID_VPU_CLKC_SEL] = &s4_vpu_clkc_sel.hw, 2917 [CLKID_VAPB_0_SEL] = &s4_vapb_0_sel.hw, 2918 [CLKID_VAPB_0_DIV] = &s4_vapb_0_div.hw, 2919 [CLKID_VAPB_0] = &s4_vapb_0.hw, 2920 [CLKID_VAPB_1_SEL] = &s4_vapb_1_sel.hw, 2921 [CLKID_VAPB_1_DIV] = &s4_vapb_1_div.hw, 2922 [CLKID_VAPB_1] = &s4_vapb_1.hw, 2923 [CLKID_VAPB] = &s4_vapb.hw, 2924 [CLKID_GE2D] = &s4_ge2d.hw, 2925 [CLKID_VDIN_MEAS_SEL] = &s4_vdin_meas_sel.hw, 2926 [CLKID_VDIN_MEAS_DIV] = &s4_vdin_meas_div.hw, 2927 [CLKID_VDIN_MEAS] = &s4_vdin_meas.hw, 2928 [CLKID_SD_EMMC_C_CLK_SEL] = &s4_sd_emmc_c_clk0_sel.hw, 2929 [CLKID_SD_EMMC_C_CLK_DIV] = &s4_sd_emmc_c_clk0_div.hw, 2930 [CLKID_SD_EMMC_C] = &s4_sd_emmc_c_clk0.hw, 2931 [CLKID_SD_EMMC_A_CLK_SEL] = &s4_sd_emmc_a_clk0_sel.hw, 2932 [CLKID_SD_EMMC_A_CLK_DIV] = &s4_sd_emmc_a_clk0_div.hw, 2933 [CLKID_SD_EMMC_A] = &s4_sd_emmc_a_clk0.hw, 2934 [CLKID_SD_EMMC_B_CLK_SEL] = &s4_sd_emmc_b_clk0_sel.hw, 2935 [CLKID_SD_EMMC_B_CLK_DIV] = &s4_sd_emmc_b_clk0_div.hw, 2936 [CLKID_SD_EMMC_B] = &s4_sd_emmc_b_clk0.hw, 2937 [CLKID_SPICC0_SEL] = &s4_spicc0_sel.hw, 2938 [CLKID_SPICC0_DIV] = &s4_spicc0_div.hw, 2939 [CLKID_SPICC0_EN] = &s4_spicc0_en.hw, 2940 [CLKID_PWM_A_SEL] = &s4_pwm_a_sel.hw, 2941 [CLKID_PWM_A_DIV] = &s4_pwm_a_div.hw, 2942 [CLKID_PWM_A] = &s4_pwm_a.hw, 2943 [CLKID_PWM_B_SEL] = &s4_pwm_b_sel.hw, 2944 [CLKID_PWM_B_DIV] = &s4_pwm_b_div.hw, 2945 [CLKID_PWM_B] = &s4_pwm_b.hw, 2946 [CLKID_PWM_C_SEL] = &s4_pwm_c_sel.hw, 2947 [CLKID_PWM_C_DIV] = &s4_pwm_c_div.hw, 2948 [CLKID_PWM_C] = &s4_pwm_c.hw, 2949 [CLKID_PWM_D_SEL] = &s4_pwm_d_sel.hw, 2950 [CLKID_PWM_D_DIV] = &s4_pwm_d_div.hw, 2951 [CLKID_PWM_D] = &s4_pwm_d.hw, 2952 [CLKID_PWM_E_SEL] = &s4_pwm_e_sel.hw, 2953 [CLKID_PWM_E_DIV] = &s4_pwm_e_div.hw, 2954 [CLKID_PWM_E] = &s4_pwm_e.hw, 2955 [CLKID_PWM_F_SEL] = &s4_pwm_f_sel.hw, 2956 [CLKID_PWM_F_DIV] = &s4_pwm_f_div.hw, 2957 [CLKID_PWM_F] = &s4_pwm_f.hw, 2958 [CLKID_PWM_G_SEL] = &s4_pwm_g_sel.hw, 2959 [CLKID_PWM_G_DIV] = &s4_pwm_g_div.hw, 2960 [CLKID_PWM_G] = &s4_pwm_g.hw, 2961 [CLKID_PWM_H_SEL] = &s4_pwm_h_sel.hw, 2962 [CLKID_PWM_H_DIV] = &s4_pwm_h_div.hw, 2963 [CLKID_PWM_H] = &s4_pwm_h.hw, 2964 [CLKID_PWM_I_SEL] = &s4_pwm_i_sel.hw, 2965 [CLKID_PWM_I_DIV] = &s4_pwm_i_div.hw, 2966 [CLKID_PWM_I] = &s4_pwm_i.hw, 2967 [CLKID_PWM_J_SEL] = &s4_pwm_j_sel.hw, 2968 [CLKID_PWM_J_DIV] = &s4_pwm_j_div.hw, 2969 [CLKID_PWM_J] = &s4_pwm_j.hw, 2970 [CLKID_SARADC_SEL] = &s4_saradc_sel.hw, 2971 [CLKID_SARADC_DIV] = &s4_saradc_div.hw, 2972 [CLKID_SARADC] = &s4_saradc.hw, 2973 [CLKID_GEN_SEL] = &s4_gen_clk_sel.hw, 2974 [CLKID_GEN_DIV] = &s4_gen_clk_div.hw, 2975 [CLKID_GEN] = &s4_gen_clk.hw, 2976 [CLKID_DDR] = &s4_ddr.hw, 2977 [CLKID_DOS] = &s4_dos.hw, 2978 [CLKID_ETHPHY] = &s4_ethphy.hw, 2979 [CLKID_MALI] = &s4_mali.hw, 2980 [CLKID_AOCPU] = &s4_aocpu.hw, 2981 [CLKID_AUCPU] = &s4_aucpu.hw, 2982 [CLKID_CEC] = &s4_cec.hw, 2983 [CLKID_SDEMMC_A] = &s4_sdemmca.hw, 2984 [CLKID_SDEMMC_B] = &s4_sdemmcb.hw, 2985 [CLKID_NAND] = &s4_nand.hw, 2986 [CLKID_SMARTCARD] = &s4_smartcard.hw, 2987 [CLKID_ACODEC] = &s4_acodec.hw, 2988 [CLKID_SPIFC] = &s4_spifc.hw, 2989 [CLKID_MSR] = &s4_msr_clk.hw, 2990 [CLKID_IR_CTRL] = &s4_ir_ctrl.hw, 2991 [CLKID_AUDIO] = &s4_audio.hw, 2992 [CLKID_ETH] = &s4_eth.hw, 2993 [CLKID_UART_A] = &s4_uart_a.hw, 2994 [CLKID_UART_B] = &s4_uart_b.hw, 2995 [CLKID_UART_C] = &s4_uart_c.hw, 2996 [CLKID_UART_D] = &s4_uart_d.hw, 2997 [CLKID_UART_E] = &s4_uart_e.hw, 2998 [CLKID_AIFIFO] = &s4_aififo.hw, 2999 [CLKID_TS_DDR] = &s4_ts_ddr.hw, 3000 [CLKID_TS_PLL] = &s4_ts_pll.hw, 3001 [CLKID_G2D] = &s4_g2d.hw, 3002 [CLKID_SPICC0] = &s4_spicc0.hw, 3003 [CLKID_USB] = &s4_usb.hw, 3004 [CLKID_I2C_M_A] = &s4_i2c_m_a.hw, 3005 [CLKID_I2C_M_B] = &s4_i2c_m_b.hw, 3006 [CLKID_I2C_M_C] = &s4_i2c_m_c.hw, 3007 [CLKID_I2C_M_D] = &s4_i2c_m_d.hw, 3008 [CLKID_I2C_M_E] = &s4_i2c_m_e.hw, 3009 [CLKID_HDMITX_APB] = &s4_hdmitx_apb.hw, 3010 [CLKID_I2C_S_A] = &s4_i2c_s_a.hw, 3011 [CLKID_USB1_TO_DDR] = &s4_usb1_to_ddr.hw, 3012 [CLKID_HDCP22] = &s4_hdcp22.hw, 3013 [CLKID_MMC_APB] = &s4_mmc_apb.hw, 3014 [CLKID_RSA] = &s4_rsa.hw, 3015 [CLKID_CPU_DEBUG] = &s4_cpu_debug.hw, 3016 [CLKID_VPU_INTR] = &s4_vpu_intr.hw, 3017 [CLKID_DEMOD] = &s4_demod.hw, 3018 [CLKID_SAR_ADC] = &s4_sar_adc.hw, 3019 [CLKID_GIC] = &s4_gic.hw, 3020 [CLKID_PWM_AB] = &s4_pwm_ab.hw, 3021 [CLKID_PWM_CD] = &s4_pwm_cd.hw, 3022 [CLKID_PWM_EF] = &s4_pwm_ef.hw, 3023 [CLKID_PWM_GH] = &s4_pwm_gh.hw, 3024 [CLKID_PWM_IJ] = &s4_pwm_ij.hw, 3025 [CLKID_HDCP22_ESMCLK_SEL] = &s4_hdcp22_esmclk_sel.hw, 3026 [CLKID_HDCP22_ESMCLK_DIV] = &s4_hdcp22_esmclk_div.hw, 3027 [CLKID_HDCP22_ESMCLK] = &s4_hdcp22_esmclk.hw, 3028 [CLKID_HDCP22_SKPCLK_SEL] = &s4_hdcp22_skpclk_sel.hw, 3029 [CLKID_HDCP22_SKPCLK_DIV] = &s4_hdcp22_skpclk_div.hw, 3030 [CLKID_HDCP22_SKPCLK] = &s4_hdcp22_skpclk.hw, 3031 }; 3032 3033 static const struct meson_clkc_data s4_peripherals_clkc_data = { 3034 .hw_clks = { 3035 .hws = s4_peripherals_hw_clks, 3036 .num = ARRAY_SIZE(s4_peripherals_hw_clks), 3037 }, 3038 }; 3039 3040 static const struct of_device_id s4_peripherals_clkc_match_table[] = { 3041 { 3042 .compatible = "amlogic,s4-peripherals-clkc", 3043 .data = &s4_peripherals_clkc_data, 3044 }, 3045 {} 3046 }; 3047 MODULE_DEVICE_TABLE(of, s4_peripherals_clkc_match_table); 3048 3049 static struct platform_driver s4_peripherals_clkc_driver = { 3050 .probe = meson_clkc_mmio_probe, 3051 .driver = { 3052 .name = "s4-peripherals-clkc", 3053 .of_match_table = s4_peripherals_clkc_match_table, 3054 }, 3055 }; 3056 module_platform_driver(s4_peripherals_clkc_driver); 3057 3058 MODULE_DESCRIPTION("Amlogic S4 Peripherals Clock Controller driver"); 3059 MODULE_AUTHOR("Yu Tu <yu.tu@amlogic.com>"); 3060 MODULE_LICENSE("GPL"); 3061 MODULE_IMPORT_NS("CLK_MESON"); 3062