1 /*
2 * linux/drivers/video/s3fb.c -- Frame buffer device driver for S3 Trio/Virge
3 *
4 * Copyright (c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive for
8 * more details.
9 *
10 * Code is based on David Boucher's viafb (http://davesdomain.org.uk/viafb/)
11 * which is based on the code of neofb.
12 */
13
14 #include <linux/aperture.h>
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/errno.h>
18 #include <linux/string.h>
19 #include <linux/mm.h>
20 #include <linux/tty.h>
21 #include <linux/delay.h>
22 #include <linux/fb.h>
23 #include <linux/svga.h>
24 #include <linux/init.h>
25 #include <linux/pci.h>
26 #include <linux/console.h> /* Why should fb driver call console functions? because console_lock() */
27 #include <video/vga.h>
28
29 #include <linux/i2c.h>
30 #include <linux/i2c-algo-bit.h>
31
32 struct s3fb_info {
33 int chip, rev, mclk_freq;
34 int wc_cookie;
35 struct vgastate state;
36 struct mutex open_lock;
37 unsigned int ref_count;
38 u32 pseudo_palette[16];
39 #ifdef CONFIG_FB_S3_DDC
40 u8 __iomem *mmio;
41 bool ddc_registered;
42 struct i2c_adapter ddc_adapter;
43 struct i2c_algo_bit_data ddc_algo;
44 #endif
45 };
46
47
48 /* ------------------------------------------------------------------------- */
49
50 static const struct svga_fb_format s3fb_formats[] = {
51 { 0, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
52 FB_TYPE_TEXT, FB_AUX_TEXT_SVGA_STEP4, FB_VISUAL_PSEUDOCOLOR, 8, 16},
53 { 4, {0, 4, 0}, {0, 4, 0}, {0, 4, 0}, {0, 0, 0}, 0,
54 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 8, 16},
55 { 4, {0, 4, 0}, {0, 4, 0}, {0, 4, 0}, {0, 0, 0}, 1,
56 FB_TYPE_INTERLEAVED_PLANES, 1, FB_VISUAL_PSEUDOCOLOR, 8, 16},
57 { 8, {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
58 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 4, 8},
59 {16, {10, 5, 0}, {5, 5, 0}, {0, 5, 0}, {0, 0, 0}, 0,
60 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 4},
61 {16, {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0}, 0,
62 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 4},
63 {24, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
64 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 1, 2},
65 {32, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
66 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 1, 2},
67 SVGA_FORMAT_END
68 };
69
70
71 static const struct svga_pll s3_pll = {3, 129, 3, 33, 0, 3,
72 35000, 240000, 14318};
73 static const struct svga_pll s3_trio3d_pll = {3, 129, 3, 31, 0, 4,
74 230000, 460000, 14318};
75
76 static const int s3_memsizes[] = {4096, 0, 3072, 8192, 2048, 6144, 1024, 512};
77
78 static const char * const s3_names[] = {"S3 Unknown", "S3 Trio32", "S3 Trio64", "S3 Trio64V+",
79 "S3 Trio64UV+", "S3 Trio64V2/DX", "S3 Trio64V2/GX",
80 "S3 Plato/PX", "S3 Aurora64V+", "S3 Virge",
81 "S3 Virge/VX", "S3 Virge/DX", "S3 Virge/GX",
82 "S3 Virge/GX2", "S3 Virge/GX2+", "",
83 "S3 Trio3D/1X", "S3 Trio3D/2X", "S3 Trio3D/2X",
84 "S3 Trio3D", "S3 Virge/MX"};
85
86 #define CHIP_UNKNOWN 0x00
87 #define CHIP_732_TRIO32 0x01
88 #define CHIP_764_TRIO64 0x02
89 #define CHIP_765_TRIO64VP 0x03
90 #define CHIP_767_TRIO64UVP 0x04
91 #define CHIP_775_TRIO64V2_DX 0x05
92 #define CHIP_785_TRIO64V2_GX 0x06
93 #define CHIP_551_PLATO_PX 0x07
94 #define CHIP_M65_AURORA64VP 0x08
95 #define CHIP_325_VIRGE 0x09
96 #define CHIP_988_VIRGE_VX 0x0A
97 #define CHIP_375_VIRGE_DX 0x0B
98 #define CHIP_385_VIRGE_GX 0x0C
99 #define CHIP_357_VIRGE_GX2 0x0D
100 #define CHIP_359_VIRGE_GX2P 0x0E
101 #define CHIP_360_TRIO3D_1X 0x10
102 #define CHIP_362_TRIO3D_2X 0x11
103 #define CHIP_368_TRIO3D_2X 0x12
104 #define CHIP_365_TRIO3D 0x13
105 #define CHIP_260_VIRGE_MX 0x14
106
107 #define CHIP_XXX_TRIO 0x80
108 #define CHIP_XXX_TRIO64V2_DXGX 0x81
109 #define CHIP_XXX_VIRGE_DXGX 0x82
110 #define CHIP_36X_TRIO3D_1X_2X 0x83
111
112 #define CHIP_UNDECIDED_FLAG 0x80
113 #define CHIP_MASK 0xFF
114
115 #define MMIO_OFFSET 0x1000000
116 #define MMIO_SIZE 0x10000
117
118 /* CRT timing register sets */
119
120 static const struct vga_regset s3_h_total_regs[] = {{0x00, 0, 7}, {0x5D, 0, 0}, VGA_REGSET_END};
121 static const struct vga_regset s3_h_display_regs[] = {{0x01, 0, 7}, {0x5D, 1, 1}, VGA_REGSET_END};
122 static const struct vga_regset s3_h_blank_start_regs[] = {{0x02, 0, 7}, {0x5D, 2, 2}, VGA_REGSET_END};
123 static const struct vga_regset s3_h_blank_end_regs[] = {{0x03, 0, 4}, {0x05, 7, 7}, VGA_REGSET_END};
124 static const struct vga_regset s3_h_sync_start_regs[] = {{0x04, 0, 7}, {0x5D, 4, 4}, VGA_REGSET_END};
125 static const struct vga_regset s3_h_sync_end_regs[] = {{0x05, 0, 4}, VGA_REGSET_END};
126
127 static const struct vga_regset s3_v_total_regs[] = {{0x06, 0, 7}, {0x07, 0, 0}, {0x07, 5, 5}, {0x5E, 0, 0}, VGA_REGSET_END};
128 static const struct vga_regset s3_v_display_regs[] = {{0x12, 0, 7}, {0x07, 1, 1}, {0x07, 6, 6}, {0x5E, 1, 1}, VGA_REGSET_END};
129 static const struct vga_regset s3_v_blank_start_regs[] = {{0x15, 0, 7}, {0x07, 3, 3}, {0x09, 5, 5}, {0x5E, 2, 2}, VGA_REGSET_END};
130 static const struct vga_regset s3_v_blank_end_regs[] = {{0x16, 0, 7}, VGA_REGSET_END};
131 static const struct vga_regset s3_v_sync_start_regs[] = {{0x10, 0, 7}, {0x07, 2, 2}, {0x07, 7, 7}, {0x5E, 4, 4}, VGA_REGSET_END};
132 static const struct vga_regset s3_v_sync_end_regs[] = {{0x11, 0, 3}, VGA_REGSET_END};
133
134 static const struct vga_regset s3_line_compare_regs[] = {{0x18, 0, 7}, {0x07, 4, 4}, {0x09, 6, 6}, {0x5E, 6, 6}, VGA_REGSET_END};
135 static const struct vga_regset s3_start_address_regs[] = {{0x0d, 0, 7}, {0x0c, 0, 7}, {0x69, 0, 4}, VGA_REGSET_END};
136 static const struct vga_regset s3_offset_regs[] = {{0x13, 0, 7}, {0x51, 4, 5}, VGA_REGSET_END}; /* set 0x43 bit 2 to 0 */
137
138 static const struct vga_regset s3_dtpc_regs[] = {{0x3B, 0, 7}, {0x5D, 6, 6}, VGA_REGSET_END};
139
140 static const struct svga_timing_regs s3_timing_regs = {
141 s3_h_total_regs, s3_h_display_regs, s3_h_blank_start_regs,
142 s3_h_blank_end_regs, s3_h_sync_start_regs, s3_h_sync_end_regs,
143 s3_v_total_regs, s3_v_display_regs, s3_v_blank_start_regs,
144 s3_v_blank_end_regs, s3_v_sync_start_regs, s3_v_sync_end_regs,
145 };
146
147
148 /* ------------------------------------------------------------------------- */
149
150 /* Module parameters */
151
152
153 static char *mode_option;
154 static int mtrr = 1;
155 static int fasttext = 1;
156
157
158 MODULE_AUTHOR("(c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org>");
159 MODULE_LICENSE("GPL");
160 MODULE_DESCRIPTION("fbdev driver for S3 Trio/Virge");
161
162 module_param(mode_option, charp, 0444);
163 MODULE_PARM_DESC(mode_option, "Default video mode ('640x480-8@60', etc)");
164 module_param_named(mode, mode_option, charp, 0444);
165 MODULE_PARM_DESC(mode, "Default video mode ('640x480-8@60', etc) (deprecated)");
166 module_param(mtrr, int, 0444);
167 MODULE_PARM_DESC(mtrr, "Enable write-combining with MTRR (1=enable, 0=disable, default=1)");
168
169 module_param(fasttext, int, 0644);
170 MODULE_PARM_DESC(fasttext, "Enable S3 fast text mode (1=enable, 0=disable, default=1)");
171
172
173 /* ------------------------------------------------------------------------- */
174
175 #ifdef CONFIG_FB_S3_DDC
176
177 #define DDC_REG 0xaa /* Trio 3D/1X/2X */
178 #define DDC_MMIO_REG 0xff20 /* all other chips */
179 #define DDC_SCL_OUT (1 << 0)
180 #define DDC_SDA_OUT (1 << 1)
181 #define DDC_SCL_IN (1 << 2)
182 #define DDC_SDA_IN (1 << 3)
183 #define DDC_DRIVE_EN (1 << 4)
184
s3fb_ddc_needs_mmio(int chip)185 static bool s3fb_ddc_needs_mmio(int chip)
186 {
187 return !(chip == CHIP_360_TRIO3D_1X ||
188 chip == CHIP_362_TRIO3D_2X ||
189 chip == CHIP_368_TRIO3D_2X);
190 }
191
s3fb_ddc_read(struct s3fb_info * par)192 static u8 s3fb_ddc_read(struct s3fb_info *par)
193 {
194 if (s3fb_ddc_needs_mmio(par->chip))
195 return readb(par->mmio + DDC_MMIO_REG);
196 else
197 return vga_rcrt(par->state.vgabase, DDC_REG);
198 }
199
s3fb_ddc_write(struct s3fb_info * par,u8 val)200 static void s3fb_ddc_write(struct s3fb_info *par, u8 val)
201 {
202 if (s3fb_ddc_needs_mmio(par->chip))
203 writeb(val, par->mmio + DDC_MMIO_REG);
204 else
205 vga_wcrt(par->state.vgabase, DDC_REG, val);
206 }
207
s3fb_ddc_setscl(void * data,int val)208 static void s3fb_ddc_setscl(void *data, int val)
209 {
210 struct s3fb_info *par = data;
211 unsigned char reg;
212
213 reg = s3fb_ddc_read(par) | DDC_DRIVE_EN;
214 if (val)
215 reg |= DDC_SCL_OUT;
216 else
217 reg &= ~DDC_SCL_OUT;
218 s3fb_ddc_write(par, reg);
219 }
220
s3fb_ddc_setsda(void * data,int val)221 static void s3fb_ddc_setsda(void *data, int val)
222 {
223 struct s3fb_info *par = data;
224 unsigned char reg;
225
226 reg = s3fb_ddc_read(par) | DDC_DRIVE_EN;
227 if (val)
228 reg |= DDC_SDA_OUT;
229 else
230 reg &= ~DDC_SDA_OUT;
231 s3fb_ddc_write(par, reg);
232 }
233
s3fb_ddc_getscl(void * data)234 static int s3fb_ddc_getscl(void *data)
235 {
236 struct s3fb_info *par = data;
237
238 return !!(s3fb_ddc_read(par) & DDC_SCL_IN);
239 }
240
s3fb_ddc_getsda(void * data)241 static int s3fb_ddc_getsda(void *data)
242 {
243 struct s3fb_info *par = data;
244
245 return !!(s3fb_ddc_read(par) & DDC_SDA_IN);
246 }
247
s3fb_setup_ddc_bus(struct fb_info * info)248 static int s3fb_setup_ddc_bus(struct fb_info *info)
249 {
250 struct s3fb_info *par = info->par;
251
252 strscpy(par->ddc_adapter.name, info->fix.id,
253 sizeof(par->ddc_adapter.name));
254 par->ddc_adapter.owner = THIS_MODULE;
255 par->ddc_adapter.algo_data = &par->ddc_algo;
256 par->ddc_adapter.dev.parent = info->device;
257 par->ddc_algo.setsda = s3fb_ddc_setsda;
258 par->ddc_algo.setscl = s3fb_ddc_setscl;
259 par->ddc_algo.getsda = s3fb_ddc_getsda;
260 par->ddc_algo.getscl = s3fb_ddc_getscl;
261 par->ddc_algo.udelay = 10;
262 par->ddc_algo.timeout = 20;
263 par->ddc_algo.data = par;
264
265 i2c_set_adapdata(&par->ddc_adapter, par);
266
267 /*
268 * some Virge cards have external MUX to switch chip I2C bus between
269 * DDC and extension pins - switch it do DDC
270 */
271 /* vga_wseq(par->state.vgabase, 0x08, 0x06); - not needed, already unlocked */
272 if (par->chip == CHIP_357_VIRGE_GX2 ||
273 par->chip == CHIP_359_VIRGE_GX2P ||
274 par->chip == CHIP_260_VIRGE_MX)
275 svga_wseq_mask(par->state.vgabase, 0x0d, 0x01, 0x03);
276 else
277 svga_wseq_mask(par->state.vgabase, 0x0d, 0x00, 0x03);
278 /* some Virge need this or the DDC is ignored */
279 svga_wcrt_mask(par->state.vgabase, 0x5c, 0x03, 0x03);
280
281 return i2c_bit_add_bus(&par->ddc_adapter);
282 }
283 #endif /* CONFIG_FB_S3_DDC */
284
285
286 /* ------------------------------------------------------------------------- */
287
288 /* Set font in S3 fast text mode */
289
s3fb_settile_fast(struct fb_info * info,struct fb_tilemap * map)290 static void s3fb_settile_fast(struct fb_info *info, struct fb_tilemap *map)
291 {
292 const u8 *font = map->data;
293 u8 __iomem *fb = (u8 __iomem *) info->screen_base;
294 int i, c;
295
296 if ((map->width != 8) || (map->height != 16) ||
297 (map->depth != 1) || (map->length != 256)) {
298 fb_err(info, "unsupported font parameters: width %d, height %d, depth %d, length %d\n",
299 map->width, map->height, map->depth, map->length);
300 return;
301 }
302
303 fb += 2;
304 for (i = 0; i < map->height; i++) {
305 for (c = 0; c < map->length; c++) {
306 fb_writeb(font[c * map->height + i], fb + c * 4);
307 }
308 fb += 1024;
309 }
310 }
311
s3fb_tilecursor(struct fb_info * info,struct fb_tilecursor * cursor)312 static void s3fb_tilecursor(struct fb_info *info, struct fb_tilecursor *cursor)
313 {
314 struct s3fb_info *par = info->par;
315
316 svga_tilecursor(par->state.vgabase, info, cursor);
317 }
318
319 static struct fb_tile_ops s3fb_tile_ops = {
320 .fb_settile = svga_settile,
321 .fb_tilecopy = svga_tilecopy,
322 .fb_tilefill = svga_tilefill,
323 .fb_tileblit = svga_tileblit,
324 .fb_tilecursor = s3fb_tilecursor,
325 .fb_get_tilemax = svga_get_tilemax,
326 };
327
328 static struct fb_tile_ops s3fb_fast_tile_ops = {
329 .fb_settile = s3fb_settile_fast,
330 .fb_tilecopy = svga_tilecopy,
331 .fb_tilefill = svga_tilefill,
332 .fb_tileblit = svga_tileblit,
333 .fb_tilecursor = s3fb_tilecursor,
334 .fb_get_tilemax = svga_get_tilemax,
335 };
336
337
338 /* ------------------------------------------------------------------------- */
339
340 /* image data is MSB-first, fb structure is MSB-first too */
expand_color(u32 c)341 static inline u32 expand_color(u32 c)
342 {
343 return ((c & 1) | ((c & 2) << 7) | ((c & 4) << 14) | ((c & 8) << 21)) * 0xFF;
344 }
345
346 /* s3fb_iplan_imageblit silently assumes that almost everything is 8-pixel aligned */
s3fb_iplan_imageblit(struct fb_info * info,const struct fb_image * image)347 static void s3fb_iplan_imageblit(struct fb_info *info, const struct fb_image *image)
348 {
349 u32 fg = expand_color(image->fg_color);
350 u32 bg = expand_color(image->bg_color);
351 const u8 *src1, *src;
352 u8 __iomem *dst1;
353 u32 __iomem *dst;
354 u32 val;
355 int x, y;
356
357 src1 = image->data;
358 dst1 = info->screen_base + (image->dy * info->fix.line_length)
359 + ((image->dx / 8) * 4);
360
361 for (y = 0; y < image->height; y++) {
362 src = src1;
363 dst = (u32 __iomem *) dst1;
364 for (x = 0; x < image->width; x += 8) {
365 val = *(src++) * 0x01010101;
366 val = (val & fg) | (~val & bg);
367 fb_writel(val, dst++);
368 }
369 src1 += image->width / 8;
370 dst1 += info->fix.line_length;
371 }
372
373 }
374
375 /* s3fb_iplan_fillrect silently assumes that almost everything is 8-pixel aligned */
s3fb_iplan_fillrect(struct fb_info * info,const struct fb_fillrect * rect)376 static void s3fb_iplan_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
377 {
378 u32 fg = expand_color(rect->color);
379 u8 __iomem *dst1;
380 u32 __iomem *dst;
381 int x, y;
382
383 dst1 = info->screen_base + (rect->dy * info->fix.line_length)
384 + ((rect->dx / 8) * 4);
385
386 for (y = 0; y < rect->height; y++) {
387 dst = (u32 __iomem *) dst1;
388 for (x = 0; x < rect->width; x += 8) {
389 fb_writel(fg, dst++);
390 }
391 dst1 += info->fix.line_length;
392 }
393 }
394
395
396 /* image data is MSB-first, fb structure is high-nibble-in-low-byte-first */
expand_pixel(u32 c)397 static inline u32 expand_pixel(u32 c)
398 {
399 return (((c & 1) << 24) | ((c & 2) << 27) | ((c & 4) << 14) | ((c & 8) << 17) |
400 ((c & 16) << 4) | ((c & 32) << 7) | ((c & 64) >> 6) | ((c & 128) >> 3)) * 0xF;
401 }
402
403 /* s3fb_cfb4_imageblit silently assumes that almost everything is 8-pixel aligned */
s3fb_cfb4_imageblit(struct fb_info * info,const struct fb_image * image)404 static void s3fb_cfb4_imageblit(struct fb_info *info, const struct fb_image *image)
405 {
406 u32 fg = image->fg_color * 0x11111111;
407 u32 bg = image->bg_color * 0x11111111;
408 const u8 *src1, *src;
409 u8 __iomem *dst1;
410 u32 __iomem *dst;
411 u32 val;
412 int x, y;
413
414 src1 = image->data;
415 dst1 = info->screen_base + (image->dy * info->fix.line_length)
416 + ((image->dx / 8) * 4);
417
418 for (y = 0; y < image->height; y++) {
419 src = src1;
420 dst = (u32 __iomem *) dst1;
421 for (x = 0; x < image->width; x += 8) {
422 val = expand_pixel(*(src++));
423 val = (val & fg) | (~val & bg);
424 fb_writel(val, dst++);
425 }
426 src1 += image->width / 8;
427 dst1 += info->fix.line_length;
428 }
429 }
430
s3fb_imageblit(struct fb_info * info,const struct fb_image * image)431 static void s3fb_imageblit(struct fb_info *info, const struct fb_image *image)
432 {
433 if ((info->var.bits_per_pixel == 4) && (image->depth == 1)
434 && ((image->width % 8) == 0) && ((image->dx % 8) == 0)) {
435 if (info->fix.type == FB_TYPE_INTERLEAVED_PLANES)
436 s3fb_iplan_imageblit(info, image);
437 else
438 s3fb_cfb4_imageblit(info, image);
439 } else
440 cfb_imageblit(info, image);
441 }
442
s3fb_fillrect(struct fb_info * info,const struct fb_fillrect * rect)443 static void s3fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
444 {
445 if ((info->var.bits_per_pixel == 4)
446 && ((rect->width % 8) == 0) && ((rect->dx % 8) == 0)
447 && (info->fix.type == FB_TYPE_INTERLEAVED_PLANES))
448 s3fb_iplan_fillrect(info, rect);
449 else
450 cfb_fillrect(info, rect);
451 }
452
453
454
455 /* ------------------------------------------------------------------------- */
456
457
s3_set_pixclock(struct fb_info * info,u32 pixclock)458 static void s3_set_pixclock(struct fb_info *info, u32 pixclock)
459 {
460 struct s3fb_info *par = info->par;
461 u16 m, n, r;
462 u8 regval;
463 int rv;
464
465 rv = svga_compute_pll((par->chip == CHIP_365_TRIO3D) ? &s3_trio3d_pll : &s3_pll,
466 1000000000 / pixclock, &m, &n, &r, info->node);
467 if (rv < 0) {
468 fb_err(info, "cannot set requested pixclock, keeping old value\n");
469 return;
470 }
471
472 /* Set VGA misc register */
473 regval = vga_r(par->state.vgabase, VGA_MIS_R);
474 vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD);
475
476 /* Set S3 clock registers */
477 if (par->chip == CHIP_357_VIRGE_GX2 ||
478 par->chip == CHIP_359_VIRGE_GX2P ||
479 par->chip == CHIP_360_TRIO3D_1X ||
480 par->chip == CHIP_362_TRIO3D_2X ||
481 par->chip == CHIP_368_TRIO3D_2X ||
482 par->chip == CHIP_260_VIRGE_MX) {
483 vga_wseq(par->state.vgabase, 0x12, (n - 2) | ((r & 3) << 6)); /* n and two bits of r */
484 vga_wseq(par->state.vgabase, 0x29, r >> 2); /* remaining highest bit of r */
485 } else
486 vga_wseq(par->state.vgabase, 0x12, (n - 2) | (r << 5));
487 vga_wseq(par->state.vgabase, 0x13, m - 2);
488
489 udelay(1000);
490
491 /* Activate clock - write 0, 1, 0 to seq/15 bit 5 */
492 regval = vga_rseq (par->state.vgabase, 0x15); /* | 0x80; */
493 vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5));
494 vga_wseq(par->state.vgabase, 0x15, regval | (1<<5));
495 vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5));
496 }
497
498
499 /* Open framebuffer */
500
s3fb_open(struct fb_info * info,int user)501 static int s3fb_open(struct fb_info *info, int user)
502 {
503 struct s3fb_info *par = info->par;
504
505 mutex_lock(&(par->open_lock));
506 if (par->ref_count == 0) {
507 void __iomem *vgabase = par->state.vgabase;
508
509 memset(&(par->state), 0, sizeof(struct vgastate));
510 par->state.vgabase = vgabase;
511 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP;
512 par->state.num_crtc = 0x70;
513 par->state.num_seq = 0x20;
514 save_vga(&(par->state));
515 }
516
517 par->ref_count++;
518 mutex_unlock(&(par->open_lock));
519
520 return 0;
521 }
522
523 /* Close framebuffer */
524
s3fb_release(struct fb_info * info,int user)525 static int s3fb_release(struct fb_info *info, int user)
526 {
527 struct s3fb_info *par = info->par;
528
529 mutex_lock(&(par->open_lock));
530 if (par->ref_count == 0) {
531 mutex_unlock(&(par->open_lock));
532 return -EINVAL;
533 }
534
535 if (par->ref_count == 1)
536 restore_vga(&(par->state));
537
538 par->ref_count--;
539 mutex_unlock(&(par->open_lock));
540
541 return 0;
542 }
543
544 /* Validate passed in var */
545
s3fb_check_var(struct fb_var_screeninfo * var,struct fb_info * info)546 static int s3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
547 {
548 struct s3fb_info *par = info->par;
549 int rv, mem, step;
550 u16 m, n, r;
551
552 if (!var->pixclock)
553 return -EINVAL;
554
555 /* Find appropriate format */
556 rv = svga_match_format (s3fb_formats, var, NULL);
557
558 /* 32bpp mode is not supported on VIRGE VX,
559 24bpp is not supported on others */
560 if ((par->chip == CHIP_988_VIRGE_VX) ? (rv == 7) : (rv == 6))
561 rv = -EINVAL;
562
563 if (rv < 0) {
564 fb_err(info, "unsupported mode requested\n");
565 return rv;
566 }
567
568 /* Do not allow to have real resoulution larger than virtual */
569 if (var->xres > var->xres_virtual)
570 var->xres_virtual = var->xres;
571
572 if (var->yres > var->yres_virtual)
573 var->yres_virtual = var->yres;
574
575 /* Round up xres_virtual to have proper alignment of lines */
576 step = s3fb_formats[rv].xresstep - 1;
577 var->xres_virtual = (var->xres_virtual+step) & ~step;
578
579 /* Check whether have enough memory */
580 mem = ((var->bits_per_pixel * var->xres_virtual) >> 3) * var->yres_virtual;
581 if (mem > info->screen_size) {
582 fb_err(info, "not enough framebuffer memory (%d kB requested , %u kB available)\n",
583 mem >> 10, (unsigned int) (info->screen_size >> 10));
584 return -EINVAL;
585 }
586
587 rv = svga_check_timings (&s3_timing_regs, var, info->node);
588 if (rv < 0) {
589 fb_err(info, "invalid timings requested\n");
590 return rv;
591 }
592
593 rv = svga_compute_pll(&s3_pll, PICOS2KHZ(var->pixclock), &m, &n, &r,
594 info->node);
595 if (rv < 0) {
596 fb_err(info, "invalid pixclock value requested\n");
597 return rv;
598 }
599
600 return 0;
601 }
602
603 /* Set video mode from par */
604
s3fb_set_par(struct fb_info * info)605 static int s3fb_set_par(struct fb_info *info)
606 {
607 struct s3fb_info *par = info->par;
608 u32 value, mode, hmul, offset_value, screen_size, multiplex, dbytes;
609 u32 bpp = info->var.bits_per_pixel;
610 u32 htotal, hsstart;
611
612 if (bpp != 0) {
613 info->fix.ypanstep = 1;
614 info->fix.line_length = (info->var.xres_virtual * bpp) / 8;
615
616 info->flags &= ~FBINFO_MISC_TILEBLITTING;
617 info->tileops = NULL;
618
619 /* in 4bpp supports 8p wide tiles only, any tiles otherwise */
620 if (bpp == 4) {
621 bitmap_zero(info->pixmap.blit_x, FB_MAX_BLIT_WIDTH);
622 set_bit(8 - 1, info->pixmap.blit_x);
623 } else {
624 bitmap_fill(info->pixmap.blit_x, FB_MAX_BLIT_WIDTH);
625 }
626 bitmap_fill(info->pixmap.blit_y, FB_MAX_BLIT_HEIGHT);
627
628 offset_value = (info->var.xres_virtual * bpp) / 64;
629 screen_size = info->var.yres_virtual * info->fix.line_length;
630 } else {
631 info->fix.ypanstep = 16;
632 info->fix.line_length = 0;
633
634 info->flags |= FBINFO_MISC_TILEBLITTING;
635 info->tileops = fasttext ? &s3fb_fast_tile_ops : &s3fb_tile_ops;
636
637 /* supports 8x16 tiles only */
638 bitmap_zero(info->pixmap.blit_x, FB_MAX_BLIT_WIDTH);
639 set_bit(8 - 1, info->pixmap.blit_x);
640 bitmap_zero(info->pixmap.blit_y, FB_MAX_BLIT_HEIGHT);
641 set_bit(16 - 1, info->pixmap.blit_y);
642
643 offset_value = info->var.xres_virtual / 16;
644 screen_size = (info->var.xres_virtual * info->var.yres_virtual) / 64;
645 }
646
647 info->var.xoffset = 0;
648 info->var.yoffset = 0;
649 info->var.activate = FB_ACTIVATE_NOW;
650
651 /* Unlock registers */
652 vga_wcrt(par->state.vgabase, 0x38, 0x48);
653 vga_wcrt(par->state.vgabase, 0x39, 0xA5);
654 vga_wseq(par->state.vgabase, 0x08, 0x06);
655 svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x80);
656
657 /* Blank screen and turn off sync */
658 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
659 svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80);
660
661 /* Set default values */
662 svga_set_default_gfx_regs(par->state.vgabase);
663 svga_set_default_atc_regs(par->state.vgabase);
664 svga_set_default_seq_regs(par->state.vgabase);
665 svga_set_default_crt_regs(par->state.vgabase);
666 svga_wcrt_multi(par->state.vgabase, s3_line_compare_regs, 0xFFFFFFFF);
667 svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, 0);
668
669 /* S3 specific initialization */
670 svga_wcrt_mask(par->state.vgabase, 0x58, 0x10, 0x10); /* enable linear framebuffer */
671 svga_wcrt_mask(par->state.vgabase, 0x31, 0x08, 0x08); /* enable sequencer access to framebuffer above 256 kB */
672
673 /* svga_wcrt_mask(par->state.vgabase, 0x33, 0x08, 0x08); */ /* DDR ? */
674 /* svga_wcrt_mask(par->state.vgabase, 0x43, 0x01, 0x01); */ /* DDR ? */
675 svga_wcrt_mask(par->state.vgabase, 0x33, 0x00, 0x08); /* no DDR ? */
676 svga_wcrt_mask(par->state.vgabase, 0x43, 0x00, 0x01); /* no DDR ? */
677
678 svga_wcrt_mask(par->state.vgabase, 0x5D, 0x00, 0x28); /* Clear strange HSlen bits */
679
680 /* svga_wcrt_mask(par->state.vgabase, 0x58, 0x03, 0x03); */
681
682 /* svga_wcrt_mask(par->state.vgabase, 0x53, 0x12, 0x13); */ /* enable MMIO */
683 /* svga_wcrt_mask(par->state.vgabase, 0x40, 0x08, 0x08); */ /* enable write buffer */
684
685
686 /* Set the offset register */
687 fb_dbg(info, "offset register : %d\n", offset_value);
688 svga_wcrt_multi(par->state.vgabase, s3_offset_regs, offset_value);
689
690 if (par->chip != CHIP_357_VIRGE_GX2 &&
691 par->chip != CHIP_359_VIRGE_GX2P &&
692 par->chip != CHIP_360_TRIO3D_1X &&
693 par->chip != CHIP_362_TRIO3D_2X &&
694 par->chip != CHIP_368_TRIO3D_2X &&
695 par->chip != CHIP_260_VIRGE_MX) {
696 vga_wcrt(par->state.vgabase, 0x54, 0x18); /* M parameter */
697 vga_wcrt(par->state.vgabase, 0x60, 0xff); /* N parameter */
698 vga_wcrt(par->state.vgabase, 0x61, 0xff); /* L parameter */
699 vga_wcrt(par->state.vgabase, 0x62, 0xff); /* L parameter */
700 }
701
702 vga_wcrt(par->state.vgabase, 0x3A, 0x35);
703 svga_wattr(par->state.vgabase, 0x33, 0x00);
704
705 if (info->var.vmode & FB_VMODE_DOUBLE)
706 svga_wcrt_mask(par->state.vgabase, 0x09, 0x80, 0x80);
707 else
708 svga_wcrt_mask(par->state.vgabase, 0x09, 0x00, 0x80);
709
710 if (info->var.vmode & FB_VMODE_INTERLACED)
711 svga_wcrt_mask(par->state.vgabase, 0x42, 0x20, 0x20);
712 else
713 svga_wcrt_mask(par->state.vgabase, 0x42, 0x00, 0x20);
714
715 /* Disable hardware graphics cursor */
716 svga_wcrt_mask(par->state.vgabase, 0x45, 0x00, 0x01);
717 /* Disable Streams engine */
718 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0x0C);
719
720 mode = svga_match_format(s3fb_formats, &(info->var), &(info->fix));
721
722 /* S3 virge DX hack */
723 if (par->chip == CHIP_375_VIRGE_DX) {
724 vga_wcrt(par->state.vgabase, 0x86, 0x80);
725 vga_wcrt(par->state.vgabase, 0x90, 0x00);
726 }
727
728 /* S3 virge VX hack */
729 if (par->chip == CHIP_988_VIRGE_VX) {
730 vga_wcrt(par->state.vgabase, 0x50, 0x00);
731 vga_wcrt(par->state.vgabase, 0x67, 0x50);
732 msleep(10); /* screen remains blank sometimes without this */
733 vga_wcrt(par->state.vgabase, 0x63, (mode <= 2) ? 0x90 : 0x09);
734 vga_wcrt(par->state.vgabase, 0x66, 0x90);
735 }
736
737 if (par->chip == CHIP_357_VIRGE_GX2 ||
738 par->chip == CHIP_359_VIRGE_GX2P ||
739 par->chip == CHIP_360_TRIO3D_1X ||
740 par->chip == CHIP_362_TRIO3D_2X ||
741 par->chip == CHIP_368_TRIO3D_2X ||
742 par->chip == CHIP_365_TRIO3D ||
743 par->chip == CHIP_375_VIRGE_DX ||
744 par->chip == CHIP_385_VIRGE_GX ||
745 par->chip == CHIP_260_VIRGE_MX) {
746 dbytes = info->var.xres * ((bpp+7)/8);
747 vga_wcrt(par->state.vgabase, 0x91, (dbytes + 7) / 8);
748 vga_wcrt(par->state.vgabase, 0x90, (((dbytes + 7) / 8) >> 8) | 0x80);
749
750 vga_wcrt(par->state.vgabase, 0x66, 0x81);
751 }
752
753 if (par->chip == CHIP_357_VIRGE_GX2 ||
754 par->chip == CHIP_359_VIRGE_GX2P ||
755 par->chip == CHIP_360_TRIO3D_1X ||
756 par->chip == CHIP_362_TRIO3D_2X ||
757 par->chip == CHIP_368_TRIO3D_2X ||
758 par->chip == CHIP_260_VIRGE_MX)
759 vga_wcrt(par->state.vgabase, 0x34, 0x00);
760 else /* enable Data Transfer Position Control (DTPC) */
761 vga_wcrt(par->state.vgabase, 0x34, 0x10);
762
763 svga_wcrt_mask(par->state.vgabase, 0x31, 0x00, 0x40);
764 multiplex = 0;
765 hmul = 1;
766
767 /* Set mode-specific register values */
768 switch (mode) {
769 case 0:
770 fb_dbg(info, "text mode\n");
771 svga_set_textmode_vga_regs(par->state.vgabase);
772
773 /* Set additional registers like in 8-bit mode */
774 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
775 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
776
777 /* Disable enhanced mode */
778 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30);
779
780 if (fasttext) {
781 fb_dbg(info, "high speed text mode set\n");
782 svga_wcrt_mask(par->state.vgabase, 0x31, 0x40, 0x40);
783 }
784 break;
785 case 1:
786 fb_dbg(info, "4 bit pseudocolor\n");
787 vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40);
788
789 /* Set additional registers like in 8-bit mode */
790 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
791 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
792
793 /* disable enhanced mode */
794 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30);
795 break;
796 case 2:
797 fb_dbg(info, "4 bit pseudocolor, planar\n");
798
799 /* Set additional registers like in 8-bit mode */
800 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
801 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
802
803 /* disable enhanced mode */
804 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30);
805 break;
806 case 3:
807 fb_dbg(info, "8 bit pseudocolor\n");
808 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
809 if (info->var.pixclock > 20000 ||
810 par->chip == CHIP_357_VIRGE_GX2 ||
811 par->chip == CHIP_359_VIRGE_GX2P ||
812 par->chip == CHIP_360_TRIO3D_1X ||
813 par->chip == CHIP_362_TRIO3D_2X ||
814 par->chip == CHIP_368_TRIO3D_2X ||
815 par->chip == CHIP_260_VIRGE_MX)
816 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
817 else {
818 svga_wcrt_mask(par->state.vgabase, 0x67, 0x10, 0xF0);
819 multiplex = 1;
820 }
821 break;
822 case 4:
823 fb_dbg(info, "5/5/5 truecolor\n");
824 if (par->chip == CHIP_988_VIRGE_VX) {
825 if (info->var.pixclock > 20000)
826 svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0);
827 else
828 svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0);
829 } else if (par->chip == CHIP_365_TRIO3D) {
830 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
831 if (info->var.pixclock > 8695) {
832 svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0);
833 hmul = 2;
834 } else {
835 svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0);
836 multiplex = 1;
837 }
838 } else {
839 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
840 svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0);
841 if (par->chip != CHIP_357_VIRGE_GX2 &&
842 par->chip != CHIP_359_VIRGE_GX2P &&
843 par->chip != CHIP_360_TRIO3D_1X &&
844 par->chip != CHIP_362_TRIO3D_2X &&
845 par->chip != CHIP_368_TRIO3D_2X &&
846 par->chip != CHIP_260_VIRGE_MX)
847 hmul = 2;
848 }
849 break;
850 case 5:
851 fb_dbg(info, "5/6/5 truecolor\n");
852 if (par->chip == CHIP_988_VIRGE_VX) {
853 if (info->var.pixclock > 20000)
854 svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0);
855 else
856 svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0);
857 } else if (par->chip == CHIP_365_TRIO3D) {
858 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
859 if (info->var.pixclock > 8695) {
860 svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0);
861 hmul = 2;
862 } else {
863 svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0);
864 multiplex = 1;
865 }
866 } else {
867 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
868 svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0);
869 if (par->chip != CHIP_357_VIRGE_GX2 &&
870 par->chip != CHIP_359_VIRGE_GX2P &&
871 par->chip != CHIP_360_TRIO3D_1X &&
872 par->chip != CHIP_362_TRIO3D_2X &&
873 par->chip != CHIP_368_TRIO3D_2X &&
874 par->chip != CHIP_260_VIRGE_MX)
875 hmul = 2;
876 }
877 break;
878 case 6:
879 /* VIRGE VX case */
880 fb_dbg(info, "8/8/8 truecolor\n");
881 svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0);
882 break;
883 case 7:
884 fb_dbg(info, "8/8/8/8 truecolor\n");
885 svga_wcrt_mask(par->state.vgabase, 0x50, 0x30, 0x30);
886 svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0);
887 break;
888 default:
889 fb_err(info, "unsupported mode - bug\n");
890 return -EINVAL;
891 }
892
893 if (par->chip != CHIP_988_VIRGE_VX) {
894 svga_wseq_mask(par->state.vgabase, 0x15, multiplex ? 0x10 : 0x00, 0x10);
895 svga_wseq_mask(par->state.vgabase, 0x18, multiplex ? 0x80 : 0x00, 0x80);
896 }
897
898 s3_set_pixclock(info, info->var.pixclock);
899 svga_set_timings(par->state.vgabase, &s3_timing_regs, &(info->var), hmul, 1,
900 (info->var.vmode & FB_VMODE_DOUBLE) ? 2 : 1,
901 (info->var.vmode & FB_VMODE_INTERLACED) ? 2 : 1,
902 hmul, info->node);
903
904 /* Set interlaced mode start/end register */
905 htotal = info->var.xres + info->var.left_margin + info->var.right_margin + info->var.hsync_len;
906 htotal = ((htotal * hmul) / 8) - 5;
907 vga_wcrt(par->state.vgabase, 0x3C, (htotal + 1) / 2);
908
909 /* Set Data Transfer Position */
910 hsstart = ((info->var.xres + info->var.right_margin) * hmul) / 8;
911 /* + 2 is needed for Virge/VX, does no harm on other cards */
912 value = clamp((htotal + hsstart + 1) / 2 + 2, hsstart + 4, htotal + 1);
913 svga_wcrt_multi(par->state.vgabase, s3_dtpc_regs, value);
914
915 if (screen_size > info->screen_size)
916 screen_size = info->screen_size;
917 memset_io(info->screen_base, 0x00, screen_size);
918 /* Device and screen back on */
919 svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80);
920 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
921
922 return 0;
923 }
924
925 /* Set a colour register */
926
s3fb_setcolreg(u_int regno,u_int red,u_int green,u_int blue,u_int transp,struct fb_info * fb)927 static int s3fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
928 u_int transp, struct fb_info *fb)
929 {
930 switch (fb->var.bits_per_pixel) {
931 case 0:
932 case 4:
933 if (regno >= 16)
934 return -EINVAL;
935
936 if ((fb->var.bits_per_pixel == 4) &&
937 (fb->var.nonstd == 0)) {
938 outb(0xF0, VGA_PEL_MSK);
939 outb(regno*16, VGA_PEL_IW);
940 } else {
941 outb(0x0F, VGA_PEL_MSK);
942 outb(regno, VGA_PEL_IW);
943 }
944 outb(red >> 10, VGA_PEL_D);
945 outb(green >> 10, VGA_PEL_D);
946 outb(blue >> 10, VGA_PEL_D);
947 break;
948 case 8:
949 if (regno >= 256)
950 return -EINVAL;
951
952 outb(0xFF, VGA_PEL_MSK);
953 outb(regno, VGA_PEL_IW);
954 outb(red >> 10, VGA_PEL_D);
955 outb(green >> 10, VGA_PEL_D);
956 outb(blue >> 10, VGA_PEL_D);
957 break;
958 case 16:
959 if (regno >= 16)
960 return 0;
961
962 if (fb->var.green.length == 5)
963 ((u32*)fb->pseudo_palette)[regno] = ((red & 0xF800) >> 1) |
964 ((green & 0xF800) >> 6) | ((blue & 0xF800) >> 11);
965 else if (fb->var.green.length == 6)
966 ((u32*)fb->pseudo_palette)[regno] = (red & 0xF800) |
967 ((green & 0xFC00) >> 5) | ((blue & 0xF800) >> 11);
968 else return -EINVAL;
969 break;
970 case 24:
971 case 32:
972 if (regno >= 16)
973 return 0;
974
975 ((u32*)fb->pseudo_palette)[regno] = ((red & 0xFF00) << 8) |
976 (green & 0xFF00) | ((blue & 0xFF00) >> 8);
977 break;
978 default:
979 return -EINVAL;
980 }
981
982 return 0;
983 }
984
985
986 /* Set the display blanking state */
987
s3fb_blank(int blank_mode,struct fb_info * info)988 static int s3fb_blank(int blank_mode, struct fb_info *info)
989 {
990 struct s3fb_info *par = info->par;
991
992 switch (blank_mode) {
993 case FB_BLANK_UNBLANK:
994 fb_dbg(info, "unblank\n");
995 svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06);
996 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
997 break;
998 case FB_BLANK_NORMAL:
999 fb_dbg(info, "blank\n");
1000 svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06);
1001 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
1002 break;
1003 case FB_BLANK_HSYNC_SUSPEND:
1004 fb_dbg(info, "hsync\n");
1005 svga_wcrt_mask(par->state.vgabase, 0x56, 0x02, 0x06);
1006 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
1007 break;
1008 case FB_BLANK_VSYNC_SUSPEND:
1009 fb_dbg(info, "vsync\n");
1010 svga_wcrt_mask(par->state.vgabase, 0x56, 0x04, 0x06);
1011 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
1012 break;
1013 case FB_BLANK_POWERDOWN:
1014 fb_dbg(info, "sync down\n");
1015 svga_wcrt_mask(par->state.vgabase, 0x56, 0x06, 0x06);
1016 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
1017 break;
1018 }
1019
1020 return 0;
1021 }
1022
1023
1024 /* Pan the display */
1025
s3fb_pan_display(struct fb_var_screeninfo * var,struct fb_info * info)1026 static int s3fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
1027 {
1028 struct s3fb_info *par = info->par;
1029 unsigned int offset;
1030
1031 /* Calculate the offset */
1032 if (info->var.bits_per_pixel == 0) {
1033 offset = (var->yoffset / 16) * (info->var.xres_virtual / 2)
1034 + (var->xoffset / 2);
1035 offset = offset >> 2;
1036 } else {
1037 offset = (var->yoffset * info->fix.line_length) +
1038 (var->xoffset * info->var.bits_per_pixel / 8);
1039 offset = offset >> 2;
1040 }
1041
1042 /* Set the offset */
1043 svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, offset);
1044
1045 return 0;
1046 }
1047
1048 /* ------------------------------------------------------------------------- */
1049
1050 /* Frame buffer operations */
1051
1052 static const struct fb_ops s3fb_ops = {
1053 .owner = THIS_MODULE,
1054 .fb_open = s3fb_open,
1055 .fb_release = s3fb_release,
1056 __FB_DEFAULT_IOMEM_OPS_RDWR,
1057 .fb_check_var = s3fb_check_var,
1058 .fb_set_par = s3fb_set_par,
1059 .fb_setcolreg = s3fb_setcolreg,
1060 .fb_blank = s3fb_blank,
1061 .fb_pan_display = s3fb_pan_display,
1062 .fb_fillrect = s3fb_fillrect,
1063 .fb_copyarea = cfb_copyarea,
1064 .fb_imageblit = s3fb_imageblit,
1065 __FB_DEFAULT_IOMEM_OPS_MMAP,
1066 .fb_get_caps = svga_get_caps,
1067 };
1068
1069 /* ------------------------------------------------------------------------- */
1070
s3_identification(struct s3fb_info * par)1071 static int s3_identification(struct s3fb_info *par)
1072 {
1073 int chip = par->chip;
1074
1075 if (chip == CHIP_XXX_TRIO) {
1076 u8 cr30 = vga_rcrt(par->state.vgabase, 0x30);
1077 u8 cr2e = vga_rcrt(par->state.vgabase, 0x2e);
1078 u8 cr2f = vga_rcrt(par->state.vgabase, 0x2f);
1079
1080 if ((cr30 == 0xE0) || (cr30 == 0xE1)) {
1081 if (cr2e == 0x10)
1082 return CHIP_732_TRIO32;
1083 if (cr2e == 0x11) {
1084 if (! (cr2f & 0x40))
1085 return CHIP_764_TRIO64;
1086 else
1087 return CHIP_765_TRIO64VP;
1088 }
1089 }
1090 }
1091
1092 if (chip == CHIP_XXX_TRIO64V2_DXGX) {
1093 u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f);
1094
1095 if (! (cr6f & 0x01))
1096 return CHIP_775_TRIO64V2_DX;
1097 else
1098 return CHIP_785_TRIO64V2_GX;
1099 }
1100
1101 if (chip == CHIP_XXX_VIRGE_DXGX) {
1102 u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f);
1103
1104 if (! (cr6f & 0x01))
1105 return CHIP_375_VIRGE_DX;
1106 else
1107 return CHIP_385_VIRGE_GX;
1108 }
1109
1110 if (chip == CHIP_36X_TRIO3D_1X_2X) {
1111 switch (vga_rcrt(par->state.vgabase, 0x2f)) {
1112 case 0x00:
1113 return CHIP_360_TRIO3D_1X;
1114 case 0x01:
1115 return CHIP_362_TRIO3D_2X;
1116 case 0x02:
1117 return CHIP_368_TRIO3D_2X;
1118 }
1119 }
1120
1121 return CHIP_UNKNOWN;
1122 }
1123
1124
1125 /* PCI probe */
1126
s3_pci_probe(struct pci_dev * dev,const struct pci_device_id * id)1127 static int s3_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
1128 {
1129 struct pci_bus_region bus_reg;
1130 struct resource vga_res;
1131 struct fb_info *info;
1132 struct s3fb_info *par;
1133 int rc;
1134 u8 regval, cr38, cr39;
1135 bool found = false;
1136
1137 /* Ignore secondary VGA device because there is no VGA arbitration */
1138 if (! svga_primary_device(dev)) {
1139 dev_info(&(dev->dev), "ignoring secondary device\n");
1140 return -ENODEV;
1141 }
1142
1143 rc = aperture_remove_conflicting_pci_devices(dev, "s3fb");
1144 if (rc)
1145 return rc;
1146
1147 /* Allocate and fill driver data structure */
1148 info = framebuffer_alloc(sizeof(struct s3fb_info), &(dev->dev));
1149 if (!info)
1150 return -ENOMEM;
1151
1152 par = info->par;
1153 mutex_init(&par->open_lock);
1154
1155 info->flags = FBINFO_PARTIAL_PAN_OK | FBINFO_HWACCEL_YPAN;
1156 info->fbops = &s3fb_ops;
1157
1158 /* Prepare PCI device */
1159 rc = pci_enable_device(dev);
1160 if (rc < 0) {
1161 dev_err(info->device, "cannot enable PCI device\n");
1162 goto err_enable_device;
1163 }
1164
1165 rc = pci_request_regions(dev, "s3fb");
1166 if (rc < 0) {
1167 dev_err(info->device, "cannot reserve framebuffer region\n");
1168 goto err_request_regions;
1169 }
1170
1171
1172 info->fix.smem_start = pci_resource_start(dev, 0);
1173 info->fix.smem_len = pci_resource_len(dev, 0);
1174
1175 /* Map physical IO memory address into kernel space */
1176 info->screen_base = pci_iomap_wc(dev, 0, 0);
1177 if (! info->screen_base) {
1178 rc = -ENOMEM;
1179 dev_err(info->device, "iomap for framebuffer failed\n");
1180 goto err_iomap;
1181 }
1182
1183 bus_reg.start = 0;
1184 bus_reg.end = 64 * 1024;
1185
1186 vga_res.flags = IORESOURCE_IO;
1187
1188 pcibios_bus_to_resource(dev->bus, &vga_res, &bus_reg);
1189
1190 par->state.vgabase = (void __iomem *) (unsigned long) vga_res.start;
1191
1192 /* Unlock regs */
1193 cr38 = vga_rcrt(par->state.vgabase, 0x38);
1194 cr39 = vga_rcrt(par->state.vgabase, 0x39);
1195 vga_wseq(par->state.vgabase, 0x08, 0x06);
1196 vga_wcrt(par->state.vgabase, 0x38, 0x48);
1197 vga_wcrt(par->state.vgabase, 0x39, 0xA5);
1198
1199 /* Identify chip type */
1200 par->chip = id->driver_data & CHIP_MASK;
1201 par->rev = vga_rcrt(par->state.vgabase, 0x2f);
1202 if (par->chip & CHIP_UNDECIDED_FLAG)
1203 par->chip = s3_identification(par);
1204
1205 /* Find how many physical memory there is on card */
1206 /* 0x36 register is accessible even if other registers are locked */
1207 regval = vga_rcrt(par->state.vgabase, 0x36);
1208 if (par->chip == CHIP_360_TRIO3D_1X ||
1209 par->chip == CHIP_362_TRIO3D_2X ||
1210 par->chip == CHIP_368_TRIO3D_2X ||
1211 par->chip == CHIP_365_TRIO3D) {
1212 switch ((regval & 0xE0) >> 5) {
1213 case 0: /* 8MB -- only 4MB usable for display */
1214 case 1: /* 4MB with 32-bit bus */
1215 case 2: /* 4MB */
1216 info->screen_size = 4 << 20;
1217 break;
1218 case 4: /* 2MB on 365 Trio3D */
1219 case 6: /* 2MB */
1220 info->screen_size = 2 << 20;
1221 break;
1222 }
1223 } else if (par->chip == CHIP_357_VIRGE_GX2 ||
1224 par->chip == CHIP_359_VIRGE_GX2P ||
1225 par->chip == CHIP_260_VIRGE_MX) {
1226 switch ((regval & 0xC0) >> 6) {
1227 case 1: /* 4MB */
1228 info->screen_size = 4 << 20;
1229 break;
1230 case 3: /* 2MB */
1231 info->screen_size = 2 << 20;
1232 break;
1233 }
1234 } else if (par->chip == CHIP_988_VIRGE_VX) {
1235 switch ((regval & 0x60) >> 5) {
1236 case 0: /* 2MB */
1237 info->screen_size = 2 << 20;
1238 break;
1239 case 1: /* 4MB */
1240 info->screen_size = 4 << 20;
1241 break;
1242 case 2: /* 6MB */
1243 info->screen_size = 6 << 20;
1244 break;
1245 case 3: /* 8MB */
1246 info->screen_size = 8 << 20;
1247 break;
1248 }
1249 /* off-screen memory */
1250 regval = vga_rcrt(par->state.vgabase, 0x37);
1251 switch ((regval & 0x60) >> 5) {
1252 case 1: /* 4MB */
1253 info->screen_size -= 4 << 20;
1254 break;
1255 case 2: /* 2MB */
1256 info->screen_size -= 2 << 20;
1257 break;
1258 }
1259 } else
1260 info->screen_size = s3_memsizes[regval >> 5] << 10;
1261 info->fix.smem_len = info->screen_size;
1262
1263 /* Find MCLK frequency */
1264 regval = vga_rseq(par->state.vgabase, 0x10);
1265 par->mclk_freq = ((vga_rseq(par->state.vgabase, 0x11) + 2) * 14318) / ((regval & 0x1F) + 2);
1266 par->mclk_freq = par->mclk_freq >> (regval >> 5);
1267
1268 /* Restore locks */
1269 vga_wcrt(par->state.vgabase, 0x38, cr38);
1270 vga_wcrt(par->state.vgabase, 0x39, cr39);
1271
1272 strcpy(info->fix.id, s3_names [par->chip]);
1273 info->fix.mmio_start = 0;
1274 info->fix.mmio_len = 0;
1275 info->fix.type = FB_TYPE_PACKED_PIXELS;
1276 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
1277 info->fix.ypanstep = 0;
1278 info->fix.accel = FB_ACCEL_NONE;
1279 info->pseudo_palette = (void*) (par->pseudo_palette);
1280 info->var.bits_per_pixel = 8;
1281
1282 #ifdef CONFIG_FB_S3_DDC
1283 /* Enable MMIO if needed */
1284 if (s3fb_ddc_needs_mmio(par->chip)) {
1285 par->mmio = ioremap(info->fix.smem_start + MMIO_OFFSET, MMIO_SIZE);
1286 if (par->mmio)
1287 svga_wcrt_mask(par->state.vgabase, 0x53, 0x08, 0x08); /* enable MMIO */
1288 else
1289 dev_err(info->device, "unable to map MMIO at 0x%lx, disabling DDC",
1290 info->fix.smem_start + MMIO_OFFSET);
1291 }
1292 if (!s3fb_ddc_needs_mmio(par->chip) || par->mmio)
1293 if (s3fb_setup_ddc_bus(info) == 0) {
1294 u8 *edid = fb_ddc_read(&par->ddc_adapter);
1295 par->ddc_registered = true;
1296 if (edid) {
1297 fb_edid_to_monspecs(edid, &info->monspecs);
1298 kfree(edid);
1299 if (!info->monspecs.modedb)
1300 dev_err(info->device, "error getting mode database\n");
1301 else {
1302 const struct fb_videomode *m;
1303
1304 fb_videomode_to_modelist(info->monspecs.modedb,
1305 info->monspecs.modedb_len,
1306 &info->modelist);
1307 m = fb_find_best_display(&info->monspecs, &info->modelist);
1308 if (m) {
1309 fb_videomode_to_var(&info->var, m);
1310 /* fill all other info->var's fields */
1311 if (s3fb_check_var(&info->var, info) == 0)
1312 found = true;
1313 }
1314 }
1315 }
1316 }
1317 #endif
1318 if (!mode_option && !found)
1319 mode_option = "640x480-8@60";
1320
1321 /* Prepare startup mode */
1322 if (mode_option) {
1323 rc = fb_find_mode(&info->var, info, mode_option,
1324 info->monspecs.modedb, info->monspecs.modedb_len,
1325 NULL, info->var.bits_per_pixel);
1326 if (!rc || rc == 4) {
1327 rc = -EINVAL;
1328 dev_err(info->device, "mode %s not found\n", mode_option);
1329 fb_destroy_modedb(info->monspecs.modedb);
1330 info->monspecs.modedb = NULL;
1331 goto err_find_mode;
1332 }
1333 }
1334
1335 fb_destroy_modedb(info->monspecs.modedb);
1336 info->monspecs.modedb = NULL;
1337
1338 /* maximize virtual vertical size for fast scrolling */
1339 info->var.yres_virtual = info->fix.smem_len * 8 /
1340 (info->var.bits_per_pixel * info->var.xres_virtual);
1341 if (info->var.yres_virtual < info->var.yres) {
1342 dev_err(info->device, "virtual vertical size smaller than real\n");
1343 rc = -EINVAL;
1344 goto err_find_mode;
1345 }
1346
1347 rc = fb_alloc_cmap(&info->cmap, 256, 0);
1348 if (rc < 0) {
1349 dev_err(info->device, "cannot allocate colormap\n");
1350 goto err_alloc_cmap;
1351 }
1352
1353 rc = register_framebuffer(info);
1354 if (rc < 0) {
1355 dev_err(info->device, "cannot register framebuffer\n");
1356 goto err_reg_fb;
1357 }
1358
1359 fb_info(info, "%s on %s, %d MB RAM, %d MHz MCLK\n",
1360 info->fix.id, pci_name(dev),
1361 info->fix.smem_len >> 20, (par->mclk_freq + 500) / 1000);
1362
1363 if (par->chip == CHIP_UNKNOWN)
1364 fb_info(info, "unknown chip, CR2D=%x, CR2E=%x, CRT2F=%x, CRT30=%x\n",
1365 vga_rcrt(par->state.vgabase, 0x2d),
1366 vga_rcrt(par->state.vgabase, 0x2e),
1367 vga_rcrt(par->state.vgabase, 0x2f),
1368 vga_rcrt(par->state.vgabase, 0x30));
1369
1370 /* Record a reference to the driver data */
1371 pci_set_drvdata(dev, info);
1372
1373 if (mtrr)
1374 par->wc_cookie = arch_phys_wc_add(info->fix.smem_start,
1375 info->fix.smem_len);
1376
1377 return 0;
1378
1379 /* Error handling */
1380 err_reg_fb:
1381 fb_dealloc_cmap(&info->cmap);
1382 err_alloc_cmap:
1383 err_find_mode:
1384 #ifdef CONFIG_FB_S3_DDC
1385 if (par->ddc_registered)
1386 i2c_del_adapter(&par->ddc_adapter);
1387 if (par->mmio)
1388 iounmap(par->mmio);
1389 #endif
1390 pci_iounmap(dev, info->screen_base);
1391 err_iomap:
1392 pci_release_regions(dev);
1393 err_request_regions:
1394 /* pci_disable_device(dev); */
1395 err_enable_device:
1396 framebuffer_release(info);
1397 return rc;
1398 }
1399
1400
1401 /* PCI remove */
1402
s3_pci_remove(struct pci_dev * dev)1403 static void s3_pci_remove(struct pci_dev *dev)
1404 {
1405 struct fb_info *info = pci_get_drvdata(dev);
1406 struct s3fb_info __maybe_unused *par;
1407
1408 if (info) {
1409 par = info->par;
1410 arch_phys_wc_del(par->wc_cookie);
1411 unregister_framebuffer(info);
1412 fb_dealloc_cmap(&info->cmap);
1413
1414 #ifdef CONFIG_FB_S3_DDC
1415 if (par->ddc_registered)
1416 i2c_del_adapter(&par->ddc_adapter);
1417 if (par->mmio)
1418 iounmap(par->mmio);
1419 #endif
1420
1421 pci_iounmap(dev, info->screen_base);
1422 pci_release_regions(dev);
1423 /* pci_disable_device(dev); */
1424
1425 framebuffer_release(info);
1426 }
1427 }
1428
1429 /* PCI suspend */
1430
s3_pci_suspend(struct device * dev)1431 static int __maybe_unused s3_pci_suspend(struct device *dev)
1432 {
1433 struct fb_info *info = dev_get_drvdata(dev);
1434 struct s3fb_info *par = info->par;
1435
1436 dev_info(info->device, "suspend\n");
1437
1438 console_lock();
1439 mutex_lock(&(par->open_lock));
1440
1441 if (par->ref_count == 0) {
1442 mutex_unlock(&(par->open_lock));
1443 console_unlock();
1444 return 0;
1445 }
1446
1447 fb_set_suspend(info, 1);
1448
1449 mutex_unlock(&(par->open_lock));
1450 console_unlock();
1451
1452 return 0;
1453 }
1454
1455
1456 /* PCI resume */
1457
s3_pci_resume(struct device * dev)1458 static int __maybe_unused s3_pci_resume(struct device *dev)
1459 {
1460 struct fb_info *info = dev_get_drvdata(dev);
1461 struct s3fb_info *par = info->par;
1462
1463 dev_info(info->device, "resume\n");
1464
1465 console_lock();
1466 mutex_lock(&(par->open_lock));
1467
1468 if (par->ref_count == 0) {
1469 mutex_unlock(&(par->open_lock));
1470 console_unlock();
1471 return 0;
1472 }
1473
1474 s3fb_set_par(info);
1475 fb_set_suspend(info, 0);
1476
1477 mutex_unlock(&(par->open_lock));
1478 console_unlock();
1479
1480 return 0;
1481 }
1482
1483 static const struct dev_pm_ops s3_pci_pm_ops = {
1484 #ifdef CONFIG_PM_SLEEP
1485 .suspend = s3_pci_suspend,
1486 .resume = s3_pci_resume,
1487 .freeze = NULL,
1488 .thaw = s3_pci_resume,
1489 .poweroff = s3_pci_suspend,
1490 .restore = s3_pci_resume,
1491 #endif
1492 };
1493
1494 /* List of boards that we are trying to support */
1495
1496 static const struct pci_device_id s3_devices[] = {
1497 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8810), .driver_data = CHIP_XXX_TRIO},
1498 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8811), .driver_data = CHIP_XXX_TRIO},
1499 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8812), .driver_data = CHIP_M65_AURORA64VP},
1500 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8814), .driver_data = CHIP_767_TRIO64UVP},
1501 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8901), .driver_data = CHIP_XXX_TRIO64V2_DXGX},
1502 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8902), .driver_data = CHIP_551_PLATO_PX},
1503
1504 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x5631), .driver_data = CHIP_325_VIRGE},
1505 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x883D), .driver_data = CHIP_988_VIRGE_VX},
1506 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A01), .driver_data = CHIP_XXX_VIRGE_DXGX},
1507 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A10), .driver_data = CHIP_357_VIRGE_GX2},
1508 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A11), .driver_data = CHIP_359_VIRGE_GX2P},
1509 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A12), .driver_data = CHIP_359_VIRGE_GX2P},
1510 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A13), .driver_data = CHIP_36X_TRIO3D_1X_2X},
1511 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8904), .driver_data = CHIP_365_TRIO3D},
1512 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8C01), .driver_data = CHIP_260_VIRGE_MX},
1513
1514 {0, 0, 0, 0, 0, 0, 0}
1515 };
1516
1517
1518 MODULE_DEVICE_TABLE(pci, s3_devices);
1519
1520 static struct pci_driver s3fb_pci_driver = {
1521 .name = "s3fb",
1522 .id_table = s3_devices,
1523 .probe = s3_pci_probe,
1524 .remove = s3_pci_remove,
1525 .driver.pm = &s3_pci_pm_ops,
1526 };
1527
1528 /* Parse user specified options */
1529
1530 #ifndef MODULE
s3fb_setup(char * options)1531 static int __init s3fb_setup(char *options)
1532 {
1533 char *opt;
1534
1535 if (!options || !*options)
1536 return 0;
1537
1538 while ((opt = strsep(&options, ",")) != NULL) {
1539
1540 if (!*opt)
1541 continue;
1542 else if (!strncmp(opt, "mtrr:", 5))
1543 mtrr = simple_strtoul(opt + 5, NULL, 0);
1544 else if (!strncmp(opt, "fasttext:", 9))
1545 fasttext = simple_strtoul(opt + 9, NULL, 0);
1546 else
1547 mode_option = opt;
1548 }
1549
1550 return 0;
1551 }
1552 #endif
1553
1554 /* Cleanup */
1555
s3fb_cleanup(void)1556 static void __exit s3fb_cleanup(void)
1557 {
1558 pr_debug("s3fb: cleaning up\n");
1559 pci_unregister_driver(&s3fb_pci_driver);
1560 }
1561
1562 /* Driver Initialisation */
1563
s3fb_init(void)1564 static int __init s3fb_init(void)
1565 {
1566
1567 #ifndef MODULE
1568 char *option = NULL;
1569 #endif
1570
1571 if (fb_modesetting_disabled("s3fb"))
1572 return -ENODEV;
1573
1574 #ifndef MODULE
1575 if (fb_get_options("s3fb", &option))
1576 return -ENODEV;
1577 s3fb_setup(option);
1578 #endif
1579
1580 pr_debug("s3fb: initializing\n");
1581 return pci_register_driver(&s3fb_pci_driver);
1582 }
1583
1584 /* ------------------------------------------------------------------------- */
1585
1586 /* Modularization */
1587
1588 module_init(s3fb_init);
1589 module_exit(s3fb_cleanup);
1590