1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * RZ/V2N System controller (SYS) driver
4 *
5 * Copyright (C) 2025 Renesas Electronics Corp.
6 */
7
8 #include <linux/bitfield.h>
9 #include <linux/bits.h>
10 #include <linux/device.h>
11 #include <linux/init.h>
12 #include <linux/io.h>
13
14 #include "rz-sysc.h"
15
16 /* Register Offsets */
17 #define SYS_LSI_MODE 0x300
18 #define SYS_LSI_MODE_SEC_EN BIT(16)
19 /*
20 * BOOTPLLCA[1:0]
21 * [0,0] => 1.1GHZ
22 * [0,1] => 1.5GHZ
23 * [1,0] => 1.6GHZ
24 * [1,1] => 1.7GHZ
25 */
26 #define SYS_LSI_MODE_STAT_BOOTPLLCA55 GENMASK(12, 11)
27 #define SYS_LSI_MODE_CA55_1_7GHZ 0x3
28
29 #define SYS_LSI_PRR 0x308
30 #define SYS_LSI_PRR_GPU_DIS BIT(0)
31 #define SYS_LSI_PRR_ISP_DIS BIT(4)
32
33 #define SYS_RZV2N_FEATURE_G31 BIT(0)
34 #define SYS_RZV2N_FEATURE_C55 BIT(1)
35 #define SYS_RZV2N_FEATURE_SEC BIT(2)
36
rzv2n_sys_print_id(struct device * dev,void __iomem * sysc_base,struct soc_device_attribute * soc_dev_attr)37 static void rzv2n_sys_print_id(struct device *dev,
38 void __iomem *sysc_base,
39 struct soc_device_attribute *soc_dev_attr)
40 {
41 u32 prr_val, mode_val;
42 u8 feature_flags;
43
44 prr_val = readl(sysc_base + SYS_LSI_PRR);
45 mode_val = readl(sysc_base + SYS_LSI_MODE);
46
47 /* Check GPU, ISP and Cryptographic configuration */
48 feature_flags = !(prr_val & SYS_LSI_PRR_GPU_DIS) ? SYS_RZV2N_FEATURE_G31 : 0;
49 feature_flags |= !(prr_val & SYS_LSI_PRR_ISP_DIS) ? SYS_RZV2N_FEATURE_C55 : 0;
50 feature_flags |= (mode_val & SYS_LSI_MODE_SEC_EN) ? SYS_RZV2N_FEATURE_SEC : 0;
51
52 dev_info(dev, "Detected Renesas %s %sn%d Rev %s%s%s%s%s\n", soc_dev_attr->family,
53 soc_dev_attr->soc_id, 41 + feature_flags, soc_dev_attr->revision,
54 feature_flags ? " with" : "",
55 feature_flags & SYS_RZV2N_FEATURE_G31 ? " GE3D (Mali-G31)" : "",
56 feature_flags & SYS_RZV2N_FEATURE_SEC ? " Cryptographic engine" : "",
57 feature_flags & SYS_RZV2N_FEATURE_C55 ? " ISP (Mali-C55)" : "");
58
59 /* Check CA55 PLL configuration */
60 if (FIELD_GET(SYS_LSI_MODE_STAT_BOOTPLLCA55, mode_val) != SYS_LSI_MODE_CA55_1_7GHZ)
61 dev_warn(dev, "CA55 PLL is not set to 1.7GHz\n");
62 }
63
64 static const struct rz_sysc_soc_id_init_data rzv2n_sys_soc_id_init_data __initconst = {
65 .family = "RZ/V2N",
66 .id = 0x867d447,
67 .devid_offset = 0x304,
68 .revision_mask = GENMASK(31, 28),
69 .specific_id_mask = GENMASK(27, 0),
70 .print_id = rzv2n_sys_print_id,
71 };
72
73 const struct rz_sysc_init_data rzv2n_sys_init_data = {
74 .soc_id_init_data = &rzv2n_sys_soc_id_init_data,
75 };
76