xref: /linux/drivers/net/can/m_can/m_can.c (revision 442bc81bd344dc52c37d8f80b854cc6da062b2d0)
1 // SPDX-License-Identifier: GPL-2.0
2 // CAN bus driver for Bosch M_CAN controller
3 // Copyright (C) 2014 Freescale Semiconductor, Inc.
4 //      Dong Aisheng <b29396@freescale.com>
5 // Copyright (C) 2018-19 Texas Instruments Incorporated - http://www.ti.com/
6 
7 /* Bosch M_CAN user manual can be obtained from:
8  * https://github.com/linux-can/can-doc/tree/master/m_can
9  */
10 
11 #include <linux/bitfield.h>
12 #include <linux/can/dev.h>
13 #include <linux/ethtool.h>
14 #include <linux/hrtimer.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/iopoll.h>
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/netdevice.h>
21 #include <linux/of.h>
22 #include <linux/phy/phy.h>
23 #include <linux/pinctrl/consumer.h>
24 #include <linux/platform_device.h>
25 #include <linux/pm_runtime.h>
26 
27 #include "m_can.h"
28 
29 /* registers definition */
30 enum m_can_reg {
31 	M_CAN_CREL	= 0x0,
32 	M_CAN_ENDN	= 0x4,
33 	M_CAN_CUST	= 0x8,
34 	M_CAN_DBTP	= 0xc,
35 	M_CAN_TEST	= 0x10,
36 	M_CAN_RWD	= 0x14,
37 	M_CAN_CCCR	= 0x18,
38 	M_CAN_NBTP	= 0x1c,
39 	M_CAN_TSCC	= 0x20,
40 	M_CAN_TSCV	= 0x24,
41 	M_CAN_TOCC	= 0x28,
42 	M_CAN_TOCV	= 0x2c,
43 	M_CAN_ECR	= 0x40,
44 	M_CAN_PSR	= 0x44,
45 	/* TDCR Register only available for version >=3.1.x */
46 	M_CAN_TDCR	= 0x48,
47 	M_CAN_IR	= 0x50,
48 	M_CAN_IE	= 0x54,
49 	M_CAN_ILS	= 0x58,
50 	M_CAN_ILE	= 0x5c,
51 	M_CAN_GFC	= 0x80,
52 	M_CAN_SIDFC	= 0x84,
53 	M_CAN_XIDFC	= 0x88,
54 	M_CAN_XIDAM	= 0x90,
55 	M_CAN_HPMS	= 0x94,
56 	M_CAN_NDAT1	= 0x98,
57 	M_CAN_NDAT2	= 0x9c,
58 	M_CAN_RXF0C	= 0xa0,
59 	M_CAN_RXF0S	= 0xa4,
60 	M_CAN_RXF0A	= 0xa8,
61 	M_CAN_RXBC	= 0xac,
62 	M_CAN_RXF1C	= 0xb0,
63 	M_CAN_RXF1S	= 0xb4,
64 	M_CAN_RXF1A	= 0xb8,
65 	M_CAN_RXESC	= 0xbc,
66 	M_CAN_TXBC	= 0xc0,
67 	M_CAN_TXFQS	= 0xc4,
68 	M_CAN_TXESC	= 0xc8,
69 	M_CAN_TXBRP	= 0xcc,
70 	M_CAN_TXBAR	= 0xd0,
71 	M_CAN_TXBCR	= 0xd4,
72 	M_CAN_TXBTO	= 0xd8,
73 	M_CAN_TXBCF	= 0xdc,
74 	M_CAN_TXBTIE	= 0xe0,
75 	M_CAN_TXBCIE	= 0xe4,
76 	M_CAN_TXEFC	= 0xf0,
77 	M_CAN_TXEFS	= 0xf4,
78 	M_CAN_TXEFA	= 0xf8,
79 };
80 
81 /* message ram configuration data length */
82 #define MRAM_CFG_LEN	8
83 
84 /* Core Release Register (CREL) */
85 #define CREL_REL_MASK		GENMASK(31, 28)
86 #define CREL_STEP_MASK		GENMASK(27, 24)
87 #define CREL_SUBSTEP_MASK	GENMASK(23, 20)
88 
89 /* Data Bit Timing & Prescaler Register (DBTP) */
90 #define DBTP_TDC		BIT(23)
91 #define DBTP_DBRP_MASK		GENMASK(20, 16)
92 #define DBTP_DTSEG1_MASK	GENMASK(12, 8)
93 #define DBTP_DTSEG2_MASK	GENMASK(7, 4)
94 #define DBTP_DSJW_MASK		GENMASK(3, 0)
95 
96 /* Transmitter Delay Compensation Register (TDCR) */
97 #define TDCR_TDCO_MASK		GENMASK(14, 8)
98 #define TDCR_TDCF_MASK		GENMASK(6, 0)
99 
100 /* Test Register (TEST) */
101 #define TEST_LBCK		BIT(4)
102 
103 /* CC Control Register (CCCR) */
104 #define CCCR_TXP		BIT(14)
105 #define CCCR_TEST		BIT(7)
106 #define CCCR_DAR		BIT(6)
107 #define CCCR_MON		BIT(5)
108 #define CCCR_CSR		BIT(4)
109 #define CCCR_CSA		BIT(3)
110 #define CCCR_ASM		BIT(2)
111 #define CCCR_CCE		BIT(1)
112 #define CCCR_INIT		BIT(0)
113 /* for version 3.0.x */
114 #define CCCR_CMR_MASK		GENMASK(11, 10)
115 #define CCCR_CMR_CANFD		0x1
116 #define CCCR_CMR_CANFD_BRS	0x2
117 #define CCCR_CMR_CAN		0x3
118 #define CCCR_CME_MASK		GENMASK(9, 8)
119 #define CCCR_CME_CAN		0
120 #define CCCR_CME_CANFD		0x1
121 #define CCCR_CME_CANFD_BRS	0x2
122 /* for version >=3.1.x */
123 #define CCCR_EFBI		BIT(13)
124 #define CCCR_PXHD		BIT(12)
125 #define CCCR_BRSE		BIT(9)
126 #define CCCR_FDOE		BIT(8)
127 /* for version >=3.2.x */
128 #define CCCR_NISO		BIT(15)
129 /* for version >=3.3.x */
130 #define CCCR_WMM		BIT(11)
131 #define CCCR_UTSU		BIT(10)
132 
133 /* Nominal Bit Timing & Prescaler Register (NBTP) */
134 #define NBTP_NSJW_MASK		GENMASK(31, 25)
135 #define NBTP_NBRP_MASK		GENMASK(24, 16)
136 #define NBTP_NTSEG1_MASK	GENMASK(15, 8)
137 #define NBTP_NTSEG2_MASK	GENMASK(6, 0)
138 
139 /* Timestamp Counter Configuration Register (TSCC) */
140 #define TSCC_TCP_MASK		GENMASK(19, 16)
141 #define TSCC_TSS_MASK		GENMASK(1, 0)
142 #define TSCC_TSS_DISABLE	0x0
143 #define TSCC_TSS_INTERNAL	0x1
144 #define TSCC_TSS_EXTERNAL	0x2
145 
146 /* Timestamp Counter Value Register (TSCV) */
147 #define TSCV_TSC_MASK		GENMASK(15, 0)
148 
149 /* Error Counter Register (ECR) */
150 #define ECR_RP			BIT(15)
151 #define ECR_REC_MASK		GENMASK(14, 8)
152 #define ECR_TEC_MASK		GENMASK(7, 0)
153 
154 /* Protocol Status Register (PSR) */
155 #define PSR_BO		BIT(7)
156 #define PSR_EW		BIT(6)
157 #define PSR_EP		BIT(5)
158 #define PSR_LEC_MASK	GENMASK(2, 0)
159 #define PSR_DLEC_MASK	GENMASK(10, 8)
160 
161 /* Interrupt Register (IR) */
162 #define IR_ALL_INT	0xffffffff
163 
164 /* Renamed bits for versions > 3.1.x */
165 #define IR_ARA		BIT(29)
166 #define IR_PED		BIT(28)
167 #define IR_PEA		BIT(27)
168 
169 /* Bits for version 3.0.x */
170 #define IR_STE		BIT(31)
171 #define IR_FOE		BIT(30)
172 #define IR_ACKE		BIT(29)
173 #define IR_BE		BIT(28)
174 #define IR_CRCE		BIT(27)
175 #define IR_WDI		BIT(26)
176 #define IR_BO		BIT(25)
177 #define IR_EW		BIT(24)
178 #define IR_EP		BIT(23)
179 #define IR_ELO		BIT(22)
180 #define IR_BEU		BIT(21)
181 #define IR_BEC		BIT(20)
182 #define IR_DRX		BIT(19)
183 #define IR_TOO		BIT(18)
184 #define IR_MRAF		BIT(17)
185 #define IR_TSW		BIT(16)
186 #define IR_TEFL		BIT(15)
187 #define IR_TEFF		BIT(14)
188 #define IR_TEFW		BIT(13)
189 #define IR_TEFN		BIT(12)
190 #define IR_TFE		BIT(11)
191 #define IR_TCF		BIT(10)
192 #define IR_TC		BIT(9)
193 #define IR_HPM		BIT(8)
194 #define IR_RF1L		BIT(7)
195 #define IR_RF1F		BIT(6)
196 #define IR_RF1W		BIT(5)
197 #define IR_RF1N		BIT(4)
198 #define IR_RF0L		BIT(3)
199 #define IR_RF0F		BIT(2)
200 #define IR_RF0W		BIT(1)
201 #define IR_RF0N		BIT(0)
202 #define IR_ERR_STATE	(IR_BO | IR_EW | IR_EP)
203 
204 /* Interrupts for version 3.0.x */
205 #define IR_ERR_LEC_30X	(IR_STE	| IR_FOE | IR_ACKE | IR_BE | IR_CRCE)
206 #define IR_ERR_BUS_30X	(IR_ERR_LEC_30X | IR_WDI | IR_BEU | IR_BEC | \
207 			 IR_TOO | IR_MRAF | IR_TSW | IR_TEFL | IR_RF1L | \
208 			 IR_RF0L)
209 #define IR_ERR_ALL_30X	(IR_ERR_STATE | IR_ERR_BUS_30X)
210 
211 /* Interrupts for version >= 3.1.x */
212 #define IR_ERR_LEC_31X	(IR_PED | IR_PEA)
213 #define IR_ERR_BUS_31X	(IR_ERR_LEC_31X | IR_WDI | IR_BEU | IR_BEC | \
214 			 IR_TOO | IR_MRAF | IR_TSW | IR_TEFL | IR_RF1L | \
215 			 IR_RF0L)
216 #define IR_ERR_ALL_31X	(IR_ERR_STATE | IR_ERR_BUS_31X)
217 
218 /* Interrupt Line Select (ILS) */
219 #define ILS_ALL_INT0	0x0
220 #define ILS_ALL_INT1	0xFFFFFFFF
221 
222 /* Interrupt Line Enable (ILE) */
223 #define ILE_EINT1	BIT(1)
224 #define ILE_EINT0	BIT(0)
225 
226 /* Rx FIFO 0/1 Configuration (RXF0C/RXF1C) */
227 #define RXFC_FWM_MASK	GENMASK(30, 24)
228 #define RXFC_FS_MASK	GENMASK(22, 16)
229 
230 /* Rx FIFO 0/1 Status (RXF0S/RXF1S) */
231 #define RXFS_RFL	BIT(25)
232 #define RXFS_FF		BIT(24)
233 #define RXFS_FPI_MASK	GENMASK(21, 16)
234 #define RXFS_FGI_MASK	GENMASK(13, 8)
235 #define RXFS_FFL_MASK	GENMASK(6, 0)
236 
237 /* Rx Buffer / FIFO Element Size Configuration (RXESC) */
238 #define RXESC_RBDS_MASK		GENMASK(10, 8)
239 #define RXESC_F1DS_MASK		GENMASK(6, 4)
240 #define RXESC_F0DS_MASK		GENMASK(2, 0)
241 #define RXESC_64B		0x7
242 
243 /* Tx Buffer Configuration (TXBC) */
244 #define TXBC_TFQS_MASK		GENMASK(29, 24)
245 #define TXBC_NDTB_MASK		GENMASK(21, 16)
246 
247 /* Tx FIFO/Queue Status (TXFQS) */
248 #define TXFQS_TFQF		BIT(21)
249 #define TXFQS_TFQPI_MASK	GENMASK(20, 16)
250 #define TXFQS_TFGI_MASK		GENMASK(12, 8)
251 #define TXFQS_TFFL_MASK		GENMASK(5, 0)
252 
253 /* Tx Buffer Element Size Configuration (TXESC) */
254 #define TXESC_TBDS_MASK		GENMASK(2, 0)
255 #define TXESC_TBDS_64B		0x7
256 
257 /* Tx Event FIFO Configuration (TXEFC) */
258 #define TXEFC_EFWM_MASK		GENMASK(29, 24)
259 #define TXEFC_EFS_MASK		GENMASK(21, 16)
260 
261 /* Tx Event FIFO Status (TXEFS) */
262 #define TXEFS_TEFL		BIT(25)
263 #define TXEFS_EFF		BIT(24)
264 #define TXEFS_EFGI_MASK		GENMASK(12, 8)
265 #define TXEFS_EFFL_MASK		GENMASK(5, 0)
266 
267 /* Tx Event FIFO Acknowledge (TXEFA) */
268 #define TXEFA_EFAI_MASK		GENMASK(4, 0)
269 
270 /* Message RAM Configuration (in bytes) */
271 #define SIDF_ELEMENT_SIZE	4
272 #define XIDF_ELEMENT_SIZE	8
273 #define RXF0_ELEMENT_SIZE	72
274 #define RXF1_ELEMENT_SIZE	72
275 #define RXB_ELEMENT_SIZE	72
276 #define TXE_ELEMENT_SIZE	8
277 #define TXB_ELEMENT_SIZE	72
278 
279 /* Message RAM Elements */
280 #define M_CAN_FIFO_ID		0x0
281 #define M_CAN_FIFO_DLC		0x4
282 #define M_CAN_FIFO_DATA		0x8
283 
284 /* Rx Buffer Element */
285 /* R0 */
286 #define RX_BUF_ESI		BIT(31)
287 #define RX_BUF_XTD		BIT(30)
288 #define RX_BUF_RTR		BIT(29)
289 /* R1 */
290 #define RX_BUF_ANMF		BIT(31)
291 #define RX_BUF_FDF		BIT(21)
292 #define RX_BUF_BRS		BIT(20)
293 #define RX_BUF_RXTS_MASK	GENMASK(15, 0)
294 
295 /* Tx Buffer Element */
296 /* T0 */
297 #define TX_BUF_ESI		BIT(31)
298 #define TX_BUF_XTD		BIT(30)
299 #define TX_BUF_RTR		BIT(29)
300 /* T1 */
301 #define TX_BUF_EFC		BIT(23)
302 #define TX_BUF_FDF		BIT(21)
303 #define TX_BUF_BRS		BIT(20)
304 #define TX_BUF_MM_MASK		GENMASK(31, 24)
305 #define TX_BUF_DLC_MASK		GENMASK(19, 16)
306 
307 /* Tx event FIFO Element */
308 /* E1 */
309 #define TX_EVENT_MM_MASK	GENMASK(31, 24)
310 #define TX_EVENT_TXTS_MASK	GENMASK(15, 0)
311 
312 /* Hrtimer polling interval */
313 #define HRTIMER_POLL_INTERVAL_MS		1
314 
315 /* The ID and DLC registers are adjacent in M_CAN FIFO memory,
316  * and we can save a (potentially slow) bus round trip by combining
317  * reads and writes to them.
318  */
319 struct id_and_dlc {
320 	u32 id;
321 	u32 dlc;
322 };
323 
324 struct m_can_fifo_element {
325 	u32 id;
326 	u32 dlc;
327 	u8 data[CANFD_MAX_DLEN];
328 };
329 
m_can_read(struct m_can_classdev * cdev,enum m_can_reg reg)330 static inline u32 m_can_read(struct m_can_classdev *cdev, enum m_can_reg reg)
331 {
332 	return cdev->ops->read_reg(cdev, reg);
333 }
334 
m_can_write(struct m_can_classdev * cdev,enum m_can_reg reg,u32 val)335 static inline void m_can_write(struct m_can_classdev *cdev, enum m_can_reg reg,
336 			       u32 val)
337 {
338 	cdev->ops->write_reg(cdev, reg, val);
339 }
340 
341 static int
m_can_fifo_read(struct m_can_classdev * cdev,u32 fgi,unsigned int offset,void * val,size_t val_count)342 m_can_fifo_read(struct m_can_classdev *cdev,
343 		u32 fgi, unsigned int offset, void *val, size_t val_count)
344 {
345 	u32 addr_offset = cdev->mcfg[MRAM_RXF0].off + fgi * RXF0_ELEMENT_SIZE +
346 		offset;
347 
348 	if (val_count == 0)
349 		return 0;
350 
351 	return cdev->ops->read_fifo(cdev, addr_offset, val, val_count);
352 }
353 
354 static int
m_can_fifo_write(struct m_can_classdev * cdev,u32 fpi,unsigned int offset,const void * val,size_t val_count)355 m_can_fifo_write(struct m_can_classdev *cdev,
356 		 u32 fpi, unsigned int offset, const void *val, size_t val_count)
357 {
358 	u32 addr_offset = cdev->mcfg[MRAM_TXB].off + fpi * TXB_ELEMENT_SIZE +
359 		offset;
360 
361 	if (val_count == 0)
362 		return 0;
363 
364 	return cdev->ops->write_fifo(cdev, addr_offset, val, val_count);
365 }
366 
m_can_fifo_write_no_off(struct m_can_classdev * cdev,u32 fpi,u32 val)367 static inline int m_can_fifo_write_no_off(struct m_can_classdev *cdev,
368 					  u32 fpi, u32 val)
369 {
370 	return cdev->ops->write_fifo(cdev, fpi, &val, 1);
371 }
372 
373 static int
m_can_txe_fifo_read(struct m_can_classdev * cdev,u32 fgi,u32 offset,u32 * val)374 m_can_txe_fifo_read(struct m_can_classdev *cdev, u32 fgi, u32 offset, u32 *val)
375 {
376 	u32 addr_offset = cdev->mcfg[MRAM_TXE].off + fgi * TXE_ELEMENT_SIZE +
377 		offset;
378 
379 	return cdev->ops->read_fifo(cdev, addr_offset, val, 1);
380 }
381 
m_can_cccr_update_bits(struct m_can_classdev * cdev,u32 mask,u32 val)382 static int m_can_cccr_update_bits(struct m_can_classdev *cdev, u32 mask, u32 val)
383 {
384 	u32 val_before = m_can_read(cdev, M_CAN_CCCR);
385 	u32 val_after = (val_before & ~mask) | val;
386 	size_t tries = 10;
387 
388 	if (!(mask & CCCR_INIT) && !(val_before & CCCR_INIT)) {
389 		dev_err(cdev->dev,
390 			"refusing to configure device when in normal mode\n");
391 		return -EBUSY;
392 	}
393 
394 	/* The chip should be in standby mode when changing the CCCR register,
395 	 * and some chips set the CSR and CSA bits when in standby. Furthermore,
396 	 * the CSR and CSA bits should be written as zeros, even when they read
397 	 * ones.
398 	 */
399 	val_after &= ~(CCCR_CSR | CCCR_CSA);
400 
401 	while (tries--) {
402 		u32 val_read;
403 
404 		/* Write the desired value in each try, as setting some bits in
405 		 * the CCCR register require other bits to be set first. E.g.
406 		 * setting the NISO bit requires setting the CCE bit first.
407 		 */
408 		m_can_write(cdev, M_CAN_CCCR, val_after);
409 
410 		val_read = m_can_read(cdev, M_CAN_CCCR) & ~(CCCR_CSR | CCCR_CSA);
411 
412 		if (val_read == val_after)
413 			return 0;
414 
415 		usleep_range(1, 5);
416 	}
417 
418 	return -ETIMEDOUT;
419 }
420 
m_can_config_enable(struct m_can_classdev * cdev)421 static int m_can_config_enable(struct m_can_classdev *cdev)
422 {
423 	int err;
424 
425 	/* CCCR_INIT must be set in order to set CCCR_CCE, but access to
426 	 * configuration registers should only be enabled when in standby mode,
427 	 * where CCCR_INIT is always set.
428 	 */
429 	err = m_can_cccr_update_bits(cdev, CCCR_CCE, CCCR_CCE);
430 	if (err)
431 		netdev_err(cdev->net, "failed to enable configuration mode\n");
432 
433 	return err;
434 }
435 
m_can_config_disable(struct m_can_classdev * cdev)436 static int m_can_config_disable(struct m_can_classdev *cdev)
437 {
438 	int err;
439 
440 	/* Only clear CCCR_CCE, since CCCR_INIT cannot be cleared while in
441 	 * standby mode
442 	 */
443 	err = m_can_cccr_update_bits(cdev, CCCR_CCE, 0);
444 	if (err)
445 		netdev_err(cdev->net, "failed to disable configuration registers\n");
446 
447 	return err;
448 }
449 
m_can_interrupt_enable(struct m_can_classdev * cdev,u32 interrupts)450 static void m_can_interrupt_enable(struct m_can_classdev *cdev, u32 interrupts)
451 {
452 	if (cdev->active_interrupts == interrupts)
453 		return;
454 	cdev->ops->write_reg(cdev, M_CAN_IE, interrupts);
455 	cdev->active_interrupts = interrupts;
456 }
457 
m_can_coalescing_disable(struct m_can_classdev * cdev)458 static void m_can_coalescing_disable(struct m_can_classdev *cdev)
459 {
460 	u32 new_interrupts = cdev->active_interrupts | IR_RF0N | IR_TEFN;
461 
462 	if (!cdev->net->irq)
463 		return;
464 
465 	hrtimer_cancel(&cdev->hrtimer);
466 	m_can_interrupt_enable(cdev, new_interrupts);
467 }
468 
m_can_enable_all_interrupts(struct m_can_classdev * cdev)469 static inline void m_can_enable_all_interrupts(struct m_can_classdev *cdev)
470 {
471 	if (!cdev->net->irq) {
472 		dev_dbg(cdev->dev, "Start hrtimer\n");
473 		hrtimer_start(&cdev->hrtimer,
474 			      ms_to_ktime(HRTIMER_POLL_INTERVAL_MS),
475 			      HRTIMER_MODE_REL_PINNED);
476 	}
477 
478 	/* Only interrupt line 0 is used in this driver */
479 	m_can_write(cdev, M_CAN_ILE, ILE_EINT0);
480 }
481 
m_can_disable_all_interrupts(struct m_can_classdev * cdev)482 static inline void m_can_disable_all_interrupts(struct m_can_classdev *cdev)
483 {
484 	m_can_coalescing_disable(cdev);
485 	m_can_write(cdev, M_CAN_ILE, 0x0);
486 
487 	if (!cdev->net->irq) {
488 		dev_dbg(cdev->dev, "Stop hrtimer\n");
489 		hrtimer_try_to_cancel(&cdev->hrtimer);
490 	}
491 }
492 
493 /* Retrieve internal timestamp counter from TSCV.TSC, and shift it to 32-bit
494  * width.
495  */
m_can_get_timestamp(struct m_can_classdev * cdev)496 static u32 m_can_get_timestamp(struct m_can_classdev *cdev)
497 {
498 	u32 tscv;
499 	u32 tsc;
500 
501 	tscv = m_can_read(cdev, M_CAN_TSCV);
502 	tsc = FIELD_GET(TSCV_TSC_MASK, tscv);
503 
504 	return (tsc << 16);
505 }
506 
m_can_clean(struct net_device * net)507 static void m_can_clean(struct net_device *net)
508 {
509 	struct m_can_classdev *cdev = netdev_priv(net);
510 	unsigned long irqflags;
511 
512 	if (cdev->tx_ops) {
513 		for (int i = 0; i != cdev->tx_fifo_size; ++i) {
514 			if (!cdev->tx_ops[i].skb)
515 				continue;
516 
517 			net->stats.tx_errors++;
518 			cdev->tx_ops[i].skb = NULL;
519 		}
520 	}
521 
522 	for (int i = 0; i != cdev->can.echo_skb_max; ++i)
523 		can_free_echo_skb(cdev->net, i, NULL);
524 
525 	netdev_reset_queue(cdev->net);
526 
527 	spin_lock_irqsave(&cdev->tx_handling_spinlock, irqflags);
528 	cdev->tx_fifo_in_flight = 0;
529 	spin_unlock_irqrestore(&cdev->tx_handling_spinlock, irqflags);
530 }
531 
532 /* For peripherals, pass skb to rx-offload, which will push skb from
533  * napi. For non-peripherals, RX is done in napi already, so push
534  * directly. timestamp is used to ensure good skb ordering in
535  * rx-offload and is ignored for non-peripherals.
536  */
m_can_receive_skb(struct m_can_classdev * cdev,struct sk_buff * skb,u32 timestamp)537 static void m_can_receive_skb(struct m_can_classdev *cdev,
538 			      struct sk_buff *skb,
539 			      u32 timestamp)
540 {
541 	if (cdev->is_peripheral) {
542 		struct net_device_stats *stats = &cdev->net->stats;
543 		int err;
544 
545 		err = can_rx_offload_queue_timestamp(&cdev->offload, skb,
546 						     timestamp);
547 		if (err)
548 			stats->rx_fifo_errors++;
549 	} else {
550 		netif_receive_skb(skb);
551 	}
552 }
553 
m_can_read_fifo(struct net_device * dev,u32 fgi)554 static int m_can_read_fifo(struct net_device *dev, u32 fgi)
555 {
556 	struct net_device_stats *stats = &dev->stats;
557 	struct m_can_classdev *cdev = netdev_priv(dev);
558 	struct canfd_frame *cf;
559 	struct sk_buff *skb;
560 	struct id_and_dlc fifo_header;
561 	u32 timestamp = 0;
562 	int err;
563 
564 	err = m_can_fifo_read(cdev, fgi, M_CAN_FIFO_ID, &fifo_header, 2);
565 	if (err)
566 		goto out_fail;
567 
568 	if (fifo_header.dlc & RX_BUF_FDF)
569 		skb = alloc_canfd_skb(dev, &cf);
570 	else
571 		skb = alloc_can_skb(dev, (struct can_frame **)&cf);
572 	if (!skb) {
573 		stats->rx_dropped++;
574 		return 0;
575 	}
576 
577 	if (fifo_header.dlc & RX_BUF_FDF)
578 		cf->len = can_fd_dlc2len((fifo_header.dlc >> 16) & 0x0F);
579 	else
580 		cf->len = can_cc_dlc2len((fifo_header.dlc >> 16) & 0x0F);
581 
582 	if (fifo_header.id & RX_BUF_XTD)
583 		cf->can_id = (fifo_header.id & CAN_EFF_MASK) | CAN_EFF_FLAG;
584 	else
585 		cf->can_id = (fifo_header.id >> 18) & CAN_SFF_MASK;
586 
587 	if (fifo_header.id & RX_BUF_ESI) {
588 		cf->flags |= CANFD_ESI;
589 		netdev_dbg(dev, "ESI Error\n");
590 	}
591 
592 	if (!(fifo_header.dlc & RX_BUF_FDF) && (fifo_header.id & RX_BUF_RTR)) {
593 		cf->can_id |= CAN_RTR_FLAG;
594 	} else {
595 		if (fifo_header.dlc & RX_BUF_BRS)
596 			cf->flags |= CANFD_BRS;
597 
598 		err = m_can_fifo_read(cdev, fgi, M_CAN_FIFO_DATA,
599 				      cf->data, DIV_ROUND_UP(cf->len, 4));
600 		if (err)
601 			goto out_free_skb;
602 
603 		stats->rx_bytes += cf->len;
604 	}
605 	stats->rx_packets++;
606 
607 	timestamp = FIELD_GET(RX_BUF_RXTS_MASK, fifo_header.dlc) << 16;
608 
609 	m_can_receive_skb(cdev, skb, timestamp);
610 
611 	return 0;
612 
613 out_free_skb:
614 	kfree_skb(skb);
615 out_fail:
616 	netdev_err(dev, "FIFO read returned %d\n", err);
617 	return err;
618 }
619 
m_can_do_rx_poll(struct net_device * dev,int quota)620 static int m_can_do_rx_poll(struct net_device *dev, int quota)
621 {
622 	struct m_can_classdev *cdev = netdev_priv(dev);
623 	u32 pkts = 0;
624 	u32 rxfs;
625 	u32 rx_count;
626 	u32 fgi;
627 	int ack_fgi = -1;
628 	int i;
629 	int err = 0;
630 
631 	rxfs = m_can_read(cdev, M_CAN_RXF0S);
632 	if (!(rxfs & RXFS_FFL_MASK)) {
633 		netdev_dbg(dev, "no messages in fifo0\n");
634 		return 0;
635 	}
636 
637 	rx_count = FIELD_GET(RXFS_FFL_MASK, rxfs);
638 	fgi = FIELD_GET(RXFS_FGI_MASK, rxfs);
639 
640 	for (i = 0; i < rx_count && quota > 0; ++i) {
641 		err = m_can_read_fifo(dev, fgi);
642 		if (err)
643 			break;
644 
645 		quota--;
646 		pkts++;
647 		ack_fgi = fgi;
648 		fgi = (++fgi >= cdev->mcfg[MRAM_RXF0].num ? 0 : fgi);
649 	}
650 
651 	if (ack_fgi != -1)
652 		m_can_write(cdev, M_CAN_RXF0A, ack_fgi);
653 
654 	if (err)
655 		return err;
656 
657 	return pkts;
658 }
659 
m_can_handle_lost_msg(struct net_device * dev)660 static int m_can_handle_lost_msg(struct net_device *dev)
661 {
662 	struct m_can_classdev *cdev = netdev_priv(dev);
663 	struct net_device_stats *stats = &dev->stats;
664 	struct sk_buff *skb;
665 	struct can_frame *frame;
666 	u32 timestamp = 0;
667 
668 	netdev_err(dev, "msg lost in rxf0\n");
669 
670 	stats->rx_errors++;
671 	stats->rx_over_errors++;
672 
673 	skb = alloc_can_err_skb(dev, &frame);
674 	if (unlikely(!skb))
675 		return 0;
676 
677 	frame->can_id |= CAN_ERR_CRTL;
678 	frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
679 
680 	if (cdev->is_peripheral)
681 		timestamp = m_can_get_timestamp(cdev);
682 
683 	m_can_receive_skb(cdev, skb, timestamp);
684 
685 	return 1;
686 }
687 
m_can_handle_lec_err(struct net_device * dev,enum m_can_lec_type lec_type)688 static int m_can_handle_lec_err(struct net_device *dev,
689 				enum m_can_lec_type lec_type)
690 {
691 	struct m_can_classdev *cdev = netdev_priv(dev);
692 	struct net_device_stats *stats = &dev->stats;
693 	struct can_frame *cf;
694 	struct sk_buff *skb;
695 	u32 timestamp = 0;
696 
697 	cdev->can.can_stats.bus_error++;
698 
699 	/* propagate the error condition to the CAN stack */
700 	skb = alloc_can_err_skb(dev, &cf);
701 
702 	/* check for 'last error code' which tells us the
703 	 * type of the last error to occur on the CAN bus
704 	 */
705 	if (likely(skb))
706 		cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
707 
708 	switch (lec_type) {
709 	case LEC_STUFF_ERROR:
710 		netdev_dbg(dev, "stuff error\n");
711 		stats->rx_errors++;
712 		if (likely(skb))
713 			cf->data[2] |= CAN_ERR_PROT_STUFF;
714 		break;
715 	case LEC_FORM_ERROR:
716 		netdev_dbg(dev, "form error\n");
717 		stats->rx_errors++;
718 		if (likely(skb))
719 			cf->data[2] |= CAN_ERR_PROT_FORM;
720 		break;
721 	case LEC_ACK_ERROR:
722 		netdev_dbg(dev, "ack error\n");
723 		stats->tx_errors++;
724 		if (likely(skb))
725 			cf->data[3] = CAN_ERR_PROT_LOC_ACK;
726 		break;
727 	case LEC_BIT1_ERROR:
728 		netdev_dbg(dev, "bit1 error\n");
729 		stats->tx_errors++;
730 		if (likely(skb))
731 			cf->data[2] |= CAN_ERR_PROT_BIT1;
732 		break;
733 	case LEC_BIT0_ERROR:
734 		netdev_dbg(dev, "bit0 error\n");
735 		stats->tx_errors++;
736 		if (likely(skb))
737 			cf->data[2] |= CAN_ERR_PROT_BIT0;
738 		break;
739 	case LEC_CRC_ERROR:
740 		netdev_dbg(dev, "CRC error\n");
741 		stats->rx_errors++;
742 		if (likely(skb))
743 			cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
744 		break;
745 	default:
746 		break;
747 	}
748 
749 	if (unlikely(!skb))
750 		return 0;
751 
752 	if (cdev->is_peripheral)
753 		timestamp = m_can_get_timestamp(cdev);
754 
755 	m_can_receive_skb(cdev, skb, timestamp);
756 
757 	return 1;
758 }
759 
__m_can_get_berr_counter(const struct net_device * dev,struct can_berr_counter * bec)760 static int __m_can_get_berr_counter(const struct net_device *dev,
761 				    struct can_berr_counter *bec)
762 {
763 	struct m_can_classdev *cdev = netdev_priv(dev);
764 	unsigned int ecr;
765 
766 	ecr = m_can_read(cdev, M_CAN_ECR);
767 	bec->rxerr = FIELD_GET(ECR_REC_MASK, ecr);
768 	bec->txerr = FIELD_GET(ECR_TEC_MASK, ecr);
769 
770 	return 0;
771 }
772 
m_can_clk_start(struct m_can_classdev * cdev)773 static int m_can_clk_start(struct m_can_classdev *cdev)
774 {
775 	if (cdev->pm_clock_support == 0)
776 		return 0;
777 
778 	return pm_runtime_resume_and_get(cdev->dev);
779 }
780 
m_can_clk_stop(struct m_can_classdev * cdev)781 static void m_can_clk_stop(struct m_can_classdev *cdev)
782 {
783 	if (cdev->pm_clock_support)
784 		pm_runtime_put_sync(cdev->dev);
785 }
786 
m_can_get_berr_counter(const struct net_device * dev,struct can_berr_counter * bec)787 static int m_can_get_berr_counter(const struct net_device *dev,
788 				  struct can_berr_counter *bec)
789 {
790 	struct m_can_classdev *cdev = netdev_priv(dev);
791 	int err;
792 
793 	err = m_can_clk_start(cdev);
794 	if (err)
795 		return err;
796 
797 	__m_can_get_berr_counter(dev, bec);
798 
799 	m_can_clk_stop(cdev);
800 
801 	return 0;
802 }
803 
m_can_handle_state_change(struct net_device * dev,enum can_state new_state)804 static int m_can_handle_state_change(struct net_device *dev,
805 				     enum can_state new_state)
806 {
807 	struct m_can_classdev *cdev = netdev_priv(dev);
808 	struct can_frame *cf;
809 	struct sk_buff *skb;
810 	struct can_berr_counter bec;
811 	unsigned int ecr;
812 	u32 timestamp = 0;
813 
814 	switch (new_state) {
815 	case CAN_STATE_ERROR_WARNING:
816 		/* error warning state */
817 		cdev->can.can_stats.error_warning++;
818 		cdev->can.state = CAN_STATE_ERROR_WARNING;
819 		break;
820 	case CAN_STATE_ERROR_PASSIVE:
821 		/* error passive state */
822 		cdev->can.can_stats.error_passive++;
823 		cdev->can.state = CAN_STATE_ERROR_PASSIVE;
824 		break;
825 	case CAN_STATE_BUS_OFF:
826 		/* bus-off state */
827 		cdev->can.state = CAN_STATE_BUS_OFF;
828 		m_can_disable_all_interrupts(cdev);
829 		cdev->can.can_stats.bus_off++;
830 		can_bus_off(dev);
831 		break;
832 	default:
833 		break;
834 	}
835 
836 	/* propagate the error condition to the CAN stack */
837 	skb = alloc_can_err_skb(dev, &cf);
838 	if (unlikely(!skb))
839 		return 0;
840 
841 	__m_can_get_berr_counter(dev, &bec);
842 
843 	switch (new_state) {
844 	case CAN_STATE_ERROR_WARNING:
845 		/* error warning state */
846 		cf->can_id |= CAN_ERR_CRTL | CAN_ERR_CNT;
847 		cf->data[1] = (bec.txerr > bec.rxerr) ?
848 			CAN_ERR_CRTL_TX_WARNING :
849 			CAN_ERR_CRTL_RX_WARNING;
850 		cf->data[6] = bec.txerr;
851 		cf->data[7] = bec.rxerr;
852 		break;
853 	case CAN_STATE_ERROR_PASSIVE:
854 		/* error passive state */
855 		cf->can_id |= CAN_ERR_CRTL | CAN_ERR_CNT;
856 		ecr = m_can_read(cdev, M_CAN_ECR);
857 		if (ecr & ECR_RP)
858 			cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
859 		if (bec.txerr > 127)
860 			cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
861 		cf->data[6] = bec.txerr;
862 		cf->data[7] = bec.rxerr;
863 		break;
864 	case CAN_STATE_BUS_OFF:
865 		/* bus-off state */
866 		cf->can_id |= CAN_ERR_BUSOFF;
867 		break;
868 	default:
869 		break;
870 	}
871 
872 	if (cdev->is_peripheral)
873 		timestamp = m_can_get_timestamp(cdev);
874 
875 	m_can_receive_skb(cdev, skb, timestamp);
876 
877 	return 1;
878 }
879 
m_can_handle_state_errors(struct net_device * dev,u32 psr)880 static int m_can_handle_state_errors(struct net_device *dev, u32 psr)
881 {
882 	struct m_can_classdev *cdev = netdev_priv(dev);
883 	int work_done = 0;
884 
885 	if (psr & PSR_EW && cdev->can.state != CAN_STATE_ERROR_WARNING) {
886 		netdev_dbg(dev, "entered error warning state\n");
887 		work_done += m_can_handle_state_change(dev,
888 						       CAN_STATE_ERROR_WARNING);
889 	}
890 
891 	if (psr & PSR_EP && cdev->can.state != CAN_STATE_ERROR_PASSIVE) {
892 		netdev_dbg(dev, "entered error passive state\n");
893 		work_done += m_can_handle_state_change(dev,
894 						       CAN_STATE_ERROR_PASSIVE);
895 	}
896 
897 	if (psr & PSR_BO && cdev->can.state != CAN_STATE_BUS_OFF) {
898 		netdev_dbg(dev, "entered error bus off state\n");
899 		work_done += m_can_handle_state_change(dev,
900 						       CAN_STATE_BUS_OFF);
901 	}
902 
903 	return work_done;
904 }
905 
m_can_handle_other_err(struct net_device * dev,u32 irqstatus)906 static void m_can_handle_other_err(struct net_device *dev, u32 irqstatus)
907 {
908 	if (irqstatus & IR_WDI)
909 		netdev_err(dev, "Message RAM Watchdog event due to missing READY\n");
910 	if (irqstatus & IR_BEU)
911 		netdev_err(dev, "Bit Error Uncorrected\n");
912 	if (irqstatus & IR_BEC)
913 		netdev_err(dev, "Bit Error Corrected\n");
914 	if (irqstatus & IR_TOO)
915 		netdev_err(dev, "Timeout reached\n");
916 	if (irqstatus & IR_MRAF)
917 		netdev_err(dev, "Message RAM access failure occurred\n");
918 }
919 
is_lec_err(u8 lec)920 static inline bool is_lec_err(u8 lec)
921 {
922 	return lec != LEC_NO_ERROR && lec != LEC_NO_CHANGE;
923 }
924 
m_can_is_protocol_err(u32 irqstatus)925 static inline bool m_can_is_protocol_err(u32 irqstatus)
926 {
927 	return irqstatus & IR_ERR_LEC_31X;
928 }
929 
m_can_handle_protocol_error(struct net_device * dev,u32 irqstatus)930 static int m_can_handle_protocol_error(struct net_device *dev, u32 irqstatus)
931 {
932 	struct net_device_stats *stats = &dev->stats;
933 	struct m_can_classdev *cdev = netdev_priv(dev);
934 	struct can_frame *cf;
935 	struct sk_buff *skb;
936 	u32 timestamp = 0;
937 
938 	/* propagate the error condition to the CAN stack */
939 	skb = alloc_can_err_skb(dev, &cf);
940 
941 	/* update tx error stats since there is protocol error */
942 	stats->tx_errors++;
943 
944 	/* update arbitration lost status */
945 	if (cdev->version >= 31 && (irqstatus & IR_PEA)) {
946 		netdev_dbg(dev, "Protocol error in Arbitration fail\n");
947 		cdev->can.can_stats.arbitration_lost++;
948 		if (skb) {
949 			cf->can_id |= CAN_ERR_LOSTARB;
950 			cf->data[0] |= CAN_ERR_LOSTARB_UNSPEC;
951 		}
952 	}
953 
954 	if (unlikely(!skb)) {
955 		netdev_dbg(dev, "allocation of skb failed\n");
956 		return 0;
957 	}
958 
959 	if (cdev->is_peripheral)
960 		timestamp = m_can_get_timestamp(cdev);
961 
962 	m_can_receive_skb(cdev, skb, timestamp);
963 
964 	return 1;
965 }
966 
m_can_handle_bus_errors(struct net_device * dev,u32 irqstatus,u32 psr)967 static int m_can_handle_bus_errors(struct net_device *dev, u32 irqstatus,
968 				   u32 psr)
969 {
970 	struct m_can_classdev *cdev = netdev_priv(dev);
971 	int work_done = 0;
972 
973 	if (irqstatus & IR_RF0L)
974 		work_done += m_can_handle_lost_msg(dev);
975 
976 	/* handle lec errors on the bus */
977 	if (cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) {
978 		u8 lec = FIELD_GET(PSR_LEC_MASK, psr);
979 		u8 dlec = FIELD_GET(PSR_DLEC_MASK, psr);
980 
981 		if (is_lec_err(lec)) {
982 			netdev_dbg(dev, "Arbitration phase error detected\n");
983 			work_done += m_can_handle_lec_err(dev, lec);
984 		}
985 
986 		if (is_lec_err(dlec)) {
987 			netdev_dbg(dev, "Data phase error detected\n");
988 			work_done += m_can_handle_lec_err(dev, dlec);
989 		}
990 	}
991 
992 	/* handle protocol errors in arbitration phase */
993 	if ((cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
994 	    m_can_is_protocol_err(irqstatus))
995 		work_done += m_can_handle_protocol_error(dev, irqstatus);
996 
997 	/* other unproccessed error interrupts */
998 	m_can_handle_other_err(dev, irqstatus);
999 
1000 	return work_done;
1001 }
1002 
m_can_rx_handler(struct net_device * dev,int quota,u32 irqstatus)1003 static int m_can_rx_handler(struct net_device *dev, int quota, u32 irqstatus)
1004 {
1005 	struct m_can_classdev *cdev = netdev_priv(dev);
1006 	int rx_work_or_err;
1007 	int work_done = 0;
1008 
1009 	if (!irqstatus)
1010 		goto end;
1011 
1012 	/* Errata workaround for issue "Needless activation of MRAF irq"
1013 	 * During frame reception while the MCAN is in Error Passive state
1014 	 * and the Receive Error Counter has the value MCAN_ECR.REC = 127,
1015 	 * it may happen that MCAN_IR.MRAF is set although there was no
1016 	 * Message RAM access failure.
1017 	 * If MCAN_IR.MRAF is enabled, an interrupt to the Host CPU is generated
1018 	 * The Message RAM Access Failure interrupt routine needs to check
1019 	 * whether MCAN_ECR.RP = ’1’ and MCAN_ECR.REC = 127.
1020 	 * In this case, reset MCAN_IR.MRAF. No further action is required.
1021 	 */
1022 	if (cdev->version <= 31 && irqstatus & IR_MRAF &&
1023 	    m_can_read(cdev, M_CAN_ECR) & ECR_RP) {
1024 		struct can_berr_counter bec;
1025 
1026 		__m_can_get_berr_counter(dev, &bec);
1027 		if (bec.rxerr == 127) {
1028 			m_can_write(cdev, M_CAN_IR, IR_MRAF);
1029 			irqstatus &= ~IR_MRAF;
1030 		}
1031 	}
1032 
1033 	if (irqstatus & IR_ERR_STATE)
1034 		work_done += m_can_handle_state_errors(dev,
1035 						       m_can_read(cdev, M_CAN_PSR));
1036 
1037 	if (irqstatus & IR_ERR_BUS_30X)
1038 		work_done += m_can_handle_bus_errors(dev, irqstatus,
1039 						     m_can_read(cdev, M_CAN_PSR));
1040 
1041 	if (irqstatus & IR_RF0N) {
1042 		rx_work_or_err = m_can_do_rx_poll(dev, (quota - work_done));
1043 		if (rx_work_or_err < 0)
1044 			return rx_work_or_err;
1045 
1046 		work_done += rx_work_or_err;
1047 	}
1048 end:
1049 	return work_done;
1050 }
1051 
m_can_poll(struct napi_struct * napi,int quota)1052 static int m_can_poll(struct napi_struct *napi, int quota)
1053 {
1054 	struct net_device *dev = napi->dev;
1055 	struct m_can_classdev *cdev = netdev_priv(dev);
1056 	int work_done;
1057 	u32 irqstatus;
1058 
1059 	irqstatus = cdev->irqstatus | m_can_read(cdev, M_CAN_IR);
1060 
1061 	work_done = m_can_rx_handler(dev, quota, irqstatus);
1062 
1063 	/* Don't re-enable interrupts if the driver had a fatal error
1064 	 * (e.g., FIFO read failure).
1065 	 */
1066 	if (work_done >= 0 && work_done < quota) {
1067 		napi_complete_done(napi, work_done);
1068 		m_can_enable_all_interrupts(cdev);
1069 	}
1070 
1071 	return work_done;
1072 }
1073 
1074 /* Echo tx skb and update net stats. Peripherals use rx-offload for
1075  * echo. timestamp is used for peripherals to ensure correct ordering
1076  * by rx-offload, and is ignored for non-peripherals.
1077  */
m_can_tx_update_stats(struct m_can_classdev * cdev,unsigned int msg_mark,u32 timestamp)1078 static unsigned int m_can_tx_update_stats(struct m_can_classdev *cdev,
1079 					  unsigned int msg_mark, u32 timestamp)
1080 {
1081 	struct net_device *dev = cdev->net;
1082 	struct net_device_stats *stats = &dev->stats;
1083 	unsigned int frame_len;
1084 
1085 	if (cdev->is_peripheral)
1086 		stats->tx_bytes +=
1087 			can_rx_offload_get_echo_skb_queue_timestamp(&cdev->offload,
1088 								    msg_mark,
1089 								    timestamp,
1090 								    &frame_len);
1091 	else
1092 		stats->tx_bytes += can_get_echo_skb(dev, msg_mark, &frame_len);
1093 
1094 	stats->tx_packets++;
1095 
1096 	return frame_len;
1097 }
1098 
m_can_finish_tx(struct m_can_classdev * cdev,int transmitted,unsigned int transmitted_frame_len)1099 static void m_can_finish_tx(struct m_can_classdev *cdev, int transmitted,
1100 			    unsigned int transmitted_frame_len)
1101 {
1102 	unsigned long irqflags;
1103 
1104 	netdev_completed_queue(cdev->net, transmitted, transmitted_frame_len);
1105 
1106 	spin_lock_irqsave(&cdev->tx_handling_spinlock, irqflags);
1107 	if (cdev->tx_fifo_in_flight >= cdev->tx_fifo_size && transmitted > 0)
1108 		netif_wake_queue(cdev->net);
1109 	cdev->tx_fifo_in_flight -= transmitted;
1110 	spin_unlock_irqrestore(&cdev->tx_handling_spinlock, irqflags);
1111 }
1112 
m_can_start_tx(struct m_can_classdev * cdev)1113 static netdev_tx_t m_can_start_tx(struct m_can_classdev *cdev)
1114 {
1115 	unsigned long irqflags;
1116 	int tx_fifo_in_flight;
1117 
1118 	spin_lock_irqsave(&cdev->tx_handling_spinlock, irqflags);
1119 	tx_fifo_in_flight = cdev->tx_fifo_in_flight + 1;
1120 	if (tx_fifo_in_flight >= cdev->tx_fifo_size) {
1121 		netif_stop_queue(cdev->net);
1122 		if (tx_fifo_in_flight > cdev->tx_fifo_size) {
1123 			netdev_err_once(cdev->net, "hard_xmit called while TX FIFO full\n");
1124 			spin_unlock_irqrestore(&cdev->tx_handling_spinlock, irqflags);
1125 			return NETDEV_TX_BUSY;
1126 		}
1127 	}
1128 	cdev->tx_fifo_in_flight = tx_fifo_in_flight;
1129 	spin_unlock_irqrestore(&cdev->tx_handling_spinlock, irqflags);
1130 
1131 	return NETDEV_TX_OK;
1132 }
1133 
m_can_echo_tx_event(struct net_device * dev)1134 static int m_can_echo_tx_event(struct net_device *dev)
1135 {
1136 	u32 txe_count = 0;
1137 	u32 m_can_txefs;
1138 	u32 fgi = 0;
1139 	int ack_fgi = -1;
1140 	int i = 0;
1141 	int err = 0;
1142 	unsigned int msg_mark;
1143 	int processed = 0;
1144 	unsigned int processed_frame_len = 0;
1145 
1146 	struct m_can_classdev *cdev = netdev_priv(dev);
1147 
1148 	/* read tx event fifo status */
1149 	m_can_txefs = m_can_read(cdev, M_CAN_TXEFS);
1150 
1151 	/* Get Tx Event fifo element count */
1152 	txe_count = FIELD_GET(TXEFS_EFFL_MASK, m_can_txefs);
1153 	fgi = FIELD_GET(TXEFS_EFGI_MASK, m_can_txefs);
1154 
1155 	/* Get and process all sent elements */
1156 	for (i = 0; i < txe_count; i++) {
1157 		u32 txe, timestamp = 0;
1158 
1159 		/* get message marker, timestamp */
1160 		err = m_can_txe_fifo_read(cdev, fgi, 4, &txe);
1161 		if (err) {
1162 			netdev_err(dev, "TXE FIFO read returned %d\n", err);
1163 			break;
1164 		}
1165 
1166 		msg_mark = FIELD_GET(TX_EVENT_MM_MASK, txe);
1167 		timestamp = FIELD_GET(TX_EVENT_TXTS_MASK, txe) << 16;
1168 
1169 		ack_fgi = fgi;
1170 		fgi = (++fgi >= cdev->mcfg[MRAM_TXE].num ? 0 : fgi);
1171 
1172 		/* update stats */
1173 		processed_frame_len += m_can_tx_update_stats(cdev, msg_mark,
1174 							     timestamp);
1175 
1176 		++processed;
1177 	}
1178 
1179 	if (ack_fgi != -1)
1180 		m_can_write(cdev, M_CAN_TXEFA, FIELD_PREP(TXEFA_EFAI_MASK,
1181 							  ack_fgi));
1182 
1183 	m_can_finish_tx(cdev, processed, processed_frame_len);
1184 
1185 	return err;
1186 }
1187 
m_can_coalescing_update(struct m_can_classdev * cdev,u32 ir)1188 static void m_can_coalescing_update(struct m_can_classdev *cdev, u32 ir)
1189 {
1190 	u32 new_interrupts = cdev->active_interrupts;
1191 	bool enable_rx_timer = false;
1192 	bool enable_tx_timer = false;
1193 
1194 	if (!cdev->net->irq)
1195 		return;
1196 
1197 	if (cdev->rx_coalesce_usecs_irq > 0 && (ir & (IR_RF0N | IR_RF0W))) {
1198 		enable_rx_timer = true;
1199 		new_interrupts &= ~IR_RF0N;
1200 	}
1201 	if (cdev->tx_coalesce_usecs_irq > 0 && (ir & (IR_TEFN | IR_TEFW))) {
1202 		enable_tx_timer = true;
1203 		new_interrupts &= ~IR_TEFN;
1204 	}
1205 	if (!enable_rx_timer && !hrtimer_active(&cdev->hrtimer))
1206 		new_interrupts |= IR_RF0N;
1207 	if (!enable_tx_timer && !hrtimer_active(&cdev->hrtimer))
1208 		new_interrupts |= IR_TEFN;
1209 
1210 	m_can_interrupt_enable(cdev, new_interrupts);
1211 	if (enable_rx_timer | enable_tx_timer)
1212 		hrtimer_start(&cdev->hrtimer, cdev->irq_timer_wait,
1213 			      HRTIMER_MODE_REL);
1214 }
1215 
1216 /* This interrupt handler is called either from the interrupt thread or a
1217  * hrtimer. This has implications like cancelling a timer won't be possible
1218  * blocking.
1219  */
m_can_interrupt_handler(struct m_can_classdev * cdev)1220 static int m_can_interrupt_handler(struct m_can_classdev *cdev)
1221 {
1222 	struct net_device *dev = cdev->net;
1223 	u32 ir = 0, ir_read;
1224 	int ret;
1225 
1226 	if (pm_runtime_suspended(cdev->dev))
1227 		return IRQ_NONE;
1228 
1229 	/* The m_can controller signals its interrupt status as a level, but
1230 	 * depending in the integration the CPU may interpret the signal as
1231 	 * edge-triggered (for example with m_can_pci). For these
1232 	 * edge-triggered integrations, we must observe that IR is 0 at least
1233 	 * once to be sure that the next interrupt will generate an edge.
1234 	 */
1235 	while ((ir_read = m_can_read(cdev, M_CAN_IR)) != 0) {
1236 		ir |= ir_read;
1237 
1238 		/* ACK all irqs */
1239 		m_can_write(cdev, M_CAN_IR, ir);
1240 
1241 		if (!cdev->irq_edge_triggered)
1242 			break;
1243 	}
1244 
1245 	m_can_coalescing_update(cdev, ir);
1246 	if (!ir)
1247 		return IRQ_NONE;
1248 
1249 	if (cdev->ops->clear_interrupts)
1250 		cdev->ops->clear_interrupts(cdev);
1251 
1252 	/* schedule NAPI in case of
1253 	 * - rx IRQ
1254 	 * - state change IRQ
1255 	 * - bus error IRQ and bus error reporting
1256 	 */
1257 	if (ir & (IR_RF0N | IR_RF0W | IR_ERR_ALL_30X)) {
1258 		cdev->irqstatus = ir;
1259 		if (!cdev->is_peripheral) {
1260 			m_can_disable_all_interrupts(cdev);
1261 			napi_schedule(&cdev->napi);
1262 		} else {
1263 			ret = m_can_rx_handler(dev, NAPI_POLL_WEIGHT, ir);
1264 			if (ret < 0)
1265 				return ret;
1266 		}
1267 	}
1268 
1269 	if (cdev->version == 30) {
1270 		if (ir & IR_TC) {
1271 			/* Transmission Complete Interrupt*/
1272 			u32 timestamp = 0;
1273 			unsigned int frame_len;
1274 
1275 			if (cdev->is_peripheral)
1276 				timestamp = m_can_get_timestamp(cdev);
1277 			frame_len = m_can_tx_update_stats(cdev, 0, timestamp);
1278 			m_can_finish_tx(cdev, 1, frame_len);
1279 		}
1280 	} else  {
1281 		if (ir & (IR_TEFN | IR_TEFW)) {
1282 			/* New TX FIFO Element arrived */
1283 			ret = m_can_echo_tx_event(dev);
1284 			if (ret != 0)
1285 				return ret;
1286 		}
1287 	}
1288 
1289 	if (cdev->is_peripheral)
1290 		can_rx_offload_threaded_irq_finish(&cdev->offload);
1291 
1292 	return IRQ_HANDLED;
1293 }
1294 
m_can_isr(int irq,void * dev_id)1295 static irqreturn_t m_can_isr(int irq, void *dev_id)
1296 {
1297 	struct net_device *dev = (struct net_device *)dev_id;
1298 	struct m_can_classdev *cdev = netdev_priv(dev);
1299 	int ret;
1300 
1301 	ret =  m_can_interrupt_handler(cdev);
1302 	if (ret < 0) {
1303 		m_can_disable_all_interrupts(cdev);
1304 		return IRQ_HANDLED;
1305 	}
1306 
1307 	return ret;
1308 }
1309 
m_can_coalescing_timer(struct hrtimer * timer)1310 static enum hrtimer_restart m_can_coalescing_timer(struct hrtimer *timer)
1311 {
1312 	struct m_can_classdev *cdev = container_of(timer, struct m_can_classdev, hrtimer);
1313 
1314 	if (cdev->can.state == CAN_STATE_BUS_OFF ||
1315 	    cdev->can.state == CAN_STATE_STOPPED)
1316 		return HRTIMER_NORESTART;
1317 
1318 	irq_wake_thread(cdev->net->irq, cdev->net);
1319 
1320 	return HRTIMER_NORESTART;
1321 }
1322 
1323 static const struct can_bittiming_const m_can_bittiming_const_30X = {
1324 	.name = KBUILD_MODNAME,
1325 	.tseg1_min = 2,		/* Time segment 1 = prop_seg + phase_seg1 */
1326 	.tseg1_max = 64,
1327 	.tseg2_min = 1,		/* Time segment 2 = phase_seg2 */
1328 	.tseg2_max = 16,
1329 	.sjw_max = 16,
1330 	.brp_min = 1,
1331 	.brp_max = 1024,
1332 	.brp_inc = 1,
1333 };
1334 
1335 static const struct can_bittiming_const m_can_data_bittiming_const_30X = {
1336 	.name = KBUILD_MODNAME,
1337 	.tseg1_min = 2,		/* Time segment 1 = prop_seg + phase_seg1 */
1338 	.tseg1_max = 16,
1339 	.tseg2_min = 1,		/* Time segment 2 = phase_seg2 */
1340 	.tseg2_max = 8,
1341 	.sjw_max = 4,
1342 	.brp_min = 1,
1343 	.brp_max = 32,
1344 	.brp_inc = 1,
1345 };
1346 
1347 static const struct can_bittiming_const m_can_bittiming_const_31X = {
1348 	.name = KBUILD_MODNAME,
1349 	.tseg1_min = 2,		/* Time segment 1 = prop_seg + phase_seg1 */
1350 	.tseg1_max = 256,
1351 	.tseg2_min = 2,		/* Time segment 2 = phase_seg2 */
1352 	.tseg2_max = 128,
1353 	.sjw_max = 128,
1354 	.brp_min = 1,
1355 	.brp_max = 512,
1356 	.brp_inc = 1,
1357 };
1358 
1359 static const struct can_bittiming_const m_can_data_bittiming_const_31X = {
1360 	.name = KBUILD_MODNAME,
1361 	.tseg1_min = 1,		/* Time segment 1 = prop_seg + phase_seg1 */
1362 	.tseg1_max = 32,
1363 	.tseg2_min = 1,		/* Time segment 2 = phase_seg2 */
1364 	.tseg2_max = 16,
1365 	.sjw_max = 16,
1366 	.brp_min = 1,
1367 	.brp_max = 32,
1368 	.brp_inc = 1,
1369 };
1370 
m_can_set_bittiming(struct net_device * dev)1371 static int m_can_set_bittiming(struct net_device *dev)
1372 {
1373 	struct m_can_classdev *cdev = netdev_priv(dev);
1374 	const struct can_bittiming *bt = &cdev->can.bittiming;
1375 	const struct can_bittiming *dbt = &cdev->can.data_bittiming;
1376 	u16 brp, sjw, tseg1, tseg2;
1377 	u32 reg_btp;
1378 
1379 	brp = bt->brp - 1;
1380 	sjw = bt->sjw - 1;
1381 	tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
1382 	tseg2 = bt->phase_seg2 - 1;
1383 	reg_btp = FIELD_PREP(NBTP_NBRP_MASK, brp) |
1384 		  FIELD_PREP(NBTP_NSJW_MASK, sjw) |
1385 		  FIELD_PREP(NBTP_NTSEG1_MASK, tseg1) |
1386 		  FIELD_PREP(NBTP_NTSEG2_MASK, tseg2);
1387 	m_can_write(cdev, M_CAN_NBTP, reg_btp);
1388 
1389 	if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) {
1390 		reg_btp = 0;
1391 		brp = dbt->brp - 1;
1392 		sjw = dbt->sjw - 1;
1393 		tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1;
1394 		tseg2 = dbt->phase_seg2 - 1;
1395 
1396 		/* TDC is only needed for bitrates beyond 2.5 MBit/s.
1397 		 * This is mentioned in the "Bit Time Requirements for CAN FD"
1398 		 * paper presented at the International CAN Conference 2013
1399 		 */
1400 		if (dbt->bitrate > 2500000) {
1401 			u32 tdco, ssp;
1402 
1403 			/* Use the same value of secondary sampling point
1404 			 * as the data sampling point
1405 			 */
1406 			ssp = dbt->sample_point;
1407 
1408 			/* Equation based on Bosch's M_CAN User Manual's
1409 			 * Transmitter Delay Compensation Section
1410 			 */
1411 			tdco = (cdev->can.clock.freq / 1000) *
1412 				ssp / dbt->bitrate;
1413 
1414 			/* Max valid TDCO value is 127 */
1415 			if (tdco > 127) {
1416 				netdev_warn(dev, "TDCO value of %u is beyond maximum. Using maximum possible value\n",
1417 					    tdco);
1418 				tdco = 127;
1419 			}
1420 
1421 			reg_btp |= DBTP_TDC;
1422 			m_can_write(cdev, M_CAN_TDCR,
1423 				    FIELD_PREP(TDCR_TDCO_MASK, tdco));
1424 		}
1425 
1426 		reg_btp |= FIELD_PREP(DBTP_DBRP_MASK, brp) |
1427 			FIELD_PREP(DBTP_DSJW_MASK, sjw) |
1428 			FIELD_PREP(DBTP_DTSEG1_MASK, tseg1) |
1429 			FIELD_PREP(DBTP_DTSEG2_MASK, tseg2);
1430 
1431 		m_can_write(cdev, M_CAN_DBTP, reg_btp);
1432 	}
1433 
1434 	return 0;
1435 }
1436 
1437 /* Configure M_CAN chip:
1438  * - set rx buffer/fifo element size
1439  * - configure rx fifo
1440  * - accept non-matching frame into fifo 0
1441  * - configure tx buffer
1442  *		- >= v3.1.x: TX FIFO is used
1443  * - configure mode
1444  * - setup bittiming
1445  * - configure timestamp generation
1446  */
m_can_chip_config(struct net_device * dev)1447 static int m_can_chip_config(struct net_device *dev)
1448 {
1449 	struct m_can_classdev *cdev = netdev_priv(dev);
1450 	u32 interrupts = IR_ALL_INT;
1451 	u32 cccr, test;
1452 	int err;
1453 
1454 	err = m_can_init_ram(cdev);
1455 	if (err) {
1456 		dev_err(cdev->dev, "Message RAM configuration failed\n");
1457 		return err;
1458 	}
1459 
1460 	/* Disable unused interrupts */
1461 	interrupts &= ~(IR_ARA | IR_ELO | IR_DRX | IR_TEFF | IR_TFE | IR_TCF |
1462 			IR_HPM | IR_RF1F | IR_RF1W | IR_RF1N | IR_RF0F |
1463 			IR_TSW);
1464 
1465 	err = m_can_config_enable(cdev);
1466 	if (err)
1467 		return err;
1468 
1469 	/* RX Buffer/FIFO Element Size 64 bytes data field */
1470 	m_can_write(cdev, M_CAN_RXESC,
1471 		    FIELD_PREP(RXESC_RBDS_MASK, RXESC_64B) |
1472 		    FIELD_PREP(RXESC_F1DS_MASK, RXESC_64B) |
1473 		    FIELD_PREP(RXESC_F0DS_MASK, RXESC_64B));
1474 
1475 	/* Accept Non-matching Frames Into FIFO 0 */
1476 	m_can_write(cdev, M_CAN_GFC, 0x0);
1477 
1478 	if (cdev->version == 30) {
1479 		/* only support one Tx Buffer currently */
1480 		m_can_write(cdev, M_CAN_TXBC, FIELD_PREP(TXBC_NDTB_MASK, 1) |
1481 			    cdev->mcfg[MRAM_TXB].off);
1482 	} else {
1483 		/* TX FIFO is used for newer IP Core versions */
1484 		m_can_write(cdev, M_CAN_TXBC,
1485 			    FIELD_PREP(TXBC_TFQS_MASK,
1486 				       cdev->mcfg[MRAM_TXB].num) |
1487 			    cdev->mcfg[MRAM_TXB].off);
1488 	}
1489 
1490 	/* support 64 bytes payload */
1491 	m_can_write(cdev, M_CAN_TXESC,
1492 		    FIELD_PREP(TXESC_TBDS_MASK, TXESC_TBDS_64B));
1493 
1494 	/* TX Event FIFO */
1495 	if (cdev->version == 30) {
1496 		m_can_write(cdev, M_CAN_TXEFC,
1497 			    FIELD_PREP(TXEFC_EFS_MASK, 1) |
1498 			    cdev->mcfg[MRAM_TXE].off);
1499 	} else {
1500 		/* Full TX Event FIFO is used */
1501 		m_can_write(cdev, M_CAN_TXEFC,
1502 			    FIELD_PREP(TXEFC_EFWM_MASK,
1503 				       cdev->tx_max_coalesced_frames_irq) |
1504 			    FIELD_PREP(TXEFC_EFS_MASK,
1505 				       cdev->mcfg[MRAM_TXE].num) |
1506 			    cdev->mcfg[MRAM_TXE].off);
1507 	}
1508 
1509 	/* rx fifo configuration, blocking mode, fifo size 1 */
1510 	m_can_write(cdev, M_CAN_RXF0C,
1511 		    FIELD_PREP(RXFC_FWM_MASK, cdev->rx_max_coalesced_frames_irq) |
1512 		    FIELD_PREP(RXFC_FS_MASK, cdev->mcfg[MRAM_RXF0].num) |
1513 		    cdev->mcfg[MRAM_RXF0].off);
1514 
1515 	m_can_write(cdev, M_CAN_RXF1C,
1516 		    FIELD_PREP(RXFC_FS_MASK, cdev->mcfg[MRAM_RXF1].num) |
1517 		    cdev->mcfg[MRAM_RXF1].off);
1518 
1519 	cccr = m_can_read(cdev, M_CAN_CCCR);
1520 	test = m_can_read(cdev, M_CAN_TEST);
1521 	test &= ~TEST_LBCK;
1522 	if (cdev->version == 30) {
1523 		/* Version 3.0.x */
1524 
1525 		cccr &= ~(CCCR_TEST | CCCR_MON | CCCR_DAR |
1526 			  FIELD_PREP(CCCR_CMR_MASK, FIELD_MAX(CCCR_CMR_MASK)) |
1527 			  FIELD_PREP(CCCR_CME_MASK, FIELD_MAX(CCCR_CME_MASK)));
1528 
1529 		if (cdev->can.ctrlmode & CAN_CTRLMODE_FD)
1530 			cccr |= FIELD_PREP(CCCR_CME_MASK, CCCR_CME_CANFD_BRS);
1531 
1532 	} else {
1533 		/* Version 3.1.x or 3.2.x */
1534 		cccr &= ~(CCCR_TEST | CCCR_MON | CCCR_BRSE | CCCR_FDOE |
1535 			  CCCR_NISO | CCCR_DAR);
1536 
1537 		/* Only 3.2.x has NISO Bit implemented */
1538 		if (cdev->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO)
1539 			cccr |= CCCR_NISO;
1540 
1541 		if (cdev->can.ctrlmode & CAN_CTRLMODE_FD)
1542 			cccr |= (CCCR_BRSE | CCCR_FDOE);
1543 	}
1544 
1545 	/* Loopback Mode */
1546 	if (cdev->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
1547 		cccr |= CCCR_TEST | CCCR_MON;
1548 		test |= TEST_LBCK;
1549 	}
1550 
1551 	/* Enable Monitoring (all versions) */
1552 	if (cdev->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
1553 		cccr |= CCCR_MON;
1554 
1555 	/* Disable Auto Retransmission (all versions) */
1556 	if (cdev->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT)
1557 		cccr |= CCCR_DAR;
1558 
1559 	/* Write config */
1560 	m_can_write(cdev, M_CAN_CCCR, cccr);
1561 	m_can_write(cdev, M_CAN_TEST, test);
1562 
1563 	/* Enable interrupts */
1564 	if (!(cdev->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) {
1565 		if (cdev->version == 30)
1566 			interrupts &= ~(IR_ERR_LEC_30X);
1567 		else
1568 			interrupts &= ~(IR_ERR_LEC_31X);
1569 	}
1570 	cdev->active_interrupts = 0;
1571 	m_can_interrupt_enable(cdev, interrupts);
1572 
1573 	/* route all interrupts to INT0 */
1574 	m_can_write(cdev, M_CAN_ILS, ILS_ALL_INT0);
1575 
1576 	/* set bittiming params */
1577 	m_can_set_bittiming(dev);
1578 
1579 	/* enable internal timestamp generation, with a prescaler of 16. The
1580 	 * prescaler is applied to the nominal bit timing
1581 	 */
1582 	m_can_write(cdev, M_CAN_TSCC,
1583 		    FIELD_PREP(TSCC_TCP_MASK, 0xf) |
1584 		    FIELD_PREP(TSCC_TSS_MASK, TSCC_TSS_INTERNAL));
1585 
1586 	err = m_can_config_disable(cdev);
1587 	if (err)
1588 		return err;
1589 
1590 	if (cdev->ops->init)
1591 		cdev->ops->init(cdev);
1592 
1593 	return 0;
1594 }
1595 
m_can_start(struct net_device * dev)1596 static int m_can_start(struct net_device *dev)
1597 {
1598 	struct m_can_classdev *cdev = netdev_priv(dev);
1599 	int ret;
1600 
1601 	/* basic m_can configuration */
1602 	ret = m_can_chip_config(dev);
1603 	if (ret)
1604 		return ret;
1605 
1606 	netdev_queue_set_dql_min_limit(netdev_get_tx_queue(cdev->net, 0),
1607 				       cdev->tx_max_coalesced_frames);
1608 
1609 	cdev->can.state = CAN_STATE_ERROR_ACTIVE;
1610 
1611 	m_can_enable_all_interrupts(cdev);
1612 
1613 	if (cdev->version > 30)
1614 		cdev->tx_fifo_putidx = FIELD_GET(TXFQS_TFQPI_MASK,
1615 						 m_can_read(cdev, M_CAN_TXFQS));
1616 
1617 	ret = m_can_cccr_update_bits(cdev, CCCR_INIT, 0);
1618 	if (ret)
1619 		netdev_err(dev, "failed to enter normal mode\n");
1620 
1621 	return ret;
1622 }
1623 
m_can_set_mode(struct net_device * dev,enum can_mode mode)1624 static int m_can_set_mode(struct net_device *dev, enum can_mode mode)
1625 {
1626 	switch (mode) {
1627 	case CAN_MODE_START:
1628 		m_can_clean(dev);
1629 		m_can_start(dev);
1630 		netif_wake_queue(dev);
1631 		break;
1632 	default:
1633 		return -EOPNOTSUPP;
1634 	}
1635 
1636 	return 0;
1637 }
1638 
1639 /* Checks core release number of M_CAN
1640  * returns 0 if an unsupported device is detected
1641  * else it returns the release and step coded as:
1642  * return value = 10 * <release> + 1 * <step>
1643  */
m_can_check_core_release(struct m_can_classdev * cdev)1644 static int m_can_check_core_release(struct m_can_classdev *cdev)
1645 {
1646 	u32 crel_reg;
1647 	u8 rel;
1648 	u8 step;
1649 	int res;
1650 
1651 	/* Read Core Release Version and split into version number
1652 	 * Example: Version 3.2.1 => rel = 3; step = 2; substep = 1;
1653 	 */
1654 	crel_reg = m_can_read(cdev, M_CAN_CREL);
1655 	rel = (u8)FIELD_GET(CREL_REL_MASK, crel_reg);
1656 	step = (u8)FIELD_GET(CREL_STEP_MASK, crel_reg);
1657 
1658 	if (rel == 3) {
1659 		/* M_CAN v3.x.y: create return value */
1660 		res = 30 + step;
1661 	} else {
1662 		/* Unsupported M_CAN version */
1663 		res = 0;
1664 	}
1665 
1666 	return res;
1667 }
1668 
1669 /* Selectable Non ISO support only in version 3.2.x
1670  * Return 1 if the bit is writable, 0 if it is not, or negative on error.
1671  */
m_can_niso_supported(struct m_can_classdev * cdev)1672 static int m_can_niso_supported(struct m_can_classdev *cdev)
1673 {
1674 	int ret, niso;
1675 
1676 	ret = m_can_config_enable(cdev);
1677 	if (ret)
1678 		return ret;
1679 
1680 	/* First try to set the NISO bit. */
1681 	niso = m_can_cccr_update_bits(cdev, CCCR_NISO, CCCR_NISO);
1682 
1683 	/* Then clear the it again. */
1684 	ret = m_can_cccr_update_bits(cdev, CCCR_NISO, 0);
1685 	if (ret) {
1686 		dev_err(cdev->dev, "failed to revert the NON-ISO bit in CCCR\n");
1687 		return ret;
1688 	}
1689 
1690 	ret = m_can_config_disable(cdev);
1691 	if (ret)
1692 		return ret;
1693 
1694 	return niso == 0;
1695 }
1696 
m_can_dev_setup(struct m_can_classdev * cdev)1697 static int m_can_dev_setup(struct m_can_classdev *cdev)
1698 {
1699 	struct net_device *dev = cdev->net;
1700 	int m_can_version, err, niso;
1701 
1702 	m_can_version = m_can_check_core_release(cdev);
1703 	/* return if unsupported version */
1704 	if (!m_can_version) {
1705 		dev_err(cdev->dev, "Unsupported version number: %2d",
1706 			m_can_version);
1707 		return -EINVAL;
1708 	}
1709 
1710 	/* Write the INIT bit, in case no hardware reset has happened before
1711 	 * the probe (for example, it was observed that the Intel Elkhart Lake
1712 	 * SoCs do not properly reset the CAN controllers on reboot)
1713 	 */
1714 	err = m_can_cccr_update_bits(cdev, CCCR_INIT, CCCR_INIT);
1715 	if (err)
1716 		return err;
1717 
1718 	if (!cdev->is_peripheral)
1719 		netif_napi_add(dev, &cdev->napi, m_can_poll);
1720 
1721 	/* Shared properties of all M_CAN versions */
1722 	cdev->version = m_can_version;
1723 	cdev->can.do_set_mode = m_can_set_mode;
1724 	cdev->can.do_get_berr_counter = m_can_get_berr_counter;
1725 
1726 	/* Set M_CAN supported operations */
1727 	cdev->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1728 		CAN_CTRLMODE_LISTENONLY |
1729 		CAN_CTRLMODE_BERR_REPORTING |
1730 		CAN_CTRLMODE_FD |
1731 		CAN_CTRLMODE_ONE_SHOT;
1732 
1733 	/* Set properties depending on M_CAN version */
1734 	switch (cdev->version) {
1735 	case 30:
1736 		/* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.0.x */
1737 		err = can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO);
1738 		if (err)
1739 			return err;
1740 		cdev->can.bittiming_const = &m_can_bittiming_const_30X;
1741 		cdev->can.data_bittiming_const = &m_can_data_bittiming_const_30X;
1742 		break;
1743 	case 31:
1744 		/* CAN_CTRLMODE_FD_NON_ISO is fixed with M_CAN IP v3.1.x */
1745 		err = can_set_static_ctrlmode(dev, CAN_CTRLMODE_FD_NON_ISO);
1746 		if (err)
1747 			return err;
1748 		cdev->can.bittiming_const = &m_can_bittiming_const_31X;
1749 		cdev->can.data_bittiming_const = &m_can_data_bittiming_const_31X;
1750 		break;
1751 	case 32:
1752 	case 33:
1753 		/* Support both MCAN version v3.2.x and v3.3.0 */
1754 		cdev->can.bittiming_const = &m_can_bittiming_const_31X;
1755 		cdev->can.data_bittiming_const = &m_can_data_bittiming_const_31X;
1756 
1757 		niso = m_can_niso_supported(cdev);
1758 		if (niso < 0)
1759 			return niso;
1760 		if (niso)
1761 			cdev->can.ctrlmode_supported |= CAN_CTRLMODE_FD_NON_ISO;
1762 		break;
1763 	default:
1764 		dev_err(cdev->dev, "Unsupported version number: %2d",
1765 			cdev->version);
1766 		return -EINVAL;
1767 	}
1768 
1769 	return 0;
1770 }
1771 
m_can_stop(struct net_device * dev)1772 static void m_can_stop(struct net_device *dev)
1773 {
1774 	struct m_can_classdev *cdev = netdev_priv(dev);
1775 	int ret;
1776 
1777 	/* disable all interrupts */
1778 	m_can_disable_all_interrupts(cdev);
1779 
1780 	/* Set init mode to disengage from the network */
1781 	ret = m_can_cccr_update_bits(cdev, CCCR_INIT, CCCR_INIT);
1782 	if (ret)
1783 		netdev_err(dev, "failed to enter standby mode: %pe\n",
1784 			   ERR_PTR(ret));
1785 
1786 	/* set the state as STOPPED */
1787 	cdev->can.state = CAN_STATE_STOPPED;
1788 
1789 	if (cdev->ops->deinit) {
1790 		ret = cdev->ops->deinit(cdev);
1791 		if (ret)
1792 			netdev_err(dev, "failed to deinitialize: %pe\n",
1793 				   ERR_PTR(ret));
1794 	}
1795 }
1796 
m_can_close(struct net_device * dev)1797 static int m_can_close(struct net_device *dev)
1798 {
1799 	struct m_can_classdev *cdev = netdev_priv(dev);
1800 
1801 	netif_stop_queue(dev);
1802 
1803 	m_can_stop(dev);
1804 	if (dev->irq)
1805 		free_irq(dev->irq, dev);
1806 
1807 	m_can_clean(dev);
1808 
1809 	if (cdev->is_peripheral) {
1810 		destroy_workqueue(cdev->tx_wq);
1811 		cdev->tx_wq = NULL;
1812 		can_rx_offload_disable(&cdev->offload);
1813 	} else {
1814 		napi_disable(&cdev->napi);
1815 	}
1816 
1817 	close_candev(dev);
1818 
1819 	m_can_clk_stop(cdev);
1820 	phy_power_off(cdev->transceiver);
1821 
1822 	return 0;
1823 }
1824 
m_can_tx_handler(struct m_can_classdev * cdev,struct sk_buff * skb)1825 static netdev_tx_t m_can_tx_handler(struct m_can_classdev *cdev,
1826 				    struct sk_buff *skb)
1827 {
1828 	struct canfd_frame *cf = (struct canfd_frame *)skb->data;
1829 	u8 len_padded = DIV_ROUND_UP(cf->len, 4);
1830 	struct m_can_fifo_element fifo_element;
1831 	struct net_device *dev = cdev->net;
1832 	u32 cccr, fdflags;
1833 	int err;
1834 	u32 putidx;
1835 	unsigned int frame_len = can_skb_get_frame_len(skb);
1836 
1837 	/* Generate ID field for TX buffer Element */
1838 	/* Common to all supported M_CAN versions */
1839 	if (cf->can_id & CAN_EFF_FLAG) {
1840 		fifo_element.id = cf->can_id & CAN_EFF_MASK;
1841 		fifo_element.id |= TX_BUF_XTD;
1842 	} else {
1843 		fifo_element.id = ((cf->can_id & CAN_SFF_MASK) << 18);
1844 	}
1845 
1846 	if (cf->can_id & CAN_RTR_FLAG)
1847 		fifo_element.id |= TX_BUF_RTR;
1848 
1849 	if (cdev->version == 30) {
1850 		netif_stop_queue(dev);
1851 
1852 		fifo_element.dlc = can_fd_len2dlc(cf->len) << 16;
1853 
1854 		/* Write the frame ID, DLC, and payload to the FIFO element. */
1855 		err = m_can_fifo_write(cdev, 0, M_CAN_FIFO_ID, &fifo_element, 2);
1856 		if (err)
1857 			goto out_fail;
1858 
1859 		err = m_can_fifo_write(cdev, 0, M_CAN_FIFO_DATA,
1860 				       cf->data, len_padded);
1861 		if (err)
1862 			goto out_fail;
1863 
1864 		if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) {
1865 			cccr = m_can_read(cdev, M_CAN_CCCR);
1866 			cccr &= ~CCCR_CMR_MASK;
1867 			if (can_is_canfd_skb(skb)) {
1868 				if (cf->flags & CANFD_BRS)
1869 					cccr |= FIELD_PREP(CCCR_CMR_MASK,
1870 							   CCCR_CMR_CANFD_BRS);
1871 				else
1872 					cccr |= FIELD_PREP(CCCR_CMR_MASK,
1873 							   CCCR_CMR_CANFD);
1874 			} else {
1875 				cccr |= FIELD_PREP(CCCR_CMR_MASK, CCCR_CMR_CAN);
1876 			}
1877 			m_can_write(cdev, M_CAN_CCCR, cccr);
1878 		}
1879 		m_can_write(cdev, M_CAN_TXBTIE, 0x1);
1880 
1881 		can_put_echo_skb(skb, dev, 0, frame_len);
1882 
1883 		m_can_write(cdev, M_CAN_TXBAR, 0x1);
1884 		/* End of xmit function for version 3.0.x */
1885 	} else {
1886 		/* Transmit routine for version >= v3.1.x */
1887 
1888 		/* get put index for frame */
1889 		putidx = cdev->tx_fifo_putidx;
1890 
1891 		/* Construct DLC Field, with CAN-FD configuration.
1892 		 * Use the put index of the fifo as the message marker,
1893 		 * used in the TX interrupt for sending the correct echo frame.
1894 		 */
1895 
1896 		/* get CAN FD configuration of frame */
1897 		fdflags = 0;
1898 		if (can_is_canfd_skb(skb)) {
1899 			fdflags |= TX_BUF_FDF;
1900 			if (cf->flags & CANFD_BRS)
1901 				fdflags |= TX_BUF_BRS;
1902 		}
1903 
1904 		fifo_element.dlc = FIELD_PREP(TX_BUF_MM_MASK, putidx) |
1905 			FIELD_PREP(TX_BUF_DLC_MASK, can_fd_len2dlc(cf->len)) |
1906 			fdflags | TX_BUF_EFC;
1907 
1908 		memcpy_and_pad(fifo_element.data, CANFD_MAX_DLEN, &cf->data,
1909 			       cf->len, 0);
1910 
1911 		err = m_can_fifo_write(cdev, putidx, M_CAN_FIFO_ID,
1912 				       &fifo_element, 2 + len_padded);
1913 		if (err)
1914 			goto out_fail;
1915 
1916 		/* Push loopback echo.
1917 		 * Will be looped back on TX interrupt based on message marker
1918 		 */
1919 		can_put_echo_skb(skb, dev, putidx, frame_len);
1920 
1921 		if (cdev->is_peripheral) {
1922 			/* Delay enabling TX FIFO element */
1923 			cdev->tx_peripheral_submit |= BIT(putidx);
1924 		} else {
1925 			/* Enable TX FIFO element to start transfer  */
1926 			m_can_write(cdev, M_CAN_TXBAR, BIT(putidx));
1927 		}
1928 		cdev->tx_fifo_putidx = (++cdev->tx_fifo_putidx >= cdev->can.echo_skb_max ?
1929 					0 : cdev->tx_fifo_putidx);
1930 	}
1931 
1932 	return NETDEV_TX_OK;
1933 
1934 out_fail:
1935 	netdev_err(dev, "FIFO write returned %d\n", err);
1936 	m_can_disable_all_interrupts(cdev);
1937 	return NETDEV_TX_BUSY;
1938 }
1939 
m_can_tx_submit(struct m_can_classdev * cdev)1940 static void m_can_tx_submit(struct m_can_classdev *cdev)
1941 {
1942 	if (cdev->version == 30)
1943 		return;
1944 	if (!cdev->is_peripheral)
1945 		return;
1946 
1947 	m_can_write(cdev, M_CAN_TXBAR, cdev->tx_peripheral_submit);
1948 	cdev->tx_peripheral_submit = 0;
1949 }
1950 
m_can_tx_work_queue(struct work_struct * ws)1951 static void m_can_tx_work_queue(struct work_struct *ws)
1952 {
1953 	struct m_can_tx_op *op = container_of(ws, struct m_can_tx_op, work);
1954 	struct m_can_classdev *cdev = op->cdev;
1955 	struct sk_buff *skb = op->skb;
1956 
1957 	op->skb = NULL;
1958 	m_can_tx_handler(cdev, skb);
1959 	if (op->submit)
1960 		m_can_tx_submit(cdev);
1961 }
1962 
m_can_tx_queue_skb(struct m_can_classdev * cdev,struct sk_buff * skb,bool submit)1963 static void m_can_tx_queue_skb(struct m_can_classdev *cdev, struct sk_buff *skb,
1964 			       bool submit)
1965 {
1966 	cdev->tx_ops[cdev->next_tx_op].skb = skb;
1967 	cdev->tx_ops[cdev->next_tx_op].submit = submit;
1968 	queue_work(cdev->tx_wq, &cdev->tx_ops[cdev->next_tx_op].work);
1969 
1970 	++cdev->next_tx_op;
1971 	if (cdev->next_tx_op >= cdev->tx_fifo_size)
1972 		cdev->next_tx_op = 0;
1973 }
1974 
m_can_start_peripheral_xmit(struct m_can_classdev * cdev,struct sk_buff * skb)1975 static netdev_tx_t m_can_start_peripheral_xmit(struct m_can_classdev *cdev,
1976 					       struct sk_buff *skb)
1977 {
1978 	bool submit;
1979 
1980 	++cdev->nr_txs_without_submit;
1981 	if (cdev->nr_txs_without_submit >= cdev->tx_max_coalesced_frames ||
1982 	    !netdev_xmit_more()) {
1983 		cdev->nr_txs_without_submit = 0;
1984 		submit = true;
1985 	} else {
1986 		submit = false;
1987 	}
1988 	m_can_tx_queue_skb(cdev, skb, submit);
1989 
1990 	return NETDEV_TX_OK;
1991 }
1992 
m_can_start_xmit(struct sk_buff * skb,struct net_device * dev)1993 static netdev_tx_t m_can_start_xmit(struct sk_buff *skb,
1994 				    struct net_device *dev)
1995 {
1996 	struct m_can_classdev *cdev = netdev_priv(dev);
1997 	unsigned int frame_len;
1998 	netdev_tx_t ret;
1999 
2000 	if (can_dev_dropped_skb(dev, skb))
2001 		return NETDEV_TX_OK;
2002 
2003 	frame_len = can_skb_get_frame_len(skb);
2004 
2005 	if (cdev->can.state == CAN_STATE_BUS_OFF) {
2006 		m_can_clean(cdev->net);
2007 		return NETDEV_TX_OK;
2008 	}
2009 
2010 	ret = m_can_start_tx(cdev);
2011 	if (ret != NETDEV_TX_OK)
2012 		return ret;
2013 
2014 	netdev_sent_queue(dev, frame_len);
2015 
2016 	if (cdev->is_peripheral)
2017 		ret = m_can_start_peripheral_xmit(cdev, skb);
2018 	else
2019 		ret = m_can_tx_handler(cdev, skb);
2020 
2021 	if (ret != NETDEV_TX_OK)
2022 		netdev_completed_queue(dev, 1, frame_len);
2023 
2024 	return ret;
2025 }
2026 
hrtimer_callback(struct hrtimer * timer)2027 static enum hrtimer_restart hrtimer_callback(struct hrtimer *timer)
2028 {
2029 	struct m_can_classdev *cdev = container_of(timer, struct
2030 						   m_can_classdev, hrtimer);
2031 	int ret;
2032 
2033 	if (cdev->can.state == CAN_STATE_BUS_OFF ||
2034 	    cdev->can.state == CAN_STATE_STOPPED)
2035 		return HRTIMER_NORESTART;
2036 
2037 	ret = m_can_interrupt_handler(cdev);
2038 
2039 	/* On error or if napi is scheduled to read, stop the timer */
2040 	if (ret < 0 || napi_is_scheduled(&cdev->napi))
2041 		return HRTIMER_NORESTART;
2042 
2043 	hrtimer_forward_now(timer, ms_to_ktime(HRTIMER_POLL_INTERVAL_MS));
2044 
2045 	return HRTIMER_RESTART;
2046 }
2047 
m_can_open(struct net_device * dev)2048 static int m_can_open(struct net_device *dev)
2049 {
2050 	struct m_can_classdev *cdev = netdev_priv(dev);
2051 	int err;
2052 
2053 	err = phy_power_on(cdev->transceiver);
2054 	if (err)
2055 		return err;
2056 
2057 	err = m_can_clk_start(cdev);
2058 	if (err)
2059 		goto out_phy_power_off;
2060 
2061 	/* open the can device */
2062 	err = open_candev(dev);
2063 	if (err) {
2064 		netdev_err(dev, "failed to open can device\n");
2065 		goto exit_disable_clks;
2066 	}
2067 
2068 	if (cdev->is_peripheral)
2069 		can_rx_offload_enable(&cdev->offload);
2070 	else
2071 		napi_enable(&cdev->napi);
2072 
2073 	/* register interrupt handler */
2074 	if (cdev->is_peripheral) {
2075 		cdev->tx_wq = alloc_ordered_workqueue("mcan_wq",
2076 						      WQ_FREEZABLE | WQ_MEM_RECLAIM);
2077 		if (!cdev->tx_wq) {
2078 			err = -ENOMEM;
2079 			goto out_wq_fail;
2080 		}
2081 
2082 		for (int i = 0; i != cdev->tx_fifo_size; ++i) {
2083 			cdev->tx_ops[i].cdev = cdev;
2084 			INIT_WORK(&cdev->tx_ops[i].work, m_can_tx_work_queue);
2085 		}
2086 
2087 		err = request_threaded_irq(dev->irq, NULL, m_can_isr,
2088 					   IRQF_ONESHOT,
2089 					   dev->name, dev);
2090 	} else if (dev->irq) {
2091 		err = request_irq(dev->irq, m_can_isr, IRQF_SHARED, dev->name,
2092 				  dev);
2093 	}
2094 
2095 	if (err < 0) {
2096 		netdev_err(dev, "failed to request interrupt\n");
2097 		goto exit_irq_fail;
2098 	}
2099 
2100 	/* start the m_can controller */
2101 	err = m_can_start(dev);
2102 	if (err)
2103 		goto exit_start_fail;
2104 
2105 	netif_start_queue(dev);
2106 
2107 	return 0;
2108 
2109 exit_start_fail:
2110 	if (cdev->is_peripheral || dev->irq)
2111 		free_irq(dev->irq, dev);
2112 exit_irq_fail:
2113 	if (cdev->is_peripheral)
2114 		destroy_workqueue(cdev->tx_wq);
2115 out_wq_fail:
2116 	if (cdev->is_peripheral)
2117 		can_rx_offload_disable(&cdev->offload);
2118 	else
2119 		napi_disable(&cdev->napi);
2120 	close_candev(dev);
2121 exit_disable_clks:
2122 	m_can_clk_stop(cdev);
2123 out_phy_power_off:
2124 	phy_power_off(cdev->transceiver);
2125 	return err;
2126 }
2127 
2128 static const struct net_device_ops m_can_netdev_ops = {
2129 	.ndo_open = m_can_open,
2130 	.ndo_stop = m_can_close,
2131 	.ndo_start_xmit = m_can_start_xmit,
2132 	.ndo_change_mtu = can_change_mtu,
2133 };
2134 
m_can_get_coalesce(struct net_device * dev,struct ethtool_coalesce * ec,struct kernel_ethtool_coalesce * kec,struct netlink_ext_ack * ext_ack)2135 static int m_can_get_coalesce(struct net_device *dev,
2136 			      struct ethtool_coalesce *ec,
2137 			      struct kernel_ethtool_coalesce *kec,
2138 			      struct netlink_ext_ack *ext_ack)
2139 {
2140 	struct m_can_classdev *cdev = netdev_priv(dev);
2141 
2142 	ec->rx_max_coalesced_frames_irq = cdev->rx_max_coalesced_frames_irq;
2143 	ec->rx_coalesce_usecs_irq = cdev->rx_coalesce_usecs_irq;
2144 	ec->tx_max_coalesced_frames = cdev->tx_max_coalesced_frames;
2145 	ec->tx_max_coalesced_frames_irq = cdev->tx_max_coalesced_frames_irq;
2146 	ec->tx_coalesce_usecs_irq = cdev->tx_coalesce_usecs_irq;
2147 
2148 	return 0;
2149 }
2150 
m_can_set_coalesce(struct net_device * dev,struct ethtool_coalesce * ec,struct kernel_ethtool_coalesce * kec,struct netlink_ext_ack * ext_ack)2151 static int m_can_set_coalesce(struct net_device *dev,
2152 			      struct ethtool_coalesce *ec,
2153 			      struct kernel_ethtool_coalesce *kec,
2154 			      struct netlink_ext_ack *ext_ack)
2155 {
2156 	struct m_can_classdev *cdev = netdev_priv(dev);
2157 
2158 	if (cdev->can.state != CAN_STATE_STOPPED) {
2159 		netdev_err(dev, "Device is in use, please shut it down first\n");
2160 		return -EBUSY;
2161 	}
2162 
2163 	if (ec->rx_max_coalesced_frames_irq > cdev->mcfg[MRAM_RXF0].num) {
2164 		netdev_err(dev, "rx-frames-irq %u greater than the RX FIFO %u\n",
2165 			   ec->rx_max_coalesced_frames_irq,
2166 			   cdev->mcfg[MRAM_RXF0].num);
2167 		return -EINVAL;
2168 	}
2169 	if ((ec->rx_max_coalesced_frames_irq == 0) != (ec->rx_coalesce_usecs_irq == 0)) {
2170 		netdev_err(dev, "rx-frames-irq and rx-usecs-irq can only be set together\n");
2171 		return -EINVAL;
2172 	}
2173 	if (ec->tx_max_coalesced_frames_irq > cdev->mcfg[MRAM_TXE].num) {
2174 		netdev_err(dev, "tx-frames-irq %u greater than the TX event FIFO %u\n",
2175 			   ec->tx_max_coalesced_frames_irq,
2176 			   cdev->mcfg[MRAM_TXE].num);
2177 		return -EINVAL;
2178 	}
2179 	if (ec->tx_max_coalesced_frames_irq > cdev->mcfg[MRAM_TXB].num) {
2180 		netdev_err(dev, "tx-frames-irq %u greater than the TX FIFO %u\n",
2181 			   ec->tx_max_coalesced_frames_irq,
2182 			   cdev->mcfg[MRAM_TXB].num);
2183 		return -EINVAL;
2184 	}
2185 	if ((ec->tx_max_coalesced_frames_irq == 0) != (ec->tx_coalesce_usecs_irq == 0)) {
2186 		netdev_err(dev, "tx-frames-irq and tx-usecs-irq can only be set together\n");
2187 		return -EINVAL;
2188 	}
2189 	if (ec->tx_max_coalesced_frames > cdev->mcfg[MRAM_TXE].num) {
2190 		netdev_err(dev, "tx-frames %u greater than the TX event FIFO %u\n",
2191 			   ec->tx_max_coalesced_frames,
2192 			   cdev->mcfg[MRAM_TXE].num);
2193 		return -EINVAL;
2194 	}
2195 	if (ec->tx_max_coalesced_frames > cdev->mcfg[MRAM_TXB].num) {
2196 		netdev_err(dev, "tx-frames %u greater than the TX FIFO %u\n",
2197 			   ec->tx_max_coalesced_frames,
2198 			   cdev->mcfg[MRAM_TXB].num);
2199 		return -EINVAL;
2200 	}
2201 	if (ec->rx_coalesce_usecs_irq != 0 && ec->tx_coalesce_usecs_irq != 0 &&
2202 	    ec->rx_coalesce_usecs_irq != ec->tx_coalesce_usecs_irq) {
2203 		netdev_err(dev, "rx-usecs-irq %u needs to be equal to tx-usecs-irq %u if both are enabled\n",
2204 			   ec->rx_coalesce_usecs_irq,
2205 			   ec->tx_coalesce_usecs_irq);
2206 		return -EINVAL;
2207 	}
2208 
2209 	cdev->rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
2210 	cdev->rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
2211 	cdev->tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
2212 	cdev->tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
2213 	cdev->tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
2214 
2215 	if (cdev->rx_coalesce_usecs_irq)
2216 		cdev->irq_timer_wait =
2217 			ns_to_ktime(cdev->rx_coalesce_usecs_irq * NSEC_PER_USEC);
2218 	else
2219 		cdev->irq_timer_wait =
2220 			ns_to_ktime(cdev->tx_coalesce_usecs_irq * NSEC_PER_USEC);
2221 
2222 	return 0;
2223 }
2224 
2225 static const struct ethtool_ops m_can_ethtool_ops_coalescing = {
2226 	.supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS_IRQ |
2227 		ETHTOOL_COALESCE_RX_MAX_FRAMES_IRQ |
2228 		ETHTOOL_COALESCE_TX_USECS_IRQ |
2229 		ETHTOOL_COALESCE_TX_MAX_FRAMES |
2230 		ETHTOOL_COALESCE_TX_MAX_FRAMES_IRQ,
2231 	.get_ts_info = ethtool_op_get_ts_info,
2232 	.get_coalesce = m_can_get_coalesce,
2233 	.set_coalesce = m_can_set_coalesce,
2234 };
2235 
2236 static const struct ethtool_ops m_can_ethtool_ops = {
2237 	.get_ts_info = ethtool_op_get_ts_info,
2238 };
2239 
register_m_can_dev(struct m_can_classdev * cdev)2240 static int register_m_can_dev(struct m_can_classdev *cdev)
2241 {
2242 	struct net_device *dev = cdev->net;
2243 
2244 	dev->flags |= IFF_ECHO;	/* we support local echo */
2245 	dev->netdev_ops = &m_can_netdev_ops;
2246 	if (dev->irq && cdev->is_peripheral)
2247 		dev->ethtool_ops = &m_can_ethtool_ops_coalescing;
2248 	else
2249 		dev->ethtool_ops = &m_can_ethtool_ops;
2250 
2251 	return register_candev(dev);
2252 }
2253 
m_can_check_mram_cfg(struct m_can_classdev * cdev,u32 mram_max_size)2254 int m_can_check_mram_cfg(struct m_can_classdev *cdev, u32 mram_max_size)
2255 {
2256 	u32 total_size;
2257 
2258 	total_size = cdev->mcfg[MRAM_TXB].off - cdev->mcfg[MRAM_SIDF].off +
2259 			cdev->mcfg[MRAM_TXB].num * TXB_ELEMENT_SIZE;
2260 	if (total_size > mram_max_size) {
2261 		dev_err(cdev->dev, "Total size of mram config(%u) exceeds mram(%u)\n",
2262 			total_size, mram_max_size);
2263 		return -EINVAL;
2264 	}
2265 
2266 	return 0;
2267 }
2268 EXPORT_SYMBOL_GPL(m_can_check_mram_cfg);
2269 
m_can_of_parse_mram(struct m_can_classdev * cdev,const u32 * mram_config_vals)2270 static void m_can_of_parse_mram(struct m_can_classdev *cdev,
2271 				const u32 *mram_config_vals)
2272 {
2273 	cdev->mcfg[MRAM_SIDF].off = mram_config_vals[0];
2274 	cdev->mcfg[MRAM_SIDF].num = mram_config_vals[1];
2275 	cdev->mcfg[MRAM_XIDF].off = cdev->mcfg[MRAM_SIDF].off +
2276 		cdev->mcfg[MRAM_SIDF].num * SIDF_ELEMENT_SIZE;
2277 	cdev->mcfg[MRAM_XIDF].num = mram_config_vals[2];
2278 	cdev->mcfg[MRAM_RXF0].off = cdev->mcfg[MRAM_XIDF].off +
2279 		cdev->mcfg[MRAM_XIDF].num * XIDF_ELEMENT_SIZE;
2280 	cdev->mcfg[MRAM_RXF0].num = mram_config_vals[3] &
2281 		FIELD_MAX(RXFC_FS_MASK);
2282 	cdev->mcfg[MRAM_RXF1].off = cdev->mcfg[MRAM_RXF0].off +
2283 		cdev->mcfg[MRAM_RXF0].num * RXF0_ELEMENT_SIZE;
2284 	cdev->mcfg[MRAM_RXF1].num = mram_config_vals[4] &
2285 		FIELD_MAX(RXFC_FS_MASK);
2286 	cdev->mcfg[MRAM_RXB].off = cdev->mcfg[MRAM_RXF1].off +
2287 		cdev->mcfg[MRAM_RXF1].num * RXF1_ELEMENT_SIZE;
2288 	cdev->mcfg[MRAM_RXB].num = mram_config_vals[5];
2289 	cdev->mcfg[MRAM_TXE].off = cdev->mcfg[MRAM_RXB].off +
2290 		cdev->mcfg[MRAM_RXB].num * RXB_ELEMENT_SIZE;
2291 	cdev->mcfg[MRAM_TXE].num = mram_config_vals[6];
2292 	cdev->mcfg[MRAM_TXB].off = cdev->mcfg[MRAM_TXE].off +
2293 		cdev->mcfg[MRAM_TXE].num * TXE_ELEMENT_SIZE;
2294 	cdev->mcfg[MRAM_TXB].num = mram_config_vals[7] &
2295 		FIELD_MAX(TXBC_NDTB_MASK);
2296 
2297 	dev_dbg(cdev->dev,
2298 		"sidf 0x%x %d xidf 0x%x %d rxf0 0x%x %d rxf1 0x%x %d rxb 0x%x %d txe 0x%x %d txb 0x%x %d\n",
2299 		cdev->mcfg[MRAM_SIDF].off, cdev->mcfg[MRAM_SIDF].num,
2300 		cdev->mcfg[MRAM_XIDF].off, cdev->mcfg[MRAM_XIDF].num,
2301 		cdev->mcfg[MRAM_RXF0].off, cdev->mcfg[MRAM_RXF0].num,
2302 		cdev->mcfg[MRAM_RXF1].off, cdev->mcfg[MRAM_RXF1].num,
2303 		cdev->mcfg[MRAM_RXB].off, cdev->mcfg[MRAM_RXB].num,
2304 		cdev->mcfg[MRAM_TXE].off, cdev->mcfg[MRAM_TXE].num,
2305 		cdev->mcfg[MRAM_TXB].off, cdev->mcfg[MRAM_TXB].num);
2306 }
2307 
m_can_init_ram(struct m_can_classdev * cdev)2308 int m_can_init_ram(struct m_can_classdev *cdev)
2309 {
2310 	int end, i, start;
2311 	int err = 0;
2312 
2313 	/* initialize the entire Message RAM in use to avoid possible
2314 	 * ECC/parity checksum errors when reading an uninitialized buffer
2315 	 */
2316 	start = cdev->mcfg[MRAM_SIDF].off;
2317 	end = cdev->mcfg[MRAM_TXB].off +
2318 		cdev->mcfg[MRAM_TXB].num * TXB_ELEMENT_SIZE;
2319 
2320 	for (i = start; i < end; i += 4) {
2321 		err = m_can_fifo_write_no_off(cdev, i, 0x0);
2322 		if (err)
2323 			break;
2324 	}
2325 
2326 	return err;
2327 }
2328 EXPORT_SYMBOL_GPL(m_can_init_ram);
2329 
m_can_class_get_clocks(struct m_can_classdev * cdev)2330 int m_can_class_get_clocks(struct m_can_classdev *cdev)
2331 {
2332 	int ret = 0;
2333 
2334 	cdev->hclk = devm_clk_get(cdev->dev, "hclk");
2335 	cdev->cclk = devm_clk_get(cdev->dev, "cclk");
2336 
2337 	if (IS_ERR(cdev->hclk) || IS_ERR(cdev->cclk)) {
2338 		dev_err(cdev->dev, "no clock found\n");
2339 		ret = -ENODEV;
2340 	}
2341 
2342 	return ret;
2343 }
2344 EXPORT_SYMBOL_GPL(m_can_class_get_clocks);
2345 
m_can_class_allocate_dev(struct device * dev,int sizeof_priv)2346 struct m_can_classdev *m_can_class_allocate_dev(struct device *dev,
2347 						int sizeof_priv)
2348 {
2349 	struct m_can_classdev *class_dev = NULL;
2350 	u32 mram_config_vals[MRAM_CFG_LEN];
2351 	struct net_device *net_dev;
2352 	u32 tx_fifo_size;
2353 	int ret;
2354 
2355 	ret = fwnode_property_read_u32_array(dev_fwnode(dev),
2356 					     "bosch,mram-cfg",
2357 					     mram_config_vals,
2358 					     sizeof(mram_config_vals) / 4);
2359 	if (ret) {
2360 		dev_err(dev, "Could not get Message RAM configuration.");
2361 		goto out;
2362 	}
2363 
2364 	/* Get TX FIFO size
2365 	 * Defines the total amount of echo buffers for loopback
2366 	 */
2367 	tx_fifo_size = mram_config_vals[7];
2368 
2369 	/* allocate the m_can device */
2370 	net_dev = alloc_candev(sizeof_priv, tx_fifo_size);
2371 	if (!net_dev) {
2372 		dev_err(dev, "Failed to allocate CAN device");
2373 		goto out;
2374 	}
2375 
2376 	class_dev = netdev_priv(net_dev);
2377 	class_dev->net = net_dev;
2378 	class_dev->dev = dev;
2379 	SET_NETDEV_DEV(net_dev, dev);
2380 
2381 	m_can_of_parse_mram(class_dev, mram_config_vals);
2382 out:
2383 	return class_dev;
2384 }
2385 EXPORT_SYMBOL_GPL(m_can_class_allocate_dev);
2386 
m_can_class_free_dev(struct net_device * net)2387 void m_can_class_free_dev(struct net_device *net)
2388 {
2389 	free_candev(net);
2390 }
2391 EXPORT_SYMBOL_GPL(m_can_class_free_dev);
2392 
m_can_class_register(struct m_can_classdev * cdev)2393 int m_can_class_register(struct m_can_classdev *cdev)
2394 {
2395 	int ret;
2396 
2397 	cdev->tx_fifo_size = max(1, min(cdev->mcfg[MRAM_TXB].num,
2398 					cdev->mcfg[MRAM_TXE].num));
2399 	if (cdev->is_peripheral) {
2400 		cdev->tx_ops =
2401 			devm_kzalloc(cdev->dev,
2402 				     cdev->tx_fifo_size * sizeof(*cdev->tx_ops),
2403 				     GFP_KERNEL);
2404 		if (!cdev->tx_ops) {
2405 			dev_err(cdev->dev, "Failed to allocate tx_ops for workqueue\n");
2406 			return -ENOMEM;
2407 		}
2408 	}
2409 
2410 	ret = m_can_clk_start(cdev);
2411 	if (ret)
2412 		return ret;
2413 
2414 	if (cdev->is_peripheral) {
2415 		ret = can_rx_offload_add_manual(cdev->net, &cdev->offload,
2416 						NAPI_POLL_WEIGHT);
2417 		if (ret)
2418 			goto clk_disable;
2419 	}
2420 
2421 	if (!cdev->net->irq) {
2422 		dev_dbg(cdev->dev, "Polling enabled, initialize hrtimer");
2423 		hrtimer_init(&cdev->hrtimer, CLOCK_MONOTONIC,
2424 			     HRTIMER_MODE_REL_PINNED);
2425 		cdev->hrtimer.function = &hrtimer_callback;
2426 	} else {
2427 		hrtimer_init(&cdev->hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2428 		cdev->hrtimer.function = m_can_coalescing_timer;
2429 	}
2430 
2431 	ret = m_can_dev_setup(cdev);
2432 	if (ret)
2433 		goto rx_offload_del;
2434 
2435 	ret = register_m_can_dev(cdev);
2436 	if (ret) {
2437 		dev_err(cdev->dev, "registering %s failed (err=%d)\n",
2438 			cdev->net->name, ret);
2439 		goto rx_offload_del;
2440 	}
2441 
2442 	of_can_transceiver(cdev->net);
2443 
2444 	dev_info(cdev->dev, "%s device registered (irq=%d, version=%d)\n",
2445 		 KBUILD_MODNAME, cdev->net->irq, cdev->version);
2446 
2447 	/* Probe finished
2448 	 * Stop clocks. They will be reactivated once the M_CAN device is opened
2449 	 */
2450 	m_can_clk_stop(cdev);
2451 
2452 	return 0;
2453 
2454 rx_offload_del:
2455 	if (cdev->is_peripheral)
2456 		can_rx_offload_del(&cdev->offload);
2457 clk_disable:
2458 	m_can_clk_stop(cdev);
2459 
2460 	return ret;
2461 }
2462 EXPORT_SYMBOL_GPL(m_can_class_register);
2463 
m_can_class_unregister(struct m_can_classdev * cdev)2464 void m_can_class_unregister(struct m_can_classdev *cdev)
2465 {
2466 	if (cdev->is_peripheral)
2467 		can_rx_offload_del(&cdev->offload);
2468 	unregister_candev(cdev->net);
2469 }
2470 EXPORT_SYMBOL_GPL(m_can_class_unregister);
2471 
m_can_class_suspend(struct device * dev)2472 int m_can_class_suspend(struct device *dev)
2473 {
2474 	struct m_can_classdev *cdev = dev_get_drvdata(dev);
2475 	struct net_device *ndev = cdev->net;
2476 	int ret = 0;
2477 
2478 	if (netif_running(ndev)) {
2479 		netif_stop_queue(ndev);
2480 		netif_device_detach(ndev);
2481 
2482 		/* leave the chip running with rx interrupt enabled if it is
2483 		 * used as a wake-up source. Coalescing needs to be reset then,
2484 		 * the timer is cancelled here, interrupts are done in resume.
2485 		 */
2486 		if (cdev->pm_wake_source) {
2487 			hrtimer_cancel(&cdev->hrtimer);
2488 			m_can_write(cdev, M_CAN_IE, IR_RF0N);
2489 
2490 			if (cdev->ops->deinit)
2491 				ret = cdev->ops->deinit(cdev);
2492 		} else {
2493 			m_can_stop(ndev);
2494 		}
2495 
2496 		m_can_clk_stop(cdev);
2497 	}
2498 
2499 	pinctrl_pm_select_sleep_state(dev);
2500 
2501 	cdev->can.state = CAN_STATE_SLEEPING;
2502 
2503 	return ret;
2504 }
2505 EXPORT_SYMBOL_GPL(m_can_class_suspend);
2506 
m_can_class_resume(struct device * dev)2507 int m_can_class_resume(struct device *dev)
2508 {
2509 	struct m_can_classdev *cdev = dev_get_drvdata(dev);
2510 	struct net_device *ndev = cdev->net;
2511 	int ret = 0;
2512 
2513 	pinctrl_pm_select_default_state(dev);
2514 
2515 	cdev->can.state = CAN_STATE_ERROR_ACTIVE;
2516 
2517 	if (netif_running(ndev)) {
2518 		ret = m_can_clk_start(cdev);
2519 		if (ret)
2520 			return ret;
2521 
2522 		if (cdev->pm_wake_source) {
2523 			/* Restore active interrupts but disable coalescing as
2524 			 * we may have missed important waterlevel interrupts
2525 			 * between suspend and resume. Timers are already
2526 			 * stopped in suspend. Here we enable all interrupts
2527 			 * again.
2528 			 */
2529 			cdev->active_interrupts |= IR_RF0N | IR_TEFN;
2530 
2531 			if (cdev->ops->init)
2532 				ret = cdev->ops->init(cdev);
2533 
2534 			m_can_write(cdev, M_CAN_IE, cdev->active_interrupts);
2535 		} else {
2536 			ret  = m_can_start(ndev);
2537 			if (ret) {
2538 				m_can_clk_stop(cdev);
2539 				return ret;
2540 			}
2541 		}
2542 
2543 		netif_device_attach(ndev);
2544 		netif_start_queue(ndev);
2545 	}
2546 
2547 	return ret;
2548 }
2549 EXPORT_SYMBOL_GPL(m_can_class_resume);
2550 
2551 MODULE_AUTHOR("Dong Aisheng <b29396@freescale.com>");
2552 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com>");
2553 MODULE_LICENSE("GPL v2");
2554 MODULE_DESCRIPTION("CAN bus driver for Bosch M_CAN controller");
2555