1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (c) 2024 AIROHA Inc
4 * Author: Lorenzo Bianconi <lorenzo@kernel.org>
5 */
6
7 #ifndef AIROHA_ETH_H
8 #define AIROHA_ETH_H
9
10 #include <linux/debugfs.h>
11 #include <linux/etherdevice.h>
12 #include <linux/iopoll.h>
13 #include <linux/kernel.h>
14 #include <linux/netdevice.h>
15 #include <linux/reset.h>
16 #include <linux/soc/airoha/airoha_offload.h>
17 #include <net/dsa.h>
18
19 #define AIROHA_MAX_NUM_GDM_PORTS 4
20 #define AIROHA_MAX_NUM_GDM_DEVS 2
21 #define AIROHA_MAX_NUM_QDMA 2
22 #define AIROHA_MAX_NUM_IRQ_BANKS 4
23 #define AIROHA_MAX_DSA_PORTS 7
24 #define AIROHA_MAX_NUM_RSTS 3
25 #define AIROHA_MAX_MTU 9220
26 #define AIROHA_MAX_RX_SIZE 16128
27 #define AIROHA_MAX_PACKET_SIZE 2048
28 #define AIROHA_NUM_QOS_CHANNELS 4
29 #define AIROHA_NUM_QOS_QUEUES 8
30 #define AIROHA_NUM_TX_RING 32
31 #define AIROHA_NUM_RX_RING 32
32 #define AIROHA_NUM_NETDEV_TX_RINGS (AIROHA_NUM_TX_RING + \
33 AIROHA_NUM_QOS_CHANNELS)
34 #define AIROHA_FE_MC_MAX_VLAN_TABLE 64
35 #define AIROHA_FE_MC_MAX_VLAN_PORT 16
36 #define AIROHA_NUM_TX_IRQ 2
37 #define AIROHA_RX_HEADROOM (NET_SKB_PAD + NET_IP_ALIGN)
38 #define AIROHA_RX_LEN(_n) ((_n) - AIROHA_RX_HEADROOM)
39 #define HW_DSCP_NUM 2048
40 #define IRQ_QUEUE_LEN(_n) ((_n) ? 1024 : 2048)
41 #define TX_DSCP_NUM 1024
42 #define RX_DSCP_NUM(_n) \
43 ((_n) == 2 ? 128 : \
44 (_n) == 11 ? 128 : \
45 (_n) == 15 ? 128 : \
46 (_n) == 0 ? 1024 : 16)
47
48 #define PSE_RSV_PAGES 128
49 #define PSE_QUEUE_RSV_PAGES 64
50
51 #define QDMA_METER_IDX(_n) ((_n) & 0xff)
52 #define QDMA_METER_GROUP(_n) (((_n) >> 8) & 0x3)
53
54 #define PPE_SRAM_NUM_ENTRIES (8 * 1024)
55 #define PPE_STATS_NUM_ENTRIES (4 * 1024)
56 #define PPE_DRAM_NUM_ENTRIES (16 * 1024)
57 #define PPE_ENTRY_SIZE 80
58 #define PPE_RAM_NUM_ENTRIES_SHIFT(_n) (__ffs((_n) >> 10))
59
60 #define MTK_HDR_LEN 4
61 #define MTK_HDR_XMIT_TAGGED_TPID_8100 1
62 #define MTK_HDR_XMIT_TAGGED_TPID_88A8 2
63
64 enum {
65 QDMA_INT_REG_IDX0,
66 QDMA_INT_REG_IDX1,
67 QDMA_INT_REG_IDX2,
68 QDMA_INT_REG_IDX3,
69 QDMA_INT_REG_IDX4,
70 QDMA_INT_REG_MAX
71 };
72
73 enum {
74 HSGMII_LAN_7581_PCIE0_SRCPORT = 0x16,
75 HSGMII_LAN_7581_PCIE1_SRCPORT,
76 HSGMII_LAN_7581_ETH_SRCPORT,
77 HSGMII_LAN_7581_USB_SRCPORT,
78 };
79
80 enum {
81 HSGMII_LAN_7583_ETH_SRCPORT = 0x16,
82 HSGMII_LAN_7583_PCIE_SRCPORT = 0x18,
83 HSGMII_LAN_7583_USB_SRCPORT,
84 };
85
86 enum {
87 XSI_PCIE0_VIP_PORT_MASK = BIT(22),
88 XSI_PCIE1_VIP_PORT_MASK = BIT(23),
89 XSI_USB_VIP_PORT_MASK = BIT(25),
90 XSI_ETH_VIP_PORT_MASK = BIT(24),
91 };
92
93 enum {
94 DEV_STATE_INITIALIZED,
95 DEV_STATE_REGISTERED,
96 };
97
98 enum {
99 CDM_CRSN_QSEL_Q1 = 1,
100 CDM_CRSN_QSEL_Q5 = 5,
101 CDM_CRSN_QSEL_Q6 = 6,
102 CDM_CRSN_QSEL_Q15 = 15,
103 };
104
105 enum {
106 CRSN_08 = 0x8,
107 CRSN_21 = 0x15, /* KA */
108 CRSN_22 = 0x16, /* hit bind and force route to CPU */
109 CRSN_24 = 0x18,
110 CRSN_25 = 0x19,
111 };
112
113 enum airoha_gdm_index {
114 AIROHA_GDM1_IDX = 1,
115 AIROHA_GDM2_IDX = 2,
116 AIROHA_GDM3_IDX = 3,
117 AIROHA_GDM4_IDX = 4,
118 };
119
120 enum {
121 FE_PSE_PORT_CDM1,
122 FE_PSE_PORT_GDM1,
123 FE_PSE_PORT_GDM2,
124 FE_PSE_PORT_GDM3,
125 FE_PSE_PORT_PPE1,
126 FE_PSE_PORT_CDM2,
127 FE_PSE_PORT_CDM3,
128 FE_PSE_PORT_CDM4,
129 FE_PSE_PORT_PPE2,
130 FE_PSE_PORT_GDM4,
131 FE_PSE_PORT_CDM5,
132 FE_PSE_PORT_DROP = 0xf,
133 };
134
135 enum tx_sched_mode {
136 TC_SCH_WRR8,
137 TC_SCH_SP,
138 TC_SCH_WRR7,
139 TC_SCH_WRR6,
140 TC_SCH_WRR5,
141 TC_SCH_WRR4,
142 TC_SCH_WRR3,
143 TC_SCH_WRR2,
144 };
145
146 enum trtcm_unit_type {
147 TRTCM_BYTE_UNIT,
148 TRTCM_PACKET_UNIT,
149 };
150
151 enum trtcm_param_type {
152 TRTCM_MISC_MODE, /* meter_en, pps_mode, tick_sel */
153 TRTCM_TOKEN_RATE_MODE,
154 TRTCM_BUCKETSIZE_SHIFT_MODE,
155 TRTCM_BUCKET_COUNTER_MODE,
156 };
157
158 enum trtcm_mode_type {
159 TRTCM_COMMIT_MODE,
160 TRTCM_PEAK_MODE,
161 };
162
163 enum trtcm_param {
164 TRTCM_TICK_SEL = BIT(0),
165 TRTCM_PKT_MODE = BIT(1),
166 TRTCM_METER_MODE = BIT(2),
167 };
168
169 #define MIN_TOKEN_SIZE 4096
170 #define MAX_TOKEN_SIZE_OFFSET 17
171 #define TRTCM_TOKEN_RATE_MASK GENMASK(23, 6)
172 #define TRTCM_TOKEN_RATE_FRACTION_MASK GENMASK(5, 0)
173
174 enum airoha_dma_map_type {
175 AIROHA_DMA_UNMAPPED,
176 AIROHA_DMA_MAP_SINGLE,
177 AIROHA_DMA_MAP_PAGE,
178 };
179
180 struct airoha_queue_entry {
181 union {
182 void *buf;
183 struct {
184 struct list_head list;
185 struct sk_buff *skb;
186 enum airoha_dma_map_type dma_type;
187 };
188 };
189 dma_addr_t dma_addr;
190 u16 dma_len;
191 };
192
193 struct airoha_queue {
194 struct airoha_qdma *qdma;
195
196 /* protect concurrent queue accesses */
197 spinlock_t lock;
198 struct airoha_queue_entry *entry;
199 struct airoha_qdma_desc *desc;
200 u16 head;
201 u16 tail;
202
203 int queued;
204 int ndesc;
205 int free_thr;
206 int buf_size;
207 bool txq_stopped;
208 bool flushing;
209
210 struct napi_struct napi;
211 struct page_pool *page_pool;
212 struct sk_buff *skb;
213
214 struct list_head tx_list;
215 };
216
217 struct airoha_tx_irq_queue {
218 struct airoha_qdma *qdma;
219
220 struct napi_struct napi;
221
222 int size;
223 u32 *q;
224 };
225
226 struct airoha_hw_stats {
227 struct u64_stats_sync syncp;
228
229 /* get_stats64 */
230 u64 rx_ok_pkts;
231 u64 tx_ok_pkts;
232 u64 rx_ok_bytes;
233 u64 tx_ok_bytes;
234 u64 rx_multicast;
235 u64 rx_errors;
236 u64 rx_drops;
237 u64 tx_drops;
238 u64 rx_crc_error;
239 u64 rx_over_errors;
240 /* ethtool stats */
241 u64 tx_broadcast;
242 u64 tx_multicast;
243 u64 tx_len[7];
244 u64 rx_broadcast;
245 u64 rx_fragment;
246 u64 rx_jabber;
247 u64 rx_len[7];
248 };
249
250 enum {
251 AIROHA_FOE_STATE_INVALID,
252 AIROHA_FOE_STATE_UNBIND,
253 AIROHA_FOE_STATE_BIND,
254 AIROHA_FOE_STATE_FIN
255 };
256
257 enum {
258 PPE_PKT_TYPE_IPV4_HNAPT = 0,
259 PPE_PKT_TYPE_IPV4_ROUTE = 1,
260 PPE_PKT_TYPE_BRIDGE = 2,
261 PPE_PKT_TYPE_IPV4_DSLITE = 3,
262 PPE_PKT_TYPE_IPV6_ROUTE_3T = 4,
263 PPE_PKT_TYPE_IPV6_ROUTE_5T = 5,
264 PPE_PKT_TYPE_IPV6_6RD = 7,
265 };
266
267 #define AIROHA_FOE_MAC_SMAC_ID GENMASK(20, 16)
268 #define AIROHA_FOE_MAC_PPPOE_ID GENMASK(15, 0)
269
270 #define AIROHA_FOE_MAC_WDMA_QOS GENMASK(15, 12)
271 #define AIROHA_FOE_MAC_WDMA_BAND BIT(11)
272 #define AIROHA_FOE_MAC_WDMA_WCID GENMASK(10, 0)
273
274 struct airoha_foe_mac_info_common {
275 u16 vlan1;
276 u16 etype;
277
278 u32 dest_mac_hi;
279
280 u16 vlan2;
281 u16 dest_mac_lo;
282
283 u32 src_mac_hi;
284 };
285
286 struct airoha_foe_mac_info {
287 struct airoha_foe_mac_info_common common;
288
289 u16 pppoe_id;
290 u16 src_mac_lo;
291
292 u32 meter;
293 };
294
295 #define AIROHA_FOE_IB1_UNBIND_PREBIND BIT(24)
296 #define AIROHA_FOE_IB1_UNBIND_PACKETS GENMASK(23, 8)
297 #define AIROHA_FOE_IB1_UNBIND_TIMESTAMP GENMASK(7, 0)
298
299 #define AIROHA_FOE_IB1_BIND_STATIC BIT(31)
300 #define AIROHA_FOE_IB1_BIND_UDP BIT(30)
301 #define AIROHA_FOE_IB1_BIND_STATE GENMASK(29, 28)
302 #define AIROHA_FOE_IB1_BIND_PACKET_TYPE GENMASK(27, 25)
303 #define AIROHA_FOE_IB1_BIND_TTL BIT(24)
304 #define AIROHA_FOE_IB1_BIND_TUNNEL_DECAP BIT(23)
305 #define AIROHA_FOE_IB1_BIND_PPPOE BIT(22)
306 #define AIROHA_FOE_IB1_BIND_VPM GENMASK(21, 20)
307 #define AIROHA_FOE_IB1_BIND_VLAN_LAYER GENMASK(19, 16)
308 #define AIROHA_FOE_IB1_BIND_KEEPALIVE BIT(15)
309 #define AIROHA_FOE_IB1_BIND_TIMESTAMP GENMASK(14, 0)
310
311 #define AIROHA_FOE_IB2_DSCP GENMASK(31, 24)
312 #define AIROHA_FOE_IB2_PORT_AG GENMASK(23, 13)
313 #define AIROHA_FOE_IB2_PCP BIT(12)
314 #define AIROHA_FOE_IB2_MULTICAST BIT(11)
315 #define AIROHA_FOE_IB2_FAST_PATH BIT(10)
316 #define AIROHA_FOE_IB2_PSE_QOS BIT(9)
317 #define AIROHA_FOE_IB2_PSE_PORT GENMASK(8, 5)
318 #define AIROHA_FOE_IB2_NBQ GENMASK(4, 0)
319
320 #define AIROHA_FOE_ACTDP GENMASK(31, 24)
321 #define AIROHA_FOE_SHAPER_ID GENMASK(23, 16)
322 #define AIROHA_FOE_CHANNEL GENMASK(15, 11)
323 #define AIROHA_FOE_QID GENMASK(10, 8)
324 #define AIROHA_FOE_DPI BIT(7)
325 #define AIROHA_FOE_TUNNEL BIT(6)
326 #define AIROHA_FOE_TUNNEL_ID GENMASK(5, 0)
327
328 #define AIROHA_FOE_TUNNEL_MTU GENMASK(31, 16)
329 #define AIROHA_FOE_ACNT_GRP3 GENMASK(15, 9)
330 #define AIROHA_FOE_METER_GRP3 GENMASK(8, 5)
331 #define AIROHA_FOE_METER_GRP2 GENMASK(4, 0)
332
333 struct airoha_foe_bridge {
334 u32 dest_mac_hi;
335
336 u16 src_mac_hi;
337 u16 dest_mac_lo;
338
339 u32 src_mac_lo;
340
341 u32 ib2;
342
343 u32 rsv[5];
344
345 u32 data;
346
347 struct airoha_foe_mac_info l2;
348 };
349
350 struct airoha_foe_ipv4_tuple {
351 u32 src_ip;
352 u32 dest_ip;
353 union {
354 struct {
355 u16 dest_port;
356 u16 src_port;
357 };
358 struct {
359 u8 protocol;
360 u8 _pad[3]; /* fill with 0xa5a5a5 */
361 };
362 u32 ports;
363 };
364 };
365
366 struct airoha_foe_ipv4 {
367 struct airoha_foe_ipv4_tuple orig_tuple;
368
369 u32 ib2;
370
371 struct airoha_foe_ipv4_tuple new_tuple;
372
373 u32 rsv[2];
374
375 u32 data;
376
377 struct airoha_foe_mac_info l2;
378 };
379
380 struct airoha_foe_ipv4_dslite {
381 struct airoha_foe_ipv4_tuple ip4;
382
383 u32 ib2;
384
385 u8 flow_label[3];
386 u8 priority;
387
388 u32 rsv[4];
389
390 u32 data;
391
392 struct airoha_foe_mac_info l2;
393 };
394
395 struct airoha_foe_ipv6 {
396 u32 src_ip[4];
397 u32 dest_ip[4];
398
399 union {
400 struct {
401 u16 dest_port;
402 u16 src_port;
403 };
404 struct {
405 u8 protocol;
406 u8 pad[3];
407 };
408 u32 ports;
409 };
410
411 u32 data;
412
413 u32 ib2;
414
415 struct airoha_foe_mac_info_common l2;
416
417 u32 meter;
418 };
419
420 struct airoha_foe_entry {
421 union {
422 struct {
423 u32 ib1;
424 union {
425 struct airoha_foe_bridge bridge;
426 struct airoha_foe_ipv4 ipv4;
427 struct airoha_foe_ipv4_dslite dslite;
428 struct airoha_foe_ipv6 ipv6;
429 DECLARE_FLEX_ARRAY(u32, d);
430 };
431 };
432 u8 data[PPE_ENTRY_SIZE];
433 };
434 };
435
436 struct airoha_foe_stats {
437 u32 bytes;
438 u32 packets;
439 };
440
441 struct airoha_foe_stats64 {
442 u64 bytes;
443 u64 packets;
444 };
445
446 struct airoha_flow_data {
447 struct ethhdr eth;
448
449 union {
450 struct {
451 __be32 src_addr;
452 __be32 dst_addr;
453 } v4;
454
455 struct {
456 struct in6_addr src_addr;
457 struct in6_addr dst_addr;
458 } v6;
459 };
460
461 __be16 src_port;
462 __be16 dst_port;
463
464 struct {
465 struct {
466 u16 id;
467 __be16 proto;
468 } hdr[2];
469 u8 num;
470 } vlan;
471 struct {
472 u16 sid;
473 u8 num;
474 } pppoe;
475 };
476
477 enum airoha_flow_entry_type {
478 FLOW_TYPE_L4,
479 FLOW_TYPE_L2,
480 FLOW_TYPE_L2_SUBFLOW,
481 };
482
483 struct airoha_flow_table_entry {
484 union {
485 struct hlist_node list; /* PPE L3 flow entry */
486 struct {
487 struct rhash_head l2_node; /* L2 flow entry */
488 struct hlist_head l2_flows; /* PPE L2 subflows list */
489 };
490 };
491
492 struct hlist_node l2_subflow_node; /* PPE L2 subflow entry */
493 u32 hash;
494
495 struct airoha_foe_stats64 stats;
496 enum airoha_flow_entry_type type;
497
498 struct rhash_head node;
499 unsigned long cookie;
500
501 /* Must be last --ends in a flexible-array member. */
502 struct airoha_foe_entry data;
503 };
504
505 struct airoha_wdma_info {
506 u8 idx;
507 u8 queue;
508 u16 wcid;
509 u8 bss;
510 };
511
512 /* RX queue to IRQ mapping: BIT(q) in IRQ(n) */
513 #define RX_IRQ0_BANK_PIN_MASK 0x839f
514 #define RX_IRQ1_BANK_PIN_MASK 0x7fe00000
515 #define RX_IRQ2_BANK_PIN_MASK 0x20
516 #define RX_IRQ3_BANK_PIN_MASK 0x40
517 #define RX_IRQ_BANK_PIN_MASK(_n) \
518 (((_n) == 3) ? RX_IRQ3_BANK_PIN_MASK : \
519 ((_n) == 2) ? RX_IRQ2_BANK_PIN_MASK : \
520 ((_n) == 1) ? RX_IRQ1_BANK_PIN_MASK : \
521 RX_IRQ0_BANK_PIN_MASK)
522
523 struct airoha_irq_bank {
524 struct airoha_qdma *qdma;
525
526 /* protect concurrent irqmask accesses */
527 spinlock_t irq_lock;
528 u32 irqmask[QDMA_INT_REG_MAX];
529 int irq;
530 };
531
532 struct airoha_qdma {
533 struct airoha_eth *eth;
534 void __iomem *regs;
535
536 struct airoha_irq_bank irq_banks[AIROHA_MAX_NUM_IRQ_BANKS];
537
538 struct airoha_tx_irq_queue q_tx_irq[AIROHA_NUM_TX_IRQ];
539
540 struct airoha_queue q_tx[AIROHA_NUM_TX_RING];
541 struct airoha_queue q_rx[AIROHA_NUM_RX_RING];
542
543 DECLARE_BITMAP(qos_channel_map, AIROHA_NUM_QOS_CHANNELS);
544 };
545
546 enum airoha_priv_flags {
547 AIROHA_PRIV_F_WAN = BIT(0),
548 };
549
550 struct airoha_gdm_dev {
551 struct airoha_gdm_port *port;
552 struct airoha_qdma *qdma;
553 struct airoha_eth *eth;
554
555 DECLARE_BITMAP(qos_sq_bmap, AIROHA_NUM_QOS_CHANNELS);
556 /* qos stats counters */
557 u64 cpu_tx_packets;
558 u64 fwd_tx_packets;
559
560 u32 flags;
561 int nbq;
562
563 struct airoha_hw_stats stats;
564 };
565
566 struct airoha_gdm_port {
567 struct airoha_gdm_dev *devs[AIROHA_MAX_NUM_GDM_DEVS];
568 int id;
569 int users;
570
571 /* protect concurrent hw_stats accesses */
572 spinlock_t stats_lock;
573
574 struct metadata_dst *dsa_meta[AIROHA_MAX_DSA_PORTS];
575 };
576
577 #define AIROHA_RXD4_PPE_CPU_REASON GENMASK(20, 16)
578 #define AIROHA_RXD4_FOE_ENTRY GENMASK(15, 0)
579
580 struct airoha_ppe {
581 struct airoha_ppe_dev dev;
582 struct airoha_eth *eth;
583
584 void *foe;
585 dma_addr_t foe_dma;
586
587 struct rhashtable l2_flows;
588
589 struct hlist_head *foe_flow;
590 u16 *foe_check_time;
591
592 struct airoha_foe_stats *foe_stats;
593 dma_addr_t foe_stats_dma;
594
595 struct dentry *debugfs_dir;
596 };
597
598 struct airoha_eth_soc_data {
599 u16 version;
600 const char * const *xsi_rsts_names;
601 int num_xsi_rsts;
602 int num_ppe;
603 struct {
604 int (*get_sport)(struct airoha_gdm_port *port, int nbq);
605 u32 (*get_vip_port)(struct airoha_gdm_port *port, int nbq);
606 int (*get_dev_from_sport)(struct airoha_qdma_desc *desc,
607 u16 *port, u16 *dev);
608 } ops;
609 };
610
611 struct airoha_eth {
612 struct device *dev;
613
614 const struct airoha_eth_soc_data *soc;
615
616 unsigned long state;
617 void __iomem *fe_regs;
618
619 struct airoha_npu __rcu *npu;
620
621 struct airoha_ppe *ppe;
622 struct rhashtable flow_table;
623
624 struct reset_control_bulk_data rsts[AIROHA_MAX_NUM_RSTS];
625 struct reset_control_bulk_data *xsi_rsts;
626
627 struct net_device *napi_dev;
628
629 struct airoha_qdma qdma[AIROHA_MAX_NUM_QDMA];
630 struct airoha_gdm_port *ports[AIROHA_MAX_NUM_GDM_PORTS];
631 };
632
633 u32 airoha_rr(void __iomem *base, u32 offset);
634 void airoha_wr(void __iomem *base, u32 offset, u32 val);
635 u32 airoha_rmw(void __iomem *base, u32 offset, u32 mask, u32 val);
636
637 #define airoha_fe_rr(eth, offset) \
638 airoha_rr((eth)->fe_regs, (offset))
639 #define airoha_fe_wr(eth, offset, val) \
640 airoha_wr((eth)->fe_regs, (offset), (val))
641 #define airoha_fe_rmw(eth, offset, mask, val) \
642 airoha_rmw((eth)->fe_regs, (offset), (mask), (val))
643 #define airoha_fe_set(eth, offset, val) \
644 airoha_rmw((eth)->fe_regs, (offset), 0, (val))
645 #define airoha_fe_clear(eth, offset, val) \
646 airoha_rmw((eth)->fe_regs, (offset), (val), 0)
647 #define airoha_fe_get(eth, offset, mask) \
648 FIELD_GET((mask), airoha_fe_rr((eth), (offset)))
649
650 #define airoha_qdma_rr(qdma, offset) \
651 airoha_rr((qdma)->regs, (offset))
652 #define airoha_qdma_wr(qdma, offset, val) \
653 airoha_wr((qdma)->regs, (offset), (val))
654 #define airoha_qdma_rmw(qdma, offset, mask, val) \
655 airoha_rmw((qdma)->regs, (offset), (mask), (val))
656 #define airoha_qdma_set(qdma, offset, val) \
657 airoha_rmw((qdma)->regs, (offset), 0, (val))
658 #define airoha_qdma_clear(qdma, offset, val) \
659 airoha_rmw((qdma)->regs, (offset), (val), 0)
660 #define airoha_qdma_get(qdma, offset, mask) \
661 FIELD_GET((mask), airoha_qdma_rr((qdma), (offset)))
662
airoha_qdma_get_txq(struct airoha_qdma * qdma,u16 qid)663 static inline u16 airoha_qdma_get_txq(struct airoha_qdma *qdma, u16 qid)
664 {
665 return qid % ARRAY_SIZE(qdma->q_tx);
666 }
667
airoha_is_lan_gdm_dev(struct airoha_gdm_dev * dev)668 static inline bool airoha_is_lan_gdm_dev(struct airoha_gdm_dev *dev)
669 {
670 return !(dev->flags & AIROHA_PRIV_F_WAN);
671 }
672
airoha_is_7581(struct airoha_eth * eth)673 static inline bool airoha_is_7581(struct airoha_eth *eth)
674 {
675 return eth->soc->version == 0x7581;
676 }
677
airoha_is_7583(struct airoha_eth * eth)678 static inline bool airoha_is_7583(struct airoha_eth *eth)
679 {
680 return eth->soc->version == 0x7583;
681 }
682
683 int airoha_get_fe_port(struct airoha_gdm_dev *dev);
684 bool airoha_is_valid_gdm_dev(struct airoha_eth *eth,
685 struct airoha_gdm_dev *dev);
686
687 void airoha_ppe_set_xmit_frame_size(struct airoha_gdm_dev *dev);
688 void airoha_ppe_set_cpu_port(struct airoha_gdm_dev *dev, u8 ppe_id, u8 fport);
689 bool airoha_ppe_is_enabled(struct airoha_eth *eth, int index);
690 void airoha_ppe_check_skb(struct airoha_ppe_dev *dev, struct sk_buff *skb,
691 u16 hash, bool rx_wlan);
692 int airoha_ppe_setup_tc_block_cb(struct airoha_ppe_dev *dev, void *type_data);
693 int airoha_ppe_init(struct airoha_eth *eth);
694 void airoha_ppe_deinit(struct airoha_eth *eth);
695 void airoha_ppe_init_upd_mem(struct airoha_gdm_dev *dev, const u8 *addr);
696 u32 airoha_ppe_get_total_num_entries(struct airoha_ppe *ppe);
697 struct airoha_foe_entry *airoha_ppe_foe_get_entry(struct airoha_ppe *ppe,
698 u32 hash);
699 void airoha_ppe_foe_entry_get_stats(struct airoha_ppe *ppe, u32 hash,
700 struct airoha_foe_stats64 *stats);
701
702 #ifdef CONFIG_DEBUG_FS
703 int airoha_ppe_debugfs_init(struct airoha_ppe *ppe);
704 #else
airoha_ppe_debugfs_init(struct airoha_ppe * ppe)705 static inline int airoha_ppe_debugfs_init(struct airoha_ppe *ppe)
706 {
707 return 0;
708 }
709 #endif
710
711 #endif /* AIROHA_ETH_H */
712