1 // SPDX-License-Identifier: GPL-2.0-only 2 // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. 3 4 #include <linux/cleanup.h> 5 #include <linux/module.h> 6 #include <linux/init.h> 7 #include <linux/io.h> 8 #include <linux/platform_device.h> 9 #include <linux/pm_runtime.h> 10 #include <linux/clk.h> 11 #include <sound/soc.h> 12 #include <sound/pcm.h> 13 #include <sound/pcm_params.h> 14 #include <sound/soc-dapm.h> 15 #include <sound/tlv.h> 16 #include <linux/of_clk.h> 17 #include <linux/clk-provider.h> 18 19 #include "lpass-macro-common.h" 20 21 #define CDC_RX_TOP_TOP_CFG0 (0x0000) 22 #define CDC_RX_TOP_SWR_CTRL (0x0008) 23 #define CDC_RX_TOP_DEBUG (0x000C) 24 #define CDC_RX_TOP_DEBUG_BUS (0x0010) 25 #define CDC_RX_TOP_DEBUG_EN0 (0x0014) 26 #define CDC_RX_TOP_DEBUG_EN1 (0x0018) 27 #define CDC_RX_TOP_DEBUG_EN2 (0x001C) 28 #define CDC_RX_TOP_HPHL_COMP_WR_LSB (0x0020) 29 #define CDC_RX_TOP_HPHL_COMP_WR_MSB (0x0024) 30 #define CDC_RX_TOP_HPHL_COMP_LUT (0x0028) 31 #define CDC_RX_TOP_HPH_LUT_BYPASS_MASK BIT(7) 32 #define CDC_RX_TOP_HPHL_COMP_RD_LSB (0x002C) 33 #define CDC_RX_TOP_HPHL_COMP_RD_MSB (0x0030) 34 #define CDC_RX_TOP_HPHR_COMP_WR_LSB (0x0034) 35 #define CDC_RX_TOP_HPHR_COMP_WR_MSB (0x0038) 36 #define CDC_RX_TOP_HPHR_COMP_LUT (0x003C) 37 #define CDC_RX_TOP_HPHR_COMP_RD_LSB (0x0040) 38 #define CDC_RX_TOP_HPHR_COMP_RD_MSB (0x0044) 39 #define CDC_RX_TOP_DSD0_DEBUG_CFG0 (0x0070) 40 #define CDC_RX_TOP_DSD0_DEBUG_CFG1 (0x0074) 41 #define CDC_RX_TOP_DSD0_DEBUG_CFG2 (0x0078) 42 #define CDC_RX_TOP_DSD0_DEBUG_CFG3 (0x007C) 43 #define CDC_RX_TOP_DSD1_DEBUG_CFG0 (0x0080) 44 #define CDC_RX_TOP_DSD1_DEBUG_CFG1 (0x0084) 45 #define CDC_RX_TOP_DSD1_DEBUG_CFG2 (0x0088) 46 #define CDC_RX_TOP_DSD1_DEBUG_CFG3 (0x008C) 47 #define CDC_RX_TOP_RX_I2S_CTL (0x0090) 48 #define CDC_RX_TOP_TX_I2S2_CTL (0x0094) 49 #define CDC_RX_TOP_I2S_CLK (0x0098) 50 #define CDC_RX_TOP_I2S_RESET (0x009C) 51 #define CDC_RX_TOP_I2S_MUX (0x00A0) 52 #define CDC_RX_CLK_RST_CTRL_MCLK_CONTROL (0x0100) 53 #define CDC_RX_CLK_MCLK_EN_MASK BIT(0) 54 #define CDC_RX_CLK_MCLK_ENABLE BIT(0) 55 #define CDC_RX_CLK_MCLK2_EN_MASK BIT(1) 56 #define CDC_RX_CLK_MCLK2_ENABLE BIT(1) 57 #define CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL (0x0104) 58 #define CDC_RX_FS_MCLK_CNT_EN_MASK BIT(0) 59 #define CDC_RX_FS_MCLK_CNT_ENABLE BIT(0) 60 #define CDC_RX_FS_MCLK_CNT_CLR_MASK BIT(1) 61 #define CDC_RX_FS_MCLK_CNT_CLR BIT(1) 62 #define CDC_RX_CLK_RST_CTRL_SWR_CONTROL (0x0108) 63 #define CDC_RX_SWR_CLK_EN_MASK BIT(0) 64 #define CDC_RX_SWR_RESET_MASK BIT(1) 65 #define CDC_RX_SWR_RESET BIT(1) 66 #define CDC_RX_CLK_RST_CTRL_DSD_CONTROL (0x010C) 67 #define CDC_RX_CLK_RST_CTRL_ASRC_SHARE_CONTROL (0x0110) 68 #define CDC_RX_SOFTCLIP_CRC (0x0140) 69 #define CDC_RX_SOFTCLIP_CLK_EN_MASK BIT(0) 70 #define CDC_RX_SOFTCLIP_SOFTCLIP_CTRL (0x0144) 71 #define CDC_RX_SOFTCLIP_EN_MASK BIT(0) 72 #define CDC_RX_INP_MUX_RX_INT0_CFG0 (0x0180) 73 #define CDC_RX_INTX_1_MIX_INP0_SEL_MASK GENMASK(3, 0) 74 #define CDC_RX_INTX_1_MIX_INP1_SEL_MASK GENMASK(7, 4) 75 #define CDC_RX_INP_MUX_RX_INT0_CFG1 (0x0184) 76 #define CDC_RX_INTX_2_SEL_MASK GENMASK(3, 0) 77 #define CDC_RX_INTX_1_MIX_INP2_SEL_MASK GENMASK(7, 4) 78 #define CDC_RX_INP_MUX_RX_INT1_CFG0 (0x0188) 79 #define CDC_RX_INP_MUX_RX_INT1_CFG1 (0x018C) 80 #define CDC_RX_INP_MUX_RX_INT2_CFG0 (0x0190) 81 #define CDC_RX_INP_MUX_RX_INT2_CFG1 (0x0194) 82 #define CDC_RX_INP_MUX_RX_MIX_CFG4 (0x0198) 83 #define CDC_RX_INP_MUX_RX_MIX_CFG5 (0x019C) 84 #define CDC_RX_INP_MUX_SIDETONE_SRC_CFG0 (0x01A0) 85 #define CDC_RX_CLSH_CRC (0x0200) 86 #define CDC_RX_CLSH_CLK_EN_MASK BIT(0) 87 #define CDC_RX_CLSH_DLY_CTRL (0x0204) 88 #define CDC_RX_CLSH_DECAY_CTRL (0x0208) 89 #define CDC_RX_CLSH_DECAY_RATE_MASK GENMASK(2, 0) 90 #define CDC_RX_CLSH_HPH_V_PA (0x020C) 91 #define CDC_RX_CLSH_HPH_V_PA_MIN_MASK GENMASK(5, 0) 92 #define CDC_RX_CLSH_EAR_V_PA (0x0210) 93 #define CDC_RX_CLSH_HPH_V_HD (0x0214) 94 #define CDC_RX_CLSH_EAR_V_HD (0x0218) 95 #define CDC_RX_CLSH_K1_MSB (0x021C) 96 #define CDC_RX_CLSH_K1_MSB_COEFF_MASK GENMASK(3, 0) 97 #define CDC_RX_CLSH_K1_LSB (0x0220) 98 #define CDC_RX_CLSH_K2_MSB (0x0224) 99 #define CDC_RX_CLSH_K2_LSB (0x0228) 100 #define CDC_RX_CLSH_IDLE_CTRL (0x022C) 101 #define CDC_RX_CLSH_IDLE_HPH (0x0230) 102 #define CDC_RX_CLSH_IDLE_EAR (0x0234) 103 #define CDC_RX_CLSH_TEST0 (0x0238) 104 #define CDC_RX_CLSH_TEST1 (0x023C) 105 #define CDC_RX_CLSH_OVR_VREF (0x0240) 106 #define CDC_RX_CLSH_CLSG_CTL (0x0244) 107 #define CDC_RX_CLSH_CLSG_CFG1 (0x0248) 108 #define CDC_RX_CLSH_CLSG_CFG2 (0x024C) 109 #define CDC_RX_BCL_VBAT_PATH_CTL (0x0280) 110 #define CDC_RX_BCL_VBAT_CFG (0x0284) 111 #define CDC_RX_BCL_VBAT_ADC_CAL1 (0x0288) 112 #define CDC_RX_BCL_VBAT_ADC_CAL2 (0x028C) 113 #define CDC_RX_BCL_VBAT_ADC_CAL3 (0x0290) 114 #define CDC_RX_BCL_VBAT_PK_EST1 (0x0294) 115 #define CDC_RX_BCL_VBAT_PK_EST2 (0x0298) 116 #define CDC_RX_BCL_VBAT_PK_EST3 (0x029C) 117 #define CDC_RX_BCL_VBAT_RF_PROC1 (0x02A0) 118 #define CDC_RX_BCL_VBAT_RF_PROC2 (0x02A4) 119 #define CDC_RX_BCL_VBAT_TAC1 (0x02A8) 120 #define CDC_RX_BCL_VBAT_TAC2 (0x02AC) 121 #define CDC_RX_BCL_VBAT_TAC3 (0x02B0) 122 #define CDC_RX_BCL_VBAT_TAC4 (0x02B4) 123 #define CDC_RX_BCL_VBAT_GAIN_UPD1 (0x02B8) 124 #define CDC_RX_BCL_VBAT_GAIN_UPD2 (0x02BC) 125 #define CDC_RX_BCL_VBAT_GAIN_UPD3 (0x02C0) 126 #define CDC_RX_BCL_VBAT_GAIN_UPD4 (0x02C4) 127 #define CDC_RX_BCL_VBAT_GAIN_UPD5 (0x02C8) 128 #define CDC_RX_BCL_VBAT_DEBUG1 (0x02CC) 129 #define CDC_RX_BCL_VBAT_GAIN_UPD_MON (0x02D0) 130 #define CDC_RX_BCL_VBAT_GAIN_MON_VAL (0x02D4) 131 #define CDC_RX_BCL_VBAT_BAN (0x02D8) 132 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD1 (0x02DC) 133 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD2 (0x02E0) 134 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD3 (0x02E4) 135 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD4 (0x02E8) 136 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD5 (0x02EC) 137 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD6 (0x02F0) 138 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD7 (0x02F4) 139 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD8 (0x02F8) 140 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD9 (0x02FC) 141 #define CDC_RX_BCL_VBAT_ATTN1 (0x0300) 142 #define CDC_RX_BCL_VBAT_ATTN2 (0x0304) 143 #define CDC_RX_BCL_VBAT_ATTN3 (0x0308) 144 #define CDC_RX_BCL_VBAT_DECODE_CTL1 (0x030C) 145 #define CDC_RX_BCL_VBAT_DECODE_CTL2 (0x0310) 146 #define CDC_RX_BCL_VBAT_DECODE_CFG1 (0x0314) 147 #define CDC_RX_BCL_VBAT_DECODE_CFG2 (0x0318) 148 #define CDC_RX_BCL_VBAT_DECODE_CFG3 (0x031C) 149 #define CDC_RX_BCL_VBAT_DECODE_CFG4 (0x0320) 150 #define CDC_RX_BCL_VBAT_DECODE_ST (0x0324) 151 #define CDC_RX_INTR_CTRL_CFG (0x0340) 152 #define CDC_RX_INTR_CTRL_CLR_COMMIT (0x0344) 153 #define CDC_RX_INTR_CTRL_PIN1_MASK0 (0x0360) 154 #define CDC_RX_INTR_CTRL_PIN1_STATUS0 (0x0368) 155 #define CDC_RX_INTR_CTRL_PIN1_CLEAR0 (0x0370) 156 #define CDC_RX_INTR_CTRL_PIN2_MASK0 (0x0380) 157 #define CDC_RX_INTR_CTRL_PIN2_STATUS0 (0x0388) 158 #define CDC_RX_INTR_CTRL_PIN2_CLEAR0 (0x0390) 159 #define CDC_RX_INTR_CTRL_LEVEL0 (0x03C0) 160 #define CDC_RX_INTR_CTRL_BYPASS0 (0x03C8) 161 #define CDC_RX_INTR_CTRL_SET0 (0x03D0) 162 #define CDC_RX_RXn_RX_PATH_CTL(rx, n) (0x0400 + rx->rxn_reg_stride * n) 163 #define CDC_RX_RX0_RX_PATH_CTL (0x0400) 164 #define CDC_RX_PATH_RESET_EN_MASK BIT(6) 165 #define CDC_RX_PATH_CLK_EN_MASK BIT(5) 166 #define CDC_RX_PATH_CLK_ENABLE BIT(5) 167 #define CDC_RX_PATH_PGA_MUTE_MASK BIT(4) 168 #define CDC_RX_PATH_PGA_MUTE_ENABLE BIT(4) 169 #define CDC_RX_PATH_PCM_RATE_MASK GENMASK(3, 0) 170 #define CDC_RX_RXn_RX_PATH_CFG0(rx, n) (0x0404 + rx->rxn_reg_stride * n) 171 #define CDC_RX_RXn_COMP_EN_MASK BIT(1) 172 #define CDC_RX_RX0_RX_PATH_CFG0 (0x0404) 173 #define CDC_RX_RXn_CLSH_EN_MASK BIT(6) 174 #define CDC_RX_DLY_ZN_EN_MASK BIT(3) 175 #define CDC_RX_DLY_ZN_ENABLE BIT(3) 176 #define CDC_RX_RXn_HD2_EN_MASK BIT(2) 177 #define CDC_RX_RXn_RX_PATH_CFG1(rx, n) (0x0408 + rx->rxn_reg_stride * n) 178 #define CDC_RX_RXn_SIDETONE_EN_MASK BIT(4) 179 #define CDC_RX_RX0_RX_PATH_CFG1 (0x0408) 180 #define CDC_RX_RX0_HPH_L_EAR_SEL_MASK BIT(1) 181 #define CDC_RX_RXn_RX_PATH_CFG2(rx, n) (0x040C + rx->rxn_reg_stride * n) 182 #define CDC_RX_RXn_HPF_CUT_FREQ_MASK GENMASK(1, 0) 183 #define CDC_RX_RX0_RX_PATH_CFG2 (0x040C) 184 #define CDC_RX_RXn_RX_PATH_CFG3(rx, n) (0x0410 + rx->rxn_reg_stride * n) 185 #define CDC_RX_RX0_RX_PATH_CFG3 (0x0410) 186 #define CDC_RX_DC_COEFF_SEL_MASK GENMASK(1, 0) 187 #define CDC_RX_DC_COEFF_SEL_TWO 0x2 188 #define CDC_RX_RXn_RX_VOL_CTL(rx, n) (0x0414 + rx->rxn_reg_stride * n) 189 #define CDC_RX_RX0_RX_VOL_CTL (0x0414) 190 #define CDC_RX_RXn_RX_PATH_MIX_CTL(rx, n) (0x0418 + rx->rxn_reg_stride * n) 191 #define CDC_RX_RXn_MIX_PCM_RATE_MASK GENMASK(3, 0) 192 #define CDC_RX_RXn_MIX_RESET_MASK BIT(6) 193 #define CDC_RX_RXn_MIX_RESET BIT(6) 194 #define CDC_RX_RXn_MIX_CLK_EN_MASK BIT(5) 195 #define CDC_RX_RX0_RX_PATH_MIX_CTL (0x0418) 196 #define CDC_RX_RX0_RX_PATH_MIX_CFG (0x041C) 197 #define CDC_RX_RXn_RX_VOL_MIX_CTL(rx, n) (0x0420 + rx->rxn_reg_stride * n) 198 #define CDC_RX_RX0_RX_VOL_MIX_CTL (0x0420) 199 #define CDC_RX_RX0_RX_PATH_SEC1 (0x0424) 200 #define CDC_RX_RX0_RX_PATH_SEC2 (0x0428) 201 #define CDC_RX_RX0_RX_PATH_SEC3 (0x042C) 202 #define CDC_RX_RXn_RX_PATH_SEC3(rx, n) (0x042c + rx->rxn_reg_stride * n) 203 #define CDC_RX_RX0_RX_PATH_SEC4 (0x0430) 204 #define CDC_RX_RX0_RX_PATH_SEC7 (0x0434) 205 #define CDC_RX_RXn_RX_PATH_SEC7(rx, n) \ 206 (0x0434 + (rx->rxn_reg_stride * n) + ((n > 1) ? rx->rxn_reg_stride2 : 0)) 207 #define CDC_RX_DSM_OUT_DELAY_SEL_MASK GENMASK(2, 0) 208 #define CDC_RX_DSM_OUT_DELAY_TWO_SAMPLE 0x2 209 #define CDC_RX_RX0_RX_PATH_MIX_SEC0 (0x0438) 210 #define CDC_RX_RX0_RX_PATH_MIX_SEC1 (0x043C) 211 #define CDC_RX_RXn_RX_PATH_DSM_CTL(rx, n) \ 212 (0x0440 + (rx->rxn_reg_stride * n) + ((n > 1) ? rx->rxn_reg_stride2 : 0)) 213 #define CDC_RX_RXn_DSM_CLK_EN_MASK BIT(0) 214 #define CDC_RX_RX0_RX_PATH_DSM_CTL (0x0440) 215 #define CDC_RX_RX0_RX_PATH_DSM_DATA1 (0x0444) 216 #define CDC_RX_RX0_RX_PATH_DSM_DATA2 (0x0448) 217 #define CDC_RX_RX0_RX_PATH_DSM_DATA3 (0x044C) 218 #define CDC_RX_RX0_RX_PATH_DSM_DATA4 (0x0450) 219 #define CDC_RX_RX0_RX_PATH_DSM_DATA5 (0x0454) 220 #define CDC_RX_RX0_RX_PATH_DSM_DATA6 (0x0458) 221 /* RX offsets prior to 2.5 codec version */ 222 #define CDC_RX_RX1_RX_PATH_CTL (0x0480) 223 #define CDC_RX_RX1_RX_PATH_CFG0 (0x0484) 224 #define CDC_RX_RX1_RX_PATH_CFG1 (0x0488) 225 #define CDC_RX_RX1_RX_PATH_CFG2 (0x048C) 226 #define CDC_RX_RX1_RX_PATH_CFG3 (0x0490) 227 #define CDC_RX_RX1_RX_VOL_CTL (0x0494) 228 #define CDC_RX_RX1_RX_PATH_MIX_CTL (0x0498) 229 #define CDC_RX_RX1_RX_PATH_MIX_CFG (0x049C) 230 #define CDC_RX_RX1_RX_VOL_MIX_CTL (0x04A0) 231 #define CDC_RX_RX1_RX_PATH_SEC1 (0x04A4) 232 #define CDC_RX_RX1_RX_PATH_SEC2 (0x04A8) 233 #define CDC_RX_RX1_RX_PATH_SEC3 (0x04AC) 234 #define CDC_RX_RXn_HD2_ALPHA_MASK GENMASK(5, 2) 235 #define CDC_RX_RX1_RX_PATH_SEC4 (0x04B0) 236 #define CDC_RX_RX1_RX_PATH_SEC7 (0x04B4) 237 #define CDC_RX_RX1_RX_PATH_MIX_SEC0 (0x04B8) 238 #define CDC_RX_RX1_RX_PATH_MIX_SEC1 (0x04BC) 239 #define CDC_RX_RX1_RX_PATH_DSM_CTL (0x04C0) 240 #define CDC_RX_RX1_RX_PATH_DSM_DATA1 (0x04C4) 241 #define CDC_RX_RX1_RX_PATH_DSM_DATA2 (0x04C8) 242 #define CDC_RX_RX1_RX_PATH_DSM_DATA3 (0x04CC) 243 #define CDC_RX_RX1_RX_PATH_DSM_DATA4 (0x04D0) 244 #define CDC_RX_RX1_RX_PATH_DSM_DATA5 (0x04D4) 245 #define CDC_RX_RX1_RX_PATH_DSM_DATA6 (0x04D8) 246 #define CDC_RX_RX2_RX_PATH_CTL (0x0500) 247 #define CDC_RX_RX2_RX_PATH_CFG0 (0x0504) 248 #define CDC_RX_RX2_CLSH_EN_MASK BIT(4) 249 #define CDC_RX_RX2_DLY_Z_EN_MASK BIT(3) 250 #define CDC_RX_RX2_RX_PATH_CFG1 (0x0508) 251 #define CDC_RX_RX2_RX_PATH_CFG2 (0x050C) 252 #define CDC_RX_RX2_RX_PATH_CFG3 (0x0510) 253 #define CDC_RX_RX2_RX_VOL_CTL (0x0514) 254 #define CDC_RX_RX2_RX_PATH_MIX_CTL (0x0518) 255 #define CDC_RX_RX2_RX_PATH_MIX_CFG (0x051C) 256 #define CDC_RX_RX2_RX_VOL_MIX_CTL (0x0520) 257 #define CDC_RX_RX2_RX_PATH_SEC0 (0x0524) 258 #define CDC_RX_RX2_RX_PATH_SEC1 (0x0528) 259 #define CDC_RX_RX2_RX_PATH_SEC2 (0x052C) 260 #define CDC_RX_RX2_RX_PATH_SEC3 (0x0530) 261 #define CDC_RX_RX2_RX_PATH_SEC4 (0x0534) 262 #define CDC_RX_RX2_RX_PATH_SEC5 (0x0538) 263 #define CDC_RX_RX2_RX_PATH_SEC6 (0x053C) 264 #define CDC_RX_RX2_RX_PATH_SEC7 (0x0540) 265 #define CDC_RX_RX2_RX_PATH_MIX_SEC0 (0x0544) 266 #define CDC_RX_RX2_RX_PATH_MIX_SEC1 (0x0548) 267 #define CDC_RX_RX2_RX_PATH_DSM_CTL (0x054C) 268 269 /* LPASS CODEC version 2.5 rx reg offsets */ 270 #define CDC_2_5_RX_RX1_RX_PATH_CTL (0x04c0) 271 #define CDC_2_5_RX_RX1_RX_PATH_CFG0 (0x04c4) 272 #define CDC_2_5_RX_RX1_RX_PATH_CFG1 (0x04c8) 273 #define CDC_2_5_RX_RX1_RX_PATH_CFG2 (0x04cC) 274 #define CDC_2_5_RX_RX1_RX_PATH_CFG3 (0x04d0) 275 #define CDC_2_5_RX_RX1_RX_VOL_CTL (0x04d4) 276 #define CDC_2_5_RX_RX1_RX_PATH_MIX_CTL (0x04d8) 277 #define CDC_2_5_RX_RX1_RX_PATH_MIX_CFG (0x04dC) 278 #define CDC_2_5_RX_RX1_RX_VOL_MIX_CTL (0x04e0) 279 #define CDC_2_5_RX_RX1_RX_PATH_SEC1 (0x04e4) 280 #define CDC_2_5_RX_RX1_RX_PATH_SEC2 (0x04e8) 281 #define CDC_2_5_RX_RX1_RX_PATH_SEC3 (0x04eC) 282 #define CDC_2_5_RX_RX1_RX_PATH_SEC4 (0x04f0) 283 #define CDC_2_5_RX_RX1_RX_PATH_SEC7 (0x04f4) 284 #define CDC_2_5_RX_RX1_RX_PATH_MIX_SEC0 (0x04f8) 285 #define CDC_2_5_RX_RX1_RX_PATH_MIX_SEC1 (0x04fC) 286 #define CDC_2_5_RX_RX1_RX_PATH_DSM_CTL (0x0500) 287 #define CDC_2_5_RX_RX1_RX_PATH_DSM_DATA1 (0x0504) 288 #define CDC_2_5_RX_RX1_RX_PATH_DSM_DATA2 (0x0508) 289 #define CDC_2_5_RX_RX1_RX_PATH_DSM_DATA3 (0x050C) 290 #define CDC_2_5_RX_RX1_RX_PATH_DSM_DATA4 (0x0510) 291 #define CDC_2_5_RX_RX1_RX_PATH_DSM_DATA5 (0x0514) 292 #define CDC_2_5_RX_RX1_RX_PATH_DSM_DATA6 (0x0518) 293 294 #define CDC_2_5_RX_RX2_RX_PATH_CTL (0x0580) 295 #define CDC_2_5_RX_RX2_RX_PATH_CFG0 (0x0584) 296 #define CDC_2_5_RX_RX2_RX_PATH_CFG1 (0x0588) 297 #define CDC_2_5_RX_RX2_RX_PATH_CFG2 (0x058C) 298 #define CDC_2_5_RX_RX2_RX_PATH_CFG3 (0x0590) 299 #define CDC_2_5_RX_RX2_RX_VOL_CTL (0x0594) 300 #define CDC_2_5_RX_RX2_RX_PATH_MIX_CTL (0x0598) 301 #define CDC_2_5_RX_RX2_RX_PATH_MIX_CFG (0x059C) 302 #define CDC_2_5_RX_RX2_RX_VOL_MIX_CTL (0x05a0) 303 #define CDC_2_5_RX_RX2_RX_PATH_SEC0 (0x05a4) 304 #define CDC_2_5_RX_RX2_RX_PATH_SEC1 (0x05a8) 305 #define CDC_2_5_RX_RX2_RX_PATH_SEC2 (0x05aC) 306 #define CDC_2_5_RX_RX2_RX_PATH_SEC3 (0x05b0) 307 #define CDC_2_5_RX_RX2_RX_PATH_SEC4 (0x05b4) 308 #define CDC_2_5_RX_RX2_RX_PATH_SEC5 (0x05b8) 309 #define CDC_2_5_RX_RX2_RX_PATH_SEC6 (0x05bC) 310 #define CDC_2_5_RX_RX2_RX_PATH_SEC7 (0x05c0) 311 #define CDC_2_5_RX_RX2_RX_PATH_MIX_SEC0 (0x05c4) 312 #define CDC_2_5_RX_RX2_RX_PATH_MIX_SEC1 (0x05c8) 313 #define CDC_2_5_RX_RX2_RX_PATH_DSM_CTL (0x05cC) 314 315 #define CDC_RX_IDLE_DETECT_PATH_CTL (0x0780) 316 #define CDC_RX_IDLE_DETECT_CFG0 (0x0784) 317 #define CDC_RX_IDLE_DETECT_CFG1 (0x0788) 318 #define CDC_RX_IDLE_DETECT_CFG2 (0x078C) 319 #define CDC_RX_IDLE_DETECT_CFG3 (0x0790) 320 #define CDC_RX_COMPANDERn_CTL0(n) (0x0800 + 0x40 * n) 321 #define CDC_RX_COMPANDERn_CLK_EN_MASK BIT(0) 322 #define CDC_RX_COMPANDERn_SOFT_RST_MASK BIT(1) 323 #define CDC_RX_COMPANDERn_HALT_MASK BIT(2) 324 #define CDC_RX_COMPANDER0_CTL0 (0x0800) 325 #define CDC_RX_COMPANDER0_CTL1 (0x0804) 326 #define CDC_RX_COMPANDER0_CTL2 (0x0808) 327 #define CDC_RX_COMPANDER0_CTL3 (0x080C) 328 #define CDC_RX_COMPANDER0_CTL4 (0x0810) 329 #define CDC_RX_COMPANDER0_CTL5 (0x0814) 330 #define CDC_RX_COMPANDER0_CTL6 (0x0818) 331 #define CDC_RX_COMPANDER0_CTL7 (0x081C) 332 #define CDC_RX_COMPANDER1_CTL0 (0x0840) 333 #define CDC_RX_COMPANDER1_CTL1 (0x0844) 334 #define CDC_RX_COMPANDER1_CTL2 (0x0848) 335 #define CDC_RX_COMPANDER1_CTL3 (0x084C) 336 #define CDC_RX_COMPANDER1_CTL4 (0x0850) 337 #define CDC_RX_COMPANDER1_CTL5 (0x0854) 338 #define CDC_RX_COMPANDER1_CTL6 (0x0858) 339 #define CDC_RX_COMPANDER1_CTL7 (0x085C) 340 #define CDC_RX_COMPANDER1_HPH_LOW_PWR_MODE_MASK BIT(5) 341 #define CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL (0x0A00) 342 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL (0x0A04) 343 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL (0x0A08) 344 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL (0x0A0C) 345 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL (0x0A10) 346 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B5_CTL (0x0A14) 347 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B6_CTL (0x0A18) 348 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B7_CTL (0x0A1C) 349 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B8_CTL (0x0A20) 350 #define CDC_RX_SIDETONE_IIR0_IIR_CTL (0x0A24) 351 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL (0x0A28) 352 #define CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL (0x0A2C) 353 #define CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL (0x0A30) 354 #define CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL (0x0A80) 355 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL (0x0A84) 356 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL (0x0A88) 357 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL (0x0A8C) 358 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL (0x0A90) 359 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B5_CTL (0x0A94) 360 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B6_CTL (0x0A98) 361 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B7_CTL (0x0A9C) 362 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B8_CTL (0x0AA0) 363 #define CDC_RX_SIDETONE_IIR1_IIR_CTL (0x0AA4) 364 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL (0x0AA8) 365 #define CDC_RX_SIDETONE_IIR1_IIR_COEF_B1_CTL (0x0AAC) 366 #define CDC_RX_SIDETONE_IIR1_IIR_COEF_B2_CTL (0x0AB0) 367 #define CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0 (0x0B00) 368 #define CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1 (0x0B04) 369 #define CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2 (0x0B08) 370 #define CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3 (0x0B0C) 371 #define CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0 (0x0B10) 372 #define CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1 (0x0B14) 373 #define CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2 (0x0B18) 374 #define CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3 (0x0B1C) 375 #define CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL (0x0B40) 376 #define CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CFG1 (0x0B44) 377 #define CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL (0x0B50) 378 #define CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CFG1 (0x0B54) 379 #define CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL (0x0C00) 380 #define CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0 (0x0C04) 381 #define CDC_RX_EC_REF_HQ1_EC_REF_HQ_PATH_CTL (0x0C40) 382 #define CDC_RX_EC_REF_HQ1_EC_REF_HQ_CFG0 (0x0C44) 383 #define CDC_RX_EC_REF_HQ2_EC_REF_HQ_PATH_CTL (0x0C80) 384 #define CDC_RX_EC_REF_HQ2_EC_REF_HQ_CFG0 (0x0C84) 385 #define CDC_RX_EC_ASRC0_CLK_RST_CTL (0x0D00) 386 #define CDC_RX_EC_ASRC0_CTL0 (0x0D04) 387 #define CDC_RX_EC_ASRC0_CTL1 (0x0D08) 388 #define CDC_RX_EC_ASRC0_FIFO_CTL (0x0D0C) 389 #define CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB (0x0D10) 390 #define CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB (0x0D14) 391 #define CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB (0x0D18) 392 #define CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB (0x0D1C) 393 #define CDC_RX_EC_ASRC0_STATUS_FIFO (0x0D20) 394 #define CDC_RX_EC_ASRC1_CLK_RST_CTL (0x0D40) 395 #define CDC_RX_EC_ASRC1_CTL0 (0x0D44) 396 #define CDC_RX_EC_ASRC1_CTL1 (0x0D48) 397 #define CDC_RX_EC_ASRC1_FIFO_CTL (0x0D4C) 398 #define CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB (0x0D50) 399 #define CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB (0x0D54) 400 #define CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB (0x0D58) 401 #define CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB (0x0D5C) 402 #define CDC_RX_EC_ASRC1_STATUS_FIFO (0x0D60) 403 #define CDC_RX_EC_ASRC2_CLK_RST_CTL (0x0D80) 404 #define CDC_RX_EC_ASRC2_CTL0 (0x0D84) 405 #define CDC_RX_EC_ASRC2_CTL1 (0x0D88) 406 #define CDC_RX_EC_ASRC2_FIFO_CTL (0x0D8C) 407 #define CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB (0x0D90) 408 #define CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB (0x0D94) 409 #define CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB (0x0D98) 410 #define CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB (0x0D9C) 411 #define CDC_RX_EC_ASRC2_STATUS_FIFO (0x0DA0) 412 #define CDC_RX_DSD0_PATH_CTL (0x0F00) 413 #define CDC_RX_DSD0_CFG0 (0x0F04) 414 #define CDC_RX_DSD0_CFG1 (0x0F08) 415 #define CDC_RX_DSD0_CFG2 (0x0F0C) 416 #define CDC_RX_DSD1_PATH_CTL (0x0F80) 417 #define CDC_RX_DSD1_CFG0 (0x0F84) 418 #define CDC_RX_DSD1_CFG1 (0x0F88) 419 #define CDC_RX_DSD1_CFG2 (0x0F8C) 420 #define RX_MAX_OFFSET (0x0F8C) 421 422 #define MCLK_FREQ 19200000 423 424 #define RX_MACRO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 425 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ 426 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\ 427 SNDRV_PCM_RATE_384000) 428 /* Fractional Rates */ 429 #define RX_MACRO_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\ 430 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800) 431 432 #define RX_MACRO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 433 SNDRV_PCM_FMTBIT_S24_LE |\ 434 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 435 436 #define RX_MACRO_ECHO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 437 SNDRV_PCM_RATE_48000) 438 #define RX_MACRO_ECHO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 439 SNDRV_PCM_FMTBIT_S24_LE |\ 440 SNDRV_PCM_FMTBIT_S24_3LE) 441 442 #define RX_MACRO_MAX_DMA_CH_PER_PORT 2 443 444 #define RX_MACRO_EC_MIX_TX0_MASK 0xf0 445 #define RX_MACRO_EC_MIX_TX1_MASK 0x0f 446 #define RX_MACRO_EC_MIX_TX2_MASK 0x0f 447 448 #define COMP_MAX_COEFF 25 449 #define RX_NUM_CLKS_MAX 5 450 451 struct comp_coeff_val { 452 u8 lsb; 453 u8 msb; 454 }; 455 456 enum { 457 HPH_ULP, 458 HPH_LOHIFI, 459 HPH_MODE_MAX, 460 }; 461 462 static const struct comp_coeff_val comp_coeff_table[HPH_MODE_MAX][COMP_MAX_COEFF] = { 463 { 464 {0x40, 0x00}, 465 {0x4C, 0x00}, 466 {0x5A, 0x00}, 467 {0x6B, 0x00}, 468 {0x7F, 0x00}, 469 {0x97, 0x00}, 470 {0xB3, 0x00}, 471 {0xD5, 0x00}, 472 {0xFD, 0x00}, 473 {0x2D, 0x01}, 474 {0x66, 0x01}, 475 {0xA7, 0x01}, 476 {0xF8, 0x01}, 477 {0x57, 0x02}, 478 {0xC7, 0x02}, 479 {0x4B, 0x03}, 480 {0xE9, 0x03}, 481 {0xA3, 0x04}, 482 {0x7D, 0x05}, 483 {0x90, 0x06}, 484 {0xD1, 0x07}, 485 {0x49, 0x09}, 486 {0x00, 0x0B}, 487 {0x01, 0x0D}, 488 {0x59, 0x0F}, 489 }, 490 { 491 {0x40, 0x00}, 492 {0x4C, 0x00}, 493 {0x5A, 0x00}, 494 {0x6B, 0x00}, 495 {0x80, 0x00}, 496 {0x98, 0x00}, 497 {0xB4, 0x00}, 498 {0xD5, 0x00}, 499 {0xFE, 0x00}, 500 {0x2E, 0x01}, 501 {0x66, 0x01}, 502 {0xA9, 0x01}, 503 {0xF8, 0x01}, 504 {0x56, 0x02}, 505 {0xC4, 0x02}, 506 {0x4F, 0x03}, 507 {0xF0, 0x03}, 508 {0xAE, 0x04}, 509 {0x8B, 0x05}, 510 {0x8E, 0x06}, 511 {0xBC, 0x07}, 512 {0x56, 0x09}, 513 {0x0F, 0x0B}, 514 {0x13, 0x0D}, 515 {0x6F, 0x0F}, 516 }, 517 }; 518 519 enum { 520 INTERP_HPHL, 521 INTERP_HPHR, 522 INTERP_AUX, 523 INTERP_MAX 524 }; 525 526 enum { 527 RX_MACRO_RX0, 528 RX_MACRO_RX1, 529 RX_MACRO_RX2, 530 RX_MACRO_RX3, 531 RX_MACRO_RX4, 532 RX_MACRO_RX5, 533 RX_MACRO_PORTS_MAX 534 }; 535 536 enum { 537 RX_MACRO_COMP1, /* HPH_L */ 538 RX_MACRO_COMP2, /* HPH_R */ 539 RX_MACRO_COMP_MAX 540 }; 541 542 enum { 543 RX_MACRO_EC0_MUX = 0, 544 RX_MACRO_EC1_MUX, 545 RX_MACRO_EC2_MUX, 546 RX_MACRO_EC_MUX_MAX, 547 }; 548 549 enum { 550 INTn_1_INP_SEL_ZERO = 0, 551 INTn_1_INP_SEL_DEC0, 552 INTn_1_INP_SEL_DEC1, 553 INTn_1_INP_SEL_IIR0, 554 INTn_1_INP_SEL_IIR1, 555 INTn_1_INP_SEL_RX0, 556 INTn_1_INP_SEL_RX1, 557 INTn_1_INP_SEL_RX2, 558 INTn_1_INP_SEL_RX3, 559 INTn_1_INP_SEL_RX4, 560 INTn_1_INP_SEL_RX5, 561 }; 562 563 enum { 564 INTn_2_INP_SEL_ZERO = 0, 565 INTn_2_INP_SEL_RX0, 566 INTn_2_INP_SEL_RX1, 567 INTn_2_INP_SEL_RX2, 568 INTn_2_INP_SEL_RX3, 569 INTn_2_INP_SEL_RX4, 570 INTn_2_INP_SEL_RX5, 571 }; 572 573 enum { 574 INTERP_MAIN_PATH, 575 INTERP_MIX_PATH, 576 }; 577 578 /* Codec supports 2 IIR filters */ 579 enum { 580 IIR0 = 0, 581 IIR1, 582 IIR_MAX, 583 }; 584 585 /* Each IIR has 5 Filter Stages */ 586 enum { 587 BAND1 = 0, 588 BAND2, 589 BAND3, 590 BAND4, 591 BAND5, 592 BAND_MAX, 593 }; 594 595 #define RX_MACRO_IIR_FILTER_SIZE (sizeof(u32) * BAND_MAX) 596 597 #define RX_MACRO_IIR_FILTER_CTL(xname, iidx, bidx) \ 598 { \ 599 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 600 .info = rx_macro_iir_filter_info, \ 601 .get = rx_macro_get_iir_band_audio_mixer, \ 602 .put = rx_macro_put_iir_band_audio_mixer, \ 603 .private_value = (unsigned long)&(struct wcd_iir_filter_ctl) { \ 604 .iir_idx = iidx, \ 605 .band_idx = bidx, \ 606 .bytes_ext = {.max = RX_MACRO_IIR_FILTER_SIZE, }, \ 607 } \ 608 } 609 610 struct interp_sample_rate { 611 int sample_rate; 612 int rate_val; 613 }; 614 615 static struct interp_sample_rate sr_val_tbl[] = { 616 {8000, 0x0}, {16000, 0x1}, {32000, 0x3}, {48000, 0x4}, {96000, 0x5}, 617 {192000, 0x6}, {384000, 0x7}, {44100, 0x9}, {88200, 0xA}, 618 {176400, 0xB}, {352800, 0xC}, 619 }; 620 621 /* Matches also rx_macro_mux_text */ 622 enum { 623 RX_MACRO_AIF1_PB, 624 RX_MACRO_AIF2_PB, 625 RX_MACRO_AIF3_PB, 626 RX_MACRO_AIF4_PB, 627 RX_MACRO_AIF_ECHO, 628 RX_MACRO_MAX_DAIS, 629 }; 630 631 enum { 632 RX_MACRO_AIF1_CAP = 0, 633 RX_MACRO_AIF2_CAP, 634 RX_MACRO_AIF3_CAP, 635 RX_MACRO_MAX_AIF_CAP_DAIS 636 }; 637 638 struct rx_macro { 639 struct device *dev; 640 int comp_enabled[RX_MACRO_COMP_MAX]; 641 /* Main path clock users count */ 642 int main_clk_users[INTERP_MAX]; 643 int rx_port_value[RX_MACRO_PORTS_MAX]; 644 u16 prim_int_users[INTERP_MAX]; 645 int rx_mclk_users; 646 int clsh_users; 647 int rx_mclk_cnt; 648 enum lpass_codec_version codec_version; 649 int rxn_reg_stride; 650 int rxn_reg_stride2; 651 bool is_ear_mode_on; 652 bool hph_pwr_mode; 653 bool hph_hd2_mode; 654 struct snd_soc_component *component; 655 unsigned long active_ch_mask[RX_MACRO_MAX_DAIS]; 656 unsigned long active_ch_cnt[RX_MACRO_MAX_DAIS]; 657 u16 bit_width[RX_MACRO_MAX_DAIS]; 658 int is_softclip_on; 659 int is_aux_hpf_on; 660 int softclip_clk_users; 661 struct lpass_macro *pds; 662 struct regmap *regmap; 663 struct clk *mclk; 664 struct clk *npl; 665 struct clk *macro; 666 struct clk *dcodec; 667 struct clk *fsgen; 668 struct clk_hw hw; 669 }; 670 #define to_rx_macro(_hw) container_of(_hw, struct rx_macro, hw) 671 672 struct wcd_iir_filter_ctl { 673 unsigned int iir_idx; 674 unsigned int band_idx; 675 struct soc_bytes_ext bytes_ext; 676 }; 677 678 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400); 679 680 static const char * const rx_int_mix_mux_text[] = { 681 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5" 682 }; 683 684 static const char * const rx_prim_mix_text[] = { 685 "ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2", 686 "RX3", "RX4", "RX5" 687 }; 688 689 static const char * const rx_sidetone_mix_text[] = { 690 "ZERO", "SRC0", "SRC1", "SRC_SUM" 691 }; 692 693 static const char * const iir_inp_mux_text[] = { 694 "ZERO", "DEC0", "DEC1", "DEC2", "DEC3", 695 "RX0", "RX1", "RX2", "RX3", "RX4", "RX5" 696 }; 697 698 static const char * const rx_int_dem_inp_mux_text[] = { 699 "NORMAL_DSM_OUT", "CLSH_DSM_OUT", 700 }; 701 702 static const char * const rx_int0_1_interp_mux_text[] = { 703 "ZERO", "RX INT0_1 MIX1", 704 }; 705 706 static const char * const rx_int1_1_interp_mux_text[] = { 707 "ZERO", "RX INT1_1 MIX1", 708 }; 709 710 static const char * const rx_int2_1_interp_mux_text[] = { 711 "ZERO", "RX INT2_1 MIX1", 712 }; 713 714 static const char * const rx_int0_2_interp_mux_text[] = { 715 "ZERO", "RX INT0_2 MUX", 716 }; 717 718 static const char * const rx_int1_2_interp_mux_text[] = { 719 "ZERO", "RX INT1_2 MUX", 720 }; 721 722 static const char * const rx_int2_2_interp_mux_text[] = { 723 "ZERO", "RX INT2_2 MUX", 724 }; 725 726 /* Order must match RX_MACRO_MAX_DAIS enum (offset by 1) */ 727 static const char *const rx_macro_mux_text[] = { 728 "ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB", "AIF4_PB" 729 }; 730 731 static const char *const rx_macro_hph_pwr_mode_text[] = { 732 "ULP", "LOHIFI" 733 }; 734 735 static const char * const rx_echo_mux_text[] = { 736 "ZERO", "RX_MIX0", "RX_MIX1", "RX_MIX2" 737 }; 738 739 static const struct soc_enum rx_macro_hph_pwr_mode_enum = 740 SOC_ENUM_SINGLE_EXT(2, rx_macro_hph_pwr_mode_text); 741 static const struct soc_enum rx_mix_tx2_mux_enum = 742 SOC_ENUM_SINGLE(CDC_RX_INP_MUX_RX_MIX_CFG5, 0, 4, rx_echo_mux_text); 743 static const struct soc_enum rx_mix_tx1_mux_enum = 744 SOC_ENUM_SINGLE(CDC_RX_INP_MUX_RX_MIX_CFG4, 0, 4, rx_echo_mux_text); 745 static const struct soc_enum rx_mix_tx0_mux_enum = 746 SOC_ENUM_SINGLE(CDC_RX_INP_MUX_RX_MIX_CFG4, 4, 4, rx_echo_mux_text); 747 748 static SOC_ENUM_SINGLE_DECL(rx_int0_2_enum, CDC_RX_INP_MUX_RX_INT0_CFG1, 0, 749 rx_int_mix_mux_text); 750 static SOC_ENUM_SINGLE_DECL(rx_int1_2_enum, CDC_RX_INP_MUX_RX_INT1_CFG1, 0, 751 rx_int_mix_mux_text); 752 static SOC_ENUM_SINGLE_DECL(rx_int2_2_enum, CDC_RX_INP_MUX_RX_INT2_CFG1, 0, 753 rx_int_mix_mux_text); 754 755 static SOC_ENUM_SINGLE_DECL(rx_int0_1_mix_inp0_enum, CDC_RX_INP_MUX_RX_INT0_CFG0, 0, 756 rx_prim_mix_text); 757 static SOC_ENUM_SINGLE_DECL(rx_int0_1_mix_inp1_enum, CDC_RX_INP_MUX_RX_INT0_CFG0, 4, 758 rx_prim_mix_text); 759 static SOC_ENUM_SINGLE_DECL(rx_int0_1_mix_inp2_enum, CDC_RX_INP_MUX_RX_INT0_CFG1, 4, 760 rx_prim_mix_text); 761 static SOC_ENUM_SINGLE_DECL(rx_int1_1_mix_inp0_enum, CDC_RX_INP_MUX_RX_INT1_CFG0, 0, 762 rx_prim_mix_text); 763 static SOC_ENUM_SINGLE_DECL(rx_int1_1_mix_inp1_enum, CDC_RX_INP_MUX_RX_INT1_CFG0, 4, 764 rx_prim_mix_text); 765 static SOC_ENUM_SINGLE_DECL(rx_int1_1_mix_inp2_enum, CDC_RX_INP_MUX_RX_INT1_CFG1, 4, 766 rx_prim_mix_text); 767 static SOC_ENUM_SINGLE_DECL(rx_int2_1_mix_inp0_enum, CDC_RX_INP_MUX_RX_INT2_CFG0, 0, 768 rx_prim_mix_text); 769 static SOC_ENUM_SINGLE_DECL(rx_int2_1_mix_inp1_enum, CDC_RX_INP_MUX_RX_INT2_CFG0, 4, 770 rx_prim_mix_text); 771 static SOC_ENUM_SINGLE_DECL(rx_int2_1_mix_inp2_enum, CDC_RX_INP_MUX_RX_INT2_CFG1, 4, 772 rx_prim_mix_text); 773 774 static SOC_ENUM_SINGLE_DECL(rx_int0_mix2_inp_enum, CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 2, 775 rx_sidetone_mix_text); 776 static SOC_ENUM_SINGLE_DECL(rx_int1_mix2_inp_enum, CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 4, 777 rx_sidetone_mix_text); 778 static SOC_ENUM_SINGLE_DECL(rx_int2_mix2_inp_enum, CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 6, 779 rx_sidetone_mix_text); 780 static SOC_ENUM_SINGLE_DECL(iir0_inp0_enum, CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0, 0, 781 iir_inp_mux_text); 782 static SOC_ENUM_SINGLE_DECL(iir0_inp1_enum, CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1, 0, 783 iir_inp_mux_text); 784 static SOC_ENUM_SINGLE_DECL(iir0_inp2_enum, CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2, 0, 785 iir_inp_mux_text); 786 static SOC_ENUM_SINGLE_DECL(iir0_inp3_enum, CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3, 0, 787 iir_inp_mux_text); 788 static SOC_ENUM_SINGLE_DECL(iir1_inp0_enum, CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0, 0, 789 iir_inp_mux_text); 790 static SOC_ENUM_SINGLE_DECL(iir1_inp1_enum, CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1, 0, 791 iir_inp_mux_text); 792 static SOC_ENUM_SINGLE_DECL(iir1_inp2_enum, CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2, 0, 793 iir_inp_mux_text); 794 static SOC_ENUM_SINGLE_DECL(iir1_inp3_enum, CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3, 0, 795 iir_inp_mux_text); 796 797 static SOC_ENUM_SINGLE_DECL(rx_int0_1_interp_enum, SND_SOC_NOPM, 0, 798 rx_int0_1_interp_mux_text); 799 static SOC_ENUM_SINGLE_DECL(rx_int1_1_interp_enum, SND_SOC_NOPM, 0, 800 rx_int1_1_interp_mux_text); 801 static SOC_ENUM_SINGLE_DECL(rx_int2_1_interp_enum, SND_SOC_NOPM, 0, 802 rx_int2_1_interp_mux_text); 803 static SOC_ENUM_SINGLE_DECL(rx_int0_2_interp_enum, SND_SOC_NOPM, 0, 804 rx_int0_2_interp_mux_text); 805 static SOC_ENUM_SINGLE_DECL(rx_int1_2_interp_enum, SND_SOC_NOPM, 0, 806 rx_int1_2_interp_mux_text); 807 static SOC_ENUM_SINGLE_DECL(rx_int2_2_interp_enum, SND_SOC_NOPM, 0, 808 rx_int2_2_interp_mux_text); 809 static SOC_ENUM_SINGLE_DECL(rx_int0_dem_inp_enum, CDC_RX_RX0_RX_PATH_CFG1, 0, 810 rx_int_dem_inp_mux_text); 811 static SOC_ENUM_SINGLE_DECL(rx_int1_dem_inp_enum, CDC_RX_RX1_RX_PATH_CFG1, 0, 812 rx_int_dem_inp_mux_text); 813 static SOC_ENUM_SINGLE_DECL(rx_2_5_int1_dem_inp_enum, CDC_2_5_RX_RX1_RX_PATH_CFG1, 0, 814 rx_int_dem_inp_mux_text); 815 816 static SOC_ENUM_SINGLE_DECL(rx_macro_rx0_enum, SND_SOC_NOPM, 0, rx_macro_mux_text); 817 static SOC_ENUM_SINGLE_DECL(rx_macro_rx1_enum, SND_SOC_NOPM, 0, rx_macro_mux_text); 818 static SOC_ENUM_SINGLE_DECL(rx_macro_rx2_enum, SND_SOC_NOPM, 0, rx_macro_mux_text); 819 static SOC_ENUM_SINGLE_DECL(rx_macro_rx3_enum, SND_SOC_NOPM, 0, rx_macro_mux_text); 820 static SOC_ENUM_SINGLE_DECL(rx_macro_rx4_enum, SND_SOC_NOPM, 0, rx_macro_mux_text); 821 static SOC_ENUM_SINGLE_DECL(rx_macro_rx5_enum, SND_SOC_NOPM, 0, rx_macro_mux_text); 822 823 static const struct snd_kcontrol_new rx_mix_tx1_mux = 824 SOC_DAPM_ENUM("RX MIX TX1_MUX Mux", rx_mix_tx1_mux_enum); 825 static const struct snd_kcontrol_new rx_mix_tx2_mux = 826 SOC_DAPM_ENUM("RX MIX TX2_MUX Mux", rx_mix_tx2_mux_enum); 827 static const struct snd_kcontrol_new rx_int0_2_mux = 828 SOC_DAPM_ENUM("rx_int0_2", rx_int0_2_enum); 829 static const struct snd_kcontrol_new rx_int1_2_mux = 830 SOC_DAPM_ENUM("rx_int1_2", rx_int1_2_enum); 831 static const struct snd_kcontrol_new rx_int2_2_mux = 832 SOC_DAPM_ENUM("rx_int2_2", rx_int2_2_enum); 833 static const struct snd_kcontrol_new rx_int0_1_mix_inp0_mux = 834 SOC_DAPM_ENUM("rx_int0_1_mix_inp0", rx_int0_1_mix_inp0_enum); 835 static const struct snd_kcontrol_new rx_int0_1_mix_inp1_mux = 836 SOC_DAPM_ENUM("rx_int0_1_mix_inp1", rx_int0_1_mix_inp1_enum); 837 static const struct snd_kcontrol_new rx_int0_1_mix_inp2_mux = 838 SOC_DAPM_ENUM("rx_int0_1_mix_inp2", rx_int0_1_mix_inp2_enum); 839 static const struct snd_kcontrol_new rx_int1_1_mix_inp0_mux = 840 SOC_DAPM_ENUM("rx_int1_1_mix_inp0", rx_int1_1_mix_inp0_enum); 841 static const struct snd_kcontrol_new rx_int1_1_mix_inp1_mux = 842 SOC_DAPM_ENUM("rx_int1_1_mix_inp1", rx_int1_1_mix_inp1_enum); 843 static const struct snd_kcontrol_new rx_int1_1_mix_inp2_mux = 844 SOC_DAPM_ENUM("rx_int1_1_mix_inp2", rx_int1_1_mix_inp2_enum); 845 static const struct snd_kcontrol_new rx_int2_1_mix_inp0_mux = 846 SOC_DAPM_ENUM("rx_int2_1_mix_inp0", rx_int2_1_mix_inp0_enum); 847 static const struct snd_kcontrol_new rx_int2_1_mix_inp1_mux = 848 SOC_DAPM_ENUM("rx_int2_1_mix_inp1", rx_int2_1_mix_inp1_enum); 849 static const struct snd_kcontrol_new rx_int2_1_mix_inp2_mux = 850 SOC_DAPM_ENUM("rx_int2_1_mix_inp2", rx_int2_1_mix_inp2_enum); 851 static const struct snd_kcontrol_new rx_int0_mix2_inp_mux = 852 SOC_DAPM_ENUM("rx_int0_mix2_inp", rx_int0_mix2_inp_enum); 853 static const struct snd_kcontrol_new rx_int1_mix2_inp_mux = 854 SOC_DAPM_ENUM("rx_int1_mix2_inp", rx_int1_mix2_inp_enum); 855 static const struct snd_kcontrol_new rx_int2_mix2_inp_mux = 856 SOC_DAPM_ENUM("rx_int2_mix2_inp", rx_int2_mix2_inp_enum); 857 static const struct snd_kcontrol_new iir0_inp0_mux = 858 SOC_DAPM_ENUM("iir0_inp0", iir0_inp0_enum); 859 static const struct snd_kcontrol_new iir0_inp1_mux = 860 SOC_DAPM_ENUM("iir0_inp1", iir0_inp1_enum); 861 static const struct snd_kcontrol_new iir0_inp2_mux = 862 SOC_DAPM_ENUM("iir0_inp2", iir0_inp2_enum); 863 static const struct snd_kcontrol_new iir0_inp3_mux = 864 SOC_DAPM_ENUM("iir0_inp3", iir0_inp3_enum); 865 static const struct snd_kcontrol_new iir1_inp0_mux = 866 SOC_DAPM_ENUM("iir1_inp0", iir1_inp0_enum); 867 static const struct snd_kcontrol_new iir1_inp1_mux = 868 SOC_DAPM_ENUM("iir1_inp1", iir1_inp1_enum); 869 static const struct snd_kcontrol_new iir1_inp2_mux = 870 SOC_DAPM_ENUM("iir1_inp2", iir1_inp2_enum); 871 static const struct snd_kcontrol_new iir1_inp3_mux = 872 SOC_DAPM_ENUM("iir1_inp3", iir1_inp3_enum); 873 static const struct snd_kcontrol_new rx_int0_1_interp_mux = 874 SOC_DAPM_ENUM("rx_int0_1_interp", rx_int0_1_interp_enum); 875 static const struct snd_kcontrol_new rx_int1_1_interp_mux = 876 SOC_DAPM_ENUM("rx_int1_1_interp", rx_int1_1_interp_enum); 877 static const struct snd_kcontrol_new rx_int2_1_interp_mux = 878 SOC_DAPM_ENUM("rx_int2_1_interp", rx_int2_1_interp_enum); 879 static const struct snd_kcontrol_new rx_int0_2_interp_mux = 880 SOC_DAPM_ENUM("rx_int0_2_interp", rx_int0_2_interp_enum); 881 static const struct snd_kcontrol_new rx_int1_2_interp_mux = 882 SOC_DAPM_ENUM("rx_int1_2_interp", rx_int1_2_interp_enum); 883 static const struct snd_kcontrol_new rx_int2_2_interp_mux = 884 SOC_DAPM_ENUM("rx_int2_2_interp", rx_int2_2_interp_enum); 885 static const struct snd_kcontrol_new rx_mix_tx0_mux = 886 SOC_DAPM_ENUM("RX MIX TX0_MUX Mux", rx_mix_tx0_mux_enum); 887 888 static const struct reg_default rx_defaults[] = { 889 /* RX Macro */ 890 { CDC_RX_TOP_TOP_CFG0, 0x00 }, 891 { CDC_RX_TOP_SWR_CTRL, 0x00 }, 892 { CDC_RX_TOP_DEBUG, 0x00 }, 893 { CDC_RX_TOP_DEBUG_BUS, 0x00 }, 894 { CDC_RX_TOP_DEBUG_EN0, 0x00 }, 895 { CDC_RX_TOP_DEBUG_EN1, 0x00 }, 896 { CDC_RX_TOP_DEBUG_EN2, 0x00 }, 897 { CDC_RX_TOP_HPHL_COMP_WR_LSB, 0x00 }, 898 { CDC_RX_TOP_HPHL_COMP_WR_MSB, 0x00 }, 899 { CDC_RX_TOP_HPHL_COMP_LUT, 0x00 }, 900 { CDC_RX_TOP_HPHL_COMP_RD_LSB, 0x00 }, 901 { CDC_RX_TOP_HPHL_COMP_RD_MSB, 0x00 }, 902 { CDC_RX_TOP_HPHR_COMP_WR_LSB, 0x00 }, 903 { CDC_RX_TOP_HPHR_COMP_WR_MSB, 0x00 }, 904 { CDC_RX_TOP_HPHR_COMP_LUT, 0x00 }, 905 { CDC_RX_TOP_HPHR_COMP_RD_LSB, 0x00 }, 906 { CDC_RX_TOP_HPHR_COMP_RD_MSB, 0x00 }, 907 { CDC_RX_TOP_DSD0_DEBUG_CFG0, 0x11 }, 908 { CDC_RX_TOP_DSD0_DEBUG_CFG1, 0x20 }, 909 { CDC_RX_TOP_DSD0_DEBUG_CFG2, 0x00 }, 910 { CDC_RX_TOP_DSD0_DEBUG_CFG3, 0x00 }, 911 { CDC_RX_TOP_DSD1_DEBUG_CFG0, 0x11 }, 912 { CDC_RX_TOP_DSD1_DEBUG_CFG1, 0x20 }, 913 { CDC_RX_TOP_DSD1_DEBUG_CFG2, 0x00 }, 914 { CDC_RX_TOP_DSD1_DEBUG_CFG3, 0x00 }, 915 { CDC_RX_TOP_RX_I2S_CTL, 0x0C }, 916 { CDC_RX_TOP_TX_I2S2_CTL, 0x0C }, 917 { CDC_RX_TOP_I2S_CLK, 0x0C }, 918 { CDC_RX_TOP_I2S_RESET, 0x00 }, 919 { CDC_RX_TOP_I2S_MUX, 0x00 }, 920 { CDC_RX_CLK_RST_CTRL_MCLK_CONTROL, 0x00 }, 921 { CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00 }, 922 { CDC_RX_CLK_RST_CTRL_SWR_CONTROL, 0x00 }, 923 { CDC_RX_CLK_RST_CTRL_DSD_CONTROL, 0x00 }, 924 { CDC_RX_CLK_RST_CTRL_ASRC_SHARE_CONTROL, 0x08 }, 925 { CDC_RX_SOFTCLIP_CRC, 0x00 }, 926 { CDC_RX_SOFTCLIP_SOFTCLIP_CTRL, 0x38 }, 927 { CDC_RX_INP_MUX_RX_INT0_CFG0, 0x00 }, 928 { CDC_RX_INP_MUX_RX_INT0_CFG1, 0x00 }, 929 { CDC_RX_INP_MUX_RX_INT1_CFG0, 0x00 }, 930 { CDC_RX_INP_MUX_RX_INT1_CFG1, 0x00 }, 931 { CDC_RX_INP_MUX_RX_INT2_CFG0, 0x00 }, 932 { CDC_RX_INP_MUX_RX_INT2_CFG1, 0x00 }, 933 { CDC_RX_INP_MUX_RX_MIX_CFG4, 0x00 }, 934 { CDC_RX_INP_MUX_RX_MIX_CFG5, 0x00 }, 935 { CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 0x00 }, 936 { CDC_RX_CLSH_CRC, 0x00 }, 937 { CDC_RX_CLSH_DLY_CTRL, 0x03 }, 938 { CDC_RX_CLSH_DECAY_CTRL, 0x02 }, 939 { CDC_RX_CLSH_HPH_V_PA, 0x1C }, 940 { CDC_RX_CLSH_EAR_V_PA, 0x39 }, 941 { CDC_RX_CLSH_HPH_V_HD, 0x0C }, 942 { CDC_RX_CLSH_EAR_V_HD, 0x0C }, 943 { CDC_RX_CLSH_K1_MSB, 0x01 }, 944 { CDC_RX_CLSH_K1_LSB, 0x00 }, 945 { CDC_RX_CLSH_K2_MSB, 0x00 }, 946 { CDC_RX_CLSH_K2_LSB, 0x80 }, 947 { CDC_RX_CLSH_IDLE_CTRL, 0x00 }, 948 { CDC_RX_CLSH_IDLE_HPH, 0x00 }, 949 { CDC_RX_CLSH_IDLE_EAR, 0x00 }, 950 { CDC_RX_CLSH_TEST0, 0x07 }, 951 { CDC_RX_CLSH_TEST1, 0x00 }, 952 { CDC_RX_CLSH_OVR_VREF, 0x00 }, 953 { CDC_RX_CLSH_CLSG_CTL, 0x02 }, 954 { CDC_RX_CLSH_CLSG_CFG1, 0x9A }, 955 { CDC_RX_CLSH_CLSG_CFG2, 0x10 }, 956 { CDC_RX_BCL_VBAT_PATH_CTL, 0x00 }, 957 { CDC_RX_BCL_VBAT_CFG, 0x10 }, 958 { CDC_RX_BCL_VBAT_ADC_CAL1, 0x00 }, 959 { CDC_RX_BCL_VBAT_ADC_CAL2, 0x00 }, 960 { CDC_RX_BCL_VBAT_ADC_CAL3, 0x04 }, 961 { CDC_RX_BCL_VBAT_PK_EST1, 0xE0 }, 962 { CDC_RX_BCL_VBAT_PK_EST2, 0x01 }, 963 { CDC_RX_BCL_VBAT_PK_EST3, 0x40 }, 964 { CDC_RX_BCL_VBAT_RF_PROC1, 0x2A }, 965 { CDC_RX_BCL_VBAT_RF_PROC2, 0x00 }, 966 { CDC_RX_BCL_VBAT_TAC1, 0x00 }, 967 { CDC_RX_BCL_VBAT_TAC2, 0x18 }, 968 { CDC_RX_BCL_VBAT_TAC3, 0x18 }, 969 { CDC_RX_BCL_VBAT_TAC4, 0x03 }, 970 { CDC_RX_BCL_VBAT_GAIN_UPD1, 0x01 }, 971 { CDC_RX_BCL_VBAT_GAIN_UPD2, 0x00 }, 972 { CDC_RX_BCL_VBAT_GAIN_UPD3, 0x00 }, 973 { CDC_RX_BCL_VBAT_GAIN_UPD4, 0x64 }, 974 { CDC_RX_BCL_VBAT_GAIN_UPD5, 0x01 }, 975 { CDC_RX_BCL_VBAT_DEBUG1, 0x00 }, 976 { CDC_RX_BCL_VBAT_GAIN_UPD_MON, 0x00 }, 977 { CDC_RX_BCL_VBAT_GAIN_MON_VAL, 0x00 }, 978 { CDC_RX_BCL_VBAT_BAN, 0x0C }, 979 { CDC_RX_BCL_VBAT_BCL_GAIN_UPD1, 0x00 }, 980 { CDC_RX_BCL_VBAT_BCL_GAIN_UPD2, 0x77 }, 981 { CDC_RX_BCL_VBAT_BCL_GAIN_UPD3, 0x01 }, 982 { CDC_RX_BCL_VBAT_BCL_GAIN_UPD4, 0x00 }, 983 { CDC_RX_BCL_VBAT_BCL_GAIN_UPD5, 0x4B }, 984 { CDC_RX_BCL_VBAT_BCL_GAIN_UPD6, 0x00 }, 985 { CDC_RX_BCL_VBAT_BCL_GAIN_UPD7, 0x01 }, 986 { CDC_RX_BCL_VBAT_BCL_GAIN_UPD8, 0x00 }, 987 { CDC_RX_BCL_VBAT_BCL_GAIN_UPD9, 0x00 }, 988 { CDC_RX_BCL_VBAT_ATTN1, 0x04 }, 989 { CDC_RX_BCL_VBAT_ATTN2, 0x08 }, 990 { CDC_RX_BCL_VBAT_ATTN3, 0x0C }, 991 { CDC_RX_BCL_VBAT_DECODE_CTL1, 0xE0 }, 992 { CDC_RX_BCL_VBAT_DECODE_CTL2, 0x00 }, 993 { CDC_RX_BCL_VBAT_DECODE_CFG1, 0x00 }, 994 { CDC_RX_BCL_VBAT_DECODE_CFG2, 0x00 }, 995 { CDC_RX_BCL_VBAT_DECODE_CFG3, 0x00 }, 996 { CDC_RX_BCL_VBAT_DECODE_CFG4, 0x00 }, 997 { CDC_RX_BCL_VBAT_DECODE_ST, 0x00 }, 998 { CDC_RX_INTR_CTRL_CFG, 0x00 }, 999 { CDC_RX_INTR_CTRL_CLR_COMMIT, 0x00 }, 1000 { CDC_RX_INTR_CTRL_PIN1_MASK0, 0xFF }, 1001 { CDC_RX_INTR_CTRL_PIN1_STATUS0, 0x00 }, 1002 { CDC_RX_INTR_CTRL_PIN1_CLEAR0, 0x00 }, 1003 { CDC_RX_INTR_CTRL_PIN2_MASK0, 0xFF }, 1004 { CDC_RX_INTR_CTRL_PIN2_STATUS0, 0x00 }, 1005 { CDC_RX_INTR_CTRL_PIN2_CLEAR0, 0x00 }, 1006 { CDC_RX_INTR_CTRL_LEVEL0, 0x00 }, 1007 { CDC_RX_INTR_CTRL_BYPASS0, 0x00 }, 1008 { CDC_RX_INTR_CTRL_SET0, 0x00 }, 1009 { CDC_RX_RX0_RX_PATH_CTL, 0x04 }, 1010 { CDC_RX_RX0_RX_PATH_CFG0, 0x00 }, 1011 { CDC_RX_RX0_RX_PATH_CFG1, 0x64 }, 1012 { CDC_RX_RX0_RX_PATH_CFG2, 0x8F }, 1013 { CDC_RX_RX0_RX_PATH_CFG3, 0x00 }, 1014 { CDC_RX_RX0_RX_VOL_CTL, 0x00 }, 1015 { CDC_RX_RX0_RX_PATH_MIX_CTL, 0x04 }, 1016 { CDC_RX_RX0_RX_PATH_MIX_CFG, 0x7E }, 1017 { CDC_RX_RX0_RX_VOL_MIX_CTL, 0x00 }, 1018 { CDC_RX_RX0_RX_PATH_SEC1, 0x08 }, 1019 { CDC_RX_RX0_RX_PATH_SEC2, 0x00 }, 1020 { CDC_RX_RX0_RX_PATH_SEC3, 0x00 }, 1021 { CDC_RX_RX0_RX_PATH_SEC4, 0x00 }, 1022 { CDC_RX_RX0_RX_PATH_SEC7, 0x00 }, 1023 { CDC_RX_RX0_RX_PATH_MIX_SEC0, 0x08 }, 1024 { CDC_RX_RX0_RX_PATH_MIX_SEC1, 0x00 }, 1025 { CDC_RX_RX0_RX_PATH_DSM_CTL, 0x08 }, 1026 { CDC_RX_RX0_RX_PATH_DSM_DATA1, 0x00 }, 1027 { CDC_RX_RX0_RX_PATH_DSM_DATA2, 0x00 }, 1028 { CDC_RX_RX0_RX_PATH_DSM_DATA3, 0x00 }, 1029 { CDC_RX_RX0_RX_PATH_DSM_DATA4, 0x55 }, 1030 { CDC_RX_RX0_RX_PATH_DSM_DATA5, 0x55 }, 1031 { CDC_RX_RX0_RX_PATH_DSM_DATA6, 0x55 }, 1032 { CDC_RX_IDLE_DETECT_PATH_CTL, 0x00 }, 1033 { CDC_RX_IDLE_DETECT_CFG0, 0x07 }, 1034 { CDC_RX_IDLE_DETECT_CFG1, 0x3C }, 1035 { CDC_RX_IDLE_DETECT_CFG2, 0x00 }, 1036 { CDC_RX_IDLE_DETECT_CFG3, 0x00 }, 1037 { CDC_RX_COMPANDER0_CTL0, 0x60 }, 1038 { CDC_RX_COMPANDER0_CTL1, 0xDB }, 1039 { CDC_RX_COMPANDER0_CTL2, 0xFF }, 1040 { CDC_RX_COMPANDER0_CTL3, 0x35 }, 1041 { CDC_RX_COMPANDER0_CTL4, 0xFF }, 1042 { CDC_RX_COMPANDER0_CTL5, 0x00 }, 1043 { CDC_RX_COMPANDER0_CTL6, 0x01 }, 1044 { CDC_RX_COMPANDER0_CTL7, 0x28 }, 1045 { CDC_RX_COMPANDER1_CTL0, 0x60 }, 1046 { CDC_RX_COMPANDER1_CTL1, 0xDB }, 1047 { CDC_RX_COMPANDER1_CTL2, 0xFF }, 1048 { CDC_RX_COMPANDER1_CTL3, 0x35 }, 1049 { CDC_RX_COMPANDER1_CTL4, 0xFF }, 1050 { CDC_RX_COMPANDER1_CTL5, 0x00 }, 1051 { CDC_RX_COMPANDER1_CTL6, 0x01 }, 1052 { CDC_RX_COMPANDER1_CTL7, 0x28 }, 1053 { CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL, 0x00 }, 1054 { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL, 0x00 }, 1055 { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL, 0x00 }, 1056 { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL, 0x00 }, 1057 { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL, 0x00 }, 1058 { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B5_CTL, 0x00 }, 1059 { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B6_CTL, 0x00 }, 1060 { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B7_CTL, 0x00 }, 1061 { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B8_CTL, 0x00 }, 1062 { CDC_RX_SIDETONE_IIR0_IIR_CTL, 0x40 }, 1063 { CDC_RX_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL, 0x00 }, 1064 { CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL, 0x00 }, 1065 { CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL, 0x00 }, 1066 { CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL, 0x00 }, 1067 { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL, 0x00 }, 1068 { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL, 0x00 }, 1069 { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL, 0x00 }, 1070 { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL, 0x00 }, 1071 { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B5_CTL, 0x00 }, 1072 { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B6_CTL, 0x00 }, 1073 { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B7_CTL, 0x00 }, 1074 { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B8_CTL, 0x00 }, 1075 { CDC_RX_SIDETONE_IIR1_IIR_CTL, 0x40 }, 1076 { CDC_RX_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL, 0x00 }, 1077 { CDC_RX_SIDETONE_IIR1_IIR_COEF_B1_CTL, 0x00 }, 1078 { CDC_RX_SIDETONE_IIR1_IIR_COEF_B2_CTL, 0x00 }, 1079 { CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0, 0x00 }, 1080 { CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1, 0x00 }, 1081 { CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2, 0x00 }, 1082 { CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3, 0x00 }, 1083 { CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0, 0x00 }, 1084 { CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1, 0x00 }, 1085 { CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2, 0x00 }, 1086 { CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3, 0x00 }, 1087 { CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL, 0x04 }, 1088 { CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CFG1, 0x00 }, 1089 { CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL, 0x04 }, 1090 { CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CFG1, 0x00 }, 1091 { CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL, 0x00 }, 1092 { CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0, 0x01 }, 1093 { CDC_RX_EC_REF_HQ1_EC_REF_HQ_PATH_CTL, 0x00 }, 1094 { CDC_RX_EC_REF_HQ1_EC_REF_HQ_CFG0, 0x01 }, 1095 { CDC_RX_EC_REF_HQ2_EC_REF_HQ_PATH_CTL, 0x00 }, 1096 { CDC_RX_EC_REF_HQ2_EC_REF_HQ_CFG0, 0x01 }, 1097 { CDC_RX_EC_ASRC0_CLK_RST_CTL, 0x00 }, 1098 { CDC_RX_EC_ASRC0_CTL0, 0x00 }, 1099 { CDC_RX_EC_ASRC0_CTL1, 0x00 }, 1100 { CDC_RX_EC_ASRC0_FIFO_CTL, 0xA8 }, 1101 { CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB, 0x00 }, 1102 { CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB, 0x00 }, 1103 { CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB, 0x00 }, 1104 { CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB, 0x00 }, 1105 { CDC_RX_EC_ASRC0_STATUS_FIFO, 0x00 }, 1106 { CDC_RX_EC_ASRC1_CLK_RST_CTL, 0x00 }, 1107 { CDC_RX_EC_ASRC1_CTL0, 0x00 }, 1108 { CDC_RX_EC_ASRC1_CTL1, 0x00 }, 1109 { CDC_RX_EC_ASRC1_FIFO_CTL, 0xA8 }, 1110 { CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB, 0x00 }, 1111 { CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB, 0x00 }, 1112 { CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB, 0x00 }, 1113 { CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB, 0x00 }, 1114 { CDC_RX_EC_ASRC1_STATUS_FIFO, 0x00 }, 1115 { CDC_RX_EC_ASRC2_CLK_RST_CTL, 0x00 }, 1116 { CDC_RX_EC_ASRC2_CTL0, 0x00 }, 1117 { CDC_RX_EC_ASRC2_CTL1, 0x00 }, 1118 { CDC_RX_EC_ASRC2_FIFO_CTL, 0xA8 }, 1119 { CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB, 0x00 }, 1120 { CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB, 0x00 }, 1121 { CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB, 0x00 }, 1122 { CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB, 0x00 }, 1123 { CDC_RX_EC_ASRC2_STATUS_FIFO, 0x00 }, 1124 { CDC_RX_DSD0_PATH_CTL, 0x00 }, 1125 { CDC_RX_DSD0_CFG0, 0x00 }, 1126 { CDC_RX_DSD0_CFG1, 0x62 }, 1127 { CDC_RX_DSD0_CFG2, 0x96 }, 1128 { CDC_RX_DSD1_PATH_CTL, 0x00 }, 1129 { CDC_RX_DSD1_CFG0, 0x00 }, 1130 { CDC_RX_DSD1_CFG1, 0x62 }, 1131 { CDC_RX_DSD1_CFG2, 0x96 }, 1132 }; 1133 1134 static const struct reg_default rx_2_5_defaults[] = { 1135 { CDC_2_5_RX_RX1_RX_PATH_CTL, 0x04 }, 1136 { CDC_2_5_RX_RX1_RX_PATH_CFG0, 0x00 }, 1137 { CDC_2_5_RX_RX1_RX_PATH_CFG1, 0x64 }, 1138 { CDC_2_5_RX_RX1_RX_PATH_CFG2, 0x8F }, 1139 { CDC_2_5_RX_RX1_RX_PATH_CFG3, 0x00 }, 1140 { CDC_2_5_RX_RX1_RX_VOL_CTL, 0x00 }, 1141 { CDC_2_5_RX_RX1_RX_PATH_MIX_CTL, 0x04 }, 1142 { CDC_2_5_RX_RX1_RX_PATH_MIX_CFG, 0x7E }, 1143 { CDC_2_5_RX_RX1_RX_VOL_MIX_CTL, 0x00 }, 1144 { CDC_2_5_RX_RX1_RX_PATH_SEC1, 0x08 }, 1145 { CDC_2_5_RX_RX1_RX_PATH_SEC2, 0x00 }, 1146 { CDC_2_5_RX_RX1_RX_PATH_SEC3, 0x00 }, 1147 { CDC_2_5_RX_RX1_RX_PATH_SEC4, 0x00 }, 1148 { CDC_2_5_RX_RX1_RX_PATH_SEC7, 0x00 }, 1149 { CDC_2_5_RX_RX1_RX_PATH_MIX_SEC0, 0x08 }, 1150 { CDC_2_5_RX_RX1_RX_PATH_MIX_SEC1, 0x00 }, 1151 { CDC_2_5_RX_RX1_RX_PATH_DSM_CTL, 0x08 }, 1152 { CDC_2_5_RX_RX1_RX_PATH_DSM_DATA1, 0x00 }, 1153 { CDC_2_5_RX_RX1_RX_PATH_DSM_DATA2, 0x00 }, 1154 { CDC_2_5_RX_RX1_RX_PATH_DSM_DATA3, 0x00 }, 1155 { CDC_2_5_RX_RX1_RX_PATH_DSM_DATA4, 0x55 }, 1156 { CDC_2_5_RX_RX1_RX_PATH_DSM_DATA5, 0x55 }, 1157 { CDC_2_5_RX_RX1_RX_PATH_DSM_DATA6, 0x55 }, 1158 { CDC_2_5_RX_RX2_RX_PATH_CTL, 0x04 }, 1159 { CDC_2_5_RX_RX2_RX_PATH_CFG0, 0x00 }, 1160 { CDC_2_5_RX_RX2_RX_PATH_CFG1, 0x64 }, 1161 { CDC_2_5_RX_RX2_RX_PATH_CFG2, 0x8F }, 1162 { CDC_2_5_RX_RX2_RX_PATH_CFG3, 0x00 }, 1163 { CDC_2_5_RX_RX2_RX_VOL_CTL, 0x00 }, 1164 { CDC_2_5_RX_RX2_RX_PATH_MIX_CTL, 0x04 }, 1165 { CDC_2_5_RX_RX2_RX_PATH_MIX_CFG, 0x7E }, 1166 { CDC_2_5_RX_RX2_RX_VOL_MIX_CTL, 0x00 }, 1167 { CDC_2_5_RX_RX2_RX_PATH_SEC0, 0x04 }, 1168 { CDC_2_5_RX_RX2_RX_PATH_SEC1, 0x08 }, 1169 { CDC_2_5_RX_RX2_RX_PATH_SEC2, 0x00 }, 1170 { CDC_2_5_RX_RX2_RX_PATH_SEC3, 0x00 }, 1171 { CDC_2_5_RX_RX2_RX_PATH_SEC4, 0x00 }, 1172 { CDC_2_5_RX_RX2_RX_PATH_SEC5, 0x00 }, 1173 { CDC_2_5_RX_RX2_RX_PATH_SEC6, 0x00 }, 1174 { CDC_2_5_RX_RX2_RX_PATH_SEC7, 0x00 }, 1175 { CDC_2_5_RX_RX2_RX_PATH_MIX_SEC0, 0x08 }, 1176 { CDC_2_5_RX_RX2_RX_PATH_MIX_SEC1, 0x00 }, 1177 { CDC_2_5_RX_RX2_RX_PATH_DSM_CTL, 0x00 }, 1178 }; 1179 1180 static const struct reg_default rx_pre_2_5_defaults[] = { 1181 { CDC_RX_RX1_RX_PATH_CTL, 0x04 }, 1182 { CDC_RX_RX1_RX_PATH_CFG0, 0x00 }, 1183 { CDC_RX_RX1_RX_PATH_CFG1, 0x64 }, 1184 { CDC_RX_RX1_RX_PATH_CFG2, 0x8F }, 1185 { CDC_RX_RX1_RX_PATH_CFG3, 0x00 }, 1186 { CDC_RX_RX1_RX_VOL_CTL, 0x00 }, 1187 { CDC_RX_RX1_RX_PATH_MIX_CTL, 0x04 }, 1188 { CDC_RX_RX1_RX_PATH_MIX_CFG, 0x7E }, 1189 { CDC_RX_RX1_RX_VOL_MIX_CTL, 0x00 }, 1190 { CDC_RX_RX1_RX_PATH_SEC1, 0x08 }, 1191 { CDC_RX_RX1_RX_PATH_SEC2, 0x00 }, 1192 { CDC_RX_RX1_RX_PATH_SEC3, 0x00 }, 1193 { CDC_RX_RX1_RX_PATH_SEC4, 0x00 }, 1194 { CDC_RX_RX1_RX_PATH_SEC7, 0x00 }, 1195 { CDC_RX_RX1_RX_PATH_MIX_SEC0, 0x08 }, 1196 { CDC_RX_RX1_RX_PATH_MIX_SEC1, 0x00 }, 1197 { CDC_RX_RX1_RX_PATH_DSM_CTL, 0x08 }, 1198 { CDC_RX_RX1_RX_PATH_DSM_DATA1, 0x00 }, 1199 { CDC_RX_RX1_RX_PATH_DSM_DATA2, 0x00 }, 1200 { CDC_RX_RX1_RX_PATH_DSM_DATA3, 0x00 }, 1201 { CDC_RX_RX1_RX_PATH_DSM_DATA4, 0x55 }, 1202 { CDC_RX_RX1_RX_PATH_DSM_DATA5, 0x55 }, 1203 { CDC_RX_RX1_RX_PATH_DSM_DATA6, 0x55 }, 1204 { CDC_RX_RX2_RX_PATH_CTL, 0x04 }, 1205 { CDC_RX_RX2_RX_PATH_CFG0, 0x00 }, 1206 { CDC_RX_RX2_RX_PATH_CFG1, 0x64 }, 1207 { CDC_RX_RX2_RX_PATH_CFG2, 0x8F }, 1208 { CDC_RX_RX2_RX_PATH_CFG3, 0x00 }, 1209 { CDC_RX_RX2_RX_VOL_CTL, 0x00 }, 1210 { CDC_RX_RX2_RX_PATH_MIX_CTL, 0x04 }, 1211 { CDC_RX_RX2_RX_PATH_MIX_CFG, 0x7E }, 1212 { CDC_RX_RX2_RX_VOL_MIX_CTL, 0x00 }, 1213 { CDC_RX_RX2_RX_PATH_SEC0, 0x04 }, 1214 { CDC_RX_RX2_RX_PATH_SEC1, 0x08 }, 1215 { CDC_RX_RX2_RX_PATH_SEC2, 0x00 }, 1216 { CDC_RX_RX2_RX_PATH_SEC3, 0x00 }, 1217 { CDC_RX_RX2_RX_PATH_SEC4, 0x00 }, 1218 { CDC_RX_RX2_RX_PATH_SEC5, 0x00 }, 1219 { CDC_RX_RX2_RX_PATH_SEC6, 0x00 }, 1220 { CDC_RX_RX2_RX_PATH_SEC7, 0x00 }, 1221 { CDC_RX_RX2_RX_PATH_MIX_SEC0, 0x08 }, 1222 { CDC_RX_RX2_RX_PATH_MIX_SEC1, 0x00 }, 1223 { CDC_RX_RX2_RX_PATH_DSM_CTL, 0x00 }, 1224 1225 }; 1226 1227 static bool rx_is_wronly_register(struct device *dev, 1228 unsigned int reg) 1229 { 1230 switch (reg) { 1231 case CDC_RX_BCL_VBAT_GAIN_UPD_MON: 1232 case CDC_RX_INTR_CTRL_CLR_COMMIT: 1233 case CDC_RX_INTR_CTRL_PIN1_CLEAR0: 1234 case CDC_RX_INTR_CTRL_PIN2_CLEAR0: 1235 return true; 1236 } 1237 1238 return false; 1239 } 1240 1241 static bool rx_is_volatile_register(struct device *dev, unsigned int reg) 1242 { 1243 /* Update volatile list for rx/tx macros */ 1244 switch (reg) { 1245 case CDC_RX_TOP_HPHL_COMP_RD_LSB: 1246 case CDC_RX_TOP_HPHL_COMP_WR_LSB: 1247 case CDC_RX_TOP_HPHL_COMP_RD_MSB: 1248 case CDC_RX_TOP_HPHL_COMP_WR_MSB: 1249 case CDC_RX_TOP_HPHR_COMP_RD_LSB: 1250 case CDC_RX_TOP_HPHR_COMP_WR_LSB: 1251 case CDC_RX_TOP_HPHR_COMP_RD_MSB: 1252 case CDC_RX_TOP_HPHR_COMP_WR_MSB: 1253 case CDC_RX_TOP_DSD0_DEBUG_CFG2: 1254 case CDC_RX_TOP_DSD1_DEBUG_CFG2: 1255 case CDC_RX_BCL_VBAT_GAIN_MON_VAL: 1256 case CDC_RX_BCL_VBAT_DECODE_ST: 1257 case CDC_RX_INTR_CTRL_PIN1_STATUS0: 1258 case CDC_RX_INTR_CTRL_PIN2_STATUS0: 1259 case CDC_RX_COMPANDER0_CTL6: 1260 case CDC_RX_COMPANDER1_CTL6: 1261 case CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB: 1262 case CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB: 1263 case CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB: 1264 case CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB: 1265 case CDC_RX_EC_ASRC0_STATUS_FIFO: 1266 case CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB: 1267 case CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB: 1268 case CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB: 1269 case CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB: 1270 case CDC_RX_EC_ASRC1_STATUS_FIFO: 1271 case CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB: 1272 case CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB: 1273 case CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB: 1274 case CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB: 1275 case CDC_RX_EC_ASRC2_STATUS_FIFO: 1276 return true; 1277 } 1278 return false; 1279 } 1280 1281 static bool rx_pre_2_5_is_rw_register(struct device *dev, unsigned int reg) 1282 { 1283 switch (reg) { 1284 case CDC_RX_RX1_RX_PATH_CTL: 1285 case CDC_RX_RX1_RX_PATH_CFG0: 1286 case CDC_RX_RX1_RX_PATH_CFG1: 1287 case CDC_RX_RX1_RX_PATH_CFG2: 1288 case CDC_RX_RX1_RX_PATH_CFG3: 1289 case CDC_RX_RX1_RX_VOL_CTL: 1290 case CDC_RX_RX1_RX_PATH_MIX_CTL: 1291 case CDC_RX_RX1_RX_PATH_MIX_CFG: 1292 case CDC_RX_RX1_RX_VOL_MIX_CTL: 1293 case CDC_RX_RX1_RX_PATH_SEC1: 1294 case CDC_RX_RX1_RX_PATH_SEC2: 1295 case CDC_RX_RX1_RX_PATH_SEC3: 1296 case CDC_RX_RX1_RX_PATH_SEC4: 1297 case CDC_RX_RX1_RX_PATH_SEC7: 1298 case CDC_RX_RX1_RX_PATH_MIX_SEC0: 1299 case CDC_RX_RX1_RX_PATH_MIX_SEC1: 1300 case CDC_RX_RX1_RX_PATH_DSM_CTL: 1301 case CDC_RX_RX1_RX_PATH_DSM_DATA1: 1302 case CDC_RX_RX1_RX_PATH_DSM_DATA2: 1303 case CDC_RX_RX1_RX_PATH_DSM_DATA3: 1304 case CDC_RX_RX1_RX_PATH_DSM_DATA4: 1305 case CDC_RX_RX1_RX_PATH_DSM_DATA5: 1306 case CDC_RX_RX1_RX_PATH_DSM_DATA6: 1307 case CDC_RX_RX2_RX_PATH_CTL: 1308 case CDC_RX_RX2_RX_PATH_CFG0: 1309 case CDC_RX_RX2_RX_PATH_CFG1: 1310 case CDC_RX_RX2_RX_PATH_CFG2: 1311 case CDC_RX_RX2_RX_PATH_CFG3: 1312 case CDC_RX_RX2_RX_VOL_CTL: 1313 case CDC_RX_RX2_RX_PATH_MIX_CTL: 1314 case CDC_RX_RX2_RX_PATH_MIX_CFG: 1315 case CDC_RX_RX2_RX_VOL_MIX_CTL: 1316 case CDC_RX_RX2_RX_PATH_SEC0: 1317 case CDC_RX_RX2_RX_PATH_SEC1: 1318 case CDC_RX_RX2_RX_PATH_SEC2: 1319 case CDC_RX_RX2_RX_PATH_SEC3: 1320 case CDC_RX_RX2_RX_PATH_SEC4: 1321 case CDC_RX_RX2_RX_PATH_SEC5: 1322 case CDC_RX_RX2_RX_PATH_SEC6: 1323 case CDC_RX_RX2_RX_PATH_SEC7: 1324 case CDC_RX_RX2_RX_PATH_MIX_SEC0: 1325 case CDC_RX_RX2_RX_PATH_MIX_SEC1: 1326 case CDC_RX_RX2_RX_PATH_DSM_CTL: 1327 return true; 1328 } 1329 1330 return false; 1331 } 1332 1333 static bool rx_2_5_is_rw_register(struct device *dev, unsigned int reg) 1334 { 1335 switch (reg) { 1336 case CDC_2_5_RX_RX1_RX_PATH_CTL: 1337 case CDC_2_5_RX_RX1_RX_PATH_CFG0: 1338 case CDC_2_5_RX_RX1_RX_PATH_CFG1: 1339 case CDC_2_5_RX_RX1_RX_PATH_CFG2: 1340 case CDC_2_5_RX_RX1_RX_PATH_CFG3: 1341 case CDC_2_5_RX_RX1_RX_VOL_CTL: 1342 case CDC_2_5_RX_RX1_RX_PATH_MIX_CTL: 1343 case CDC_2_5_RX_RX1_RX_PATH_MIX_CFG: 1344 case CDC_2_5_RX_RX1_RX_VOL_MIX_CTL: 1345 case CDC_2_5_RX_RX1_RX_PATH_SEC1: 1346 case CDC_2_5_RX_RX1_RX_PATH_SEC2: 1347 case CDC_2_5_RX_RX1_RX_PATH_SEC3: 1348 case CDC_2_5_RX_RX1_RX_PATH_SEC4: 1349 case CDC_2_5_RX_RX1_RX_PATH_SEC7: 1350 case CDC_2_5_RX_RX1_RX_PATH_MIX_SEC0: 1351 case CDC_2_5_RX_RX1_RX_PATH_MIX_SEC1: 1352 case CDC_2_5_RX_RX1_RX_PATH_DSM_CTL: 1353 case CDC_2_5_RX_RX1_RX_PATH_DSM_DATA1: 1354 case CDC_2_5_RX_RX1_RX_PATH_DSM_DATA2: 1355 case CDC_2_5_RX_RX1_RX_PATH_DSM_DATA3: 1356 case CDC_2_5_RX_RX1_RX_PATH_DSM_DATA4: 1357 case CDC_2_5_RX_RX1_RX_PATH_DSM_DATA5: 1358 case CDC_2_5_RX_RX1_RX_PATH_DSM_DATA6: 1359 case CDC_2_5_RX_RX2_RX_PATH_CTL: 1360 case CDC_2_5_RX_RX2_RX_PATH_CFG0: 1361 case CDC_2_5_RX_RX2_RX_PATH_CFG1: 1362 case CDC_2_5_RX_RX2_RX_PATH_CFG2: 1363 case CDC_2_5_RX_RX2_RX_PATH_CFG3: 1364 case CDC_2_5_RX_RX2_RX_VOL_CTL: 1365 case CDC_2_5_RX_RX2_RX_PATH_MIX_CTL: 1366 case CDC_2_5_RX_RX2_RX_PATH_MIX_CFG: 1367 case CDC_2_5_RX_RX2_RX_VOL_MIX_CTL: 1368 case CDC_2_5_RX_RX2_RX_PATH_SEC0: 1369 case CDC_2_5_RX_RX2_RX_PATH_SEC1: 1370 case CDC_2_5_RX_RX2_RX_PATH_SEC2: 1371 case CDC_2_5_RX_RX2_RX_PATH_SEC3: 1372 case CDC_2_5_RX_RX2_RX_PATH_SEC4: 1373 case CDC_2_5_RX_RX2_RX_PATH_SEC5: 1374 case CDC_2_5_RX_RX2_RX_PATH_SEC6: 1375 case CDC_2_5_RX_RX2_RX_PATH_SEC7: 1376 case CDC_2_5_RX_RX2_RX_PATH_MIX_SEC0: 1377 case CDC_2_5_RX_RX2_RX_PATH_MIX_SEC1: 1378 case CDC_2_5_RX_RX2_RX_PATH_DSM_CTL: 1379 return true; 1380 } 1381 1382 return false; 1383 } 1384 1385 static bool rx_is_rw_register(struct device *dev, unsigned int reg) 1386 { 1387 struct rx_macro *rx = dev_get_drvdata(dev); 1388 1389 switch (reg) { 1390 case CDC_RX_TOP_TOP_CFG0: 1391 case CDC_RX_TOP_SWR_CTRL: 1392 case CDC_RX_TOP_DEBUG: 1393 case CDC_RX_TOP_DEBUG_BUS: 1394 case CDC_RX_TOP_DEBUG_EN0: 1395 case CDC_RX_TOP_DEBUG_EN1: 1396 case CDC_RX_TOP_DEBUG_EN2: 1397 case CDC_RX_TOP_HPHL_COMP_WR_LSB: 1398 case CDC_RX_TOP_HPHL_COMP_WR_MSB: 1399 case CDC_RX_TOP_HPHL_COMP_LUT: 1400 case CDC_RX_TOP_HPHR_COMP_WR_LSB: 1401 case CDC_RX_TOP_HPHR_COMP_WR_MSB: 1402 case CDC_RX_TOP_HPHR_COMP_LUT: 1403 case CDC_RX_TOP_DSD0_DEBUG_CFG0: 1404 case CDC_RX_TOP_DSD0_DEBUG_CFG1: 1405 case CDC_RX_TOP_DSD0_DEBUG_CFG3: 1406 case CDC_RX_TOP_DSD1_DEBUG_CFG0: 1407 case CDC_RX_TOP_DSD1_DEBUG_CFG1: 1408 case CDC_RX_TOP_DSD1_DEBUG_CFG3: 1409 case CDC_RX_TOP_RX_I2S_CTL: 1410 case CDC_RX_TOP_TX_I2S2_CTL: 1411 case CDC_RX_TOP_I2S_CLK: 1412 case CDC_RX_TOP_I2S_RESET: 1413 case CDC_RX_TOP_I2S_MUX: 1414 case CDC_RX_CLK_RST_CTRL_MCLK_CONTROL: 1415 case CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL: 1416 case CDC_RX_CLK_RST_CTRL_SWR_CONTROL: 1417 case CDC_RX_CLK_RST_CTRL_DSD_CONTROL: 1418 case CDC_RX_CLK_RST_CTRL_ASRC_SHARE_CONTROL: 1419 case CDC_RX_SOFTCLIP_CRC: 1420 case CDC_RX_SOFTCLIP_SOFTCLIP_CTRL: 1421 case CDC_RX_INP_MUX_RX_INT0_CFG0: 1422 case CDC_RX_INP_MUX_RX_INT0_CFG1: 1423 case CDC_RX_INP_MUX_RX_INT1_CFG0: 1424 case CDC_RX_INP_MUX_RX_INT1_CFG1: 1425 case CDC_RX_INP_MUX_RX_INT2_CFG0: 1426 case CDC_RX_INP_MUX_RX_INT2_CFG1: 1427 case CDC_RX_INP_MUX_RX_MIX_CFG4: 1428 case CDC_RX_INP_MUX_RX_MIX_CFG5: 1429 case CDC_RX_INP_MUX_SIDETONE_SRC_CFG0: 1430 case CDC_RX_CLSH_CRC: 1431 case CDC_RX_CLSH_DLY_CTRL: 1432 case CDC_RX_CLSH_DECAY_CTRL: 1433 case CDC_RX_CLSH_HPH_V_PA: 1434 case CDC_RX_CLSH_EAR_V_PA: 1435 case CDC_RX_CLSH_HPH_V_HD: 1436 case CDC_RX_CLSH_EAR_V_HD: 1437 case CDC_RX_CLSH_K1_MSB: 1438 case CDC_RX_CLSH_K1_LSB: 1439 case CDC_RX_CLSH_K2_MSB: 1440 case CDC_RX_CLSH_K2_LSB: 1441 case CDC_RX_CLSH_IDLE_CTRL: 1442 case CDC_RX_CLSH_IDLE_HPH: 1443 case CDC_RX_CLSH_IDLE_EAR: 1444 case CDC_RX_CLSH_TEST0: 1445 case CDC_RX_CLSH_TEST1: 1446 case CDC_RX_CLSH_OVR_VREF: 1447 case CDC_RX_CLSH_CLSG_CTL: 1448 case CDC_RX_CLSH_CLSG_CFG1: 1449 case CDC_RX_CLSH_CLSG_CFG2: 1450 case CDC_RX_BCL_VBAT_PATH_CTL: 1451 case CDC_RX_BCL_VBAT_CFG: 1452 case CDC_RX_BCL_VBAT_ADC_CAL1: 1453 case CDC_RX_BCL_VBAT_ADC_CAL2: 1454 case CDC_RX_BCL_VBAT_ADC_CAL3: 1455 case CDC_RX_BCL_VBAT_PK_EST1: 1456 case CDC_RX_BCL_VBAT_PK_EST2: 1457 case CDC_RX_BCL_VBAT_PK_EST3: 1458 case CDC_RX_BCL_VBAT_RF_PROC1: 1459 case CDC_RX_BCL_VBAT_RF_PROC2: 1460 case CDC_RX_BCL_VBAT_TAC1: 1461 case CDC_RX_BCL_VBAT_TAC2: 1462 case CDC_RX_BCL_VBAT_TAC3: 1463 case CDC_RX_BCL_VBAT_TAC4: 1464 case CDC_RX_BCL_VBAT_GAIN_UPD1: 1465 case CDC_RX_BCL_VBAT_GAIN_UPD2: 1466 case CDC_RX_BCL_VBAT_GAIN_UPD3: 1467 case CDC_RX_BCL_VBAT_GAIN_UPD4: 1468 case CDC_RX_BCL_VBAT_GAIN_UPD5: 1469 case CDC_RX_BCL_VBAT_DEBUG1: 1470 case CDC_RX_BCL_VBAT_BAN: 1471 case CDC_RX_BCL_VBAT_BCL_GAIN_UPD1: 1472 case CDC_RX_BCL_VBAT_BCL_GAIN_UPD2: 1473 case CDC_RX_BCL_VBAT_BCL_GAIN_UPD3: 1474 case CDC_RX_BCL_VBAT_BCL_GAIN_UPD4: 1475 case CDC_RX_BCL_VBAT_BCL_GAIN_UPD5: 1476 case CDC_RX_BCL_VBAT_BCL_GAIN_UPD6: 1477 case CDC_RX_BCL_VBAT_BCL_GAIN_UPD7: 1478 case CDC_RX_BCL_VBAT_BCL_GAIN_UPD8: 1479 case CDC_RX_BCL_VBAT_BCL_GAIN_UPD9: 1480 case CDC_RX_BCL_VBAT_ATTN1: 1481 case CDC_RX_BCL_VBAT_ATTN2: 1482 case CDC_RX_BCL_VBAT_ATTN3: 1483 case CDC_RX_BCL_VBAT_DECODE_CTL1: 1484 case CDC_RX_BCL_VBAT_DECODE_CTL2: 1485 case CDC_RX_BCL_VBAT_DECODE_CFG1: 1486 case CDC_RX_BCL_VBAT_DECODE_CFG2: 1487 case CDC_RX_BCL_VBAT_DECODE_CFG3: 1488 case CDC_RX_BCL_VBAT_DECODE_CFG4: 1489 case CDC_RX_INTR_CTRL_CFG: 1490 case CDC_RX_INTR_CTRL_PIN1_MASK0: 1491 case CDC_RX_INTR_CTRL_PIN2_MASK0: 1492 case CDC_RX_INTR_CTRL_LEVEL0: 1493 case CDC_RX_INTR_CTRL_BYPASS0: 1494 case CDC_RX_INTR_CTRL_SET0: 1495 case CDC_RX_RX0_RX_PATH_CTL: 1496 case CDC_RX_RX0_RX_PATH_CFG0: 1497 case CDC_RX_RX0_RX_PATH_CFG1: 1498 case CDC_RX_RX0_RX_PATH_CFG2: 1499 case CDC_RX_RX0_RX_PATH_CFG3: 1500 case CDC_RX_RX0_RX_VOL_CTL: 1501 case CDC_RX_RX0_RX_PATH_MIX_CTL: 1502 case CDC_RX_RX0_RX_PATH_MIX_CFG: 1503 case CDC_RX_RX0_RX_VOL_MIX_CTL: 1504 case CDC_RX_RX0_RX_PATH_SEC1: 1505 case CDC_RX_RX0_RX_PATH_SEC2: 1506 case CDC_RX_RX0_RX_PATH_SEC3: 1507 case CDC_RX_RX0_RX_PATH_SEC4: 1508 case CDC_RX_RX0_RX_PATH_SEC7: 1509 case CDC_RX_RX0_RX_PATH_MIX_SEC0: 1510 case CDC_RX_RX0_RX_PATH_MIX_SEC1: 1511 case CDC_RX_RX0_RX_PATH_DSM_CTL: 1512 case CDC_RX_RX0_RX_PATH_DSM_DATA1: 1513 case CDC_RX_RX0_RX_PATH_DSM_DATA2: 1514 case CDC_RX_RX0_RX_PATH_DSM_DATA3: 1515 case CDC_RX_RX0_RX_PATH_DSM_DATA4: 1516 case CDC_RX_RX0_RX_PATH_DSM_DATA5: 1517 case CDC_RX_RX0_RX_PATH_DSM_DATA6: 1518 case CDC_RX_IDLE_DETECT_PATH_CTL: 1519 case CDC_RX_IDLE_DETECT_CFG0: 1520 case CDC_RX_IDLE_DETECT_CFG1: 1521 case CDC_RX_IDLE_DETECT_CFG2: 1522 case CDC_RX_IDLE_DETECT_CFG3: 1523 case CDC_RX_COMPANDER0_CTL0: 1524 case CDC_RX_COMPANDER0_CTL1: 1525 case CDC_RX_COMPANDER0_CTL2: 1526 case CDC_RX_COMPANDER0_CTL3: 1527 case CDC_RX_COMPANDER0_CTL4: 1528 case CDC_RX_COMPANDER0_CTL5: 1529 case CDC_RX_COMPANDER0_CTL7: 1530 case CDC_RX_COMPANDER1_CTL0: 1531 case CDC_RX_COMPANDER1_CTL1: 1532 case CDC_RX_COMPANDER1_CTL2: 1533 case CDC_RX_COMPANDER1_CTL3: 1534 case CDC_RX_COMPANDER1_CTL4: 1535 case CDC_RX_COMPANDER1_CTL5: 1536 case CDC_RX_COMPANDER1_CTL7: 1537 case CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL: 1538 case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL: 1539 case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL: 1540 case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL: 1541 case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL: 1542 case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B5_CTL: 1543 case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B6_CTL: 1544 case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B7_CTL: 1545 case CDC_RX_SIDETONE_IIR0_IIR_GAIN_B8_CTL: 1546 case CDC_RX_SIDETONE_IIR0_IIR_CTL: 1547 case CDC_RX_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL: 1548 case CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL: 1549 case CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL: 1550 case CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL: 1551 case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL: 1552 case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL: 1553 case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL: 1554 case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL: 1555 case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B5_CTL: 1556 case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B6_CTL: 1557 case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B7_CTL: 1558 case CDC_RX_SIDETONE_IIR1_IIR_GAIN_B8_CTL: 1559 case CDC_RX_SIDETONE_IIR1_IIR_CTL: 1560 case CDC_RX_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL: 1561 case CDC_RX_SIDETONE_IIR1_IIR_COEF_B1_CTL: 1562 case CDC_RX_SIDETONE_IIR1_IIR_COEF_B2_CTL: 1563 case CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0: 1564 case CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1: 1565 case CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2: 1566 case CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3: 1567 case CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0: 1568 case CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1: 1569 case CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2: 1570 case CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3: 1571 case CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL: 1572 case CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CFG1: 1573 case CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL: 1574 case CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CFG1: 1575 case CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL: 1576 case CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0: 1577 case CDC_RX_EC_REF_HQ1_EC_REF_HQ_PATH_CTL: 1578 case CDC_RX_EC_REF_HQ1_EC_REF_HQ_CFG0: 1579 case CDC_RX_EC_REF_HQ2_EC_REF_HQ_PATH_CTL: 1580 case CDC_RX_EC_REF_HQ2_EC_REF_HQ_CFG0: 1581 case CDC_RX_EC_ASRC0_CLK_RST_CTL: 1582 case CDC_RX_EC_ASRC0_CTL0: 1583 case CDC_RX_EC_ASRC0_CTL1: 1584 case CDC_RX_EC_ASRC0_FIFO_CTL: 1585 case CDC_RX_EC_ASRC1_CLK_RST_CTL: 1586 case CDC_RX_EC_ASRC1_CTL0: 1587 case CDC_RX_EC_ASRC1_CTL1: 1588 case CDC_RX_EC_ASRC1_FIFO_CTL: 1589 case CDC_RX_EC_ASRC2_CLK_RST_CTL: 1590 case CDC_RX_EC_ASRC2_CTL0: 1591 case CDC_RX_EC_ASRC2_CTL1: 1592 case CDC_RX_EC_ASRC2_FIFO_CTL: 1593 case CDC_RX_DSD0_PATH_CTL: 1594 case CDC_RX_DSD0_CFG0: 1595 case CDC_RX_DSD0_CFG1: 1596 case CDC_RX_DSD0_CFG2: 1597 case CDC_RX_DSD1_PATH_CTL: 1598 case CDC_RX_DSD1_CFG0: 1599 case CDC_RX_DSD1_CFG1: 1600 case CDC_RX_DSD1_CFG2: 1601 return true; 1602 } 1603 1604 switch (rx->codec_version) { 1605 case LPASS_CODEC_VERSION_1_0: 1606 case LPASS_CODEC_VERSION_1_1: 1607 case LPASS_CODEC_VERSION_1_2: 1608 case LPASS_CODEC_VERSION_2_0: 1609 case LPASS_CODEC_VERSION_2_1: 1610 return rx_pre_2_5_is_rw_register(dev, reg); 1611 case LPASS_CODEC_VERSION_2_5: 1612 case LPASS_CODEC_VERSION_2_6: 1613 case LPASS_CODEC_VERSION_2_7: 1614 case LPASS_CODEC_VERSION_2_8: 1615 return rx_2_5_is_rw_register(dev, reg); 1616 default: 1617 break; 1618 } 1619 1620 return false; 1621 } 1622 1623 static bool rx_is_writeable_register(struct device *dev, unsigned int reg) 1624 { 1625 bool ret; 1626 1627 ret = rx_is_rw_register(dev, reg); 1628 if (!ret) 1629 return rx_is_wronly_register(dev, reg); 1630 1631 return ret; 1632 } 1633 1634 static bool rx_is_readable_register(struct device *dev, unsigned int reg) 1635 { 1636 switch (reg) { 1637 case CDC_RX_TOP_HPHL_COMP_RD_LSB: 1638 case CDC_RX_TOP_HPHL_COMP_RD_MSB: 1639 case CDC_RX_TOP_HPHR_COMP_RD_LSB: 1640 case CDC_RX_TOP_HPHR_COMP_RD_MSB: 1641 case CDC_RX_TOP_DSD0_DEBUG_CFG2: 1642 case CDC_RX_TOP_DSD1_DEBUG_CFG2: 1643 case CDC_RX_BCL_VBAT_GAIN_MON_VAL: 1644 case CDC_RX_BCL_VBAT_DECODE_ST: 1645 case CDC_RX_INTR_CTRL_PIN1_STATUS0: 1646 case CDC_RX_INTR_CTRL_PIN2_STATUS0: 1647 case CDC_RX_COMPANDER0_CTL6: 1648 case CDC_RX_COMPANDER1_CTL6: 1649 case CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB: 1650 case CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB: 1651 case CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB: 1652 case CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB: 1653 case CDC_RX_EC_ASRC0_STATUS_FIFO: 1654 case CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB: 1655 case CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB: 1656 case CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB: 1657 case CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB: 1658 case CDC_RX_EC_ASRC1_STATUS_FIFO: 1659 case CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB: 1660 case CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB: 1661 case CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB: 1662 case CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB: 1663 case CDC_RX_EC_ASRC2_STATUS_FIFO: 1664 return true; 1665 } 1666 1667 return rx_is_rw_register(dev, reg); 1668 } 1669 1670 static const struct regmap_config rx_regmap_config = { 1671 .name = "rx_macro", 1672 .reg_bits = 16, 1673 .val_bits = 32, /* 8 but with 32 bit read/write */ 1674 .reg_stride = 4, 1675 .cache_type = REGCACHE_FLAT, 1676 .max_register = RX_MAX_OFFSET, 1677 .writeable_reg = rx_is_writeable_register, 1678 .volatile_reg = rx_is_volatile_register, 1679 .readable_reg = rx_is_readable_register, 1680 }; 1681 1682 static int rx_macro_int_dem_inp_mux_put(struct snd_kcontrol *kcontrol, 1683 struct snd_ctl_elem_value *ucontrol) 1684 { 1685 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol); 1686 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm); 1687 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 1688 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 1689 unsigned short look_ahead_dly_reg; 1690 unsigned int val; 1691 1692 val = ucontrol->value.enumerated.item[0]; 1693 1694 if (e->reg == CDC_RX_RXn_RX_PATH_CFG1(rx, 0)) 1695 look_ahead_dly_reg = CDC_RX_RXn_RX_PATH_CFG0(rx, 0); 1696 else if (e->reg == CDC_RX_RXn_RX_PATH_CFG1(rx, 1)) 1697 look_ahead_dly_reg = CDC_RX_RXn_RX_PATH_CFG0(rx, 1); 1698 1699 /* Set Look Ahead Delay */ 1700 if (val) 1701 snd_soc_component_update_bits(component, look_ahead_dly_reg, 1702 CDC_RX_DLY_ZN_EN_MASK, 1703 CDC_RX_DLY_ZN_ENABLE); 1704 else 1705 snd_soc_component_update_bits(component, look_ahead_dly_reg, 1706 CDC_RX_DLY_ZN_EN_MASK, 0); 1707 /* Set DEM INP Select */ 1708 return snd_soc_dapm_put_enum_double(kcontrol, ucontrol); 1709 } 1710 1711 static const struct snd_kcontrol_new rx_int0_dem_inp_mux = 1712 SOC_DAPM_ENUM_EXT("rx_int0_dem_inp", rx_int0_dem_inp_enum, 1713 snd_soc_dapm_get_enum_double, rx_macro_int_dem_inp_mux_put); 1714 static const struct snd_kcontrol_new rx_int1_dem_inp_mux = 1715 SOC_DAPM_ENUM_EXT("rx_int1_dem_inp", rx_int1_dem_inp_enum, 1716 snd_soc_dapm_get_enum_double, rx_macro_int_dem_inp_mux_put); 1717 1718 static const struct snd_kcontrol_new rx_2_5_int1_dem_inp_mux = 1719 SOC_DAPM_ENUM_EXT("rx_int1_dem_inp", rx_2_5_int1_dem_inp_enum, 1720 snd_soc_dapm_get_enum_double, rx_macro_int_dem_inp_mux_put); 1721 1722 static int rx_macro_set_prim_interpolator_rate(struct snd_soc_dai *dai, 1723 int rate_reg_val, u32 sample_rate) 1724 { 1725 1726 u8 int_1_mix1_inp; 1727 u32 j, port; 1728 u16 int_mux_cfg0, int_mux_cfg1; 1729 u16 int_fs_reg; 1730 u8 inp0_sel, inp1_sel, inp2_sel; 1731 struct snd_soc_component *component = dai->component; 1732 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 1733 1734 for_each_set_bit(port, &rx->active_ch_mask[dai->id], RX_MACRO_PORTS_MAX) { 1735 int_1_mix1_inp = port; 1736 int_mux_cfg0 = CDC_RX_INP_MUX_RX_INT0_CFG0; 1737 /* 1738 * Loop through all interpolator MUX inputs and find out 1739 * to which interpolator input, the rx port 1740 * is connected 1741 */ 1742 for (j = 0; j < INTERP_MAX; j++) { 1743 int_mux_cfg1 = int_mux_cfg0 + 4; 1744 1745 inp0_sel = snd_soc_component_read_field(component, int_mux_cfg0, 1746 CDC_RX_INTX_1_MIX_INP0_SEL_MASK); 1747 inp1_sel = snd_soc_component_read_field(component, int_mux_cfg0, 1748 CDC_RX_INTX_1_MIX_INP1_SEL_MASK); 1749 inp2_sel = snd_soc_component_read_field(component, int_mux_cfg1, 1750 CDC_RX_INTX_1_MIX_INP2_SEL_MASK); 1751 1752 if ((inp0_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0) || 1753 (inp1_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0) || 1754 (inp2_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0)) { 1755 int_fs_reg = CDC_RX_RXn_RX_PATH_CTL(rx, j); 1756 /* sample_rate is in Hz */ 1757 snd_soc_component_update_bits(component, int_fs_reg, 1758 CDC_RX_PATH_PCM_RATE_MASK, 1759 rate_reg_val); 1760 } 1761 int_mux_cfg0 += 8; 1762 } 1763 } 1764 1765 return 0; 1766 } 1767 1768 static int rx_macro_set_mix_interpolator_rate(struct snd_soc_dai *dai, 1769 int rate_reg_val, u32 sample_rate) 1770 { 1771 1772 u8 int_2_inp; 1773 u32 j, port; 1774 u16 int_mux_cfg1, int_fs_reg; 1775 u8 int_mux_cfg1_val; 1776 struct snd_soc_component *component = dai->component; 1777 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 1778 1779 for_each_set_bit(port, &rx->active_ch_mask[dai->id], RX_MACRO_PORTS_MAX) { 1780 int_2_inp = port; 1781 1782 int_mux_cfg1 = CDC_RX_INP_MUX_RX_INT0_CFG1; 1783 for (j = 0; j < INTERP_MAX; j++) { 1784 int_mux_cfg1_val = snd_soc_component_read_field(component, int_mux_cfg1, 1785 CDC_RX_INTX_2_SEL_MASK); 1786 1787 if (int_mux_cfg1_val == int_2_inp + INTn_2_INP_SEL_RX0) { 1788 int_fs_reg = CDC_RX_RXn_RX_PATH_MIX_CTL(rx, j); 1789 snd_soc_component_update_bits(component, int_fs_reg, 1790 CDC_RX_RXn_MIX_PCM_RATE_MASK, 1791 rate_reg_val); 1792 } 1793 int_mux_cfg1 += 8; 1794 } 1795 } 1796 return 0; 1797 } 1798 1799 static int rx_macro_set_interpolator_rate(struct snd_soc_dai *dai, 1800 u32 sample_rate) 1801 { 1802 int rate_val = 0; 1803 int i, ret; 1804 1805 for (i = 0; i < ARRAY_SIZE(sr_val_tbl); i++) 1806 if (sample_rate == sr_val_tbl[i].sample_rate) 1807 rate_val = sr_val_tbl[i].rate_val; 1808 1809 ret = rx_macro_set_prim_interpolator_rate(dai, rate_val, sample_rate); 1810 if (ret) 1811 return ret; 1812 1813 ret = rx_macro_set_mix_interpolator_rate(dai, rate_val, sample_rate); 1814 1815 return ret; 1816 } 1817 1818 static int rx_macro_hw_params(struct snd_pcm_substream *substream, 1819 struct snd_pcm_hw_params *params, 1820 struct snd_soc_dai *dai) 1821 { 1822 struct snd_soc_component *component = dai->component; 1823 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 1824 int ret; 1825 1826 switch (substream->stream) { 1827 case SNDRV_PCM_STREAM_PLAYBACK: 1828 ret = rx_macro_set_interpolator_rate(dai, params_rate(params)); 1829 if (ret) { 1830 dev_err(component->dev, "%s: cannot set sample rate: %u\n", 1831 __func__, params_rate(params)); 1832 return ret; 1833 } 1834 rx->bit_width[dai->id] = params_width(params); 1835 break; 1836 default: 1837 break; 1838 } 1839 return 0; 1840 } 1841 1842 static int rx_macro_get_channel_map(const struct snd_soc_dai *dai, 1843 unsigned int *tx_num, unsigned int *tx_slot, 1844 unsigned int *rx_num, unsigned int *rx_slot) 1845 { 1846 struct snd_soc_component *component = dai->component; 1847 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 1848 u16 val, mask = 0, cnt = 0, temp; 1849 1850 switch (dai->id) { 1851 case RX_MACRO_AIF1_PB: 1852 case RX_MACRO_AIF2_PB: 1853 case RX_MACRO_AIF3_PB: 1854 case RX_MACRO_AIF4_PB: 1855 for_each_set_bit(temp, &rx->active_ch_mask[dai->id], 1856 RX_MACRO_PORTS_MAX) { 1857 mask |= (1 << temp); 1858 if (++cnt == RX_MACRO_MAX_DMA_CH_PER_PORT) 1859 break; 1860 } 1861 /* 1862 * CDC_DMA_RX_0 port drives RX0/RX1 -- ch_mask 0x1/0x2/0x3 1863 * CDC_DMA_RX_1 port drives RX2/RX3 -- ch_mask 0x1/0x2/0x3 1864 * CDC_DMA_RX_2 port drives RX4 -- ch_mask 0x1 1865 * CDC_DMA_RX_3 port drives RX5 -- ch_mask 0x1 1866 * AIFn can pair to any CDC_DMA_RX_n port. 1867 * In general, below convention is used:: 1868 * CDC_DMA_RX_0(AIF1)/CDC_DMA_RX_1(AIF2)/ 1869 * CDC_DMA_RX_2(AIF3)/CDC_DMA_RX_3(AIF4) 1870 */ 1871 if (mask & 0x0C) 1872 mask = mask >> 2; 1873 if ((mask & 0x10) || (mask & 0x20)) 1874 mask = 0x1; 1875 *rx_slot = mask; 1876 *rx_num = rx->active_ch_cnt[dai->id]; 1877 break; 1878 case RX_MACRO_AIF_ECHO: 1879 val = snd_soc_component_read(component, CDC_RX_INP_MUX_RX_MIX_CFG4); 1880 if (val & RX_MACRO_EC_MIX_TX0_MASK) { 1881 mask |= 0x1; 1882 cnt++; 1883 } 1884 if (val & RX_MACRO_EC_MIX_TX1_MASK) { 1885 mask |= 0x2; 1886 cnt++; 1887 } 1888 val = snd_soc_component_read(component, 1889 CDC_RX_INP_MUX_RX_MIX_CFG5); 1890 if (val & RX_MACRO_EC_MIX_TX2_MASK) { 1891 mask |= 0x4; 1892 cnt++; 1893 } 1894 *tx_slot = mask; 1895 *tx_num = cnt; 1896 break; 1897 default: 1898 dev_err(component->dev, "%s: Invalid AIF\n", __func__); 1899 break; 1900 } 1901 return 0; 1902 } 1903 1904 static int rx_macro_digital_mute(struct snd_soc_dai *dai, int mute, int stream) 1905 { 1906 struct snd_soc_component *component = dai->component; 1907 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 1908 uint16_t j, reg, mix_reg, dsm_reg; 1909 u16 int_mux_cfg0, int_mux_cfg1; 1910 u8 int_mux_cfg0_val, int_mux_cfg1_val; 1911 1912 switch (dai->id) { 1913 case RX_MACRO_AIF1_PB: 1914 case RX_MACRO_AIF2_PB: 1915 case RX_MACRO_AIF3_PB: 1916 case RX_MACRO_AIF4_PB: 1917 for (j = 0; j < INTERP_MAX; j++) { 1918 reg = CDC_RX_RXn_RX_PATH_CTL(rx, j); 1919 mix_reg = CDC_RX_RXn_RX_PATH_MIX_CTL(rx, j); 1920 dsm_reg = CDC_RX_RXn_RX_PATH_DSM_CTL(rx, j); 1921 1922 if (mute) { 1923 snd_soc_component_update_bits(component, reg, 1924 CDC_RX_PATH_PGA_MUTE_MASK, 1925 CDC_RX_PATH_PGA_MUTE_ENABLE); 1926 snd_soc_component_update_bits(component, mix_reg, 1927 CDC_RX_PATH_PGA_MUTE_MASK, 1928 CDC_RX_PATH_PGA_MUTE_ENABLE); 1929 } else { 1930 snd_soc_component_update_bits(component, reg, 1931 CDC_RX_PATH_PGA_MUTE_MASK, 0x0); 1932 snd_soc_component_update_bits(component, mix_reg, 1933 CDC_RX_PATH_PGA_MUTE_MASK, 0x0); 1934 } 1935 1936 int_mux_cfg0 = CDC_RX_INP_MUX_RX_INT0_CFG0 + j * 8; 1937 int_mux_cfg1 = int_mux_cfg0 + 4; 1938 int_mux_cfg0_val = snd_soc_component_read(component, int_mux_cfg0); 1939 int_mux_cfg1_val = snd_soc_component_read(component, int_mux_cfg1); 1940 1941 if (snd_soc_component_read(component, dsm_reg) & 0x01) { 1942 if (int_mux_cfg0_val || (int_mux_cfg1_val & 0xF0)) 1943 snd_soc_component_update_bits(component, reg, 0x20, 0x20); 1944 if (int_mux_cfg1_val & 0x0F) { 1945 snd_soc_component_update_bits(component, reg, 0x20, 0x20); 1946 snd_soc_component_update_bits(component, mix_reg, 0x20, 1947 0x20); 1948 } 1949 } 1950 } 1951 break; 1952 default: 1953 break; 1954 } 1955 return 0; 1956 } 1957 1958 static const struct snd_soc_dai_ops rx_macro_dai_ops = { 1959 .hw_params = rx_macro_hw_params, 1960 .get_channel_map = rx_macro_get_channel_map, 1961 .mute_stream = rx_macro_digital_mute, 1962 }; 1963 1964 static struct snd_soc_dai_driver rx_macro_dai[] = { 1965 { 1966 .name = "rx_macro_rx1", 1967 .id = RX_MACRO_AIF1_PB, 1968 .playback = { 1969 .stream_name = "RX_MACRO_AIF1 Playback", 1970 .rates = RX_MACRO_RATES | RX_MACRO_FRAC_RATES, 1971 .formats = RX_MACRO_FORMATS, 1972 .rate_max = 384000, 1973 .rate_min = 8000, 1974 .channels_min = 1, 1975 .channels_max = 2, 1976 }, 1977 .ops = &rx_macro_dai_ops, 1978 }, 1979 { 1980 .name = "rx_macro_rx2", 1981 .id = RX_MACRO_AIF2_PB, 1982 .playback = { 1983 .stream_name = "RX_MACRO_AIF2 Playback", 1984 .rates = RX_MACRO_RATES | RX_MACRO_FRAC_RATES, 1985 .formats = RX_MACRO_FORMATS, 1986 .rate_max = 384000, 1987 .rate_min = 8000, 1988 .channels_min = 1, 1989 .channels_max = 2, 1990 }, 1991 .ops = &rx_macro_dai_ops, 1992 }, 1993 { 1994 .name = "rx_macro_rx3", 1995 .id = RX_MACRO_AIF3_PB, 1996 .playback = { 1997 .stream_name = "RX_MACRO_AIF3 Playback", 1998 .rates = RX_MACRO_RATES | RX_MACRO_FRAC_RATES, 1999 .formats = RX_MACRO_FORMATS, 2000 .rate_max = 384000, 2001 .rate_min = 8000, 2002 .channels_min = 1, 2003 .channels_max = 2, 2004 }, 2005 .ops = &rx_macro_dai_ops, 2006 }, 2007 { 2008 .name = "rx_macro_rx4", 2009 .id = RX_MACRO_AIF4_PB, 2010 .playback = { 2011 .stream_name = "RX_MACRO_AIF4 Playback", 2012 .rates = RX_MACRO_RATES | RX_MACRO_FRAC_RATES, 2013 .formats = RX_MACRO_FORMATS, 2014 .rate_max = 384000, 2015 .rate_min = 8000, 2016 .channels_min = 1, 2017 .channels_max = 2, 2018 }, 2019 .ops = &rx_macro_dai_ops, 2020 }, 2021 { 2022 .name = "rx_macro_echo", 2023 .id = RX_MACRO_AIF_ECHO, 2024 .capture = { 2025 .stream_name = "RX_AIF_ECHO Capture", 2026 .rates = RX_MACRO_ECHO_RATES, 2027 .formats = RX_MACRO_ECHO_FORMATS, 2028 .rate_max = 48000, 2029 .rate_min = 8000, 2030 .channels_min = 1, 2031 .channels_max = 3, 2032 }, 2033 .ops = &rx_macro_dai_ops, 2034 }, 2035 }; 2036 2037 static void rx_macro_mclk_enable(struct rx_macro *rx, bool mclk_enable) 2038 { 2039 struct regmap *regmap = rx->regmap; 2040 2041 if (mclk_enable) { 2042 if (rx->rx_mclk_users == 0) { 2043 regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_MCLK_CONTROL, 2044 CDC_RX_CLK_MCLK_EN_MASK | 2045 CDC_RX_CLK_MCLK2_EN_MASK, 2046 CDC_RX_CLK_MCLK_ENABLE | 2047 CDC_RX_CLK_MCLK2_ENABLE); 2048 regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL, 2049 CDC_RX_FS_MCLK_CNT_CLR_MASK, 0x00); 2050 regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL, 2051 CDC_RX_FS_MCLK_CNT_EN_MASK, 2052 CDC_RX_FS_MCLK_CNT_ENABLE); 2053 regcache_mark_dirty(regmap); 2054 regcache_sync(regmap); 2055 } 2056 rx->rx_mclk_users++; 2057 } else { 2058 if (rx->rx_mclk_users <= 0) { 2059 dev_err(rx->dev, "%s: clock already disabled\n", __func__); 2060 rx->rx_mclk_users = 0; 2061 return; 2062 } 2063 rx->rx_mclk_users--; 2064 if (rx->rx_mclk_users == 0) { 2065 regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL, 2066 CDC_RX_FS_MCLK_CNT_EN_MASK, 0x0); 2067 regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL, 2068 CDC_RX_FS_MCLK_CNT_CLR_MASK, 2069 CDC_RX_FS_MCLK_CNT_CLR); 2070 regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_MCLK_CONTROL, 2071 CDC_RX_CLK_MCLK_EN_MASK | 2072 CDC_RX_CLK_MCLK2_EN_MASK, 0x0); 2073 } 2074 } 2075 } 2076 2077 static int rx_macro_mclk_event(struct snd_soc_dapm_widget *w, 2078 struct snd_kcontrol *kcontrol, int event) 2079 { 2080 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2081 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2082 int ret = 0; 2083 2084 switch (event) { 2085 case SND_SOC_DAPM_PRE_PMU: 2086 rx_macro_mclk_enable(rx, true); 2087 break; 2088 case SND_SOC_DAPM_POST_PMD: 2089 rx_macro_mclk_enable(rx, false); 2090 break; 2091 default: 2092 dev_err(component->dev, "%s: invalid DAPM event %d\n", __func__, event); 2093 ret = -EINVAL; 2094 } 2095 return ret; 2096 } 2097 2098 static bool rx_macro_adie_lb(struct snd_soc_component *component, 2099 int interp_idx) 2100 { 2101 u16 int_mux_cfg0, int_mux_cfg1; 2102 u8 int_n_inp0, int_n_inp1, int_n_inp2; 2103 2104 int_mux_cfg0 = CDC_RX_INP_MUX_RX_INT0_CFG0 + interp_idx * 8; 2105 int_mux_cfg1 = int_mux_cfg0 + 4; 2106 2107 int_n_inp0 = snd_soc_component_read_field(component, int_mux_cfg0, 2108 CDC_RX_INTX_1_MIX_INP0_SEL_MASK); 2109 int_n_inp1 = snd_soc_component_read_field(component, int_mux_cfg0, 2110 CDC_RX_INTX_1_MIX_INP1_SEL_MASK); 2111 int_n_inp2 = snd_soc_component_read_field(component, int_mux_cfg1, 2112 CDC_RX_INTX_1_MIX_INP2_SEL_MASK); 2113 2114 if (int_n_inp0 == INTn_1_INP_SEL_DEC0 || 2115 int_n_inp0 == INTn_1_INP_SEL_DEC1 || 2116 int_n_inp0 == INTn_1_INP_SEL_IIR0 || 2117 int_n_inp0 == INTn_1_INP_SEL_IIR1) 2118 return true; 2119 2120 if (int_n_inp1 == INTn_1_INP_SEL_DEC0 || 2121 int_n_inp1 == INTn_1_INP_SEL_DEC1 || 2122 int_n_inp1 == INTn_1_INP_SEL_IIR0 || 2123 int_n_inp1 == INTn_1_INP_SEL_IIR1) 2124 return true; 2125 2126 if (int_n_inp2 == INTn_1_INP_SEL_DEC0 || 2127 int_n_inp2 == INTn_1_INP_SEL_DEC1 || 2128 int_n_inp2 == INTn_1_INP_SEL_IIR0 || 2129 int_n_inp2 == INTn_1_INP_SEL_IIR1) 2130 return true; 2131 2132 return false; 2133 } 2134 2135 static int rx_macro_enable_interp_clk(struct snd_soc_component *component, 2136 int event, int interp_idx); 2137 static int rx_macro_enable_main_path(struct snd_soc_dapm_widget *w, 2138 struct snd_kcontrol *kcontrol, 2139 int event) 2140 { 2141 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2142 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2143 u16 gain_reg, reg; 2144 2145 reg = CDC_RX_RXn_RX_PATH_CTL(rx, w->shift); 2146 gain_reg = CDC_RX_RXn_RX_VOL_CTL(rx, w->shift); 2147 2148 switch (event) { 2149 case SND_SOC_DAPM_PRE_PMU: 2150 rx_macro_enable_interp_clk(component, event, w->shift); 2151 if (rx_macro_adie_lb(component, w->shift)) 2152 snd_soc_component_update_bits(component, reg, 2153 CDC_RX_PATH_CLK_EN_MASK, 2154 CDC_RX_PATH_CLK_ENABLE); 2155 break; 2156 case SND_SOC_DAPM_POST_PMU: 2157 snd_soc_component_write(component, gain_reg, 2158 snd_soc_component_read(component, gain_reg)); 2159 break; 2160 case SND_SOC_DAPM_POST_PMD: 2161 rx_macro_enable_interp_clk(component, event, w->shift); 2162 break; 2163 } 2164 2165 return 0; 2166 } 2167 2168 static int rx_macro_config_compander(struct snd_soc_component *component, 2169 struct rx_macro *rx, 2170 int comp, int event) 2171 { 2172 u8 pcm_rate, val; 2173 2174 /* AUX does not have compander */ 2175 if (comp == INTERP_AUX) 2176 return 0; 2177 2178 pcm_rate = snd_soc_component_read(component, CDC_RX_RXn_RX_PATH_CTL(rx, comp)) & 0x0F; 2179 if (pcm_rate < 0x06) 2180 val = 0x03; 2181 else if (pcm_rate < 0x08) 2182 val = 0x01; 2183 else if (pcm_rate < 0x0B) 2184 val = 0x02; 2185 else 2186 val = 0x00; 2187 2188 if (SND_SOC_DAPM_EVENT_ON(event)) 2189 snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_CFG3(rx, comp), 2190 CDC_RX_DC_COEFF_SEL_MASK, val); 2191 2192 if (SND_SOC_DAPM_EVENT_OFF(event)) 2193 snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_CFG3(rx, comp), 2194 CDC_RX_DC_COEFF_SEL_MASK, 0x3); 2195 if (!rx->comp_enabled[comp]) 2196 return 0; 2197 2198 if (SND_SOC_DAPM_EVENT_ON(event)) { 2199 /* Enable Compander Clock */ 2200 snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp), 2201 CDC_RX_COMPANDERn_CLK_EN_MASK, 0x1); 2202 snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp), 2203 CDC_RX_COMPANDERn_SOFT_RST_MASK, 0x1); 2204 snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp), 2205 CDC_RX_COMPANDERn_SOFT_RST_MASK, 0x0); 2206 snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG0(rx, comp), 2207 CDC_RX_RXn_COMP_EN_MASK, 0x1); 2208 } 2209 2210 if (SND_SOC_DAPM_EVENT_OFF(event)) { 2211 snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp), 2212 CDC_RX_COMPANDERn_HALT_MASK, 0x1); 2213 snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG0(rx, comp), 2214 CDC_RX_RXn_COMP_EN_MASK, 0x0); 2215 snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp), 2216 CDC_RX_COMPANDERn_CLK_EN_MASK, 0x0); 2217 snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp), 2218 CDC_RX_COMPANDERn_HALT_MASK, 0x0); 2219 } 2220 2221 return 0; 2222 } 2223 2224 static int rx_macro_load_compander_coeff(struct snd_soc_component *component, 2225 struct rx_macro *rx, 2226 int comp, int event) 2227 { 2228 u16 comp_coeff_lsb_reg, comp_coeff_msb_reg; 2229 int i; 2230 int hph_pwr_mode; 2231 2232 /* AUX does not have compander */ 2233 if (comp == INTERP_AUX) 2234 return 0; 2235 2236 if (!rx->comp_enabled[comp]) 2237 return 0; 2238 2239 if (comp == INTERP_HPHL) { 2240 comp_coeff_lsb_reg = CDC_RX_TOP_HPHL_COMP_WR_LSB; 2241 comp_coeff_msb_reg = CDC_RX_TOP_HPHL_COMP_WR_MSB; 2242 } else if (comp == INTERP_HPHR) { 2243 comp_coeff_lsb_reg = CDC_RX_TOP_HPHR_COMP_WR_LSB; 2244 comp_coeff_msb_reg = CDC_RX_TOP_HPHR_COMP_WR_MSB; 2245 } else { 2246 /* compander coefficients are loaded only for hph path */ 2247 return 0; 2248 } 2249 2250 hph_pwr_mode = rx->hph_pwr_mode; 2251 2252 if (SND_SOC_DAPM_EVENT_ON(event)) { 2253 /* Load Compander Coeff */ 2254 for (i = 0; i < COMP_MAX_COEFF; i++) { 2255 snd_soc_component_write(component, comp_coeff_lsb_reg, 2256 comp_coeff_table[hph_pwr_mode][i].lsb); 2257 snd_soc_component_write(component, comp_coeff_msb_reg, 2258 comp_coeff_table[hph_pwr_mode][i].msb); 2259 } 2260 } 2261 2262 return 0; 2263 } 2264 2265 static void rx_macro_enable_softclip_clk(struct snd_soc_component *component, 2266 struct rx_macro *rx, bool enable) 2267 { 2268 if (enable) { 2269 if (rx->softclip_clk_users == 0) 2270 snd_soc_component_write_field(component, CDC_RX_SOFTCLIP_CRC, 2271 CDC_RX_SOFTCLIP_CLK_EN_MASK, 1); 2272 rx->softclip_clk_users++; 2273 } else { 2274 rx->softclip_clk_users--; 2275 if (rx->softclip_clk_users == 0) 2276 snd_soc_component_write_field(component, CDC_RX_SOFTCLIP_CRC, 2277 CDC_RX_SOFTCLIP_CLK_EN_MASK, 0); 2278 } 2279 } 2280 2281 static int rx_macro_config_softclip(struct snd_soc_component *component, 2282 struct rx_macro *rx, int event) 2283 { 2284 2285 if (!rx->is_softclip_on) 2286 return 0; 2287 2288 if (SND_SOC_DAPM_EVENT_ON(event)) { 2289 /* Enable Softclip clock */ 2290 rx_macro_enable_softclip_clk(component, rx, true); 2291 /* Enable Softclip control */ 2292 snd_soc_component_write_field(component, CDC_RX_SOFTCLIP_SOFTCLIP_CTRL, 2293 CDC_RX_SOFTCLIP_EN_MASK, 0x01); 2294 } 2295 2296 if (SND_SOC_DAPM_EVENT_OFF(event)) { 2297 snd_soc_component_write_field(component, CDC_RX_SOFTCLIP_SOFTCLIP_CTRL, 2298 CDC_RX_SOFTCLIP_EN_MASK, 0x0); 2299 rx_macro_enable_softclip_clk(component, rx, false); 2300 } 2301 2302 return 0; 2303 } 2304 2305 static int rx_macro_config_aux_hpf(struct snd_soc_component *component, 2306 struct rx_macro *rx, int event) 2307 { 2308 if (SND_SOC_DAPM_EVENT_ON(event)) { 2309 /* Update Aux HPF control */ 2310 if (!rx->is_aux_hpf_on) 2311 snd_soc_component_update_bits(component, 2312 CDC_RX_RXn_RX_PATH_CFG1(rx, 2), 0x04, 0x00); 2313 } 2314 2315 if (SND_SOC_DAPM_EVENT_OFF(event)) { 2316 /* Reset to default (HPF=ON) */ 2317 snd_soc_component_update_bits(component, 2318 CDC_RX_RXn_RX_PATH_CFG1(rx, 2), 0x04, 0x04); 2319 } 2320 2321 return 0; 2322 } 2323 2324 static inline void rx_macro_enable_clsh_block(struct rx_macro *rx, bool enable) 2325 { 2326 if ((enable && ++rx->clsh_users == 1) || (!enable && --rx->clsh_users == 0)) 2327 snd_soc_component_update_bits(rx->component, CDC_RX_CLSH_CRC, 2328 CDC_RX_CLSH_CLK_EN_MASK, enable); 2329 if (rx->clsh_users < 0) 2330 rx->clsh_users = 0; 2331 } 2332 2333 static int rx_macro_config_classh(struct snd_soc_component *component, 2334 struct rx_macro *rx, 2335 int interp_n, int event) 2336 { 2337 if (SND_SOC_DAPM_EVENT_OFF(event)) { 2338 rx_macro_enable_clsh_block(rx, false); 2339 return 0; 2340 } 2341 2342 if (!SND_SOC_DAPM_EVENT_ON(event)) 2343 return 0; 2344 2345 rx_macro_enable_clsh_block(rx, true); 2346 if (interp_n == INTERP_HPHL || 2347 interp_n == INTERP_HPHR) { 2348 /* 2349 * These K1 values depend on the Headphone Impedance 2350 * For now it is assumed to be 16 ohm 2351 */ 2352 snd_soc_component_write(component, CDC_RX_CLSH_K1_LSB, 0xc0); 2353 snd_soc_component_write_field(component, CDC_RX_CLSH_K1_MSB, 2354 CDC_RX_CLSH_K1_MSB_COEFF_MASK, 0); 2355 } 2356 switch (interp_n) { 2357 case INTERP_HPHL: 2358 if (rx->is_ear_mode_on) 2359 snd_soc_component_update_bits(component, 2360 CDC_RX_CLSH_HPH_V_PA, 2361 CDC_RX_CLSH_HPH_V_PA_MIN_MASK, 0x39); 2362 else 2363 snd_soc_component_update_bits(component, 2364 CDC_RX_CLSH_HPH_V_PA, 2365 CDC_RX_CLSH_HPH_V_PA_MIN_MASK, 0x1c); 2366 snd_soc_component_update_bits(component, 2367 CDC_RX_CLSH_DECAY_CTRL, 2368 CDC_RX_CLSH_DECAY_RATE_MASK, 0x0); 2369 snd_soc_component_write_field(component, 2370 CDC_RX_RXn_RX_PATH_CFG0(rx, 0), 2371 CDC_RX_RXn_CLSH_EN_MASK, 0x1); 2372 break; 2373 case INTERP_HPHR: 2374 if (rx->is_ear_mode_on) 2375 snd_soc_component_update_bits(component, 2376 CDC_RX_CLSH_HPH_V_PA, 2377 CDC_RX_CLSH_HPH_V_PA_MIN_MASK, 0x39); 2378 else 2379 snd_soc_component_update_bits(component, 2380 CDC_RX_CLSH_HPH_V_PA, 2381 CDC_RX_CLSH_HPH_V_PA_MIN_MASK, 0x1c); 2382 snd_soc_component_update_bits(component, 2383 CDC_RX_CLSH_DECAY_CTRL, 2384 CDC_RX_CLSH_DECAY_RATE_MASK, 0x0); 2385 snd_soc_component_write_field(component, 2386 CDC_RX_RXn_RX_PATH_CFG0(rx, 1), 2387 CDC_RX_RXn_CLSH_EN_MASK, 0x1); 2388 break; 2389 case INTERP_AUX: 2390 snd_soc_component_update_bits(component, 2391 CDC_RX_RXn_RX_PATH_CFG0(rx, 2), 2392 CDC_RX_RX2_DLY_Z_EN_MASK, 1); 2393 snd_soc_component_write_field(component, 2394 CDC_RX_RXn_RX_PATH_CFG0(rx, 2), 2395 CDC_RX_RX2_CLSH_EN_MASK, 1); 2396 break; 2397 } 2398 2399 return 0; 2400 } 2401 2402 static void rx_macro_hd2_control(struct snd_soc_component *component, 2403 u16 interp_idx, int event) 2404 { 2405 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2406 u16 hd2_scale_reg, hd2_enable_reg; 2407 2408 switch (interp_idx) { 2409 case INTERP_HPHL: 2410 hd2_scale_reg = CDC_RX_RXn_RX_PATH_SEC3(rx, 0); 2411 hd2_enable_reg = CDC_RX_RXn_RX_PATH_CFG0(rx, 0); 2412 break; 2413 case INTERP_HPHR: 2414 hd2_scale_reg = CDC_RX_RXn_RX_PATH_SEC3(rx, 1); 2415 hd2_enable_reg = CDC_RX_RXn_RX_PATH_CFG0(rx, 1); 2416 break; 2417 } 2418 2419 if (hd2_enable_reg && SND_SOC_DAPM_EVENT_ON(event)) { 2420 snd_soc_component_update_bits(component, hd2_scale_reg, 2421 CDC_RX_RXn_HD2_ALPHA_MASK, 0x14); 2422 snd_soc_component_write_field(component, hd2_enable_reg, 2423 CDC_RX_RXn_HD2_EN_MASK, 1); 2424 } 2425 2426 if (hd2_enable_reg && SND_SOC_DAPM_EVENT_OFF(event)) { 2427 snd_soc_component_write_field(component, hd2_enable_reg, 2428 CDC_RX_RXn_HD2_EN_MASK, 0); 2429 snd_soc_component_update_bits(component, hd2_scale_reg, 2430 CDC_RX_RXn_HD2_ALPHA_MASK, 0x0); 2431 } 2432 } 2433 2434 static int rx_macro_get_compander(struct snd_kcontrol *kcontrol, 2435 struct snd_ctl_elem_value *ucontrol) 2436 { 2437 struct snd_soc_component *component = 2438 snd_soc_kcontrol_component(kcontrol); 2439 int comp = ((struct soc_mixer_control *) kcontrol->private_value)->shift; 2440 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2441 2442 ucontrol->value.integer.value[0] = rx->comp_enabled[comp]; 2443 return 0; 2444 } 2445 2446 static int rx_macro_set_compander(struct snd_kcontrol *kcontrol, 2447 struct snd_ctl_elem_value *ucontrol) 2448 { 2449 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2450 int comp = ((struct soc_mixer_control *) kcontrol->private_value)->shift; 2451 int value = ucontrol->value.integer.value[0]; 2452 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2453 2454 rx->comp_enabled[comp] = value; 2455 2456 return 0; 2457 } 2458 2459 static int rx_macro_mux_get(struct snd_kcontrol *kcontrol, 2460 struct snd_ctl_elem_value *ucontrol) 2461 { 2462 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol); 2463 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm); 2464 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2465 2466 ucontrol->value.enumerated.item[0] = 2467 rx->rx_port_value[widget->shift]; 2468 return 0; 2469 } 2470 2471 static int rx_macro_mux_put(struct snd_kcontrol *kcontrol, 2472 struct snd_ctl_elem_value *ucontrol) 2473 { 2474 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol); 2475 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm); 2476 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 2477 struct snd_soc_dapm_update *update = NULL; 2478 u32 rx_port_value = ucontrol->value.enumerated.item[0]; 2479 unsigned int dai_id; 2480 u32 aif_rst; 2481 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2482 2483 aif_rst = rx->rx_port_value[widget->shift]; 2484 if (!rx_port_value) { 2485 if (aif_rst == 0) 2486 return 0; 2487 if (aif_rst > RX_MACRO_AIF4_PB) { 2488 dev_err(component->dev, "%s: Invalid AIF reset\n", __func__); 2489 return 0; 2490 } 2491 } 2492 rx->rx_port_value[widget->shift] = rx_port_value; 2493 2494 switch (rx_port_value) { 2495 case 0: 2496 /* 2497 * active_ch_cnt and active_ch_mask use DAI IDs (RX_MACRO_MAX_DAIS). 2498 * active_ch_cnt == 0 was tested in if() above. 2499 */ 2500 dai_id = aif_rst - 1; 2501 if (rx->active_ch_cnt[dai_id]) { 2502 clear_bit(widget->shift, &rx->active_ch_mask[dai_id]); 2503 rx->active_ch_cnt[dai_id]--; 2504 } 2505 break; 2506 case 1: 2507 case 2: 2508 case 3: 2509 case 4: 2510 /* active_ch_cnt and active_ch_mask use DAI IDs (WSA_MACRO_MAX_DAIS). */ 2511 dai_id = rx_port_value - 1; 2512 set_bit(widget->shift, &rx->active_ch_mask[dai_id]); 2513 rx->active_ch_cnt[dai_id]++; 2514 break; 2515 default: 2516 dev_err(component->dev, 2517 "%s:Invalid AIF_ID for RX_MACRO MUX %d\n", 2518 __func__, rx_port_value); 2519 goto err; 2520 } 2521 2522 snd_soc_dapm_mux_update_power(widget->dapm, kcontrol, 2523 rx_port_value, e, update); 2524 return 0; 2525 err: 2526 return -EINVAL; 2527 } 2528 2529 static const struct snd_kcontrol_new rx_macro_rx0_mux = 2530 SOC_DAPM_ENUM_EXT("rx_macro_rx0", rx_macro_rx0_enum, 2531 rx_macro_mux_get, rx_macro_mux_put); 2532 static const struct snd_kcontrol_new rx_macro_rx1_mux = 2533 SOC_DAPM_ENUM_EXT("rx_macro_rx1", rx_macro_rx1_enum, 2534 rx_macro_mux_get, rx_macro_mux_put); 2535 static const struct snd_kcontrol_new rx_macro_rx2_mux = 2536 SOC_DAPM_ENUM_EXT("rx_macro_rx2", rx_macro_rx2_enum, 2537 rx_macro_mux_get, rx_macro_mux_put); 2538 static const struct snd_kcontrol_new rx_macro_rx3_mux = 2539 SOC_DAPM_ENUM_EXT("rx_macro_rx3", rx_macro_rx3_enum, 2540 rx_macro_mux_get, rx_macro_mux_put); 2541 static const struct snd_kcontrol_new rx_macro_rx4_mux = 2542 SOC_DAPM_ENUM_EXT("rx_macro_rx4", rx_macro_rx4_enum, 2543 rx_macro_mux_get, rx_macro_mux_put); 2544 static const struct snd_kcontrol_new rx_macro_rx5_mux = 2545 SOC_DAPM_ENUM_EXT("rx_macro_rx5", rx_macro_rx5_enum, 2546 rx_macro_mux_get, rx_macro_mux_put); 2547 2548 static int rx_macro_get_ear_mode(struct snd_kcontrol *kcontrol, 2549 struct snd_ctl_elem_value *ucontrol) 2550 { 2551 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2552 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2553 2554 ucontrol->value.integer.value[0] = rx->is_ear_mode_on; 2555 return 0; 2556 } 2557 2558 static int rx_macro_put_ear_mode(struct snd_kcontrol *kcontrol, 2559 struct snd_ctl_elem_value *ucontrol) 2560 { 2561 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2562 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2563 2564 rx->is_ear_mode_on = (!ucontrol->value.integer.value[0] ? false : true); 2565 return 0; 2566 } 2567 2568 static int rx_macro_get_hph_hd2_mode(struct snd_kcontrol *kcontrol, 2569 struct snd_ctl_elem_value *ucontrol) 2570 { 2571 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2572 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2573 2574 ucontrol->value.integer.value[0] = rx->hph_hd2_mode; 2575 return 0; 2576 } 2577 2578 static int rx_macro_put_hph_hd2_mode(struct snd_kcontrol *kcontrol, 2579 struct snd_ctl_elem_value *ucontrol) 2580 { 2581 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2582 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2583 2584 rx->hph_hd2_mode = ucontrol->value.integer.value[0]; 2585 return 0; 2586 } 2587 2588 static int rx_macro_get_hph_pwr_mode(struct snd_kcontrol *kcontrol, 2589 struct snd_ctl_elem_value *ucontrol) 2590 { 2591 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2592 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2593 2594 ucontrol->value.enumerated.item[0] = rx->hph_pwr_mode; 2595 return 0; 2596 } 2597 2598 static int rx_macro_put_hph_pwr_mode(struct snd_kcontrol *kcontrol, 2599 struct snd_ctl_elem_value *ucontrol) 2600 { 2601 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2602 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2603 2604 rx->hph_pwr_mode = ucontrol->value.enumerated.item[0]; 2605 return 0; 2606 } 2607 2608 static int rx_macro_soft_clip_enable_get(struct snd_kcontrol *kcontrol, 2609 struct snd_ctl_elem_value *ucontrol) 2610 { 2611 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2612 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2613 2614 ucontrol->value.integer.value[0] = rx->is_softclip_on; 2615 2616 return 0; 2617 } 2618 2619 static int rx_macro_soft_clip_enable_put(struct snd_kcontrol *kcontrol, 2620 struct snd_ctl_elem_value *ucontrol) 2621 { 2622 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2623 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2624 2625 rx->is_softclip_on = ucontrol->value.integer.value[0]; 2626 2627 return 0; 2628 } 2629 2630 static int rx_macro_aux_hpf_mode_get(struct snd_kcontrol *kcontrol, 2631 struct snd_ctl_elem_value *ucontrol) 2632 { 2633 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2634 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2635 2636 ucontrol->value.integer.value[0] = rx->is_aux_hpf_on; 2637 2638 return 0; 2639 } 2640 2641 static int rx_macro_aux_hpf_mode_put(struct snd_kcontrol *kcontrol, 2642 struct snd_ctl_elem_value *ucontrol) 2643 { 2644 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 2645 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2646 2647 rx->is_aux_hpf_on = ucontrol->value.integer.value[0]; 2648 2649 return 0; 2650 } 2651 2652 static int rx_macro_hphdelay_lutbypass(struct snd_soc_component *component, 2653 struct rx_macro *rx, 2654 u16 interp_idx, int event) 2655 { 2656 u16 hph_lut_bypass_reg; 2657 u16 hph_comp_ctrl7; 2658 2659 switch (interp_idx) { 2660 case INTERP_HPHL: 2661 hph_lut_bypass_reg = CDC_RX_TOP_HPHL_COMP_LUT; 2662 hph_comp_ctrl7 = CDC_RX_COMPANDER0_CTL7; 2663 break; 2664 case INTERP_HPHR: 2665 hph_lut_bypass_reg = CDC_RX_TOP_HPHR_COMP_LUT; 2666 hph_comp_ctrl7 = CDC_RX_COMPANDER1_CTL7; 2667 break; 2668 default: 2669 return -EINVAL; 2670 } 2671 2672 if (hph_lut_bypass_reg && SND_SOC_DAPM_EVENT_ON(event)) { 2673 if (interp_idx == INTERP_HPHL) { 2674 if (rx->is_ear_mode_on) 2675 snd_soc_component_write_field(component, 2676 CDC_RX_RXn_RX_PATH_CFG1(rx, 0), 2677 CDC_RX_RX0_HPH_L_EAR_SEL_MASK, 0x1); 2678 else 2679 snd_soc_component_write_field(component, 2680 hph_lut_bypass_reg, 2681 CDC_RX_TOP_HPH_LUT_BYPASS_MASK, 1); 2682 } else { 2683 snd_soc_component_write_field(component, hph_lut_bypass_reg, 2684 CDC_RX_TOP_HPH_LUT_BYPASS_MASK, 1); 2685 } 2686 if (rx->hph_pwr_mode) 2687 snd_soc_component_write_field(component, hph_comp_ctrl7, 2688 CDC_RX_COMPANDER1_HPH_LOW_PWR_MODE_MASK, 0x0); 2689 } 2690 2691 if (hph_lut_bypass_reg && SND_SOC_DAPM_EVENT_OFF(event)) { 2692 snd_soc_component_write_field(component, 2693 CDC_RX_RXn_RX_PATH_CFG1(rx, 0), 2694 CDC_RX_RX0_HPH_L_EAR_SEL_MASK, 0x0); 2695 snd_soc_component_update_bits(component, hph_lut_bypass_reg, 2696 CDC_RX_TOP_HPH_LUT_BYPASS_MASK, 0); 2697 snd_soc_component_write_field(component, hph_comp_ctrl7, 2698 CDC_RX_COMPANDER1_HPH_LOW_PWR_MODE_MASK, 0x1); 2699 } 2700 2701 return 0; 2702 } 2703 2704 static int rx_macro_enable_interp_clk(struct snd_soc_component *component, 2705 int event, int interp_idx) 2706 { 2707 u16 main_reg, dsm_reg, rx_cfg2_reg; 2708 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2709 2710 main_reg = CDC_RX_RXn_RX_PATH_CTL(rx, interp_idx); 2711 dsm_reg = CDC_RX_RXn_RX_PATH_DSM_CTL(rx, interp_idx); 2712 rx_cfg2_reg = CDC_RX_RXn_RX_PATH_CFG2(rx, interp_idx); 2713 2714 if (SND_SOC_DAPM_EVENT_ON(event)) { 2715 if (rx->main_clk_users[interp_idx] == 0) { 2716 /* Main path PGA mute enable */ 2717 snd_soc_component_write_field(component, main_reg, 2718 CDC_RX_PATH_PGA_MUTE_MASK, 0x1); 2719 snd_soc_component_write_field(component, dsm_reg, 2720 CDC_RX_RXn_DSM_CLK_EN_MASK, 0x1); 2721 snd_soc_component_update_bits(component, rx_cfg2_reg, 2722 CDC_RX_RXn_HPF_CUT_FREQ_MASK, 0x03); 2723 rx_macro_load_compander_coeff(component, rx, interp_idx, event); 2724 if (rx->hph_hd2_mode) 2725 rx_macro_hd2_control(component, interp_idx, event); 2726 rx_macro_hphdelay_lutbypass(component, rx, interp_idx, event); 2727 rx_macro_config_compander(component, rx, interp_idx, event); 2728 if (interp_idx == INTERP_AUX) { 2729 rx_macro_config_softclip(component, rx, event); 2730 rx_macro_config_aux_hpf(component, rx, event); 2731 } 2732 rx_macro_config_classh(component, rx, interp_idx, event); 2733 } 2734 rx->main_clk_users[interp_idx]++; 2735 } 2736 2737 if (SND_SOC_DAPM_EVENT_OFF(event)) { 2738 rx->main_clk_users[interp_idx]--; 2739 if (rx->main_clk_users[interp_idx] <= 0) { 2740 rx->main_clk_users[interp_idx] = 0; 2741 /* Main path PGA mute enable */ 2742 snd_soc_component_write_field(component, main_reg, 2743 CDC_RX_PATH_PGA_MUTE_MASK, 0x1); 2744 /* Clk Disable */ 2745 snd_soc_component_write_field(component, dsm_reg, 2746 CDC_RX_RXn_DSM_CLK_EN_MASK, 0); 2747 snd_soc_component_write_field(component, main_reg, 2748 CDC_RX_PATH_CLK_EN_MASK, 0); 2749 /* Reset enable and disable */ 2750 snd_soc_component_write_field(component, main_reg, 2751 CDC_RX_PATH_RESET_EN_MASK, 1); 2752 snd_soc_component_write_field(component, main_reg, 2753 CDC_RX_PATH_RESET_EN_MASK, 0); 2754 /* Reset rate to 48K*/ 2755 snd_soc_component_update_bits(component, main_reg, 2756 CDC_RX_PATH_PCM_RATE_MASK, 2757 0x04); 2758 snd_soc_component_update_bits(component, rx_cfg2_reg, 2759 CDC_RX_RXn_HPF_CUT_FREQ_MASK, 0x00); 2760 rx_macro_config_classh(component, rx, interp_idx, event); 2761 rx_macro_config_compander(component, rx, interp_idx, event); 2762 if (interp_idx == INTERP_AUX) { 2763 rx_macro_config_softclip(component, rx, event); 2764 rx_macro_config_aux_hpf(component, rx, event); 2765 } 2766 rx_macro_hphdelay_lutbypass(component, rx, interp_idx, event); 2767 if (rx->hph_hd2_mode) 2768 rx_macro_hd2_control(component, interp_idx, event); 2769 } 2770 } 2771 2772 return rx->main_clk_users[interp_idx]; 2773 } 2774 2775 static int rx_macro_enable_mix_path(struct snd_soc_dapm_widget *w, 2776 struct snd_kcontrol *kcontrol, int event) 2777 { 2778 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2779 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2780 u16 gain_reg, mix_reg; 2781 2782 gain_reg = CDC_RX_RXn_RX_VOL_MIX_CTL(rx, w->shift); 2783 mix_reg = CDC_RX_RXn_RX_PATH_MIX_CTL(rx, w->shift); 2784 2785 switch (event) { 2786 case SND_SOC_DAPM_PRE_PMU: 2787 rx_macro_enable_interp_clk(component, event, w->shift); 2788 break; 2789 case SND_SOC_DAPM_POST_PMU: 2790 snd_soc_component_write(component, gain_reg, 2791 snd_soc_component_read(component, gain_reg)); 2792 break; 2793 case SND_SOC_DAPM_POST_PMD: 2794 /* Clk Disable */ 2795 snd_soc_component_update_bits(component, mix_reg, 2796 CDC_RX_RXn_MIX_CLK_EN_MASK, 0x00); 2797 rx_macro_enable_interp_clk(component, event, w->shift); 2798 /* Reset enable and disable */ 2799 snd_soc_component_update_bits(component, mix_reg, 2800 CDC_RX_RXn_MIX_RESET_MASK, 2801 CDC_RX_RXn_MIX_RESET); 2802 snd_soc_component_update_bits(component, mix_reg, 2803 CDC_RX_RXn_MIX_RESET_MASK, 0x00); 2804 break; 2805 } 2806 2807 return 0; 2808 } 2809 2810 static int rx_macro_enable_rx_path_clk(struct snd_soc_dapm_widget *w, 2811 struct snd_kcontrol *kcontrol, int event) 2812 { 2813 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2814 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 2815 2816 switch (event) { 2817 case SND_SOC_DAPM_PRE_PMU: 2818 rx_macro_enable_interp_clk(component, event, w->shift); 2819 snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG1(rx, w->shift), 2820 CDC_RX_RXn_SIDETONE_EN_MASK, 1); 2821 snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CTL(rx, w->shift), 2822 CDC_RX_PATH_CLK_EN_MASK, 1); 2823 break; 2824 case SND_SOC_DAPM_POST_PMD: 2825 snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG1(rx, w->shift), 2826 CDC_RX_RXn_SIDETONE_EN_MASK, 0); 2827 rx_macro_enable_interp_clk(component, event, w->shift); 2828 break; 2829 default: 2830 break; 2831 } 2832 return 0; 2833 } 2834 2835 static int rx_macro_set_iir_gain(struct snd_soc_dapm_widget *w, 2836 struct snd_kcontrol *kcontrol, int event) 2837 { 2838 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2839 2840 switch (event) { 2841 case SND_SOC_DAPM_POST_PMU: /* fall through */ 2842 case SND_SOC_DAPM_PRE_PMD: 2843 if (strnstr(w->name, "IIR0", sizeof("IIR0"))) { 2844 snd_soc_component_write(component, 2845 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL, 2846 snd_soc_component_read(component, 2847 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL)); 2848 snd_soc_component_write(component, 2849 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL, 2850 snd_soc_component_read(component, 2851 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL)); 2852 snd_soc_component_write(component, 2853 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL, 2854 snd_soc_component_read(component, 2855 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL)); 2856 snd_soc_component_write(component, 2857 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL, 2858 snd_soc_component_read(component, 2859 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL)); 2860 } else { 2861 snd_soc_component_write(component, 2862 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL, 2863 snd_soc_component_read(component, 2864 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL)); 2865 snd_soc_component_write(component, 2866 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL, 2867 snd_soc_component_read(component, 2868 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL)); 2869 snd_soc_component_write(component, 2870 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL, 2871 snd_soc_component_read(component, 2872 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL)); 2873 snd_soc_component_write(component, 2874 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL, 2875 snd_soc_component_read(component, 2876 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL)); 2877 } 2878 break; 2879 } 2880 return 0; 2881 } 2882 2883 static uint32_t get_iir_band_coeff(struct snd_soc_component *component, 2884 int iir_idx, int band_idx, int coeff_idx) 2885 { 2886 u32 value; 2887 int reg, b2_reg; 2888 2889 /* Address does not automatically update if reading */ 2890 reg = CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL + 0x80 * iir_idx; 2891 b2_reg = CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL + 0x80 * iir_idx; 2892 2893 snd_soc_component_write(component, reg, 2894 ((band_idx * BAND_MAX + coeff_idx) * 2895 sizeof(uint32_t)) & 0x7F); 2896 2897 value = snd_soc_component_read(component, b2_reg); 2898 snd_soc_component_write(component, reg, 2899 ((band_idx * BAND_MAX + coeff_idx) 2900 * sizeof(uint32_t) + 1) & 0x7F); 2901 2902 value |= (snd_soc_component_read(component, b2_reg) << 8); 2903 snd_soc_component_write(component, reg, 2904 ((band_idx * BAND_MAX + coeff_idx) 2905 * sizeof(uint32_t) + 2) & 0x7F); 2906 2907 value |= (snd_soc_component_read(component, b2_reg) << 16); 2908 snd_soc_component_write(component, reg, 2909 ((band_idx * BAND_MAX + coeff_idx) 2910 * sizeof(uint32_t) + 3) & 0x7F); 2911 2912 /* Mask bits top 2 bits since they are reserved */ 2913 value |= (snd_soc_component_read(component, b2_reg) << 24); 2914 return value; 2915 } 2916 2917 static void set_iir_band_coeff(struct snd_soc_component *component, 2918 int iir_idx, int band_idx, uint32_t value) 2919 { 2920 int reg = CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL + 0x80 * iir_idx; 2921 2922 snd_soc_component_write(component, reg, (value & 0xFF)); 2923 snd_soc_component_write(component, reg, (value >> 8) & 0xFF); 2924 snd_soc_component_write(component, reg, (value >> 16) & 0xFF); 2925 /* Mask top 2 bits, 7-8 are reserved */ 2926 snd_soc_component_write(component, reg, (value >> 24) & 0x3F); 2927 } 2928 2929 static int rx_macro_put_iir_band_audio_mixer( 2930 struct snd_kcontrol *kcontrol, 2931 struct snd_ctl_elem_value *ucontrol) 2932 { 2933 struct snd_soc_component *component = 2934 snd_soc_kcontrol_component(kcontrol); 2935 struct wcd_iir_filter_ctl *ctl = 2936 (struct wcd_iir_filter_ctl *)kcontrol->private_value; 2937 struct soc_bytes_ext *params = &ctl->bytes_ext; 2938 int iir_idx = ctl->iir_idx; 2939 int band_idx = ctl->band_idx; 2940 u32 coeff[BAND_MAX]; 2941 int reg = CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL + 0x80 * iir_idx; 2942 2943 memcpy(&coeff[0], ucontrol->value.bytes.data, params->max); 2944 2945 /* Mask top bit it is reserved */ 2946 /* Updates addr automatically for each B2 write */ 2947 snd_soc_component_write(component, reg, (band_idx * BAND_MAX * 2948 sizeof(uint32_t)) & 0x7F); 2949 2950 set_iir_band_coeff(component, iir_idx, band_idx, coeff[0]); 2951 set_iir_band_coeff(component, iir_idx, band_idx, coeff[1]); 2952 set_iir_band_coeff(component, iir_idx, band_idx, coeff[2]); 2953 set_iir_band_coeff(component, iir_idx, band_idx, coeff[3]); 2954 set_iir_band_coeff(component, iir_idx, band_idx, coeff[4]); 2955 2956 return 0; 2957 } 2958 2959 static int rx_macro_get_iir_band_audio_mixer(struct snd_kcontrol *kcontrol, 2960 struct snd_ctl_elem_value *ucontrol) 2961 { 2962 struct snd_soc_component *component = 2963 snd_soc_kcontrol_component(kcontrol); 2964 struct wcd_iir_filter_ctl *ctl = 2965 (struct wcd_iir_filter_ctl *)kcontrol->private_value; 2966 struct soc_bytes_ext *params = &ctl->bytes_ext; 2967 int iir_idx = ctl->iir_idx; 2968 int band_idx = ctl->band_idx; 2969 u32 coeff[BAND_MAX]; 2970 2971 coeff[0] = get_iir_band_coeff(component, iir_idx, band_idx, 0); 2972 coeff[1] = get_iir_band_coeff(component, iir_idx, band_idx, 1); 2973 coeff[2] = get_iir_band_coeff(component, iir_idx, band_idx, 2); 2974 coeff[3] = get_iir_band_coeff(component, iir_idx, band_idx, 3); 2975 coeff[4] = get_iir_band_coeff(component, iir_idx, band_idx, 4); 2976 2977 memcpy(ucontrol->value.bytes.data, &coeff[0], params->max); 2978 2979 return 0; 2980 } 2981 2982 static int rx_macro_iir_filter_info(struct snd_kcontrol *kcontrol, 2983 struct snd_ctl_elem_info *ucontrol) 2984 { 2985 struct wcd_iir_filter_ctl *ctl = 2986 (struct wcd_iir_filter_ctl *)kcontrol->private_value; 2987 struct soc_bytes_ext *params = &ctl->bytes_ext; 2988 2989 ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES; 2990 ucontrol->count = params->max; 2991 2992 return 0; 2993 } 2994 2995 static const struct snd_kcontrol_new rx_macro_def_snd_controls[] = { 2996 SOC_SINGLE_S8_TLV("RX_RX1 Digital Volume", CDC_RX_RX1_RX_VOL_CTL, 2997 -84, 40, digital_gain), 2998 SOC_SINGLE_S8_TLV("RX_RX2 Digital Volume", CDC_RX_RX2_RX_VOL_CTL, 2999 -84, 40, digital_gain), 3000 SOC_SINGLE_S8_TLV("RX_RX1 Mix Digital Volume", CDC_RX_RX1_RX_VOL_MIX_CTL, 3001 -84, 40, digital_gain), 3002 SOC_SINGLE_S8_TLV("RX_RX2 Mix Digital Volume", CDC_RX_RX2_RX_VOL_MIX_CTL, 3003 -84, 40, digital_gain), 3004 }; 3005 3006 static const struct snd_kcontrol_new rx_macro_2_5_snd_controls[] = { 3007 3008 SOC_SINGLE_S8_TLV("RX_RX1 Digital Volume", CDC_2_5_RX_RX1_RX_VOL_CTL, 3009 -84, 40, digital_gain), 3010 SOC_SINGLE_S8_TLV("RX_RX2 Digital Volume", CDC_2_5_RX_RX2_RX_VOL_CTL, 3011 -84, 40, digital_gain), 3012 SOC_SINGLE_S8_TLV("RX_RX1 Mix Digital Volume", CDC_2_5_RX_RX1_RX_VOL_MIX_CTL, 3013 -84, 40, digital_gain), 3014 SOC_SINGLE_S8_TLV("RX_RX2 Mix Digital Volume", CDC_2_5_RX_RX2_RX_VOL_MIX_CTL, 3015 -84, 40, digital_gain), 3016 }; 3017 3018 static const struct snd_kcontrol_new rx_macro_snd_controls[] = { 3019 SOC_SINGLE_S8_TLV("RX_RX0 Digital Volume", CDC_RX_RX0_RX_VOL_CTL, 3020 -84, 40, digital_gain), 3021 SOC_SINGLE_S8_TLV("RX_RX0 Mix Digital Volume", CDC_RX_RX0_RX_VOL_MIX_CTL, 3022 -84, 40, digital_gain), 3023 SOC_SINGLE_EXT("RX_COMP1 Switch", SND_SOC_NOPM, RX_MACRO_COMP1, 1, 0, 3024 rx_macro_get_compander, rx_macro_set_compander), 3025 SOC_SINGLE_EXT("RX_COMP2 Switch", SND_SOC_NOPM, RX_MACRO_COMP2, 1, 0, 3026 rx_macro_get_compander, rx_macro_set_compander), 3027 3028 SOC_SINGLE_EXT("RX_EAR Mode Switch", SND_SOC_NOPM, 0, 1, 0, 3029 rx_macro_get_ear_mode, rx_macro_put_ear_mode), 3030 3031 SOC_SINGLE_EXT("RX_HPH HD2 Mode Switch", SND_SOC_NOPM, 0, 1, 0, 3032 rx_macro_get_hph_hd2_mode, rx_macro_put_hph_hd2_mode), 3033 3034 SOC_ENUM_EXT("RX_HPH PWR Mode", rx_macro_hph_pwr_mode_enum, 3035 rx_macro_get_hph_pwr_mode, rx_macro_put_hph_pwr_mode), 3036 3037 SOC_SINGLE_EXT("RX_Softclip Switch", SND_SOC_NOPM, 0, 1, 0, 3038 rx_macro_soft_clip_enable_get, 3039 rx_macro_soft_clip_enable_put), 3040 SOC_SINGLE_EXT("AUX_HPF Switch", SND_SOC_NOPM, 0, 1, 0, 3041 rx_macro_aux_hpf_mode_get, 3042 rx_macro_aux_hpf_mode_put), 3043 3044 SOC_SINGLE_S8_TLV("IIR0 INP0 Volume", 3045 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL, -84, 40, 3046 digital_gain), 3047 SOC_SINGLE_S8_TLV("IIR0 INP1 Volume", 3048 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL, -84, 40, 3049 digital_gain), 3050 SOC_SINGLE_S8_TLV("IIR0 INP2 Volume", 3051 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL, -84, 40, 3052 digital_gain), 3053 SOC_SINGLE_S8_TLV("IIR0 INP3 Volume", 3054 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL, -84, 40, 3055 digital_gain), 3056 SOC_SINGLE_S8_TLV("IIR1 INP0 Volume", 3057 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL, -84, 40, 3058 digital_gain), 3059 SOC_SINGLE_S8_TLV("IIR1 INP1 Volume", 3060 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL, -84, 40, 3061 digital_gain), 3062 SOC_SINGLE_S8_TLV("IIR1 INP2 Volume", 3063 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL, -84, 40, 3064 digital_gain), 3065 SOC_SINGLE_S8_TLV("IIR1 INP3 Volume", 3066 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL, -84, 40, 3067 digital_gain), 3068 3069 SOC_SINGLE("IIR1 Band1 Switch", CDC_RX_SIDETONE_IIR0_IIR_CTL, 3070 0, 1, 0), 3071 SOC_SINGLE("IIR1 Band2 Switch", CDC_RX_SIDETONE_IIR0_IIR_CTL, 3072 1, 1, 0), 3073 SOC_SINGLE("IIR1 Band3 Switch", CDC_RX_SIDETONE_IIR0_IIR_CTL, 3074 2, 1, 0), 3075 SOC_SINGLE("IIR1 Band4 Switch", CDC_RX_SIDETONE_IIR0_IIR_CTL, 3076 3, 1, 0), 3077 SOC_SINGLE("IIR1 Band5 Switch", CDC_RX_SIDETONE_IIR0_IIR_CTL, 3078 4, 1, 0), 3079 SOC_SINGLE("IIR2 Band1 Switch", CDC_RX_SIDETONE_IIR1_IIR_CTL, 3080 0, 1, 0), 3081 SOC_SINGLE("IIR2 Band2 Switch", CDC_RX_SIDETONE_IIR1_IIR_CTL, 3082 1, 1, 0), 3083 SOC_SINGLE("IIR2 Band3 Switch", CDC_RX_SIDETONE_IIR1_IIR_CTL, 3084 2, 1, 0), 3085 SOC_SINGLE("IIR2 Band4 Switch", CDC_RX_SIDETONE_IIR1_IIR_CTL, 3086 3, 1, 0), 3087 SOC_SINGLE("IIR2 Band5 Switch", CDC_RX_SIDETONE_IIR1_IIR_CTL, 3088 4, 1, 0), 3089 3090 RX_MACRO_IIR_FILTER_CTL("IIR0 Band1", IIR0, BAND1), 3091 RX_MACRO_IIR_FILTER_CTL("IIR0 Band2", IIR0, BAND2), 3092 RX_MACRO_IIR_FILTER_CTL("IIR0 Band3", IIR0, BAND3), 3093 RX_MACRO_IIR_FILTER_CTL("IIR0 Band4", IIR0, BAND4), 3094 RX_MACRO_IIR_FILTER_CTL("IIR0 Band5", IIR0, BAND5), 3095 3096 RX_MACRO_IIR_FILTER_CTL("IIR1 Band1", IIR1, BAND1), 3097 RX_MACRO_IIR_FILTER_CTL("IIR1 Band2", IIR1, BAND2), 3098 RX_MACRO_IIR_FILTER_CTL("IIR1 Band3", IIR1, BAND3), 3099 RX_MACRO_IIR_FILTER_CTL("IIR1 Band4", IIR1, BAND4), 3100 RX_MACRO_IIR_FILTER_CTL("IIR1 Band5", IIR1, BAND5), 3101 3102 }; 3103 3104 static int rx_macro_enable_echo(struct snd_soc_dapm_widget *w, 3105 struct snd_kcontrol *kcontrol, 3106 int event) 3107 { 3108 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 3109 u16 val, ec_hq_reg; 3110 int ec_tx = -1; 3111 3112 val = snd_soc_component_read(component, 3113 CDC_RX_INP_MUX_RX_MIX_CFG4); 3114 if (!(snd_soc_dapm_widget_name_cmp(w, "RX MIX TX0 MUX"))) 3115 ec_tx = ((val & 0xf0) >> 0x4) - 1; 3116 else if (!(snd_soc_dapm_widget_name_cmp(w, "RX MIX TX1 MUX"))) 3117 ec_tx = (val & 0x0f) - 1; 3118 3119 val = snd_soc_component_read(component, 3120 CDC_RX_INP_MUX_RX_MIX_CFG5); 3121 if (!(snd_soc_dapm_widget_name_cmp(w, "RX MIX TX2 MUX"))) 3122 ec_tx = (val & 0x0f) - 1; 3123 3124 if (ec_tx < 0 || (ec_tx >= RX_MACRO_EC_MUX_MAX)) { 3125 dev_err(component->dev, "%s: EC mix control not set correctly\n", 3126 __func__); 3127 return -EINVAL; 3128 } 3129 ec_hq_reg = CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL + 3130 0x40 * ec_tx; 3131 snd_soc_component_update_bits(component, ec_hq_reg, 0x01, 0x01); 3132 ec_hq_reg = CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0 + 3133 0x40 * ec_tx; 3134 /* default set to 48k */ 3135 snd_soc_component_update_bits(component, ec_hq_reg, 0x1E, 0x08); 3136 3137 return 0; 3138 } 3139 3140 static const struct snd_soc_dapm_widget rx_macro_2_5_dapm_widgets[] = { 3141 SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0, 3142 &rx_2_5_int1_dem_inp_mux), 3143 }; 3144 3145 static const struct snd_soc_dapm_widget rx_macro_def_dapm_widgets[] = { 3146 SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0, 3147 &rx_int1_dem_inp_mux), 3148 }; 3149 3150 static const struct snd_soc_dapm_widget rx_macro_dapm_widgets[] = { 3151 SND_SOC_DAPM_AIF_IN("RX AIF1 PB", "RX_MACRO_AIF1 Playback", 0, 3152 SND_SOC_NOPM, 0, 0), 3153 3154 SND_SOC_DAPM_AIF_IN("RX AIF2 PB", "RX_MACRO_AIF2 Playback", 0, 3155 SND_SOC_NOPM, 0, 0), 3156 3157 SND_SOC_DAPM_AIF_IN("RX AIF3 PB", "RX_MACRO_AIF3 Playback", 0, 3158 SND_SOC_NOPM, 0, 0), 3159 3160 SND_SOC_DAPM_AIF_IN("RX AIF4 PB", "RX_MACRO_AIF4 Playback", 0, 3161 SND_SOC_NOPM, 0, 0), 3162 3163 SND_SOC_DAPM_AIF_OUT("RX AIF_ECHO", "RX_AIF_ECHO Capture", 0, 3164 SND_SOC_NOPM, 0, 0), 3165 3166 SND_SOC_DAPM_MUX("RX_MACRO RX0 MUX", SND_SOC_NOPM, RX_MACRO_RX0, 0, 3167 &rx_macro_rx0_mux), 3168 SND_SOC_DAPM_MUX("RX_MACRO RX1 MUX", SND_SOC_NOPM, RX_MACRO_RX1, 0, 3169 &rx_macro_rx1_mux), 3170 SND_SOC_DAPM_MUX("RX_MACRO RX2 MUX", SND_SOC_NOPM, RX_MACRO_RX2, 0, 3171 &rx_macro_rx2_mux), 3172 SND_SOC_DAPM_MUX("RX_MACRO RX3 MUX", SND_SOC_NOPM, RX_MACRO_RX3, 0, 3173 &rx_macro_rx3_mux), 3174 SND_SOC_DAPM_MUX("RX_MACRO RX4 MUX", SND_SOC_NOPM, RX_MACRO_RX4, 0, 3175 &rx_macro_rx4_mux), 3176 SND_SOC_DAPM_MUX("RX_MACRO RX5 MUX", SND_SOC_NOPM, RX_MACRO_RX5, 0, 3177 &rx_macro_rx5_mux), 3178 3179 SND_SOC_DAPM_MIXER("RX_RX0", SND_SOC_NOPM, 0, 0, NULL, 0), 3180 SND_SOC_DAPM_MIXER("RX_RX1", SND_SOC_NOPM, 0, 0, NULL, 0), 3181 SND_SOC_DAPM_MIXER("RX_RX2", SND_SOC_NOPM, 0, 0, NULL, 0), 3182 SND_SOC_DAPM_MIXER("RX_RX3", SND_SOC_NOPM, 0, 0, NULL, 0), 3183 SND_SOC_DAPM_MIXER("RX_RX4", SND_SOC_NOPM, 0, 0, NULL, 0), 3184 SND_SOC_DAPM_MIXER("RX_RX5", SND_SOC_NOPM, 0, 0, NULL, 0), 3185 3186 SND_SOC_DAPM_MUX("IIR0 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp0_mux), 3187 SND_SOC_DAPM_MUX("IIR0 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp1_mux), 3188 SND_SOC_DAPM_MUX("IIR0 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp2_mux), 3189 SND_SOC_DAPM_MUX("IIR0 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp3_mux), 3190 SND_SOC_DAPM_MUX("IIR1 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp0_mux), 3191 SND_SOC_DAPM_MUX("IIR1 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp1_mux), 3192 SND_SOC_DAPM_MUX("IIR1 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp2_mux), 3193 SND_SOC_DAPM_MUX("IIR1 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp3_mux), 3194 3195 SND_SOC_DAPM_MUX_E("RX MIX TX0 MUX", SND_SOC_NOPM, 3196 RX_MACRO_EC0_MUX, 0, 3197 &rx_mix_tx0_mux, rx_macro_enable_echo, 3198 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3199 SND_SOC_DAPM_MUX_E("RX MIX TX1 MUX", SND_SOC_NOPM, 3200 RX_MACRO_EC1_MUX, 0, 3201 &rx_mix_tx1_mux, rx_macro_enable_echo, 3202 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3203 SND_SOC_DAPM_MUX_E("RX MIX TX2 MUX", SND_SOC_NOPM, 3204 RX_MACRO_EC2_MUX, 0, 3205 &rx_mix_tx2_mux, rx_macro_enable_echo, 3206 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3207 3208 SND_SOC_DAPM_MIXER_E("IIR0", CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL, 3209 4, 0, NULL, 0, rx_macro_set_iir_gain, 3210 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 3211 SND_SOC_DAPM_MIXER_E("IIR1", CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL, 3212 4, 0, NULL, 0, rx_macro_set_iir_gain, 3213 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 3214 SND_SOC_DAPM_MIXER("SRC0", CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL, 3215 4, 0, NULL, 0), 3216 SND_SOC_DAPM_MIXER("SRC1", CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL, 3217 4, 0, NULL, 0), 3218 3219 SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0, 3220 &rx_int0_dem_inp_mux), 3221 3222 SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", SND_SOC_NOPM, INTERP_HPHL, 0, 3223 &rx_int0_2_mux, rx_macro_enable_mix_path, 3224 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3225 SND_SOC_DAPM_POST_PMD), 3226 SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", SND_SOC_NOPM, INTERP_HPHR, 0, 3227 &rx_int1_2_mux, rx_macro_enable_mix_path, 3228 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3229 SND_SOC_DAPM_POST_PMD), 3230 SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", SND_SOC_NOPM, INTERP_AUX, 0, 3231 &rx_int2_2_mux, rx_macro_enable_mix_path, 3232 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3233 SND_SOC_DAPM_POST_PMD), 3234 3235 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, &rx_int0_1_mix_inp0_mux), 3236 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, &rx_int0_1_mix_inp1_mux), 3237 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, &rx_int0_1_mix_inp2_mux), 3238 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, &rx_int1_1_mix_inp0_mux), 3239 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, &rx_int1_1_mix_inp1_mux), 3240 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, &rx_int1_1_mix_inp2_mux), 3241 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, &rx_int2_1_mix_inp0_mux), 3242 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, &rx_int2_1_mix_inp1_mux), 3243 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, &rx_int2_1_mix_inp2_mux), 3244 3245 SND_SOC_DAPM_MUX_E("RX INT0_1 INTERP", SND_SOC_NOPM, INTERP_HPHL, 0, 3246 &rx_int0_1_interp_mux, rx_macro_enable_main_path, 3247 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3248 SND_SOC_DAPM_POST_PMD), 3249 SND_SOC_DAPM_MUX_E("RX INT1_1 INTERP", SND_SOC_NOPM, INTERP_HPHR, 0, 3250 &rx_int1_1_interp_mux, rx_macro_enable_main_path, 3251 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3252 SND_SOC_DAPM_POST_PMD), 3253 SND_SOC_DAPM_MUX_E("RX INT2_1 INTERP", SND_SOC_NOPM, INTERP_AUX, 0, 3254 &rx_int2_1_interp_mux, rx_macro_enable_main_path, 3255 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 3256 SND_SOC_DAPM_POST_PMD), 3257 3258 SND_SOC_DAPM_MUX("RX INT0_2 INTERP", SND_SOC_NOPM, 0, 0, 3259 &rx_int0_2_interp_mux), 3260 SND_SOC_DAPM_MUX("RX INT1_2 INTERP", SND_SOC_NOPM, 0, 0, 3261 &rx_int1_2_interp_mux), 3262 SND_SOC_DAPM_MUX("RX INT2_2 INTERP", SND_SOC_NOPM, 0, 0, 3263 &rx_int2_2_interp_mux), 3264 3265 SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 3266 SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 3267 SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 3268 SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 3269 SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 3270 SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 3271 3272 SND_SOC_DAPM_MUX_E("RX INT0 MIX2 INP", SND_SOC_NOPM, INTERP_HPHL, 3273 0, &rx_int0_mix2_inp_mux, rx_macro_enable_rx_path_clk, 3274 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3275 SND_SOC_DAPM_MUX_E("RX INT1 MIX2 INP", SND_SOC_NOPM, INTERP_HPHR, 3276 0, &rx_int1_mix2_inp_mux, rx_macro_enable_rx_path_clk, 3277 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3278 SND_SOC_DAPM_MUX_E("RX INT2 MIX2 INP", SND_SOC_NOPM, INTERP_AUX, 3279 0, &rx_int2_mix2_inp_mux, rx_macro_enable_rx_path_clk, 3280 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3281 3282 SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 3283 SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 3284 SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), 3285 3286 SND_SOC_DAPM_OUTPUT("HPHL_OUT"), 3287 SND_SOC_DAPM_OUTPUT("HPHR_OUT"), 3288 SND_SOC_DAPM_OUTPUT("AUX_OUT"), 3289 3290 SND_SOC_DAPM_INPUT("RX_TX DEC0_INP"), 3291 SND_SOC_DAPM_INPUT("RX_TX DEC1_INP"), 3292 SND_SOC_DAPM_INPUT("RX_TX DEC2_INP"), 3293 SND_SOC_DAPM_INPUT("RX_TX DEC3_INP"), 3294 3295 SND_SOC_DAPM_SUPPLY_S("RX_MCLK", 0, SND_SOC_NOPM, 0, 0, 3296 rx_macro_mclk_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 3297 }; 3298 3299 static const struct snd_soc_dapm_route rx_audio_map[] = { 3300 {"RX AIF1 PB", NULL, "RX_MCLK"}, 3301 {"RX AIF2 PB", NULL, "RX_MCLK"}, 3302 {"RX AIF3 PB", NULL, "RX_MCLK"}, 3303 {"RX AIF4 PB", NULL, "RX_MCLK"}, 3304 3305 {"RX_MACRO RX0 MUX", "AIF1_PB", "RX AIF1 PB"}, 3306 {"RX_MACRO RX1 MUX", "AIF1_PB", "RX AIF1 PB"}, 3307 {"RX_MACRO RX2 MUX", "AIF1_PB", "RX AIF1 PB"}, 3308 {"RX_MACRO RX3 MUX", "AIF1_PB", "RX AIF1 PB"}, 3309 {"RX_MACRO RX4 MUX", "AIF1_PB", "RX AIF1 PB"}, 3310 {"RX_MACRO RX5 MUX", "AIF1_PB", "RX AIF1 PB"}, 3311 3312 {"RX_MACRO RX0 MUX", "AIF2_PB", "RX AIF2 PB"}, 3313 {"RX_MACRO RX1 MUX", "AIF2_PB", "RX AIF2 PB"}, 3314 {"RX_MACRO RX2 MUX", "AIF2_PB", "RX AIF2 PB"}, 3315 {"RX_MACRO RX3 MUX", "AIF2_PB", "RX AIF2 PB"}, 3316 {"RX_MACRO RX4 MUX", "AIF2_PB", "RX AIF2 PB"}, 3317 {"RX_MACRO RX5 MUX", "AIF2_PB", "RX AIF2 PB"}, 3318 3319 {"RX_MACRO RX0 MUX", "AIF3_PB", "RX AIF3 PB"}, 3320 {"RX_MACRO RX1 MUX", "AIF3_PB", "RX AIF3 PB"}, 3321 {"RX_MACRO RX2 MUX", "AIF3_PB", "RX AIF3 PB"}, 3322 {"RX_MACRO RX3 MUX", "AIF3_PB", "RX AIF3 PB"}, 3323 {"RX_MACRO RX4 MUX", "AIF3_PB", "RX AIF3 PB"}, 3324 {"RX_MACRO RX5 MUX", "AIF3_PB", "RX AIF3 PB"}, 3325 3326 {"RX_MACRO RX0 MUX", "AIF4_PB", "RX AIF4 PB"}, 3327 {"RX_MACRO RX1 MUX", "AIF4_PB", "RX AIF4 PB"}, 3328 {"RX_MACRO RX2 MUX", "AIF4_PB", "RX AIF4 PB"}, 3329 {"RX_MACRO RX3 MUX", "AIF4_PB", "RX AIF4 PB"}, 3330 {"RX_MACRO RX4 MUX", "AIF4_PB", "RX AIF4 PB"}, 3331 {"RX_MACRO RX5 MUX", "AIF4_PB", "RX AIF4 PB"}, 3332 3333 {"RX_RX0", NULL, "RX_MACRO RX0 MUX"}, 3334 {"RX_RX1", NULL, "RX_MACRO RX1 MUX"}, 3335 {"RX_RX2", NULL, "RX_MACRO RX2 MUX"}, 3336 {"RX_RX3", NULL, "RX_MACRO RX3 MUX"}, 3337 {"RX_RX4", NULL, "RX_MACRO RX4 MUX"}, 3338 {"RX_RX5", NULL, "RX_MACRO RX5 MUX"}, 3339 3340 {"RX INT0_1 MIX1 INP0", "RX0", "RX_RX0"}, 3341 {"RX INT0_1 MIX1 INP0", "RX1", "RX_RX1"}, 3342 {"RX INT0_1 MIX1 INP0", "RX2", "RX_RX2"}, 3343 {"RX INT0_1 MIX1 INP0", "RX3", "RX_RX3"}, 3344 {"RX INT0_1 MIX1 INP0", "RX4", "RX_RX4"}, 3345 {"RX INT0_1 MIX1 INP0", "RX5", "RX_RX5"}, 3346 {"RX INT0_1 MIX1 INP0", "IIR0", "IIR0"}, 3347 {"RX INT0_1 MIX1 INP0", "IIR1", "IIR1"}, 3348 {"RX INT0_1 MIX1 INP0", "DEC0", "RX_TX DEC0_INP"}, 3349 {"RX INT0_1 MIX1 INP0", "DEC1", "RX_TX DEC1_INP"}, 3350 {"RX INT0_1 MIX1 INP1", "RX0", "RX_RX0"}, 3351 {"RX INT0_1 MIX1 INP1", "RX1", "RX_RX1"}, 3352 {"RX INT0_1 MIX1 INP1", "RX2", "RX_RX2"}, 3353 {"RX INT0_1 MIX1 INP1", "RX3", "RX_RX3"}, 3354 {"RX INT0_1 MIX1 INP1", "RX4", "RX_RX4"}, 3355 {"RX INT0_1 MIX1 INP1", "RX5", "RX_RX5"}, 3356 {"RX INT0_1 MIX1 INP1", "IIR0", "IIR0"}, 3357 {"RX INT0_1 MIX1 INP1", "IIR1", "IIR1"}, 3358 {"RX INT0_1 MIX1 INP1", "DEC0", "RX_TX DEC0_INP"}, 3359 {"RX INT0_1 MIX1 INP1", "DEC1", "RX_TX DEC1_INP"}, 3360 {"RX INT0_1 MIX1 INP2", "RX0", "RX_RX0"}, 3361 {"RX INT0_1 MIX1 INP2", "RX1", "RX_RX1"}, 3362 {"RX INT0_1 MIX1 INP2", "RX2", "RX_RX2"}, 3363 {"RX INT0_1 MIX1 INP2", "RX3", "RX_RX3"}, 3364 {"RX INT0_1 MIX1 INP2", "RX4", "RX_RX4"}, 3365 {"RX INT0_1 MIX1 INP2", "RX5", "RX_RX5"}, 3366 {"RX INT0_1 MIX1 INP2", "IIR0", "IIR0"}, 3367 {"RX INT0_1 MIX1 INP2", "IIR1", "IIR1"}, 3368 {"RX INT0_1 MIX1 INP2", "DEC0", "RX_TX DEC0_INP"}, 3369 {"RX INT0_1 MIX1 INP2", "DEC1", "RX_TX DEC1_INP"}, 3370 3371 {"RX INT1_1 MIX1 INP0", "RX0", "RX_RX0"}, 3372 {"RX INT1_1 MIX1 INP0", "RX1", "RX_RX1"}, 3373 {"RX INT1_1 MIX1 INP0", "RX2", "RX_RX2"}, 3374 {"RX INT1_1 MIX1 INP0", "RX3", "RX_RX3"}, 3375 {"RX INT1_1 MIX1 INP0", "RX4", "RX_RX4"}, 3376 {"RX INT1_1 MIX1 INP0", "RX5", "RX_RX5"}, 3377 {"RX INT1_1 MIX1 INP0", "IIR0", "IIR0"}, 3378 {"RX INT1_1 MIX1 INP0", "IIR1", "IIR1"}, 3379 {"RX INT1_1 MIX1 INP0", "DEC0", "RX_TX DEC0_INP"}, 3380 {"RX INT1_1 MIX1 INP0", "DEC1", "RX_TX DEC1_INP"}, 3381 {"RX INT1_1 MIX1 INP1", "RX0", "RX_RX0"}, 3382 {"RX INT1_1 MIX1 INP1", "RX1", "RX_RX1"}, 3383 {"RX INT1_1 MIX1 INP1", "RX2", "RX_RX2"}, 3384 {"RX INT1_1 MIX1 INP1", "RX3", "RX_RX3"}, 3385 {"RX INT1_1 MIX1 INP1", "RX4", "RX_RX4"}, 3386 {"RX INT1_1 MIX1 INP1", "RX5", "RX_RX5"}, 3387 {"RX INT1_1 MIX1 INP1", "IIR0", "IIR0"}, 3388 {"RX INT1_1 MIX1 INP1", "IIR1", "IIR1"}, 3389 {"RX INT1_1 MIX1 INP1", "DEC0", "RX_TX DEC0_INP"}, 3390 {"RX INT1_1 MIX1 INP1", "DEC1", "RX_TX DEC1_INP"}, 3391 {"RX INT1_1 MIX1 INP2", "RX0", "RX_RX0"}, 3392 {"RX INT1_1 MIX1 INP2", "RX1", "RX_RX1"}, 3393 {"RX INT1_1 MIX1 INP2", "RX2", "RX_RX2"}, 3394 {"RX INT1_1 MIX1 INP2", "RX3", "RX_RX3"}, 3395 {"RX INT1_1 MIX1 INP2", "RX4", "RX_RX4"}, 3396 {"RX INT1_1 MIX1 INP2", "RX5", "RX_RX5"}, 3397 {"RX INT1_1 MIX1 INP2", "IIR0", "IIR0"}, 3398 {"RX INT1_1 MIX1 INP2", "IIR1", "IIR1"}, 3399 {"RX INT1_1 MIX1 INP2", "DEC0", "RX_TX DEC0_INP"}, 3400 {"RX INT1_1 MIX1 INP2", "DEC1", "RX_TX DEC1_INP"}, 3401 3402 {"RX INT2_1 MIX1 INP0", "RX0", "RX_RX0"}, 3403 {"RX INT2_1 MIX1 INP0", "RX1", "RX_RX1"}, 3404 {"RX INT2_1 MIX1 INP0", "RX2", "RX_RX2"}, 3405 {"RX INT2_1 MIX1 INP0", "RX3", "RX_RX3"}, 3406 {"RX INT2_1 MIX1 INP0", "RX4", "RX_RX4"}, 3407 {"RX INT2_1 MIX1 INP0", "RX5", "RX_RX5"}, 3408 {"RX INT2_1 MIX1 INP0", "IIR0", "IIR0"}, 3409 {"RX INT2_1 MIX1 INP0", "IIR1", "IIR1"}, 3410 {"RX INT2_1 MIX1 INP0", "DEC0", "RX_TX DEC0_INP"}, 3411 {"RX INT2_1 MIX1 INP0", "DEC1", "RX_TX DEC1_INP"}, 3412 {"RX INT2_1 MIX1 INP1", "RX0", "RX_RX0"}, 3413 {"RX INT2_1 MIX1 INP1", "RX1", "RX_RX1"}, 3414 {"RX INT2_1 MIX1 INP1", "RX2", "RX_RX2"}, 3415 {"RX INT2_1 MIX1 INP1", "RX3", "RX_RX3"}, 3416 {"RX INT2_1 MIX1 INP1", "RX4", "RX_RX4"}, 3417 {"RX INT2_1 MIX1 INP1", "RX5", "RX_RX5"}, 3418 {"RX INT2_1 MIX1 INP1", "IIR0", "IIR0"}, 3419 {"RX INT2_1 MIX1 INP1", "IIR1", "IIR1"}, 3420 {"RX INT2_1 MIX1 INP1", "DEC0", "RX_TX DEC0_INP"}, 3421 {"RX INT2_1 MIX1 INP1", "DEC1", "RX_TX DEC1_INP"}, 3422 {"RX INT2_1 MIX1 INP2", "RX0", "RX_RX0"}, 3423 {"RX INT2_1 MIX1 INP2", "RX1", "RX_RX1"}, 3424 {"RX INT2_1 MIX1 INP2", "RX2", "RX_RX2"}, 3425 {"RX INT2_1 MIX1 INP2", "RX3", "RX_RX3"}, 3426 {"RX INT2_1 MIX1 INP2", "RX4", "RX_RX4"}, 3427 {"RX INT2_1 MIX1 INP2", "RX5", "RX_RX5"}, 3428 {"RX INT2_1 MIX1 INP2", "IIR0", "IIR0"}, 3429 {"RX INT2_1 MIX1 INP2", "IIR1", "IIR1"}, 3430 {"RX INT2_1 MIX1 INP2", "DEC0", "RX_TX DEC0_INP"}, 3431 {"RX INT2_1 MIX1 INP2", "DEC1", "RX_TX DEC1_INP"}, 3432 3433 {"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP0"}, 3434 {"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP1"}, 3435 {"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP2"}, 3436 {"RX INT1_1 MIX1", NULL, "RX INT1_1 MIX1 INP0"}, 3437 {"RX INT1_1 MIX1", NULL, "RX INT1_1 MIX1 INP1"}, 3438 {"RX INT1_1 MIX1", NULL, "RX INT1_1 MIX1 INP2"}, 3439 {"RX INT2_1 MIX1", NULL, "RX INT2_1 MIX1 INP0"}, 3440 {"RX INT2_1 MIX1", NULL, "RX INT2_1 MIX1 INP1"}, 3441 {"RX INT2_1 MIX1", NULL, "RX INT2_1 MIX1 INP2"}, 3442 3443 {"RX MIX TX0 MUX", "RX_MIX0", "RX INT0 SEC MIX"}, 3444 {"RX MIX TX0 MUX", "RX_MIX1", "RX INT1 SEC MIX"}, 3445 {"RX MIX TX0 MUX", "RX_MIX2", "RX INT2 SEC MIX"}, 3446 {"RX MIX TX1 MUX", "RX_MIX0", "RX INT0 SEC MIX"}, 3447 {"RX MIX TX1 MUX", "RX_MIX1", "RX INT1 SEC MIX"}, 3448 {"RX MIX TX1 MUX", "RX_MIX2", "RX INT2 SEC MIX"}, 3449 {"RX MIX TX2 MUX", "RX_MIX0", "RX INT0 SEC MIX"}, 3450 {"RX MIX TX2 MUX", "RX_MIX1", "RX INT1 SEC MIX"}, 3451 {"RX MIX TX2 MUX", "RX_MIX2", "RX INT2 SEC MIX"}, 3452 {"RX AIF_ECHO", NULL, "RX MIX TX0 MUX"}, 3453 {"RX AIF_ECHO", NULL, "RX MIX TX1 MUX"}, 3454 {"RX AIF_ECHO", NULL, "RX MIX TX2 MUX"}, 3455 {"RX AIF_ECHO", NULL, "RX_MCLK"}, 3456 3457 /* Mixing path INT0 */ 3458 {"RX INT0_2 MUX", "RX0", "RX_RX0"}, 3459 {"RX INT0_2 MUX", "RX1", "RX_RX1"}, 3460 {"RX INT0_2 MUX", "RX2", "RX_RX2"}, 3461 {"RX INT0_2 MUX", "RX3", "RX_RX3"}, 3462 {"RX INT0_2 MUX", "RX4", "RX_RX4"}, 3463 {"RX INT0_2 MUX", "RX5", "RX_RX5"}, 3464 {"RX INT0_2 INTERP", NULL, "RX INT0_2 MUX"}, 3465 {"RX INT0 SEC MIX", NULL, "RX INT0_2 INTERP"}, 3466 3467 /* Mixing path INT1 */ 3468 {"RX INT1_2 MUX", "RX0", "RX_RX0"}, 3469 {"RX INT1_2 MUX", "RX1", "RX_RX1"}, 3470 {"RX INT1_2 MUX", "RX2", "RX_RX2"}, 3471 {"RX INT1_2 MUX", "RX3", "RX_RX3"}, 3472 {"RX INT1_2 MUX", "RX4", "RX_RX4"}, 3473 {"RX INT1_2 MUX", "RX5", "RX_RX5"}, 3474 {"RX INT1_2 INTERP", NULL, "RX INT1_2 MUX"}, 3475 {"RX INT1 SEC MIX", NULL, "RX INT1_2 INTERP"}, 3476 3477 /* Mixing path INT2 */ 3478 {"RX INT2_2 MUX", "RX0", "RX_RX0"}, 3479 {"RX INT2_2 MUX", "RX1", "RX_RX1"}, 3480 {"RX INT2_2 MUX", "RX2", "RX_RX2"}, 3481 {"RX INT2_2 MUX", "RX3", "RX_RX3"}, 3482 {"RX INT2_2 MUX", "RX4", "RX_RX4"}, 3483 {"RX INT2_2 MUX", "RX5", "RX_RX5"}, 3484 {"RX INT2_2 INTERP", NULL, "RX INT2_2 MUX"}, 3485 {"RX INT2 SEC MIX", NULL, "RX INT2_2 INTERP"}, 3486 3487 {"RX INT0_1 INTERP", NULL, "RX INT0_1 MIX1"}, 3488 {"RX INT0 SEC MIX", NULL, "RX INT0_1 INTERP"}, 3489 {"RX INT0 MIX2", NULL, "RX INT0 SEC MIX"}, 3490 {"RX INT0 MIX2", NULL, "RX INT0 MIX2 INP"}, 3491 {"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 MIX2"}, 3492 {"HPHL_OUT", NULL, "RX INT0 DEM MUX"}, 3493 {"HPHL_OUT", NULL, "RX_MCLK"}, 3494 3495 {"RX INT1_1 INTERP", NULL, "RX INT1_1 MIX1"}, 3496 {"RX INT1 SEC MIX", NULL, "RX INT1_1 INTERP"}, 3497 {"RX INT1 MIX2", NULL, "RX INT1 SEC MIX"}, 3498 {"RX INT1 MIX2", NULL, "RX INT1 MIX2 INP"}, 3499 {"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 MIX2"}, 3500 {"HPHR_OUT", NULL, "RX INT1 DEM MUX"}, 3501 {"HPHR_OUT", NULL, "RX_MCLK"}, 3502 3503 {"RX INT2_1 INTERP", NULL, "RX INT2_1 MIX1"}, 3504 3505 {"RX INT2 SEC MIX", NULL, "RX INT2_1 INTERP"}, 3506 {"RX INT2 MIX2", NULL, "RX INT2 SEC MIX"}, 3507 {"RX INT2 MIX2", NULL, "RX INT2 MIX2 INP"}, 3508 {"AUX_OUT", NULL, "RX INT2 MIX2"}, 3509 {"AUX_OUT", NULL, "RX_MCLK"}, 3510 3511 {"IIR0", NULL, "RX_MCLK"}, 3512 {"IIR0", NULL, "IIR0 INP0 MUX"}, 3513 {"IIR0 INP0 MUX", "DEC0", "RX_TX DEC0_INP"}, 3514 {"IIR0 INP0 MUX", "DEC1", "RX_TX DEC1_INP"}, 3515 {"IIR0 INP0 MUX", "DEC2", "RX_TX DEC2_INP"}, 3516 {"IIR0 INP0 MUX", "DEC3", "RX_TX DEC3_INP"}, 3517 {"IIR0 INP0 MUX", "RX0", "RX_RX0"}, 3518 {"IIR0 INP0 MUX", "RX1", "RX_RX1"}, 3519 {"IIR0 INP0 MUX", "RX2", "RX_RX2"}, 3520 {"IIR0 INP0 MUX", "RX3", "RX_RX3"}, 3521 {"IIR0 INP0 MUX", "RX4", "RX_RX4"}, 3522 {"IIR0 INP0 MUX", "RX5", "RX_RX5"}, 3523 {"IIR0", NULL, "IIR0 INP1 MUX"}, 3524 {"IIR0 INP1 MUX", "DEC0", "RX_TX DEC0_INP"}, 3525 {"IIR0 INP1 MUX", "DEC1", "RX_TX DEC1_INP"}, 3526 {"IIR0 INP1 MUX", "DEC2", "RX_TX DEC2_INP"}, 3527 {"IIR0 INP1 MUX", "DEC3", "RX_TX DEC3_INP"}, 3528 {"IIR0 INP1 MUX", "RX0", "RX_RX0"}, 3529 {"IIR0 INP1 MUX", "RX1", "RX_RX1"}, 3530 {"IIR0 INP1 MUX", "RX2", "RX_RX2"}, 3531 {"IIR0 INP1 MUX", "RX3", "RX_RX3"}, 3532 {"IIR0 INP1 MUX", "RX4", "RX_RX4"}, 3533 {"IIR0 INP1 MUX", "RX5", "RX_RX5"}, 3534 {"IIR0", NULL, "IIR0 INP2 MUX"}, 3535 {"IIR0 INP2 MUX", "DEC0", "RX_TX DEC0_INP"}, 3536 {"IIR0 INP2 MUX", "DEC1", "RX_TX DEC1_INP"}, 3537 {"IIR0 INP2 MUX", "DEC2", "RX_TX DEC2_INP"}, 3538 {"IIR0 INP2 MUX", "DEC3", "RX_TX DEC3_INP"}, 3539 {"IIR0 INP2 MUX", "RX0", "RX_RX0"}, 3540 {"IIR0 INP2 MUX", "RX1", "RX_RX1"}, 3541 {"IIR0 INP2 MUX", "RX2", "RX_RX2"}, 3542 {"IIR0 INP2 MUX", "RX3", "RX_RX3"}, 3543 {"IIR0 INP2 MUX", "RX4", "RX_RX4"}, 3544 {"IIR0 INP2 MUX", "RX5", "RX_RX5"}, 3545 {"IIR0", NULL, "IIR0 INP3 MUX"}, 3546 {"IIR0 INP3 MUX", "DEC0", "RX_TX DEC0_INP"}, 3547 {"IIR0 INP3 MUX", "DEC1", "RX_TX DEC1_INP"}, 3548 {"IIR0 INP3 MUX", "DEC2", "RX_TX DEC2_INP"}, 3549 {"IIR0 INP3 MUX", "DEC3", "RX_TX DEC3_INP"}, 3550 {"IIR0 INP3 MUX", "RX0", "RX_RX0"}, 3551 {"IIR0 INP3 MUX", "RX1", "RX_RX1"}, 3552 {"IIR0 INP3 MUX", "RX2", "RX_RX2"}, 3553 {"IIR0 INP3 MUX", "RX3", "RX_RX3"}, 3554 {"IIR0 INP3 MUX", "RX4", "RX_RX4"}, 3555 {"IIR0 INP3 MUX", "RX5", "RX_RX5"}, 3556 3557 {"IIR1", NULL, "RX_MCLK"}, 3558 {"IIR1", NULL, "IIR1 INP0 MUX"}, 3559 {"IIR1 INP0 MUX", "DEC0", "RX_TX DEC0_INP"}, 3560 {"IIR1 INP0 MUX", "DEC1", "RX_TX DEC1_INP"}, 3561 {"IIR1 INP0 MUX", "DEC2", "RX_TX DEC2_INP"}, 3562 {"IIR1 INP0 MUX", "DEC3", "RX_TX DEC3_INP"}, 3563 {"IIR1 INP0 MUX", "RX0", "RX_RX0"}, 3564 {"IIR1 INP0 MUX", "RX1", "RX_RX1"}, 3565 {"IIR1 INP0 MUX", "RX2", "RX_RX2"}, 3566 {"IIR1 INP0 MUX", "RX3", "RX_RX3"}, 3567 {"IIR1 INP0 MUX", "RX4", "RX_RX4"}, 3568 {"IIR1 INP0 MUX", "RX5", "RX_RX5"}, 3569 {"IIR1", NULL, "IIR1 INP1 MUX"}, 3570 {"IIR1 INP1 MUX", "DEC0", "RX_TX DEC0_INP"}, 3571 {"IIR1 INP1 MUX", "DEC1", "RX_TX DEC1_INP"}, 3572 {"IIR1 INP1 MUX", "DEC2", "RX_TX DEC2_INP"}, 3573 {"IIR1 INP1 MUX", "DEC3", "RX_TX DEC3_INP"}, 3574 {"IIR1 INP1 MUX", "RX0", "RX_RX0"}, 3575 {"IIR1 INP1 MUX", "RX1", "RX_RX1"}, 3576 {"IIR1 INP1 MUX", "RX2", "RX_RX2"}, 3577 {"IIR1 INP1 MUX", "RX3", "RX_RX3"}, 3578 {"IIR1 INP1 MUX", "RX4", "RX_RX4"}, 3579 {"IIR1 INP1 MUX", "RX5", "RX_RX5"}, 3580 {"IIR1", NULL, "IIR1 INP2 MUX"}, 3581 {"IIR1 INP2 MUX", "DEC0", "RX_TX DEC0_INP"}, 3582 {"IIR1 INP2 MUX", "DEC1", "RX_TX DEC1_INP"}, 3583 {"IIR1 INP2 MUX", "DEC2", "RX_TX DEC2_INP"}, 3584 {"IIR1 INP2 MUX", "DEC3", "RX_TX DEC3_INP"}, 3585 {"IIR1 INP2 MUX", "RX0", "RX_RX0"}, 3586 {"IIR1 INP2 MUX", "RX1", "RX_RX1"}, 3587 {"IIR1 INP2 MUX", "RX2", "RX_RX2"}, 3588 {"IIR1 INP2 MUX", "RX3", "RX_RX3"}, 3589 {"IIR1 INP2 MUX", "RX4", "RX_RX4"}, 3590 {"IIR1 INP2 MUX", "RX5", "RX_RX5"}, 3591 {"IIR1", NULL, "IIR1 INP3 MUX"}, 3592 {"IIR1 INP3 MUX", "DEC0", "RX_TX DEC0_INP"}, 3593 {"IIR1 INP3 MUX", "DEC1", "RX_TX DEC1_INP"}, 3594 {"IIR1 INP3 MUX", "DEC2", "RX_TX DEC2_INP"}, 3595 {"IIR1 INP3 MUX", "DEC3", "RX_TX DEC3_INP"}, 3596 {"IIR1 INP3 MUX", "RX0", "RX_RX0"}, 3597 {"IIR1 INP3 MUX", "RX1", "RX_RX1"}, 3598 {"IIR1 INP3 MUX", "RX2", "RX_RX2"}, 3599 {"IIR1 INP3 MUX", "RX3", "RX_RX3"}, 3600 {"IIR1 INP3 MUX", "RX4", "RX_RX4"}, 3601 {"IIR1 INP3 MUX", "RX5", "RX_RX5"}, 3602 3603 {"SRC0", NULL, "IIR0"}, 3604 {"SRC1", NULL, "IIR1"}, 3605 {"RX INT0 MIX2 INP", "SRC0", "SRC0"}, 3606 {"RX INT0 MIX2 INP", "SRC1", "SRC1"}, 3607 {"RX INT1 MIX2 INP", "SRC0", "SRC0"}, 3608 {"RX INT1 MIX2 INP", "SRC1", "SRC1"}, 3609 {"RX INT2 MIX2 INP", "SRC0", "SRC0"}, 3610 {"RX INT2 MIX2 INP", "SRC1", "SRC1"}, 3611 }; 3612 3613 static int rx_macro_component_probe(struct snd_soc_component *component) 3614 { 3615 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 3616 struct rx_macro *rx = snd_soc_component_get_drvdata(component); 3617 const struct snd_soc_dapm_widget *widgets; 3618 const struct snd_kcontrol_new *controls; 3619 unsigned int num_controls, num_widgets; 3620 int ret; 3621 3622 snd_soc_component_init_regmap(component, rx->regmap); 3623 3624 snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_SEC7(rx, 0), 3625 CDC_RX_DSM_OUT_DELAY_SEL_MASK, 3626 CDC_RX_DSM_OUT_DELAY_TWO_SAMPLE); 3627 snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_SEC7(rx, 1), 3628 CDC_RX_DSM_OUT_DELAY_SEL_MASK, 3629 CDC_RX_DSM_OUT_DELAY_TWO_SAMPLE); 3630 snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_SEC7(rx, 2), 3631 CDC_RX_DSM_OUT_DELAY_SEL_MASK, 3632 CDC_RX_DSM_OUT_DELAY_TWO_SAMPLE); 3633 snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_CFG3(rx, 0), 3634 CDC_RX_DC_COEFF_SEL_MASK, 3635 CDC_RX_DC_COEFF_SEL_TWO); 3636 snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_CFG3(rx, 1), 3637 CDC_RX_DC_COEFF_SEL_MASK, 3638 CDC_RX_DC_COEFF_SEL_TWO); 3639 snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_CFG3(rx, 2), 3640 CDC_RX_DC_COEFF_SEL_MASK, 3641 CDC_RX_DC_COEFF_SEL_TWO); 3642 3643 switch (rx->codec_version) { 3644 case LPASS_CODEC_VERSION_1_0: 3645 case LPASS_CODEC_VERSION_1_1: 3646 case LPASS_CODEC_VERSION_1_2: 3647 case LPASS_CODEC_VERSION_2_0: 3648 case LPASS_CODEC_VERSION_2_1: 3649 controls = rx_macro_def_snd_controls; 3650 num_controls = ARRAY_SIZE(rx_macro_def_snd_controls); 3651 widgets = rx_macro_def_dapm_widgets; 3652 num_widgets = ARRAY_SIZE(rx_macro_def_dapm_widgets); 3653 break; 3654 case LPASS_CODEC_VERSION_2_5: 3655 case LPASS_CODEC_VERSION_2_6: 3656 case LPASS_CODEC_VERSION_2_7: 3657 case LPASS_CODEC_VERSION_2_8: 3658 controls = rx_macro_2_5_snd_controls; 3659 num_controls = ARRAY_SIZE(rx_macro_2_5_snd_controls); 3660 widgets = rx_macro_2_5_dapm_widgets; 3661 num_widgets = ARRAY_SIZE(rx_macro_2_5_dapm_widgets); 3662 break; 3663 default: 3664 return -EINVAL; 3665 } 3666 3667 rx->component = component; 3668 3669 ret = snd_soc_add_component_controls(component, controls, num_controls); 3670 if (ret) 3671 return ret; 3672 3673 return snd_soc_dapm_new_controls(dapm, widgets, num_widgets); 3674 } 3675 3676 static int swclk_gate_enable(struct clk_hw *hw) 3677 { 3678 struct rx_macro *rx = to_rx_macro(hw); 3679 int ret; 3680 3681 ret = clk_prepare_enable(rx->mclk); 3682 if (ret) { 3683 dev_err(rx->dev, "unable to prepare mclk\n"); 3684 return ret; 3685 } 3686 3687 rx_macro_mclk_enable(rx, true); 3688 3689 regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, 3690 CDC_RX_SWR_CLK_EN_MASK, 1); 3691 3692 return 0; 3693 } 3694 3695 static void swclk_gate_disable(struct clk_hw *hw) 3696 { 3697 struct rx_macro *rx = to_rx_macro(hw); 3698 3699 regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, 3700 CDC_RX_SWR_CLK_EN_MASK, 0); 3701 3702 rx_macro_mclk_enable(rx, false); 3703 clk_disable_unprepare(rx->mclk); 3704 } 3705 3706 static int swclk_gate_is_enabled(struct clk_hw *hw) 3707 { 3708 struct rx_macro *rx = to_rx_macro(hw); 3709 int ret, val; 3710 3711 regmap_read(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, &val); 3712 ret = val & BIT(0); 3713 3714 return ret; 3715 } 3716 3717 static unsigned long swclk_recalc_rate(struct clk_hw *hw, 3718 unsigned long parent_rate) 3719 { 3720 return parent_rate / 2; 3721 } 3722 3723 static const struct clk_ops swclk_gate_ops = { 3724 .prepare = swclk_gate_enable, 3725 .unprepare = swclk_gate_disable, 3726 .is_enabled = swclk_gate_is_enabled, 3727 .recalc_rate = swclk_recalc_rate, 3728 3729 }; 3730 3731 static int rx_macro_register_mclk_output(struct rx_macro *rx) 3732 { 3733 struct device *dev = rx->dev; 3734 const char *parent_clk_name = NULL; 3735 const char *clk_name = "lpass-rx-mclk"; 3736 struct clk_hw *hw; 3737 struct clk_init_data init; 3738 int ret; 3739 3740 if (rx->npl) 3741 parent_clk_name = __clk_get_name(rx->npl); 3742 else 3743 parent_clk_name = __clk_get_name(rx->mclk); 3744 3745 init.name = clk_name; 3746 init.ops = &swclk_gate_ops; 3747 init.flags = 0; 3748 init.parent_names = &parent_clk_name; 3749 init.num_parents = 1; 3750 rx->hw.init = &init; 3751 hw = &rx->hw; 3752 ret = devm_clk_hw_register(rx->dev, hw); 3753 if (ret) 3754 return ret; 3755 3756 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw); 3757 } 3758 3759 static const struct snd_soc_component_driver rx_macro_component_drv = { 3760 .name = "RX-MACRO", 3761 .probe = rx_macro_component_probe, 3762 .controls = rx_macro_snd_controls, 3763 .num_controls = ARRAY_SIZE(rx_macro_snd_controls), 3764 .dapm_widgets = rx_macro_dapm_widgets, 3765 .num_dapm_widgets = ARRAY_SIZE(rx_macro_dapm_widgets), 3766 .dapm_routes = rx_audio_map, 3767 .num_dapm_routes = ARRAY_SIZE(rx_audio_map), 3768 }; 3769 3770 static int rx_macro_probe(struct platform_device *pdev) 3771 { 3772 struct device *dev = &pdev->dev; 3773 kernel_ulong_t flags; 3774 struct rx_macro *rx; 3775 void __iomem *base; 3776 int ret, def_count; 3777 3778 flags = (kernel_ulong_t)device_get_match_data(dev); 3779 3780 rx = devm_kzalloc(dev, sizeof(*rx), GFP_KERNEL); 3781 if (!rx) 3782 return -ENOMEM; 3783 3784 rx->macro = devm_clk_get_optional(dev, "macro"); 3785 if (IS_ERR(rx->macro)) 3786 return dev_err_probe(dev, PTR_ERR(rx->macro), "unable to get macro clock\n"); 3787 3788 rx->dcodec = devm_clk_get_optional(dev, "dcodec"); 3789 if (IS_ERR(rx->dcodec)) 3790 return dev_err_probe(dev, PTR_ERR(rx->dcodec), "unable to get dcodec clock\n"); 3791 3792 rx->mclk = devm_clk_get(dev, "mclk"); 3793 if (IS_ERR(rx->mclk)) 3794 return dev_err_probe(dev, PTR_ERR(rx->mclk), "unable to get mclk clock\n"); 3795 3796 if (flags & LPASS_MACRO_FLAG_HAS_NPL_CLOCK) { 3797 rx->npl = devm_clk_get(dev, "npl"); 3798 if (IS_ERR(rx->npl)) 3799 return dev_err_probe(dev, PTR_ERR(rx->npl), "unable to get npl clock\n"); 3800 } 3801 3802 rx->fsgen = devm_clk_get(dev, "fsgen"); 3803 if (IS_ERR(rx->fsgen)) 3804 return dev_err_probe(dev, PTR_ERR(rx->fsgen), "unable to get fsgen clock\n"); 3805 3806 rx->pds = lpass_macro_pds_init(dev); 3807 if (IS_ERR(rx->pds)) 3808 return PTR_ERR(rx->pds); 3809 3810 ret = devm_add_action_or_reset(dev, lpass_macro_pds_exit_action, rx->pds); 3811 if (ret) 3812 return ret; 3813 3814 base = devm_platform_ioremap_resource(pdev, 0); 3815 if (IS_ERR(base)) 3816 return PTR_ERR(base); 3817 3818 rx->codec_version = lpass_macro_get_codec_version(); 3819 struct reg_default *reg_defaults __free(kfree) = NULL; 3820 3821 switch (rx->codec_version) { 3822 case LPASS_CODEC_VERSION_1_0: 3823 case LPASS_CODEC_VERSION_1_1: 3824 case LPASS_CODEC_VERSION_1_2: 3825 case LPASS_CODEC_VERSION_2_0: 3826 case LPASS_CODEC_VERSION_2_1: 3827 rx->rxn_reg_stride = 0x80; 3828 rx->rxn_reg_stride2 = 0xc; 3829 def_count = ARRAY_SIZE(rx_defaults) + ARRAY_SIZE(rx_pre_2_5_defaults); 3830 reg_defaults = kmalloc_array(def_count, sizeof(struct reg_default), GFP_KERNEL); 3831 if (!reg_defaults) 3832 return -ENOMEM; 3833 memcpy(®_defaults[0], rx_defaults, sizeof(rx_defaults)); 3834 memcpy(®_defaults[ARRAY_SIZE(rx_defaults)], 3835 rx_pre_2_5_defaults, sizeof(rx_pre_2_5_defaults)); 3836 break; 3837 case LPASS_CODEC_VERSION_2_5: 3838 case LPASS_CODEC_VERSION_2_6: 3839 case LPASS_CODEC_VERSION_2_7: 3840 case LPASS_CODEC_VERSION_2_8: 3841 rx->rxn_reg_stride = 0xc0; 3842 rx->rxn_reg_stride2 = 0x0; 3843 def_count = ARRAY_SIZE(rx_defaults) + ARRAY_SIZE(rx_2_5_defaults); 3844 reg_defaults = kmalloc_array(def_count, sizeof(struct reg_default), GFP_KERNEL); 3845 if (!reg_defaults) 3846 return -ENOMEM; 3847 memcpy(®_defaults[0], rx_defaults, sizeof(rx_defaults)); 3848 memcpy(®_defaults[ARRAY_SIZE(rx_defaults)], 3849 rx_2_5_defaults, sizeof(rx_2_5_defaults)); 3850 break; 3851 default: 3852 dev_err(dev, "Unsupported Codec version (%d)\n", rx->codec_version); 3853 return -EINVAL; 3854 } 3855 3856 struct regmap_config *reg_config __free(kfree) = kmemdup(&rx_regmap_config, 3857 sizeof(*reg_config), 3858 GFP_KERNEL); 3859 if (!reg_config) 3860 return -ENOMEM; 3861 3862 reg_config->reg_defaults = reg_defaults; 3863 reg_config->num_reg_defaults = def_count; 3864 3865 rx->regmap = devm_regmap_init_mmio(dev, base, reg_config); 3866 if (IS_ERR(rx->regmap)) 3867 return PTR_ERR(rx->regmap); 3868 3869 dev_set_drvdata(dev, rx); 3870 3871 rx->dev = dev; 3872 3873 /* set MCLK and NPL rates */ 3874 clk_set_rate(rx->mclk, MCLK_FREQ); 3875 clk_set_rate(rx->npl, MCLK_FREQ); 3876 3877 ret = clk_prepare_enable(rx->macro); 3878 if (ret) 3879 return ret; 3880 3881 ret = clk_prepare_enable(rx->dcodec); 3882 if (ret) 3883 goto err_dcodec; 3884 3885 ret = clk_prepare_enable(rx->mclk); 3886 if (ret) 3887 goto err_mclk; 3888 3889 ret = clk_prepare_enable(rx->npl); 3890 if (ret) 3891 goto err_npl; 3892 3893 ret = clk_prepare_enable(rx->fsgen); 3894 if (ret) 3895 goto err_fsgen; 3896 3897 /* reset swr block */ 3898 regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, 3899 CDC_RX_SWR_RESET_MASK, 3900 CDC_RX_SWR_RESET); 3901 3902 regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, 3903 CDC_RX_SWR_CLK_EN_MASK, 1); 3904 3905 regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, 3906 CDC_RX_SWR_RESET_MASK, 0); 3907 3908 ret = devm_snd_soc_register_component(dev, &rx_macro_component_drv, 3909 rx_macro_dai, 3910 ARRAY_SIZE(rx_macro_dai)); 3911 if (ret) 3912 goto err_clkout; 3913 3914 3915 pm_runtime_set_autosuspend_delay(dev, 3000); 3916 pm_runtime_use_autosuspend(dev); 3917 pm_runtime_mark_last_busy(dev); 3918 pm_runtime_set_active(dev); 3919 pm_runtime_enable(dev); 3920 3921 ret = rx_macro_register_mclk_output(rx); 3922 if (ret) 3923 goto err_clkout; 3924 3925 return 0; 3926 3927 err_clkout: 3928 clk_disable_unprepare(rx->fsgen); 3929 err_fsgen: 3930 clk_disable_unprepare(rx->npl); 3931 err_npl: 3932 clk_disable_unprepare(rx->mclk); 3933 err_mclk: 3934 clk_disable_unprepare(rx->dcodec); 3935 err_dcodec: 3936 clk_disable_unprepare(rx->macro); 3937 3938 return ret; 3939 } 3940 3941 static void rx_macro_remove(struct platform_device *pdev) 3942 { 3943 struct rx_macro *rx = dev_get_drvdata(&pdev->dev); 3944 3945 clk_disable_unprepare(rx->mclk); 3946 clk_disable_unprepare(rx->npl); 3947 clk_disable_unprepare(rx->fsgen); 3948 clk_disable_unprepare(rx->macro); 3949 clk_disable_unprepare(rx->dcodec); 3950 } 3951 3952 static const struct of_device_id rx_macro_dt_match[] = { 3953 { 3954 .compatible = "qcom,sc7280-lpass-rx-macro", 3955 .data = (void *)LPASS_MACRO_FLAG_HAS_NPL_CLOCK, 3956 3957 }, { 3958 .compatible = "qcom,sm8250-lpass-rx-macro", 3959 .data = (void *)LPASS_MACRO_FLAG_HAS_NPL_CLOCK, 3960 }, { 3961 .compatible = "qcom,sm8450-lpass-rx-macro", 3962 .data = (void *)LPASS_MACRO_FLAG_HAS_NPL_CLOCK, 3963 }, { 3964 .compatible = "qcom,sm8550-lpass-rx-macro", 3965 }, { 3966 .compatible = "qcom,sc8280xp-lpass-rx-macro", 3967 .data = (void *)LPASS_MACRO_FLAG_HAS_NPL_CLOCK, 3968 }, 3969 { } 3970 }; 3971 MODULE_DEVICE_TABLE(of, rx_macro_dt_match); 3972 3973 static int rx_macro_runtime_suspend(struct device *dev) 3974 { 3975 struct rx_macro *rx = dev_get_drvdata(dev); 3976 3977 regcache_cache_only(rx->regmap, true); 3978 regcache_mark_dirty(rx->regmap); 3979 3980 clk_disable_unprepare(rx->fsgen); 3981 clk_disable_unprepare(rx->npl); 3982 clk_disable_unprepare(rx->mclk); 3983 3984 return 0; 3985 } 3986 3987 static int rx_macro_runtime_resume(struct device *dev) 3988 { 3989 struct rx_macro *rx = dev_get_drvdata(dev); 3990 int ret; 3991 3992 ret = clk_prepare_enable(rx->mclk); 3993 if (ret) { 3994 dev_err(dev, "unable to prepare mclk\n"); 3995 return ret; 3996 } 3997 3998 ret = clk_prepare_enable(rx->npl); 3999 if (ret) { 4000 dev_err(dev, "unable to prepare mclkx2\n"); 4001 goto err_npl; 4002 } 4003 4004 ret = clk_prepare_enable(rx->fsgen); 4005 if (ret) { 4006 dev_err(dev, "unable to prepare fsgen\n"); 4007 goto err_fsgen; 4008 } 4009 regcache_cache_only(rx->regmap, false); 4010 regcache_sync(rx->regmap); 4011 4012 return 0; 4013 err_fsgen: 4014 clk_disable_unprepare(rx->npl); 4015 err_npl: 4016 clk_disable_unprepare(rx->mclk); 4017 4018 return ret; 4019 } 4020 4021 static const struct dev_pm_ops rx_macro_pm_ops = { 4022 RUNTIME_PM_OPS(rx_macro_runtime_suspend, rx_macro_runtime_resume, NULL) 4023 }; 4024 4025 static struct platform_driver rx_macro_driver = { 4026 .driver = { 4027 .name = "rx_macro", 4028 .of_match_table = rx_macro_dt_match, 4029 .suppress_bind_attrs = true, 4030 .pm = pm_ptr(&rx_macro_pm_ops), 4031 }, 4032 .probe = rx_macro_probe, 4033 .remove = rx_macro_remove, 4034 }; 4035 4036 module_platform_driver(rx_macro_driver); 4037 4038 MODULE_DESCRIPTION("RX macro driver"); 4039 MODULE_LICENSE("GPL"); 4040