1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2024 AIROHA Inc 4 * Author: Lorenzo Bianconi <lorenzo@kernel.org> 5 */ 6 #include <linux/of.h> 7 #include <linux/of_net.h> 8 #include <linux/of_reserved_mem.h> 9 #include <linux/platform_device.h> 10 #include <linux/tcp.h> 11 #include <linux/u64_stats_sync.h> 12 #include <net/dst_metadata.h> 13 #include <net/page_pool/helpers.h> 14 #include <net/pkt_cls.h> 15 #include <uapi/linux/ppp_defs.h> 16 17 #include "airoha_regs.h" 18 #include "airoha_eth.h" 19 20 u32 airoha_rr(void __iomem *base, u32 offset) 21 { 22 return readl(base + offset); 23 } 24 25 void airoha_wr(void __iomem *base, u32 offset, u32 val) 26 { 27 writel(val, base + offset); 28 } 29 30 u32 airoha_rmw(void __iomem *base, u32 offset, u32 mask, u32 val) 31 { 32 val |= (airoha_rr(base, offset) & ~mask); 33 airoha_wr(base, offset, val); 34 35 return val; 36 } 37 38 static void airoha_qdma_set_irqmask(struct airoha_irq_bank *irq_bank, 39 int index, u32 clear, u32 set) 40 { 41 struct airoha_qdma *qdma = irq_bank->qdma; 42 int bank = irq_bank - &qdma->irq_banks[0]; 43 unsigned long flags; 44 45 if (WARN_ON_ONCE(index >= ARRAY_SIZE(irq_bank->irqmask))) 46 return; 47 48 spin_lock_irqsave(&irq_bank->irq_lock, flags); 49 50 irq_bank->irqmask[index] &= ~clear; 51 irq_bank->irqmask[index] |= set; 52 airoha_qdma_wr(qdma, REG_INT_ENABLE(bank, index), 53 irq_bank->irqmask[index]); 54 /* Read irq_enable register in order to guarantee the update above 55 * completes in the spinlock critical section. 56 */ 57 airoha_qdma_rr(qdma, REG_INT_ENABLE(bank, index)); 58 59 spin_unlock_irqrestore(&irq_bank->irq_lock, flags); 60 } 61 62 static void airoha_qdma_irq_enable(struct airoha_irq_bank *irq_bank, 63 int index, u32 mask) 64 { 65 airoha_qdma_set_irqmask(irq_bank, index, 0, mask); 66 } 67 68 static void airoha_qdma_irq_disable(struct airoha_irq_bank *irq_bank, 69 int index, u32 mask) 70 { 71 airoha_qdma_set_irqmask(irq_bank, index, mask, 0); 72 } 73 74 static void airoha_set_macaddr(struct airoha_gdm_port *port, const u8 *addr) 75 { 76 struct airoha_eth *eth = port->qdma->eth; 77 u32 val, reg; 78 79 reg = airoha_is_lan_gdm_port(port) ? REG_FE_LAN_MAC_H 80 : REG_FE_WAN_MAC_H; 81 val = (addr[0] << 16) | (addr[1] << 8) | addr[2]; 82 airoha_fe_wr(eth, reg, val); 83 84 val = (addr[3] << 16) | (addr[4] << 8) | addr[5]; 85 airoha_fe_wr(eth, REG_FE_MAC_LMIN(reg), val); 86 airoha_fe_wr(eth, REG_FE_MAC_LMAX(reg), val); 87 88 airoha_ppe_init_upd_mem(port); 89 } 90 91 static void airoha_set_gdm_port_fwd_cfg(struct airoha_eth *eth, u32 addr, 92 u32 val) 93 { 94 airoha_fe_rmw(eth, addr, GDM_OCFQ_MASK, 95 FIELD_PREP(GDM_OCFQ_MASK, val)); 96 airoha_fe_rmw(eth, addr, GDM_MCFQ_MASK, 97 FIELD_PREP(GDM_MCFQ_MASK, val)); 98 airoha_fe_rmw(eth, addr, GDM_BCFQ_MASK, 99 FIELD_PREP(GDM_BCFQ_MASK, val)); 100 airoha_fe_rmw(eth, addr, GDM_UCFQ_MASK, 101 FIELD_PREP(GDM_UCFQ_MASK, val)); 102 } 103 104 static int airoha_set_vip_for_gdm_port(struct airoha_gdm_port *port, 105 bool enable) 106 { 107 struct airoha_eth *eth = port->qdma->eth; 108 u32 vip_port; 109 110 vip_port = eth->soc->ops.get_vip_port(port, port->nbq); 111 if (enable) { 112 airoha_fe_set(eth, REG_FE_VIP_PORT_EN, vip_port); 113 airoha_fe_set(eth, REG_FE_IFC_PORT_EN, vip_port); 114 } else { 115 airoha_fe_clear(eth, REG_FE_VIP_PORT_EN, vip_port); 116 airoha_fe_clear(eth, REG_FE_IFC_PORT_EN, vip_port); 117 } 118 119 return 0; 120 } 121 122 static void airoha_fe_maccr_init(struct airoha_eth *eth) 123 { 124 int p; 125 126 for (p = 1; p <= ARRAY_SIZE(eth->ports); p++) 127 airoha_fe_set(eth, REG_GDM_FWD_CFG(p), 128 GDM_TCP_CKSUM_MASK | GDM_UDP_CKSUM_MASK | 129 GDM_IP4_CKSUM_MASK | GDM_DROP_CRC_ERR_MASK); 130 131 airoha_fe_rmw(eth, REG_CDM_VLAN_CTRL(1), CDM_VLAN_MASK, 132 FIELD_PREP(CDM_VLAN_MASK, 0x8100)); 133 134 airoha_fe_set(eth, REG_FE_CPORT_CFG, FE_CPORT_PAD); 135 } 136 137 static void airoha_fe_vip_setup(struct airoha_eth *eth) 138 { 139 airoha_fe_wr(eth, REG_FE_VIP_PATN(3), ETH_P_PPP_DISC); 140 airoha_fe_wr(eth, REG_FE_VIP_EN(3), PATN_FCPU_EN_MASK | PATN_EN_MASK); 141 142 airoha_fe_wr(eth, REG_FE_VIP_PATN(4), PPP_LCP); 143 airoha_fe_wr(eth, REG_FE_VIP_EN(4), 144 PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) | 145 PATN_EN_MASK); 146 147 airoha_fe_wr(eth, REG_FE_VIP_PATN(6), PPP_IPCP); 148 airoha_fe_wr(eth, REG_FE_VIP_EN(6), 149 PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) | 150 PATN_EN_MASK); 151 152 airoha_fe_wr(eth, REG_FE_VIP_PATN(7), PPP_CHAP); 153 airoha_fe_wr(eth, REG_FE_VIP_EN(7), 154 PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) | 155 PATN_EN_MASK); 156 157 /* BOOTP (0x43) */ 158 airoha_fe_wr(eth, REG_FE_VIP_PATN(8), 0x43); 159 airoha_fe_wr(eth, REG_FE_VIP_EN(8), 160 PATN_FCPU_EN_MASK | PATN_SP_EN_MASK | 161 FIELD_PREP(PATN_TYPE_MASK, 4) | PATN_EN_MASK); 162 163 /* BOOTP (0x44) */ 164 airoha_fe_wr(eth, REG_FE_VIP_PATN(9), 0x44); 165 airoha_fe_wr(eth, REG_FE_VIP_EN(9), 166 PATN_FCPU_EN_MASK | PATN_SP_EN_MASK | 167 FIELD_PREP(PATN_TYPE_MASK, 4) | PATN_EN_MASK); 168 169 /* ISAKMP */ 170 airoha_fe_wr(eth, REG_FE_VIP_PATN(10), 0x1f401f4); 171 airoha_fe_wr(eth, REG_FE_VIP_EN(10), 172 PATN_FCPU_EN_MASK | PATN_DP_EN_MASK | PATN_SP_EN_MASK | 173 FIELD_PREP(PATN_TYPE_MASK, 4) | PATN_EN_MASK); 174 175 airoha_fe_wr(eth, REG_FE_VIP_PATN(11), PPP_IPV6CP); 176 airoha_fe_wr(eth, REG_FE_VIP_EN(11), 177 PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) | 178 PATN_EN_MASK); 179 180 /* DHCPv6 */ 181 airoha_fe_wr(eth, REG_FE_VIP_PATN(12), 0x2220223); 182 airoha_fe_wr(eth, REG_FE_VIP_EN(12), 183 PATN_FCPU_EN_MASK | PATN_DP_EN_MASK | PATN_SP_EN_MASK | 184 FIELD_PREP(PATN_TYPE_MASK, 4) | PATN_EN_MASK); 185 186 airoha_fe_wr(eth, REG_FE_VIP_PATN(19), PPP_PAP); 187 airoha_fe_wr(eth, REG_FE_VIP_EN(19), 188 PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) | 189 PATN_EN_MASK); 190 191 /* ETH->ETH_P_1905 (0x893a) */ 192 airoha_fe_wr(eth, REG_FE_VIP_PATN(20), 0x893a); 193 airoha_fe_wr(eth, REG_FE_VIP_EN(20), 194 PATN_FCPU_EN_MASK | PATN_EN_MASK); 195 196 airoha_fe_wr(eth, REG_FE_VIP_PATN(21), ETH_P_LLDP); 197 airoha_fe_wr(eth, REG_FE_VIP_EN(21), 198 PATN_FCPU_EN_MASK | PATN_EN_MASK); 199 } 200 201 static u32 airoha_fe_get_pse_queue_rsv_pages(struct airoha_eth *eth, 202 u32 port, u32 queue) 203 { 204 u32 val; 205 206 airoha_fe_rmw(eth, REG_FE_PSE_QUEUE_CFG_WR, 207 PSE_CFG_PORT_ID_MASK | PSE_CFG_QUEUE_ID_MASK, 208 FIELD_PREP(PSE_CFG_PORT_ID_MASK, port) | 209 FIELD_PREP(PSE_CFG_QUEUE_ID_MASK, queue)); 210 val = airoha_fe_rr(eth, REG_FE_PSE_QUEUE_CFG_VAL); 211 212 return FIELD_GET(PSE_CFG_OQ_RSV_MASK, val); 213 } 214 215 static void airoha_fe_set_pse_queue_rsv_pages(struct airoha_eth *eth, 216 u32 port, u32 queue, u32 val) 217 { 218 airoha_fe_rmw(eth, REG_FE_PSE_QUEUE_CFG_VAL, PSE_CFG_OQ_RSV_MASK, 219 FIELD_PREP(PSE_CFG_OQ_RSV_MASK, val)); 220 airoha_fe_rmw(eth, REG_FE_PSE_QUEUE_CFG_WR, 221 PSE_CFG_PORT_ID_MASK | PSE_CFG_QUEUE_ID_MASK | 222 PSE_CFG_WR_EN_MASK | PSE_CFG_OQRSV_SEL_MASK, 223 FIELD_PREP(PSE_CFG_PORT_ID_MASK, port) | 224 FIELD_PREP(PSE_CFG_QUEUE_ID_MASK, queue) | 225 PSE_CFG_WR_EN_MASK | PSE_CFG_OQRSV_SEL_MASK); 226 } 227 228 static u32 airoha_fe_get_pse_all_rsv(struct airoha_eth *eth) 229 { 230 u32 val = airoha_fe_rr(eth, REG_FE_PSE_BUF_SET); 231 232 return FIELD_GET(PSE_ALLRSV_MASK, val); 233 } 234 235 static int airoha_fe_set_pse_oq_rsv(struct airoha_eth *eth, 236 u32 port, u32 queue, u32 val) 237 { 238 u32 orig_val = airoha_fe_get_pse_queue_rsv_pages(eth, port, queue); 239 u32 tmp, all_rsv, fq_limit; 240 241 airoha_fe_set_pse_queue_rsv_pages(eth, port, queue, val); 242 243 /* modify all rsv */ 244 all_rsv = airoha_fe_get_pse_all_rsv(eth); 245 all_rsv += (val - orig_val); 246 airoha_fe_rmw(eth, REG_FE_PSE_BUF_SET, PSE_ALLRSV_MASK, 247 FIELD_PREP(PSE_ALLRSV_MASK, all_rsv)); 248 249 /* modify hthd */ 250 tmp = airoha_fe_rr(eth, PSE_FQ_CFG); 251 fq_limit = FIELD_GET(PSE_FQ_LIMIT_MASK, tmp); 252 tmp = fq_limit - all_rsv - 0x20; 253 airoha_fe_rmw(eth, REG_PSE_SHARE_USED_THD, 254 PSE_SHARE_USED_HTHD_MASK, 255 FIELD_PREP(PSE_SHARE_USED_HTHD_MASK, tmp)); 256 257 tmp = fq_limit - all_rsv - 0x100; 258 airoha_fe_rmw(eth, REG_PSE_SHARE_USED_THD, 259 PSE_SHARE_USED_MTHD_MASK, 260 FIELD_PREP(PSE_SHARE_USED_MTHD_MASK, tmp)); 261 tmp = (3 * tmp) >> 2; 262 airoha_fe_rmw(eth, REG_FE_PSE_BUF_SET, 263 PSE_SHARE_USED_LTHD_MASK, 264 FIELD_PREP(PSE_SHARE_USED_LTHD_MASK, tmp)); 265 266 return 0; 267 } 268 269 static void airoha_fe_pse_ports_init(struct airoha_eth *eth) 270 { 271 const u32 pse_port_num_queues[] = { 272 [FE_PSE_PORT_CDM1] = 6, 273 [FE_PSE_PORT_GDM1] = 6, 274 [FE_PSE_PORT_GDM2] = 32, 275 [FE_PSE_PORT_GDM3] = 6, 276 [FE_PSE_PORT_PPE1] = 4, 277 [FE_PSE_PORT_CDM2] = 6, 278 [FE_PSE_PORT_CDM3] = 8, 279 [FE_PSE_PORT_CDM4] = 10, 280 [FE_PSE_PORT_PPE2] = 4, 281 [FE_PSE_PORT_GDM4] = 2, 282 [FE_PSE_PORT_CDM5] = 2, 283 }; 284 int q; 285 286 if (airoha_ppe_is_enabled(eth, 1)) { 287 u32 all_rsv; 288 289 /* hw misses PPE2 oq rsv */ 290 all_rsv = airoha_fe_get_pse_all_rsv(eth); 291 all_rsv += PSE_RSV_PAGES * 292 pse_port_num_queues[FE_PSE_PORT_PPE2]; 293 airoha_fe_rmw(eth, REG_FE_PSE_BUF_SET, PSE_ALLRSV_MASK, 294 FIELD_PREP(PSE_ALLRSV_MASK, all_rsv)); 295 } 296 297 /* CMD1 */ 298 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_CDM1]; q++) 299 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM1, q, 300 PSE_QUEUE_RSV_PAGES); 301 /* GMD1 */ 302 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_GDM1]; q++) 303 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM1, q, 304 PSE_QUEUE_RSV_PAGES); 305 /* GMD2 */ 306 for (q = 6; q < pse_port_num_queues[FE_PSE_PORT_GDM2]; q++) 307 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM2, q, 0); 308 /* GMD3 */ 309 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_GDM3]; q++) 310 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM3, q, 311 PSE_QUEUE_RSV_PAGES); 312 /* PPE1 */ 313 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_PPE1]; q++) { 314 if (q < pse_port_num_queues[FE_PSE_PORT_PPE1]) 315 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE1, q, 316 PSE_QUEUE_RSV_PAGES); 317 else 318 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE1, q, 0); 319 } 320 /* CDM2 */ 321 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_CDM2]; q++) 322 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM2, q, 323 PSE_QUEUE_RSV_PAGES); 324 /* CDM3 */ 325 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_CDM3] - 1; q++) 326 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM3, q, 0); 327 /* CDM4 */ 328 for (q = 4; q < pse_port_num_queues[FE_PSE_PORT_CDM4]; q++) 329 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM4, q, 330 PSE_QUEUE_RSV_PAGES); 331 if (airoha_ppe_is_enabled(eth, 1)) { 332 /* PPE2 */ 333 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_PPE2]; q++) { 334 if (q < pse_port_num_queues[FE_PSE_PORT_PPE2] / 2) 335 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE2, 336 q, 337 PSE_QUEUE_RSV_PAGES); 338 else 339 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE2, 340 q, 0); 341 } 342 } 343 /* GMD4 */ 344 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_GDM4]; q++) 345 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM4, q, 346 PSE_QUEUE_RSV_PAGES); 347 /* CDM5 */ 348 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_CDM5]; q++) 349 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM5, q, 350 PSE_QUEUE_RSV_PAGES); 351 } 352 353 static int airoha_fe_mc_vlan_clear(struct airoha_eth *eth) 354 { 355 int i; 356 357 for (i = 0; i < AIROHA_FE_MC_MAX_VLAN_TABLE; i++) { 358 int err, j; 359 u32 val; 360 361 airoha_fe_wr(eth, REG_MC_VLAN_DATA, 0x0); 362 363 val = FIELD_PREP(MC_VLAN_CFG_TABLE_ID_MASK, i) | 364 MC_VLAN_CFG_TABLE_SEL_MASK | MC_VLAN_CFG_RW_MASK; 365 airoha_fe_wr(eth, REG_MC_VLAN_CFG, val); 366 err = read_poll_timeout(airoha_fe_rr, val, 367 val & MC_VLAN_CFG_CMD_DONE_MASK, 368 USEC_PER_MSEC, 5 * USEC_PER_MSEC, 369 false, eth, REG_MC_VLAN_CFG); 370 if (err) 371 return err; 372 373 for (j = 0; j < AIROHA_FE_MC_MAX_VLAN_PORT; j++) { 374 airoha_fe_wr(eth, REG_MC_VLAN_DATA, 0x0); 375 376 val = FIELD_PREP(MC_VLAN_CFG_TABLE_ID_MASK, i) | 377 FIELD_PREP(MC_VLAN_CFG_PORT_ID_MASK, j) | 378 MC_VLAN_CFG_RW_MASK; 379 airoha_fe_wr(eth, REG_MC_VLAN_CFG, val); 380 err = read_poll_timeout(airoha_fe_rr, val, 381 val & MC_VLAN_CFG_CMD_DONE_MASK, 382 USEC_PER_MSEC, 383 5 * USEC_PER_MSEC, false, eth, 384 REG_MC_VLAN_CFG); 385 if (err) 386 return err; 387 } 388 } 389 390 return 0; 391 } 392 393 static void airoha_fe_crsn_qsel_init(struct airoha_eth *eth) 394 { 395 /* CDM1_CRSN_QSEL */ 396 airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_22 >> 2), 397 CDM_CRSN_QSEL_REASON_MASK(CRSN_22), 398 FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_22), 399 CDM_CRSN_QSEL_Q1)); 400 airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_08 >> 2), 401 CDM_CRSN_QSEL_REASON_MASK(CRSN_08), 402 FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_08), 403 CDM_CRSN_QSEL_Q1)); 404 airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_21 >> 2), 405 CDM_CRSN_QSEL_REASON_MASK(CRSN_21), 406 FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_21), 407 CDM_CRSN_QSEL_Q1)); 408 airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_24 >> 2), 409 CDM_CRSN_QSEL_REASON_MASK(CRSN_24), 410 FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_24), 411 CDM_CRSN_QSEL_Q6)); 412 airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_25 >> 2), 413 CDM_CRSN_QSEL_REASON_MASK(CRSN_25), 414 FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_25), 415 CDM_CRSN_QSEL_Q1)); 416 /* CDM2_CRSN_QSEL */ 417 airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_08 >> 2), 418 CDM_CRSN_QSEL_REASON_MASK(CRSN_08), 419 FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_08), 420 CDM_CRSN_QSEL_Q1)); 421 airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_21 >> 2), 422 CDM_CRSN_QSEL_REASON_MASK(CRSN_21), 423 FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_21), 424 CDM_CRSN_QSEL_Q1)); 425 airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_22 >> 2), 426 CDM_CRSN_QSEL_REASON_MASK(CRSN_22), 427 FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_22), 428 CDM_CRSN_QSEL_Q1)); 429 airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_24 >> 2), 430 CDM_CRSN_QSEL_REASON_MASK(CRSN_24), 431 FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_24), 432 CDM_CRSN_QSEL_Q6)); 433 airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_25 >> 2), 434 CDM_CRSN_QSEL_REASON_MASK(CRSN_25), 435 FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_25), 436 CDM_CRSN_QSEL_Q1)); 437 } 438 439 static int airoha_fe_init(struct airoha_eth *eth) 440 { 441 airoha_fe_maccr_init(eth); 442 443 /* PSE IQ reserve */ 444 airoha_fe_rmw(eth, REG_PSE_IQ_REV1, PSE_IQ_RES1_P2_MASK, 445 FIELD_PREP(PSE_IQ_RES1_P2_MASK, 0x10)); 446 airoha_fe_rmw(eth, REG_PSE_IQ_REV2, 447 PSE_IQ_RES2_P5_MASK | PSE_IQ_RES2_P4_MASK, 448 FIELD_PREP(PSE_IQ_RES2_P5_MASK, 0x40) | 449 FIELD_PREP(PSE_IQ_RES2_P4_MASK, 0x34)); 450 451 /* enable FE copy engine for KA/DPI */ 452 airoha_fe_wr(eth, REG_FE_PCE_CFG, PCE_DPI_EN_MASK | PCE_KA_EN_MASK); 453 /* set vip queue selection to ring 1 */ 454 airoha_fe_rmw(eth, REG_CDM_FWD_CFG(1), CDM_VIP_QSEL_MASK, 455 FIELD_PREP(CDM_VIP_QSEL_MASK, 0x4)); 456 airoha_fe_rmw(eth, REG_CDM_FWD_CFG(2), CDM_VIP_QSEL_MASK, 457 FIELD_PREP(CDM_VIP_QSEL_MASK, 0x4)); 458 /* set GDM4 source interface offset to 8 */ 459 airoha_fe_rmw(eth, REG_GDM_SRC_PORT_SET(4), 460 GDM_SPORT_OFF2_MASK | 461 GDM_SPORT_OFF1_MASK | 462 GDM_SPORT_OFF0_MASK, 463 FIELD_PREP(GDM_SPORT_OFF2_MASK, 8) | 464 FIELD_PREP(GDM_SPORT_OFF1_MASK, 8) | 465 FIELD_PREP(GDM_SPORT_OFF0_MASK, 8)); 466 467 /* set PSE Page as 128B */ 468 airoha_fe_rmw(eth, REG_FE_DMA_GLO_CFG, 469 FE_DMA_GLO_L2_SPACE_MASK | FE_DMA_GLO_PG_SZ_MASK, 470 FIELD_PREP(FE_DMA_GLO_L2_SPACE_MASK, 2) | 471 FE_DMA_GLO_PG_SZ_MASK); 472 airoha_fe_wr(eth, REG_FE_RST_GLO_CFG, 473 FE_RST_CORE_MASK | FE_RST_GDM3_MBI_ARB_MASK | 474 FE_RST_GDM4_MBI_ARB_MASK); 475 usleep_range(1000, 2000); 476 477 /* connect RxRing1 and RxRing15 to PSE Port0 OQ-1 478 * connect other rings to PSE Port0 OQ-0 479 */ 480 airoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP0, BIT(4)); 481 airoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP1, BIT(28)); 482 airoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP2, BIT(4)); 483 airoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP3, BIT(28)); 484 485 airoha_fe_vip_setup(eth); 486 airoha_fe_pse_ports_init(eth); 487 488 airoha_fe_set(eth, REG_GDM_MISC_CFG, 489 GDM2_RDM_ACK_WAIT_PREF_MASK | 490 GDM2_CHN_VLD_MODE_MASK); 491 airoha_fe_rmw(eth, REG_CDM_FWD_CFG(2), CDM_OAM_QSEL_MASK, 492 FIELD_PREP(CDM_OAM_QSEL_MASK, 15)); 493 494 /* init fragment and assemble Force Port */ 495 /* NPU Core-3, NPU Bridge Channel-3 */ 496 airoha_fe_rmw(eth, REG_IP_FRAG_FP, 497 IP_FRAGMENT_PORT_MASK | IP_FRAGMENT_NBQ_MASK, 498 FIELD_PREP(IP_FRAGMENT_PORT_MASK, 6) | 499 FIELD_PREP(IP_FRAGMENT_NBQ_MASK, 3)); 500 /* QDMA LAN, RX Ring-22 */ 501 airoha_fe_rmw(eth, REG_IP_FRAG_FP, 502 IP_ASSEMBLE_PORT_MASK | IP_ASSEMBLE_NBQ_MASK, 503 FIELD_PREP(IP_ASSEMBLE_PORT_MASK, 0) | 504 FIELD_PREP(IP_ASSEMBLE_NBQ_MASK, 22)); 505 506 airoha_fe_set(eth, REG_GDM_FWD_CFG(AIROHA_GDM3_IDX), GDM_PAD_EN_MASK); 507 airoha_fe_set(eth, REG_GDM_FWD_CFG(AIROHA_GDM4_IDX), GDM_PAD_EN_MASK); 508 509 airoha_fe_crsn_qsel_init(eth); 510 511 airoha_fe_clear(eth, REG_FE_CPORT_CFG, FE_CPORT_QUEUE_XFC_MASK); 512 airoha_fe_set(eth, REG_FE_CPORT_CFG, FE_CPORT_PORT_XFC_MASK); 513 514 /* default aging mode for mbi unlock issue */ 515 airoha_fe_rmw(eth, REG_GDM_CHN_RLS(2), 516 MBI_RX_AGE_SEL_MASK | MBI_TX_AGE_SEL_MASK, 517 FIELD_PREP(MBI_RX_AGE_SEL_MASK, 3) | 518 FIELD_PREP(MBI_TX_AGE_SEL_MASK, 3)); 519 520 /* disable IFC by default */ 521 airoha_fe_clear(eth, REG_FE_CSR_IFC_CFG, FE_IFC_EN_MASK); 522 523 /* enable 1:N vlan action, init vlan table */ 524 airoha_fe_set(eth, REG_MC_VLAN_EN, MC_VLAN_EN_MASK); 525 526 return airoha_fe_mc_vlan_clear(eth); 527 } 528 529 static int airoha_qdma_fill_rx_queue(struct airoha_queue *q) 530 { 531 struct airoha_qdma *qdma = q->qdma; 532 int qid = q - &qdma->q_rx[0]; 533 int nframes = 0; 534 535 while (q->queued < q->ndesc - 1) { 536 struct airoha_queue_entry *e = &q->entry[q->head]; 537 struct airoha_qdma_desc *desc = &q->desc[q->head]; 538 struct page *page; 539 int offset; 540 u32 val; 541 542 page = page_pool_dev_alloc_frag(q->page_pool, &offset, 543 q->buf_size); 544 if (!page) 545 break; 546 547 q->head = (q->head + 1) % q->ndesc; 548 q->queued++; 549 nframes++; 550 551 e->buf = page_address(page) + offset; 552 e->dma_addr = page_pool_get_dma_addr(page) + offset; 553 e->dma_len = SKB_WITH_OVERHEAD(q->buf_size); 554 555 val = FIELD_PREP(QDMA_DESC_LEN_MASK, e->dma_len); 556 WRITE_ONCE(desc->ctrl, cpu_to_le32(val)); 557 WRITE_ONCE(desc->addr, cpu_to_le32(e->dma_addr)); 558 val = FIELD_PREP(QDMA_DESC_NEXT_ID_MASK, q->head); 559 WRITE_ONCE(desc->data, cpu_to_le32(val)); 560 WRITE_ONCE(desc->msg0, 0); 561 WRITE_ONCE(desc->msg1, 0); 562 WRITE_ONCE(desc->msg2, 0); 563 WRITE_ONCE(desc->msg3, 0); 564 } 565 566 if (nframes) 567 airoha_qdma_rmw(qdma, REG_RX_CPU_IDX(qid), 568 RX_RING_CPU_IDX_MASK, 569 FIELD_PREP(RX_RING_CPU_IDX_MASK, q->head)); 570 571 return nframes; 572 } 573 574 static int airoha_qdma_get_gdm_port(struct airoha_eth *eth, 575 struct airoha_qdma_desc *desc) 576 { 577 u32 port, sport, msg1 = le32_to_cpu(READ_ONCE(desc->msg1)); 578 579 sport = FIELD_GET(QDMA_ETH_RXMSG_SPORT_MASK, msg1); 580 switch (sport) { 581 case 0x10 ... 0x14: 582 port = 0; 583 break; 584 case 0x2 ... 0x4: 585 port = sport - 1; 586 break; 587 default: 588 return -EINVAL; 589 } 590 591 return port >= ARRAY_SIZE(eth->ports) ? -EINVAL : port; 592 } 593 594 static int airoha_qdma_rx_process(struct airoha_queue *q, int budget) 595 { 596 enum dma_data_direction dir = page_pool_get_dma_dir(q->page_pool); 597 struct airoha_qdma *qdma = q->qdma; 598 struct airoha_eth *eth = qdma->eth; 599 int qid = q - &qdma->q_rx[0]; 600 int done = 0; 601 602 while (done < budget) { 603 struct airoha_queue_entry *e = &q->entry[q->tail]; 604 struct airoha_qdma_desc *desc = &q->desc[q->tail]; 605 u32 hash, reason, msg1, desc_ctrl; 606 struct airoha_gdm_port *port; 607 int data_len, len, p; 608 struct page *page; 609 610 desc_ctrl = le32_to_cpu(READ_ONCE(desc->ctrl)); 611 if (!(desc_ctrl & QDMA_DESC_DONE_MASK)) 612 break; 613 614 dma_rmb(); 615 616 q->tail = (q->tail + 1) % q->ndesc; 617 q->queued--; 618 619 dma_sync_single_for_cpu(eth->dev, e->dma_addr, 620 SKB_WITH_OVERHEAD(q->buf_size), dir); 621 622 page = virt_to_head_page(e->buf); 623 len = FIELD_GET(QDMA_DESC_LEN_MASK, desc_ctrl); 624 data_len = q->skb ? q->buf_size 625 : SKB_WITH_OVERHEAD(q->buf_size); 626 if (!len || data_len < len) 627 goto free_frag; 628 629 p = airoha_qdma_get_gdm_port(eth, desc); 630 if (p < 0 || !eth->ports[p]) 631 goto free_frag; 632 633 port = eth->ports[p]; 634 if (!q->skb) { /* first buffer */ 635 q->skb = napi_build_skb(e->buf, q->buf_size); 636 if (!q->skb) 637 goto free_frag; 638 639 __skb_put(q->skb, len); 640 skb_mark_for_recycle(q->skb); 641 q->skb->dev = port->dev; 642 q->skb->protocol = eth_type_trans(q->skb, port->dev); 643 q->skb->ip_summed = CHECKSUM_UNNECESSARY; 644 skb_record_rx_queue(q->skb, qid); 645 } else { /* scattered frame */ 646 struct skb_shared_info *shinfo = skb_shinfo(q->skb); 647 int nr_frags = shinfo->nr_frags; 648 649 if (nr_frags >= ARRAY_SIZE(shinfo->frags)) 650 goto free_frag; 651 652 skb_add_rx_frag(q->skb, nr_frags, page, 653 e->buf - page_address(page), len, 654 q->buf_size); 655 } 656 657 if (FIELD_GET(QDMA_DESC_MORE_MASK, desc_ctrl)) 658 continue; 659 660 if (netdev_uses_dsa(port->dev)) { 661 /* PPE module requires untagged packets to work 662 * properly and it provides DSA port index via the 663 * DMA descriptor. Report DSA tag to the DSA stack 664 * via skb dst info. 665 */ 666 u32 msg0 = le32_to_cpu(READ_ONCE(desc->msg0)); 667 u32 sptag = FIELD_GET(QDMA_ETH_RXMSG_SPTAG, msg0); 668 669 if (sptag < ARRAY_SIZE(port->dsa_meta) && 670 port->dsa_meta[sptag]) 671 skb_dst_set_noref(q->skb, 672 &port->dsa_meta[sptag]->dst); 673 } 674 675 msg1 = le32_to_cpu(READ_ONCE(desc->msg1)); 676 hash = FIELD_GET(AIROHA_RXD4_FOE_ENTRY, msg1); 677 if (hash != AIROHA_RXD4_FOE_ENTRY) 678 skb_set_hash(q->skb, jhash_1word(hash, 0), 679 PKT_HASH_TYPE_L4); 680 681 reason = FIELD_GET(AIROHA_RXD4_PPE_CPU_REASON, msg1); 682 if (reason == PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED) 683 airoha_ppe_check_skb(ð->ppe->dev, q->skb, hash, 684 false); 685 686 done++; 687 napi_gro_receive(&q->napi, q->skb); 688 q->skb = NULL; 689 continue; 690 free_frag: 691 if (q->skb) { 692 dev_kfree_skb(q->skb); 693 q->skb = NULL; 694 } 695 page_pool_put_full_page(q->page_pool, page, true); 696 } 697 airoha_qdma_fill_rx_queue(q); 698 699 return done; 700 } 701 702 static int airoha_qdma_rx_napi_poll(struct napi_struct *napi, int budget) 703 { 704 struct airoha_queue *q = container_of(napi, struct airoha_queue, napi); 705 int cur, done = 0; 706 707 do { 708 cur = airoha_qdma_rx_process(q, budget - done); 709 done += cur; 710 } while (cur && done < budget); 711 712 if (done < budget && napi_complete(napi)) { 713 struct airoha_qdma *qdma = q->qdma; 714 int i, qid = q - &qdma->q_rx[0]; 715 int intr_reg = qid < RX_DONE_HIGH_OFFSET ? QDMA_INT_REG_IDX1 716 : QDMA_INT_REG_IDX2; 717 718 for (i = 0; i < ARRAY_SIZE(qdma->irq_banks); i++) { 719 if (!(BIT(qid) & RX_IRQ_BANK_PIN_MASK(i))) 720 continue; 721 722 airoha_qdma_irq_enable(&qdma->irq_banks[i], intr_reg, 723 BIT(qid % RX_DONE_HIGH_OFFSET)); 724 } 725 } 726 727 return done; 728 } 729 730 static int airoha_qdma_init_rx_queue(struct airoha_queue *q, 731 struct airoha_qdma *qdma, int ndesc) 732 { 733 const struct page_pool_params pp_params = { 734 .order = 0, 735 .pool_size = 256, 736 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 737 .dma_dir = DMA_FROM_DEVICE, 738 .max_len = PAGE_SIZE, 739 .nid = NUMA_NO_NODE, 740 .dev = qdma->eth->dev, 741 .napi = &q->napi, 742 }; 743 struct airoha_eth *eth = qdma->eth; 744 int qid = q - &qdma->q_rx[0], thr; 745 dma_addr_t dma_addr; 746 747 q->buf_size = PAGE_SIZE / 2; 748 q->qdma = qdma; 749 750 q->entry = devm_kzalloc(eth->dev, ndesc * sizeof(*q->entry), 751 GFP_KERNEL); 752 if (!q->entry) 753 return -ENOMEM; 754 755 q->desc = dmam_alloc_coherent(eth->dev, ndesc * sizeof(*q->desc), 756 &dma_addr, GFP_KERNEL); 757 if (!q->desc) 758 return -ENOMEM; 759 760 q->page_pool = page_pool_create(&pp_params); 761 if (IS_ERR(q->page_pool)) { 762 int err = PTR_ERR(q->page_pool); 763 764 q->page_pool = NULL; 765 return err; 766 } 767 768 q->ndesc = ndesc; 769 netif_napi_add(eth->napi_dev, &q->napi, airoha_qdma_rx_napi_poll); 770 771 airoha_qdma_wr(qdma, REG_RX_RING_BASE(qid), dma_addr); 772 airoha_qdma_rmw(qdma, REG_RX_RING_SIZE(qid), 773 RX_RING_SIZE_MASK, 774 FIELD_PREP(RX_RING_SIZE_MASK, ndesc)); 775 776 thr = clamp(ndesc >> 3, 1, 32); 777 airoha_qdma_rmw(qdma, REG_RX_RING_SIZE(qid), RX_RING_THR_MASK, 778 FIELD_PREP(RX_RING_THR_MASK, thr)); 779 airoha_qdma_rmw(qdma, REG_RX_DMA_IDX(qid), RX_RING_DMA_IDX_MASK, 780 FIELD_PREP(RX_RING_DMA_IDX_MASK, q->head)); 781 airoha_qdma_set(qdma, REG_RX_SCATTER_CFG(qid), RX_RING_SG_EN_MASK); 782 783 airoha_qdma_fill_rx_queue(q); 784 785 return 0; 786 } 787 788 static void airoha_qdma_cleanup_rx_queue(struct airoha_queue *q) 789 { 790 struct airoha_qdma *qdma = q->qdma; 791 struct airoha_eth *eth = qdma->eth; 792 int qid = q - &qdma->q_rx[0]; 793 794 while (q->queued) { 795 struct airoha_queue_entry *e = &q->entry[q->tail]; 796 struct airoha_qdma_desc *desc = &q->desc[q->tail]; 797 struct page *page = virt_to_head_page(e->buf); 798 799 dma_sync_single_for_cpu(eth->dev, e->dma_addr, e->dma_len, 800 page_pool_get_dma_dir(q->page_pool)); 801 page_pool_put_full_page(q->page_pool, page, false); 802 /* Reset DMA descriptor */ 803 WRITE_ONCE(desc->ctrl, 0); 804 WRITE_ONCE(desc->addr, 0); 805 WRITE_ONCE(desc->data, 0); 806 WRITE_ONCE(desc->msg0, 0); 807 WRITE_ONCE(desc->msg1, 0); 808 WRITE_ONCE(desc->msg2, 0); 809 WRITE_ONCE(desc->msg3, 0); 810 811 q->tail = (q->tail + 1) % q->ndesc; 812 q->queued--; 813 } 814 815 q->head = q->tail; 816 /* Set RX_DMA_IDX to RX_CPU_IDX to notify the hw the QDMA RX ring is 817 * empty. 818 */ 819 airoha_qdma_rmw(qdma, REG_RX_CPU_IDX(qid), RX_RING_CPU_IDX_MASK, 820 FIELD_PREP(RX_RING_CPU_IDX_MASK, q->head)); 821 airoha_qdma_rmw(qdma, REG_RX_DMA_IDX(qid), RX_RING_DMA_IDX_MASK, 822 FIELD_PREP(RX_RING_DMA_IDX_MASK, q->tail)); 823 } 824 825 static int airoha_qdma_init_rx(struct airoha_qdma *qdma) 826 { 827 int i; 828 829 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) { 830 int err; 831 832 if (!(RX_DONE_INT_MASK & BIT(i))) { 833 /* rx-queue not binded to irq */ 834 continue; 835 } 836 837 err = airoha_qdma_init_rx_queue(&qdma->q_rx[i], qdma, 838 RX_DSCP_NUM(i)); 839 if (err) 840 return err; 841 } 842 843 return 0; 844 } 845 846 static void airoha_qdma_wake_netdev_txqs(struct airoha_queue *q) 847 { 848 struct airoha_qdma *qdma = q->qdma; 849 struct airoha_eth *eth = qdma->eth; 850 int i, qid = q - &qdma->q_tx[0]; 851 852 for (i = 0; i < ARRAY_SIZE(eth->ports); i++) { 853 struct airoha_gdm_port *port = eth->ports[i]; 854 int j; 855 856 if (!port) 857 continue; 858 859 if (port->qdma != qdma) 860 continue; 861 862 for (j = 0; j < port->dev->num_tx_queues; j++) { 863 if (airoha_qdma_get_txq(qdma, j) != qid) 864 continue; 865 866 netif_wake_subqueue(port->dev, j); 867 } 868 } 869 q->txq_stopped = false; 870 } 871 872 static int airoha_qdma_tx_napi_poll(struct napi_struct *napi, int budget) 873 { 874 struct airoha_tx_irq_queue *irq_q; 875 int id, done = 0, irq_queued; 876 struct airoha_qdma *qdma; 877 struct airoha_eth *eth; 878 u32 status, head; 879 880 irq_q = container_of(napi, struct airoha_tx_irq_queue, napi); 881 qdma = irq_q->qdma; 882 id = irq_q - &qdma->q_tx_irq[0]; 883 eth = qdma->eth; 884 885 status = airoha_qdma_rr(qdma, REG_IRQ_STATUS(id)); 886 head = FIELD_GET(IRQ_HEAD_IDX_MASK, status); 887 head = head % irq_q->size; 888 irq_queued = FIELD_GET(IRQ_ENTRY_LEN_MASK, status); 889 890 while (irq_queued > 0 && done < budget) { 891 u32 qid, val = irq_q->q[head]; 892 struct airoha_qdma_desc *desc; 893 struct airoha_queue_entry *e; 894 struct airoha_queue *q; 895 u32 index, desc_ctrl; 896 struct sk_buff *skb; 897 898 if (val == 0xff) 899 break; 900 901 irq_q->q[head] = 0xff; /* mark as done */ 902 head = (head + 1) % irq_q->size; 903 irq_queued--; 904 done++; 905 906 qid = FIELD_GET(IRQ_RING_IDX_MASK, val); 907 if (qid >= ARRAY_SIZE(qdma->q_tx)) 908 continue; 909 910 q = &qdma->q_tx[qid]; 911 if (!q->ndesc) 912 continue; 913 914 index = FIELD_GET(IRQ_DESC_IDX_MASK, val); 915 if (index >= q->ndesc) 916 continue; 917 918 spin_lock_bh(&q->lock); 919 920 if (!q->queued) 921 goto unlock; 922 923 desc = &q->desc[index]; 924 desc_ctrl = le32_to_cpu(desc->ctrl); 925 926 if (!(desc_ctrl & QDMA_DESC_DONE_MASK) && 927 !(desc_ctrl & QDMA_DESC_DROP_MASK)) 928 goto unlock; 929 930 e = &q->entry[index]; 931 skb = e->skb; 932 933 dma_unmap_single(eth->dev, e->dma_addr, e->dma_len, 934 DMA_TO_DEVICE); 935 e->dma_addr = 0; 936 list_add_tail(&e->list, &q->tx_list); 937 938 WRITE_ONCE(desc->msg0, 0); 939 WRITE_ONCE(desc->msg1, 0); 940 q->queued--; 941 942 if (skb) { 943 struct netdev_queue *txq; 944 945 txq = skb_get_tx_queue(skb->dev, skb); 946 netdev_tx_completed_queue(txq, 1, skb->len); 947 dev_kfree_skb_any(skb); 948 } 949 950 if (q->txq_stopped && q->ndesc - q->queued >= q->free_thr) { 951 /* Since multiple net_device TX queues can share the 952 * same hw QDMA TX queue, there is no guarantee we have 953 * inflight packets queued in hw belonging to a 954 * net_device TX queue stopped in the xmit path. 955 * In order to avoid any potential net_device TX queue 956 * stall, we need to wake all the net_device TX queues 957 * feeding the same hw QDMA TX queue. 958 */ 959 airoha_qdma_wake_netdev_txqs(q); 960 } 961 962 unlock: 963 spin_unlock_bh(&q->lock); 964 } 965 966 if (done) { 967 int i, len = done >> 7; 968 969 for (i = 0; i < len; i++) 970 airoha_qdma_rmw(qdma, REG_IRQ_CLEAR_LEN(id), 971 IRQ_CLEAR_LEN_MASK, 0x80); 972 airoha_qdma_rmw(qdma, REG_IRQ_CLEAR_LEN(id), 973 IRQ_CLEAR_LEN_MASK, (done & 0x7f)); 974 } 975 976 if (done < budget && napi_complete(napi)) 977 airoha_qdma_irq_enable(&qdma->irq_banks[0], QDMA_INT_REG_IDX0, 978 TX_DONE_INT_MASK(id)); 979 980 return done; 981 } 982 983 static int airoha_qdma_init_tx_queue(struct airoha_queue *q, 984 struct airoha_qdma *qdma, int size) 985 { 986 struct airoha_eth *eth = qdma->eth; 987 int i, qid = q - &qdma->q_tx[0]; 988 dma_addr_t dma_addr; 989 990 spin_lock_init(&q->lock); 991 q->qdma = qdma; 992 q->free_thr = 1 + MAX_SKB_FRAGS; 993 INIT_LIST_HEAD(&q->tx_list); 994 995 q->entry = devm_kzalloc(eth->dev, size * sizeof(*q->entry), 996 GFP_KERNEL); 997 if (!q->entry) 998 return -ENOMEM; 999 1000 q->desc = dmam_alloc_coherent(eth->dev, size * sizeof(*q->desc), 1001 &dma_addr, GFP_KERNEL); 1002 if (!q->desc) 1003 return -ENOMEM; 1004 1005 for (i = 0; i < size; i++) { 1006 u32 val = FIELD_PREP(QDMA_DESC_DONE_MASK, 1); 1007 1008 list_add_tail(&q->entry[i].list, &q->tx_list); 1009 WRITE_ONCE(q->desc[i].ctrl, cpu_to_le32(val)); 1010 } 1011 q->ndesc = size; 1012 1013 /* xmit ring drop default setting */ 1014 airoha_qdma_set(qdma, REG_TX_RING_BLOCKING(qid), 1015 TX_RING_IRQ_BLOCKING_TX_DROP_EN_MASK); 1016 1017 airoha_qdma_wr(qdma, REG_TX_RING_BASE(qid), dma_addr); 1018 airoha_qdma_rmw(qdma, REG_TX_CPU_IDX(qid), TX_RING_CPU_IDX_MASK, 1019 FIELD_PREP(TX_RING_CPU_IDX_MASK, 0)); 1020 airoha_qdma_rmw(qdma, REG_TX_DMA_IDX(qid), TX_RING_DMA_IDX_MASK, 1021 FIELD_PREP(TX_RING_DMA_IDX_MASK, 0)); 1022 1023 return 0; 1024 } 1025 1026 static int airoha_qdma_tx_irq_init(struct airoha_tx_irq_queue *irq_q, 1027 struct airoha_qdma *qdma, int size) 1028 { 1029 int id = irq_q - &qdma->q_tx_irq[0]; 1030 struct airoha_eth *eth = qdma->eth; 1031 dma_addr_t dma_addr; 1032 1033 irq_q->q = dmam_alloc_coherent(eth->dev, size * sizeof(u32), 1034 &dma_addr, GFP_KERNEL); 1035 if (!irq_q->q) 1036 return -ENOMEM; 1037 1038 memset(irq_q->q, 0xff, size * sizeof(u32)); 1039 irq_q->size = size; 1040 irq_q->qdma = qdma; 1041 1042 netif_napi_add_tx(eth->napi_dev, &irq_q->napi, 1043 airoha_qdma_tx_napi_poll); 1044 1045 airoha_qdma_wr(qdma, REG_TX_IRQ_BASE(id), dma_addr); 1046 airoha_qdma_rmw(qdma, REG_TX_IRQ_CFG(id), TX_IRQ_DEPTH_MASK, 1047 FIELD_PREP(TX_IRQ_DEPTH_MASK, size)); 1048 airoha_qdma_rmw(qdma, REG_TX_IRQ_CFG(id), TX_IRQ_THR_MASK, 1049 FIELD_PREP(TX_IRQ_THR_MASK, 1)); 1050 1051 return 0; 1052 } 1053 1054 static int airoha_qdma_init_tx(struct airoha_qdma *qdma) 1055 { 1056 int i, err; 1057 1058 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++) { 1059 err = airoha_qdma_tx_irq_init(&qdma->q_tx_irq[i], qdma, 1060 IRQ_QUEUE_LEN(i)); 1061 if (err) 1062 return err; 1063 } 1064 1065 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) { 1066 err = airoha_qdma_init_tx_queue(&qdma->q_tx[i], qdma, 1067 TX_DSCP_NUM); 1068 if (err) 1069 return err; 1070 } 1071 1072 return 0; 1073 } 1074 1075 static void airoha_qdma_cleanup_tx_queue(struct airoha_queue *q) 1076 { 1077 struct airoha_qdma *qdma = q->qdma; 1078 struct airoha_eth *eth = qdma->eth; 1079 int i, qid = q - &qdma->q_tx[0]; 1080 u16 index = 0; 1081 1082 spin_lock_bh(&q->lock); 1083 for (i = 0; i < q->ndesc; i++) { 1084 struct airoha_queue_entry *e = &q->entry[i]; 1085 struct airoha_qdma_desc *desc = &q->desc[i]; 1086 1087 if (!e->dma_addr) 1088 continue; 1089 1090 dma_unmap_single(eth->dev, e->dma_addr, e->dma_len, 1091 DMA_TO_DEVICE); 1092 dev_kfree_skb_any(e->skb); 1093 e->dma_addr = 0; 1094 e->skb = NULL; 1095 list_add_tail(&e->list, &q->tx_list); 1096 1097 /* Reset DMA descriptor */ 1098 WRITE_ONCE(desc->ctrl, 0); 1099 WRITE_ONCE(desc->addr, 0); 1100 WRITE_ONCE(desc->data, 0); 1101 WRITE_ONCE(desc->msg0, 0); 1102 WRITE_ONCE(desc->msg1, 0); 1103 WRITE_ONCE(desc->msg2, 0); 1104 1105 q->queued--; 1106 } 1107 1108 if (!list_empty(&q->tx_list)) { 1109 struct airoha_queue_entry *e; 1110 1111 e = list_first_entry(&q->tx_list, struct airoha_queue_entry, 1112 list); 1113 index = e - q->entry; 1114 } 1115 /* Set TX_DMA_IDX to TX_CPU_IDX to notify the hw the QDMA TX ring is 1116 * empty. 1117 */ 1118 airoha_qdma_rmw(qdma, REG_TX_CPU_IDX(qid), TX_RING_CPU_IDX_MASK, 1119 FIELD_PREP(TX_RING_CPU_IDX_MASK, index)); 1120 airoha_qdma_rmw(qdma, REG_TX_DMA_IDX(qid), TX_RING_DMA_IDX_MASK, 1121 FIELD_PREP(TX_RING_DMA_IDX_MASK, index)); 1122 1123 spin_unlock_bh(&q->lock); 1124 } 1125 1126 static int airoha_qdma_init_hfwd_queues(struct airoha_qdma *qdma) 1127 { 1128 int size, index, num_desc = HW_DSCP_NUM; 1129 struct airoha_eth *eth = qdma->eth; 1130 int id = qdma - ð->qdma[0]; 1131 u32 status, buf_size; 1132 dma_addr_t dma_addr; 1133 const char *name; 1134 1135 name = devm_kasprintf(eth->dev, GFP_KERNEL, "qdma%d-buf", id); 1136 if (!name) 1137 return -ENOMEM; 1138 1139 buf_size = id ? AIROHA_MAX_PACKET_SIZE / 2 : AIROHA_MAX_PACKET_SIZE; 1140 index = of_property_match_string(eth->dev->of_node, 1141 "memory-region-names", name); 1142 if (index >= 0) { 1143 struct reserved_mem *rmem; 1144 struct device_node *np; 1145 1146 /* Consume reserved memory for hw forwarding buffers queue if 1147 * available in the DTS 1148 */ 1149 np = of_parse_phandle(eth->dev->of_node, "memory-region", 1150 index); 1151 if (!np) 1152 return -ENODEV; 1153 1154 rmem = of_reserved_mem_lookup(np); 1155 of_node_put(np); 1156 dma_addr = rmem->base; 1157 /* Compute the number of hw descriptors according to the 1158 * reserved memory size and the payload buffer size 1159 */ 1160 num_desc = div_u64(rmem->size, buf_size); 1161 } else { 1162 size = buf_size * num_desc; 1163 if (!dmam_alloc_coherent(eth->dev, size, &dma_addr, 1164 GFP_KERNEL)) 1165 return -ENOMEM; 1166 } 1167 1168 airoha_qdma_wr(qdma, REG_FWD_BUF_BASE, dma_addr); 1169 1170 size = num_desc * sizeof(struct airoha_qdma_fwd_desc); 1171 if (!dmam_alloc_coherent(eth->dev, size, &dma_addr, GFP_KERNEL)) 1172 return -ENOMEM; 1173 1174 airoha_qdma_wr(qdma, REG_FWD_DSCP_BASE, dma_addr); 1175 /* QDMA0: 2KB. QDMA1: 1KB */ 1176 airoha_qdma_rmw(qdma, REG_HW_FWD_DSCP_CFG, 1177 HW_FWD_DSCP_PAYLOAD_SIZE_MASK, 1178 FIELD_PREP(HW_FWD_DSCP_PAYLOAD_SIZE_MASK, !!id)); 1179 airoha_qdma_rmw(qdma, REG_FWD_DSCP_LOW_THR, FWD_DSCP_LOW_THR_MASK, 1180 FIELD_PREP(FWD_DSCP_LOW_THR_MASK, 128)); 1181 airoha_qdma_rmw(qdma, REG_LMGR_INIT_CFG, 1182 LMGR_INIT_START | LMGR_SRAM_MODE_MASK | 1183 HW_FWD_DESC_NUM_MASK, 1184 FIELD_PREP(HW_FWD_DESC_NUM_MASK, num_desc) | 1185 LMGR_INIT_START | LMGR_SRAM_MODE_MASK); 1186 1187 return read_poll_timeout(airoha_qdma_rr, status, 1188 !(status & LMGR_INIT_START), USEC_PER_MSEC, 1189 30 * USEC_PER_MSEC, true, qdma, 1190 REG_LMGR_INIT_CFG); 1191 } 1192 1193 static void airoha_qdma_init_qos(struct airoha_qdma *qdma) 1194 { 1195 airoha_qdma_clear(qdma, REG_TXWRR_MODE_CFG, TWRR_WEIGHT_SCALE_MASK); 1196 airoha_qdma_set(qdma, REG_TXWRR_MODE_CFG, TWRR_WEIGHT_BASE_MASK); 1197 1198 airoha_qdma_clear(qdma, REG_PSE_BUF_USAGE_CFG, 1199 PSE_BUF_ESTIMATE_EN_MASK); 1200 1201 airoha_qdma_set(qdma, REG_EGRESS_RATE_METER_CFG, 1202 EGRESS_RATE_METER_EN_MASK | 1203 EGRESS_RATE_METER_EQ_RATE_EN_MASK); 1204 /* 2047us x 31 = 63.457ms */ 1205 airoha_qdma_rmw(qdma, REG_EGRESS_RATE_METER_CFG, 1206 EGRESS_RATE_METER_WINDOW_SZ_MASK, 1207 FIELD_PREP(EGRESS_RATE_METER_WINDOW_SZ_MASK, 0x1f)); 1208 airoha_qdma_rmw(qdma, REG_EGRESS_RATE_METER_CFG, 1209 EGRESS_RATE_METER_TIMESLICE_MASK, 1210 FIELD_PREP(EGRESS_RATE_METER_TIMESLICE_MASK, 0x7ff)); 1211 1212 /* ratelimit init */ 1213 airoha_qdma_set(qdma, REG_GLB_TRTCM_CFG, GLB_TRTCM_EN_MASK); 1214 /* fast-tick 25us */ 1215 airoha_qdma_rmw(qdma, REG_GLB_TRTCM_CFG, GLB_FAST_TICK_MASK, 1216 FIELD_PREP(GLB_FAST_TICK_MASK, 25)); 1217 airoha_qdma_rmw(qdma, REG_GLB_TRTCM_CFG, GLB_SLOW_TICK_RATIO_MASK, 1218 FIELD_PREP(GLB_SLOW_TICK_RATIO_MASK, 40)); 1219 1220 airoha_qdma_set(qdma, REG_EGRESS_TRTCM_CFG, EGRESS_TRTCM_EN_MASK); 1221 airoha_qdma_rmw(qdma, REG_EGRESS_TRTCM_CFG, EGRESS_FAST_TICK_MASK, 1222 FIELD_PREP(EGRESS_FAST_TICK_MASK, 25)); 1223 airoha_qdma_rmw(qdma, REG_EGRESS_TRTCM_CFG, 1224 EGRESS_SLOW_TICK_RATIO_MASK, 1225 FIELD_PREP(EGRESS_SLOW_TICK_RATIO_MASK, 40)); 1226 1227 airoha_qdma_set(qdma, REG_INGRESS_TRTCM_CFG, INGRESS_TRTCM_EN_MASK); 1228 airoha_qdma_clear(qdma, REG_INGRESS_TRTCM_CFG, 1229 INGRESS_TRTCM_MODE_MASK); 1230 airoha_qdma_rmw(qdma, REG_INGRESS_TRTCM_CFG, INGRESS_FAST_TICK_MASK, 1231 FIELD_PREP(INGRESS_FAST_TICK_MASK, 125)); 1232 airoha_qdma_rmw(qdma, REG_INGRESS_TRTCM_CFG, 1233 INGRESS_SLOW_TICK_RATIO_MASK, 1234 FIELD_PREP(INGRESS_SLOW_TICK_RATIO_MASK, 8)); 1235 1236 airoha_qdma_set(qdma, REG_SLA_TRTCM_CFG, SLA_TRTCM_EN_MASK); 1237 airoha_qdma_rmw(qdma, REG_SLA_TRTCM_CFG, SLA_FAST_TICK_MASK, 1238 FIELD_PREP(SLA_FAST_TICK_MASK, 25)); 1239 airoha_qdma_rmw(qdma, REG_SLA_TRTCM_CFG, SLA_SLOW_TICK_RATIO_MASK, 1240 FIELD_PREP(SLA_SLOW_TICK_RATIO_MASK, 40)); 1241 } 1242 1243 static void airoha_qdma_init_qos_stats(struct airoha_qdma *qdma) 1244 { 1245 int i; 1246 1247 for (i = 0; i < AIROHA_NUM_QOS_CHANNELS; i++) { 1248 /* Tx-cpu transferred count */ 1249 airoha_qdma_wr(qdma, REG_CNTR_VAL(i << 1), 0); 1250 airoha_qdma_wr(qdma, REG_CNTR_CFG(i << 1), 1251 CNTR_EN_MASK | CNTR_ALL_QUEUE_EN_MASK | 1252 CNTR_ALL_DSCP_RING_EN_MASK | 1253 FIELD_PREP(CNTR_CHAN_MASK, i)); 1254 /* Tx-fwd transferred count */ 1255 airoha_qdma_wr(qdma, REG_CNTR_VAL((i << 1) + 1), 0); 1256 airoha_qdma_wr(qdma, REG_CNTR_CFG(i << 1), 1257 CNTR_EN_MASK | CNTR_ALL_QUEUE_EN_MASK | 1258 CNTR_ALL_DSCP_RING_EN_MASK | 1259 FIELD_PREP(CNTR_SRC_MASK, 1) | 1260 FIELD_PREP(CNTR_CHAN_MASK, i)); 1261 } 1262 } 1263 1264 static int airoha_qdma_hw_init(struct airoha_qdma *qdma) 1265 { 1266 int i; 1267 1268 for (i = 0; i < ARRAY_SIZE(qdma->irq_banks); i++) { 1269 /* clear pending irqs */ 1270 airoha_qdma_wr(qdma, REG_INT_STATUS(i), 0xffffffff); 1271 /* setup rx irqs */ 1272 airoha_qdma_irq_enable(&qdma->irq_banks[i], QDMA_INT_REG_IDX0, 1273 INT_RX0_MASK(RX_IRQ_BANK_PIN_MASK(i))); 1274 airoha_qdma_irq_enable(&qdma->irq_banks[i], QDMA_INT_REG_IDX1, 1275 INT_RX1_MASK(RX_IRQ_BANK_PIN_MASK(i))); 1276 airoha_qdma_irq_enable(&qdma->irq_banks[i], QDMA_INT_REG_IDX2, 1277 INT_RX2_MASK(RX_IRQ_BANK_PIN_MASK(i))); 1278 airoha_qdma_irq_enable(&qdma->irq_banks[i], QDMA_INT_REG_IDX3, 1279 INT_RX3_MASK(RX_IRQ_BANK_PIN_MASK(i))); 1280 } 1281 /* setup tx irqs */ 1282 airoha_qdma_irq_enable(&qdma->irq_banks[0], QDMA_INT_REG_IDX0, 1283 TX_COHERENT_LOW_INT_MASK | INT_TX_MASK); 1284 airoha_qdma_irq_enable(&qdma->irq_banks[0], QDMA_INT_REG_IDX4, 1285 TX_COHERENT_HIGH_INT_MASK); 1286 1287 /* setup irq binding */ 1288 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) { 1289 if (!qdma->q_tx[i].ndesc) 1290 continue; 1291 1292 if (TX_RING_IRQ_BLOCKING_MAP_MASK & BIT(i)) 1293 airoha_qdma_set(qdma, REG_TX_RING_BLOCKING(i), 1294 TX_RING_IRQ_BLOCKING_CFG_MASK); 1295 else 1296 airoha_qdma_clear(qdma, REG_TX_RING_BLOCKING(i), 1297 TX_RING_IRQ_BLOCKING_CFG_MASK); 1298 } 1299 1300 airoha_qdma_wr(qdma, REG_QDMA_GLOBAL_CFG, 1301 FIELD_PREP(GLOBAL_CFG_DMA_PREFERENCE_MASK, 3) | 1302 GLOBAL_CFG_CPU_TXR_RR_MASK | 1303 GLOBAL_CFG_PAYLOAD_BYTE_SWAP_MASK | 1304 GLOBAL_CFG_MULTICAST_MODIFY_FP_MASK | 1305 GLOBAL_CFG_MULTICAST_EN_MASK | 1306 GLOBAL_CFG_IRQ0_EN_MASK | GLOBAL_CFG_IRQ1_EN_MASK | 1307 GLOBAL_CFG_TX_WB_DONE_MASK | 1308 FIELD_PREP(GLOBAL_CFG_MAX_ISSUE_NUM_MASK, 2)); 1309 1310 airoha_qdma_init_qos(qdma); 1311 1312 /* disable qdma rx delay interrupt */ 1313 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) { 1314 if (!qdma->q_rx[i].ndesc) 1315 continue; 1316 1317 airoha_qdma_clear(qdma, REG_RX_DELAY_INT_IDX(i), 1318 RX_DELAY_INT_MASK); 1319 } 1320 1321 airoha_qdma_set(qdma, REG_TXQ_CNGST_CFG, 1322 TXQ_CNGST_DROP_EN | TXQ_CNGST_DEI_DROP_EN); 1323 airoha_qdma_init_qos_stats(qdma); 1324 1325 return 0; 1326 } 1327 1328 static irqreturn_t airoha_irq_handler(int irq, void *dev_instance) 1329 { 1330 struct airoha_irq_bank *irq_bank = dev_instance; 1331 struct airoha_qdma *qdma = irq_bank->qdma; 1332 u32 rx_intr_mask = 0, rx_intr1, rx_intr2; 1333 u32 intr[ARRAY_SIZE(irq_bank->irqmask)]; 1334 int i; 1335 1336 for (i = 0; i < ARRAY_SIZE(intr); i++) { 1337 intr[i] = airoha_qdma_rr(qdma, REG_INT_STATUS(i)); 1338 intr[i] &= irq_bank->irqmask[i]; 1339 airoha_qdma_wr(qdma, REG_INT_STATUS(i), intr[i]); 1340 } 1341 1342 if (!test_bit(DEV_STATE_INITIALIZED, &qdma->eth->state)) 1343 return IRQ_NONE; 1344 1345 rx_intr1 = intr[1] & RX_DONE_LOW_INT_MASK; 1346 if (rx_intr1) { 1347 airoha_qdma_irq_disable(irq_bank, QDMA_INT_REG_IDX1, rx_intr1); 1348 rx_intr_mask |= rx_intr1; 1349 } 1350 1351 rx_intr2 = intr[2] & RX_DONE_HIGH_INT_MASK; 1352 if (rx_intr2) { 1353 airoha_qdma_irq_disable(irq_bank, QDMA_INT_REG_IDX2, rx_intr2); 1354 rx_intr_mask |= (rx_intr2 << 16); 1355 } 1356 1357 for (i = 0; rx_intr_mask && i < ARRAY_SIZE(qdma->q_rx); i++) { 1358 if (!qdma->q_rx[i].ndesc) 1359 continue; 1360 1361 if (rx_intr_mask & BIT(i)) 1362 napi_schedule(&qdma->q_rx[i].napi); 1363 } 1364 1365 if (intr[0] & INT_TX_MASK) { 1366 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++) { 1367 if (!(intr[0] & TX_DONE_INT_MASK(i))) 1368 continue; 1369 1370 airoha_qdma_irq_disable(irq_bank, QDMA_INT_REG_IDX0, 1371 TX_DONE_INT_MASK(i)); 1372 napi_schedule(&qdma->q_tx_irq[i].napi); 1373 } 1374 } 1375 1376 return IRQ_HANDLED; 1377 } 1378 1379 static int airoha_qdma_init_irq_banks(struct platform_device *pdev, 1380 struct airoha_qdma *qdma) 1381 { 1382 struct airoha_eth *eth = qdma->eth; 1383 int i, id = qdma - ð->qdma[0]; 1384 1385 for (i = 0; i < ARRAY_SIZE(qdma->irq_banks); i++) { 1386 struct airoha_irq_bank *irq_bank = &qdma->irq_banks[i]; 1387 int err, irq_index = 4 * id + i; 1388 const char *name; 1389 1390 spin_lock_init(&irq_bank->irq_lock); 1391 irq_bank->qdma = qdma; 1392 1393 irq_bank->irq = platform_get_irq(pdev, irq_index); 1394 if (irq_bank->irq < 0) 1395 return irq_bank->irq; 1396 1397 name = devm_kasprintf(eth->dev, GFP_KERNEL, 1398 KBUILD_MODNAME ".%d", irq_index); 1399 if (!name) 1400 return -ENOMEM; 1401 1402 err = devm_request_irq(eth->dev, irq_bank->irq, 1403 airoha_irq_handler, IRQF_SHARED, name, 1404 irq_bank); 1405 if (err) 1406 return err; 1407 } 1408 1409 return 0; 1410 } 1411 1412 static int airoha_qdma_init(struct platform_device *pdev, 1413 struct airoha_eth *eth, 1414 struct airoha_qdma *qdma) 1415 { 1416 int err, id = qdma - ð->qdma[0]; 1417 const char *res; 1418 1419 qdma->eth = eth; 1420 res = devm_kasprintf(eth->dev, GFP_KERNEL, "qdma%d", id); 1421 if (!res) 1422 return -ENOMEM; 1423 1424 qdma->regs = devm_platform_ioremap_resource_byname(pdev, res); 1425 if (IS_ERR(qdma->regs)) 1426 return dev_err_probe(eth->dev, PTR_ERR(qdma->regs), 1427 "failed to iomap qdma%d regs\n", id); 1428 1429 err = airoha_qdma_init_irq_banks(pdev, qdma); 1430 if (err) 1431 return err; 1432 1433 err = airoha_qdma_init_rx(qdma); 1434 if (err) 1435 return err; 1436 1437 err = airoha_qdma_init_tx(qdma); 1438 if (err) 1439 return err; 1440 1441 err = airoha_qdma_init_hfwd_queues(qdma); 1442 if (err) 1443 return err; 1444 1445 return airoha_qdma_hw_init(qdma); 1446 } 1447 1448 static void airoha_qdma_cleanup(struct airoha_qdma *qdma) 1449 { 1450 int i; 1451 1452 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) { 1453 if (!qdma->q_rx[i].ndesc) 1454 continue; 1455 1456 netif_napi_del(&qdma->q_rx[i].napi); 1457 airoha_qdma_cleanup_rx_queue(&qdma->q_rx[i]); 1458 if (qdma->q_rx[i].page_pool) { 1459 page_pool_destroy(qdma->q_rx[i].page_pool); 1460 qdma->q_rx[i].page_pool = NULL; 1461 } 1462 } 1463 1464 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++) { 1465 if (!qdma->q_tx_irq[i].size) 1466 continue; 1467 1468 netif_napi_del(&qdma->q_tx_irq[i].napi); 1469 } 1470 1471 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) { 1472 if (!qdma->q_tx[i].ndesc) 1473 continue; 1474 1475 airoha_qdma_cleanup_tx_queue(&qdma->q_tx[i]); 1476 } 1477 } 1478 1479 static int airoha_hw_init(struct platform_device *pdev, 1480 struct airoha_eth *eth) 1481 { 1482 int err, i; 1483 1484 /* disable xsi */ 1485 err = reset_control_bulk_assert(eth->soc->num_xsi_rsts, eth->xsi_rsts); 1486 if (err) 1487 return err; 1488 1489 err = reset_control_bulk_assert(ARRAY_SIZE(eth->rsts), eth->rsts); 1490 if (err) 1491 return err; 1492 1493 msleep(20); 1494 err = reset_control_bulk_deassert(ARRAY_SIZE(eth->rsts), eth->rsts); 1495 if (err) 1496 return err; 1497 1498 msleep(20); 1499 err = airoha_fe_init(eth); 1500 if (err) 1501 return err; 1502 1503 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) { 1504 err = airoha_qdma_init(pdev, eth, ð->qdma[i]); 1505 if (err) 1506 goto error; 1507 } 1508 1509 err = airoha_ppe_init(eth); 1510 if (err) 1511 goto error; 1512 1513 set_bit(DEV_STATE_INITIALIZED, ð->state); 1514 1515 return 0; 1516 error: 1517 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) 1518 airoha_qdma_cleanup(ð->qdma[i]); 1519 1520 return err; 1521 } 1522 1523 static void airoha_hw_cleanup(struct airoha_eth *eth) 1524 { 1525 int i; 1526 1527 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) 1528 airoha_qdma_cleanup(ð->qdma[i]); 1529 airoha_ppe_deinit(eth); 1530 } 1531 1532 static void airoha_qdma_start_napi(struct airoha_qdma *qdma) 1533 { 1534 int i; 1535 1536 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++) 1537 napi_enable(&qdma->q_tx_irq[i].napi); 1538 1539 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) { 1540 if (!qdma->q_rx[i].ndesc) 1541 continue; 1542 1543 napi_enable(&qdma->q_rx[i].napi); 1544 } 1545 } 1546 1547 static void airoha_qdma_stop_napi(struct airoha_qdma *qdma) 1548 { 1549 int i; 1550 1551 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++) 1552 napi_disable(&qdma->q_tx_irq[i].napi); 1553 1554 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) { 1555 if (!qdma->q_rx[i].ndesc) 1556 continue; 1557 1558 napi_disable(&qdma->q_rx[i].napi); 1559 } 1560 } 1561 1562 static void airoha_update_hw_stats(struct airoha_gdm_port *port) 1563 { 1564 struct airoha_eth *eth = port->qdma->eth; 1565 u32 val, i = 0; 1566 1567 spin_lock(&port->stats.lock); 1568 u64_stats_update_begin(&port->stats.syncp); 1569 1570 /* TX */ 1571 val = airoha_fe_rr(eth, REG_FE_GDM_TX_OK_PKT_CNT_H(port->id)); 1572 port->stats.tx_ok_pkts += ((u64)val << 32); 1573 val = airoha_fe_rr(eth, REG_FE_GDM_TX_OK_PKT_CNT_L(port->id)); 1574 port->stats.tx_ok_pkts += val; 1575 1576 val = airoha_fe_rr(eth, REG_FE_GDM_TX_OK_BYTE_CNT_H(port->id)); 1577 port->stats.tx_ok_bytes += ((u64)val << 32); 1578 val = airoha_fe_rr(eth, REG_FE_GDM_TX_OK_BYTE_CNT_L(port->id)); 1579 port->stats.tx_ok_bytes += val; 1580 1581 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_DROP_CNT(port->id)); 1582 port->stats.tx_drops += val; 1583 1584 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_BC_CNT(port->id)); 1585 port->stats.tx_broadcast += val; 1586 1587 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_MC_CNT(port->id)); 1588 port->stats.tx_multicast += val; 1589 1590 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_RUNT_CNT(port->id)); 1591 port->stats.tx_len[i] += val; 1592 1593 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_E64_CNT_H(port->id)); 1594 port->stats.tx_len[i] += ((u64)val << 32); 1595 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_E64_CNT_L(port->id)); 1596 port->stats.tx_len[i++] += val; 1597 1598 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L64_CNT_H(port->id)); 1599 port->stats.tx_len[i] += ((u64)val << 32); 1600 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L64_CNT_L(port->id)); 1601 port->stats.tx_len[i++] += val; 1602 1603 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L127_CNT_H(port->id)); 1604 port->stats.tx_len[i] += ((u64)val << 32); 1605 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L127_CNT_L(port->id)); 1606 port->stats.tx_len[i++] += val; 1607 1608 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L255_CNT_H(port->id)); 1609 port->stats.tx_len[i] += ((u64)val << 32); 1610 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L255_CNT_L(port->id)); 1611 port->stats.tx_len[i++] += val; 1612 1613 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L511_CNT_H(port->id)); 1614 port->stats.tx_len[i] += ((u64)val << 32); 1615 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L511_CNT_L(port->id)); 1616 port->stats.tx_len[i++] += val; 1617 1618 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L1023_CNT_H(port->id)); 1619 port->stats.tx_len[i] += ((u64)val << 32); 1620 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L1023_CNT_L(port->id)); 1621 port->stats.tx_len[i++] += val; 1622 1623 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_LONG_CNT(port->id)); 1624 port->stats.tx_len[i++] += val; 1625 1626 /* RX */ 1627 val = airoha_fe_rr(eth, REG_FE_GDM_RX_OK_PKT_CNT_H(port->id)); 1628 port->stats.rx_ok_pkts += ((u64)val << 32); 1629 val = airoha_fe_rr(eth, REG_FE_GDM_RX_OK_PKT_CNT_L(port->id)); 1630 port->stats.rx_ok_pkts += val; 1631 1632 val = airoha_fe_rr(eth, REG_FE_GDM_RX_OK_BYTE_CNT_H(port->id)); 1633 port->stats.rx_ok_bytes += ((u64)val << 32); 1634 val = airoha_fe_rr(eth, REG_FE_GDM_RX_OK_BYTE_CNT_L(port->id)); 1635 port->stats.rx_ok_bytes += val; 1636 1637 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_DROP_CNT(port->id)); 1638 port->stats.rx_drops += val; 1639 1640 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_BC_CNT(port->id)); 1641 port->stats.rx_broadcast += val; 1642 1643 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_MC_CNT(port->id)); 1644 port->stats.rx_multicast += val; 1645 1646 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ERROR_DROP_CNT(port->id)); 1647 port->stats.rx_errors += val; 1648 1649 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_CRC_ERR_CNT(port->id)); 1650 port->stats.rx_crc_error += val; 1651 1652 val = airoha_fe_rr(eth, REG_FE_GDM_RX_OVERFLOW_DROP_CNT(port->id)); 1653 port->stats.rx_over_errors += val; 1654 1655 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_FRAG_CNT(port->id)); 1656 port->stats.rx_fragment += val; 1657 1658 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_JABBER_CNT(port->id)); 1659 port->stats.rx_jabber += val; 1660 1661 i = 0; 1662 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_RUNT_CNT(port->id)); 1663 port->stats.rx_len[i] += val; 1664 1665 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_E64_CNT_H(port->id)); 1666 port->stats.rx_len[i] += ((u64)val << 32); 1667 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_E64_CNT_L(port->id)); 1668 port->stats.rx_len[i++] += val; 1669 1670 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L64_CNT_H(port->id)); 1671 port->stats.rx_len[i] += ((u64)val << 32); 1672 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L64_CNT_L(port->id)); 1673 port->stats.rx_len[i++] += val; 1674 1675 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L127_CNT_H(port->id)); 1676 port->stats.rx_len[i] += ((u64)val << 32); 1677 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L127_CNT_L(port->id)); 1678 port->stats.rx_len[i++] += val; 1679 1680 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L255_CNT_H(port->id)); 1681 port->stats.rx_len[i] += ((u64)val << 32); 1682 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L255_CNT_L(port->id)); 1683 port->stats.rx_len[i++] += val; 1684 1685 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L511_CNT_H(port->id)); 1686 port->stats.rx_len[i] += ((u64)val << 32); 1687 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L511_CNT_L(port->id)); 1688 port->stats.rx_len[i++] += val; 1689 1690 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L1023_CNT_H(port->id)); 1691 port->stats.rx_len[i] += ((u64)val << 32); 1692 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L1023_CNT_L(port->id)); 1693 port->stats.rx_len[i++] += val; 1694 1695 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_LONG_CNT(port->id)); 1696 port->stats.rx_len[i++] += val; 1697 1698 /* reset mib counters */ 1699 airoha_fe_set(eth, REG_FE_GDM_MIB_CLEAR(port->id), 1700 FE_GDM_MIB_RX_CLEAR_MASK | FE_GDM_MIB_TX_CLEAR_MASK); 1701 1702 u64_stats_update_end(&port->stats.syncp); 1703 spin_unlock(&port->stats.lock); 1704 } 1705 1706 static int airoha_dev_open(struct net_device *dev) 1707 { 1708 int err, len = ETH_HLEN + dev->mtu + ETH_FCS_LEN; 1709 struct airoha_gdm_port *port = netdev_priv(dev); 1710 struct airoha_qdma *qdma = port->qdma; 1711 u32 pse_port = FE_PSE_PORT_PPE1; 1712 1713 netif_tx_start_all_queues(dev); 1714 err = airoha_set_vip_for_gdm_port(port, true); 1715 if (err) 1716 return err; 1717 1718 if (netdev_uses_dsa(dev)) 1719 airoha_fe_set(qdma->eth, REG_GDM_INGRESS_CFG(port->id), 1720 GDM_STAG_EN_MASK); 1721 else 1722 airoha_fe_clear(qdma->eth, REG_GDM_INGRESS_CFG(port->id), 1723 GDM_STAG_EN_MASK); 1724 1725 airoha_fe_rmw(qdma->eth, REG_GDM_LEN_CFG(port->id), 1726 GDM_SHORT_LEN_MASK | GDM_LONG_LEN_MASK, 1727 FIELD_PREP(GDM_SHORT_LEN_MASK, 60) | 1728 FIELD_PREP(GDM_LONG_LEN_MASK, len)); 1729 1730 airoha_qdma_set(qdma, REG_QDMA_GLOBAL_CFG, 1731 GLOBAL_CFG_TX_DMA_EN_MASK | 1732 GLOBAL_CFG_RX_DMA_EN_MASK); 1733 atomic_inc(&qdma->users); 1734 1735 if (port->id == AIROHA_GDM2_IDX && 1736 airoha_ppe_is_enabled(qdma->eth, 1)) { 1737 /* For PPE2 always use secondary cpu port. */ 1738 pse_port = FE_PSE_PORT_PPE2; 1739 } 1740 airoha_set_gdm_port_fwd_cfg(qdma->eth, REG_GDM_FWD_CFG(port->id), 1741 pse_port); 1742 1743 return 0; 1744 } 1745 1746 static int airoha_dev_stop(struct net_device *dev) 1747 { 1748 struct airoha_gdm_port *port = netdev_priv(dev); 1749 struct airoha_qdma *qdma = port->qdma; 1750 int i; 1751 1752 netif_tx_disable(dev); 1753 airoha_set_vip_for_gdm_port(port, false); 1754 for (i = 0; i < dev->num_tx_queues; i++) 1755 netdev_tx_reset_subqueue(dev, i); 1756 1757 airoha_set_gdm_port_fwd_cfg(qdma->eth, REG_GDM_FWD_CFG(port->id), 1758 FE_PSE_PORT_DROP); 1759 1760 if (atomic_dec_and_test(&qdma->users)) { 1761 airoha_qdma_clear(qdma, REG_QDMA_GLOBAL_CFG, 1762 GLOBAL_CFG_TX_DMA_EN_MASK | 1763 GLOBAL_CFG_RX_DMA_EN_MASK); 1764 1765 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) { 1766 if (!qdma->q_tx[i].ndesc) 1767 continue; 1768 1769 airoha_qdma_cleanup_tx_queue(&qdma->q_tx[i]); 1770 } 1771 } 1772 1773 return 0; 1774 } 1775 1776 static int airoha_dev_set_macaddr(struct net_device *dev, void *p) 1777 { 1778 struct airoha_gdm_port *port = netdev_priv(dev); 1779 int err; 1780 1781 err = eth_mac_addr(dev, p); 1782 if (err) 1783 return err; 1784 1785 airoha_set_macaddr(port, dev->dev_addr); 1786 1787 return 0; 1788 } 1789 1790 static int airoha_set_gdm2_loopback(struct airoha_gdm_port *port) 1791 { 1792 struct airoha_eth *eth = port->qdma->eth; 1793 u32 val, pse_port, chan; 1794 int i, src_port; 1795 1796 airoha_set_gdm_port_fwd_cfg(eth, REG_GDM_FWD_CFG(AIROHA_GDM2_IDX), 1797 FE_PSE_PORT_DROP); 1798 airoha_fe_clear(eth, REG_GDM_FWD_CFG(AIROHA_GDM2_IDX), 1799 GDM_STRIP_CRC_MASK); 1800 1801 /* Enable GDM2 loopback */ 1802 airoha_fe_wr(eth, REG_GDM_TXCHN_EN(AIROHA_GDM2_IDX), 0xffffffff); 1803 airoha_fe_wr(eth, REG_GDM_RXCHN_EN(AIROHA_GDM2_IDX), 0xffff); 1804 1805 chan = port->id == AIROHA_GDM3_IDX ? airoha_is_7581(eth) ? 4 : 3 : 0; 1806 airoha_fe_rmw(eth, REG_GDM_LPBK_CFG(AIROHA_GDM2_IDX), 1807 LPBK_CHAN_MASK | LPBK_MODE_MASK | LPBK_EN_MASK, 1808 FIELD_PREP(LPBK_CHAN_MASK, chan) | 1809 LBK_GAP_MODE_MASK | LBK_LEN_MODE_MASK | 1810 LBK_CHAN_MODE_MASK | LPBK_EN_MASK); 1811 airoha_fe_rmw(eth, REG_GDM_LEN_CFG(AIROHA_GDM2_IDX), 1812 GDM_SHORT_LEN_MASK | GDM_LONG_LEN_MASK, 1813 FIELD_PREP(GDM_SHORT_LEN_MASK, 60) | 1814 FIELD_PREP(GDM_LONG_LEN_MASK, AIROHA_MAX_MTU)); 1815 /* Forward the traffic to the proper GDM port */ 1816 pse_port = port->id == AIROHA_GDM3_IDX ? FE_PSE_PORT_GDM3 1817 : FE_PSE_PORT_GDM4; 1818 airoha_set_gdm_port_fwd_cfg(eth, REG_GDM_FWD_CFG(AIROHA_GDM2_IDX), 1819 pse_port); 1820 1821 /* Disable VIP and IFC for GDM2 */ 1822 airoha_fe_clear(eth, REG_FE_VIP_PORT_EN, BIT(AIROHA_GDM2_IDX)); 1823 airoha_fe_clear(eth, REG_FE_IFC_PORT_EN, BIT(AIROHA_GDM2_IDX)); 1824 1825 src_port = eth->soc->ops.get_src_port_id(port, port->nbq); 1826 if (src_port < 0) 1827 return src_port; 1828 1829 airoha_fe_rmw(eth, REG_FE_WAN_PORT, 1830 WAN1_EN_MASK | WAN1_MASK | WAN0_MASK, 1831 FIELD_PREP(WAN0_MASK, src_port)); 1832 val = src_port & SP_CPORT_DFT_MASK; 1833 airoha_fe_rmw(eth, 1834 REG_SP_DFT_CPORT(src_port >> fls(SP_CPORT_DFT_MASK)), 1835 SP_CPORT_MASK(val), 1836 __field_prep(SP_CPORT_MASK(val), FE_PSE_PORT_CDM2)); 1837 1838 for (i = 0; i < eth->soc->num_ppe; i++) 1839 airoha_ppe_set_cpu_port(port, i, AIROHA_GDM2_IDX); 1840 1841 if (port->id == AIROHA_GDM4_IDX && airoha_is_7581(eth)) { 1842 u32 mask = FC_ID_OF_SRC_PORT_MASK(port->nbq); 1843 1844 airoha_fe_rmw(eth, REG_SRC_PORT_FC_MAP6, mask, 1845 __field_prep(mask, AIROHA_GDM2_IDX)); 1846 } 1847 1848 return 0; 1849 } 1850 1851 static int airoha_dev_init(struct net_device *dev) 1852 { 1853 struct airoha_gdm_port *port = netdev_priv(dev); 1854 struct airoha_eth *eth = port->eth; 1855 int i; 1856 1857 /* QDMA0 is used for lan ports while QDMA1 is used for WAN ports */ 1858 port->qdma = ð->qdma[!airoha_is_lan_gdm_port(port)]; 1859 port->dev->irq = port->qdma->irq_banks[0].irq; 1860 airoha_set_macaddr(port, dev->dev_addr); 1861 1862 switch (port->id) { 1863 case AIROHA_GDM3_IDX: 1864 case AIROHA_GDM4_IDX: 1865 /* If GDM2 is active we can't enable loopback */ 1866 if (!eth->ports[1]) { 1867 int err; 1868 1869 err = airoha_set_gdm2_loopback(port); 1870 if (err) 1871 return err; 1872 } 1873 break; 1874 default: 1875 break; 1876 } 1877 1878 for (i = 0; i < eth->soc->num_ppe; i++) 1879 airoha_ppe_set_cpu_port(port, i, 1880 airoha_get_fe_port(port)); 1881 1882 return 0; 1883 } 1884 1885 static void airoha_dev_get_stats64(struct net_device *dev, 1886 struct rtnl_link_stats64 *storage) 1887 { 1888 struct airoha_gdm_port *port = netdev_priv(dev); 1889 unsigned int start; 1890 1891 airoha_update_hw_stats(port); 1892 do { 1893 start = u64_stats_fetch_begin(&port->stats.syncp); 1894 storage->rx_packets = port->stats.rx_ok_pkts; 1895 storage->tx_packets = port->stats.tx_ok_pkts; 1896 storage->rx_bytes = port->stats.rx_ok_bytes; 1897 storage->tx_bytes = port->stats.tx_ok_bytes; 1898 storage->multicast = port->stats.rx_multicast; 1899 storage->rx_errors = port->stats.rx_errors; 1900 storage->rx_dropped = port->stats.rx_drops; 1901 storage->tx_dropped = port->stats.tx_drops; 1902 storage->rx_crc_errors = port->stats.rx_crc_error; 1903 storage->rx_over_errors = port->stats.rx_over_errors; 1904 } while (u64_stats_fetch_retry(&port->stats.syncp, start)); 1905 } 1906 1907 static int airoha_dev_change_mtu(struct net_device *dev, int mtu) 1908 { 1909 struct airoha_gdm_port *port = netdev_priv(dev); 1910 struct airoha_eth *eth = port->qdma->eth; 1911 u32 len = ETH_HLEN + mtu + ETH_FCS_LEN; 1912 1913 airoha_fe_rmw(eth, REG_GDM_LEN_CFG(port->id), 1914 GDM_LONG_LEN_MASK, 1915 FIELD_PREP(GDM_LONG_LEN_MASK, len)); 1916 WRITE_ONCE(dev->mtu, mtu); 1917 1918 return 0; 1919 } 1920 1921 static u16 airoha_dev_select_queue(struct net_device *dev, struct sk_buff *skb, 1922 struct net_device *sb_dev) 1923 { 1924 struct airoha_gdm_port *port = netdev_priv(dev); 1925 int queue, channel; 1926 1927 /* For dsa device select QoS channel according to the dsa user port 1928 * index, rely on port id otherwise. Select QoS queue based on the 1929 * skb priority. 1930 */ 1931 channel = netdev_uses_dsa(dev) ? skb_get_queue_mapping(skb) : port->id; 1932 channel = channel % AIROHA_NUM_QOS_CHANNELS; 1933 queue = (skb->priority - 1) % AIROHA_NUM_QOS_QUEUES; /* QoS queue */ 1934 queue = channel * AIROHA_NUM_QOS_QUEUES + queue; 1935 1936 return queue < dev->num_tx_queues ? queue : 0; 1937 } 1938 1939 static u32 airoha_get_dsa_tag(struct sk_buff *skb, struct net_device *dev) 1940 { 1941 #if IS_ENABLED(CONFIG_NET_DSA) 1942 struct ethhdr *ehdr; 1943 u8 xmit_tpid; 1944 u16 tag; 1945 1946 if (!netdev_uses_dsa(dev)) 1947 return 0; 1948 1949 if (dev->dsa_ptr->tag_ops->proto != DSA_TAG_PROTO_MTK) 1950 return 0; 1951 1952 if (skb_cow_head(skb, 0)) 1953 return 0; 1954 1955 ehdr = (struct ethhdr *)skb->data; 1956 tag = be16_to_cpu(ehdr->h_proto); 1957 xmit_tpid = tag >> 8; 1958 1959 switch (xmit_tpid) { 1960 case MTK_HDR_XMIT_TAGGED_TPID_8100: 1961 ehdr->h_proto = cpu_to_be16(ETH_P_8021Q); 1962 tag &= ~(MTK_HDR_XMIT_TAGGED_TPID_8100 << 8); 1963 break; 1964 case MTK_HDR_XMIT_TAGGED_TPID_88A8: 1965 ehdr->h_proto = cpu_to_be16(ETH_P_8021AD); 1966 tag &= ~(MTK_HDR_XMIT_TAGGED_TPID_88A8 << 8); 1967 break; 1968 default: 1969 /* PPE module requires untagged DSA packets to work properly, 1970 * so move DSA tag to DMA descriptor. 1971 */ 1972 memmove(skb->data + MTK_HDR_LEN, skb->data, 2 * ETH_ALEN); 1973 __skb_pull(skb, MTK_HDR_LEN); 1974 break; 1975 } 1976 1977 return tag; 1978 #else 1979 return 0; 1980 #endif 1981 } 1982 1983 int airoha_get_fe_port(struct airoha_gdm_port *port) 1984 { 1985 struct airoha_qdma *qdma = port->qdma; 1986 struct airoha_eth *eth = qdma->eth; 1987 1988 switch (eth->soc->version) { 1989 case 0x7583: 1990 return port->id == AIROHA_GDM3_IDX ? FE_PSE_PORT_GDM3 1991 : port->id; 1992 case 0x7581: 1993 default: 1994 return port->id == AIROHA_GDM4_IDX ? FE_PSE_PORT_GDM4 1995 : port->id; 1996 } 1997 } 1998 1999 static netdev_tx_t airoha_dev_xmit(struct sk_buff *skb, 2000 struct net_device *dev) 2001 { 2002 struct airoha_gdm_port *port = netdev_priv(dev); 2003 struct airoha_qdma *qdma = port->qdma; 2004 u32 nr_frags, tag, msg0, msg1, len; 2005 struct airoha_queue_entry *e; 2006 struct netdev_queue *txq; 2007 struct airoha_queue *q; 2008 LIST_HEAD(tx_list); 2009 int i = 0, qid; 2010 void *data; 2011 u16 index; 2012 u8 fport; 2013 2014 qid = airoha_qdma_get_txq(qdma, skb_get_queue_mapping(skb)); 2015 tag = airoha_get_dsa_tag(skb, dev); 2016 2017 msg0 = FIELD_PREP(QDMA_ETH_TXMSG_CHAN_MASK, 2018 qid / AIROHA_NUM_QOS_QUEUES) | 2019 FIELD_PREP(QDMA_ETH_TXMSG_QUEUE_MASK, 2020 qid % AIROHA_NUM_QOS_QUEUES) | 2021 FIELD_PREP(QDMA_ETH_TXMSG_SP_TAG_MASK, tag); 2022 if (skb->ip_summed == CHECKSUM_PARTIAL) 2023 msg0 |= FIELD_PREP(QDMA_ETH_TXMSG_TCO_MASK, 1) | 2024 FIELD_PREP(QDMA_ETH_TXMSG_UCO_MASK, 1) | 2025 FIELD_PREP(QDMA_ETH_TXMSG_ICO_MASK, 1); 2026 2027 /* TSO: fill MSS info in tcp checksum field */ 2028 if (skb_is_gso(skb)) { 2029 if (skb_cow_head(skb, 0)) 2030 goto error; 2031 2032 if (skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV4 | 2033 SKB_GSO_TCPV6)) { 2034 __be16 csum = cpu_to_be16(skb_shinfo(skb)->gso_size); 2035 2036 tcp_hdr(skb)->check = (__force __sum16)csum; 2037 msg0 |= FIELD_PREP(QDMA_ETH_TXMSG_TSO_MASK, 1); 2038 } 2039 } 2040 2041 fport = airoha_get_fe_port(port); 2042 msg1 = FIELD_PREP(QDMA_ETH_TXMSG_FPORT_MASK, fport) | 2043 FIELD_PREP(QDMA_ETH_TXMSG_METER_MASK, 0x7f); 2044 2045 q = &qdma->q_tx[qid]; 2046 if (WARN_ON_ONCE(!q->ndesc)) 2047 goto error; 2048 2049 spin_lock_bh(&q->lock); 2050 2051 txq = skb_get_tx_queue(dev, skb); 2052 nr_frags = 1 + skb_shinfo(skb)->nr_frags; 2053 2054 if (q->queued + nr_frags >= q->ndesc) { 2055 /* not enough space in the queue */ 2056 netif_tx_stop_queue(txq); 2057 q->txq_stopped = true; 2058 spin_unlock_bh(&q->lock); 2059 return NETDEV_TX_BUSY; 2060 } 2061 2062 len = skb_headlen(skb); 2063 data = skb->data; 2064 2065 e = list_first_entry(&q->tx_list, struct airoha_queue_entry, 2066 list); 2067 index = e - q->entry; 2068 2069 while (true) { 2070 struct airoha_qdma_desc *desc = &q->desc[index]; 2071 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2072 dma_addr_t addr; 2073 u32 val; 2074 2075 addr = dma_map_single(dev->dev.parent, data, len, 2076 DMA_TO_DEVICE); 2077 if (unlikely(dma_mapping_error(dev->dev.parent, addr))) 2078 goto error_unmap; 2079 2080 list_move_tail(&e->list, &tx_list); 2081 e->skb = i == nr_frags - 1 ? skb : NULL; 2082 e->dma_addr = addr; 2083 e->dma_len = len; 2084 2085 e = list_first_entry(&q->tx_list, struct airoha_queue_entry, 2086 list); 2087 index = e - q->entry; 2088 2089 val = FIELD_PREP(QDMA_DESC_LEN_MASK, len); 2090 if (i < nr_frags - 1) 2091 val |= FIELD_PREP(QDMA_DESC_MORE_MASK, 1); 2092 WRITE_ONCE(desc->ctrl, cpu_to_le32(val)); 2093 WRITE_ONCE(desc->addr, cpu_to_le32(addr)); 2094 val = FIELD_PREP(QDMA_DESC_NEXT_ID_MASK, index); 2095 WRITE_ONCE(desc->data, cpu_to_le32(val)); 2096 WRITE_ONCE(desc->msg0, cpu_to_le32(msg0)); 2097 WRITE_ONCE(desc->msg1, cpu_to_le32(msg1)); 2098 WRITE_ONCE(desc->msg2, cpu_to_le32(0xffff)); 2099 2100 if (++i == nr_frags) 2101 break; 2102 2103 data = skb_frag_address(frag); 2104 len = skb_frag_size(frag); 2105 } 2106 q->queued += i; 2107 2108 skb_tx_timestamp(skb); 2109 netdev_tx_sent_queue(txq, skb->len); 2110 if (q->ndesc - q->queued < q->free_thr) { 2111 netif_tx_stop_queue(txq); 2112 q->txq_stopped = true; 2113 } 2114 2115 if (netif_xmit_stopped(txq) || !netdev_xmit_more()) 2116 airoha_qdma_rmw(qdma, REG_TX_CPU_IDX(qid), 2117 TX_RING_CPU_IDX_MASK, 2118 FIELD_PREP(TX_RING_CPU_IDX_MASK, index)); 2119 2120 spin_unlock_bh(&q->lock); 2121 2122 return NETDEV_TX_OK; 2123 2124 error_unmap: 2125 list_for_each_entry(e, &tx_list, list) { 2126 dma_unmap_single(dev->dev.parent, e->dma_addr, e->dma_len, 2127 DMA_TO_DEVICE); 2128 e->dma_addr = 0; 2129 } 2130 list_splice(&tx_list, &q->tx_list); 2131 2132 spin_unlock_bh(&q->lock); 2133 error: 2134 dev_kfree_skb_any(skb); 2135 dev->stats.tx_dropped++; 2136 2137 return NETDEV_TX_OK; 2138 } 2139 2140 static void airoha_ethtool_get_drvinfo(struct net_device *dev, 2141 struct ethtool_drvinfo *info) 2142 { 2143 struct airoha_gdm_port *port = netdev_priv(dev); 2144 struct airoha_eth *eth = port->qdma->eth; 2145 2146 strscpy(info->driver, eth->dev->driver->name, sizeof(info->driver)); 2147 strscpy(info->bus_info, dev_name(eth->dev), sizeof(info->bus_info)); 2148 } 2149 2150 static void airoha_ethtool_get_mac_stats(struct net_device *dev, 2151 struct ethtool_eth_mac_stats *stats) 2152 { 2153 struct airoha_gdm_port *port = netdev_priv(dev); 2154 unsigned int start; 2155 2156 airoha_update_hw_stats(port); 2157 do { 2158 start = u64_stats_fetch_begin(&port->stats.syncp); 2159 stats->FramesTransmittedOK = port->stats.tx_ok_pkts; 2160 stats->OctetsTransmittedOK = port->stats.tx_ok_bytes; 2161 stats->MulticastFramesXmittedOK = port->stats.tx_multicast; 2162 stats->BroadcastFramesXmittedOK = port->stats.tx_broadcast; 2163 stats->FramesReceivedOK = port->stats.rx_ok_pkts; 2164 stats->OctetsReceivedOK = port->stats.rx_ok_bytes; 2165 stats->BroadcastFramesReceivedOK = port->stats.rx_broadcast; 2166 } while (u64_stats_fetch_retry(&port->stats.syncp, start)); 2167 } 2168 2169 static const struct ethtool_rmon_hist_range airoha_ethtool_rmon_ranges[] = { 2170 { 0, 64 }, 2171 { 65, 127 }, 2172 { 128, 255 }, 2173 { 256, 511 }, 2174 { 512, 1023 }, 2175 { 1024, 1518 }, 2176 { 1519, 10239 }, 2177 {}, 2178 }; 2179 2180 static void 2181 airoha_ethtool_get_rmon_stats(struct net_device *dev, 2182 struct ethtool_rmon_stats *stats, 2183 const struct ethtool_rmon_hist_range **ranges) 2184 { 2185 struct airoha_gdm_port *port = netdev_priv(dev); 2186 struct airoha_hw_stats *hw_stats = &port->stats; 2187 unsigned int start; 2188 2189 BUILD_BUG_ON(ARRAY_SIZE(airoha_ethtool_rmon_ranges) != 2190 ARRAY_SIZE(hw_stats->tx_len) + 1); 2191 BUILD_BUG_ON(ARRAY_SIZE(airoha_ethtool_rmon_ranges) != 2192 ARRAY_SIZE(hw_stats->rx_len) + 1); 2193 2194 *ranges = airoha_ethtool_rmon_ranges; 2195 airoha_update_hw_stats(port); 2196 do { 2197 int i; 2198 2199 start = u64_stats_fetch_begin(&port->stats.syncp); 2200 stats->fragments = hw_stats->rx_fragment; 2201 stats->jabbers = hw_stats->rx_jabber; 2202 for (i = 0; i < ARRAY_SIZE(airoha_ethtool_rmon_ranges) - 1; 2203 i++) { 2204 stats->hist[i] = hw_stats->rx_len[i]; 2205 stats->hist_tx[i] = hw_stats->tx_len[i]; 2206 } 2207 } while (u64_stats_fetch_retry(&port->stats.syncp, start)); 2208 } 2209 2210 static int airoha_qdma_set_chan_tx_sched(struct net_device *dev, 2211 int channel, enum tx_sched_mode mode, 2212 const u16 *weights, u8 n_weights) 2213 { 2214 struct airoha_gdm_port *port = netdev_priv(dev); 2215 int i; 2216 2217 for (i = 0; i < AIROHA_NUM_TX_RING; i++) 2218 airoha_qdma_clear(port->qdma, REG_QUEUE_CLOSE_CFG(channel), 2219 TXQ_DISABLE_CHAN_QUEUE_MASK(channel, i)); 2220 2221 for (i = 0; i < n_weights; i++) { 2222 u32 status; 2223 int err; 2224 2225 airoha_qdma_wr(port->qdma, REG_TXWRR_WEIGHT_CFG, 2226 TWRR_RW_CMD_MASK | 2227 FIELD_PREP(TWRR_CHAN_IDX_MASK, channel) | 2228 FIELD_PREP(TWRR_QUEUE_IDX_MASK, i) | 2229 FIELD_PREP(TWRR_VALUE_MASK, weights[i])); 2230 err = read_poll_timeout(airoha_qdma_rr, status, 2231 status & TWRR_RW_CMD_DONE, 2232 USEC_PER_MSEC, 10 * USEC_PER_MSEC, 2233 true, port->qdma, 2234 REG_TXWRR_WEIGHT_CFG); 2235 if (err) 2236 return err; 2237 } 2238 2239 airoha_qdma_rmw(port->qdma, REG_CHAN_QOS_MODE(channel >> 3), 2240 CHAN_QOS_MODE_MASK(channel), 2241 __field_prep(CHAN_QOS_MODE_MASK(channel), mode)); 2242 2243 return 0; 2244 } 2245 2246 static int airoha_qdma_set_tx_prio_sched(struct net_device *dev, int channel) 2247 { 2248 static const u16 w[AIROHA_NUM_QOS_QUEUES] = {}; 2249 2250 return airoha_qdma_set_chan_tx_sched(dev, channel, TC_SCH_SP, w, 2251 ARRAY_SIZE(w)); 2252 } 2253 2254 static int airoha_qdma_set_tx_ets_sched(struct net_device *dev, int channel, 2255 struct tc_ets_qopt_offload *opt) 2256 { 2257 struct tc_ets_qopt_offload_replace_params *p = &opt->replace_params; 2258 enum tx_sched_mode mode = TC_SCH_SP; 2259 u16 w[AIROHA_NUM_QOS_QUEUES] = {}; 2260 int i, nstrict = 0; 2261 2262 if (p->bands > AIROHA_NUM_QOS_QUEUES) 2263 return -EINVAL; 2264 2265 for (i = 0; i < p->bands; i++) { 2266 if (!p->quanta[i]) 2267 nstrict++; 2268 } 2269 2270 /* this configuration is not supported by the hw */ 2271 if (nstrict == AIROHA_NUM_QOS_QUEUES - 1) 2272 return -EINVAL; 2273 2274 /* EN7581 SoC supports fixed QoS band priority where WRR queues have 2275 * lowest priorities with respect to SP ones. 2276 * e.g: WRR0, WRR1, .., WRRm, SP0, SP1, .., SPn 2277 */ 2278 for (i = 0; i < nstrict; i++) { 2279 if (p->priomap[p->bands - i - 1] != i) 2280 return -EINVAL; 2281 } 2282 2283 for (i = 0; i < p->bands - nstrict; i++) { 2284 if (p->priomap[i] != nstrict + i) 2285 return -EINVAL; 2286 2287 w[i] = p->weights[nstrict + i]; 2288 } 2289 2290 if (!nstrict) 2291 mode = TC_SCH_WRR8; 2292 else if (nstrict < AIROHA_NUM_QOS_QUEUES - 1) 2293 mode = nstrict + 1; 2294 2295 return airoha_qdma_set_chan_tx_sched(dev, channel, mode, w, 2296 ARRAY_SIZE(w)); 2297 } 2298 2299 static int airoha_qdma_get_tx_ets_stats(struct net_device *dev, int channel, 2300 struct tc_ets_qopt_offload *opt) 2301 { 2302 struct airoha_gdm_port *port = netdev_priv(dev); 2303 u64 cpu_tx_packets = airoha_qdma_rr(port->qdma, 2304 REG_CNTR_VAL(channel << 1)); 2305 u64 fwd_tx_packets = airoha_qdma_rr(port->qdma, 2306 REG_CNTR_VAL((channel << 1) + 1)); 2307 u64 tx_packets = (cpu_tx_packets - port->cpu_tx_packets) + 2308 (fwd_tx_packets - port->fwd_tx_packets); 2309 2310 _bstats_update(opt->stats.bstats, 0, tx_packets); 2311 2312 port->cpu_tx_packets = cpu_tx_packets; 2313 port->fwd_tx_packets = fwd_tx_packets; 2314 2315 return 0; 2316 } 2317 2318 static int airoha_tc_setup_qdisc_ets(struct net_device *dev, 2319 struct tc_ets_qopt_offload *opt) 2320 { 2321 int channel; 2322 2323 if (opt->parent == TC_H_ROOT) 2324 return -EINVAL; 2325 2326 channel = TC_H_MAJ(opt->handle) >> 16; 2327 channel = channel % AIROHA_NUM_QOS_CHANNELS; 2328 2329 switch (opt->command) { 2330 case TC_ETS_REPLACE: 2331 return airoha_qdma_set_tx_ets_sched(dev, channel, opt); 2332 case TC_ETS_DESTROY: 2333 /* PRIO is default qdisc scheduler */ 2334 return airoha_qdma_set_tx_prio_sched(dev, channel); 2335 case TC_ETS_STATS: 2336 return airoha_qdma_get_tx_ets_stats(dev, channel, opt); 2337 default: 2338 return -EOPNOTSUPP; 2339 } 2340 } 2341 2342 static int airoha_qdma_get_rl_param(struct airoha_qdma *qdma, int queue_id, 2343 u32 addr, enum trtcm_param_type param, 2344 u32 *val_low, u32 *val_high) 2345 { 2346 u32 idx = QDMA_METER_IDX(queue_id), group = QDMA_METER_GROUP(queue_id); 2347 u32 val, config = FIELD_PREP(RATE_LIMIT_PARAM_TYPE_MASK, param) | 2348 FIELD_PREP(RATE_LIMIT_METER_GROUP_MASK, group) | 2349 FIELD_PREP(RATE_LIMIT_PARAM_INDEX_MASK, idx); 2350 2351 airoha_qdma_wr(qdma, REG_TRTCM_CFG_PARAM(addr), config); 2352 if (read_poll_timeout(airoha_qdma_rr, val, 2353 val & RATE_LIMIT_PARAM_RW_DONE_MASK, 2354 USEC_PER_MSEC, 10 * USEC_PER_MSEC, true, qdma, 2355 REG_TRTCM_CFG_PARAM(addr))) 2356 return -ETIMEDOUT; 2357 2358 *val_low = airoha_qdma_rr(qdma, REG_TRTCM_DATA_LOW(addr)); 2359 if (val_high) 2360 *val_high = airoha_qdma_rr(qdma, REG_TRTCM_DATA_HIGH(addr)); 2361 2362 return 0; 2363 } 2364 2365 static int airoha_qdma_set_rl_param(struct airoha_qdma *qdma, int queue_id, 2366 u32 addr, enum trtcm_param_type param, 2367 u32 val) 2368 { 2369 u32 idx = QDMA_METER_IDX(queue_id), group = QDMA_METER_GROUP(queue_id); 2370 u32 config = RATE_LIMIT_PARAM_RW_MASK | 2371 FIELD_PREP(RATE_LIMIT_PARAM_TYPE_MASK, param) | 2372 FIELD_PREP(RATE_LIMIT_METER_GROUP_MASK, group) | 2373 FIELD_PREP(RATE_LIMIT_PARAM_INDEX_MASK, idx); 2374 2375 airoha_qdma_wr(qdma, REG_TRTCM_DATA_LOW(addr), val); 2376 airoha_qdma_wr(qdma, REG_TRTCM_CFG_PARAM(addr), config); 2377 2378 return read_poll_timeout(airoha_qdma_rr, val, 2379 val & RATE_LIMIT_PARAM_RW_DONE_MASK, 2380 USEC_PER_MSEC, 10 * USEC_PER_MSEC, true, 2381 qdma, REG_TRTCM_CFG_PARAM(addr)); 2382 } 2383 2384 static int airoha_qdma_set_rl_config(struct airoha_qdma *qdma, int queue_id, 2385 u32 addr, bool enable, u32 enable_mask) 2386 { 2387 u32 val; 2388 int err; 2389 2390 err = airoha_qdma_get_rl_param(qdma, queue_id, addr, TRTCM_MISC_MODE, 2391 &val, NULL); 2392 if (err) 2393 return err; 2394 2395 val = enable ? val | enable_mask : val & ~enable_mask; 2396 2397 return airoha_qdma_set_rl_param(qdma, queue_id, addr, TRTCM_MISC_MODE, 2398 val); 2399 } 2400 2401 static int airoha_qdma_set_rl_token_bucket(struct airoha_qdma *qdma, 2402 int queue_id, u32 rate_val, 2403 u32 bucket_size) 2404 { 2405 u32 val, config, tick, unit, rate, rate_frac; 2406 int err; 2407 2408 err = airoha_qdma_get_rl_param(qdma, queue_id, REG_INGRESS_TRTCM_CFG, 2409 TRTCM_MISC_MODE, &config, NULL); 2410 if (err) 2411 return err; 2412 2413 val = airoha_qdma_rr(qdma, REG_INGRESS_TRTCM_CFG); 2414 tick = FIELD_GET(INGRESS_FAST_TICK_MASK, val); 2415 if (config & TRTCM_TICK_SEL) 2416 tick *= FIELD_GET(INGRESS_SLOW_TICK_RATIO_MASK, val); 2417 if (!tick) 2418 return -EINVAL; 2419 2420 unit = (config & TRTCM_PKT_MODE) ? 1000000 / tick : 8000 / tick; 2421 if (!unit) 2422 return -EINVAL; 2423 2424 rate = rate_val / unit; 2425 rate_frac = rate_val % unit; 2426 rate_frac = FIELD_PREP(TRTCM_TOKEN_RATE_MASK, rate_frac) / unit; 2427 rate = FIELD_PREP(TRTCM_TOKEN_RATE_MASK, rate) | 2428 FIELD_PREP(TRTCM_TOKEN_RATE_FRACTION_MASK, rate_frac); 2429 2430 err = airoha_qdma_set_rl_param(qdma, queue_id, REG_INGRESS_TRTCM_CFG, 2431 TRTCM_TOKEN_RATE_MODE, rate); 2432 if (err) 2433 return err; 2434 2435 val = bucket_size; 2436 if (!(config & TRTCM_PKT_MODE)) 2437 val = max_t(u32, val, MIN_TOKEN_SIZE); 2438 val = min_t(u32, __fls(val), MAX_TOKEN_SIZE_OFFSET); 2439 2440 return airoha_qdma_set_rl_param(qdma, queue_id, REG_INGRESS_TRTCM_CFG, 2441 TRTCM_BUCKETSIZE_SHIFT_MODE, val); 2442 } 2443 2444 static int airoha_qdma_init_rl_config(struct airoha_qdma *qdma, int queue_id, 2445 bool enable, enum trtcm_unit_type unit) 2446 { 2447 bool tick_sel = queue_id == 0 || queue_id == 2 || queue_id == 8; 2448 enum trtcm_param mode = TRTCM_METER_MODE; 2449 int err; 2450 2451 mode |= unit == TRTCM_PACKET_UNIT ? TRTCM_PKT_MODE : 0; 2452 err = airoha_qdma_set_rl_config(qdma, queue_id, REG_INGRESS_TRTCM_CFG, 2453 enable, mode); 2454 if (err) 2455 return err; 2456 2457 return airoha_qdma_set_rl_config(qdma, queue_id, REG_INGRESS_TRTCM_CFG, 2458 tick_sel, TRTCM_TICK_SEL); 2459 } 2460 2461 static int airoha_qdma_get_trtcm_param(struct airoha_qdma *qdma, int channel, 2462 u32 addr, enum trtcm_param_type param, 2463 enum trtcm_mode_type mode, 2464 u32 *val_low, u32 *val_high) 2465 { 2466 u32 idx = QDMA_METER_IDX(channel), group = QDMA_METER_GROUP(channel); 2467 u32 val, config = FIELD_PREP(TRTCM_PARAM_TYPE_MASK, param) | 2468 FIELD_PREP(TRTCM_METER_GROUP_MASK, group) | 2469 FIELD_PREP(TRTCM_PARAM_INDEX_MASK, idx) | 2470 FIELD_PREP(TRTCM_PARAM_RATE_TYPE_MASK, mode); 2471 2472 airoha_qdma_wr(qdma, REG_TRTCM_CFG_PARAM(addr), config); 2473 if (read_poll_timeout(airoha_qdma_rr, val, 2474 val & TRTCM_PARAM_RW_DONE_MASK, 2475 USEC_PER_MSEC, 10 * USEC_PER_MSEC, true, 2476 qdma, REG_TRTCM_CFG_PARAM(addr))) 2477 return -ETIMEDOUT; 2478 2479 *val_low = airoha_qdma_rr(qdma, REG_TRTCM_DATA_LOW(addr)); 2480 if (val_high) 2481 *val_high = airoha_qdma_rr(qdma, REG_TRTCM_DATA_HIGH(addr)); 2482 2483 return 0; 2484 } 2485 2486 static int airoha_qdma_set_trtcm_param(struct airoha_qdma *qdma, int channel, 2487 u32 addr, enum trtcm_param_type param, 2488 enum trtcm_mode_type mode, u32 val) 2489 { 2490 u32 idx = QDMA_METER_IDX(channel), group = QDMA_METER_GROUP(channel); 2491 u32 config = TRTCM_PARAM_RW_MASK | 2492 FIELD_PREP(TRTCM_PARAM_TYPE_MASK, param) | 2493 FIELD_PREP(TRTCM_METER_GROUP_MASK, group) | 2494 FIELD_PREP(TRTCM_PARAM_INDEX_MASK, idx) | 2495 FIELD_PREP(TRTCM_PARAM_RATE_TYPE_MASK, mode); 2496 2497 airoha_qdma_wr(qdma, REG_TRTCM_DATA_LOW(addr), val); 2498 airoha_qdma_wr(qdma, REG_TRTCM_CFG_PARAM(addr), config); 2499 2500 return read_poll_timeout(airoha_qdma_rr, val, 2501 val & TRTCM_PARAM_RW_DONE_MASK, 2502 USEC_PER_MSEC, 10 * USEC_PER_MSEC, true, 2503 qdma, REG_TRTCM_CFG_PARAM(addr)); 2504 } 2505 2506 static int airoha_qdma_set_trtcm_config(struct airoha_qdma *qdma, int channel, 2507 u32 addr, enum trtcm_mode_type mode, 2508 bool enable, u32 enable_mask) 2509 { 2510 u32 val; 2511 2512 if (airoha_qdma_get_trtcm_param(qdma, channel, addr, TRTCM_MISC_MODE, 2513 mode, &val, NULL)) 2514 return -EINVAL; 2515 2516 val = enable ? val | enable_mask : val & ~enable_mask; 2517 2518 return airoha_qdma_set_trtcm_param(qdma, channel, addr, TRTCM_MISC_MODE, 2519 mode, val); 2520 } 2521 2522 static int airoha_qdma_set_trtcm_token_bucket(struct airoha_qdma *qdma, 2523 int channel, u32 addr, 2524 enum trtcm_mode_type mode, 2525 u32 rate_val, u32 bucket_size) 2526 { 2527 u32 val, config, tick, unit, rate, rate_frac; 2528 int err; 2529 2530 if (airoha_qdma_get_trtcm_param(qdma, channel, addr, TRTCM_MISC_MODE, 2531 mode, &config, NULL)) 2532 return -EINVAL; 2533 2534 val = airoha_qdma_rr(qdma, addr); 2535 tick = FIELD_GET(INGRESS_FAST_TICK_MASK, val); 2536 if (config & TRTCM_TICK_SEL) 2537 tick *= FIELD_GET(INGRESS_SLOW_TICK_RATIO_MASK, val); 2538 if (!tick) 2539 return -EINVAL; 2540 2541 unit = (config & TRTCM_PKT_MODE) ? 1000000 / tick : 8000 / tick; 2542 if (!unit) 2543 return -EINVAL; 2544 2545 rate = rate_val / unit; 2546 rate_frac = rate_val % unit; 2547 rate_frac = FIELD_PREP(TRTCM_TOKEN_RATE_MASK, rate_frac) / unit; 2548 rate = FIELD_PREP(TRTCM_TOKEN_RATE_MASK, rate) | 2549 FIELD_PREP(TRTCM_TOKEN_RATE_FRACTION_MASK, rate_frac); 2550 2551 err = airoha_qdma_set_trtcm_param(qdma, channel, addr, 2552 TRTCM_TOKEN_RATE_MODE, mode, rate); 2553 if (err) 2554 return err; 2555 2556 val = max_t(u32, bucket_size, MIN_TOKEN_SIZE); 2557 val = min_t(u32, __fls(val), MAX_TOKEN_SIZE_OFFSET); 2558 2559 return airoha_qdma_set_trtcm_param(qdma, channel, addr, 2560 TRTCM_BUCKETSIZE_SHIFT_MODE, 2561 mode, val); 2562 } 2563 2564 static int airoha_qdma_set_tx_rate_limit(struct net_device *dev, 2565 int channel, u32 rate, 2566 u32 bucket_size) 2567 { 2568 struct airoha_gdm_port *port = netdev_priv(dev); 2569 int i, err; 2570 2571 for (i = 0; i <= TRTCM_PEAK_MODE; i++) { 2572 err = airoha_qdma_set_trtcm_config(port->qdma, channel, 2573 REG_EGRESS_TRTCM_CFG, i, 2574 !!rate, TRTCM_METER_MODE); 2575 if (err) 2576 return err; 2577 2578 err = airoha_qdma_set_trtcm_token_bucket(port->qdma, channel, 2579 REG_EGRESS_TRTCM_CFG, 2580 i, rate, bucket_size); 2581 if (err) 2582 return err; 2583 } 2584 2585 return 0; 2586 } 2587 2588 static int airoha_tc_htb_alloc_leaf_queue(struct net_device *dev, 2589 struct tc_htb_qopt_offload *opt) 2590 { 2591 u32 channel = TC_H_MIN(opt->classid) % AIROHA_NUM_QOS_CHANNELS; 2592 u32 rate = div_u64(opt->rate, 1000) << 3; /* kbps */ 2593 int err, num_tx_queues = dev->real_num_tx_queues; 2594 struct airoha_gdm_port *port = netdev_priv(dev); 2595 2596 if (opt->parent_classid != TC_HTB_CLASSID_ROOT) { 2597 NL_SET_ERR_MSG_MOD(opt->extack, "invalid parent classid"); 2598 return -EINVAL; 2599 } 2600 2601 err = airoha_qdma_set_tx_rate_limit(dev, channel, rate, opt->quantum); 2602 if (err) { 2603 NL_SET_ERR_MSG_MOD(opt->extack, 2604 "failed configuring htb offload"); 2605 return err; 2606 } 2607 2608 if (opt->command == TC_HTB_NODE_MODIFY) 2609 return 0; 2610 2611 err = netif_set_real_num_tx_queues(dev, num_tx_queues + 1); 2612 if (err) { 2613 airoha_qdma_set_tx_rate_limit(dev, channel, 0, opt->quantum); 2614 NL_SET_ERR_MSG_MOD(opt->extack, 2615 "failed setting real_num_tx_queues"); 2616 return err; 2617 } 2618 2619 set_bit(channel, port->qos_sq_bmap); 2620 opt->qid = AIROHA_NUM_TX_RING + channel; 2621 2622 return 0; 2623 } 2624 2625 static int airoha_qdma_set_rx_meter(struct airoha_gdm_port *port, 2626 u32 rate, u32 bucket_size, 2627 enum trtcm_unit_type unit_type) 2628 { 2629 struct airoha_qdma *qdma = port->qdma; 2630 int i; 2631 2632 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) { 2633 int err; 2634 2635 if (!qdma->q_rx[i].ndesc) 2636 continue; 2637 2638 err = airoha_qdma_init_rl_config(qdma, i, !!rate, unit_type); 2639 if (err) 2640 return err; 2641 2642 err = airoha_qdma_set_rl_token_bucket(qdma, i, rate, 2643 bucket_size); 2644 if (err) 2645 return err; 2646 } 2647 2648 return 0; 2649 } 2650 2651 static int airoha_tc_matchall_act_validate(struct tc_cls_matchall_offload *f) 2652 { 2653 const struct flow_action *actions = &f->rule->action; 2654 const struct flow_action_entry *act; 2655 2656 if (!flow_action_has_entries(actions)) { 2657 NL_SET_ERR_MSG_MOD(f->common.extack, 2658 "filter run with no actions"); 2659 return -EINVAL; 2660 } 2661 2662 if (!flow_offload_has_one_action(actions)) { 2663 NL_SET_ERR_MSG_MOD(f->common.extack, 2664 "only once action per filter is supported"); 2665 return -EOPNOTSUPP; 2666 } 2667 2668 act = &actions->entries[0]; 2669 if (act->id != FLOW_ACTION_POLICE) { 2670 NL_SET_ERR_MSG_MOD(f->common.extack, "unsupported action"); 2671 return -EOPNOTSUPP; 2672 } 2673 2674 if (act->police.exceed.act_id != FLOW_ACTION_DROP) { 2675 NL_SET_ERR_MSG_MOD(f->common.extack, 2676 "invalid exceed action id"); 2677 return -EOPNOTSUPP; 2678 } 2679 2680 if (act->police.notexceed.act_id != FLOW_ACTION_ACCEPT) { 2681 NL_SET_ERR_MSG_MOD(f->common.extack, 2682 "invalid notexceed action id"); 2683 return -EOPNOTSUPP; 2684 } 2685 2686 if (act->police.notexceed.act_id == FLOW_ACTION_ACCEPT && 2687 !flow_action_is_last_entry(actions, act)) { 2688 NL_SET_ERR_MSG_MOD(f->common.extack, 2689 "action accept must be last"); 2690 return -EOPNOTSUPP; 2691 } 2692 2693 if (act->police.peakrate_bytes_ps || act->police.avrate || 2694 act->police.overhead || act->police.mtu) { 2695 NL_SET_ERR_MSG_MOD(f->common.extack, 2696 "peakrate/avrate/overhead/mtu unsupported"); 2697 return -EOPNOTSUPP; 2698 } 2699 2700 return 0; 2701 } 2702 2703 static int airoha_dev_tc_matchall(struct net_device *dev, 2704 struct tc_cls_matchall_offload *f) 2705 { 2706 enum trtcm_unit_type unit_type = TRTCM_BYTE_UNIT; 2707 struct airoha_gdm_port *port = netdev_priv(dev); 2708 u32 rate = 0, bucket_size = 0; 2709 2710 switch (f->command) { 2711 case TC_CLSMATCHALL_REPLACE: { 2712 const struct flow_action_entry *act; 2713 int err; 2714 2715 err = airoha_tc_matchall_act_validate(f); 2716 if (err) 2717 return err; 2718 2719 act = &f->rule->action.entries[0]; 2720 if (act->police.rate_pkt_ps) { 2721 rate = act->police.rate_pkt_ps; 2722 bucket_size = act->police.burst_pkt; 2723 unit_type = TRTCM_PACKET_UNIT; 2724 } else { 2725 rate = div_u64(act->police.rate_bytes_ps, 1000); 2726 rate = rate << 3; /* Kbps */ 2727 bucket_size = act->police.burst; 2728 } 2729 fallthrough; 2730 } 2731 case TC_CLSMATCHALL_DESTROY: 2732 return airoha_qdma_set_rx_meter(port, rate, bucket_size, 2733 unit_type); 2734 default: 2735 return -EOPNOTSUPP; 2736 } 2737 } 2738 2739 static int airoha_dev_setup_tc_block_cb(enum tc_setup_type type, 2740 void *type_data, void *cb_priv) 2741 { 2742 struct net_device *dev = cb_priv; 2743 struct airoha_gdm_port *port = netdev_priv(dev); 2744 struct airoha_eth *eth = port->qdma->eth; 2745 2746 if (!tc_can_offload(dev)) 2747 return -EOPNOTSUPP; 2748 2749 switch (type) { 2750 case TC_SETUP_CLSFLOWER: 2751 return airoha_ppe_setup_tc_block_cb(ð->ppe->dev, type_data); 2752 case TC_SETUP_CLSMATCHALL: 2753 return airoha_dev_tc_matchall(dev, type_data); 2754 default: 2755 return -EOPNOTSUPP; 2756 } 2757 } 2758 2759 static int airoha_dev_setup_tc_block(struct net_device *dev, 2760 struct flow_block_offload *f) 2761 { 2762 flow_setup_cb_t *cb = airoha_dev_setup_tc_block_cb; 2763 static LIST_HEAD(block_cb_list); 2764 struct flow_block_cb *block_cb; 2765 2766 if (f->binder_type != FLOW_BLOCK_BINDER_TYPE_CLSACT_INGRESS) 2767 return -EOPNOTSUPP; 2768 2769 f->driver_block_list = &block_cb_list; 2770 switch (f->command) { 2771 case FLOW_BLOCK_BIND: 2772 block_cb = flow_block_cb_lookup(f->block, cb, dev); 2773 if (block_cb) { 2774 flow_block_cb_incref(block_cb); 2775 return 0; 2776 } 2777 block_cb = flow_block_cb_alloc(cb, dev, dev, NULL); 2778 if (IS_ERR(block_cb)) 2779 return PTR_ERR(block_cb); 2780 2781 flow_block_cb_incref(block_cb); 2782 flow_block_cb_add(block_cb, f); 2783 list_add_tail(&block_cb->driver_list, &block_cb_list); 2784 return 0; 2785 case FLOW_BLOCK_UNBIND: 2786 block_cb = flow_block_cb_lookup(f->block, cb, dev); 2787 if (!block_cb) 2788 return -ENOENT; 2789 2790 if (!flow_block_cb_decref(block_cb)) { 2791 flow_block_cb_remove(block_cb, f); 2792 list_del(&block_cb->driver_list); 2793 } 2794 return 0; 2795 default: 2796 return -EOPNOTSUPP; 2797 } 2798 } 2799 2800 static void airoha_tc_remove_htb_queue(struct net_device *dev, int queue) 2801 { 2802 struct airoha_gdm_port *port = netdev_priv(dev); 2803 2804 netif_set_real_num_tx_queues(dev, dev->real_num_tx_queues - 1); 2805 airoha_qdma_set_tx_rate_limit(dev, queue + 1, 0, 0); 2806 clear_bit(queue, port->qos_sq_bmap); 2807 } 2808 2809 static int airoha_tc_htb_delete_leaf_queue(struct net_device *dev, 2810 struct tc_htb_qopt_offload *opt) 2811 { 2812 u32 channel = TC_H_MIN(opt->classid) % AIROHA_NUM_QOS_CHANNELS; 2813 struct airoha_gdm_port *port = netdev_priv(dev); 2814 2815 if (!test_bit(channel, port->qos_sq_bmap)) { 2816 NL_SET_ERR_MSG_MOD(opt->extack, "invalid queue id"); 2817 return -EINVAL; 2818 } 2819 2820 airoha_tc_remove_htb_queue(dev, channel); 2821 2822 return 0; 2823 } 2824 2825 static int airoha_tc_htb_destroy(struct net_device *dev) 2826 { 2827 struct airoha_gdm_port *port = netdev_priv(dev); 2828 int q; 2829 2830 for_each_set_bit(q, port->qos_sq_bmap, AIROHA_NUM_QOS_CHANNELS) 2831 airoha_tc_remove_htb_queue(dev, q); 2832 2833 return 0; 2834 } 2835 2836 static int airoha_tc_get_htb_get_leaf_queue(struct net_device *dev, 2837 struct tc_htb_qopt_offload *opt) 2838 { 2839 u32 channel = TC_H_MIN(opt->classid) % AIROHA_NUM_QOS_CHANNELS; 2840 struct airoha_gdm_port *port = netdev_priv(dev); 2841 2842 if (!test_bit(channel, port->qos_sq_bmap)) { 2843 NL_SET_ERR_MSG_MOD(opt->extack, "invalid queue id"); 2844 return -EINVAL; 2845 } 2846 2847 opt->qid = AIROHA_NUM_TX_RING + channel; 2848 2849 return 0; 2850 } 2851 2852 static int airoha_tc_setup_qdisc_htb(struct net_device *dev, 2853 struct tc_htb_qopt_offload *opt) 2854 { 2855 switch (opt->command) { 2856 case TC_HTB_CREATE: 2857 break; 2858 case TC_HTB_DESTROY: 2859 return airoha_tc_htb_destroy(dev); 2860 case TC_HTB_NODE_MODIFY: 2861 case TC_HTB_LEAF_ALLOC_QUEUE: 2862 return airoha_tc_htb_alloc_leaf_queue(dev, opt); 2863 case TC_HTB_LEAF_DEL: 2864 case TC_HTB_LEAF_DEL_LAST: 2865 case TC_HTB_LEAF_DEL_LAST_FORCE: 2866 return airoha_tc_htb_delete_leaf_queue(dev, opt); 2867 case TC_HTB_LEAF_QUERY_QUEUE: 2868 return airoha_tc_get_htb_get_leaf_queue(dev, opt); 2869 default: 2870 return -EOPNOTSUPP; 2871 } 2872 2873 return 0; 2874 } 2875 2876 static int airoha_dev_tc_setup(struct net_device *dev, enum tc_setup_type type, 2877 void *type_data) 2878 { 2879 switch (type) { 2880 case TC_SETUP_QDISC_ETS: 2881 return airoha_tc_setup_qdisc_ets(dev, type_data); 2882 case TC_SETUP_QDISC_HTB: 2883 return airoha_tc_setup_qdisc_htb(dev, type_data); 2884 case TC_SETUP_BLOCK: 2885 case TC_SETUP_FT: 2886 return airoha_dev_setup_tc_block(dev, type_data); 2887 default: 2888 return -EOPNOTSUPP; 2889 } 2890 } 2891 2892 static const struct net_device_ops airoha_netdev_ops = { 2893 .ndo_init = airoha_dev_init, 2894 .ndo_open = airoha_dev_open, 2895 .ndo_stop = airoha_dev_stop, 2896 .ndo_change_mtu = airoha_dev_change_mtu, 2897 .ndo_select_queue = airoha_dev_select_queue, 2898 .ndo_start_xmit = airoha_dev_xmit, 2899 .ndo_get_stats64 = airoha_dev_get_stats64, 2900 .ndo_set_mac_address = airoha_dev_set_macaddr, 2901 .ndo_setup_tc = airoha_dev_tc_setup, 2902 }; 2903 2904 static const struct ethtool_ops airoha_ethtool_ops = { 2905 .get_drvinfo = airoha_ethtool_get_drvinfo, 2906 .get_eth_mac_stats = airoha_ethtool_get_mac_stats, 2907 .get_rmon_stats = airoha_ethtool_get_rmon_stats, 2908 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2909 .get_link = ethtool_op_get_link, 2910 }; 2911 2912 static int airoha_metadata_dst_alloc(struct airoha_gdm_port *port) 2913 { 2914 int i; 2915 2916 for (i = 0; i < ARRAY_SIZE(port->dsa_meta); i++) { 2917 struct metadata_dst *md_dst; 2918 2919 md_dst = metadata_dst_alloc(0, METADATA_HW_PORT_MUX, 2920 GFP_KERNEL); 2921 if (!md_dst) 2922 return -ENOMEM; 2923 2924 md_dst->u.port_info.port_id = i; 2925 port->dsa_meta[i] = md_dst; 2926 } 2927 2928 return 0; 2929 } 2930 2931 static void airoha_metadata_dst_free(struct airoha_gdm_port *port) 2932 { 2933 int i; 2934 2935 for (i = 0; i < ARRAY_SIZE(port->dsa_meta); i++) { 2936 if (!port->dsa_meta[i]) 2937 continue; 2938 2939 dst_release(&port->dsa_meta[i]->dst); 2940 } 2941 } 2942 2943 bool airoha_is_valid_gdm_port(struct airoha_eth *eth, 2944 struct airoha_gdm_port *port) 2945 { 2946 int i; 2947 2948 for (i = 0; i < ARRAY_SIZE(eth->ports); i++) { 2949 if (eth->ports[i] == port) 2950 return true; 2951 } 2952 2953 return false; 2954 } 2955 2956 static int airoha_alloc_gdm_port(struct airoha_eth *eth, 2957 struct device_node *np) 2958 { 2959 const __be32 *id_ptr = of_get_property(np, "reg", NULL); 2960 struct airoha_gdm_port *port; 2961 struct net_device *dev; 2962 int err, p; 2963 u32 id; 2964 2965 if (!id_ptr) { 2966 dev_err(eth->dev, "missing gdm port id\n"); 2967 return -EINVAL; 2968 } 2969 2970 id = be32_to_cpup(id_ptr); 2971 p = id - 1; 2972 2973 if (!id || id > ARRAY_SIZE(eth->ports)) { 2974 dev_err(eth->dev, "invalid gdm port id: %d\n", id); 2975 return -EINVAL; 2976 } 2977 2978 if (eth->ports[p]) { 2979 dev_err(eth->dev, "duplicate gdm port id: %d\n", id); 2980 return -EINVAL; 2981 } 2982 2983 dev = devm_alloc_etherdev_mqs(eth->dev, sizeof(*port), 2984 AIROHA_NUM_NETDEV_TX_RINGS, 2985 AIROHA_NUM_RX_RING); 2986 if (!dev) { 2987 dev_err(eth->dev, "alloc_etherdev failed\n"); 2988 return -ENOMEM; 2989 } 2990 2991 dev->netdev_ops = &airoha_netdev_ops; 2992 dev->ethtool_ops = &airoha_ethtool_ops; 2993 dev->max_mtu = AIROHA_MAX_MTU; 2994 dev->watchdog_timeo = 5 * HZ; 2995 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | 2996 NETIF_F_TSO6 | NETIF_F_IPV6_CSUM | 2997 NETIF_F_SG | NETIF_F_TSO | 2998 NETIF_F_HW_TC; 2999 dev->features |= dev->hw_features; 3000 dev->vlan_features = dev->hw_features; 3001 dev->dev.of_node = np; 3002 SET_NETDEV_DEV(dev, eth->dev); 3003 3004 /* reserve hw queues for HTB offloading */ 3005 err = netif_set_real_num_tx_queues(dev, AIROHA_NUM_TX_RING); 3006 if (err) 3007 return err; 3008 3009 err = of_get_ethdev_address(np, dev); 3010 if (err) { 3011 if (err == -EPROBE_DEFER) 3012 return err; 3013 3014 eth_hw_addr_random(dev); 3015 dev_info(eth->dev, "generated random MAC address %pM\n", 3016 dev->dev_addr); 3017 } 3018 3019 port = netdev_priv(dev); 3020 u64_stats_init(&port->stats.syncp); 3021 spin_lock_init(&port->stats.lock); 3022 port->eth = eth; 3023 port->dev = dev; 3024 port->id = id; 3025 /* XXX: Read nbq from DTS */ 3026 port->nbq = id == AIROHA_GDM3_IDX && airoha_is_7581(eth) ? 4 : 0; 3027 eth->ports[p] = port; 3028 3029 return airoha_metadata_dst_alloc(port); 3030 } 3031 3032 static int airoha_register_gdm_devices(struct airoha_eth *eth) 3033 { 3034 int i; 3035 3036 for (i = 0; i < ARRAY_SIZE(eth->ports); i++) { 3037 struct airoha_gdm_port *port = eth->ports[i]; 3038 int err; 3039 3040 if (!port) 3041 continue; 3042 3043 err = register_netdev(port->dev); 3044 if (err) 3045 return err; 3046 } 3047 3048 set_bit(DEV_STATE_REGISTERED, ð->state); 3049 3050 return 0; 3051 } 3052 3053 static int airoha_probe(struct platform_device *pdev) 3054 { 3055 struct reset_control_bulk_data *xsi_rsts; 3056 struct device_node *np; 3057 struct airoha_eth *eth; 3058 int i, err; 3059 3060 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL); 3061 if (!eth) 3062 return -ENOMEM; 3063 3064 eth->soc = of_device_get_match_data(&pdev->dev); 3065 if (!eth->soc) 3066 return -EINVAL; 3067 3068 eth->dev = &pdev->dev; 3069 3070 err = dma_set_mask_and_coherent(eth->dev, DMA_BIT_MASK(32)); 3071 if (err) { 3072 dev_err(eth->dev, "failed configuring DMA mask\n"); 3073 return err; 3074 } 3075 3076 eth->fe_regs = devm_platform_ioremap_resource_byname(pdev, "fe"); 3077 if (IS_ERR(eth->fe_regs)) 3078 return dev_err_probe(eth->dev, PTR_ERR(eth->fe_regs), 3079 "failed to iomap fe regs\n"); 3080 3081 eth->rsts[0].id = "fe"; 3082 eth->rsts[1].id = "pdma"; 3083 eth->rsts[2].id = "qdma"; 3084 err = devm_reset_control_bulk_get_exclusive(eth->dev, 3085 ARRAY_SIZE(eth->rsts), 3086 eth->rsts); 3087 if (err) { 3088 dev_err(eth->dev, "failed to get bulk reset lines\n"); 3089 return err; 3090 } 3091 3092 xsi_rsts = devm_kcalloc(eth->dev, 3093 eth->soc->num_xsi_rsts, sizeof(*xsi_rsts), 3094 GFP_KERNEL); 3095 if (!xsi_rsts) 3096 return -ENOMEM; 3097 3098 eth->xsi_rsts = xsi_rsts; 3099 for (i = 0; i < eth->soc->num_xsi_rsts; i++) 3100 eth->xsi_rsts[i].id = eth->soc->xsi_rsts_names[i]; 3101 3102 err = devm_reset_control_bulk_get_exclusive(eth->dev, 3103 eth->soc->num_xsi_rsts, 3104 eth->xsi_rsts); 3105 if (err) { 3106 dev_err(eth->dev, "failed to get bulk xsi reset lines\n"); 3107 return err; 3108 } 3109 3110 eth->napi_dev = alloc_netdev_dummy(0); 3111 if (!eth->napi_dev) 3112 return -ENOMEM; 3113 3114 /* Enable threaded NAPI by default */ 3115 eth->napi_dev->threaded = true; 3116 strscpy(eth->napi_dev->name, "qdma_eth", sizeof(eth->napi_dev->name)); 3117 platform_set_drvdata(pdev, eth); 3118 3119 err = airoha_hw_init(pdev, eth); 3120 if (err) 3121 goto error_netdev_free; 3122 3123 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) 3124 airoha_qdma_start_napi(ð->qdma[i]); 3125 3126 for_each_child_of_node(pdev->dev.of_node, np) { 3127 if (!of_device_is_compatible(np, "airoha,eth-mac")) 3128 continue; 3129 3130 if (!of_device_is_available(np)) 3131 continue; 3132 3133 err = airoha_alloc_gdm_port(eth, np); 3134 if (err) { 3135 of_node_put(np); 3136 goto error_napi_stop; 3137 } 3138 } 3139 3140 err = airoha_register_gdm_devices(eth); 3141 if (err) 3142 goto error_napi_stop; 3143 3144 return 0; 3145 3146 error_napi_stop: 3147 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) 3148 airoha_qdma_stop_napi(ð->qdma[i]); 3149 3150 for (i = 0; i < ARRAY_SIZE(eth->ports); i++) { 3151 struct airoha_gdm_port *port = eth->ports[i]; 3152 3153 if (!port) 3154 continue; 3155 3156 if (port->dev->reg_state == NETREG_REGISTERED) 3157 unregister_netdev(port->dev); 3158 airoha_metadata_dst_free(port); 3159 } 3160 airoha_hw_cleanup(eth); 3161 error_netdev_free: 3162 free_netdev(eth->napi_dev); 3163 platform_set_drvdata(pdev, NULL); 3164 3165 return err; 3166 } 3167 3168 static void airoha_remove(struct platform_device *pdev) 3169 { 3170 struct airoha_eth *eth = platform_get_drvdata(pdev); 3171 int i; 3172 3173 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) 3174 airoha_qdma_stop_napi(ð->qdma[i]); 3175 3176 for (i = 0; i < ARRAY_SIZE(eth->ports); i++) { 3177 struct airoha_gdm_port *port = eth->ports[i]; 3178 3179 if (!port) 3180 continue; 3181 3182 unregister_netdev(port->dev); 3183 airoha_metadata_dst_free(port); 3184 } 3185 airoha_hw_cleanup(eth); 3186 3187 free_netdev(eth->napi_dev); 3188 platform_set_drvdata(pdev, NULL); 3189 } 3190 3191 static const char * const en7581_xsi_rsts_names[] = { 3192 "xsi-mac", 3193 "hsi0-mac", 3194 "hsi1-mac", 3195 "hsi-mac", 3196 "xfp-mac", 3197 }; 3198 3199 static int airoha_en7581_get_src_port_id(struct airoha_gdm_port *port, int nbq) 3200 { 3201 switch (port->id) { 3202 case AIROHA_GDM3_IDX: 3203 /* 7581 SoC supports PCIe serdes on GDM3 port */ 3204 if (nbq == 4) 3205 return HSGMII_LAN_7581_PCIE0_SRCPORT; 3206 if (nbq == 5) 3207 return HSGMII_LAN_7581_PCIE1_SRCPORT; 3208 break; 3209 case AIROHA_GDM4_IDX: 3210 /* 7581 SoC supports eth and usb serdes on GDM4 port */ 3211 if (!nbq) 3212 return HSGMII_LAN_7581_ETH_SRCPORT; 3213 if (nbq == 1) 3214 return HSGMII_LAN_7581_USB_SRCPORT; 3215 break; 3216 default: 3217 break; 3218 } 3219 3220 return -EINVAL; 3221 } 3222 3223 static u32 airoha_en7581_get_vip_port(struct airoha_gdm_port *port, int nbq) 3224 { 3225 switch (port->id) { 3226 case AIROHA_GDM3_IDX: 3227 if (nbq == 4) 3228 return XSI_PCIE0_VIP_PORT_MASK; 3229 if (nbq == 5) 3230 return XSI_PCIE1_VIP_PORT_MASK; 3231 break; 3232 case AIROHA_GDM4_IDX: 3233 if (!nbq) 3234 return XSI_ETH_VIP_PORT_MASK; 3235 if (nbq == 1) 3236 return XSI_USB_VIP_PORT_MASK; 3237 break; 3238 default: 3239 break; 3240 } 3241 3242 return 0; 3243 } 3244 3245 static const char * const an7583_xsi_rsts_names[] = { 3246 "xsi-mac", 3247 "hsi0-mac", 3248 "hsi1-mac", 3249 "xfp-mac", 3250 }; 3251 3252 static int airoha_an7583_get_src_port_id(struct airoha_gdm_port *port, int nbq) 3253 { 3254 switch (port->id) { 3255 case AIROHA_GDM3_IDX: 3256 /* 7583 SoC supports eth serdes on GDM3 port */ 3257 if (!nbq) 3258 return HSGMII_LAN_7583_ETH_SRCPORT; 3259 break; 3260 case AIROHA_GDM4_IDX: 3261 /* 7583 SoC supports PCIe and USB serdes on GDM4 port */ 3262 if (!nbq) 3263 return HSGMII_LAN_7583_PCIE_SRCPORT; 3264 if (nbq == 1) 3265 return HSGMII_LAN_7583_USB_SRCPORT; 3266 break; 3267 default: 3268 break; 3269 } 3270 3271 return -EINVAL; 3272 } 3273 3274 static u32 airoha_an7583_get_vip_port(struct airoha_gdm_port *port, int nbq) 3275 { 3276 switch (port->id) { 3277 case AIROHA_GDM3_IDX: 3278 if (!nbq) 3279 return XSI_ETH_VIP_PORT_MASK; 3280 break; 3281 case AIROHA_GDM4_IDX: 3282 if (!nbq) 3283 return XSI_PCIE0_VIP_PORT_MASK; 3284 if (nbq == 1) 3285 return XSI_USB_VIP_PORT_MASK; 3286 break; 3287 default: 3288 break; 3289 } 3290 3291 return 0; 3292 } 3293 3294 static const struct airoha_eth_soc_data en7581_soc_data = { 3295 .version = 0x7581, 3296 .xsi_rsts_names = en7581_xsi_rsts_names, 3297 .num_xsi_rsts = ARRAY_SIZE(en7581_xsi_rsts_names), 3298 .num_ppe = 2, 3299 .ops = { 3300 .get_src_port_id = airoha_en7581_get_src_port_id, 3301 .get_vip_port = airoha_en7581_get_vip_port, 3302 }, 3303 }; 3304 3305 static const struct airoha_eth_soc_data an7583_soc_data = { 3306 .version = 0x7583, 3307 .xsi_rsts_names = an7583_xsi_rsts_names, 3308 .num_xsi_rsts = ARRAY_SIZE(an7583_xsi_rsts_names), 3309 .num_ppe = 1, 3310 .ops = { 3311 .get_src_port_id = airoha_an7583_get_src_port_id, 3312 .get_vip_port = airoha_an7583_get_vip_port, 3313 }, 3314 }; 3315 3316 static const struct of_device_id of_airoha_match[] = { 3317 { .compatible = "airoha,en7581-eth", .data = &en7581_soc_data }, 3318 { .compatible = "airoha,an7583-eth", .data = &an7583_soc_data }, 3319 { /* sentinel */ } 3320 }; 3321 MODULE_DEVICE_TABLE(of, of_airoha_match); 3322 3323 static struct platform_driver airoha_driver = { 3324 .probe = airoha_probe, 3325 .remove = airoha_remove, 3326 .driver = { 3327 .name = KBUILD_MODNAME, 3328 .of_match_table = of_airoha_match, 3329 }, 3330 }; 3331 module_platform_driver(airoha_driver); 3332 3333 MODULE_LICENSE("GPL"); 3334 MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>"); 3335 MODULE_DESCRIPTION("Ethernet driver for Airoha SoC"); 3336