1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
3 // Copyright (c) 2017-2018, Linaro Limited
4
5 #include <linux/module.h>
6 #include <linux/init.h>
7 #include <linux/platform_device.h>
8 #include <linux/cleanup.h>
9 #include <linux/device.h>
10 #include <linux/wait.h>
11 #include <linux/bitops.h>
12 #include <linux/regulator/consumer.h>
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/kernel.h>
16 #include <linux/slimbus.h>
17 #include <sound/soc.h>
18 #include <sound/pcm_params.h>
19 #include <sound/soc-dapm.h>
20 #include <linux/gpio/consumer.h>
21 #include <linux/of.h>
22 #include <linux/of_irq.h>
23 #include <sound/tlv.h>
24 #include <sound/info.h>
25 #include "wcd9335.h"
26 #include "wcd-clsh-v2.h"
27
28 #include <dt-bindings/sound/qcom,wcd9335.h>
29
30 #define WCD9335_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
31 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
32 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
33 /* Fractional Rates */
34 #define WCD9335_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100)
35 #define WCD9335_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \
36 SNDRV_PCM_FMTBIT_S24_LE)
37
38 /* slave port water mark level
39 * (0: 6bytes, 1: 9bytes, 2: 12 bytes, 3: 15 bytes)
40 */
41 #define SLAVE_PORT_WATER_MARK_6BYTES 0
42 #define SLAVE_PORT_WATER_MARK_9BYTES 1
43 #define SLAVE_PORT_WATER_MARK_12BYTES 2
44 #define SLAVE_PORT_WATER_MARK_15BYTES 3
45 #define SLAVE_PORT_WATER_MARK_SHIFT 1
46 #define SLAVE_PORT_ENABLE 1
47 #define SLAVE_PORT_DISABLE 0
48 #define WCD9335_SLIM_WATER_MARK_VAL \
49 ((SLAVE_PORT_WATER_MARK_12BYTES << SLAVE_PORT_WATER_MARK_SHIFT) | \
50 (SLAVE_PORT_ENABLE))
51
52 #define WCD9335_SLIM_NUM_PORT_REG 3
53 #define WCD9335_SLIM_PGD_PORT_INT_TX_EN0 (WCD9335_SLIM_PGD_PORT_INT_EN0 + 2)
54
55 #define WCD9335_MCLK_CLK_12P288MHZ 12288000
56 #define WCD9335_MCLK_CLK_9P6MHZ 9600000
57
58 #define WCD9335_SLIM_CLOSE_TIMEOUT 1000
59 #define WCD9335_SLIM_IRQ_OVERFLOW (1 << 0)
60 #define WCD9335_SLIM_IRQ_UNDERFLOW (1 << 1)
61 #define WCD9335_SLIM_IRQ_PORT_CLOSED (1 << 2)
62
63 #define WCD9335_NUM_INTERPOLATORS 9
64 #define WCD9335_RX_START 16
65 #define WCD9335_SLIM_CH_START 128
66 #define WCD9335_MAX_MICBIAS 4
67 #define WCD9335_MAX_VALID_ADC_MUX 13
68 #define WCD9335_INVALID_ADC_MUX 9
69
70 #define TX_HPF_CUT_OFF_FREQ_MASK 0x60
71 #define CF_MIN_3DB_4HZ 0x0
72 #define CF_MIN_3DB_75HZ 0x1
73 #define CF_MIN_3DB_150HZ 0x2
74 #define WCD9335_DMIC_CLK_DIV_2 0x0
75 #define WCD9335_DMIC_CLK_DIV_3 0x1
76 #define WCD9335_DMIC_CLK_DIV_4 0x2
77 #define WCD9335_DMIC_CLK_DIV_6 0x3
78 #define WCD9335_DMIC_CLK_DIV_8 0x4
79 #define WCD9335_DMIC_CLK_DIV_16 0x5
80 #define WCD9335_DMIC_CLK_DRIVE_DEFAULT 0x02
81 #define WCD9335_AMIC_PWR_LEVEL_LP 0
82 #define WCD9335_AMIC_PWR_LEVEL_DEFAULT 1
83 #define WCD9335_AMIC_PWR_LEVEL_HP 2
84 #define WCD9335_AMIC_PWR_LVL_MASK 0x60
85 #define WCD9335_AMIC_PWR_LVL_SHIFT 0x5
86
87 #define WCD9335_DEC_PWR_LVL_MASK 0x06
88 #define WCD9335_DEC_PWR_LVL_LP 0x02
89 #define WCD9335_DEC_PWR_LVL_HP 0x04
90 #define WCD9335_DEC_PWR_LVL_DF 0x00
91
92 #define WCD9335_SLIM_RX_CH(p) \
93 {.port = p + WCD9335_RX_START, .shift = p,}
94
95 #define WCD9335_SLIM_TX_CH(p) \
96 {.port = p, .shift = p,}
97
98 /* vout step value */
99 #define WCD9335_CALCULATE_VOUT_D(req_mv) (((req_mv - 650) * 10) / 25)
100
101 #define WCD9335_INTERPOLATOR_PATH(id) \
102 {"RX INT" #id "_1 MIX1 INP0", "RX0", "SLIM RX0"}, \
103 {"RX INT" #id "_1 MIX1 INP0", "RX1", "SLIM RX1"}, \
104 {"RX INT" #id "_1 MIX1 INP0", "RX2", "SLIM RX2"}, \
105 {"RX INT" #id "_1 MIX1 INP0", "RX3", "SLIM RX3"}, \
106 {"RX INT" #id "_1 MIX1 INP0", "RX4", "SLIM RX4"}, \
107 {"RX INT" #id "_1 MIX1 INP0", "RX5", "SLIM RX5"}, \
108 {"RX INT" #id "_1 MIX1 INP0", "RX6", "SLIM RX6"}, \
109 {"RX INT" #id "_1 MIX1 INP0", "RX7", "SLIM RX7"}, \
110 {"RX INT" #id "_1 MIX1 INP1", "RX0", "SLIM RX0"}, \
111 {"RX INT" #id "_1 MIX1 INP1", "RX1", "SLIM RX1"}, \
112 {"RX INT" #id "_1 MIX1 INP1", "RX2", "SLIM RX2"}, \
113 {"RX INT" #id "_1 MIX1 INP1", "RX3", "SLIM RX3"}, \
114 {"RX INT" #id "_1 MIX1 INP1", "RX4", "SLIM RX4"}, \
115 {"RX INT" #id "_1 MIX1 INP1", "RX5", "SLIM RX5"}, \
116 {"RX INT" #id "_1 MIX1 INP1", "RX6", "SLIM RX6"}, \
117 {"RX INT" #id "_1 MIX1 INP1", "RX7", "SLIM RX7"}, \
118 {"RX INT" #id "_1 MIX1 INP2", "RX0", "SLIM RX0"}, \
119 {"RX INT" #id "_1 MIX1 INP2", "RX1", "SLIM RX1"}, \
120 {"RX INT" #id "_1 MIX1 INP2", "RX2", "SLIM RX2"}, \
121 {"RX INT" #id "_1 MIX1 INP2", "RX3", "SLIM RX3"}, \
122 {"RX INT" #id "_1 MIX1 INP2", "RX4", "SLIM RX4"}, \
123 {"RX INT" #id "_1 MIX1 INP2", "RX5", "SLIM RX5"}, \
124 {"RX INT" #id "_1 MIX1 INP2", "RX6", "SLIM RX6"}, \
125 {"RX INT" #id "_1 MIX1 INP2", "RX7", "SLIM RX7"}, \
126 {"RX INT" #id "_2 MUX", "RX0", "SLIM RX0"}, \
127 {"RX INT" #id "_2 MUX", "RX1", "SLIM RX1"}, \
128 {"RX INT" #id "_2 MUX", "RX2", "SLIM RX2"}, \
129 {"RX INT" #id "_2 MUX", "RX3", "SLIM RX3"}, \
130 {"RX INT" #id "_2 MUX", "RX4", "SLIM RX4"}, \
131 {"RX INT" #id "_2 MUX", "RX5", "SLIM RX5"}, \
132 {"RX INT" #id "_2 MUX", "RX6", "SLIM RX6"}, \
133 {"RX INT" #id "_2 MUX", "RX7", "SLIM RX7"}, \
134 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP0"}, \
135 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP1"}, \
136 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP2"}, \
137 {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_2 MUX"}, \
138 {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_1 MIX1"}, \
139 {"RX INT" #id " MIX2", NULL, "RX INT" #id " SEC MIX"}, \
140 {"RX INT" #id " INTERP", NULL, "RX INT" #id " MIX2"}
141
142 #define WCD9335_ADC_MUX_PATH(id) \
143 {"AIF1_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \
144 {"AIF2_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \
145 {"AIF3_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \
146 {"SLIM TX" #id " MUX", "DEC" #id, "ADC MUX" #id}, \
147 {"ADC MUX" #id, "DMIC", "DMIC MUX" #id}, \
148 {"ADC MUX" #id, "AMIC", "AMIC MUX" #id}, \
149 {"DMIC MUX" #id, "DMIC0", "DMIC0"}, \
150 {"DMIC MUX" #id, "DMIC1", "DMIC1"}, \
151 {"DMIC MUX" #id, "DMIC2", "DMIC2"}, \
152 {"DMIC MUX" #id, "DMIC3", "DMIC3"}, \
153 {"DMIC MUX" #id, "DMIC4", "DMIC4"}, \
154 {"DMIC MUX" #id, "DMIC5", "DMIC5"}, \
155 {"AMIC MUX" #id, "ADC1", "ADC1"}, \
156 {"AMIC MUX" #id, "ADC2", "ADC2"}, \
157 {"AMIC MUX" #id, "ADC3", "ADC3"}, \
158 {"AMIC MUX" #id, "ADC4", "ADC4"}, \
159 {"AMIC MUX" #id, "ADC5", "ADC5"}, \
160 {"AMIC MUX" #id, "ADC6", "ADC6"}
161
162 #define NUM_CODEC_DAIS 7
163
164 enum {
165 WCD9335_RX0 = 0,
166 WCD9335_RX1,
167 WCD9335_RX2,
168 WCD9335_RX3,
169 WCD9335_RX4,
170 WCD9335_RX5,
171 WCD9335_RX6,
172 WCD9335_RX7,
173 WCD9335_RX8,
174 WCD9335_RX9,
175 WCD9335_RX10,
176 WCD9335_RX11,
177 WCD9335_RX12,
178 WCD9335_RX_MAX,
179 };
180
181 enum {
182 WCD9335_TX0 = 0,
183 WCD9335_TX1,
184 WCD9335_TX2,
185 WCD9335_TX3,
186 WCD9335_TX4,
187 WCD9335_TX5,
188 WCD9335_TX6,
189 WCD9335_TX7,
190 WCD9335_TX8,
191 WCD9335_TX9,
192 WCD9335_TX10,
193 WCD9335_TX11,
194 WCD9335_TX12,
195 WCD9335_TX13,
196 WCD9335_TX14,
197 WCD9335_TX15,
198 WCD9335_TX_MAX,
199 };
200
201 enum {
202 SIDO_SOURCE_INTERNAL = 0,
203 SIDO_SOURCE_RCO_BG,
204 };
205
206 enum wcd9335_sido_voltage {
207 SIDO_VOLTAGE_SVS_MV = 950,
208 SIDO_VOLTAGE_NOMINAL_MV = 1100,
209 };
210
211 enum {
212 COMPANDER_1, /* HPH_L */
213 COMPANDER_2, /* HPH_R */
214 COMPANDER_3, /* LO1_DIFF */
215 COMPANDER_4, /* LO2_DIFF */
216 COMPANDER_5, /* LO3_SE */
217 COMPANDER_6, /* LO4_SE */
218 COMPANDER_7, /* SWR SPK CH1 */
219 COMPANDER_8, /* SWR SPK CH2 */
220 COMPANDER_MAX,
221 };
222
223 enum {
224 INTn_2_INP_SEL_ZERO = 0,
225 INTn_2_INP_SEL_RX0,
226 INTn_2_INP_SEL_RX1,
227 INTn_2_INP_SEL_RX2,
228 INTn_2_INP_SEL_RX3,
229 INTn_2_INP_SEL_RX4,
230 INTn_2_INP_SEL_RX5,
231 INTn_2_INP_SEL_RX6,
232 INTn_2_INP_SEL_RX7,
233 INTn_2_INP_SEL_PROXIMITY,
234 };
235
236 enum {
237 INTn_1_MIX_INP_SEL_ZERO = 0,
238 INTn_1_MIX_INP_SEL_DEC0,
239 INTn_1_MIX_INP_SEL_DEC1,
240 INTn_1_MIX_INP_SEL_IIR0,
241 INTn_1_MIX_INP_SEL_IIR1,
242 INTn_1_MIX_INP_SEL_RX0,
243 INTn_1_MIX_INP_SEL_RX1,
244 INTn_1_MIX_INP_SEL_RX2,
245 INTn_1_MIX_INP_SEL_RX3,
246 INTn_1_MIX_INP_SEL_RX4,
247 INTn_1_MIX_INP_SEL_RX5,
248 INTn_1_MIX_INP_SEL_RX6,
249 INTn_1_MIX_INP_SEL_RX7,
250
251 };
252
253 enum {
254 INTERP_EAR = 0,
255 INTERP_HPHL,
256 INTERP_HPHR,
257 INTERP_LO1,
258 INTERP_LO2,
259 INTERP_LO3,
260 INTERP_LO4,
261 INTERP_SPKR1,
262 INTERP_SPKR2,
263 };
264
265 enum wcd_clock_type {
266 WCD_CLK_OFF,
267 WCD_CLK_RCO,
268 WCD_CLK_MCLK,
269 };
270
271 enum {
272 MIC_BIAS_1 = 1,
273 MIC_BIAS_2,
274 MIC_BIAS_3,
275 MIC_BIAS_4
276 };
277
278 enum {
279 MICB_PULLUP_ENABLE,
280 MICB_PULLUP_DISABLE,
281 MICB_ENABLE,
282 MICB_DISABLE,
283 };
284
285 struct wcd9335_slim_ch {
286 u32 ch_num;
287 u16 port;
288 u16 shift;
289 struct list_head list;
290 };
291
292 struct wcd_slim_codec_dai_data {
293 struct list_head slim_ch_list;
294 struct slim_stream_config sconfig;
295 struct slim_stream_runtime *sruntime;
296 };
297
298 struct wcd9335_codec {
299 struct device *dev;
300 struct clk *mclk;
301 struct clk *native_clk;
302 u32 mclk_rate;
303
304 struct slim_device *slim;
305 struct slim_device *slim_ifc_dev;
306 struct regmap *regmap;
307 struct regmap *if_regmap;
308 struct regmap_irq_chip_data *irq_data;
309
310 struct wcd9335_slim_ch rx_chs[WCD9335_RX_MAX];
311 struct wcd9335_slim_ch tx_chs[WCD9335_TX_MAX];
312 u32 num_rx_port;
313 u32 num_tx_port;
314
315 int sido_input_src;
316 enum wcd9335_sido_voltage sido_voltage;
317
318 struct wcd_slim_codec_dai_data dai[NUM_CODEC_DAIS];
319 struct snd_soc_component *component;
320
321 int master_bias_users;
322 int clk_mclk_users;
323 int clk_rco_users;
324 int sido_ccl_cnt;
325 enum wcd_clock_type clk_type;
326
327 struct wcd_clsh_ctrl *clsh_ctrl;
328 u32 hph_mode;
329 int prim_int_users[WCD9335_NUM_INTERPOLATORS];
330
331 int comp_enabled[COMPANDER_MAX];
332
333 int intr1;
334 struct gpio_desc *reset_gpio;
335
336 unsigned int rx_port_value[WCD9335_RX_MAX];
337 unsigned int tx_port_value[WCD9335_TX_MAX];
338 int hph_l_gain;
339 int hph_r_gain;
340 u32 rx_bias_count;
341
342 /*TX*/
343 int micb_ref[WCD9335_MAX_MICBIAS];
344 int pullup_ref[WCD9335_MAX_MICBIAS];
345
346 int dmic_0_1_clk_cnt;
347 int dmic_2_3_clk_cnt;
348 int dmic_4_5_clk_cnt;
349 };
350
351 struct wcd9335_irq {
352 int irq;
353 irqreturn_t (*handler)(int irq, void *data);
354 char *name;
355 };
356
357 static const char * const wcd9335_supplies[] = {
358 "vdd-buck", "vdd-buck-sido", "vdd-tx", "vdd-rx", "vdd-io",
359 };
360
361 static const struct wcd9335_slim_ch wcd9335_tx_chs[WCD9335_TX_MAX] = {
362 WCD9335_SLIM_TX_CH(0),
363 WCD9335_SLIM_TX_CH(1),
364 WCD9335_SLIM_TX_CH(2),
365 WCD9335_SLIM_TX_CH(3),
366 WCD9335_SLIM_TX_CH(4),
367 WCD9335_SLIM_TX_CH(5),
368 WCD9335_SLIM_TX_CH(6),
369 WCD9335_SLIM_TX_CH(7),
370 WCD9335_SLIM_TX_CH(8),
371 WCD9335_SLIM_TX_CH(9),
372 WCD9335_SLIM_TX_CH(10),
373 WCD9335_SLIM_TX_CH(11),
374 WCD9335_SLIM_TX_CH(12),
375 WCD9335_SLIM_TX_CH(13),
376 WCD9335_SLIM_TX_CH(14),
377 WCD9335_SLIM_TX_CH(15),
378 };
379
380 static const struct wcd9335_slim_ch wcd9335_rx_chs[WCD9335_RX_MAX] = {
381 WCD9335_SLIM_RX_CH(0), /* 16 */
382 WCD9335_SLIM_RX_CH(1), /* 17 */
383 WCD9335_SLIM_RX_CH(2),
384 WCD9335_SLIM_RX_CH(3),
385 WCD9335_SLIM_RX_CH(4),
386 WCD9335_SLIM_RX_CH(5),
387 WCD9335_SLIM_RX_CH(6),
388 WCD9335_SLIM_RX_CH(7),
389 WCD9335_SLIM_RX_CH(8),
390 WCD9335_SLIM_RX_CH(9),
391 WCD9335_SLIM_RX_CH(10),
392 WCD9335_SLIM_RX_CH(11),
393 WCD9335_SLIM_RX_CH(12),
394 };
395
396 struct interp_sample_rate {
397 int rate;
398 int rate_val;
399 };
400
401 static const struct interp_sample_rate int_mix_rate_val[] = {
402 {48000, 0x4}, /* 48K */
403 {96000, 0x5}, /* 96K */
404 {192000, 0x6}, /* 192K */
405 };
406
407 static const struct interp_sample_rate int_prim_rate_val[] = {
408 {8000, 0x0}, /* 8K */
409 {16000, 0x1}, /* 16K */
410 {24000, -EINVAL},/* 24K */
411 {32000, 0x3}, /* 32K */
412 {48000, 0x4}, /* 48K */
413 {96000, 0x5}, /* 96K */
414 {192000, 0x6}, /* 192K */
415 {384000, 0x7}, /* 384K */
416 {44100, 0x8}, /* 44.1K */
417 };
418
419 struct wcd9335_reg_mask_val {
420 u16 reg;
421 u8 mask;
422 u8 val;
423 };
424
425 static const struct wcd9335_reg_mask_val wcd9335_codec_reg_init[] = {
426 /* Rbuckfly/R_EAR(32) */
427 {WCD9335_CDC_CLSH_K2_MSB, 0x0F, 0x00},
428 {WCD9335_CDC_CLSH_K2_LSB, 0xFF, 0x60},
429 {WCD9335_CPE_SS_DMIC_CFG, 0x80, 0x00},
430 {WCD9335_CDC_BOOST0_BOOST_CTL, 0x70, 0x50},
431 {WCD9335_CDC_BOOST1_BOOST_CTL, 0x70, 0x50},
432 {WCD9335_CDC_RX7_RX_PATH_CFG1, 0x08, 0x08},
433 {WCD9335_CDC_RX8_RX_PATH_CFG1, 0x08, 0x08},
434 {WCD9335_ANA_LO_1_2, 0x3C, 0X3C},
435 {WCD9335_DIFF_LO_COM_SWCAP_REFBUF_FREQ, 0x70, 0x00},
436 {WCD9335_DIFF_LO_COM_PA_FREQ, 0x70, 0x40},
437 {WCD9335_SOC_MAD_AUDIO_CTL_2, 0x03, 0x03},
438 {WCD9335_CDC_TOP_TOP_CFG1, 0x02, 0x02},
439 {WCD9335_CDC_TOP_TOP_CFG1, 0x01, 0x01},
440 {WCD9335_EAR_CMBUFF, 0x08, 0x00},
441 {WCD9335_CDC_TX9_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
442 {WCD9335_CDC_TX10_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
443 {WCD9335_CDC_TX11_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
444 {WCD9335_CDC_TX12_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
445 {WCD9335_CDC_COMPANDER7_CTL3, 0x80, 0x80},
446 {WCD9335_CDC_COMPANDER8_CTL3, 0x80, 0x80},
447 {WCD9335_CDC_COMPANDER7_CTL7, 0x01, 0x01},
448 {WCD9335_CDC_COMPANDER8_CTL7, 0x01, 0x01},
449 {WCD9335_CDC_RX0_RX_PATH_CFG0, 0x01, 0x01},
450 {WCD9335_CDC_RX1_RX_PATH_CFG0, 0x01, 0x01},
451 {WCD9335_CDC_RX2_RX_PATH_CFG0, 0x01, 0x01},
452 {WCD9335_CDC_RX3_RX_PATH_CFG0, 0x01, 0x01},
453 {WCD9335_CDC_RX4_RX_PATH_CFG0, 0x01, 0x01},
454 {WCD9335_CDC_RX5_RX_PATH_CFG0, 0x01, 0x01},
455 {WCD9335_CDC_RX6_RX_PATH_CFG0, 0x01, 0x01},
456 {WCD9335_CDC_RX7_RX_PATH_CFG0, 0x01, 0x01},
457 {WCD9335_CDC_RX8_RX_PATH_CFG0, 0x01, 0x01},
458 {WCD9335_CDC_RX0_RX_PATH_MIX_CFG, 0x01, 0x01},
459 {WCD9335_CDC_RX1_RX_PATH_MIX_CFG, 0x01, 0x01},
460 {WCD9335_CDC_RX2_RX_PATH_MIX_CFG, 0x01, 0x01},
461 {WCD9335_CDC_RX3_RX_PATH_MIX_CFG, 0x01, 0x01},
462 {WCD9335_CDC_RX4_RX_PATH_MIX_CFG, 0x01, 0x01},
463 {WCD9335_CDC_RX5_RX_PATH_MIX_CFG, 0x01, 0x01},
464 {WCD9335_CDC_RX6_RX_PATH_MIX_CFG, 0x01, 0x01},
465 {WCD9335_CDC_RX7_RX_PATH_MIX_CFG, 0x01, 0x01},
466 {WCD9335_CDC_RX8_RX_PATH_MIX_CFG, 0x01, 0x01},
467 {WCD9335_VBADC_IBIAS_FE, 0x0C, 0x08},
468 {WCD9335_RCO_CTRL_2, 0x0F, 0x08},
469 {WCD9335_RX_BIAS_FLYB_MID_RST, 0xF0, 0x10},
470 {WCD9335_FLYBACK_CTRL_1, 0x20, 0x20},
471 {WCD9335_HPH_OCP_CTL, 0xFF, 0x5A},
472 {WCD9335_HPH_L_TEST, 0x01, 0x01},
473 {WCD9335_HPH_R_TEST, 0x01, 0x01},
474 {WCD9335_CDC_BOOST0_BOOST_CFG1, 0x3F, 0x12},
475 {WCD9335_CDC_BOOST0_BOOST_CFG2, 0x1C, 0x08},
476 {WCD9335_CDC_COMPANDER7_CTL7, 0x1E, 0x18},
477 {WCD9335_CDC_BOOST1_BOOST_CFG1, 0x3F, 0x12},
478 {WCD9335_CDC_BOOST1_BOOST_CFG2, 0x1C, 0x08},
479 {WCD9335_CDC_COMPANDER8_CTL7, 0x1E, 0x18},
480 {WCD9335_CDC_TX0_TX_PATH_SEC7, 0xFF, 0x45},
481 {WCD9335_CDC_RX0_RX_PATH_SEC0, 0xFC, 0xF4},
482 {WCD9335_HPH_REFBUFF_LP_CTL, 0x08, 0x08},
483 {WCD9335_HPH_REFBUFF_LP_CTL, 0x06, 0x02},
484 };
485
486 /* Cutoff frequency for high pass filter */
487 static const char * const cf_text[] = {
488 "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ"
489 };
490
491 static const char * const rx_cf_text[] = {
492 "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ",
493 "CF_NEG_3DB_0P48HZ"
494 };
495
496 static const char * const rx_int0_7_mix_mux_text[] = {
497 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5",
498 "RX6", "RX7", "PROXIMITY"
499 };
500
501 static const char * const rx_int_mix_mux_text[] = {
502 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5",
503 "RX6", "RX7"
504 };
505
506 static const char * const rx_prim_mix_text[] = {
507 "ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2",
508 "RX3", "RX4", "RX5", "RX6", "RX7"
509 };
510
511 static const char * const rx_int_dem_inp_mux_text[] = {
512 "NORMAL_DSM_OUT", "CLSH_DSM_OUT",
513 };
514
515 static const char * const rx_int0_interp_mux_text[] = {
516 "ZERO", "RX INT0 MIX2",
517 };
518
519 static const char * const rx_int1_interp_mux_text[] = {
520 "ZERO", "RX INT1 MIX2",
521 };
522
523 static const char * const rx_int2_interp_mux_text[] = {
524 "ZERO", "RX INT2 MIX2",
525 };
526
527 static const char * const rx_int3_interp_mux_text[] = {
528 "ZERO", "RX INT3 MIX2",
529 };
530
531 static const char * const rx_int4_interp_mux_text[] = {
532 "ZERO", "RX INT4 MIX2",
533 };
534
535 static const char * const rx_int5_interp_mux_text[] = {
536 "ZERO", "RX INT5 MIX2",
537 };
538
539 static const char * const rx_int6_interp_mux_text[] = {
540 "ZERO", "RX INT6 MIX2",
541 };
542
543 static const char * const rx_int7_interp_mux_text[] = {
544 "ZERO", "RX INT7 MIX2",
545 };
546
547 static const char * const rx_int8_interp_mux_text[] = {
548 "ZERO", "RX INT8 SEC MIX"
549 };
550
551 static const char * const rx_hph_mode_mux_text[] = {
552 "Class H Invalid", "Class-H Hi-Fi", "Class-H Low Power", "Class-AB",
553 "Class-H Hi-Fi Low Power"
554 };
555
556 static const char *const slim_rx_mux_text[] = {
557 "ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB", "AIF4_PB",
558 };
559
560 static const char * const adc_mux_text[] = {
561 "DMIC", "AMIC", "ANC_FB_TUNE1", "ANC_FB_TUNE2"
562 };
563
564 static const char * const dmic_mux_text[] = {
565 "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5",
566 "SMIC0", "SMIC1", "SMIC2", "SMIC3"
567 };
568
569 static const char * const dmic_mux_alt_text[] = {
570 "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5",
571 };
572
573 static const char * const amic_mux_text[] = {
574 "ZERO", "ADC1", "ADC2", "ADC3", "ADC4", "ADC5", "ADC6"
575 };
576
577 static const char * const sb_tx0_mux_text[] = {
578 "ZERO", "RX_MIX_TX0", "DEC0", "DEC0_192"
579 };
580
581 static const char * const sb_tx1_mux_text[] = {
582 "ZERO", "RX_MIX_TX1", "DEC1", "DEC1_192"
583 };
584
585 static const char * const sb_tx2_mux_text[] = {
586 "ZERO", "RX_MIX_TX2", "DEC2", "DEC2_192"
587 };
588
589 static const char * const sb_tx3_mux_text[] = {
590 "ZERO", "RX_MIX_TX3", "DEC3", "DEC3_192"
591 };
592
593 static const char * const sb_tx4_mux_text[] = {
594 "ZERO", "RX_MIX_TX4", "DEC4", "DEC4_192"
595 };
596
597 static const char * const sb_tx5_mux_text[] = {
598 "ZERO", "RX_MIX_TX5", "DEC5", "DEC5_192"
599 };
600
601 static const char * const sb_tx6_mux_text[] = {
602 "ZERO", "RX_MIX_TX6", "DEC6", "DEC6_192"
603 };
604
605 static const char * const sb_tx7_mux_text[] = {
606 "ZERO", "RX_MIX_TX7", "DEC7", "DEC7_192"
607 };
608
609 static const char * const sb_tx8_mux_text[] = {
610 "ZERO", "RX_MIX_TX8", "DEC8", "DEC8_192"
611 };
612
613 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
614 static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
615 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
616 static const DECLARE_TLV_DB_SCALE(ear_pa_gain, 0, 150, 0);
617
618 static const struct soc_enum cf_dec0_enum =
619 SOC_ENUM_SINGLE(WCD9335_CDC_TX0_TX_PATH_CFG0, 5, 3, cf_text);
620
621 static const struct soc_enum cf_dec1_enum =
622 SOC_ENUM_SINGLE(WCD9335_CDC_TX1_TX_PATH_CFG0, 5, 3, cf_text);
623
624 static const struct soc_enum cf_dec2_enum =
625 SOC_ENUM_SINGLE(WCD9335_CDC_TX2_TX_PATH_CFG0, 5, 3, cf_text);
626
627 static const struct soc_enum cf_dec3_enum =
628 SOC_ENUM_SINGLE(WCD9335_CDC_TX3_TX_PATH_CFG0, 5, 3, cf_text);
629
630 static const struct soc_enum cf_dec4_enum =
631 SOC_ENUM_SINGLE(WCD9335_CDC_TX4_TX_PATH_CFG0, 5, 3, cf_text);
632
633 static const struct soc_enum cf_dec5_enum =
634 SOC_ENUM_SINGLE(WCD9335_CDC_TX5_TX_PATH_CFG0, 5, 3, cf_text);
635
636 static const struct soc_enum cf_dec6_enum =
637 SOC_ENUM_SINGLE(WCD9335_CDC_TX6_TX_PATH_CFG0, 5, 3, cf_text);
638
639 static const struct soc_enum cf_dec7_enum =
640 SOC_ENUM_SINGLE(WCD9335_CDC_TX7_TX_PATH_CFG0, 5, 3, cf_text);
641
642 static const struct soc_enum cf_dec8_enum =
643 SOC_ENUM_SINGLE(WCD9335_CDC_TX8_TX_PATH_CFG0, 5, 3, cf_text);
644
645 static const struct soc_enum cf_int0_1_enum =
646 SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_CFG2, 0, 4, rx_cf_text);
647
648 static SOC_ENUM_SINGLE_DECL(cf_int0_2_enum, WCD9335_CDC_RX0_RX_PATH_MIX_CFG, 2,
649 rx_cf_text);
650
651 static const struct soc_enum cf_int1_1_enum =
652 SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_CFG2, 0, 4, rx_cf_text);
653
654 static SOC_ENUM_SINGLE_DECL(cf_int1_2_enum, WCD9335_CDC_RX1_RX_PATH_MIX_CFG, 2,
655 rx_cf_text);
656
657 static const struct soc_enum cf_int2_1_enum =
658 SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_CFG2, 0, 4, rx_cf_text);
659
660 static SOC_ENUM_SINGLE_DECL(cf_int2_2_enum, WCD9335_CDC_RX2_RX_PATH_MIX_CFG, 2,
661 rx_cf_text);
662
663 static const struct soc_enum cf_int3_1_enum =
664 SOC_ENUM_SINGLE(WCD9335_CDC_RX3_RX_PATH_CFG2, 0, 4, rx_cf_text);
665
666 static SOC_ENUM_SINGLE_DECL(cf_int3_2_enum, WCD9335_CDC_RX3_RX_PATH_MIX_CFG, 2,
667 rx_cf_text);
668
669 static const struct soc_enum cf_int4_1_enum =
670 SOC_ENUM_SINGLE(WCD9335_CDC_RX4_RX_PATH_CFG2, 0, 4, rx_cf_text);
671
672 static SOC_ENUM_SINGLE_DECL(cf_int4_2_enum, WCD9335_CDC_RX4_RX_PATH_MIX_CFG, 2,
673 rx_cf_text);
674
675 static const struct soc_enum cf_int5_1_enum =
676 SOC_ENUM_SINGLE(WCD9335_CDC_RX5_RX_PATH_CFG2, 0, 4, rx_cf_text);
677
678 static SOC_ENUM_SINGLE_DECL(cf_int5_2_enum, WCD9335_CDC_RX5_RX_PATH_MIX_CFG, 2,
679 rx_cf_text);
680
681 static const struct soc_enum cf_int6_1_enum =
682 SOC_ENUM_SINGLE(WCD9335_CDC_RX6_RX_PATH_CFG2, 0, 4, rx_cf_text);
683
684 static SOC_ENUM_SINGLE_DECL(cf_int6_2_enum, WCD9335_CDC_RX6_RX_PATH_MIX_CFG, 2,
685 rx_cf_text);
686
687 static const struct soc_enum cf_int7_1_enum =
688 SOC_ENUM_SINGLE(WCD9335_CDC_RX7_RX_PATH_CFG2, 0, 4, rx_cf_text);
689
690 static SOC_ENUM_SINGLE_DECL(cf_int7_2_enum, WCD9335_CDC_RX7_RX_PATH_MIX_CFG, 2,
691 rx_cf_text);
692
693 static const struct soc_enum cf_int8_1_enum =
694 SOC_ENUM_SINGLE(WCD9335_CDC_RX8_RX_PATH_CFG2, 0, 4, rx_cf_text);
695
696 static SOC_ENUM_SINGLE_DECL(cf_int8_2_enum, WCD9335_CDC_RX8_RX_PATH_MIX_CFG, 2,
697 rx_cf_text);
698
699 static const struct soc_enum rx_hph_mode_mux_enum =
700 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
701 rx_hph_mode_mux_text);
702
703 static const struct soc_enum slim_rx_mux_enum =
704 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim_rx_mux_text), slim_rx_mux_text);
705
706 static const struct soc_enum rx_int0_2_mux_chain_enum =
707 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG1, 0, 10,
708 rx_int0_7_mix_mux_text);
709
710 static const struct soc_enum rx_int1_2_mux_chain_enum =
711 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG1, 0, 9,
712 rx_int_mix_mux_text);
713
714 static const struct soc_enum rx_int2_2_mux_chain_enum =
715 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG1, 0, 9,
716 rx_int_mix_mux_text);
717
718 static const struct soc_enum rx_int3_2_mux_chain_enum =
719 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG1, 0, 9,
720 rx_int_mix_mux_text);
721
722 static const struct soc_enum rx_int4_2_mux_chain_enum =
723 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG1, 0, 9,
724 rx_int_mix_mux_text);
725
726 static const struct soc_enum rx_int5_2_mux_chain_enum =
727 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG1, 0, 9,
728 rx_int_mix_mux_text);
729
730 static const struct soc_enum rx_int6_2_mux_chain_enum =
731 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG1, 0, 9,
732 rx_int_mix_mux_text);
733
734 static const struct soc_enum rx_int7_2_mux_chain_enum =
735 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG1, 0, 10,
736 rx_int0_7_mix_mux_text);
737
738 static const struct soc_enum rx_int8_2_mux_chain_enum =
739 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG1, 0, 9,
740 rx_int_mix_mux_text);
741
742 static const struct soc_enum rx_int0_1_mix_inp0_chain_enum =
743 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG0, 0, 13,
744 rx_prim_mix_text);
745
746 static const struct soc_enum rx_int0_1_mix_inp1_chain_enum =
747 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG0, 4, 13,
748 rx_prim_mix_text);
749
750 static const struct soc_enum rx_int0_1_mix_inp2_chain_enum =
751 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG1, 4, 13,
752 rx_prim_mix_text);
753
754 static const struct soc_enum rx_int1_1_mix_inp0_chain_enum =
755 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG0, 0, 13,
756 rx_prim_mix_text);
757
758 static const struct soc_enum rx_int1_1_mix_inp1_chain_enum =
759 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG0, 4, 13,
760 rx_prim_mix_text);
761
762 static const struct soc_enum rx_int1_1_mix_inp2_chain_enum =
763 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG1, 4, 13,
764 rx_prim_mix_text);
765
766 static const struct soc_enum rx_int2_1_mix_inp0_chain_enum =
767 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG0, 0, 13,
768 rx_prim_mix_text);
769
770 static const struct soc_enum rx_int2_1_mix_inp1_chain_enum =
771 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG0, 4, 13,
772 rx_prim_mix_text);
773
774 static const struct soc_enum rx_int2_1_mix_inp2_chain_enum =
775 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG1, 4, 13,
776 rx_prim_mix_text);
777
778 static const struct soc_enum rx_int3_1_mix_inp0_chain_enum =
779 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG0, 0, 13,
780 rx_prim_mix_text);
781
782 static const struct soc_enum rx_int3_1_mix_inp1_chain_enum =
783 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG0, 4, 13,
784 rx_prim_mix_text);
785
786 static const struct soc_enum rx_int3_1_mix_inp2_chain_enum =
787 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG1, 4, 13,
788 rx_prim_mix_text);
789
790 static const struct soc_enum rx_int4_1_mix_inp0_chain_enum =
791 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG0, 0, 13,
792 rx_prim_mix_text);
793
794 static const struct soc_enum rx_int4_1_mix_inp1_chain_enum =
795 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG0, 4, 13,
796 rx_prim_mix_text);
797
798 static const struct soc_enum rx_int4_1_mix_inp2_chain_enum =
799 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG1, 4, 13,
800 rx_prim_mix_text);
801
802 static const struct soc_enum rx_int5_1_mix_inp0_chain_enum =
803 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG0, 0, 13,
804 rx_prim_mix_text);
805
806 static const struct soc_enum rx_int5_1_mix_inp1_chain_enum =
807 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG0, 4, 13,
808 rx_prim_mix_text);
809
810 static const struct soc_enum rx_int5_1_mix_inp2_chain_enum =
811 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG1, 4, 13,
812 rx_prim_mix_text);
813
814 static const struct soc_enum rx_int6_1_mix_inp0_chain_enum =
815 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG0, 0, 13,
816 rx_prim_mix_text);
817
818 static const struct soc_enum rx_int6_1_mix_inp1_chain_enum =
819 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG0, 4, 13,
820 rx_prim_mix_text);
821
822 static const struct soc_enum rx_int6_1_mix_inp2_chain_enum =
823 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG1, 4, 13,
824 rx_prim_mix_text);
825
826 static const struct soc_enum rx_int7_1_mix_inp0_chain_enum =
827 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG0, 0, 13,
828 rx_prim_mix_text);
829
830 static const struct soc_enum rx_int7_1_mix_inp1_chain_enum =
831 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG0, 4, 13,
832 rx_prim_mix_text);
833
834 static const struct soc_enum rx_int7_1_mix_inp2_chain_enum =
835 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG1, 4, 13,
836 rx_prim_mix_text);
837
838 static const struct soc_enum rx_int8_1_mix_inp0_chain_enum =
839 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG0, 0, 13,
840 rx_prim_mix_text);
841
842 static const struct soc_enum rx_int8_1_mix_inp1_chain_enum =
843 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG0, 4, 13,
844 rx_prim_mix_text);
845
846 static const struct soc_enum rx_int8_1_mix_inp2_chain_enum =
847 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG1, 4, 13,
848 rx_prim_mix_text);
849
850 static const struct soc_enum rx_int0_dem_inp_mux_enum =
851 SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_SEC0, 0,
852 ARRAY_SIZE(rx_int_dem_inp_mux_text),
853 rx_int_dem_inp_mux_text);
854
855 static const struct soc_enum rx_int1_dem_inp_mux_enum =
856 SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_SEC0, 0,
857 ARRAY_SIZE(rx_int_dem_inp_mux_text),
858 rx_int_dem_inp_mux_text);
859
860 static const struct soc_enum rx_int2_dem_inp_mux_enum =
861 SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_SEC0, 0,
862 ARRAY_SIZE(rx_int_dem_inp_mux_text),
863 rx_int_dem_inp_mux_text);
864
865 static const struct soc_enum rx_int0_interp_mux_enum =
866 SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_CTL, 5, 2,
867 rx_int0_interp_mux_text);
868
869 static const struct soc_enum rx_int1_interp_mux_enum =
870 SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_CTL, 5, 2,
871 rx_int1_interp_mux_text);
872
873 static const struct soc_enum rx_int2_interp_mux_enum =
874 SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_CTL, 5, 2,
875 rx_int2_interp_mux_text);
876
877 static const struct soc_enum rx_int3_interp_mux_enum =
878 SOC_ENUM_SINGLE(WCD9335_CDC_RX3_RX_PATH_CTL, 5, 2,
879 rx_int3_interp_mux_text);
880
881 static const struct soc_enum rx_int4_interp_mux_enum =
882 SOC_ENUM_SINGLE(WCD9335_CDC_RX4_RX_PATH_CTL, 5, 2,
883 rx_int4_interp_mux_text);
884
885 static const struct soc_enum rx_int5_interp_mux_enum =
886 SOC_ENUM_SINGLE(WCD9335_CDC_RX5_RX_PATH_CTL, 5, 2,
887 rx_int5_interp_mux_text);
888
889 static const struct soc_enum rx_int6_interp_mux_enum =
890 SOC_ENUM_SINGLE(WCD9335_CDC_RX6_RX_PATH_CTL, 5, 2,
891 rx_int6_interp_mux_text);
892
893 static const struct soc_enum rx_int7_interp_mux_enum =
894 SOC_ENUM_SINGLE(WCD9335_CDC_RX7_RX_PATH_CTL, 5, 2,
895 rx_int7_interp_mux_text);
896
897 static const struct soc_enum rx_int8_interp_mux_enum =
898 SOC_ENUM_SINGLE(WCD9335_CDC_RX8_RX_PATH_CTL, 5, 2,
899 rx_int8_interp_mux_text);
900
901 static const struct soc_enum tx_adc_mux0_chain_enum =
902 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0, 4,
903 adc_mux_text);
904
905 static const struct soc_enum tx_adc_mux1_chain_enum =
906 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0, 4,
907 adc_mux_text);
908
909 static const struct soc_enum tx_adc_mux2_chain_enum =
910 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0, 4,
911 adc_mux_text);
912
913 static const struct soc_enum tx_adc_mux3_chain_enum =
914 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0, 4,
915 adc_mux_text);
916
917 static const struct soc_enum tx_adc_mux4_chain_enum =
918 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 6, 4,
919 adc_mux_text);
920
921 static const struct soc_enum tx_adc_mux5_chain_enum =
922 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 6, 4,
923 adc_mux_text);
924
925 static const struct soc_enum tx_adc_mux6_chain_enum =
926 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 6, 4,
927 adc_mux_text);
928
929 static const struct soc_enum tx_adc_mux7_chain_enum =
930 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 6, 4,
931 adc_mux_text);
932
933 static const struct soc_enum tx_adc_mux8_chain_enum =
934 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 6, 4,
935 adc_mux_text);
936
937 static const struct soc_enum tx_dmic_mux0_enum =
938 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 3, 11,
939 dmic_mux_text);
940
941 static const struct soc_enum tx_dmic_mux1_enum =
942 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 3, 11,
943 dmic_mux_text);
944
945 static const struct soc_enum tx_dmic_mux2_enum =
946 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 3, 11,
947 dmic_mux_text);
948
949 static const struct soc_enum tx_dmic_mux3_enum =
950 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 3, 11,
951 dmic_mux_text);
952
953 static const struct soc_enum tx_dmic_mux4_enum =
954 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 3, 7,
955 dmic_mux_alt_text);
956
957 static const struct soc_enum tx_dmic_mux5_enum =
958 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 3, 7,
959 dmic_mux_alt_text);
960
961 static const struct soc_enum tx_dmic_mux6_enum =
962 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 3, 7,
963 dmic_mux_alt_text);
964
965 static const struct soc_enum tx_dmic_mux7_enum =
966 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 3, 7,
967 dmic_mux_alt_text);
968
969 static const struct soc_enum tx_dmic_mux8_enum =
970 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 3, 7,
971 dmic_mux_alt_text);
972
973 static const struct soc_enum tx_amic_mux0_enum =
974 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0, 7,
975 amic_mux_text);
976
977 static const struct soc_enum tx_amic_mux1_enum =
978 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0, 7,
979 amic_mux_text);
980
981 static const struct soc_enum tx_amic_mux2_enum =
982 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0, 7,
983 amic_mux_text);
984
985 static const struct soc_enum tx_amic_mux3_enum =
986 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0, 7,
987 amic_mux_text);
988
989 static const struct soc_enum tx_amic_mux4_enum =
990 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0, 7,
991 amic_mux_text);
992
993 static const struct soc_enum tx_amic_mux5_enum =
994 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0, 7,
995 amic_mux_text);
996
997 static const struct soc_enum tx_amic_mux6_enum =
998 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0, 7,
999 amic_mux_text);
1000
1001 static const struct soc_enum tx_amic_mux7_enum =
1002 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0, 7,
1003 amic_mux_text);
1004
1005 static const struct soc_enum tx_amic_mux8_enum =
1006 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 0, 7,
1007 amic_mux_text);
1008
1009 static const struct soc_enum sb_tx0_mux_enum =
1010 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 0, 4,
1011 sb_tx0_mux_text);
1012
1013 static const struct soc_enum sb_tx1_mux_enum =
1014 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 2, 4,
1015 sb_tx1_mux_text);
1016
1017 static const struct soc_enum sb_tx2_mux_enum =
1018 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 4, 4,
1019 sb_tx2_mux_text);
1020
1021 static const struct soc_enum sb_tx3_mux_enum =
1022 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 6, 4,
1023 sb_tx3_mux_text);
1024
1025 static const struct soc_enum sb_tx4_mux_enum =
1026 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 0, 4,
1027 sb_tx4_mux_text);
1028
1029 static const struct soc_enum sb_tx5_mux_enum =
1030 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 2, 4,
1031 sb_tx5_mux_text);
1032
1033 static const struct soc_enum sb_tx6_mux_enum =
1034 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 4, 4,
1035 sb_tx6_mux_text);
1036
1037 static const struct soc_enum sb_tx7_mux_enum =
1038 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 6, 4,
1039 sb_tx7_mux_text);
1040
1041 static const struct soc_enum sb_tx8_mux_enum =
1042 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG2, 0, 4,
1043 sb_tx8_mux_text);
1044
1045 static const struct snd_kcontrol_new rx_int0_2_mux =
1046 SOC_DAPM_ENUM("RX INT0_2 MUX Mux", rx_int0_2_mux_chain_enum);
1047
1048 static const struct snd_kcontrol_new rx_int1_2_mux =
1049 SOC_DAPM_ENUM("RX INT1_2 MUX Mux", rx_int1_2_mux_chain_enum);
1050
1051 static const struct snd_kcontrol_new rx_int2_2_mux =
1052 SOC_DAPM_ENUM("RX INT2_2 MUX Mux", rx_int2_2_mux_chain_enum);
1053
1054 static const struct snd_kcontrol_new rx_int3_2_mux =
1055 SOC_DAPM_ENUM("RX INT3_2 MUX Mux", rx_int3_2_mux_chain_enum);
1056
1057 static const struct snd_kcontrol_new rx_int4_2_mux =
1058 SOC_DAPM_ENUM("RX INT4_2 MUX Mux", rx_int4_2_mux_chain_enum);
1059
1060 static const struct snd_kcontrol_new rx_int5_2_mux =
1061 SOC_DAPM_ENUM("RX INT5_2 MUX Mux", rx_int5_2_mux_chain_enum);
1062
1063 static const struct snd_kcontrol_new rx_int6_2_mux =
1064 SOC_DAPM_ENUM("RX INT6_2 MUX Mux", rx_int6_2_mux_chain_enum);
1065
1066 static const struct snd_kcontrol_new rx_int7_2_mux =
1067 SOC_DAPM_ENUM("RX INT7_2 MUX Mux", rx_int7_2_mux_chain_enum);
1068
1069 static const struct snd_kcontrol_new rx_int8_2_mux =
1070 SOC_DAPM_ENUM("RX INT8_2 MUX Mux", rx_int8_2_mux_chain_enum);
1071
1072 static const struct snd_kcontrol_new rx_int0_1_mix_inp0_mux =
1073 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP0 Mux", rx_int0_1_mix_inp0_chain_enum);
1074
1075 static const struct snd_kcontrol_new rx_int0_1_mix_inp1_mux =
1076 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP1 Mux", rx_int0_1_mix_inp1_chain_enum);
1077
1078 static const struct snd_kcontrol_new rx_int0_1_mix_inp2_mux =
1079 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP2 Mux", rx_int0_1_mix_inp2_chain_enum);
1080
1081 static const struct snd_kcontrol_new rx_int1_1_mix_inp0_mux =
1082 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP0 Mux", rx_int1_1_mix_inp0_chain_enum);
1083
1084 static const struct snd_kcontrol_new rx_int1_1_mix_inp1_mux =
1085 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP1 Mux", rx_int1_1_mix_inp1_chain_enum);
1086
1087 static const struct snd_kcontrol_new rx_int1_1_mix_inp2_mux =
1088 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP2 Mux", rx_int1_1_mix_inp2_chain_enum);
1089
1090 static const struct snd_kcontrol_new rx_int2_1_mix_inp0_mux =
1091 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP0 Mux", rx_int2_1_mix_inp0_chain_enum);
1092
1093 static const struct snd_kcontrol_new rx_int2_1_mix_inp1_mux =
1094 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP1 Mux", rx_int2_1_mix_inp1_chain_enum);
1095
1096 static const struct snd_kcontrol_new rx_int2_1_mix_inp2_mux =
1097 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP2 Mux", rx_int2_1_mix_inp2_chain_enum);
1098
1099 static const struct snd_kcontrol_new rx_int3_1_mix_inp0_mux =
1100 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP0 Mux", rx_int3_1_mix_inp0_chain_enum);
1101
1102 static const struct snd_kcontrol_new rx_int3_1_mix_inp1_mux =
1103 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP1 Mux", rx_int3_1_mix_inp1_chain_enum);
1104
1105 static const struct snd_kcontrol_new rx_int3_1_mix_inp2_mux =
1106 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP2 Mux", rx_int3_1_mix_inp2_chain_enum);
1107
1108 static const struct snd_kcontrol_new rx_int4_1_mix_inp0_mux =
1109 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP0 Mux", rx_int4_1_mix_inp0_chain_enum);
1110
1111 static const struct snd_kcontrol_new rx_int4_1_mix_inp1_mux =
1112 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP1 Mux", rx_int4_1_mix_inp1_chain_enum);
1113
1114 static const struct snd_kcontrol_new rx_int4_1_mix_inp2_mux =
1115 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP2 Mux", rx_int4_1_mix_inp2_chain_enum);
1116
1117 static const struct snd_kcontrol_new rx_int5_1_mix_inp0_mux =
1118 SOC_DAPM_ENUM("RX INT5_1 MIX1 INP0 Mux", rx_int5_1_mix_inp0_chain_enum);
1119
1120 static const struct snd_kcontrol_new rx_int5_1_mix_inp1_mux =
1121 SOC_DAPM_ENUM("RX INT5_1 MIX1 INP1 Mux", rx_int5_1_mix_inp1_chain_enum);
1122
1123 static const struct snd_kcontrol_new rx_int5_1_mix_inp2_mux =
1124 SOC_DAPM_ENUM("RX INT5_1 MIX1 INP2 Mux", rx_int5_1_mix_inp2_chain_enum);
1125
1126 static const struct snd_kcontrol_new rx_int6_1_mix_inp0_mux =
1127 SOC_DAPM_ENUM("RX INT6_1 MIX1 INP0 Mux", rx_int6_1_mix_inp0_chain_enum);
1128
1129 static const struct snd_kcontrol_new rx_int6_1_mix_inp1_mux =
1130 SOC_DAPM_ENUM("RX INT6_1 MIX1 INP1 Mux", rx_int6_1_mix_inp1_chain_enum);
1131
1132 static const struct snd_kcontrol_new rx_int6_1_mix_inp2_mux =
1133 SOC_DAPM_ENUM("RX INT6_1 MIX1 INP2 Mux", rx_int6_1_mix_inp2_chain_enum);
1134
1135 static const struct snd_kcontrol_new rx_int7_1_mix_inp0_mux =
1136 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP0 Mux", rx_int7_1_mix_inp0_chain_enum);
1137
1138 static const struct snd_kcontrol_new rx_int7_1_mix_inp1_mux =
1139 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP1 Mux", rx_int7_1_mix_inp1_chain_enum);
1140
1141 static const struct snd_kcontrol_new rx_int7_1_mix_inp2_mux =
1142 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP2 Mux", rx_int7_1_mix_inp2_chain_enum);
1143
1144 static const struct snd_kcontrol_new rx_int8_1_mix_inp0_mux =
1145 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP0 Mux", rx_int8_1_mix_inp0_chain_enum);
1146
1147 static const struct snd_kcontrol_new rx_int8_1_mix_inp1_mux =
1148 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP1 Mux", rx_int8_1_mix_inp1_chain_enum);
1149
1150 static const struct snd_kcontrol_new rx_int8_1_mix_inp2_mux =
1151 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP2 Mux", rx_int8_1_mix_inp2_chain_enum);
1152
1153 static const struct snd_kcontrol_new rx_int0_interp_mux =
1154 SOC_DAPM_ENUM("RX INT0 INTERP Mux", rx_int0_interp_mux_enum);
1155
1156 static const struct snd_kcontrol_new rx_int1_interp_mux =
1157 SOC_DAPM_ENUM("RX INT1 INTERP Mux", rx_int1_interp_mux_enum);
1158
1159 static const struct snd_kcontrol_new rx_int2_interp_mux =
1160 SOC_DAPM_ENUM("RX INT2 INTERP Mux", rx_int2_interp_mux_enum);
1161
1162 static const struct snd_kcontrol_new rx_int3_interp_mux =
1163 SOC_DAPM_ENUM("RX INT3 INTERP Mux", rx_int3_interp_mux_enum);
1164
1165 static const struct snd_kcontrol_new rx_int4_interp_mux =
1166 SOC_DAPM_ENUM("RX INT4 INTERP Mux", rx_int4_interp_mux_enum);
1167
1168 static const struct snd_kcontrol_new rx_int5_interp_mux =
1169 SOC_DAPM_ENUM("RX INT5 INTERP Mux", rx_int5_interp_mux_enum);
1170
1171 static const struct snd_kcontrol_new rx_int6_interp_mux =
1172 SOC_DAPM_ENUM("RX INT6 INTERP Mux", rx_int6_interp_mux_enum);
1173
1174 static const struct snd_kcontrol_new rx_int7_interp_mux =
1175 SOC_DAPM_ENUM("RX INT7 INTERP Mux", rx_int7_interp_mux_enum);
1176
1177 static const struct snd_kcontrol_new rx_int8_interp_mux =
1178 SOC_DAPM_ENUM("RX INT8 INTERP Mux", rx_int8_interp_mux_enum);
1179
1180 static const struct snd_kcontrol_new tx_dmic_mux0 =
1181 SOC_DAPM_ENUM("DMIC MUX0 Mux", tx_dmic_mux0_enum);
1182
1183 static const struct snd_kcontrol_new tx_dmic_mux1 =
1184 SOC_DAPM_ENUM("DMIC MUX1 Mux", tx_dmic_mux1_enum);
1185
1186 static const struct snd_kcontrol_new tx_dmic_mux2 =
1187 SOC_DAPM_ENUM("DMIC MUX2 Mux", tx_dmic_mux2_enum);
1188
1189 static const struct snd_kcontrol_new tx_dmic_mux3 =
1190 SOC_DAPM_ENUM("DMIC MUX3 Mux", tx_dmic_mux3_enum);
1191
1192 static const struct snd_kcontrol_new tx_dmic_mux4 =
1193 SOC_DAPM_ENUM("DMIC MUX4 Mux", tx_dmic_mux4_enum);
1194
1195 static const struct snd_kcontrol_new tx_dmic_mux5 =
1196 SOC_DAPM_ENUM("DMIC MUX5 Mux", tx_dmic_mux5_enum);
1197
1198 static const struct snd_kcontrol_new tx_dmic_mux6 =
1199 SOC_DAPM_ENUM("DMIC MUX6 Mux", tx_dmic_mux6_enum);
1200
1201 static const struct snd_kcontrol_new tx_dmic_mux7 =
1202 SOC_DAPM_ENUM("DMIC MUX7 Mux", tx_dmic_mux7_enum);
1203
1204 static const struct snd_kcontrol_new tx_dmic_mux8 =
1205 SOC_DAPM_ENUM("DMIC MUX8 Mux", tx_dmic_mux8_enum);
1206
1207 static const struct snd_kcontrol_new tx_amic_mux0 =
1208 SOC_DAPM_ENUM("AMIC MUX0 Mux", tx_amic_mux0_enum);
1209
1210 static const struct snd_kcontrol_new tx_amic_mux1 =
1211 SOC_DAPM_ENUM("AMIC MUX1 Mux", tx_amic_mux1_enum);
1212
1213 static const struct snd_kcontrol_new tx_amic_mux2 =
1214 SOC_DAPM_ENUM("AMIC MUX2 Mux", tx_amic_mux2_enum);
1215
1216 static const struct snd_kcontrol_new tx_amic_mux3 =
1217 SOC_DAPM_ENUM("AMIC MUX3 Mux", tx_amic_mux3_enum);
1218
1219 static const struct snd_kcontrol_new tx_amic_mux4 =
1220 SOC_DAPM_ENUM("AMIC MUX4 Mux", tx_amic_mux4_enum);
1221
1222 static const struct snd_kcontrol_new tx_amic_mux5 =
1223 SOC_DAPM_ENUM("AMIC MUX5 Mux", tx_amic_mux5_enum);
1224
1225 static const struct snd_kcontrol_new tx_amic_mux6 =
1226 SOC_DAPM_ENUM("AMIC MUX6 Mux", tx_amic_mux6_enum);
1227
1228 static const struct snd_kcontrol_new tx_amic_mux7 =
1229 SOC_DAPM_ENUM("AMIC MUX7 Mux", tx_amic_mux7_enum);
1230
1231 static const struct snd_kcontrol_new tx_amic_mux8 =
1232 SOC_DAPM_ENUM("AMIC MUX8 Mux", tx_amic_mux8_enum);
1233
1234 static const struct snd_kcontrol_new sb_tx0_mux =
1235 SOC_DAPM_ENUM("SLIM TX0 MUX Mux", sb_tx0_mux_enum);
1236
1237 static const struct snd_kcontrol_new sb_tx1_mux =
1238 SOC_DAPM_ENUM("SLIM TX1 MUX Mux", sb_tx1_mux_enum);
1239
1240 static const struct snd_kcontrol_new sb_tx2_mux =
1241 SOC_DAPM_ENUM("SLIM TX2 MUX Mux", sb_tx2_mux_enum);
1242
1243 static const struct snd_kcontrol_new sb_tx3_mux =
1244 SOC_DAPM_ENUM("SLIM TX3 MUX Mux", sb_tx3_mux_enum);
1245
1246 static const struct snd_kcontrol_new sb_tx4_mux =
1247 SOC_DAPM_ENUM("SLIM TX4 MUX Mux", sb_tx4_mux_enum);
1248
1249 static const struct snd_kcontrol_new sb_tx5_mux =
1250 SOC_DAPM_ENUM("SLIM TX5 MUX Mux", sb_tx5_mux_enum);
1251
1252 static const struct snd_kcontrol_new sb_tx6_mux =
1253 SOC_DAPM_ENUM("SLIM TX6 MUX Mux", sb_tx6_mux_enum);
1254
1255 static const struct snd_kcontrol_new sb_tx7_mux =
1256 SOC_DAPM_ENUM("SLIM TX7 MUX Mux", sb_tx7_mux_enum);
1257
1258 static const struct snd_kcontrol_new sb_tx8_mux =
1259 SOC_DAPM_ENUM("SLIM TX8 MUX Mux", sb_tx8_mux_enum);
1260
slim_rx_mux_get(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)1261 static int slim_rx_mux_get(struct snd_kcontrol *kc,
1262 struct snd_ctl_elem_value *ucontrol)
1263 {
1264 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc);
1265 struct wcd9335_codec *wcd = dev_get_drvdata(w->dapm->dev);
1266 u32 port_id = w->shift;
1267
1268 ucontrol->value.enumerated.item[0] = wcd->rx_port_value[port_id];
1269
1270 return 0;
1271 }
1272
slim_rx_mux_put(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)1273 static int slim_rx_mux_put(struct snd_kcontrol *kc,
1274 struct snd_ctl_elem_value *ucontrol)
1275 {
1276 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc);
1277 struct wcd9335_codec *wcd = dev_get_drvdata(w->dapm->dev);
1278 struct soc_enum *e = (struct soc_enum *)kc->private_value;
1279 struct snd_soc_dapm_update *update = NULL;
1280 u32 port_id = w->shift;
1281
1282 if (wcd->rx_port_value[port_id] == ucontrol->value.enumerated.item[0])
1283 return 0;
1284
1285 wcd->rx_port_value[port_id] = ucontrol->value.enumerated.item[0];
1286
1287 /* Remove channel from any list it's in before adding it to a new one */
1288 list_del_init(&wcd->rx_chs[port_id].list);
1289
1290 switch (wcd->rx_port_value[port_id]) {
1291 case 0:
1292 /* Channel already removed from lists. Nothing to do here */
1293 break;
1294 case 1:
1295 list_add_tail(&wcd->rx_chs[port_id].list,
1296 &wcd->dai[AIF1_PB].slim_ch_list);
1297 break;
1298 case 2:
1299 list_add_tail(&wcd->rx_chs[port_id].list,
1300 &wcd->dai[AIF2_PB].slim_ch_list);
1301 break;
1302 case 3:
1303 list_add_tail(&wcd->rx_chs[port_id].list,
1304 &wcd->dai[AIF3_PB].slim_ch_list);
1305 break;
1306 case 4:
1307 list_add_tail(&wcd->rx_chs[port_id].list,
1308 &wcd->dai[AIF4_PB].slim_ch_list);
1309 break;
1310 default:
1311 dev_err(wcd->dev, "Unknown AIF %d\n", wcd->rx_port_value[port_id]);
1312 goto err;
1313 }
1314
1315 snd_soc_dapm_mux_update_power(w->dapm, kc, wcd->rx_port_value[port_id],
1316 e, update);
1317
1318 return 0;
1319 err:
1320 return -EINVAL;
1321 }
1322
slim_tx_mixer_get(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)1323 static int slim_tx_mixer_get(struct snd_kcontrol *kc,
1324 struct snd_ctl_elem_value *ucontrol)
1325 {
1326
1327 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc);
1328 struct wcd9335_codec *wcd = dev_get_drvdata(dapm->dev);
1329 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kc);
1330 struct soc_mixer_control *mixer =
1331 (struct soc_mixer_control *)kc->private_value;
1332 int dai_id = widget->shift;
1333 int port_id = mixer->shift;
1334
1335 ucontrol->value.integer.value[0] = wcd->tx_port_value[port_id] == dai_id;
1336
1337 return 0;
1338 }
1339
slim_tx_mixer_put(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)1340 static int slim_tx_mixer_put(struct snd_kcontrol *kc,
1341 struct snd_ctl_elem_value *ucontrol)
1342 {
1343
1344 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kc);
1345 struct wcd9335_codec *wcd = dev_get_drvdata(widget->dapm->dev);
1346 struct snd_soc_dapm_update *update = NULL;
1347 struct soc_mixer_control *mixer =
1348 (struct soc_mixer_control *)kc->private_value;
1349 int enable = ucontrol->value.integer.value[0];
1350 int dai_id = widget->shift;
1351 int port_id = mixer->shift;
1352
1353 switch (dai_id) {
1354 case AIF1_CAP:
1355 case AIF2_CAP:
1356 case AIF3_CAP:
1357 /* only add to the list if value not set */
1358 if (enable && wcd->tx_port_value[port_id] != dai_id) {
1359 wcd->tx_port_value[port_id] = dai_id;
1360 list_add_tail(&wcd->tx_chs[port_id].list,
1361 &wcd->dai[dai_id].slim_ch_list);
1362 } else if (!enable && wcd->tx_port_value[port_id] == dai_id) {
1363 wcd->tx_port_value[port_id] = -1;
1364 list_del_init(&wcd->tx_chs[port_id].list);
1365 }
1366 break;
1367 default:
1368 dev_err(wcd->dev, "Unknown AIF %d\n", dai_id);
1369 return -EINVAL;
1370 }
1371
1372 snd_soc_dapm_mixer_update_power(widget->dapm, kc, enable, update);
1373
1374 return 0;
1375 }
1376
1377 static const struct snd_kcontrol_new slim_rx_mux[WCD9335_RX_MAX] = {
1378 SOC_DAPM_ENUM_EXT("SLIM RX0 Mux", slim_rx_mux_enum,
1379 slim_rx_mux_get, slim_rx_mux_put),
1380 SOC_DAPM_ENUM_EXT("SLIM RX1 Mux", slim_rx_mux_enum,
1381 slim_rx_mux_get, slim_rx_mux_put),
1382 SOC_DAPM_ENUM_EXT("SLIM RX2 Mux", slim_rx_mux_enum,
1383 slim_rx_mux_get, slim_rx_mux_put),
1384 SOC_DAPM_ENUM_EXT("SLIM RX3 Mux", slim_rx_mux_enum,
1385 slim_rx_mux_get, slim_rx_mux_put),
1386 SOC_DAPM_ENUM_EXT("SLIM RX4 Mux", slim_rx_mux_enum,
1387 slim_rx_mux_get, slim_rx_mux_put),
1388 SOC_DAPM_ENUM_EXT("SLIM RX5 Mux", slim_rx_mux_enum,
1389 slim_rx_mux_get, slim_rx_mux_put),
1390 SOC_DAPM_ENUM_EXT("SLIM RX6 Mux", slim_rx_mux_enum,
1391 slim_rx_mux_get, slim_rx_mux_put),
1392 SOC_DAPM_ENUM_EXT("SLIM RX7 Mux", slim_rx_mux_enum,
1393 slim_rx_mux_get, slim_rx_mux_put),
1394 };
1395
1396 static const struct snd_kcontrol_new aif1_cap_mixer[] = {
1397 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0,
1398 slim_tx_mixer_get, slim_tx_mixer_put),
1399 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0,
1400 slim_tx_mixer_get, slim_tx_mixer_put),
1401 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0,
1402 slim_tx_mixer_get, slim_tx_mixer_put),
1403 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0,
1404 slim_tx_mixer_get, slim_tx_mixer_put),
1405 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0,
1406 slim_tx_mixer_get, slim_tx_mixer_put),
1407 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0,
1408 slim_tx_mixer_get, slim_tx_mixer_put),
1409 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0,
1410 slim_tx_mixer_get, slim_tx_mixer_put),
1411 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0,
1412 slim_tx_mixer_get, slim_tx_mixer_put),
1413 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0,
1414 slim_tx_mixer_get, slim_tx_mixer_put),
1415 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD9335_TX9, 1, 0,
1416 slim_tx_mixer_get, slim_tx_mixer_put),
1417 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD9335_TX10, 1, 0,
1418 slim_tx_mixer_get, slim_tx_mixer_put),
1419 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD9335_TX11, 1, 0,
1420 slim_tx_mixer_get, slim_tx_mixer_put),
1421 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD9335_TX13, 1, 0,
1422 slim_tx_mixer_get, slim_tx_mixer_put),
1423 };
1424
1425 static const struct snd_kcontrol_new aif2_cap_mixer[] = {
1426 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0,
1427 slim_tx_mixer_get, slim_tx_mixer_put),
1428 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0,
1429 slim_tx_mixer_get, slim_tx_mixer_put),
1430 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0,
1431 slim_tx_mixer_get, slim_tx_mixer_put),
1432 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0,
1433 slim_tx_mixer_get, slim_tx_mixer_put),
1434 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0,
1435 slim_tx_mixer_get, slim_tx_mixer_put),
1436 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0,
1437 slim_tx_mixer_get, slim_tx_mixer_put),
1438 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0,
1439 slim_tx_mixer_get, slim_tx_mixer_put),
1440 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0,
1441 slim_tx_mixer_get, slim_tx_mixer_put),
1442 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0,
1443 slim_tx_mixer_get, slim_tx_mixer_put),
1444 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD9335_TX9, 1, 0,
1445 slim_tx_mixer_get, slim_tx_mixer_put),
1446 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD9335_TX10, 1, 0,
1447 slim_tx_mixer_get, slim_tx_mixer_put),
1448 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD9335_TX11, 1, 0,
1449 slim_tx_mixer_get, slim_tx_mixer_put),
1450 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD9335_TX13, 1, 0,
1451 slim_tx_mixer_get, slim_tx_mixer_put),
1452 };
1453
1454 static const struct snd_kcontrol_new aif3_cap_mixer[] = {
1455 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0,
1456 slim_tx_mixer_get, slim_tx_mixer_put),
1457 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0,
1458 slim_tx_mixer_get, slim_tx_mixer_put),
1459 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0,
1460 slim_tx_mixer_get, slim_tx_mixer_put),
1461 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0,
1462 slim_tx_mixer_get, slim_tx_mixer_put),
1463 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0,
1464 slim_tx_mixer_get, slim_tx_mixer_put),
1465 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0,
1466 slim_tx_mixer_get, slim_tx_mixer_put),
1467 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0,
1468 slim_tx_mixer_get, slim_tx_mixer_put),
1469 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0,
1470 slim_tx_mixer_get, slim_tx_mixer_put),
1471 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0,
1472 slim_tx_mixer_get, slim_tx_mixer_put),
1473 };
1474
wcd9335_put_dec_enum(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)1475 static int wcd9335_put_dec_enum(struct snd_kcontrol *kc,
1476 struct snd_ctl_elem_value *ucontrol)
1477 {
1478 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc);
1479 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm);
1480 struct soc_enum *e = (struct soc_enum *)kc->private_value;
1481 unsigned int val, reg, sel;
1482
1483 val = ucontrol->value.enumerated.item[0];
1484
1485 switch (e->reg) {
1486 case WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1:
1487 reg = WCD9335_CDC_TX0_TX_PATH_CFG0;
1488 break;
1489 case WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG1:
1490 reg = WCD9335_CDC_TX1_TX_PATH_CFG0;
1491 break;
1492 case WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG1:
1493 reg = WCD9335_CDC_TX2_TX_PATH_CFG0;
1494 break;
1495 case WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG1:
1496 reg = WCD9335_CDC_TX3_TX_PATH_CFG0;
1497 break;
1498 case WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0:
1499 reg = WCD9335_CDC_TX4_TX_PATH_CFG0;
1500 break;
1501 case WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0:
1502 reg = WCD9335_CDC_TX5_TX_PATH_CFG0;
1503 break;
1504 case WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0:
1505 reg = WCD9335_CDC_TX6_TX_PATH_CFG0;
1506 break;
1507 case WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0:
1508 reg = WCD9335_CDC_TX7_TX_PATH_CFG0;
1509 break;
1510 case WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0:
1511 reg = WCD9335_CDC_TX8_TX_PATH_CFG0;
1512 break;
1513 default:
1514 return -EINVAL;
1515 }
1516
1517 /* AMIC: 0, DMIC: 1 */
1518 sel = val ? WCD9335_CDC_TX_ADC_AMIC_SEL : WCD9335_CDC_TX_ADC_DMIC_SEL;
1519 snd_soc_component_update_bits(component, reg,
1520 WCD9335_CDC_TX_ADC_AMIC_DMIC_SEL_MASK,
1521 sel);
1522
1523 return snd_soc_dapm_put_enum_double(kc, ucontrol);
1524 }
1525
wcd9335_int_dem_inp_mux_put(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)1526 static int wcd9335_int_dem_inp_mux_put(struct snd_kcontrol *kc,
1527 struct snd_ctl_elem_value *ucontrol)
1528 {
1529 struct soc_enum *e = (struct soc_enum *)kc->private_value;
1530 struct snd_soc_component *component;
1531 int reg, val;
1532
1533 component = snd_soc_dapm_kcontrol_component(kc);
1534 val = ucontrol->value.enumerated.item[0];
1535
1536 if (e->reg == WCD9335_CDC_RX0_RX_PATH_SEC0)
1537 reg = WCD9335_CDC_RX0_RX_PATH_CFG0;
1538 else if (e->reg == WCD9335_CDC_RX1_RX_PATH_SEC0)
1539 reg = WCD9335_CDC_RX1_RX_PATH_CFG0;
1540 else if (e->reg == WCD9335_CDC_RX2_RX_PATH_SEC0)
1541 reg = WCD9335_CDC_RX2_RX_PATH_CFG0;
1542 else
1543 return -EINVAL;
1544
1545 /* Set Look Ahead Delay */
1546 snd_soc_component_update_bits(component, reg,
1547 WCD9335_CDC_RX_PATH_CFG0_DLY_ZN_EN_MASK,
1548 val ? WCD9335_CDC_RX_PATH_CFG0_DLY_ZN_EN : 0);
1549 /* Set DEM INP Select */
1550 return snd_soc_dapm_put_enum_double(kc, ucontrol);
1551 }
1552
1553 static const struct snd_kcontrol_new rx_int0_dem_inp_mux =
1554 SOC_DAPM_ENUM_EXT("RX INT0 DEM MUX Mux", rx_int0_dem_inp_mux_enum,
1555 snd_soc_dapm_get_enum_double,
1556 wcd9335_int_dem_inp_mux_put);
1557
1558 static const struct snd_kcontrol_new rx_int1_dem_inp_mux =
1559 SOC_DAPM_ENUM_EXT("RX INT1 DEM MUX Mux", rx_int1_dem_inp_mux_enum,
1560 snd_soc_dapm_get_enum_double,
1561 wcd9335_int_dem_inp_mux_put);
1562
1563 static const struct snd_kcontrol_new rx_int2_dem_inp_mux =
1564 SOC_DAPM_ENUM_EXT("RX INT2 DEM MUX Mux", rx_int2_dem_inp_mux_enum,
1565 snd_soc_dapm_get_enum_double,
1566 wcd9335_int_dem_inp_mux_put);
1567
1568 static const struct snd_kcontrol_new tx_adc_mux0 =
1569 SOC_DAPM_ENUM_EXT("ADC MUX0 Mux", tx_adc_mux0_chain_enum,
1570 snd_soc_dapm_get_enum_double,
1571 wcd9335_put_dec_enum);
1572
1573 static const struct snd_kcontrol_new tx_adc_mux1 =
1574 SOC_DAPM_ENUM_EXT("ADC MUX1 Mux", tx_adc_mux1_chain_enum,
1575 snd_soc_dapm_get_enum_double,
1576 wcd9335_put_dec_enum);
1577
1578 static const struct snd_kcontrol_new tx_adc_mux2 =
1579 SOC_DAPM_ENUM_EXT("ADC MUX2 Mux", tx_adc_mux2_chain_enum,
1580 snd_soc_dapm_get_enum_double,
1581 wcd9335_put_dec_enum);
1582
1583 static const struct snd_kcontrol_new tx_adc_mux3 =
1584 SOC_DAPM_ENUM_EXT("ADC MUX3 Mux", tx_adc_mux3_chain_enum,
1585 snd_soc_dapm_get_enum_double,
1586 wcd9335_put_dec_enum);
1587
1588 static const struct snd_kcontrol_new tx_adc_mux4 =
1589 SOC_DAPM_ENUM_EXT("ADC MUX4 Mux", tx_adc_mux4_chain_enum,
1590 snd_soc_dapm_get_enum_double,
1591 wcd9335_put_dec_enum);
1592
1593 static const struct snd_kcontrol_new tx_adc_mux5 =
1594 SOC_DAPM_ENUM_EXT("ADC MUX5 Mux", tx_adc_mux5_chain_enum,
1595 snd_soc_dapm_get_enum_double,
1596 wcd9335_put_dec_enum);
1597
1598 static const struct snd_kcontrol_new tx_adc_mux6 =
1599 SOC_DAPM_ENUM_EXT("ADC MUX6 Mux", tx_adc_mux6_chain_enum,
1600 snd_soc_dapm_get_enum_double,
1601 wcd9335_put_dec_enum);
1602
1603 static const struct snd_kcontrol_new tx_adc_mux7 =
1604 SOC_DAPM_ENUM_EXT("ADC MUX7 Mux", tx_adc_mux7_chain_enum,
1605 snd_soc_dapm_get_enum_double,
1606 wcd9335_put_dec_enum);
1607
1608 static const struct snd_kcontrol_new tx_adc_mux8 =
1609 SOC_DAPM_ENUM_EXT("ADC MUX8 Mux", tx_adc_mux8_chain_enum,
1610 snd_soc_dapm_get_enum_double,
1611 wcd9335_put_dec_enum);
1612
wcd9335_set_mix_interpolator_rate(struct snd_soc_dai * dai,int rate_val,u32 rate)1613 static int wcd9335_set_mix_interpolator_rate(struct snd_soc_dai *dai,
1614 int rate_val,
1615 u32 rate)
1616 {
1617 struct snd_soc_component *component = dai->component;
1618 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
1619 struct wcd9335_slim_ch *ch;
1620 int val, j;
1621
1622 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1623 for (j = 0; j < WCD9335_NUM_INTERPOLATORS; j++) {
1624 val = snd_soc_component_read(component,
1625 WCD9335_CDC_RX_INP_MUX_RX_INT_CFG1(j)) &
1626 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1627
1628 if (val == (ch->shift + INTn_2_INP_SEL_RX0))
1629 snd_soc_component_update_bits(component,
1630 WCD9335_CDC_RX_PATH_MIX_CTL(j),
1631 WCD9335_CDC_MIX_PCM_RATE_MASK,
1632 rate_val);
1633 }
1634 }
1635
1636 return 0;
1637 }
1638
wcd9335_set_prim_interpolator_rate(struct snd_soc_dai * dai,u8 rate_val,u32 rate)1639 static int wcd9335_set_prim_interpolator_rate(struct snd_soc_dai *dai,
1640 u8 rate_val,
1641 u32 rate)
1642 {
1643 struct snd_soc_component *comp = dai->component;
1644 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
1645 struct wcd9335_slim_ch *ch;
1646 u8 cfg0, cfg1, inp0_sel, inp1_sel, inp2_sel;
1647 int inp, j;
1648
1649 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1650 inp = ch->shift + INTn_1_MIX_INP_SEL_RX0;
1651 /*
1652 * Loop through all interpolator MUX inputs and find out
1653 * to which interpolator input, the slim rx port
1654 * is connected
1655 */
1656 for (j = 0; j < WCD9335_NUM_INTERPOLATORS; j++) {
1657 cfg0 = snd_soc_component_read(comp,
1658 WCD9335_CDC_RX_INP_MUX_RX_INT_CFG0(j));
1659 cfg1 = snd_soc_component_read(comp,
1660 WCD9335_CDC_RX_INP_MUX_RX_INT_CFG1(j));
1661
1662 inp0_sel = cfg0 &
1663 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1664 inp1_sel = (cfg0 >> 4) &
1665 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1666 inp2_sel = (cfg1 >> 4) &
1667 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1668
1669 if ((inp0_sel == inp) || (inp1_sel == inp) ||
1670 (inp2_sel == inp)) {
1671 /* rate is in Hz */
1672 if ((j == 0) && (rate == 44100))
1673 dev_info(wcd->dev,
1674 "Cannot set 44.1KHz on INT0\n");
1675 else
1676 snd_soc_component_update_bits(comp,
1677 WCD9335_CDC_RX_PATH_CTL(j),
1678 WCD9335_CDC_MIX_PCM_RATE_MASK,
1679 rate_val);
1680 }
1681 }
1682 }
1683
1684 return 0;
1685 }
1686
wcd9335_set_interpolator_rate(struct snd_soc_dai * dai,u32 rate)1687 static int wcd9335_set_interpolator_rate(struct snd_soc_dai *dai, u32 rate)
1688 {
1689 int i;
1690
1691 /* set mixing path rate */
1692 for (i = 0; i < ARRAY_SIZE(int_mix_rate_val); i++) {
1693 if (rate == int_mix_rate_val[i].rate) {
1694 wcd9335_set_mix_interpolator_rate(dai,
1695 int_mix_rate_val[i].rate_val, rate);
1696 break;
1697 }
1698 }
1699
1700 /* set primary path sample rate */
1701 for (i = 0; i < ARRAY_SIZE(int_prim_rate_val); i++) {
1702 if (rate == int_prim_rate_val[i].rate) {
1703 wcd9335_set_prim_interpolator_rate(dai,
1704 int_prim_rate_val[i].rate_val, rate);
1705 break;
1706 }
1707 }
1708
1709 return 0;
1710 }
1711
wcd9335_slim_set_hw_params(struct wcd9335_codec * wcd,struct wcd_slim_codec_dai_data * dai_data,int direction)1712 static int wcd9335_slim_set_hw_params(struct wcd9335_codec *wcd,
1713 struct wcd_slim_codec_dai_data *dai_data,
1714 int direction)
1715 {
1716 struct list_head *slim_ch_list = &dai_data->slim_ch_list;
1717 struct slim_stream_config *cfg = &dai_data->sconfig;
1718 struct wcd9335_slim_ch *ch;
1719 u16 payload = 0;
1720 int ret, i;
1721
1722 cfg->ch_count = 0;
1723 cfg->direction = direction;
1724 cfg->port_mask = 0;
1725
1726 /* Configure slave interface device */
1727 list_for_each_entry(ch, slim_ch_list, list) {
1728 cfg->ch_count++;
1729 payload |= 1 << ch->shift;
1730 cfg->port_mask |= BIT(ch->port);
1731 }
1732
1733 cfg->chs = kcalloc(cfg->ch_count, sizeof(unsigned int), GFP_KERNEL);
1734 if (!cfg->chs)
1735 return -ENOMEM;
1736
1737 i = 0;
1738 list_for_each_entry(ch, slim_ch_list, list) {
1739 cfg->chs[i++] = ch->ch_num;
1740 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
1741 /* write to interface device */
1742 ret = regmap_write(wcd->if_regmap,
1743 WCD9335_SLIM_PGD_RX_PORT_MULTI_CHNL_0(ch->port),
1744 payload);
1745
1746 if (ret < 0)
1747 goto err;
1748
1749 /* configure the slave port for water mark and enable*/
1750 ret = regmap_write(wcd->if_regmap,
1751 WCD9335_SLIM_PGD_RX_PORT_CFG(ch->port),
1752 WCD9335_SLIM_WATER_MARK_VAL);
1753 if (ret < 0)
1754 goto err;
1755 } else {
1756 ret = regmap_write(wcd->if_regmap,
1757 WCD9335_SLIM_PGD_TX_PORT_MULTI_CHNL_0(ch->port),
1758 payload & 0x00FF);
1759 if (ret < 0)
1760 goto err;
1761
1762 /* ports 8,9 */
1763 ret = regmap_write(wcd->if_regmap,
1764 WCD9335_SLIM_PGD_TX_PORT_MULTI_CHNL_1(ch->port),
1765 (payload & 0xFF00)>>8);
1766 if (ret < 0)
1767 goto err;
1768
1769 /* configure the slave port for water mark and enable*/
1770 ret = regmap_write(wcd->if_regmap,
1771 WCD9335_SLIM_PGD_TX_PORT_CFG(ch->port),
1772 WCD9335_SLIM_WATER_MARK_VAL);
1773
1774 if (ret < 0)
1775 goto err;
1776 }
1777 }
1778
1779 dai_data->sruntime = slim_stream_allocate(wcd->slim, "WCD9335-SLIM");
1780
1781 return 0;
1782
1783 err:
1784 dev_err(wcd->dev, "Error Setting slim hw params\n");
1785 kfree(cfg->chs);
1786 cfg->chs = NULL;
1787
1788 return ret;
1789 }
1790
wcd9335_set_decimator_rate(struct snd_soc_dai * dai,u8 rate_val,u32 rate)1791 static int wcd9335_set_decimator_rate(struct snd_soc_dai *dai,
1792 u8 rate_val, u32 rate)
1793 {
1794 struct snd_soc_component *comp = dai->component;
1795 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp);
1796 u8 shift = 0, shift_val = 0, tx_mux_sel;
1797 struct wcd9335_slim_ch *ch;
1798 int tx_port, tx_port_reg;
1799 int decimator = -1;
1800
1801 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1802 tx_port = ch->port;
1803 if ((tx_port == 12) || (tx_port >= 14)) {
1804 dev_err(wcd->dev, "Invalid SLIM TX%u port DAI ID:%d\n",
1805 tx_port, dai->id);
1806 return -EINVAL;
1807 }
1808 /* Find the SB TX MUX input - which decimator is connected */
1809 if (tx_port < 4) {
1810 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0;
1811 shift = (tx_port << 1);
1812 shift_val = 0x03;
1813 } else if (tx_port < 8) {
1814 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1;
1815 shift = ((tx_port - 4) << 1);
1816 shift_val = 0x03;
1817 } else if (tx_port < 11) {
1818 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG2;
1819 shift = ((tx_port - 8) << 1);
1820 shift_val = 0x03;
1821 } else if (tx_port == 11) {
1822 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG3;
1823 shift = 0;
1824 shift_val = 0x0F;
1825 } else /* (tx_port == 13) */ {
1826 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG3;
1827 shift = 4;
1828 shift_val = 0x03;
1829 }
1830
1831 tx_mux_sel = snd_soc_component_read(comp, tx_port_reg) &
1832 (shift_val << shift);
1833
1834 tx_mux_sel = tx_mux_sel >> shift;
1835 if (tx_port <= 8) {
1836 if ((tx_mux_sel == 0x2) || (tx_mux_sel == 0x3))
1837 decimator = tx_port;
1838 } else if (tx_port <= 10) {
1839 if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2))
1840 decimator = ((tx_port == 9) ? 7 : 6);
1841 } else if (tx_port == 11) {
1842 if ((tx_mux_sel >= 1) && (tx_mux_sel < 7))
1843 decimator = tx_mux_sel - 1;
1844 } else if (tx_port == 13) {
1845 if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2))
1846 decimator = 5;
1847 }
1848
1849 if (decimator >= 0) {
1850 snd_soc_component_update_bits(comp,
1851 WCD9335_CDC_TX_PATH_CTL(decimator),
1852 WCD9335_CDC_TX_PATH_CTL_PCM_RATE_MASK,
1853 rate_val);
1854 } else if ((tx_port <= 8) && (tx_mux_sel == 0x01)) {
1855 /* Check if the TX Mux input is RX MIX TXn */
1856 dev_err(wcd->dev, "RX_MIX_TX%u going to SLIM TX%u\n",
1857 tx_port, tx_port);
1858 } else {
1859 dev_err(wcd->dev, "ERROR: Invalid decimator: %d\n",
1860 decimator);
1861 return -EINVAL;
1862 }
1863 }
1864
1865 return 0;
1866 }
1867
wcd9335_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)1868 static int wcd9335_hw_params(struct snd_pcm_substream *substream,
1869 struct snd_pcm_hw_params *params,
1870 struct snd_soc_dai *dai)
1871 {
1872 struct wcd9335_codec *wcd;
1873 int ret, tx_fs_rate = 0;
1874
1875 wcd = snd_soc_component_get_drvdata(dai->component);
1876
1877 switch (substream->stream) {
1878 case SNDRV_PCM_STREAM_PLAYBACK:
1879 ret = wcd9335_set_interpolator_rate(dai, params_rate(params));
1880 if (ret) {
1881 dev_err(wcd->dev, "cannot set sample rate: %u\n",
1882 params_rate(params));
1883 return ret;
1884 }
1885 switch (params_width(params)) {
1886 case 16 ... 24:
1887 wcd->dai[dai->id].sconfig.bps = params_width(params);
1888 break;
1889 default:
1890 dev_err(wcd->dev, "%s: Invalid format 0x%x\n",
1891 __func__, params_width(params));
1892 return -EINVAL;
1893 }
1894 break;
1895
1896 case SNDRV_PCM_STREAM_CAPTURE:
1897 switch (params_rate(params)) {
1898 case 8000:
1899 tx_fs_rate = 0;
1900 break;
1901 case 16000:
1902 tx_fs_rate = 1;
1903 break;
1904 case 32000:
1905 tx_fs_rate = 3;
1906 break;
1907 case 48000:
1908 tx_fs_rate = 4;
1909 break;
1910 case 96000:
1911 tx_fs_rate = 5;
1912 break;
1913 case 192000:
1914 tx_fs_rate = 6;
1915 break;
1916 case 384000:
1917 tx_fs_rate = 7;
1918 break;
1919 default:
1920 dev_err(wcd->dev, "%s: Invalid TX sample rate: %d\n",
1921 __func__, params_rate(params));
1922 return -EINVAL;
1923
1924 }
1925
1926 ret = wcd9335_set_decimator_rate(dai, tx_fs_rate,
1927 params_rate(params));
1928 if (ret < 0) {
1929 dev_err(wcd->dev, "Cannot set TX Decimator rate\n");
1930 return ret;
1931 }
1932 switch (params_width(params)) {
1933 case 16 ... 32:
1934 wcd->dai[dai->id].sconfig.bps = params_width(params);
1935 break;
1936 default:
1937 dev_err(wcd->dev, "%s: Invalid format 0x%x\n",
1938 __func__, params_width(params));
1939 return -EINVAL;
1940 }
1941 break;
1942 default:
1943 dev_err(wcd->dev, "Invalid stream type %d\n",
1944 substream->stream);
1945 return -EINVAL;
1946 }
1947
1948 wcd->dai[dai->id].sconfig.rate = params_rate(params);
1949 wcd9335_slim_set_hw_params(wcd, &wcd->dai[dai->id], substream->stream);
1950
1951 return 0;
1952 }
1953
wcd9335_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)1954 static int wcd9335_trigger(struct snd_pcm_substream *substream, int cmd,
1955 struct snd_soc_dai *dai)
1956 {
1957 struct wcd_slim_codec_dai_data *dai_data;
1958 struct wcd9335_codec *wcd;
1959 struct slim_stream_config *cfg;
1960
1961 wcd = snd_soc_component_get_drvdata(dai->component);
1962
1963 dai_data = &wcd->dai[dai->id];
1964
1965 switch (cmd) {
1966 case SNDRV_PCM_TRIGGER_START:
1967 case SNDRV_PCM_TRIGGER_RESUME:
1968 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1969 cfg = &dai_data->sconfig;
1970 slim_stream_prepare(dai_data->sruntime, cfg);
1971 slim_stream_enable(dai_data->sruntime);
1972 break;
1973 case SNDRV_PCM_TRIGGER_STOP:
1974 case SNDRV_PCM_TRIGGER_SUSPEND:
1975 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1976 slim_stream_disable(dai_data->sruntime);
1977 slim_stream_unprepare(dai_data->sruntime);
1978 break;
1979 default:
1980 break;
1981 }
1982
1983 return 0;
1984 }
1985
wcd9335_set_channel_map(struct snd_soc_dai * dai,unsigned int tx_num,const unsigned int * tx_slot,unsigned int rx_num,const unsigned int * rx_slot)1986 static int wcd9335_set_channel_map(struct snd_soc_dai *dai,
1987 unsigned int tx_num,
1988 const unsigned int *tx_slot,
1989 unsigned int rx_num,
1990 const unsigned int *rx_slot)
1991 {
1992 struct wcd9335_codec *wcd;
1993 int i;
1994
1995 wcd = snd_soc_component_get_drvdata(dai->component);
1996
1997 if (!tx_slot || !rx_slot) {
1998 dev_err(wcd->dev, "Invalid tx_slot=%p, rx_slot=%p\n",
1999 tx_slot, rx_slot);
2000 return -EINVAL;
2001 }
2002
2003 wcd->num_rx_port = rx_num;
2004 for (i = 0; i < rx_num; i++) {
2005 wcd->rx_chs[i].ch_num = rx_slot[i];
2006 INIT_LIST_HEAD(&wcd->rx_chs[i].list);
2007 }
2008
2009 wcd->num_tx_port = tx_num;
2010 for (i = 0; i < tx_num; i++) {
2011 wcd->tx_chs[i].ch_num = tx_slot[i];
2012 INIT_LIST_HEAD(&wcd->tx_chs[i].list);
2013 }
2014
2015 return 0;
2016 }
2017
wcd9335_get_channel_map(const struct snd_soc_dai * dai,unsigned int * tx_num,unsigned int * tx_slot,unsigned int * rx_num,unsigned int * rx_slot)2018 static int wcd9335_get_channel_map(const struct snd_soc_dai *dai,
2019 unsigned int *tx_num, unsigned int *tx_slot,
2020 unsigned int *rx_num, unsigned int *rx_slot)
2021 {
2022 struct wcd9335_slim_ch *ch;
2023 struct wcd9335_codec *wcd;
2024 int i = 0;
2025
2026 wcd = snd_soc_component_get_drvdata(dai->component);
2027
2028 switch (dai->id) {
2029 case AIF1_PB:
2030 case AIF2_PB:
2031 case AIF3_PB:
2032 case AIF4_PB:
2033 if (!rx_slot || !rx_num) {
2034 dev_err(wcd->dev, "Invalid rx_slot %p or rx_num %p\n",
2035 rx_slot, rx_num);
2036 return -EINVAL;
2037 }
2038
2039 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list)
2040 rx_slot[i++] = ch->ch_num;
2041
2042 *rx_num = i;
2043 break;
2044 case AIF1_CAP:
2045 case AIF2_CAP:
2046 case AIF3_CAP:
2047 if (!tx_slot || !tx_num) {
2048 dev_err(wcd->dev, "Invalid tx_slot %p or tx_num %p\n",
2049 tx_slot, tx_num);
2050 return -EINVAL;
2051 }
2052 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list)
2053 tx_slot[i++] = ch->ch_num;
2054
2055 *tx_num = i;
2056 break;
2057 default:
2058 dev_err(wcd->dev, "Invalid DAI ID %x\n", dai->id);
2059 break;
2060 }
2061
2062 return 0;
2063 }
2064
2065 static const struct snd_soc_dai_ops wcd9335_dai_ops = {
2066 .hw_params = wcd9335_hw_params,
2067 .trigger = wcd9335_trigger,
2068 .set_channel_map = wcd9335_set_channel_map,
2069 .get_channel_map = wcd9335_get_channel_map,
2070 };
2071
2072 static struct snd_soc_dai_driver wcd9335_slim_dais[] = {
2073 [0] = {
2074 .name = "wcd9335_rx1",
2075 .id = AIF1_PB,
2076 .playback = {
2077 .stream_name = "AIF1 Playback",
2078 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK |
2079 SNDRV_PCM_RATE_384000,
2080 .formats = WCD9335_FORMATS_S16_S24_LE,
2081 .rate_max = 384000,
2082 .rate_min = 8000,
2083 .channels_min = 1,
2084 .channels_max = 2,
2085 },
2086 .ops = &wcd9335_dai_ops,
2087 },
2088 [1] = {
2089 .name = "wcd9335_tx1",
2090 .id = AIF1_CAP,
2091 .capture = {
2092 .stream_name = "AIF1 Capture",
2093 .rates = WCD9335_RATES_MASK,
2094 .formats = SNDRV_PCM_FMTBIT_S16_LE,
2095 .rate_min = 8000,
2096 .rate_max = 192000,
2097 .channels_min = 1,
2098 .channels_max = 4,
2099 },
2100 .ops = &wcd9335_dai_ops,
2101 },
2102 [2] = {
2103 .name = "wcd9335_rx2",
2104 .id = AIF2_PB,
2105 .playback = {
2106 .stream_name = "AIF2 Playback",
2107 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK |
2108 SNDRV_PCM_RATE_384000,
2109 .formats = WCD9335_FORMATS_S16_S24_LE,
2110 .rate_min = 8000,
2111 .rate_max = 384000,
2112 .channels_min = 1,
2113 .channels_max = 2,
2114 },
2115 .ops = &wcd9335_dai_ops,
2116 },
2117 [3] = {
2118 .name = "wcd9335_tx2",
2119 .id = AIF2_CAP,
2120 .capture = {
2121 .stream_name = "AIF2 Capture",
2122 .rates = WCD9335_RATES_MASK,
2123 .formats = SNDRV_PCM_FMTBIT_S16_LE,
2124 .rate_min = 8000,
2125 .rate_max = 192000,
2126 .channels_min = 1,
2127 .channels_max = 4,
2128 },
2129 .ops = &wcd9335_dai_ops,
2130 },
2131 [4] = {
2132 .name = "wcd9335_rx3",
2133 .id = AIF3_PB,
2134 .playback = {
2135 .stream_name = "AIF3 Playback",
2136 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK |
2137 SNDRV_PCM_RATE_384000,
2138 .formats = WCD9335_FORMATS_S16_S24_LE,
2139 .rate_min = 8000,
2140 .rate_max = 384000,
2141 .channels_min = 1,
2142 .channels_max = 2,
2143 },
2144 .ops = &wcd9335_dai_ops,
2145 },
2146 [5] = {
2147 .name = "wcd9335_tx3",
2148 .id = AIF3_CAP,
2149 .capture = {
2150 .stream_name = "AIF3 Capture",
2151 .rates = WCD9335_RATES_MASK,
2152 .formats = SNDRV_PCM_FMTBIT_S16_LE,
2153 .rate_min = 8000,
2154 .rate_max = 192000,
2155 .channels_min = 1,
2156 .channels_max = 4,
2157 },
2158 .ops = &wcd9335_dai_ops,
2159 },
2160 [6] = {
2161 .name = "wcd9335_rx4",
2162 .id = AIF4_PB,
2163 .playback = {
2164 .stream_name = "AIF4 Playback",
2165 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK |
2166 SNDRV_PCM_RATE_384000,
2167 .formats = WCD9335_FORMATS_S16_S24_LE,
2168 .rate_min = 8000,
2169 .rate_max = 384000,
2170 .channels_min = 1,
2171 .channels_max = 2,
2172 },
2173 .ops = &wcd9335_dai_ops,
2174 },
2175 };
2176
wcd9335_get_compander(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)2177 static int wcd9335_get_compander(struct snd_kcontrol *kc,
2178 struct snd_ctl_elem_value *ucontrol)
2179 {
2180
2181 struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2182 int comp = ((struct soc_mixer_control *)kc->private_value)->shift;
2183 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
2184
2185 ucontrol->value.integer.value[0] = wcd->comp_enabled[comp];
2186 return 0;
2187 }
2188
wcd9335_set_compander(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)2189 static int wcd9335_set_compander(struct snd_kcontrol *kc,
2190 struct snd_ctl_elem_value *ucontrol)
2191 {
2192 struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2193 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
2194 int comp = ((struct soc_mixer_control *) kc->private_value)->shift;
2195 int value = ucontrol->value.integer.value[0];
2196 int sel;
2197
2198 wcd->comp_enabled[comp] = value;
2199 sel = value ? WCD9335_HPH_GAIN_SRC_SEL_COMPANDER :
2200 WCD9335_HPH_GAIN_SRC_SEL_REGISTER;
2201
2202 /* Any specific register configuration for compander */
2203 switch (comp) {
2204 case COMPANDER_1:
2205 /* Set Gain Source Select based on compander enable/disable */
2206 snd_soc_component_update_bits(component, WCD9335_HPH_L_EN,
2207 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel);
2208 break;
2209 case COMPANDER_2:
2210 snd_soc_component_update_bits(component, WCD9335_HPH_R_EN,
2211 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel);
2212 break;
2213 case COMPANDER_5:
2214 snd_soc_component_update_bits(component, WCD9335_SE_LO_LO3_GAIN,
2215 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel);
2216 break;
2217 case COMPANDER_6:
2218 snd_soc_component_update_bits(component, WCD9335_SE_LO_LO4_GAIN,
2219 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel);
2220 break;
2221 default:
2222 break;
2223 }
2224
2225 return 0;
2226 }
2227
wcd9335_rx_hph_mode_get(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)2228 static int wcd9335_rx_hph_mode_get(struct snd_kcontrol *kc,
2229 struct snd_ctl_elem_value *ucontrol)
2230 {
2231 struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2232 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
2233
2234 ucontrol->value.enumerated.item[0] = wcd->hph_mode;
2235
2236 return 0;
2237 }
2238
wcd9335_rx_hph_mode_put(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)2239 static int wcd9335_rx_hph_mode_put(struct snd_kcontrol *kc,
2240 struct snd_ctl_elem_value *ucontrol)
2241 {
2242 struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2243 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
2244 u32 mode_val;
2245
2246 mode_val = ucontrol->value.enumerated.item[0];
2247
2248 if (mode_val == 0) {
2249 dev_err(wcd->dev, "Invalid HPH Mode, default to ClSH HiFi\n");
2250 mode_val = CLS_H_HIFI;
2251 }
2252 wcd->hph_mode = mode_val;
2253
2254 return 0;
2255 }
2256
2257 static const struct snd_kcontrol_new wcd9335_snd_controls[] = {
2258 /* -84dB min - 40dB max */
2259 SOC_SINGLE_S8_TLV("RX0 Digital Volume", WCD9335_CDC_RX0_RX_VOL_CTL,
2260 -84, 40, digital_gain),
2261 SOC_SINGLE_S8_TLV("RX1 Digital Volume", WCD9335_CDC_RX1_RX_VOL_CTL,
2262 -84, 40, digital_gain),
2263 SOC_SINGLE_S8_TLV("RX2 Digital Volume", WCD9335_CDC_RX2_RX_VOL_CTL,
2264 -84, 40, digital_gain),
2265 SOC_SINGLE_S8_TLV("RX3 Digital Volume", WCD9335_CDC_RX3_RX_VOL_CTL,
2266 -84, 40, digital_gain),
2267 SOC_SINGLE_S8_TLV("RX4 Digital Volume", WCD9335_CDC_RX4_RX_VOL_CTL,
2268 -84, 40, digital_gain),
2269 SOC_SINGLE_S8_TLV("RX5 Digital Volume", WCD9335_CDC_RX5_RX_VOL_CTL,
2270 -84, 40, digital_gain),
2271 SOC_SINGLE_S8_TLV("RX6 Digital Volume", WCD9335_CDC_RX6_RX_VOL_CTL,
2272 -84, 40, digital_gain),
2273 SOC_SINGLE_S8_TLV("RX7 Digital Volume", WCD9335_CDC_RX7_RX_VOL_CTL,
2274 -84, 40, digital_gain),
2275 SOC_SINGLE_S8_TLV("RX8 Digital Volume", WCD9335_CDC_RX8_RX_VOL_CTL,
2276 -84, 40, digital_gain),
2277 SOC_SINGLE_S8_TLV("RX0 Mix Digital Volume", WCD9335_CDC_RX0_RX_VOL_MIX_CTL,
2278 -84, 40, digital_gain),
2279 SOC_SINGLE_S8_TLV("RX1 Mix Digital Volume", WCD9335_CDC_RX1_RX_VOL_MIX_CTL,
2280 -84, 40, digital_gain),
2281 SOC_SINGLE_S8_TLV("RX2 Mix Digital Volume", WCD9335_CDC_RX2_RX_VOL_MIX_CTL,
2282 -84, 40, digital_gain),
2283 SOC_SINGLE_S8_TLV("RX3 Mix Digital Volume", WCD9335_CDC_RX3_RX_VOL_MIX_CTL,
2284 -84, 40, digital_gain),
2285 SOC_SINGLE_S8_TLV("RX4 Mix Digital Volume", WCD9335_CDC_RX4_RX_VOL_MIX_CTL,
2286 -84, 40, digital_gain),
2287 SOC_SINGLE_S8_TLV("RX5 Mix Digital Volume", WCD9335_CDC_RX5_RX_VOL_MIX_CTL,
2288 -84, 40, digital_gain),
2289 SOC_SINGLE_S8_TLV("RX6 Mix Digital Volume", WCD9335_CDC_RX6_RX_VOL_MIX_CTL,
2290 -84, 40, digital_gain),
2291 SOC_SINGLE_S8_TLV("RX7 Mix Digital Volume", WCD9335_CDC_RX7_RX_VOL_MIX_CTL,
2292 -84, 40, digital_gain),
2293 SOC_SINGLE_S8_TLV("RX8 Mix Digital Volume", WCD9335_CDC_RX8_RX_VOL_MIX_CTL,
2294 -84, 40, digital_gain),
2295 SOC_ENUM("RX INT0_1 HPF cut off", cf_int0_1_enum),
2296 SOC_ENUM("RX INT0_2 HPF cut off", cf_int0_2_enum),
2297 SOC_ENUM("RX INT1_1 HPF cut off", cf_int1_1_enum),
2298 SOC_ENUM("RX INT1_2 HPF cut off", cf_int1_2_enum),
2299 SOC_ENUM("RX INT2_1 HPF cut off", cf_int2_1_enum),
2300 SOC_ENUM("RX INT2_2 HPF cut off", cf_int2_2_enum),
2301 SOC_ENUM("RX INT3_1 HPF cut off", cf_int3_1_enum),
2302 SOC_ENUM("RX INT3_2 HPF cut off", cf_int3_2_enum),
2303 SOC_ENUM("RX INT4_1 HPF cut off", cf_int4_1_enum),
2304 SOC_ENUM("RX INT4_2 HPF cut off", cf_int4_2_enum),
2305 SOC_ENUM("RX INT5_1 HPF cut off", cf_int5_1_enum),
2306 SOC_ENUM("RX INT5_2 HPF cut off", cf_int5_2_enum),
2307 SOC_ENUM("RX INT6_1 HPF cut off", cf_int6_1_enum),
2308 SOC_ENUM("RX INT6_2 HPF cut off", cf_int6_2_enum),
2309 SOC_ENUM("RX INT7_1 HPF cut off", cf_int7_1_enum),
2310 SOC_ENUM("RX INT7_2 HPF cut off", cf_int7_2_enum),
2311 SOC_ENUM("RX INT8_1 HPF cut off", cf_int8_1_enum),
2312 SOC_ENUM("RX INT8_2 HPF cut off", cf_int8_2_enum),
2313 SOC_SINGLE_EXT("COMP1 Switch", SND_SOC_NOPM, COMPANDER_1, 1, 0,
2314 wcd9335_get_compander, wcd9335_set_compander),
2315 SOC_SINGLE_EXT("COMP2 Switch", SND_SOC_NOPM, COMPANDER_2, 1, 0,
2316 wcd9335_get_compander, wcd9335_set_compander),
2317 SOC_SINGLE_EXT("COMP3 Switch", SND_SOC_NOPM, COMPANDER_3, 1, 0,
2318 wcd9335_get_compander, wcd9335_set_compander),
2319 SOC_SINGLE_EXT("COMP4 Switch", SND_SOC_NOPM, COMPANDER_4, 1, 0,
2320 wcd9335_get_compander, wcd9335_set_compander),
2321 SOC_SINGLE_EXT("COMP5 Switch", SND_SOC_NOPM, COMPANDER_5, 1, 0,
2322 wcd9335_get_compander, wcd9335_set_compander),
2323 SOC_SINGLE_EXT("COMP6 Switch", SND_SOC_NOPM, COMPANDER_6, 1, 0,
2324 wcd9335_get_compander, wcd9335_set_compander),
2325 SOC_SINGLE_EXT("COMP7 Switch", SND_SOC_NOPM, COMPANDER_7, 1, 0,
2326 wcd9335_get_compander, wcd9335_set_compander),
2327 SOC_SINGLE_EXT("COMP8 Switch", SND_SOC_NOPM, COMPANDER_8, 1, 0,
2328 wcd9335_get_compander, wcd9335_set_compander),
2329 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
2330 wcd9335_rx_hph_mode_get, wcd9335_rx_hph_mode_put),
2331
2332 /* Gain Controls */
2333 SOC_SINGLE_TLV("EAR PA Volume", WCD9335_ANA_EAR, 4, 4, 1,
2334 ear_pa_gain),
2335 SOC_SINGLE_TLV("HPHL Volume", WCD9335_HPH_L_EN, 0, 20, 1,
2336 line_gain),
2337 SOC_SINGLE_TLV("HPHR Volume", WCD9335_HPH_R_EN, 0, 20, 1,
2338 line_gain),
2339 SOC_SINGLE_TLV("LINEOUT1 Volume", WCD9335_DIFF_LO_LO1_COMPANDER,
2340 3, 16, 1, line_gain),
2341 SOC_SINGLE_TLV("LINEOUT2 Volume", WCD9335_DIFF_LO_LO2_COMPANDER,
2342 3, 16, 1, line_gain),
2343 SOC_SINGLE_TLV("LINEOUT3 Volume", WCD9335_SE_LO_LO3_GAIN, 0, 20, 1,
2344 line_gain),
2345 SOC_SINGLE_TLV("LINEOUT4 Volume", WCD9335_SE_LO_LO4_GAIN, 0, 20, 1,
2346 line_gain),
2347
2348 SOC_SINGLE_TLV("ADC1 Volume", WCD9335_ANA_AMIC1, 0, 20, 0,
2349 analog_gain),
2350 SOC_SINGLE_TLV("ADC2 Volume", WCD9335_ANA_AMIC2, 0, 20, 0,
2351 analog_gain),
2352 SOC_SINGLE_TLV("ADC3 Volume", WCD9335_ANA_AMIC3, 0, 20, 0,
2353 analog_gain),
2354 SOC_SINGLE_TLV("ADC4 Volume", WCD9335_ANA_AMIC4, 0, 20, 0,
2355 analog_gain),
2356 SOC_SINGLE_TLV("ADC5 Volume", WCD9335_ANA_AMIC5, 0, 20, 0,
2357 analog_gain),
2358 SOC_SINGLE_TLV("ADC6 Volume", WCD9335_ANA_AMIC6, 0, 20, 0,
2359 analog_gain),
2360
2361 SOC_ENUM("TX0 HPF cut off", cf_dec0_enum),
2362 SOC_ENUM("TX1 HPF cut off", cf_dec1_enum),
2363 SOC_ENUM("TX2 HPF cut off", cf_dec2_enum),
2364 SOC_ENUM("TX3 HPF cut off", cf_dec3_enum),
2365 SOC_ENUM("TX4 HPF cut off", cf_dec4_enum),
2366 SOC_ENUM("TX5 HPF cut off", cf_dec5_enum),
2367 SOC_ENUM("TX6 HPF cut off", cf_dec6_enum),
2368 SOC_ENUM("TX7 HPF cut off", cf_dec7_enum),
2369 SOC_ENUM("TX8 HPF cut off", cf_dec8_enum),
2370 };
2371
2372 static const struct snd_soc_dapm_route wcd9335_audio_map[] = {
2373 {"SLIM RX0 MUX", "AIF1_PB", "AIF1 PB"},
2374 {"SLIM RX1 MUX", "AIF1_PB", "AIF1 PB"},
2375 {"SLIM RX2 MUX", "AIF1_PB", "AIF1 PB"},
2376 {"SLIM RX3 MUX", "AIF1_PB", "AIF1 PB"},
2377 {"SLIM RX4 MUX", "AIF1_PB", "AIF1 PB"},
2378 {"SLIM RX5 MUX", "AIF1_PB", "AIF1 PB"},
2379 {"SLIM RX6 MUX", "AIF1_PB", "AIF1 PB"},
2380 {"SLIM RX7 MUX", "AIF1_PB", "AIF1 PB"},
2381
2382 {"SLIM RX0 MUX", "AIF2_PB", "AIF2 PB"},
2383 {"SLIM RX1 MUX", "AIF2_PB", "AIF2 PB"},
2384 {"SLIM RX2 MUX", "AIF2_PB", "AIF2 PB"},
2385 {"SLIM RX3 MUX", "AIF2_PB", "AIF2 PB"},
2386 {"SLIM RX4 MUX", "AIF2_PB", "AIF2 PB"},
2387 {"SLIM RX5 MUX", "AIF2_PB", "AIF2 PB"},
2388 {"SLIM RX6 MUX", "AIF2_PB", "AIF2 PB"},
2389 {"SLIM RX7 MUX", "AIF2_PB", "AIF2 PB"},
2390
2391 {"SLIM RX0 MUX", "AIF3_PB", "AIF3 PB"},
2392 {"SLIM RX1 MUX", "AIF3_PB", "AIF3 PB"},
2393 {"SLIM RX2 MUX", "AIF3_PB", "AIF3 PB"},
2394 {"SLIM RX3 MUX", "AIF3_PB", "AIF3 PB"},
2395 {"SLIM RX4 MUX", "AIF3_PB", "AIF3 PB"},
2396 {"SLIM RX5 MUX", "AIF3_PB", "AIF3 PB"},
2397 {"SLIM RX6 MUX", "AIF3_PB", "AIF3 PB"},
2398 {"SLIM RX7 MUX", "AIF3_PB", "AIF3 PB"},
2399
2400 {"SLIM RX0 MUX", "AIF4_PB", "AIF4 PB"},
2401 {"SLIM RX1 MUX", "AIF4_PB", "AIF4 PB"},
2402 {"SLIM RX2 MUX", "AIF4_PB", "AIF4 PB"},
2403 {"SLIM RX3 MUX", "AIF4_PB", "AIF4 PB"},
2404 {"SLIM RX4 MUX", "AIF4_PB", "AIF4 PB"},
2405 {"SLIM RX5 MUX", "AIF4_PB", "AIF4 PB"},
2406 {"SLIM RX6 MUX", "AIF4_PB", "AIF4 PB"},
2407 {"SLIM RX7 MUX", "AIF4_PB", "AIF4 PB"},
2408
2409 {"SLIM RX0", NULL, "SLIM RX0 MUX"},
2410 {"SLIM RX1", NULL, "SLIM RX1 MUX"},
2411 {"SLIM RX2", NULL, "SLIM RX2 MUX"},
2412 {"SLIM RX3", NULL, "SLIM RX3 MUX"},
2413 {"SLIM RX4", NULL, "SLIM RX4 MUX"},
2414 {"SLIM RX5", NULL, "SLIM RX5 MUX"},
2415 {"SLIM RX6", NULL, "SLIM RX6 MUX"},
2416 {"SLIM RX7", NULL, "SLIM RX7 MUX"},
2417
2418 WCD9335_INTERPOLATOR_PATH(0),
2419 WCD9335_INTERPOLATOR_PATH(1),
2420 WCD9335_INTERPOLATOR_PATH(2),
2421 WCD9335_INTERPOLATOR_PATH(3),
2422 WCD9335_INTERPOLATOR_PATH(4),
2423 WCD9335_INTERPOLATOR_PATH(5),
2424 WCD9335_INTERPOLATOR_PATH(6),
2425 WCD9335_INTERPOLATOR_PATH(7),
2426 WCD9335_INTERPOLATOR_PATH(8),
2427
2428 /* EAR PA */
2429 {"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 INTERP"},
2430 {"RX INT0 DAC", NULL, "RX INT0 DEM MUX"},
2431 {"RX INT0 DAC", NULL, "RX_BIAS"},
2432 {"EAR PA", NULL, "RX INT0 DAC"},
2433 {"EAR", NULL, "EAR PA"},
2434
2435 /* HPHL */
2436 {"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 INTERP"},
2437 {"RX INT1 DAC", NULL, "RX INT1 DEM MUX"},
2438 {"RX INT1 DAC", NULL, "RX_BIAS"},
2439 {"HPHL PA", NULL, "RX INT1 DAC"},
2440 {"HPHL", NULL, "HPHL PA"},
2441
2442 /* HPHR */
2443 {"RX INT2 DEM MUX", "CLSH_DSM_OUT", "RX INT2 INTERP"},
2444 {"RX INT2 DAC", NULL, "RX INT2 DEM MUX"},
2445 {"RX INT2 DAC", NULL, "RX_BIAS"},
2446 {"HPHR PA", NULL, "RX INT2 DAC"},
2447 {"HPHR", NULL, "HPHR PA"},
2448
2449 /* LINEOUT1 */
2450 {"RX INT3 DAC", NULL, "RX INT3 INTERP"},
2451 {"RX INT3 DAC", NULL, "RX_BIAS"},
2452 {"LINEOUT1 PA", NULL, "RX INT3 DAC"},
2453 {"LINEOUT1", NULL, "LINEOUT1 PA"},
2454
2455 /* LINEOUT2 */
2456 {"RX INT4 DAC", NULL, "RX INT4 INTERP"},
2457 {"RX INT4 DAC", NULL, "RX_BIAS"},
2458 {"LINEOUT2 PA", NULL, "RX INT4 DAC"},
2459 {"LINEOUT2", NULL, "LINEOUT2 PA"},
2460
2461 /* LINEOUT3 */
2462 {"RX INT5 DAC", NULL, "RX INT5 INTERP"},
2463 {"RX INT5 DAC", NULL, "RX_BIAS"},
2464 {"LINEOUT3 PA", NULL, "RX INT5 DAC"},
2465 {"LINEOUT3", NULL, "LINEOUT3 PA"},
2466
2467 /* LINEOUT4 */
2468 {"RX INT6 DAC", NULL, "RX INT6 INTERP"},
2469 {"RX INT6 DAC", NULL, "RX_BIAS"},
2470 {"LINEOUT4 PA", NULL, "RX INT6 DAC"},
2471 {"LINEOUT4", NULL, "LINEOUT4 PA"},
2472
2473 /* SLIMBUS Connections */
2474 {"AIF1 CAP", NULL, "AIF1_CAP Mixer"},
2475 {"AIF2 CAP", NULL, "AIF2_CAP Mixer"},
2476 {"AIF3 CAP", NULL, "AIF3_CAP Mixer"},
2477
2478 /* ADC Mux */
2479 WCD9335_ADC_MUX_PATH(0),
2480 WCD9335_ADC_MUX_PATH(1),
2481 WCD9335_ADC_MUX_PATH(2),
2482 WCD9335_ADC_MUX_PATH(3),
2483 WCD9335_ADC_MUX_PATH(4),
2484 WCD9335_ADC_MUX_PATH(5),
2485 WCD9335_ADC_MUX_PATH(6),
2486 WCD9335_ADC_MUX_PATH(7),
2487 WCD9335_ADC_MUX_PATH(8),
2488
2489 /* ADC Connections */
2490 {"ADC1", NULL, "AMIC1"},
2491 {"ADC2", NULL, "AMIC2"},
2492 {"ADC3", NULL, "AMIC3"},
2493 {"ADC4", NULL, "AMIC4"},
2494 {"ADC5", NULL, "AMIC5"},
2495 {"ADC6", NULL, "AMIC6"},
2496 };
2497
wcd9335_micbias_control(struct snd_soc_component * component,int micb_num,int req,bool is_dapm)2498 static int wcd9335_micbias_control(struct snd_soc_component *component,
2499 int micb_num, int req, bool is_dapm)
2500 {
2501 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(component);
2502 int micb_index = micb_num - 1;
2503 u16 micb_reg;
2504
2505 if ((micb_index < 0) || (micb_index > WCD9335_MAX_MICBIAS - 1)) {
2506 dev_err(wcd->dev, "Invalid micbias index, micb_ind:%d\n",
2507 micb_index);
2508 return -EINVAL;
2509 }
2510
2511 switch (micb_num) {
2512 case MIC_BIAS_1:
2513 micb_reg = WCD9335_ANA_MICB1;
2514 break;
2515 case MIC_BIAS_2:
2516 micb_reg = WCD9335_ANA_MICB2;
2517 break;
2518 case MIC_BIAS_3:
2519 micb_reg = WCD9335_ANA_MICB3;
2520 break;
2521 case MIC_BIAS_4:
2522 micb_reg = WCD9335_ANA_MICB4;
2523 break;
2524 default:
2525 dev_err(component->dev, "%s: Invalid micbias number: %d\n",
2526 __func__, micb_num);
2527 return -EINVAL;
2528 }
2529
2530 switch (req) {
2531 case MICB_PULLUP_ENABLE:
2532 wcd->pullup_ref[micb_index]++;
2533 if ((wcd->pullup_ref[micb_index] == 1) &&
2534 (wcd->micb_ref[micb_index] == 0))
2535 snd_soc_component_update_bits(component, micb_reg,
2536 0xC0, 0x80);
2537 break;
2538 case MICB_PULLUP_DISABLE:
2539 wcd->pullup_ref[micb_index]--;
2540 if ((wcd->pullup_ref[micb_index] == 0) &&
2541 (wcd->micb_ref[micb_index] == 0))
2542 snd_soc_component_update_bits(component, micb_reg,
2543 0xC0, 0x00);
2544 break;
2545 case MICB_ENABLE:
2546 wcd->micb_ref[micb_index]++;
2547 if (wcd->micb_ref[micb_index] == 1)
2548 snd_soc_component_update_bits(component, micb_reg,
2549 0xC0, 0x40);
2550 break;
2551 case MICB_DISABLE:
2552 wcd->micb_ref[micb_index]--;
2553 if ((wcd->micb_ref[micb_index] == 0) &&
2554 (wcd->pullup_ref[micb_index] > 0))
2555 snd_soc_component_update_bits(component, micb_reg,
2556 0xC0, 0x80);
2557 else if ((wcd->micb_ref[micb_index] == 0) &&
2558 (wcd->pullup_ref[micb_index] == 0)) {
2559 snd_soc_component_update_bits(component, micb_reg,
2560 0xC0, 0x00);
2561 }
2562 break;
2563 }
2564
2565 return 0;
2566 }
2567
__wcd9335_codec_enable_micbias(struct snd_soc_dapm_widget * w,int event)2568 static int __wcd9335_codec_enable_micbias(struct snd_soc_dapm_widget *w,
2569 int event)
2570 {
2571 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
2572 int micb_num;
2573
2574 if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
2575 micb_num = MIC_BIAS_1;
2576 else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
2577 micb_num = MIC_BIAS_2;
2578 else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
2579 micb_num = MIC_BIAS_3;
2580 else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4")))
2581 micb_num = MIC_BIAS_4;
2582 else
2583 return -EINVAL;
2584
2585 switch (event) {
2586 case SND_SOC_DAPM_PRE_PMU:
2587 /*
2588 * MIC BIAS can also be requested by MBHC,
2589 * so use ref count to handle micbias pullup
2590 * and enable requests
2591 */
2592 wcd9335_micbias_control(comp, micb_num, MICB_ENABLE, true);
2593 break;
2594 case SND_SOC_DAPM_POST_PMU:
2595 /* wait for cnp time */
2596 usleep_range(1000, 1100);
2597 break;
2598 case SND_SOC_DAPM_POST_PMD:
2599 wcd9335_micbias_control(comp, micb_num, MICB_DISABLE, true);
2600 break;
2601 }
2602
2603 return 0;
2604 }
2605
wcd9335_codec_enable_micbias(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)2606 static int wcd9335_codec_enable_micbias(struct snd_soc_dapm_widget *w,
2607 struct snd_kcontrol *kc, int event)
2608 {
2609 return __wcd9335_codec_enable_micbias(w, event);
2610 }
2611
wcd9335_codec_set_tx_hold(struct snd_soc_component * comp,u16 amic_reg,bool set)2612 static void wcd9335_codec_set_tx_hold(struct snd_soc_component *comp,
2613 u16 amic_reg, bool set)
2614 {
2615 u8 mask = 0x20;
2616 u8 val;
2617
2618 if (amic_reg == WCD9335_ANA_AMIC1 || amic_reg == WCD9335_ANA_AMIC3 ||
2619 amic_reg == WCD9335_ANA_AMIC5)
2620 mask = 0x40;
2621
2622 val = set ? mask : 0x00;
2623
2624 switch (amic_reg) {
2625 case WCD9335_ANA_AMIC1:
2626 case WCD9335_ANA_AMIC2:
2627 snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC2, mask,
2628 val);
2629 break;
2630 case WCD9335_ANA_AMIC3:
2631 case WCD9335_ANA_AMIC4:
2632 snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC4, mask,
2633 val);
2634 break;
2635 case WCD9335_ANA_AMIC5:
2636 case WCD9335_ANA_AMIC6:
2637 snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC6, mask,
2638 val);
2639 break;
2640 default:
2641 dev_err(comp->dev, "%s: invalid amic: %d\n",
2642 __func__, amic_reg);
2643 break;
2644 }
2645 }
2646
wcd9335_codec_enable_adc(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)2647 static int wcd9335_codec_enable_adc(struct snd_soc_dapm_widget *w,
2648 struct snd_kcontrol *kc, int event)
2649 {
2650 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
2651
2652 switch (event) {
2653 case SND_SOC_DAPM_PRE_PMU:
2654 wcd9335_codec_set_tx_hold(comp, w->reg, true);
2655 break;
2656 default:
2657 break;
2658 }
2659
2660 return 0;
2661 }
2662
wcd9335_codec_find_amic_input(struct snd_soc_component * comp,int adc_mux_n)2663 static int wcd9335_codec_find_amic_input(struct snd_soc_component *comp,
2664 int adc_mux_n)
2665 {
2666 int mux_sel, reg, mreg;
2667
2668 if (adc_mux_n < 0 || adc_mux_n > WCD9335_MAX_VALID_ADC_MUX ||
2669 adc_mux_n == WCD9335_INVALID_ADC_MUX)
2670 return 0;
2671
2672 /* Check whether adc mux input is AMIC or DMIC */
2673 if (adc_mux_n < 4) {
2674 reg = WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1 + 2 * adc_mux_n;
2675 mreg = WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0 + 2 * adc_mux_n;
2676 mux_sel = snd_soc_component_read(comp, reg) & 0x3;
2677 } else {
2678 reg = WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + adc_mux_n - 4;
2679 mreg = reg;
2680 mux_sel = snd_soc_component_read(comp, reg) >> 6;
2681 }
2682
2683 if (mux_sel != WCD9335_CDC_TX_INP_MUX_SEL_AMIC)
2684 return 0;
2685
2686 return snd_soc_component_read(comp, mreg) & 0x07;
2687 }
2688
wcd9335_codec_get_amic_pwlvl_reg(struct snd_soc_component * comp,int amic)2689 static u16 wcd9335_codec_get_amic_pwlvl_reg(struct snd_soc_component *comp,
2690 int amic)
2691 {
2692 u16 pwr_level_reg = 0;
2693
2694 switch (amic) {
2695 case 1:
2696 case 2:
2697 pwr_level_reg = WCD9335_ANA_AMIC1;
2698 break;
2699
2700 case 3:
2701 case 4:
2702 pwr_level_reg = WCD9335_ANA_AMIC3;
2703 break;
2704
2705 case 5:
2706 case 6:
2707 pwr_level_reg = WCD9335_ANA_AMIC5;
2708 break;
2709 default:
2710 dev_err(comp->dev, "invalid amic: %d\n", amic);
2711 break;
2712 }
2713
2714 return pwr_level_reg;
2715 }
2716
wcd9335_codec_enable_dec(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)2717 static int wcd9335_codec_enable_dec(struct snd_soc_dapm_widget *w,
2718 struct snd_kcontrol *kc, int event)
2719 {
2720 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
2721 unsigned int decimator;
2722 char *dec_adc_mux_name = NULL;
2723 char *widget_name;
2724 int ret = 0, amic_n;
2725 u16 tx_vol_ctl_reg, pwr_level_reg = 0, dec_cfg_reg, hpf_gate_reg;
2726 u16 tx_gain_ctl_reg;
2727 char *dec;
2728 u8 hpf_coff_freq;
2729
2730 char *wname __free(kfree) = kmemdup_nul(w->name, 15, GFP_KERNEL);
2731 if (!wname)
2732 return -ENOMEM;
2733
2734 widget_name = wname;
2735 dec_adc_mux_name = strsep(&widget_name, " ");
2736 if (!dec_adc_mux_name) {
2737 dev_err(comp->dev, "%s: Invalid decimator = %s\n",
2738 __func__, w->name);
2739 return -EINVAL;
2740 }
2741 dec_adc_mux_name = widget_name;
2742
2743 dec = strpbrk(dec_adc_mux_name, "012345678");
2744 if (!dec) {
2745 dev_err(comp->dev, "%s: decimator index not found\n",
2746 __func__);
2747 return -EINVAL;
2748 }
2749
2750 ret = kstrtouint(dec, 10, &decimator);
2751 if (ret < 0) {
2752 dev_err(comp->dev, "%s: Invalid decimator = %s\n",
2753 __func__, wname);
2754 return -EINVAL;
2755 }
2756
2757 tx_vol_ctl_reg = WCD9335_CDC_TX0_TX_PATH_CTL + 16 * decimator;
2758 hpf_gate_reg = WCD9335_CDC_TX0_TX_PATH_SEC2 + 16 * decimator;
2759 dec_cfg_reg = WCD9335_CDC_TX0_TX_PATH_CFG0 + 16 * decimator;
2760 tx_gain_ctl_reg = WCD9335_CDC_TX0_TX_VOL_CTL + 16 * decimator;
2761
2762 switch (event) {
2763 case SND_SOC_DAPM_PRE_PMU:
2764 amic_n = wcd9335_codec_find_amic_input(comp, decimator);
2765 if (amic_n)
2766 pwr_level_reg = wcd9335_codec_get_amic_pwlvl_reg(comp,
2767 amic_n);
2768
2769 if (pwr_level_reg) {
2770 switch ((snd_soc_component_read(comp, pwr_level_reg) &
2771 WCD9335_AMIC_PWR_LVL_MASK) >>
2772 WCD9335_AMIC_PWR_LVL_SHIFT) {
2773 case WCD9335_AMIC_PWR_LEVEL_LP:
2774 snd_soc_component_update_bits(comp, dec_cfg_reg,
2775 WCD9335_DEC_PWR_LVL_MASK,
2776 WCD9335_DEC_PWR_LVL_LP);
2777 break;
2778
2779 case WCD9335_AMIC_PWR_LEVEL_HP:
2780 snd_soc_component_update_bits(comp, dec_cfg_reg,
2781 WCD9335_DEC_PWR_LVL_MASK,
2782 WCD9335_DEC_PWR_LVL_HP);
2783 break;
2784 case WCD9335_AMIC_PWR_LEVEL_DEFAULT:
2785 default:
2786 snd_soc_component_update_bits(comp, dec_cfg_reg,
2787 WCD9335_DEC_PWR_LVL_MASK,
2788 WCD9335_DEC_PWR_LVL_DF);
2789 break;
2790 }
2791 }
2792 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) &
2793 TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
2794
2795 if (hpf_coff_freq != CF_MIN_3DB_150HZ)
2796 snd_soc_component_update_bits(comp, dec_cfg_reg,
2797 TX_HPF_CUT_OFF_FREQ_MASK,
2798 CF_MIN_3DB_150HZ << 5);
2799 /* Enable TX PGA Mute */
2800 snd_soc_component_update_bits(comp, tx_vol_ctl_reg,
2801 0x10, 0x10);
2802 /* Enable APC */
2803 snd_soc_component_update_bits(comp, dec_cfg_reg, 0x08, 0x08);
2804 break;
2805 case SND_SOC_DAPM_POST_PMU:
2806 snd_soc_component_update_bits(comp, hpf_gate_reg, 0x01, 0x00);
2807
2808 if (decimator == 0) {
2809 snd_soc_component_write(comp,
2810 WCD9335_MBHC_ZDET_RAMP_CTL, 0x83);
2811 snd_soc_component_write(comp,
2812 WCD9335_MBHC_ZDET_RAMP_CTL, 0xA3);
2813 snd_soc_component_write(comp,
2814 WCD9335_MBHC_ZDET_RAMP_CTL, 0x83);
2815 snd_soc_component_write(comp,
2816 WCD9335_MBHC_ZDET_RAMP_CTL, 0x03);
2817 }
2818
2819 snd_soc_component_update_bits(comp, hpf_gate_reg,
2820 0x01, 0x01);
2821 snd_soc_component_update_bits(comp, tx_vol_ctl_reg,
2822 0x10, 0x00);
2823 snd_soc_component_write(comp, tx_gain_ctl_reg,
2824 snd_soc_component_read(comp, tx_gain_ctl_reg));
2825 break;
2826 case SND_SOC_DAPM_PRE_PMD:
2827 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) &
2828 TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
2829 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 0x10, 0x10);
2830 snd_soc_component_update_bits(comp, dec_cfg_reg, 0x08, 0x00);
2831 if (hpf_coff_freq != CF_MIN_3DB_150HZ) {
2832 snd_soc_component_update_bits(comp, dec_cfg_reg,
2833 TX_HPF_CUT_OFF_FREQ_MASK,
2834 hpf_coff_freq << 5);
2835 }
2836 break;
2837 case SND_SOC_DAPM_POST_PMD:
2838 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 0x10, 0x00);
2839 break;
2840 }
2841
2842 return ret;
2843 }
2844
wcd9335_get_dmic_clk_val(struct snd_soc_component * component,u32 mclk_rate)2845 static u8 wcd9335_get_dmic_clk_val(struct snd_soc_component *component,
2846 u32 mclk_rate)
2847 {
2848 u8 dmic_ctl_val;
2849
2850 if (mclk_rate == WCD9335_MCLK_CLK_9P6MHZ)
2851 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_2;
2852 else
2853 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_3;
2854
2855 return dmic_ctl_val;
2856 }
2857
wcd9335_codec_enable_dmic(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)2858 static int wcd9335_codec_enable_dmic(struct snd_soc_dapm_widget *w,
2859 struct snd_kcontrol *kc, int event)
2860 {
2861 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
2862 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp);
2863 u8 dmic_clk_en = 0x01;
2864 u16 dmic_clk_reg;
2865 s32 *dmic_clk_cnt;
2866 u8 dmic_rate_val, dmic_rate_shift = 1;
2867 unsigned int dmic;
2868 int ret;
2869 char *wname;
2870
2871 wname = strpbrk(w->name, "012345");
2872 if (!wname) {
2873 dev_err(comp->dev, "%s: widget not found\n", __func__);
2874 return -EINVAL;
2875 }
2876
2877 ret = kstrtouint(wname, 10, &dmic);
2878 if (ret < 0) {
2879 dev_err(comp->dev, "%s: Invalid DMIC line on the codec\n",
2880 __func__);
2881 return -EINVAL;
2882 }
2883
2884 switch (dmic) {
2885 case 0:
2886 case 1:
2887 dmic_clk_cnt = &(wcd->dmic_0_1_clk_cnt);
2888 dmic_clk_reg = WCD9335_CPE_SS_DMIC0_CTL;
2889 break;
2890 case 2:
2891 case 3:
2892 dmic_clk_cnt = &(wcd->dmic_2_3_clk_cnt);
2893 dmic_clk_reg = WCD9335_CPE_SS_DMIC1_CTL;
2894 break;
2895 case 4:
2896 case 5:
2897 dmic_clk_cnt = &(wcd->dmic_4_5_clk_cnt);
2898 dmic_clk_reg = WCD9335_CPE_SS_DMIC2_CTL;
2899 break;
2900 default:
2901 dev_err(comp->dev, "%s: Invalid DMIC Selection\n",
2902 __func__);
2903 return -EINVAL;
2904 }
2905
2906 switch (event) {
2907 case SND_SOC_DAPM_PRE_PMU:
2908 dmic_rate_val = wcd9335_get_dmic_clk_val(comp, wcd->mclk_rate);
2909 (*dmic_clk_cnt)++;
2910 if (*dmic_clk_cnt == 1) {
2911 snd_soc_component_update_bits(comp, dmic_clk_reg,
2912 0x07 << dmic_rate_shift,
2913 dmic_rate_val << dmic_rate_shift);
2914 snd_soc_component_update_bits(comp, dmic_clk_reg,
2915 dmic_clk_en, dmic_clk_en);
2916 }
2917
2918 break;
2919 case SND_SOC_DAPM_POST_PMD:
2920 dmic_rate_val = wcd9335_get_dmic_clk_val(comp, wcd->mclk_rate);
2921 (*dmic_clk_cnt)--;
2922 if (*dmic_clk_cnt == 0) {
2923 snd_soc_component_update_bits(comp, dmic_clk_reg,
2924 dmic_clk_en, 0);
2925 snd_soc_component_update_bits(comp, dmic_clk_reg,
2926 0x07 << dmic_rate_shift,
2927 dmic_rate_val << dmic_rate_shift);
2928 }
2929 break;
2930 }
2931
2932 return 0;
2933 }
2934
wcd9335_codec_enable_int_port(struct wcd_slim_codec_dai_data * dai,struct snd_soc_component * component)2935 static void wcd9335_codec_enable_int_port(struct wcd_slim_codec_dai_data *dai,
2936 struct snd_soc_component *component)
2937 {
2938 int port_num = 0;
2939 unsigned short reg = 0;
2940 unsigned int val = 0;
2941 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
2942 struct wcd9335_slim_ch *ch;
2943
2944 list_for_each_entry(ch, &dai->slim_ch_list, list) {
2945 if (ch->port >= WCD9335_RX_START) {
2946 port_num = ch->port - WCD9335_RX_START;
2947 reg = WCD9335_SLIM_PGD_PORT_INT_EN0 + (port_num / 8);
2948 } else {
2949 port_num = ch->port;
2950 reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 + (port_num / 8);
2951 }
2952
2953 regmap_read(wcd->if_regmap, reg, &val);
2954 if (!(val & BIT(port_num % 8)))
2955 regmap_write(wcd->if_regmap, reg,
2956 val | BIT(port_num % 8));
2957 }
2958 }
2959
wcd9335_codec_enable_slim(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)2960 static int wcd9335_codec_enable_slim(struct snd_soc_dapm_widget *w,
2961 struct snd_kcontrol *kc,
2962 int event)
2963 {
2964 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
2965 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp);
2966 struct wcd_slim_codec_dai_data *dai = &wcd->dai[w->shift];
2967
2968 switch (event) {
2969 case SND_SOC_DAPM_POST_PMU:
2970 wcd9335_codec_enable_int_port(dai, comp);
2971 break;
2972 case SND_SOC_DAPM_POST_PMD:
2973 kfree(dai->sconfig.chs);
2974
2975 break;
2976 }
2977
2978 return 0;
2979 }
2980
wcd9335_codec_enable_mix_path(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)2981 static int wcd9335_codec_enable_mix_path(struct snd_soc_dapm_widget *w,
2982 struct snd_kcontrol *kc, int event)
2983 {
2984 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
2985 u16 gain_reg;
2986 int val = 0;
2987
2988 switch (w->reg) {
2989 case WCD9335_CDC_RX0_RX_PATH_MIX_CTL:
2990 gain_reg = WCD9335_CDC_RX0_RX_VOL_MIX_CTL;
2991 break;
2992 case WCD9335_CDC_RX1_RX_PATH_MIX_CTL:
2993 gain_reg = WCD9335_CDC_RX1_RX_VOL_MIX_CTL;
2994 break;
2995 case WCD9335_CDC_RX2_RX_PATH_MIX_CTL:
2996 gain_reg = WCD9335_CDC_RX2_RX_VOL_MIX_CTL;
2997 break;
2998 case WCD9335_CDC_RX3_RX_PATH_MIX_CTL:
2999 gain_reg = WCD9335_CDC_RX3_RX_VOL_MIX_CTL;
3000 break;
3001 case WCD9335_CDC_RX4_RX_PATH_MIX_CTL:
3002 gain_reg = WCD9335_CDC_RX4_RX_VOL_MIX_CTL;
3003 break;
3004 case WCD9335_CDC_RX5_RX_PATH_MIX_CTL:
3005 gain_reg = WCD9335_CDC_RX5_RX_VOL_MIX_CTL;
3006 break;
3007 case WCD9335_CDC_RX6_RX_PATH_MIX_CTL:
3008 gain_reg = WCD9335_CDC_RX6_RX_VOL_MIX_CTL;
3009 break;
3010 case WCD9335_CDC_RX7_RX_PATH_MIX_CTL:
3011 gain_reg = WCD9335_CDC_RX7_RX_VOL_MIX_CTL;
3012 break;
3013 case WCD9335_CDC_RX8_RX_PATH_MIX_CTL:
3014 gain_reg = WCD9335_CDC_RX8_RX_VOL_MIX_CTL;
3015 break;
3016 default:
3017 dev_err(comp->dev, "%s: No gain register avail for %s\n",
3018 __func__, w->name);
3019 return 0;
3020 }
3021
3022 switch (event) {
3023 case SND_SOC_DAPM_POST_PMU:
3024 val = snd_soc_component_read(comp, gain_reg);
3025 snd_soc_component_write(comp, gain_reg, val);
3026 break;
3027 case SND_SOC_DAPM_POST_PMD:
3028 break;
3029 }
3030
3031 return 0;
3032 }
3033
wcd9335_interp_get_primary_reg(u16 reg,u16 * ind)3034 static u16 wcd9335_interp_get_primary_reg(u16 reg, u16 *ind)
3035 {
3036 u16 prim_int_reg = WCD9335_CDC_RX0_RX_PATH_CTL;
3037
3038 switch (reg) {
3039 case WCD9335_CDC_RX0_RX_PATH_CTL:
3040 case WCD9335_CDC_RX0_RX_PATH_MIX_CTL:
3041 prim_int_reg = WCD9335_CDC_RX0_RX_PATH_CTL;
3042 *ind = 0;
3043 break;
3044 case WCD9335_CDC_RX1_RX_PATH_CTL:
3045 case WCD9335_CDC_RX1_RX_PATH_MIX_CTL:
3046 prim_int_reg = WCD9335_CDC_RX1_RX_PATH_CTL;
3047 *ind = 1;
3048 break;
3049 case WCD9335_CDC_RX2_RX_PATH_CTL:
3050 case WCD9335_CDC_RX2_RX_PATH_MIX_CTL:
3051 prim_int_reg = WCD9335_CDC_RX2_RX_PATH_CTL;
3052 *ind = 2;
3053 break;
3054 case WCD9335_CDC_RX3_RX_PATH_CTL:
3055 case WCD9335_CDC_RX3_RX_PATH_MIX_CTL:
3056 prim_int_reg = WCD9335_CDC_RX3_RX_PATH_CTL;
3057 *ind = 3;
3058 break;
3059 case WCD9335_CDC_RX4_RX_PATH_CTL:
3060 case WCD9335_CDC_RX4_RX_PATH_MIX_CTL:
3061 prim_int_reg = WCD9335_CDC_RX4_RX_PATH_CTL;
3062 *ind = 4;
3063 break;
3064 case WCD9335_CDC_RX5_RX_PATH_CTL:
3065 case WCD9335_CDC_RX5_RX_PATH_MIX_CTL:
3066 prim_int_reg = WCD9335_CDC_RX5_RX_PATH_CTL;
3067 *ind = 5;
3068 break;
3069 case WCD9335_CDC_RX6_RX_PATH_CTL:
3070 case WCD9335_CDC_RX6_RX_PATH_MIX_CTL:
3071 prim_int_reg = WCD9335_CDC_RX6_RX_PATH_CTL;
3072 *ind = 6;
3073 break;
3074 case WCD9335_CDC_RX7_RX_PATH_CTL:
3075 case WCD9335_CDC_RX7_RX_PATH_MIX_CTL:
3076 prim_int_reg = WCD9335_CDC_RX7_RX_PATH_CTL;
3077 *ind = 7;
3078 break;
3079 case WCD9335_CDC_RX8_RX_PATH_CTL:
3080 case WCD9335_CDC_RX8_RX_PATH_MIX_CTL:
3081 prim_int_reg = WCD9335_CDC_RX8_RX_PATH_CTL;
3082 *ind = 8;
3083 break;
3084 }
3085
3086 return prim_int_reg;
3087 }
3088
wcd9335_codec_hd2_control(struct snd_soc_component * component,u16 prim_int_reg,int event)3089 static void wcd9335_codec_hd2_control(struct snd_soc_component *component,
3090 u16 prim_int_reg, int event)
3091 {
3092 u16 hd2_scale_reg;
3093 u16 hd2_enable_reg = 0;
3094
3095 if (prim_int_reg == WCD9335_CDC_RX1_RX_PATH_CTL) {
3096 hd2_scale_reg = WCD9335_CDC_RX1_RX_PATH_SEC3;
3097 hd2_enable_reg = WCD9335_CDC_RX1_RX_PATH_CFG0;
3098 }
3099 if (prim_int_reg == WCD9335_CDC_RX2_RX_PATH_CTL) {
3100 hd2_scale_reg = WCD9335_CDC_RX2_RX_PATH_SEC3;
3101 hd2_enable_reg = WCD9335_CDC_RX2_RX_PATH_CFG0;
3102 }
3103
3104 if (hd2_enable_reg && SND_SOC_DAPM_EVENT_ON(event)) {
3105 snd_soc_component_update_bits(component, hd2_scale_reg,
3106 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_MASK,
3107 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_0P2500);
3108 snd_soc_component_update_bits(component, hd2_scale_reg,
3109 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_MASK,
3110 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_2);
3111 snd_soc_component_update_bits(component, hd2_enable_reg,
3112 WCD9335_CDC_RX_PATH_CFG_HD2_EN_MASK,
3113 WCD9335_CDC_RX_PATH_CFG_HD2_ENABLE);
3114 }
3115
3116 if (hd2_enable_reg && SND_SOC_DAPM_EVENT_OFF(event)) {
3117 snd_soc_component_update_bits(component, hd2_enable_reg,
3118 WCD9335_CDC_RX_PATH_CFG_HD2_EN_MASK,
3119 WCD9335_CDC_RX_PATH_CFG_HD2_DISABLE);
3120 snd_soc_component_update_bits(component, hd2_scale_reg,
3121 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_MASK,
3122 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_1);
3123 snd_soc_component_update_bits(component, hd2_scale_reg,
3124 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_MASK,
3125 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_0P0000);
3126 }
3127 }
3128
wcd9335_codec_enable_prim_interpolator(struct snd_soc_component * comp,u16 reg,int event)3129 static int wcd9335_codec_enable_prim_interpolator(
3130 struct snd_soc_component *comp,
3131 u16 reg, int event)
3132 {
3133 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3134 u16 ind = 0;
3135 int prim_int_reg = wcd9335_interp_get_primary_reg(reg, &ind);
3136
3137 switch (event) {
3138 case SND_SOC_DAPM_PRE_PMU:
3139 wcd->prim_int_users[ind]++;
3140 if (wcd->prim_int_users[ind] == 1) {
3141 snd_soc_component_update_bits(comp, prim_int_reg,
3142 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3143 WCD9335_CDC_RX_PGA_MUTE_ENABLE);
3144 wcd9335_codec_hd2_control(comp, prim_int_reg, event);
3145 snd_soc_component_update_bits(comp, prim_int_reg,
3146 WCD9335_CDC_RX_CLK_EN_MASK,
3147 WCD9335_CDC_RX_CLK_ENABLE);
3148 }
3149
3150 if ((reg != prim_int_reg) &&
3151 ((snd_soc_component_read(comp, prim_int_reg)) &
3152 WCD9335_CDC_RX_PGA_MUTE_EN_MASK))
3153 snd_soc_component_update_bits(comp, reg,
3154 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3155 WCD9335_CDC_RX_PGA_MUTE_ENABLE);
3156 break;
3157 case SND_SOC_DAPM_POST_PMD:
3158 wcd->prim_int_users[ind]--;
3159 if (wcd->prim_int_users[ind] == 0) {
3160 snd_soc_component_update_bits(comp, prim_int_reg,
3161 WCD9335_CDC_RX_CLK_EN_MASK,
3162 WCD9335_CDC_RX_CLK_DISABLE);
3163 snd_soc_component_update_bits(comp, prim_int_reg,
3164 WCD9335_CDC_RX_RESET_MASK,
3165 WCD9335_CDC_RX_RESET_ENABLE);
3166 snd_soc_component_update_bits(comp, prim_int_reg,
3167 WCD9335_CDC_RX_RESET_MASK,
3168 WCD9335_CDC_RX_RESET_DISABLE);
3169 wcd9335_codec_hd2_control(comp, prim_int_reg, event);
3170 }
3171 break;
3172 }
3173
3174 return 0;
3175 }
3176
wcd9335_config_compander(struct snd_soc_component * component,int interp_n,int event)3177 static int wcd9335_config_compander(struct snd_soc_component *component,
3178 int interp_n, int event)
3179 {
3180 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
3181 int comp;
3182 u16 comp_ctl0_reg, rx_path_cfg0_reg;
3183
3184 /* EAR does not have compander */
3185 if (!interp_n)
3186 return 0;
3187
3188 comp = interp_n - 1;
3189 if (!wcd->comp_enabled[comp])
3190 return 0;
3191
3192 comp_ctl0_reg = WCD9335_CDC_COMPANDER1_CTL(comp);
3193 rx_path_cfg0_reg = WCD9335_CDC_RX1_RX_PATH_CFG(comp);
3194
3195 if (SND_SOC_DAPM_EVENT_ON(event)) {
3196 /* Enable Compander Clock */
3197 snd_soc_component_update_bits(component, comp_ctl0_reg,
3198 WCD9335_CDC_COMPANDER_CLK_EN_MASK,
3199 WCD9335_CDC_COMPANDER_CLK_ENABLE);
3200 /* Reset comander */
3201 snd_soc_component_update_bits(component, comp_ctl0_reg,
3202 WCD9335_CDC_COMPANDER_SOFT_RST_MASK,
3203 WCD9335_CDC_COMPANDER_SOFT_RST_ENABLE);
3204 snd_soc_component_update_bits(component, comp_ctl0_reg,
3205 WCD9335_CDC_COMPANDER_SOFT_RST_MASK,
3206 WCD9335_CDC_COMPANDER_SOFT_RST_DISABLE);
3207 /* Enables DRE in this path */
3208 snd_soc_component_update_bits(component, rx_path_cfg0_reg,
3209 WCD9335_CDC_RX_PATH_CFG_CMP_EN_MASK,
3210 WCD9335_CDC_RX_PATH_CFG_CMP_ENABLE);
3211 }
3212
3213 if (SND_SOC_DAPM_EVENT_OFF(event)) {
3214 snd_soc_component_update_bits(component, comp_ctl0_reg,
3215 WCD9335_CDC_COMPANDER_HALT_MASK,
3216 WCD9335_CDC_COMPANDER_HALT);
3217 snd_soc_component_update_bits(component, rx_path_cfg0_reg,
3218 WCD9335_CDC_RX_PATH_CFG_CMP_EN_MASK,
3219 WCD9335_CDC_RX_PATH_CFG_CMP_DISABLE);
3220
3221 snd_soc_component_update_bits(component, comp_ctl0_reg,
3222 WCD9335_CDC_COMPANDER_SOFT_RST_MASK,
3223 WCD9335_CDC_COMPANDER_SOFT_RST_ENABLE);
3224 snd_soc_component_update_bits(component, comp_ctl0_reg,
3225 WCD9335_CDC_COMPANDER_SOFT_RST_MASK,
3226 WCD9335_CDC_COMPANDER_SOFT_RST_DISABLE);
3227 snd_soc_component_update_bits(component, comp_ctl0_reg,
3228 WCD9335_CDC_COMPANDER_CLK_EN_MASK,
3229 WCD9335_CDC_COMPANDER_CLK_DISABLE);
3230 snd_soc_component_update_bits(component, comp_ctl0_reg,
3231 WCD9335_CDC_COMPANDER_HALT_MASK,
3232 WCD9335_CDC_COMPANDER_NOHALT);
3233 }
3234
3235 return 0;
3236 }
3237
wcd9335_codec_enable_interpolator(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3238 static int wcd9335_codec_enable_interpolator(struct snd_soc_dapm_widget *w,
3239 struct snd_kcontrol *kc, int event)
3240 {
3241 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3242 u16 gain_reg;
3243 u16 reg;
3244 int val;
3245
3246 if (!(snd_soc_dapm_widget_name_cmp(w, "RX INT0 INTERP"))) {
3247 reg = WCD9335_CDC_RX0_RX_PATH_CTL;
3248 gain_reg = WCD9335_CDC_RX0_RX_VOL_CTL;
3249 } else if (!(snd_soc_dapm_widget_name_cmp(w, "RX INT1 INTERP"))) {
3250 reg = WCD9335_CDC_RX1_RX_PATH_CTL;
3251 gain_reg = WCD9335_CDC_RX1_RX_VOL_CTL;
3252 } else if (!(snd_soc_dapm_widget_name_cmp(w, "RX INT2 INTERP"))) {
3253 reg = WCD9335_CDC_RX2_RX_PATH_CTL;
3254 gain_reg = WCD9335_CDC_RX2_RX_VOL_CTL;
3255 } else if (!(snd_soc_dapm_widget_name_cmp(w, "RX INT3 INTERP"))) {
3256 reg = WCD9335_CDC_RX3_RX_PATH_CTL;
3257 gain_reg = WCD9335_CDC_RX3_RX_VOL_CTL;
3258 } else if (!(snd_soc_dapm_widget_name_cmp(w, "RX INT4 INTERP"))) {
3259 reg = WCD9335_CDC_RX4_RX_PATH_CTL;
3260 gain_reg = WCD9335_CDC_RX4_RX_VOL_CTL;
3261 } else if (!(snd_soc_dapm_widget_name_cmp(w, "RX INT5 INTERP"))) {
3262 reg = WCD9335_CDC_RX5_RX_PATH_CTL;
3263 gain_reg = WCD9335_CDC_RX5_RX_VOL_CTL;
3264 } else if (!(snd_soc_dapm_widget_name_cmp(w, "RX INT6 INTERP"))) {
3265 reg = WCD9335_CDC_RX6_RX_PATH_CTL;
3266 gain_reg = WCD9335_CDC_RX6_RX_VOL_CTL;
3267 } else if (!(snd_soc_dapm_widget_name_cmp(w, "RX INT7 INTERP"))) {
3268 reg = WCD9335_CDC_RX7_RX_PATH_CTL;
3269 gain_reg = WCD9335_CDC_RX7_RX_VOL_CTL;
3270 } else if (!(snd_soc_dapm_widget_name_cmp(w, "RX INT8 INTERP"))) {
3271 reg = WCD9335_CDC_RX8_RX_PATH_CTL;
3272 gain_reg = WCD9335_CDC_RX8_RX_VOL_CTL;
3273 } else {
3274 dev_err(comp->dev, "%s: Interpolator reg not found\n",
3275 __func__);
3276 return -EINVAL;
3277 }
3278
3279 switch (event) {
3280 case SND_SOC_DAPM_PRE_PMU:
3281 /* Reset if needed */
3282 wcd9335_codec_enable_prim_interpolator(comp, reg, event);
3283 break;
3284 case SND_SOC_DAPM_POST_PMU:
3285 wcd9335_config_compander(comp, w->shift, event);
3286 val = snd_soc_component_read(comp, gain_reg);
3287 snd_soc_component_write(comp, gain_reg, val);
3288 break;
3289 case SND_SOC_DAPM_POST_PMD:
3290 wcd9335_config_compander(comp, w->shift, event);
3291 wcd9335_codec_enable_prim_interpolator(comp, reg, event);
3292 break;
3293 }
3294
3295 return 0;
3296 }
3297
wcd9335_codec_hph_mode_gain_opt(struct snd_soc_component * component,u8 gain)3298 static void wcd9335_codec_hph_mode_gain_opt(struct snd_soc_component *component,
3299 u8 gain)
3300 {
3301 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
3302 u8 hph_l_en, hph_r_en;
3303 u8 l_val, r_val;
3304 u8 hph_pa_status;
3305 bool is_hphl_pa, is_hphr_pa;
3306
3307 hph_pa_status = snd_soc_component_read(component, WCD9335_ANA_HPH);
3308 is_hphl_pa = hph_pa_status >> 7;
3309 is_hphr_pa = (hph_pa_status & 0x40) >> 6;
3310
3311 hph_l_en = snd_soc_component_read(component, WCD9335_HPH_L_EN);
3312 hph_r_en = snd_soc_component_read(component, WCD9335_HPH_R_EN);
3313
3314 l_val = (hph_l_en & 0xC0) | 0x20 | gain;
3315 r_val = (hph_r_en & 0xC0) | 0x20 | gain;
3316
3317 /*
3318 * Set HPH_L & HPH_R gain source selection to REGISTER
3319 * for better click and pop only if corresponding PAs are
3320 * not enabled. Also cache the values of the HPHL/R
3321 * PA gains to be applied after PAs are enabled
3322 */
3323 if ((l_val != hph_l_en) && !is_hphl_pa) {
3324 snd_soc_component_write(component, WCD9335_HPH_L_EN, l_val);
3325 wcd->hph_l_gain = hph_l_en & 0x1F;
3326 }
3327
3328 if ((r_val != hph_r_en) && !is_hphr_pa) {
3329 snd_soc_component_write(component, WCD9335_HPH_R_EN, r_val);
3330 wcd->hph_r_gain = hph_r_en & 0x1F;
3331 }
3332 }
3333
wcd9335_codec_hph_lohifi_config(struct snd_soc_component * comp,int event)3334 static void wcd9335_codec_hph_lohifi_config(struct snd_soc_component *comp,
3335 int event)
3336 {
3337 if (SND_SOC_DAPM_EVENT_ON(event)) {
3338 snd_soc_component_update_bits(comp, WCD9335_RX_BIAS_HPH_PA,
3339 WCD9335_RX_BIAS_HPH_PA_AMP_5_UA_MASK,
3340 0x06);
3341 snd_soc_component_update_bits(comp,
3342 WCD9335_RX_BIAS_HPH_RDACBUFF_CNP2,
3343 0xF0, 0x40);
3344 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
3345 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
3346 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000);
3347 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3348 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
3349 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE);
3350 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1,
3351 WCD9335_HPH_PA_GM3_IB_SCALE_MASK,
3352 0x0C);
3353 wcd9335_codec_hph_mode_gain_opt(comp, 0x11);
3354 }
3355
3356 if (SND_SOC_DAPM_EVENT_OFF(event)) {
3357 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3358 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
3359 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE);
3360 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
3361 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
3362 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500);
3363 snd_soc_component_write(comp, WCD9335_RX_BIAS_HPH_RDACBUFF_CNP2,
3364 0x8A);
3365 snd_soc_component_update_bits(comp, WCD9335_RX_BIAS_HPH_PA,
3366 WCD9335_RX_BIAS_HPH_PA_AMP_5_UA_MASK,
3367 0x0A);
3368 }
3369 }
3370
wcd9335_codec_hph_lp_config(struct snd_soc_component * comp,int event)3371 static void wcd9335_codec_hph_lp_config(struct snd_soc_component *comp,
3372 int event)
3373 {
3374 if (SND_SOC_DAPM_EVENT_ON(event)) {
3375 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1,
3376 WCD9335_HPH_PA_GM3_IB_SCALE_MASK,
3377 0x0C);
3378 wcd9335_codec_hph_mode_gain_opt(comp, 0x10);
3379 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
3380 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
3381 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000);
3382 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3383 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
3384 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE);
3385 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3386 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_MASK,
3387 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_ENABLE);
3388 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3389 WCD9335_HPH_PA_CTL2_HPH_PSRR_ENH_MASK,
3390 WCD9335_HPH_PA_CTL2_HPH_PSRR_ENABLE);
3391 snd_soc_component_update_bits(comp, WCD9335_HPH_RDAC_LDO_CTL,
3392 WCD9335_HPH_RDAC_N1P65_LD_OUTCTL_MASK,
3393 WCD9335_HPH_RDAC_N1P65_LD_OUTCTL_V_N1P60);
3394 snd_soc_component_update_bits(comp, WCD9335_HPH_RDAC_LDO_CTL,
3395 WCD9335_HPH_RDAC_1P65_LD_OUTCTL_MASK,
3396 WCD9335_HPH_RDAC_1P65_LD_OUTCTL_V_N1P60);
3397 snd_soc_component_update_bits(comp,
3398 WCD9335_RX_BIAS_HPH_RDAC_LDO, 0x0F, 0x01);
3399 snd_soc_component_update_bits(comp,
3400 WCD9335_RX_BIAS_HPH_RDAC_LDO, 0xF0, 0x10);
3401 }
3402
3403 if (SND_SOC_DAPM_EVENT_OFF(event)) {
3404 snd_soc_component_write(comp, WCD9335_RX_BIAS_HPH_RDAC_LDO,
3405 0x88);
3406 snd_soc_component_write(comp, WCD9335_HPH_RDAC_LDO_CTL,
3407 0x33);
3408 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3409 WCD9335_HPH_PA_CTL2_HPH_PSRR_ENH_MASK,
3410 WCD9335_HPH_PA_CTL2_HPH_PSRR_DISABLE);
3411 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3412 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_MASK,
3413 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_DISABLE);
3414 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3415 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
3416 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE);
3417 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
3418 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
3419 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500);
3420 snd_soc_component_update_bits(comp, WCD9335_HPH_R_EN,
3421 WCD9335_HPH_CONST_SEL_L_MASK,
3422 WCD9335_HPH_CONST_SEL_L_HQ_PATH);
3423 snd_soc_component_update_bits(comp, WCD9335_HPH_L_EN,
3424 WCD9335_HPH_CONST_SEL_L_MASK,
3425 WCD9335_HPH_CONST_SEL_L_HQ_PATH);
3426 }
3427 }
3428
wcd9335_codec_hph_hifi_config(struct snd_soc_component * comp,int event)3429 static void wcd9335_codec_hph_hifi_config(struct snd_soc_component *comp,
3430 int event)
3431 {
3432 if (SND_SOC_DAPM_EVENT_ON(event)) {
3433 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
3434 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
3435 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000);
3436 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3437 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
3438 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE);
3439 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1,
3440 WCD9335_HPH_PA_GM3_IB_SCALE_MASK,
3441 0x0C);
3442 wcd9335_codec_hph_mode_gain_opt(comp, 0x11);
3443 }
3444
3445 if (SND_SOC_DAPM_EVENT_OFF(event)) {
3446 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3447 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
3448 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE);
3449 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
3450 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
3451 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500);
3452 }
3453 }
3454
wcd9335_codec_hph_mode_config(struct snd_soc_component * component,int event,int mode)3455 static void wcd9335_codec_hph_mode_config(struct snd_soc_component *component,
3456 int event, int mode)
3457 {
3458 switch (mode) {
3459 case CLS_H_LP:
3460 wcd9335_codec_hph_lp_config(component, event);
3461 break;
3462 case CLS_H_LOHIFI:
3463 wcd9335_codec_hph_lohifi_config(component, event);
3464 break;
3465 case CLS_H_HIFI:
3466 wcd9335_codec_hph_hifi_config(component, event);
3467 break;
3468 }
3469 }
3470
wcd9335_codec_hphl_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3471 static int wcd9335_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
3472 struct snd_kcontrol *kc,
3473 int event)
3474 {
3475 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3476 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3477 int hph_mode = wcd->hph_mode;
3478 u8 dem_inp;
3479
3480 switch (event) {
3481 case SND_SOC_DAPM_PRE_PMU:
3482 /* Read DEM INP Select */
3483 dem_inp = snd_soc_component_read(comp,
3484 WCD9335_CDC_RX1_RX_PATH_SEC0) & 0x03;
3485 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) ||
3486 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) {
3487 dev_err(comp->dev, "Incorrect DEM Input\n");
3488 return -EINVAL;
3489 }
3490 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
3491 WCD_CLSH_STATE_HPHL,
3492 ((hph_mode == CLS_H_LOHIFI) ?
3493 CLS_H_HIFI : hph_mode));
3494
3495 wcd9335_codec_hph_mode_config(comp, event, hph_mode);
3496
3497 break;
3498 case SND_SOC_DAPM_POST_PMU:
3499 usleep_range(1000, 1100);
3500 break;
3501 case SND_SOC_DAPM_PRE_PMD:
3502 break;
3503 case SND_SOC_DAPM_POST_PMD:
3504 /* 1000us required as per HW requirement */
3505 usleep_range(1000, 1100);
3506
3507 if (!(wcd_clsh_ctrl_get_state(wcd->clsh_ctrl) &
3508 WCD_CLSH_STATE_HPHR))
3509 wcd9335_codec_hph_mode_config(comp, event, hph_mode);
3510
3511 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3512 WCD_CLSH_STATE_HPHL,
3513 ((hph_mode == CLS_H_LOHIFI) ?
3514 CLS_H_HIFI : hph_mode));
3515 break;
3516 }
3517
3518 return 0;
3519 }
3520
wcd9335_codec_lineout_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3521 static int wcd9335_codec_lineout_dac_event(struct snd_soc_dapm_widget *w,
3522 struct snd_kcontrol *kc, int event)
3523 {
3524 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3525 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3526
3527 switch (event) {
3528 case SND_SOC_DAPM_PRE_PMU:
3529 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
3530 WCD_CLSH_STATE_LO, CLS_AB);
3531 break;
3532 case SND_SOC_DAPM_POST_PMD:
3533 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3534 WCD_CLSH_STATE_LO, CLS_AB);
3535 break;
3536 }
3537
3538 return 0;
3539 }
3540
wcd9335_codec_ear_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3541 static int wcd9335_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
3542 struct snd_kcontrol *kc, int event)
3543 {
3544 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3545 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3546
3547 switch (event) {
3548 case SND_SOC_DAPM_PRE_PMU:
3549 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
3550 WCD_CLSH_STATE_EAR, CLS_H_NORMAL);
3551
3552 break;
3553 case SND_SOC_DAPM_POST_PMD:
3554 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3555 WCD_CLSH_STATE_EAR, CLS_H_NORMAL);
3556 break;
3557 }
3558
3559 return 0;
3560 }
3561
wcd9335_codec_hph_post_pa_config(struct wcd9335_codec * wcd,int mode,int event)3562 static void wcd9335_codec_hph_post_pa_config(struct wcd9335_codec *wcd,
3563 int mode, int event)
3564 {
3565 u8 scale_val = 0;
3566
3567 switch (event) {
3568 case SND_SOC_DAPM_POST_PMU:
3569 switch (mode) {
3570 case CLS_H_HIFI:
3571 scale_val = 0x3;
3572 break;
3573 case CLS_H_LOHIFI:
3574 scale_val = 0x1;
3575 break;
3576 }
3577 break;
3578 case SND_SOC_DAPM_PRE_PMD:
3579 scale_val = 0x6;
3580 break;
3581 }
3582
3583 if (scale_val)
3584 snd_soc_component_update_bits(wcd->component,
3585 WCD9335_HPH_PA_CTL1,
3586 WCD9335_HPH_PA_GM3_IB_SCALE_MASK,
3587 scale_val << 1);
3588 if (SND_SOC_DAPM_EVENT_ON(event)) {
3589 if (wcd->comp_enabled[COMPANDER_1] ||
3590 wcd->comp_enabled[COMPANDER_2]) {
3591 /* GAIN Source Selection */
3592 snd_soc_component_update_bits(wcd->component,
3593 WCD9335_HPH_L_EN,
3594 WCD9335_HPH_GAIN_SRC_SEL_MASK,
3595 WCD9335_HPH_GAIN_SRC_SEL_COMPANDER);
3596 snd_soc_component_update_bits(wcd->component,
3597 WCD9335_HPH_R_EN,
3598 WCD9335_HPH_GAIN_SRC_SEL_MASK,
3599 WCD9335_HPH_GAIN_SRC_SEL_COMPANDER);
3600 snd_soc_component_update_bits(wcd->component,
3601 WCD9335_HPH_AUTO_CHOP,
3602 WCD9335_HPH_AUTO_CHOP_MASK,
3603 WCD9335_HPH_AUTO_CHOP_FORCE_ENABLE);
3604 }
3605 snd_soc_component_update_bits(wcd->component,
3606 WCD9335_HPH_L_EN,
3607 WCD9335_HPH_PA_GAIN_MASK,
3608 wcd->hph_l_gain);
3609 snd_soc_component_update_bits(wcd->component,
3610 WCD9335_HPH_R_EN,
3611 WCD9335_HPH_PA_GAIN_MASK,
3612 wcd->hph_r_gain);
3613 }
3614
3615 if (SND_SOC_DAPM_EVENT_OFF(event))
3616 snd_soc_component_update_bits(wcd->component,
3617 WCD9335_HPH_AUTO_CHOP,
3618 WCD9335_HPH_AUTO_CHOP_MASK,
3619 WCD9335_HPH_AUTO_CHOP_ENABLE_BY_CMPDR_GAIN);
3620 }
3621
wcd9335_codec_hphr_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3622 static int wcd9335_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
3623 struct snd_kcontrol *kc,
3624 int event)
3625 {
3626 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3627 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3628 int hph_mode = wcd->hph_mode;
3629 u8 dem_inp;
3630
3631 switch (event) {
3632 case SND_SOC_DAPM_PRE_PMU:
3633
3634 /* Read DEM INP Select */
3635 dem_inp = snd_soc_component_read(comp,
3636 WCD9335_CDC_RX2_RX_PATH_SEC0) &
3637 WCD9335_CDC_RX_PATH_DEM_INP_SEL_MASK;
3638 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) ||
3639 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) {
3640 dev_err(comp->dev, "DEM Input not set correctly, hph_mode: %d\n",
3641 hph_mode);
3642 return -EINVAL;
3643 }
3644
3645 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl,
3646 WCD_CLSH_EVENT_PRE_DAC,
3647 WCD_CLSH_STATE_HPHR,
3648 ((hph_mode == CLS_H_LOHIFI) ?
3649 CLS_H_HIFI : hph_mode));
3650
3651 wcd9335_codec_hph_mode_config(comp, event, hph_mode);
3652
3653 break;
3654 case SND_SOC_DAPM_POST_PMD:
3655 /* 1000us required as per HW requirement */
3656 usleep_range(1000, 1100);
3657
3658 if (!(wcd_clsh_ctrl_get_state(wcd->clsh_ctrl) &
3659 WCD_CLSH_STATE_HPHL))
3660 wcd9335_codec_hph_mode_config(comp, event, hph_mode);
3661
3662 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3663 WCD_CLSH_STATE_HPHR, ((hph_mode == CLS_H_LOHIFI) ?
3664 CLS_H_HIFI : hph_mode));
3665 break;
3666 }
3667
3668 return 0;
3669 }
3670
wcd9335_codec_enable_hphl_pa(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3671 static int wcd9335_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
3672 struct snd_kcontrol *kc,
3673 int event)
3674 {
3675 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3676 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3677 int hph_mode = wcd->hph_mode;
3678
3679 switch (event) {
3680 case SND_SOC_DAPM_PRE_PMU:
3681 break;
3682 case SND_SOC_DAPM_POST_PMU:
3683 /*
3684 * 7ms sleep is required after PA is enabled as per
3685 * HW requirement
3686 */
3687 usleep_range(7000, 7100);
3688
3689 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event);
3690 snd_soc_component_update_bits(comp,
3691 WCD9335_CDC_RX1_RX_PATH_CTL,
3692 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3693 WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3694
3695 /* Remove mix path mute if it is enabled */
3696 if ((snd_soc_component_read(comp,
3697 WCD9335_CDC_RX1_RX_PATH_MIX_CTL)) &
3698 WCD9335_CDC_RX_PGA_MUTE_EN_MASK)
3699 snd_soc_component_update_bits(comp,
3700 WCD9335_CDC_RX1_RX_PATH_MIX_CTL,
3701 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3702 WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3703
3704 break;
3705 case SND_SOC_DAPM_PRE_PMD:
3706 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event);
3707 break;
3708 case SND_SOC_DAPM_POST_PMD:
3709 /* 5ms sleep is required after PA is disabled as per
3710 * HW requirement
3711 */
3712 usleep_range(5000, 5500);
3713 break;
3714 }
3715
3716 return 0;
3717 }
3718
wcd9335_codec_enable_lineout_pa(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3719 static int wcd9335_codec_enable_lineout_pa(struct snd_soc_dapm_widget *w,
3720 struct snd_kcontrol *kc,
3721 int event)
3722 {
3723 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3724 int vol_reg = 0, mix_vol_reg = 0;
3725
3726 if (w->reg == WCD9335_ANA_LO_1_2) {
3727 if (w->shift == 7) {
3728 vol_reg = WCD9335_CDC_RX3_RX_PATH_CTL;
3729 mix_vol_reg = WCD9335_CDC_RX3_RX_PATH_MIX_CTL;
3730 } else if (w->shift == 6) {
3731 vol_reg = WCD9335_CDC_RX4_RX_PATH_CTL;
3732 mix_vol_reg = WCD9335_CDC_RX4_RX_PATH_MIX_CTL;
3733 }
3734 } else if (w->reg == WCD9335_ANA_LO_3_4) {
3735 if (w->shift == 7) {
3736 vol_reg = WCD9335_CDC_RX5_RX_PATH_CTL;
3737 mix_vol_reg = WCD9335_CDC_RX5_RX_PATH_MIX_CTL;
3738 } else if (w->shift == 6) {
3739 vol_reg = WCD9335_CDC_RX6_RX_PATH_CTL;
3740 mix_vol_reg = WCD9335_CDC_RX6_RX_PATH_MIX_CTL;
3741 }
3742 } else {
3743 dev_err(comp->dev, "Error enabling lineout PA\n");
3744 return -EINVAL;
3745 }
3746
3747 switch (event) {
3748 case SND_SOC_DAPM_POST_PMU:
3749 /* 5ms sleep is required after PA is enabled as per
3750 * HW requirement
3751 */
3752 usleep_range(5000, 5500);
3753 snd_soc_component_update_bits(comp, vol_reg,
3754 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3755 WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3756
3757 /* Remove mix path mute if it is enabled */
3758 if ((snd_soc_component_read(comp, mix_vol_reg)) &
3759 WCD9335_CDC_RX_PGA_MUTE_EN_MASK)
3760 snd_soc_component_update_bits(comp, mix_vol_reg,
3761 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3762 WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3763 break;
3764 case SND_SOC_DAPM_POST_PMD:
3765 /* 5ms sleep is required after PA is disabled as per
3766 * HW requirement
3767 */
3768 usleep_range(5000, 5500);
3769 break;
3770 }
3771
3772 return 0;
3773 }
3774
wcd9335_codec_init_flyback(struct snd_soc_component * component)3775 static void wcd9335_codec_init_flyback(struct snd_soc_component *component)
3776 {
3777 snd_soc_component_update_bits(component, WCD9335_HPH_L_EN,
3778 WCD9335_HPH_CONST_SEL_L_MASK,
3779 WCD9335_HPH_CONST_SEL_L_BYPASS);
3780 snd_soc_component_update_bits(component, WCD9335_HPH_R_EN,
3781 WCD9335_HPH_CONST_SEL_L_MASK,
3782 WCD9335_HPH_CONST_SEL_L_BYPASS);
3783 snd_soc_component_update_bits(component, WCD9335_RX_BIAS_FLYB_BUFF,
3784 WCD9335_RX_BIAS_FLYB_VPOS_5_UA_MASK,
3785 WCD9335_RX_BIAS_FLYB_I_0P0_UA);
3786 snd_soc_component_update_bits(component, WCD9335_RX_BIAS_FLYB_BUFF,
3787 WCD9335_RX_BIAS_FLYB_VNEG_5_UA_MASK,
3788 WCD9335_RX_BIAS_FLYB_I_0P0_UA);
3789 }
3790
wcd9335_codec_enable_rx_bias(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3791 static int wcd9335_codec_enable_rx_bias(struct snd_soc_dapm_widget *w,
3792 struct snd_kcontrol *kc, int event)
3793 {
3794 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3795 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3796
3797 switch (event) {
3798 case SND_SOC_DAPM_PRE_PMU:
3799 wcd->rx_bias_count++;
3800 if (wcd->rx_bias_count == 1) {
3801 wcd9335_codec_init_flyback(comp);
3802 snd_soc_component_update_bits(comp,
3803 WCD9335_ANA_RX_SUPPLIES,
3804 WCD9335_ANA_RX_BIAS_ENABLE_MASK,
3805 WCD9335_ANA_RX_BIAS_ENABLE);
3806 }
3807 break;
3808 case SND_SOC_DAPM_POST_PMD:
3809 wcd->rx_bias_count--;
3810 if (!wcd->rx_bias_count)
3811 snd_soc_component_update_bits(comp,
3812 WCD9335_ANA_RX_SUPPLIES,
3813 WCD9335_ANA_RX_BIAS_ENABLE_MASK,
3814 WCD9335_ANA_RX_BIAS_DISABLE);
3815 break;
3816 }
3817
3818 return 0;
3819 }
3820
wcd9335_codec_enable_hphr_pa(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3821 static int wcd9335_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
3822 struct snd_kcontrol *kc, int event)
3823 {
3824 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3825 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3826 int hph_mode = wcd->hph_mode;
3827
3828 switch (event) {
3829 case SND_SOC_DAPM_PRE_PMU:
3830 break;
3831 case SND_SOC_DAPM_POST_PMU:
3832 /*
3833 * 7ms sleep is required after PA is enabled as per
3834 * HW requirement
3835 */
3836 usleep_range(7000, 7100);
3837 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event);
3838 snd_soc_component_update_bits(comp,
3839 WCD9335_CDC_RX2_RX_PATH_CTL,
3840 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3841 WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3842 /* Remove mix path mute if it is enabled */
3843 if ((snd_soc_component_read(comp,
3844 WCD9335_CDC_RX2_RX_PATH_MIX_CTL)) &
3845 WCD9335_CDC_RX_PGA_MUTE_EN_MASK)
3846 snd_soc_component_update_bits(comp,
3847 WCD9335_CDC_RX2_RX_PATH_MIX_CTL,
3848 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3849 WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3850
3851 break;
3852
3853 case SND_SOC_DAPM_PRE_PMD:
3854 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event);
3855 break;
3856 case SND_SOC_DAPM_POST_PMD:
3857 /* 5ms sleep is required after PA is disabled as per
3858 * HW requirement
3859 */
3860 usleep_range(5000, 5500);
3861 break;
3862 }
3863
3864 return 0;
3865 }
3866
wcd9335_codec_enable_ear_pa(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3867 static int wcd9335_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
3868 struct snd_kcontrol *kc, int event)
3869 {
3870 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3871
3872 switch (event) {
3873 case SND_SOC_DAPM_POST_PMU:
3874 /* 5ms sleep is required after PA is enabled as per
3875 * HW requirement
3876 */
3877 usleep_range(5000, 5500);
3878 snd_soc_component_update_bits(comp,
3879 WCD9335_CDC_RX0_RX_PATH_CTL,
3880 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3881 WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3882 /* Remove mix path mute if it is enabled */
3883 if ((snd_soc_component_read(comp,
3884 WCD9335_CDC_RX0_RX_PATH_MIX_CTL)) &
3885 WCD9335_CDC_RX_PGA_MUTE_EN_MASK)
3886 snd_soc_component_update_bits(comp,
3887 WCD9335_CDC_RX0_RX_PATH_MIX_CTL,
3888 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3889 WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3890 break;
3891 case SND_SOC_DAPM_POST_PMD:
3892 /* 5ms sleep is required after PA is disabled as per
3893 * HW requirement
3894 */
3895 usleep_range(5000, 5500);
3896
3897 break;
3898 }
3899
3900 return 0;
3901 }
3902
wcd9335_slimbus_irq(int irq,void * data)3903 static irqreturn_t wcd9335_slimbus_irq(int irq, void *data)
3904 {
3905 struct wcd9335_codec *wcd = data;
3906 unsigned long status = 0;
3907 int i, j, port_id;
3908 unsigned int val, int_val = 0;
3909 irqreturn_t ret = IRQ_NONE;
3910 bool tx;
3911 unsigned short reg = 0;
3912
3913 for (i = WCD9335_SLIM_PGD_PORT_INT_STATUS_RX_0, j = 0;
3914 i <= WCD9335_SLIM_PGD_PORT_INT_STATUS_TX_1; i++, j++) {
3915 regmap_read(wcd->if_regmap, i, &val);
3916 status |= ((u32)val << (8 * j));
3917 }
3918
3919 for_each_set_bit(j, &status, 32) {
3920 tx = (j >= 16);
3921 port_id = (tx ? j - 16 : j);
3922 regmap_read(wcd->if_regmap,
3923 WCD9335_SLIM_PGD_PORT_INT_RX_SOURCE0 + j, &val);
3924 if (val) {
3925 if (!tx)
3926 reg = WCD9335_SLIM_PGD_PORT_INT_EN0 +
3927 (port_id / 8);
3928 else
3929 reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 +
3930 (port_id / 8);
3931 regmap_read(
3932 wcd->if_regmap, reg, &int_val);
3933 /*
3934 * Ignore interrupts for ports for which the
3935 * interrupts are not specifically enabled.
3936 */
3937 if (!(int_val & (1 << (port_id % 8))))
3938 continue;
3939 }
3940
3941 if (val & WCD9335_SLIM_IRQ_OVERFLOW)
3942 dev_err_ratelimited(wcd->dev,
3943 "%s: overflow error on %s port %d, value %x\n",
3944 __func__, (tx ? "TX" : "RX"), port_id, val);
3945
3946 if (val & WCD9335_SLIM_IRQ_UNDERFLOW)
3947 dev_err_ratelimited(wcd->dev,
3948 "%s: underflow error on %s port %d, value %x\n",
3949 __func__, (tx ? "TX" : "RX"), port_id, val);
3950
3951 if ((val & WCD9335_SLIM_IRQ_OVERFLOW) ||
3952 (val & WCD9335_SLIM_IRQ_UNDERFLOW)) {
3953 if (!tx)
3954 reg = WCD9335_SLIM_PGD_PORT_INT_EN0 +
3955 (port_id / 8);
3956 else
3957 reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 +
3958 (port_id / 8);
3959 regmap_read(
3960 wcd->if_regmap, reg, &int_val);
3961 if (int_val & (1 << (port_id % 8))) {
3962 int_val = int_val ^ (1 << (port_id % 8));
3963 regmap_write(wcd->if_regmap,
3964 reg, int_val);
3965 }
3966 }
3967
3968 regmap_write(wcd->if_regmap,
3969 WCD9335_SLIM_PGD_PORT_INT_CLR_RX_0 + (j / 8),
3970 BIT(j % 8));
3971 ret = IRQ_HANDLED;
3972 }
3973
3974 return ret;
3975 }
3976
3977 static const struct wcd9335_irq wcd9335_irqs[] = {
3978 {
3979 .irq = WCD9335_IRQ_SLIMBUS,
3980 .handler = wcd9335_slimbus_irq,
3981 .name = "SLIM Slave",
3982 },
3983 };
3984
wcd9335_setup_irqs(struct wcd9335_codec * wcd)3985 static int wcd9335_setup_irqs(struct wcd9335_codec *wcd)
3986 {
3987 int irq, ret, i;
3988
3989 for (i = 0; i < ARRAY_SIZE(wcd9335_irqs); i++) {
3990 irq = regmap_irq_get_virq(wcd->irq_data, wcd9335_irqs[i].irq);
3991 if (irq < 0) {
3992 dev_err(wcd->dev, "Failed to get %s\n",
3993 wcd9335_irqs[i].name);
3994 return irq;
3995 }
3996
3997 ret = devm_request_threaded_irq(wcd->dev, irq, NULL,
3998 wcd9335_irqs[i].handler,
3999 IRQF_TRIGGER_RISING |
4000 IRQF_ONESHOT,
4001 wcd9335_irqs[i].name, wcd);
4002 if (ret) {
4003 dev_err(wcd->dev, "Failed to request %s\n",
4004 wcd9335_irqs[i].name);
4005 return ret;
4006 }
4007 }
4008
4009 /* enable interrupts on all slave ports */
4010 for (i = 0; i < WCD9335_SLIM_NUM_PORT_REG; i++)
4011 regmap_write(wcd->if_regmap, WCD9335_SLIM_PGD_PORT_INT_EN0 + i,
4012 0xFF);
4013
4014 return ret;
4015 }
4016
wcd9335_teardown_irqs(struct wcd9335_codec * wcd)4017 static void wcd9335_teardown_irqs(struct wcd9335_codec *wcd)
4018 {
4019 int i;
4020
4021 /* disable interrupts on all slave ports */
4022 for (i = 0; i < WCD9335_SLIM_NUM_PORT_REG; i++)
4023 regmap_write(wcd->if_regmap, WCD9335_SLIM_PGD_PORT_INT_EN0 + i,
4024 0x00);
4025 }
4026
wcd9335_cdc_sido_ccl_enable(struct wcd9335_codec * wcd,bool ccl_flag)4027 static void wcd9335_cdc_sido_ccl_enable(struct wcd9335_codec *wcd,
4028 bool ccl_flag)
4029 {
4030 struct snd_soc_component *comp = wcd->component;
4031
4032 if (ccl_flag) {
4033 if (++wcd->sido_ccl_cnt == 1)
4034 snd_soc_component_write(comp, WCD9335_SIDO_SIDO_CCL_10,
4035 WCD9335_SIDO_SIDO_CCL_DEF_VALUE);
4036 } else {
4037 if (wcd->sido_ccl_cnt == 0) {
4038 dev_err(wcd->dev, "sido_ccl already disabled\n");
4039 return;
4040 }
4041 if (--wcd->sido_ccl_cnt == 0)
4042 snd_soc_component_write(comp, WCD9335_SIDO_SIDO_CCL_10,
4043 WCD9335_SIDO_SIDO_CCL_10_ICHARG_PWR_SEL_C320FF);
4044 }
4045 }
4046
wcd9335_enable_master_bias(struct wcd9335_codec * wcd)4047 static int wcd9335_enable_master_bias(struct wcd9335_codec *wcd)
4048 {
4049 wcd->master_bias_users++;
4050 if (wcd->master_bias_users == 1) {
4051 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
4052 WCD9335_ANA_BIAS_EN_MASK,
4053 WCD9335_ANA_BIAS_ENABLE);
4054 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
4055 WCD9335_ANA_BIAS_PRECHRG_EN_MASK,
4056 WCD9335_ANA_BIAS_PRECHRG_ENABLE);
4057 /*
4058 * 1ms delay is required after pre-charge is enabled
4059 * as per HW requirement
4060 */
4061 usleep_range(1000, 1100);
4062 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
4063 WCD9335_ANA_BIAS_PRECHRG_EN_MASK,
4064 WCD9335_ANA_BIAS_PRECHRG_DISABLE);
4065 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
4066 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE,
4067 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE_MANUAL);
4068 }
4069
4070 return 0;
4071 }
4072
wcd9335_enable_mclk(struct wcd9335_codec * wcd)4073 static int wcd9335_enable_mclk(struct wcd9335_codec *wcd)
4074 {
4075 /* Enable mclk requires master bias to be enabled first */
4076 if (wcd->master_bias_users <= 0)
4077 return -EINVAL;
4078
4079 if (((wcd->clk_mclk_users == 0) && (wcd->clk_type == WCD_CLK_MCLK)) ||
4080 ((wcd->clk_mclk_users > 0) && (wcd->clk_type != WCD_CLK_MCLK))) {
4081 dev_err(wcd->dev, "Error enabling MCLK, clk_type: %d\n",
4082 wcd->clk_type);
4083 return -EINVAL;
4084 }
4085
4086 if (++wcd->clk_mclk_users == 1) {
4087 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
4088 WCD9335_ANA_CLK_EXT_CLKBUF_EN_MASK,
4089 WCD9335_ANA_CLK_EXT_CLKBUF_ENABLE);
4090 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
4091 WCD9335_ANA_CLK_MCLK_SRC_MASK,
4092 WCD9335_ANA_CLK_MCLK_SRC_EXTERNAL);
4093 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
4094 WCD9335_ANA_CLK_MCLK_EN_MASK,
4095 WCD9335_ANA_CLK_MCLK_ENABLE);
4096 regmap_update_bits(wcd->regmap,
4097 WCD9335_CDC_CLK_RST_CTRL_FS_CNT_CONTROL,
4098 WCD9335_CDC_CLK_RST_CTRL_FS_CNT_EN_MASK,
4099 WCD9335_CDC_CLK_RST_CTRL_FS_CNT_ENABLE);
4100 regmap_update_bits(wcd->regmap,
4101 WCD9335_CDC_CLK_RST_CTRL_MCLK_CONTROL,
4102 WCD9335_CDC_CLK_RST_CTRL_MCLK_EN_MASK,
4103 WCD9335_CDC_CLK_RST_CTRL_MCLK_ENABLE);
4104 /*
4105 * 10us sleep is required after clock is enabled
4106 * as per HW requirement
4107 */
4108 usleep_range(10, 15);
4109 }
4110
4111 wcd->clk_type = WCD_CLK_MCLK;
4112
4113 return 0;
4114 }
4115
wcd9335_disable_mclk(struct wcd9335_codec * wcd)4116 static int wcd9335_disable_mclk(struct wcd9335_codec *wcd)
4117 {
4118 if (wcd->clk_mclk_users <= 0)
4119 return -EINVAL;
4120
4121 if (--wcd->clk_mclk_users == 0) {
4122 if (wcd->clk_rco_users > 0) {
4123 /* MCLK to RCO switch */
4124 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
4125 WCD9335_ANA_CLK_MCLK_SRC_MASK,
4126 WCD9335_ANA_CLK_MCLK_SRC_RCO);
4127 wcd->clk_type = WCD_CLK_RCO;
4128 } else {
4129 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
4130 WCD9335_ANA_CLK_MCLK_EN_MASK,
4131 WCD9335_ANA_CLK_MCLK_DISABLE);
4132 wcd->clk_type = WCD_CLK_OFF;
4133 }
4134
4135 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
4136 WCD9335_ANA_CLK_EXT_CLKBUF_EN_MASK,
4137 WCD9335_ANA_CLK_EXT_CLKBUF_DISABLE);
4138 }
4139
4140 return 0;
4141 }
4142
wcd9335_disable_master_bias(struct wcd9335_codec * wcd)4143 static int wcd9335_disable_master_bias(struct wcd9335_codec *wcd)
4144 {
4145 if (wcd->master_bias_users <= 0)
4146 return -EINVAL;
4147
4148 wcd->master_bias_users--;
4149 if (wcd->master_bias_users == 0) {
4150 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
4151 WCD9335_ANA_BIAS_EN_MASK,
4152 WCD9335_ANA_BIAS_DISABLE);
4153 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
4154 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE,
4155 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE_MANUAL);
4156 }
4157 return 0;
4158 }
4159
wcd9335_cdc_req_mclk_enable(struct wcd9335_codec * wcd,bool enable)4160 static int wcd9335_cdc_req_mclk_enable(struct wcd9335_codec *wcd,
4161 bool enable)
4162 {
4163 int ret = 0;
4164
4165 if (enable) {
4166 wcd9335_cdc_sido_ccl_enable(wcd, true);
4167 ret = clk_prepare_enable(wcd->mclk);
4168 if (ret) {
4169 dev_err(wcd->dev, "%s: ext clk enable failed\n",
4170 __func__);
4171 goto err;
4172 }
4173 /* get BG */
4174 wcd9335_enable_master_bias(wcd);
4175 /* get MCLK */
4176 wcd9335_enable_mclk(wcd);
4177
4178 } else {
4179 /* put MCLK */
4180 wcd9335_disable_mclk(wcd);
4181 /* put BG */
4182 wcd9335_disable_master_bias(wcd);
4183 clk_disable_unprepare(wcd->mclk);
4184 wcd9335_cdc_sido_ccl_enable(wcd, false);
4185 }
4186 err:
4187 return ret;
4188 }
4189
wcd9335_codec_apply_sido_voltage(struct wcd9335_codec * wcd,enum wcd9335_sido_voltage req_mv)4190 static void wcd9335_codec_apply_sido_voltage(struct wcd9335_codec *wcd,
4191 enum wcd9335_sido_voltage req_mv)
4192 {
4193 struct snd_soc_component *comp = wcd->component;
4194 int vout_d_val;
4195
4196 if (req_mv == wcd->sido_voltage)
4197 return;
4198
4199 /* compute the vout_d step value */
4200 vout_d_val = WCD9335_CALCULATE_VOUT_D(req_mv) &
4201 WCD9335_ANA_BUCK_VOUT_MASK;
4202 snd_soc_component_write(comp, WCD9335_ANA_BUCK_VOUT_D, vout_d_val);
4203 snd_soc_component_update_bits(comp, WCD9335_ANA_BUCK_CTL,
4204 WCD9335_ANA_BUCK_CTL_RAMP_START_MASK,
4205 WCD9335_ANA_BUCK_CTL_RAMP_START_ENABLE);
4206
4207 /* 1 msec sleep required after SIDO Vout_D voltage change */
4208 usleep_range(1000, 1100);
4209 wcd->sido_voltage = req_mv;
4210 snd_soc_component_update_bits(comp, WCD9335_ANA_BUCK_CTL,
4211 WCD9335_ANA_BUCK_CTL_RAMP_START_MASK,
4212 WCD9335_ANA_BUCK_CTL_RAMP_START_DISABLE);
4213 }
4214
wcd9335_codec_update_sido_voltage(struct wcd9335_codec * wcd,enum wcd9335_sido_voltage req_mv)4215 static int wcd9335_codec_update_sido_voltage(struct wcd9335_codec *wcd,
4216 enum wcd9335_sido_voltage req_mv)
4217 {
4218 int ret = 0;
4219
4220 /* enable mclk before setting SIDO voltage */
4221 ret = wcd9335_cdc_req_mclk_enable(wcd, true);
4222 if (ret) {
4223 dev_err(wcd->dev, "Ext clk enable failed\n");
4224 goto err;
4225 }
4226
4227 wcd9335_codec_apply_sido_voltage(wcd, req_mv);
4228 wcd9335_cdc_req_mclk_enable(wcd, false);
4229
4230 err:
4231 return ret;
4232 }
4233
_wcd9335_codec_enable_mclk(struct snd_soc_component * component,int enable)4234 static int _wcd9335_codec_enable_mclk(struct snd_soc_component *component,
4235 int enable)
4236 {
4237 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
4238 int ret;
4239
4240 if (enable) {
4241 ret = wcd9335_cdc_req_mclk_enable(wcd, true);
4242 if (ret)
4243 return ret;
4244
4245 wcd9335_codec_apply_sido_voltage(wcd,
4246 SIDO_VOLTAGE_NOMINAL_MV);
4247 } else {
4248 wcd9335_codec_update_sido_voltage(wcd,
4249 wcd->sido_voltage);
4250 wcd9335_cdc_req_mclk_enable(wcd, false);
4251 }
4252
4253 return 0;
4254 }
4255
wcd9335_codec_enable_mclk(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)4256 static int wcd9335_codec_enable_mclk(struct snd_soc_dapm_widget *w,
4257 struct snd_kcontrol *kc, int event)
4258 {
4259 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4260
4261 switch (event) {
4262 case SND_SOC_DAPM_PRE_PMU:
4263 return _wcd9335_codec_enable_mclk(comp, true);
4264 case SND_SOC_DAPM_POST_PMD:
4265 return _wcd9335_codec_enable_mclk(comp, false);
4266 }
4267
4268 return 0;
4269 }
4270
4271 static const struct snd_soc_dapm_widget wcd9335_dapm_widgets[] = {
4272 /* TODO SPK1 & SPK2 OUT*/
4273 SND_SOC_DAPM_OUTPUT("EAR"),
4274 SND_SOC_DAPM_OUTPUT("HPHL"),
4275 SND_SOC_DAPM_OUTPUT("HPHR"),
4276 SND_SOC_DAPM_OUTPUT("LINEOUT1"),
4277 SND_SOC_DAPM_OUTPUT("LINEOUT2"),
4278 SND_SOC_DAPM_OUTPUT("LINEOUT3"),
4279 SND_SOC_DAPM_OUTPUT("LINEOUT4"),
4280 SND_SOC_DAPM_AIF_IN_E("AIF1 PB", "AIF1 Playback", 0, SND_SOC_NOPM,
4281 AIF1_PB, 0, wcd9335_codec_enable_slim,
4282 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4283 SND_SOC_DAPM_AIF_IN_E("AIF2 PB", "AIF2 Playback", 0, SND_SOC_NOPM,
4284 AIF2_PB, 0, wcd9335_codec_enable_slim,
4285 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4286 SND_SOC_DAPM_AIF_IN_E("AIF3 PB", "AIF3 Playback", 0, SND_SOC_NOPM,
4287 AIF3_PB, 0, wcd9335_codec_enable_slim,
4288 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4289 SND_SOC_DAPM_AIF_IN_E("AIF4 PB", "AIF4 Playback", 0, SND_SOC_NOPM,
4290 AIF4_PB, 0, wcd9335_codec_enable_slim,
4291 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4292 SND_SOC_DAPM_MUX("SLIM RX0 MUX", SND_SOC_NOPM, WCD9335_RX0, 0,
4293 &slim_rx_mux[WCD9335_RX0]),
4294 SND_SOC_DAPM_MUX("SLIM RX1 MUX", SND_SOC_NOPM, WCD9335_RX1, 0,
4295 &slim_rx_mux[WCD9335_RX1]),
4296 SND_SOC_DAPM_MUX("SLIM RX2 MUX", SND_SOC_NOPM, WCD9335_RX2, 0,
4297 &slim_rx_mux[WCD9335_RX2]),
4298 SND_SOC_DAPM_MUX("SLIM RX3 MUX", SND_SOC_NOPM, WCD9335_RX3, 0,
4299 &slim_rx_mux[WCD9335_RX3]),
4300 SND_SOC_DAPM_MUX("SLIM RX4 MUX", SND_SOC_NOPM, WCD9335_RX4, 0,
4301 &slim_rx_mux[WCD9335_RX4]),
4302 SND_SOC_DAPM_MUX("SLIM RX5 MUX", SND_SOC_NOPM, WCD9335_RX5, 0,
4303 &slim_rx_mux[WCD9335_RX5]),
4304 SND_SOC_DAPM_MUX("SLIM RX6 MUX", SND_SOC_NOPM, WCD9335_RX6, 0,
4305 &slim_rx_mux[WCD9335_RX6]),
4306 SND_SOC_DAPM_MUX("SLIM RX7 MUX", SND_SOC_NOPM, WCD9335_RX7, 0,
4307 &slim_rx_mux[WCD9335_RX7]),
4308 SND_SOC_DAPM_MIXER("SLIM RX0", SND_SOC_NOPM, 0, 0, NULL, 0),
4309 SND_SOC_DAPM_MIXER("SLIM RX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4310 SND_SOC_DAPM_MIXER("SLIM RX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4311 SND_SOC_DAPM_MIXER("SLIM RX3", SND_SOC_NOPM, 0, 0, NULL, 0),
4312 SND_SOC_DAPM_MIXER("SLIM RX4", SND_SOC_NOPM, 0, 0, NULL, 0),
4313 SND_SOC_DAPM_MIXER("SLIM RX5", SND_SOC_NOPM, 0, 0, NULL, 0),
4314 SND_SOC_DAPM_MIXER("SLIM RX6", SND_SOC_NOPM, 0, 0, NULL, 0),
4315 SND_SOC_DAPM_MIXER("SLIM RX7", SND_SOC_NOPM, 0, 0, NULL, 0),
4316 SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", WCD9335_CDC_RX0_RX_PATH_MIX_CTL,
4317 5, 0, &rx_int0_2_mux, wcd9335_codec_enable_mix_path,
4318 SND_SOC_DAPM_POST_PMU),
4319 SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", WCD9335_CDC_RX1_RX_PATH_MIX_CTL,
4320 5, 0, &rx_int1_2_mux, wcd9335_codec_enable_mix_path,
4321 SND_SOC_DAPM_POST_PMU),
4322 SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", WCD9335_CDC_RX2_RX_PATH_MIX_CTL,
4323 5, 0, &rx_int2_2_mux, wcd9335_codec_enable_mix_path,
4324 SND_SOC_DAPM_POST_PMU),
4325 SND_SOC_DAPM_MUX_E("RX INT3_2 MUX", WCD9335_CDC_RX3_RX_PATH_MIX_CTL,
4326 5, 0, &rx_int3_2_mux, wcd9335_codec_enable_mix_path,
4327 SND_SOC_DAPM_POST_PMU),
4328 SND_SOC_DAPM_MUX_E("RX INT4_2 MUX", WCD9335_CDC_RX4_RX_PATH_MIX_CTL,
4329 5, 0, &rx_int4_2_mux, wcd9335_codec_enable_mix_path,
4330 SND_SOC_DAPM_POST_PMU),
4331 SND_SOC_DAPM_MUX_E("RX INT5_2 MUX", WCD9335_CDC_RX5_RX_PATH_MIX_CTL,
4332 5, 0, &rx_int5_2_mux, wcd9335_codec_enable_mix_path,
4333 SND_SOC_DAPM_POST_PMU),
4334 SND_SOC_DAPM_MUX_E("RX INT6_2 MUX", WCD9335_CDC_RX6_RX_PATH_MIX_CTL,
4335 5, 0, &rx_int6_2_mux, wcd9335_codec_enable_mix_path,
4336 SND_SOC_DAPM_POST_PMU),
4337 SND_SOC_DAPM_MUX_E("RX INT7_2 MUX", WCD9335_CDC_RX7_RX_PATH_MIX_CTL,
4338 5, 0, &rx_int7_2_mux, wcd9335_codec_enable_mix_path,
4339 SND_SOC_DAPM_POST_PMU),
4340 SND_SOC_DAPM_MUX_E("RX INT8_2 MUX", WCD9335_CDC_RX8_RX_PATH_MIX_CTL,
4341 5, 0, &rx_int8_2_mux, wcd9335_codec_enable_mix_path,
4342 SND_SOC_DAPM_POST_PMU),
4343 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4344 &rx_int0_1_mix_inp0_mux),
4345 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4346 &rx_int0_1_mix_inp1_mux),
4347 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4348 &rx_int0_1_mix_inp2_mux),
4349 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4350 &rx_int1_1_mix_inp0_mux),
4351 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4352 &rx_int1_1_mix_inp1_mux),
4353 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4354 &rx_int1_1_mix_inp2_mux),
4355 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4356 &rx_int2_1_mix_inp0_mux),
4357 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4358 &rx_int2_1_mix_inp1_mux),
4359 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4360 &rx_int2_1_mix_inp2_mux),
4361 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4362 &rx_int3_1_mix_inp0_mux),
4363 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4364 &rx_int3_1_mix_inp1_mux),
4365 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4366 &rx_int3_1_mix_inp2_mux),
4367 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4368 &rx_int4_1_mix_inp0_mux),
4369 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4370 &rx_int4_1_mix_inp1_mux),
4371 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4372 &rx_int4_1_mix_inp2_mux),
4373 SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4374 &rx_int5_1_mix_inp0_mux),
4375 SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4376 &rx_int5_1_mix_inp1_mux),
4377 SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4378 &rx_int5_1_mix_inp2_mux),
4379 SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4380 &rx_int6_1_mix_inp0_mux),
4381 SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4382 &rx_int6_1_mix_inp1_mux),
4383 SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4384 &rx_int6_1_mix_inp2_mux),
4385 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4386 &rx_int7_1_mix_inp0_mux),
4387 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4388 &rx_int7_1_mix_inp1_mux),
4389 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4390 &rx_int7_1_mix_inp2_mux),
4391 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4392 &rx_int8_1_mix_inp0_mux),
4393 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4394 &rx_int8_1_mix_inp1_mux),
4395 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4396 &rx_int8_1_mix_inp2_mux),
4397
4398 SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4399 SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4400 SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4401 SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4402 SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4403 SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4404 SND_SOC_DAPM_MIXER("RX INT3_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4405 SND_SOC_DAPM_MIXER("RX INT3 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4406 SND_SOC_DAPM_MIXER("RX INT4_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4407 SND_SOC_DAPM_MIXER("RX INT4 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4408 SND_SOC_DAPM_MIXER("RX INT5_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4409 SND_SOC_DAPM_MIXER("RX INT5 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4410 SND_SOC_DAPM_MIXER("RX INT6_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4411 SND_SOC_DAPM_MIXER("RX INT6 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4412 SND_SOC_DAPM_MIXER("RX INT7_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4413 SND_SOC_DAPM_MIXER("RX INT7 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4414 SND_SOC_DAPM_MIXER("RX INT8_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4415 SND_SOC_DAPM_MIXER("RX INT8 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4416
4417 SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4418 SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4419 SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4420 SND_SOC_DAPM_MIXER("RX INT3 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4421 SND_SOC_DAPM_MIXER("RX INT4 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4422 SND_SOC_DAPM_MIXER("RX INT5 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4423 SND_SOC_DAPM_MIXER("RX INT6 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4424 SND_SOC_DAPM_MIXER("RX INT7 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4425 SND_SOC_DAPM_MIXER("RX INT8 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4426
4427 SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0,
4428 &rx_int0_dem_inp_mux),
4429 SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0,
4430 &rx_int1_dem_inp_mux),
4431 SND_SOC_DAPM_MUX("RX INT2 DEM MUX", SND_SOC_NOPM, 0, 0,
4432 &rx_int2_dem_inp_mux),
4433
4434 SND_SOC_DAPM_MUX_E("RX INT0 INTERP", SND_SOC_NOPM,
4435 INTERP_EAR, 0, &rx_int0_interp_mux,
4436 wcd9335_codec_enable_interpolator,
4437 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4438 SND_SOC_DAPM_POST_PMD),
4439 SND_SOC_DAPM_MUX_E("RX INT1 INTERP", SND_SOC_NOPM,
4440 INTERP_HPHL, 0, &rx_int1_interp_mux,
4441 wcd9335_codec_enable_interpolator,
4442 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4443 SND_SOC_DAPM_POST_PMD),
4444 SND_SOC_DAPM_MUX_E("RX INT2 INTERP", SND_SOC_NOPM,
4445 INTERP_HPHR, 0, &rx_int2_interp_mux,
4446 wcd9335_codec_enable_interpolator,
4447 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4448 SND_SOC_DAPM_POST_PMD),
4449 SND_SOC_DAPM_MUX_E("RX INT3 INTERP", SND_SOC_NOPM,
4450 INTERP_LO1, 0, &rx_int3_interp_mux,
4451 wcd9335_codec_enable_interpolator,
4452 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4453 SND_SOC_DAPM_POST_PMD),
4454 SND_SOC_DAPM_MUX_E("RX INT4 INTERP", SND_SOC_NOPM,
4455 INTERP_LO2, 0, &rx_int4_interp_mux,
4456 wcd9335_codec_enable_interpolator,
4457 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4458 SND_SOC_DAPM_POST_PMD),
4459 SND_SOC_DAPM_MUX_E("RX INT5 INTERP", SND_SOC_NOPM,
4460 INTERP_LO3, 0, &rx_int5_interp_mux,
4461 wcd9335_codec_enable_interpolator,
4462 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4463 SND_SOC_DAPM_POST_PMD),
4464 SND_SOC_DAPM_MUX_E("RX INT6 INTERP", SND_SOC_NOPM,
4465 INTERP_LO4, 0, &rx_int6_interp_mux,
4466 wcd9335_codec_enable_interpolator,
4467 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4468 SND_SOC_DAPM_POST_PMD),
4469 SND_SOC_DAPM_MUX_E("RX INT7 INTERP", SND_SOC_NOPM,
4470 INTERP_SPKR1, 0, &rx_int7_interp_mux,
4471 wcd9335_codec_enable_interpolator,
4472 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4473 SND_SOC_DAPM_POST_PMD),
4474 SND_SOC_DAPM_MUX_E("RX INT8 INTERP", SND_SOC_NOPM,
4475 INTERP_SPKR2, 0, &rx_int8_interp_mux,
4476 wcd9335_codec_enable_interpolator,
4477 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4478 SND_SOC_DAPM_POST_PMD),
4479
4480 SND_SOC_DAPM_DAC_E("RX INT0 DAC", NULL, SND_SOC_NOPM,
4481 0, 0, wcd9335_codec_ear_dac_event,
4482 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4483 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4484 SND_SOC_DAPM_DAC_E("RX INT1 DAC", NULL, WCD9335_ANA_HPH,
4485 5, 0, wcd9335_codec_hphl_dac_event,
4486 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4487 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4488 SND_SOC_DAPM_DAC_E("RX INT2 DAC", NULL, WCD9335_ANA_HPH,
4489 4, 0, wcd9335_codec_hphr_dac_event,
4490 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4491 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4492 SND_SOC_DAPM_DAC_E("RX INT3 DAC", NULL, SND_SOC_NOPM,
4493 0, 0, wcd9335_codec_lineout_dac_event,
4494 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4495 SND_SOC_DAPM_DAC_E("RX INT4 DAC", NULL, SND_SOC_NOPM,
4496 0, 0, wcd9335_codec_lineout_dac_event,
4497 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4498 SND_SOC_DAPM_DAC_E("RX INT5 DAC", NULL, SND_SOC_NOPM,
4499 0, 0, wcd9335_codec_lineout_dac_event,
4500 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4501 SND_SOC_DAPM_DAC_E("RX INT6 DAC", NULL, SND_SOC_NOPM,
4502 0, 0, wcd9335_codec_lineout_dac_event,
4503 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4504 SND_SOC_DAPM_PGA_E("HPHL PA", WCD9335_ANA_HPH, 7, 0, NULL, 0,
4505 wcd9335_codec_enable_hphl_pa,
4506 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4507 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4508 SND_SOC_DAPM_PGA_E("HPHR PA", WCD9335_ANA_HPH, 6, 0, NULL, 0,
4509 wcd9335_codec_enable_hphr_pa,
4510 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4511 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4512 SND_SOC_DAPM_PGA_E("EAR PA", WCD9335_ANA_EAR, 7, 0, NULL, 0,
4513 wcd9335_codec_enable_ear_pa,
4514 SND_SOC_DAPM_POST_PMU |
4515 SND_SOC_DAPM_POST_PMD),
4516 SND_SOC_DAPM_PGA_E("LINEOUT1 PA", WCD9335_ANA_LO_1_2, 7, 0, NULL, 0,
4517 wcd9335_codec_enable_lineout_pa,
4518 SND_SOC_DAPM_POST_PMU |
4519 SND_SOC_DAPM_POST_PMD),
4520 SND_SOC_DAPM_PGA_E("LINEOUT2 PA", WCD9335_ANA_LO_1_2, 6, 0, NULL, 0,
4521 wcd9335_codec_enable_lineout_pa,
4522 SND_SOC_DAPM_POST_PMU |
4523 SND_SOC_DAPM_POST_PMD),
4524 SND_SOC_DAPM_PGA_E("LINEOUT3 PA", WCD9335_ANA_LO_3_4, 7, 0, NULL, 0,
4525 wcd9335_codec_enable_lineout_pa,
4526 SND_SOC_DAPM_POST_PMU |
4527 SND_SOC_DAPM_POST_PMD),
4528 SND_SOC_DAPM_PGA_E("LINEOUT4 PA", WCD9335_ANA_LO_3_4, 6, 0, NULL, 0,
4529 wcd9335_codec_enable_lineout_pa,
4530 SND_SOC_DAPM_POST_PMU |
4531 SND_SOC_DAPM_POST_PMD),
4532 SND_SOC_DAPM_SUPPLY("RX_BIAS", SND_SOC_NOPM, 0, 0,
4533 wcd9335_codec_enable_rx_bias, SND_SOC_DAPM_PRE_PMU |
4534 SND_SOC_DAPM_POST_PMD),
4535 SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0,
4536 wcd9335_codec_enable_mclk, SND_SOC_DAPM_PRE_PMU |
4537 SND_SOC_DAPM_POST_PMD),
4538
4539 /* TX */
4540 SND_SOC_DAPM_INPUT("AMIC1"),
4541 SND_SOC_DAPM_INPUT("AMIC2"),
4542 SND_SOC_DAPM_INPUT("AMIC3"),
4543 SND_SOC_DAPM_INPUT("AMIC4"),
4544 SND_SOC_DAPM_INPUT("AMIC5"),
4545 SND_SOC_DAPM_INPUT("AMIC6"),
4546
4547 SND_SOC_DAPM_AIF_OUT_E("AIF1 CAP", "AIF1 Capture", 0, SND_SOC_NOPM,
4548 AIF1_CAP, 0, wcd9335_codec_enable_slim,
4549 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4550
4551 SND_SOC_DAPM_AIF_OUT_E("AIF2 CAP", "AIF2 Capture", 0, SND_SOC_NOPM,
4552 AIF2_CAP, 0, wcd9335_codec_enable_slim,
4553 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4554
4555 SND_SOC_DAPM_AIF_OUT_E("AIF3 CAP", "AIF3 Capture", 0, SND_SOC_NOPM,
4556 AIF3_CAP, 0, wcd9335_codec_enable_slim,
4557 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4558
4559 SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0,
4560 wcd9335_codec_enable_micbias,
4561 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4562 SND_SOC_DAPM_POST_PMD),
4563 SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0,
4564 wcd9335_codec_enable_micbias,
4565 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4566 SND_SOC_DAPM_POST_PMD),
4567 SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0,
4568 wcd9335_codec_enable_micbias,
4569 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4570 SND_SOC_DAPM_POST_PMD),
4571 SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, 0, 0,
4572 wcd9335_codec_enable_micbias,
4573 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4574 SND_SOC_DAPM_POST_PMD),
4575
4576 SND_SOC_DAPM_ADC_E("ADC1", NULL, WCD9335_ANA_AMIC1, 7, 0,
4577 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4578 SND_SOC_DAPM_ADC_E("ADC2", NULL, WCD9335_ANA_AMIC2, 7, 0,
4579 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4580 SND_SOC_DAPM_ADC_E("ADC3", NULL, WCD9335_ANA_AMIC3, 7, 0,
4581 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4582 SND_SOC_DAPM_ADC_E("ADC4", NULL, WCD9335_ANA_AMIC4, 7, 0,
4583 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4584 SND_SOC_DAPM_ADC_E("ADC5", NULL, WCD9335_ANA_AMIC5, 7, 0,
4585 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4586 SND_SOC_DAPM_ADC_E("ADC6", NULL, WCD9335_ANA_AMIC6, 7, 0,
4587 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4588
4589 /* Digital Mic Inputs */
4590 SND_SOC_DAPM_ADC_E("DMIC0", NULL, SND_SOC_NOPM, 0, 0,
4591 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4592 SND_SOC_DAPM_POST_PMD),
4593
4594 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
4595 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4596 SND_SOC_DAPM_POST_PMD),
4597
4598 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0,
4599 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4600 SND_SOC_DAPM_POST_PMD),
4601
4602 SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 0, 0,
4603 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4604 SND_SOC_DAPM_POST_PMD),
4605
4606 SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 0, 0,
4607 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4608 SND_SOC_DAPM_POST_PMD),
4609
4610 SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 0, 0,
4611 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4612 SND_SOC_DAPM_POST_PMD),
4613
4614 SND_SOC_DAPM_MUX("DMIC MUX0", SND_SOC_NOPM, 0, 0,
4615 &tx_dmic_mux0),
4616 SND_SOC_DAPM_MUX("DMIC MUX1", SND_SOC_NOPM, 0, 0,
4617 &tx_dmic_mux1),
4618 SND_SOC_DAPM_MUX("DMIC MUX2", SND_SOC_NOPM, 0, 0,
4619 &tx_dmic_mux2),
4620 SND_SOC_DAPM_MUX("DMIC MUX3", SND_SOC_NOPM, 0, 0,
4621 &tx_dmic_mux3),
4622 SND_SOC_DAPM_MUX("DMIC MUX4", SND_SOC_NOPM, 0, 0,
4623 &tx_dmic_mux4),
4624 SND_SOC_DAPM_MUX("DMIC MUX5", SND_SOC_NOPM, 0, 0,
4625 &tx_dmic_mux5),
4626 SND_SOC_DAPM_MUX("DMIC MUX6", SND_SOC_NOPM, 0, 0,
4627 &tx_dmic_mux6),
4628 SND_SOC_DAPM_MUX("DMIC MUX7", SND_SOC_NOPM, 0, 0,
4629 &tx_dmic_mux7),
4630 SND_SOC_DAPM_MUX("DMIC MUX8", SND_SOC_NOPM, 0, 0,
4631 &tx_dmic_mux8),
4632
4633 SND_SOC_DAPM_MUX("AMIC MUX0", SND_SOC_NOPM, 0, 0,
4634 &tx_amic_mux0),
4635 SND_SOC_DAPM_MUX("AMIC MUX1", SND_SOC_NOPM, 0, 0,
4636 &tx_amic_mux1),
4637 SND_SOC_DAPM_MUX("AMIC MUX2", SND_SOC_NOPM, 0, 0,
4638 &tx_amic_mux2),
4639 SND_SOC_DAPM_MUX("AMIC MUX3", SND_SOC_NOPM, 0, 0,
4640 &tx_amic_mux3),
4641 SND_SOC_DAPM_MUX("AMIC MUX4", SND_SOC_NOPM, 0, 0,
4642 &tx_amic_mux4),
4643 SND_SOC_DAPM_MUX("AMIC MUX5", SND_SOC_NOPM, 0, 0,
4644 &tx_amic_mux5),
4645 SND_SOC_DAPM_MUX("AMIC MUX6", SND_SOC_NOPM, 0, 0,
4646 &tx_amic_mux6),
4647 SND_SOC_DAPM_MUX("AMIC MUX7", SND_SOC_NOPM, 0, 0,
4648 &tx_amic_mux7),
4649 SND_SOC_DAPM_MUX("AMIC MUX8", SND_SOC_NOPM, 0, 0,
4650 &tx_amic_mux8),
4651
4652 SND_SOC_DAPM_MIXER("AIF1_CAP Mixer", SND_SOC_NOPM, AIF1_CAP, 0,
4653 aif1_cap_mixer, ARRAY_SIZE(aif1_cap_mixer)),
4654
4655 SND_SOC_DAPM_MIXER("AIF2_CAP Mixer", SND_SOC_NOPM, AIF2_CAP, 0,
4656 aif2_cap_mixer, ARRAY_SIZE(aif2_cap_mixer)),
4657
4658 SND_SOC_DAPM_MIXER("AIF3_CAP Mixer", SND_SOC_NOPM, AIF3_CAP, 0,
4659 aif3_cap_mixer, ARRAY_SIZE(aif3_cap_mixer)),
4660
4661 SND_SOC_DAPM_MUX("SLIM TX0 MUX", SND_SOC_NOPM, WCD9335_TX0, 0,
4662 &sb_tx0_mux),
4663 SND_SOC_DAPM_MUX("SLIM TX1 MUX", SND_SOC_NOPM, WCD9335_TX1, 0,
4664 &sb_tx1_mux),
4665 SND_SOC_DAPM_MUX("SLIM TX2 MUX", SND_SOC_NOPM, WCD9335_TX2, 0,
4666 &sb_tx2_mux),
4667 SND_SOC_DAPM_MUX("SLIM TX3 MUX", SND_SOC_NOPM, WCD9335_TX3, 0,
4668 &sb_tx3_mux),
4669 SND_SOC_DAPM_MUX("SLIM TX4 MUX", SND_SOC_NOPM, WCD9335_TX4, 0,
4670 &sb_tx4_mux),
4671 SND_SOC_DAPM_MUX("SLIM TX5 MUX", SND_SOC_NOPM, WCD9335_TX5, 0,
4672 &sb_tx5_mux),
4673 SND_SOC_DAPM_MUX("SLIM TX6 MUX", SND_SOC_NOPM, WCD9335_TX6, 0,
4674 &sb_tx6_mux),
4675 SND_SOC_DAPM_MUX("SLIM TX7 MUX", SND_SOC_NOPM, WCD9335_TX7, 0,
4676 &sb_tx7_mux),
4677 SND_SOC_DAPM_MUX("SLIM TX8 MUX", SND_SOC_NOPM, WCD9335_TX8, 0,
4678 &sb_tx8_mux),
4679
4680 SND_SOC_DAPM_MUX_E("ADC MUX0", WCD9335_CDC_TX0_TX_PATH_CTL, 5, 0,
4681 &tx_adc_mux0, wcd9335_codec_enable_dec,
4682 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4683 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4684
4685 SND_SOC_DAPM_MUX_E("ADC MUX1", WCD9335_CDC_TX1_TX_PATH_CTL, 5, 0,
4686 &tx_adc_mux1, wcd9335_codec_enable_dec,
4687 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4688 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4689
4690 SND_SOC_DAPM_MUX_E("ADC MUX2", WCD9335_CDC_TX2_TX_PATH_CTL, 5, 0,
4691 &tx_adc_mux2, wcd9335_codec_enable_dec,
4692 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4693 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4694
4695 SND_SOC_DAPM_MUX_E("ADC MUX3", WCD9335_CDC_TX3_TX_PATH_CTL, 5, 0,
4696 &tx_adc_mux3, wcd9335_codec_enable_dec,
4697 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4698 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4699
4700 SND_SOC_DAPM_MUX_E("ADC MUX4", WCD9335_CDC_TX4_TX_PATH_CTL, 5, 0,
4701 &tx_adc_mux4, wcd9335_codec_enable_dec,
4702 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4703 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4704
4705 SND_SOC_DAPM_MUX_E("ADC MUX5", WCD9335_CDC_TX5_TX_PATH_CTL, 5, 0,
4706 &tx_adc_mux5, wcd9335_codec_enable_dec,
4707 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4708 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4709
4710 SND_SOC_DAPM_MUX_E("ADC MUX6", WCD9335_CDC_TX6_TX_PATH_CTL, 5, 0,
4711 &tx_adc_mux6, wcd9335_codec_enable_dec,
4712 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4713 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4714
4715 SND_SOC_DAPM_MUX_E("ADC MUX7", WCD9335_CDC_TX7_TX_PATH_CTL, 5, 0,
4716 &tx_adc_mux7, wcd9335_codec_enable_dec,
4717 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4718 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4719
4720 SND_SOC_DAPM_MUX_E("ADC MUX8", WCD9335_CDC_TX8_TX_PATH_CTL, 5, 0,
4721 &tx_adc_mux8, wcd9335_codec_enable_dec,
4722 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4723 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4724 };
4725
wcd9335_enable_sido_buck(struct snd_soc_component * component)4726 static void wcd9335_enable_sido_buck(struct snd_soc_component *component)
4727 {
4728 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
4729
4730 snd_soc_component_update_bits(component, WCD9335_ANA_RCO,
4731 WCD9335_ANA_RCO_BG_EN_MASK,
4732 WCD9335_ANA_RCO_BG_ENABLE);
4733 snd_soc_component_update_bits(component, WCD9335_ANA_BUCK_CTL,
4734 WCD9335_ANA_BUCK_CTL_VOUT_D_IREF_MASK,
4735 WCD9335_ANA_BUCK_CTL_VOUT_D_IREF_EXT);
4736 /* 100us sleep needed after IREF settings */
4737 usleep_range(100, 110);
4738 snd_soc_component_update_bits(component, WCD9335_ANA_BUCK_CTL,
4739 WCD9335_ANA_BUCK_CTL_VOUT_D_VREF_MASK,
4740 WCD9335_ANA_BUCK_CTL_VOUT_D_VREF_EXT);
4741 /* 100us sleep needed after VREF settings */
4742 usleep_range(100, 110);
4743 wcd->sido_input_src = SIDO_SOURCE_RCO_BG;
4744 }
4745
wcd9335_enable_efuse_sensing(struct snd_soc_component * comp)4746 static int wcd9335_enable_efuse_sensing(struct snd_soc_component *comp)
4747 {
4748 _wcd9335_codec_enable_mclk(comp, true);
4749 snd_soc_component_update_bits(comp,
4750 WCD9335_CHIP_TIER_CTRL_EFUSE_CTL,
4751 WCD9335_CHIP_TIER_CTRL_EFUSE_EN_MASK,
4752 WCD9335_CHIP_TIER_CTRL_EFUSE_ENABLE);
4753 /*
4754 * 5ms sleep required after enabling efuse control
4755 * before checking the status.
4756 */
4757 usleep_range(5000, 5500);
4758
4759 if (!(snd_soc_component_read(comp,
4760 WCD9335_CHIP_TIER_CTRL_EFUSE_STATUS) &
4761 WCD9335_CHIP_TIER_CTRL_EFUSE_EN_MASK))
4762 WARN(1, "%s: Efuse sense is not complete\n", __func__);
4763
4764 wcd9335_enable_sido_buck(comp);
4765 _wcd9335_codec_enable_mclk(comp, false);
4766
4767 return 0;
4768 }
4769
wcd9335_codec_init(struct snd_soc_component * component)4770 static void wcd9335_codec_init(struct snd_soc_component *component)
4771 {
4772 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
4773 int i;
4774
4775 /* ungate MCLK and set clk rate */
4776 regmap_update_bits(wcd->regmap, WCD9335_CODEC_RPM_CLK_GATE,
4777 WCD9335_CODEC_RPM_CLK_GATE_MCLK_GATE_MASK, 0);
4778
4779 regmap_update_bits(wcd->regmap, WCD9335_CODEC_RPM_CLK_MCLK_CFG,
4780 WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
4781 WCD9335_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ);
4782
4783 for (i = 0; i < ARRAY_SIZE(wcd9335_codec_reg_init); i++)
4784 snd_soc_component_update_bits(component,
4785 wcd9335_codec_reg_init[i].reg,
4786 wcd9335_codec_reg_init[i].mask,
4787 wcd9335_codec_reg_init[i].val);
4788
4789 wcd9335_enable_efuse_sensing(component);
4790 }
4791
wcd9335_codec_probe(struct snd_soc_component * component)4792 static int wcd9335_codec_probe(struct snd_soc_component *component)
4793 {
4794 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
4795 int ret;
4796 int i;
4797
4798 snd_soc_component_init_regmap(component, wcd->regmap);
4799 /* Class-H Init*/
4800 wcd->clsh_ctrl = wcd_clsh_ctrl_alloc(component, WCD9335);
4801 if (IS_ERR(wcd->clsh_ctrl))
4802 return PTR_ERR(wcd->clsh_ctrl);
4803
4804 /* Default HPH Mode to Class-H HiFi */
4805 wcd->hph_mode = CLS_H_HIFI;
4806 wcd->component = component;
4807
4808 wcd9335_codec_init(component);
4809
4810 for (i = 0; i < NUM_CODEC_DAIS; i++)
4811 INIT_LIST_HEAD(&wcd->dai[i].slim_ch_list);
4812
4813 ret = wcd9335_setup_irqs(wcd);
4814 if (ret)
4815 goto free_clsh_ctrl;
4816
4817 return 0;
4818
4819 free_clsh_ctrl:
4820 wcd_clsh_ctrl_free(wcd->clsh_ctrl);
4821 return ret;
4822 }
4823
wcd9335_codec_remove(struct snd_soc_component * comp)4824 static void wcd9335_codec_remove(struct snd_soc_component *comp)
4825 {
4826 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
4827
4828 wcd_clsh_ctrl_free(wcd->clsh_ctrl);
4829 wcd9335_teardown_irqs(wcd);
4830 }
4831
wcd9335_codec_set_sysclk(struct snd_soc_component * comp,int clk_id,int source,unsigned int freq,int dir)4832 static int wcd9335_codec_set_sysclk(struct snd_soc_component *comp,
4833 int clk_id, int source,
4834 unsigned int freq, int dir)
4835 {
4836 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
4837
4838 wcd->mclk_rate = freq;
4839
4840 if (wcd->mclk_rate == WCD9335_MCLK_CLK_12P288MHZ)
4841 snd_soc_component_update_bits(comp,
4842 WCD9335_CODEC_RPM_CLK_MCLK_CFG,
4843 WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
4844 WCD9335_CODEC_RPM_CLK_MCLK_CFG_12P288MHZ);
4845 else if (wcd->mclk_rate == WCD9335_MCLK_CLK_9P6MHZ)
4846 snd_soc_component_update_bits(comp,
4847 WCD9335_CODEC_RPM_CLK_MCLK_CFG,
4848 WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
4849 WCD9335_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ);
4850
4851 return clk_set_rate(wcd->mclk, freq);
4852 }
4853
4854 static const struct snd_soc_component_driver wcd9335_component_drv = {
4855 .probe = wcd9335_codec_probe,
4856 .remove = wcd9335_codec_remove,
4857 .set_sysclk = wcd9335_codec_set_sysclk,
4858 .controls = wcd9335_snd_controls,
4859 .num_controls = ARRAY_SIZE(wcd9335_snd_controls),
4860 .dapm_widgets = wcd9335_dapm_widgets,
4861 .num_dapm_widgets = ARRAY_SIZE(wcd9335_dapm_widgets),
4862 .dapm_routes = wcd9335_audio_map,
4863 .num_dapm_routes = ARRAY_SIZE(wcd9335_audio_map),
4864 .endianness = 1,
4865 };
4866
wcd9335_probe(struct wcd9335_codec * wcd)4867 static int wcd9335_probe(struct wcd9335_codec *wcd)
4868 {
4869 struct device *dev = wcd->dev;
4870
4871 memcpy(wcd->rx_chs, wcd9335_rx_chs, sizeof(wcd9335_rx_chs));
4872 memcpy(wcd->tx_chs, wcd9335_tx_chs, sizeof(wcd9335_tx_chs));
4873
4874 wcd->sido_input_src = SIDO_SOURCE_INTERNAL;
4875 wcd->sido_voltage = SIDO_VOLTAGE_NOMINAL_MV;
4876
4877 return devm_snd_soc_register_component(dev, &wcd9335_component_drv,
4878 wcd9335_slim_dais,
4879 ARRAY_SIZE(wcd9335_slim_dais));
4880 }
4881
4882 static const struct regmap_range_cfg wcd9335_ranges[] = {
4883 {
4884 .name = "WCD9335",
4885 .range_min = 0x0,
4886 .range_max = WCD9335_MAX_REGISTER,
4887 .selector_reg = WCD9335_SEL_REGISTER,
4888 .selector_mask = 0xff,
4889 .selector_shift = 0,
4890 .window_start = 0x800,
4891 .window_len = 0x100,
4892 },
4893 };
4894
wcd9335_is_volatile_register(struct device * dev,unsigned int reg)4895 static bool wcd9335_is_volatile_register(struct device *dev, unsigned int reg)
4896 {
4897 switch (reg) {
4898 case WCD9335_INTR_PIN1_STATUS0...WCD9335_INTR_PIN2_CLEAR3:
4899 case WCD9335_ANA_MBHC_RESULT_3:
4900 case WCD9335_ANA_MBHC_RESULT_2:
4901 case WCD9335_ANA_MBHC_RESULT_1:
4902 case WCD9335_ANA_MBHC_MECH:
4903 case WCD9335_ANA_MBHC_ELECT:
4904 case WCD9335_ANA_MBHC_ZDET:
4905 case WCD9335_ANA_MICB2:
4906 case WCD9335_ANA_RCO:
4907 case WCD9335_ANA_BIAS:
4908 return true;
4909 default:
4910 return false;
4911 }
4912 }
4913
4914 static const struct regmap_config wcd9335_regmap_config = {
4915 .reg_bits = 16,
4916 .val_bits = 8,
4917 .cache_type = REGCACHE_MAPLE,
4918 .max_register = WCD9335_MAX_REGISTER,
4919 .can_multi_write = true,
4920 .ranges = wcd9335_ranges,
4921 .num_ranges = ARRAY_SIZE(wcd9335_ranges),
4922 .volatile_reg = wcd9335_is_volatile_register,
4923 };
4924
4925 static const struct regmap_range_cfg wcd9335_ifc_ranges[] = {
4926 {
4927 .name = "WCD9335-IFC-DEV",
4928 .range_min = 0x0,
4929 .range_max = WCD9335_MAX_REGISTER,
4930 .selector_reg = WCD9335_SEL_REGISTER,
4931 .selector_mask = 0xfff,
4932 .selector_shift = 0,
4933 .window_start = 0x800,
4934 .window_len = 0x400,
4935 },
4936 };
4937
4938 static const struct regmap_config wcd9335_ifc_regmap_config = {
4939 .reg_bits = 16,
4940 .val_bits = 8,
4941 .can_multi_write = true,
4942 .max_register = WCD9335_MAX_REGISTER,
4943 .ranges = wcd9335_ifc_ranges,
4944 .num_ranges = ARRAY_SIZE(wcd9335_ifc_ranges),
4945 };
4946
4947 static const struct regmap_irq wcd9335_codec_irqs[] = {
4948 /* INTR_REG 0 */
4949 [WCD9335_IRQ_SLIMBUS] = {
4950 .reg_offset = 0,
4951 .mask = BIT(0),
4952 .type = {
4953 .type_reg_offset = 0,
4954 .types_supported = IRQ_TYPE_EDGE_BOTH,
4955 .type_reg_mask = BIT(0),
4956 },
4957 },
4958 };
4959
4960 static const unsigned int wcd9335_config_regs[] = {
4961 WCD9335_INTR_LEVEL0,
4962 };
4963
4964 static const struct regmap_irq_chip wcd9335_regmap_irq1_chip = {
4965 .name = "wcd9335_pin1_irq",
4966 .status_base = WCD9335_INTR_PIN1_STATUS0,
4967 .mask_base = WCD9335_INTR_PIN1_MASK0,
4968 .ack_base = WCD9335_INTR_PIN1_CLEAR0,
4969 .num_regs = 4,
4970 .irqs = wcd9335_codec_irqs,
4971 .num_irqs = ARRAY_SIZE(wcd9335_codec_irqs),
4972 .config_base = wcd9335_config_regs,
4973 .num_config_bases = ARRAY_SIZE(wcd9335_config_regs),
4974 .num_config_regs = 4,
4975 .set_type_config = regmap_irq_set_type_config_simple,
4976 };
4977
wcd9335_parse_dt(struct wcd9335_codec * wcd)4978 static int wcd9335_parse_dt(struct wcd9335_codec *wcd)
4979 {
4980 struct device *dev = wcd->dev;
4981 int ret;
4982
4983 wcd->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
4984 if (IS_ERR(wcd->reset_gpio))
4985 return dev_err_probe(dev, PTR_ERR(wcd->reset_gpio), "Reset GPIO missing from DT\n");
4986
4987 wcd->mclk = devm_clk_get(dev, "mclk");
4988 if (IS_ERR(wcd->mclk))
4989 return dev_err_probe(dev, PTR_ERR(wcd->mclk), "mclk not found\n");
4990
4991 wcd->native_clk = devm_clk_get(dev, "slimbus");
4992 if (IS_ERR(wcd->native_clk))
4993 return dev_err_probe(dev, PTR_ERR(wcd->native_clk), "slimbus clock not found\n");
4994
4995 ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(wcd9335_supplies),
4996 wcd9335_supplies);
4997 if (ret)
4998 return dev_err_probe(dev, ret, "Failed to get and enable supplies\n");
4999
5000 return 0;
5001 }
5002
wcd9335_power_on_reset(struct wcd9335_codec * wcd)5003 static int wcd9335_power_on_reset(struct wcd9335_codec *wcd)
5004 {
5005 /*
5006 * For WCD9335, it takes about 600us for the Vout_A and
5007 * Vout_D to be ready after BUCK_SIDO is powered up.
5008 * SYS_RST_N shouldn't be pulled high during this time
5009 * Toggle the reset line to make sure the reset pulse is
5010 * correctly applied
5011 */
5012 usleep_range(600, 650);
5013
5014 gpiod_set_value(wcd->reset_gpio, 1);
5015 msleep(20);
5016 gpiod_set_value(wcd->reset_gpio, 0);
5017 msleep(20);
5018
5019 return 0;
5020 }
5021
wcd9335_bring_up(struct wcd9335_codec * wcd)5022 static int wcd9335_bring_up(struct wcd9335_codec *wcd)
5023 {
5024 struct regmap *rm = wcd->regmap;
5025 int val, byte0;
5026
5027 regmap_read(rm, WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT0, &val);
5028 regmap_read(rm, WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE0, &byte0);
5029
5030 if ((val < 0) || (byte0 < 0)) {
5031 dev_err(wcd->dev, "WCD9335 CODEC version detection fail!\n");
5032 return -EINVAL;
5033 }
5034
5035 if (byte0 == 0x1) {
5036 dev_info(wcd->dev, "WCD9335 CODEC version is v2.0\n");
5037 regmap_write(rm, WCD9335_CODEC_RPM_RST_CTL, 0x01);
5038 regmap_write(rm, WCD9335_SIDO_SIDO_TEST_2, 0x00);
5039 regmap_write(rm, WCD9335_SIDO_SIDO_CCL_8, 0x6F);
5040 regmap_write(rm, WCD9335_BIAS_VBG_FINE_ADJ, 0x65);
5041 regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x5);
5042 regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x7);
5043 regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x3);
5044 regmap_write(rm, WCD9335_CODEC_RPM_RST_CTL, 0x3);
5045 } else {
5046 dev_err(wcd->dev, "WCD9335 CODEC version not supported\n");
5047 return -EINVAL;
5048 }
5049
5050 return 0;
5051 }
5052
wcd9335_irq_init(struct wcd9335_codec * wcd)5053 static int wcd9335_irq_init(struct wcd9335_codec *wcd)
5054 {
5055 int ret;
5056
5057 /*
5058 * INTR1 consists of all possible interrupt sources Ear OCP,
5059 * HPH OCP, MBHC, MAD, VBAT, and SVA
5060 * INTR2 is a subset of first interrupt sources MAD, VBAT, and SVA
5061 */
5062 wcd->intr1 = of_irq_get_byname(wcd->dev->of_node, "intr1");
5063 if (wcd->intr1 < 0)
5064 return dev_err_probe(wcd->dev, wcd->intr1,
5065 "Unable to configure IRQ\n");
5066
5067 ret = devm_regmap_add_irq_chip(wcd->dev, wcd->regmap, wcd->intr1,
5068 IRQF_TRIGGER_HIGH, 0,
5069 &wcd9335_regmap_irq1_chip, &wcd->irq_data);
5070 if (ret)
5071 return dev_err_probe(wcd->dev, ret, "Failed to register IRQ chip\n");
5072
5073 return 0;
5074 }
5075
wcd9335_slim_probe(struct slim_device * slim)5076 static int wcd9335_slim_probe(struct slim_device *slim)
5077 {
5078 struct device *dev = &slim->dev;
5079 struct wcd9335_codec *wcd;
5080 int ret;
5081
5082 wcd = devm_kzalloc(dev, sizeof(*wcd), GFP_KERNEL);
5083 if (!wcd)
5084 return -ENOMEM;
5085
5086 wcd->dev = dev;
5087 ret = wcd9335_parse_dt(wcd);
5088 if (ret)
5089 return ret;
5090
5091 ret = wcd9335_power_on_reset(wcd);
5092 if (ret)
5093 return ret;
5094
5095 dev_set_drvdata(dev, wcd);
5096
5097 return 0;
5098 }
5099
wcd9335_slim_status(struct slim_device * sdev,enum slim_device_status status)5100 static int wcd9335_slim_status(struct slim_device *sdev,
5101 enum slim_device_status status)
5102 {
5103 struct device *dev = &sdev->dev;
5104 struct device_node *ifc_dev_np;
5105 struct wcd9335_codec *wcd;
5106 int ret;
5107
5108 wcd = dev_get_drvdata(dev);
5109
5110 ifc_dev_np = of_parse_phandle(dev->of_node, "slim-ifc-dev", 0);
5111 if (!ifc_dev_np) {
5112 dev_err(dev, "No Interface device found\n");
5113 return -EINVAL;
5114 }
5115
5116 wcd->slim = sdev;
5117 wcd->slim_ifc_dev = of_slim_get_device(sdev->ctrl, ifc_dev_np);
5118 of_node_put(ifc_dev_np);
5119 if (!wcd->slim_ifc_dev) {
5120 dev_err(dev, "Unable to get SLIM Interface device\n");
5121 return -EINVAL;
5122 }
5123
5124 slim_get_logical_addr(wcd->slim_ifc_dev);
5125
5126 wcd->regmap = regmap_init_slimbus(sdev, &wcd9335_regmap_config);
5127 if (IS_ERR(wcd->regmap))
5128 return dev_err_probe(dev, PTR_ERR(wcd->regmap),
5129 "Failed to allocate slim register map\n");
5130
5131 wcd->if_regmap = regmap_init_slimbus(wcd->slim_ifc_dev,
5132 &wcd9335_ifc_regmap_config);
5133 if (IS_ERR(wcd->if_regmap))
5134 return dev_err_probe(dev, PTR_ERR(wcd->if_regmap),
5135 "Failed to allocate ifc register map\n");
5136
5137 ret = wcd9335_bring_up(wcd);
5138 if (ret) {
5139 dev_err(dev, "Failed to bringup WCD9335\n");
5140 return ret;
5141 }
5142
5143 ret = wcd9335_irq_init(wcd);
5144 if (ret)
5145 return ret;
5146
5147 wcd9335_probe(wcd);
5148
5149 return 0;
5150 }
5151
5152 static const struct slim_device_id wcd9335_slim_id[] = {
5153 {SLIM_MANF_ID_QCOM, SLIM_PROD_CODE_WCD9335, 0x1, 0x0},
5154 {}
5155 };
5156 MODULE_DEVICE_TABLE(slim, wcd9335_slim_id);
5157
5158 static struct slim_driver wcd9335_slim_driver = {
5159 .driver = {
5160 .name = "wcd9335-slim",
5161 },
5162 .probe = wcd9335_slim_probe,
5163 .device_status = wcd9335_slim_status,
5164 .id_table = wcd9335_slim_id,
5165 };
5166
5167 module_slim_driver(wcd9335_slim_driver);
5168 MODULE_DESCRIPTION("WCD9335 slim driver");
5169 MODULE_LICENSE("GPL v2");
5170