1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later
2 /*
3 * Copyright 2008 - 2016 Freescale Semiconductor Inc.
4 * Copyright 2020 NXP
5 */
6
7 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
8
9 #include <linux/init.h>
10 #include <linux/mod_devicetable.h>
11 #include <linux/module.h>
12 #include <linux/of_mdio.h>
13 #include <linux/of_net.h>
14 #include <linux/io.h>
15 #include <linux/if_arp.h>
16 #include <linux/if_vlan.h>
17 #include <linux/icmp.h>
18 #include <linux/ip.h>
19 #include <linux/ipv6.h>
20 #include <linux/platform_device.h>
21 #include <linux/udp.h>
22 #include <linux/tcp.h>
23 #include <linux/net.h>
24 #include <linux/skbuff.h>
25 #include <linux/etherdevice.h>
26 #include <linux/if_ether.h>
27 #include <linux/highmem.h>
28 #include <linux/percpu.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/sort.h>
31 #include <linux/phy_fixed.h>
32 #include <linux/bpf.h>
33 #include <linux/bpf_trace.h>
34 #include <soc/fsl/bman.h>
35 #include <soc/fsl/qman.h>
36 #include "fman.h"
37 #include "fman_port.h"
38 #include "mac.h"
39 #include "dpaa_eth.h"
40
41 /* CREATE_TRACE_POINTS only needs to be defined once. Other dpaa files
42 * using trace events only need to #include <trace/events/sched.h>
43 */
44 #define CREATE_TRACE_POINTS
45 #include "dpaa_eth_trace.h"
46
47 static int debug = -1;
48 module_param(debug, int, 0444);
49 MODULE_PARM_DESC(debug, "Module/Driver verbosity level (0=none,...,16=all)");
50
51 static u16 tx_timeout = 1000;
52 module_param(tx_timeout, ushort, 0444);
53 MODULE_PARM_DESC(tx_timeout, "The Tx timeout in ms");
54
55 #define FM_FD_STAT_RX_ERRORS \
56 (FM_FD_ERR_DMA | FM_FD_ERR_PHYSICAL | \
57 FM_FD_ERR_SIZE | FM_FD_ERR_CLS_DISCARD | \
58 FM_FD_ERR_EXTRACTION | FM_FD_ERR_NO_SCHEME | \
59 FM_FD_ERR_PRS_TIMEOUT | FM_FD_ERR_PRS_ILL_INSTRUCT | \
60 FM_FD_ERR_PRS_HDR_ERR)
61
62 #define FM_FD_STAT_TX_ERRORS \
63 (FM_FD_ERR_UNSUPPORTED_FORMAT | \
64 FM_FD_ERR_LENGTH | FM_FD_ERR_DMA)
65
66 #define DPAA_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
67 NETIF_MSG_LINK | NETIF_MSG_IFUP | \
68 NETIF_MSG_IFDOWN | NETIF_MSG_HW)
69
70 #define DPAA_INGRESS_CS_THRESHOLD 0x10000000
71 /* Ingress congestion threshold on FMan ports
72 * The size in bytes of the ingress tail-drop threshold on FMan ports.
73 * Traffic piling up above this value will be rejected by QMan and discarded
74 * by FMan.
75 */
76
77 /* Size in bytes of the FQ taildrop threshold */
78 #define DPAA_FQ_TD 0x200000
79
80 #define DPAA_CS_THRESHOLD_1G 0x06000000
81 /* Egress congestion threshold on 1G ports, range 0x1000 .. 0x10000000
82 * The size in bytes of the egress Congestion State notification threshold on
83 * 1G ports. The 1G dTSECs can quite easily be flooded by cores doing Tx in a
84 * tight loop (e.g. by sending UDP datagrams at "while(1) speed"),
85 * and the larger the frame size, the more acute the problem.
86 * So we have to find a balance between these factors:
87 * - avoiding the device staying congested for a prolonged time (risking
88 * the netdev watchdog to fire - see also the tx_timeout module param);
89 * - affecting performance of protocols such as TCP, which otherwise
90 * behave well under the congestion notification mechanism;
91 * - preventing the Tx cores from tightly-looping (as if the congestion
92 * threshold was too low to be effective);
93 * - running out of memory if the CS threshold is set too high.
94 */
95
96 #define DPAA_CS_THRESHOLD_10G 0x10000000
97 /* The size in bytes of the egress Congestion State notification threshold on
98 * 10G ports, range 0x1000 .. 0x10000000
99 */
100
101 /* Largest value that the FQD's OAL field can hold */
102 #define FSL_QMAN_MAX_OAL 127
103
104 /* Default alignment for start of data in an Rx FD */
105 #ifdef CONFIG_DPAA_ERRATUM_A050385
106 /* aligning data start to 64 avoids DMA transaction splits, unless the buffer
107 * is crossing a 4k page boundary
108 */
109 #define DPAA_FD_DATA_ALIGNMENT (fman_has_errata_a050385() ? 64 : 16)
110 /* aligning to 256 avoids DMA transaction splits caused by 4k page boundary
111 * crossings; also, all SG fragments except the last must have a size multiple
112 * of 256 to avoid DMA transaction splits
113 */
114 #define DPAA_A050385_ALIGN 256
115 #define DPAA_FD_RX_DATA_ALIGNMENT (fman_has_errata_a050385() ? \
116 DPAA_A050385_ALIGN : 16)
117 #else
118 #define DPAA_FD_DATA_ALIGNMENT 16
119 #define DPAA_FD_RX_DATA_ALIGNMENT DPAA_FD_DATA_ALIGNMENT
120 #endif
121
122 /* The DPAA requires 256 bytes reserved and mapped for the SGT */
123 #define DPAA_SGT_SIZE 256
124
125 /* Values for the L3R field of the FM Parse Results
126 */
127 /* L3 Type field: First IP Present IPv4 */
128 #define FM_L3_PARSE_RESULT_IPV4 0x8000
129 /* L3 Type field: First IP Present IPv6 */
130 #define FM_L3_PARSE_RESULT_IPV6 0x4000
131 /* Values for the L4R field of the FM Parse Results */
132 /* L4 Type field: UDP */
133 #define FM_L4_PARSE_RESULT_UDP 0x40
134 /* L4 Type field: TCP */
135 #define FM_L4_PARSE_RESULT_TCP 0x20
136
137 /* FD status field indicating whether the FM Parser has attempted to validate
138 * the L4 csum of the frame.
139 * Note that having this bit set doesn't necessarily imply that the checksum
140 * is valid. One would have to check the parse results to find that out.
141 */
142 #define FM_FD_STAT_L4CV 0x00000004
143
144 #define DPAA_SGT_MAX_ENTRIES 16 /* maximum number of entries in SG Table */
145 #define DPAA_BUFF_RELEASE_MAX 8 /* maximum number of buffers released at once */
146
147 #define FSL_DPAA_BPID_INV 0xff
148 #define FSL_DPAA_ETH_MAX_BUF_COUNT 128
149 #define FSL_DPAA_ETH_REFILL_THRESHOLD 80
150
151 #define DPAA_TX_PRIV_DATA_SIZE 16
152 #define DPAA_PARSE_RESULTS_SIZE sizeof(struct fman_prs_result)
153 #define DPAA_TIME_STAMP_SIZE 8
154 #define DPAA_HASH_RESULTS_SIZE 8
155 #define DPAA_HWA_SIZE (DPAA_PARSE_RESULTS_SIZE + DPAA_TIME_STAMP_SIZE \
156 + DPAA_HASH_RESULTS_SIZE)
157 #define DPAA_RX_PRIV_DATA_DEFAULT_SIZE (DPAA_TX_PRIV_DATA_SIZE + \
158 XDP_PACKET_HEADROOM - DPAA_HWA_SIZE)
159 #ifdef CONFIG_DPAA_ERRATUM_A050385
160 #define DPAA_RX_PRIV_DATA_A050385_SIZE (DPAA_A050385_ALIGN - DPAA_HWA_SIZE)
161 #define DPAA_RX_PRIV_DATA_SIZE (fman_has_errata_a050385() ? \
162 DPAA_RX_PRIV_DATA_A050385_SIZE : \
163 DPAA_RX_PRIV_DATA_DEFAULT_SIZE)
164 #else
165 #define DPAA_RX_PRIV_DATA_SIZE DPAA_RX_PRIV_DATA_DEFAULT_SIZE
166 #endif
167
168 #define DPAA_ETH_PCD_RXQ_NUM 128
169
170 #define DPAA_ENQUEUE_RETRIES 100000
171
172 enum port_type {RX, TX};
173
174 struct fm_port_fqs {
175 struct dpaa_fq *tx_defq;
176 struct dpaa_fq *tx_errq;
177 struct dpaa_fq *rx_defq;
178 struct dpaa_fq *rx_errq;
179 struct dpaa_fq *rx_pcdq;
180 };
181
182 /* All the dpa bps in use at any moment */
183 static struct dpaa_bp *dpaa_bp_array[BM_MAX_NUM_OF_POOLS];
184
185 #define DPAA_BP_RAW_SIZE 4096
186
187 #ifdef CONFIG_DPAA_ERRATUM_A050385
188 #define dpaa_bp_size(raw_size) (SKB_WITH_OVERHEAD(raw_size) & \
189 ~(DPAA_A050385_ALIGN - 1))
190 #else
191 #define dpaa_bp_size(raw_size) SKB_WITH_OVERHEAD(raw_size)
192 #endif
193
194 static int dpaa_max_frm;
195
196 static int dpaa_rx_extra_headroom;
197
198 #define dpaa_get_max_mtu() \
199 (dpaa_max_frm - (VLAN_ETH_HLEN + ETH_FCS_LEN))
200
201 static void dpaa_eth_cgr_set_speed(struct mac_device *mac_dev, int speed);
202
dpaa_netdev_init(struct net_device * net_dev,const struct net_device_ops * dpaa_ops,u16 tx_timeout)203 static int dpaa_netdev_init(struct net_device *net_dev,
204 const struct net_device_ops *dpaa_ops,
205 u16 tx_timeout)
206 {
207 struct dpaa_priv *priv = netdev_priv(net_dev);
208 struct device *dev = net_dev->dev.parent;
209 struct mac_device *mac_dev = priv->mac_dev;
210 struct dpaa_percpu_priv *percpu_priv;
211 const u8 *mac_addr;
212 int i, err;
213
214 /* Although we access another CPU's private data here
215 * we do it at initialization so it is safe
216 */
217 for_each_possible_cpu(i) {
218 percpu_priv = per_cpu_ptr(priv->percpu_priv, i);
219 percpu_priv->net_dev = net_dev;
220 }
221
222 net_dev->netdev_ops = dpaa_ops;
223 mac_addr = mac_dev->addr;
224
225 net_dev->mem_start = (unsigned long)priv->mac_dev->res->start;
226 net_dev->mem_end = (unsigned long)priv->mac_dev->res->end;
227
228 net_dev->min_mtu = ETH_MIN_MTU;
229 net_dev->max_mtu = dpaa_get_max_mtu();
230
231 net_dev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
232 NETIF_F_RXHASH);
233
234 net_dev->hw_features |= NETIF_F_SG | NETIF_F_HIGHDMA;
235 /* The kernels enables GSO automatically, if we declare NETIF_F_SG.
236 * For conformity, we'll still declare GSO explicitly.
237 */
238 net_dev->features |= NETIF_F_GSO;
239 net_dev->features |= NETIF_F_RXCSUM;
240
241 net_dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
242 net_dev->lltx = true;
243 /* we do not want shared skbs on TX */
244 net_dev->priv_flags &= ~IFF_TX_SKB_SHARING;
245
246 net_dev->features |= net_dev->hw_features;
247 net_dev->vlan_features = net_dev->features;
248
249 net_dev->xdp_features = NETDEV_XDP_ACT_BASIC |
250 NETDEV_XDP_ACT_REDIRECT |
251 NETDEV_XDP_ACT_NDO_XMIT;
252
253 if (is_valid_ether_addr(mac_addr)) {
254 memcpy(net_dev->perm_addr, mac_addr, net_dev->addr_len);
255 eth_hw_addr_set(net_dev, mac_addr);
256 } else {
257 eth_hw_addr_random(net_dev);
258 err = mac_dev->change_addr(mac_dev->fman_mac,
259 (const enet_addr_t *)net_dev->dev_addr);
260 if (err) {
261 dev_err(dev, "Failed to set random MAC address\n");
262 return -EINVAL;
263 }
264 dev_info(dev, "Using random MAC address: %pM\n",
265 net_dev->dev_addr);
266 }
267
268 net_dev->ethtool_ops = &dpaa_ethtool_ops;
269
270 net_dev->needed_headroom = priv->tx_headroom;
271 net_dev->watchdog_timeo = msecs_to_jiffies(tx_timeout);
272
273 /* The rest of the config is filled in by the mac device already */
274 mac_dev->phylink_config.dev = &net_dev->dev;
275 mac_dev->phylink_config.type = PHYLINK_NETDEV;
276 mac_dev->update_speed = dpaa_eth_cgr_set_speed;
277 mac_dev->phylink = phylink_create(&mac_dev->phylink_config,
278 dev_fwnode(mac_dev->dev),
279 mac_dev->phy_if,
280 mac_dev->phylink_ops);
281 if (IS_ERR(mac_dev->phylink)) {
282 err = PTR_ERR(mac_dev->phylink);
283 dev_err_probe(dev, err, "Could not create phylink\n");
284 return err;
285 }
286
287 /* start without the RUNNING flag, phylib controls it later */
288 netif_carrier_off(net_dev);
289
290 err = register_netdev(net_dev);
291 if (err < 0) {
292 dev_err(dev, "register_netdev() = %d\n", err);
293 phylink_destroy(mac_dev->phylink);
294 return err;
295 }
296
297 return 0;
298 }
299
dpaa_stop(struct net_device * net_dev)300 static int dpaa_stop(struct net_device *net_dev)
301 {
302 struct mac_device *mac_dev;
303 struct dpaa_priv *priv;
304 int i, error;
305 int err = 0;
306
307 priv = netdev_priv(net_dev);
308 mac_dev = priv->mac_dev;
309
310 netif_tx_stop_all_queues(net_dev);
311 /* Allow the Fman (Tx) port to process in-flight frames before we
312 * try switching it off.
313 */
314 msleep(200);
315
316 phylink_stop(mac_dev->phylink);
317 mac_dev->disable(mac_dev->fman_mac);
318
319 for (i = 0; i < ARRAY_SIZE(mac_dev->port); i++) {
320 error = fman_port_disable(mac_dev->port[i]);
321 if (error)
322 err = error;
323 }
324
325 phylink_disconnect_phy(mac_dev->phylink);
326 net_dev->phydev = NULL;
327
328 msleep(200);
329
330 return err;
331 }
332
dpaa_tx_timeout(struct net_device * net_dev,unsigned int txqueue)333 static void dpaa_tx_timeout(struct net_device *net_dev, unsigned int txqueue)
334 {
335 struct dpaa_percpu_priv *percpu_priv;
336 const struct dpaa_priv *priv;
337
338 priv = netdev_priv(net_dev);
339 percpu_priv = this_cpu_ptr(priv->percpu_priv);
340
341 netif_crit(priv, timer, net_dev, "Transmit timeout latency: %u ms\n",
342 jiffies_to_msecs(jiffies - dev_trans_start(net_dev)));
343
344 percpu_priv->stats.tx_errors++;
345 }
346
347 /* Calculates the statistics for the given device by adding the statistics
348 * collected by each CPU.
349 */
dpaa_get_stats64(struct net_device * net_dev,struct rtnl_link_stats64 * s)350 static void dpaa_get_stats64(struct net_device *net_dev,
351 struct rtnl_link_stats64 *s)
352 {
353 int numstats = sizeof(struct rtnl_link_stats64) / sizeof(u64);
354 struct dpaa_priv *priv = netdev_priv(net_dev);
355 struct dpaa_percpu_priv *percpu_priv;
356 u64 *netstats = (u64 *)s;
357 u64 *cpustats;
358 int i, j;
359
360 for_each_possible_cpu(i) {
361 percpu_priv = per_cpu_ptr(priv->percpu_priv, i);
362
363 cpustats = (u64 *)&percpu_priv->stats;
364
365 /* add stats from all CPUs */
366 for (j = 0; j < numstats; j++)
367 netstats[j] += cpustats[j];
368 }
369 }
370
dpaa_setup_tc(struct net_device * net_dev,enum tc_setup_type type,void * type_data)371 static int dpaa_setup_tc(struct net_device *net_dev, enum tc_setup_type type,
372 void *type_data)
373 {
374 struct dpaa_priv *priv = netdev_priv(net_dev);
375 int num_txqs_per_tc = dpaa_num_txqs_per_tc();
376 struct tc_mqprio_qopt *mqprio = type_data;
377 u8 num_tc;
378 int i;
379
380 if (type != TC_SETUP_QDISC_MQPRIO)
381 return -EOPNOTSUPP;
382
383 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
384 num_tc = mqprio->num_tc;
385
386 if (num_tc == priv->num_tc)
387 return 0;
388
389 if (!num_tc) {
390 netdev_reset_tc(net_dev);
391 goto out;
392 }
393
394 if (num_tc > DPAA_TC_NUM) {
395 netdev_err(net_dev, "Too many traffic classes: max %d supported.\n",
396 DPAA_TC_NUM);
397 return -EINVAL;
398 }
399
400 netdev_set_num_tc(net_dev, num_tc);
401
402 for (i = 0; i < num_tc; i++)
403 netdev_set_tc_queue(net_dev, i, num_txqs_per_tc,
404 i * num_txqs_per_tc);
405
406 out:
407 priv->num_tc = num_tc ? : 1;
408 netif_set_real_num_tx_queues(net_dev, priv->num_tc * num_txqs_per_tc);
409 return 0;
410 }
411
dpaa_mac_dev_get(struct platform_device * pdev)412 static struct mac_device *dpaa_mac_dev_get(struct platform_device *pdev)
413 {
414 struct dpaa_eth_data *eth_data;
415 struct device *dpaa_dev;
416 struct mac_device *mac_dev;
417
418 dpaa_dev = &pdev->dev;
419 eth_data = dpaa_dev->platform_data;
420 if (!eth_data) {
421 dev_err(dpaa_dev, "eth_data missing\n");
422 return ERR_PTR(-ENODEV);
423 }
424 mac_dev = eth_data->mac_dev;
425 if (!mac_dev) {
426 dev_err(dpaa_dev, "mac_dev missing\n");
427 return ERR_PTR(-EINVAL);
428 }
429
430 return mac_dev;
431 }
432
dpaa_set_mac_address(struct net_device * net_dev,void * addr)433 static int dpaa_set_mac_address(struct net_device *net_dev, void *addr)
434 {
435 const struct dpaa_priv *priv;
436 struct mac_device *mac_dev;
437 struct sockaddr old_addr;
438 int err;
439
440 priv = netdev_priv(net_dev);
441
442 memcpy(old_addr.sa_data, net_dev->dev_addr, ETH_ALEN);
443
444 err = eth_mac_addr(net_dev, addr);
445 if (err < 0) {
446 netif_err(priv, drv, net_dev, "eth_mac_addr() = %d\n", err);
447 return err;
448 }
449
450 mac_dev = priv->mac_dev;
451
452 err = mac_dev->change_addr(mac_dev->fman_mac,
453 (const enet_addr_t *)net_dev->dev_addr);
454 if (err < 0) {
455 netif_err(priv, drv, net_dev, "mac_dev->change_addr() = %d\n",
456 err);
457 /* reverting to previous address */
458 eth_mac_addr(net_dev, &old_addr);
459
460 return err;
461 }
462
463 return 0;
464 }
465
dpaa_set_rx_mode(struct net_device * net_dev)466 static void dpaa_set_rx_mode(struct net_device *net_dev)
467 {
468 const struct dpaa_priv *priv;
469 int err;
470
471 priv = netdev_priv(net_dev);
472
473 if (!!(net_dev->flags & IFF_PROMISC) != priv->mac_dev->promisc) {
474 priv->mac_dev->promisc = !priv->mac_dev->promisc;
475 err = priv->mac_dev->set_promisc(priv->mac_dev->fman_mac,
476 priv->mac_dev->promisc);
477 if (err < 0)
478 netif_err(priv, drv, net_dev,
479 "mac_dev->set_promisc() = %d\n",
480 err);
481 }
482
483 if (!!(net_dev->flags & IFF_ALLMULTI) != priv->mac_dev->allmulti) {
484 priv->mac_dev->allmulti = !priv->mac_dev->allmulti;
485 err = priv->mac_dev->set_allmulti(priv->mac_dev->fman_mac,
486 priv->mac_dev->allmulti);
487 if (err < 0)
488 netif_err(priv, drv, net_dev,
489 "mac_dev->set_allmulti() = %d\n",
490 err);
491 }
492
493 err = priv->mac_dev->set_multi(net_dev, priv->mac_dev);
494 if (err < 0)
495 netif_err(priv, drv, net_dev, "mac_dev->set_multi() = %d\n",
496 err);
497 }
498
dpaa_bpid2pool(int bpid)499 static struct dpaa_bp *dpaa_bpid2pool(int bpid)
500 {
501 if (WARN_ON(bpid < 0 || bpid >= BM_MAX_NUM_OF_POOLS))
502 return NULL;
503
504 return dpaa_bp_array[bpid];
505 }
506
507 /* checks if this bpool is already allocated */
dpaa_bpid2pool_use(int bpid)508 static bool dpaa_bpid2pool_use(int bpid)
509 {
510 if (dpaa_bpid2pool(bpid)) {
511 refcount_inc(&dpaa_bp_array[bpid]->refs);
512 return true;
513 }
514
515 return false;
516 }
517
518 /* called only once per bpid by dpaa_bp_alloc_pool() */
dpaa_bpid2pool_map(int bpid,struct dpaa_bp * dpaa_bp)519 static void dpaa_bpid2pool_map(int bpid, struct dpaa_bp *dpaa_bp)
520 {
521 dpaa_bp_array[bpid] = dpaa_bp;
522 refcount_set(&dpaa_bp->refs, 1);
523 }
524
dpaa_bp_alloc_pool(struct dpaa_bp * dpaa_bp)525 static int dpaa_bp_alloc_pool(struct dpaa_bp *dpaa_bp)
526 {
527 int err;
528
529 if (dpaa_bp->size == 0 || dpaa_bp->config_count == 0) {
530 pr_err("%s: Buffer pool is not properly initialized! Missing size or initial number of buffers\n",
531 __func__);
532 return -EINVAL;
533 }
534
535 /* If the pool is already specified, we only create one per bpid */
536 if (dpaa_bp->bpid != FSL_DPAA_BPID_INV &&
537 dpaa_bpid2pool_use(dpaa_bp->bpid))
538 return 0;
539
540 if (dpaa_bp->bpid == FSL_DPAA_BPID_INV) {
541 dpaa_bp->pool = bman_new_pool();
542 if (!dpaa_bp->pool) {
543 pr_err("%s: bman_new_pool() failed\n",
544 __func__);
545 return -ENODEV;
546 }
547
548 dpaa_bp->bpid = (u8)bman_get_bpid(dpaa_bp->pool);
549 }
550
551 if (dpaa_bp->seed_cb) {
552 err = dpaa_bp->seed_cb(dpaa_bp);
553 if (err)
554 goto pool_seed_failed;
555 }
556
557 dpaa_bpid2pool_map(dpaa_bp->bpid, dpaa_bp);
558
559 return 0;
560
561 pool_seed_failed:
562 pr_err("%s: pool seeding failed\n", __func__);
563 bman_free_pool(dpaa_bp->pool);
564
565 return err;
566 }
567
568 /* remove and free all the buffers from the given buffer pool */
dpaa_bp_drain(struct dpaa_bp * bp)569 static void dpaa_bp_drain(struct dpaa_bp *bp)
570 {
571 u8 num = 8;
572 int ret;
573
574 do {
575 struct bm_buffer bmb[8];
576 int i;
577
578 ret = bman_acquire(bp->pool, bmb, num);
579 if (ret < 0) {
580 if (num == 8) {
581 /* we have less than 8 buffers left;
582 * drain them one by one
583 */
584 num = 1;
585 ret = 1;
586 continue;
587 } else {
588 /* Pool is fully drained */
589 break;
590 }
591 }
592
593 if (bp->free_buf_cb)
594 for (i = 0; i < num; i++)
595 bp->free_buf_cb(bp, &bmb[i]);
596 } while (ret > 0);
597 }
598
dpaa_bp_free(struct dpaa_bp * dpaa_bp)599 static void dpaa_bp_free(struct dpaa_bp *dpaa_bp)
600 {
601 struct dpaa_bp *bp = dpaa_bpid2pool(dpaa_bp->bpid);
602
603 /* the mapping between bpid and dpaa_bp is done very late in the
604 * allocation procedure; if something failed before the mapping, the bp
605 * was not configured, therefore we don't need the below instructions
606 */
607 if (!bp)
608 return;
609
610 if (!refcount_dec_and_test(&bp->refs))
611 return;
612
613 if (bp->free_buf_cb)
614 dpaa_bp_drain(bp);
615
616 dpaa_bp_array[bp->bpid] = NULL;
617 bman_free_pool(bp->pool);
618 }
619
dpaa_bps_free(struct dpaa_priv * priv)620 static void dpaa_bps_free(struct dpaa_priv *priv)
621 {
622 dpaa_bp_free(priv->dpaa_bp);
623 }
624
625 /* Use multiple WQs for FQ assignment:
626 * - Tx Confirmation queues go to WQ1.
627 * - Rx Error and Tx Error queues go to WQ5 (giving them a better chance
628 * to be scheduled, in case there are many more FQs in WQ6).
629 * - Rx Default goes to WQ6.
630 * - Tx queues go to different WQs depending on their priority. Equal
631 * chunks of NR_CPUS queues go to WQ6 (lowest priority), WQ2, WQ1 and
632 * WQ0 (highest priority).
633 * This ensures that Tx-confirmed buffers are timely released. In particular,
634 * it avoids congestion on the Tx Confirm FQs, which can pile up PFDRs if they
635 * are greatly outnumbered by other FQs in the system, while
636 * dequeue scheduling is round-robin.
637 */
dpaa_assign_wq(struct dpaa_fq * fq,int idx)638 static inline void dpaa_assign_wq(struct dpaa_fq *fq, int idx)
639 {
640 switch (fq->fq_type) {
641 case FQ_TYPE_TX_CONFIRM:
642 case FQ_TYPE_TX_CONF_MQ:
643 fq->wq = 1;
644 break;
645 case FQ_TYPE_RX_ERROR:
646 case FQ_TYPE_TX_ERROR:
647 fq->wq = 5;
648 break;
649 case FQ_TYPE_RX_DEFAULT:
650 case FQ_TYPE_RX_PCD:
651 fq->wq = 6;
652 break;
653 case FQ_TYPE_TX:
654 switch (idx / dpaa_num_txqs_per_tc()) {
655 case 0:
656 /* Low priority (best effort) */
657 fq->wq = 6;
658 break;
659 case 1:
660 /* Medium priority */
661 fq->wq = 2;
662 break;
663 case 2:
664 /* High priority */
665 fq->wq = 1;
666 break;
667 case 3:
668 /* Very high priority */
669 fq->wq = 0;
670 break;
671 default:
672 WARN(1, "Too many TX FQs: more than %zu!\n",
673 dpaa_max_num_txqs());
674 }
675 break;
676 default:
677 WARN(1, "Invalid FQ type %d for FQID %d!\n",
678 fq->fq_type, fq->fqid);
679 }
680 }
681
dpaa_fq_alloc(struct device * dev,u32 start,u32 count,struct list_head * list,enum dpaa_fq_type fq_type)682 static struct dpaa_fq *dpaa_fq_alloc(struct device *dev,
683 u32 start, u32 count,
684 struct list_head *list,
685 enum dpaa_fq_type fq_type)
686 {
687 struct dpaa_fq *dpaa_fq;
688 int i;
689
690 dpaa_fq = devm_kcalloc(dev, count, sizeof(*dpaa_fq),
691 GFP_KERNEL);
692 if (!dpaa_fq)
693 return NULL;
694
695 for (i = 0; i < count; i++) {
696 dpaa_fq[i].fq_type = fq_type;
697 dpaa_fq[i].fqid = start ? start + i : 0;
698 list_add_tail(&dpaa_fq[i].list, list);
699 }
700
701 for (i = 0; i < count; i++)
702 dpaa_assign_wq(dpaa_fq + i, i);
703
704 return dpaa_fq;
705 }
706
dpaa_alloc_all_fqs(struct device * dev,struct list_head * list,struct fm_port_fqs * port_fqs)707 static int dpaa_alloc_all_fqs(struct device *dev, struct list_head *list,
708 struct fm_port_fqs *port_fqs)
709 {
710 struct dpaa_fq *dpaa_fq;
711 u32 fq_base, fq_base_aligned, i;
712
713 dpaa_fq = dpaa_fq_alloc(dev, 0, 1, list, FQ_TYPE_RX_ERROR);
714 if (!dpaa_fq)
715 goto fq_alloc_failed;
716
717 port_fqs->rx_errq = &dpaa_fq[0];
718
719 dpaa_fq = dpaa_fq_alloc(dev, 0, 1, list, FQ_TYPE_RX_DEFAULT);
720 if (!dpaa_fq)
721 goto fq_alloc_failed;
722
723 port_fqs->rx_defq = &dpaa_fq[0];
724
725 /* the PCD FQIDs range needs to be aligned for correct operation */
726 if (qman_alloc_fqid_range(&fq_base, 2 * DPAA_ETH_PCD_RXQ_NUM))
727 goto fq_alloc_failed;
728
729 fq_base_aligned = ALIGN(fq_base, DPAA_ETH_PCD_RXQ_NUM);
730
731 for (i = fq_base; i < fq_base_aligned; i++)
732 qman_release_fqid(i);
733
734 for (i = fq_base_aligned + DPAA_ETH_PCD_RXQ_NUM;
735 i < (fq_base + 2 * DPAA_ETH_PCD_RXQ_NUM); i++)
736 qman_release_fqid(i);
737
738 dpaa_fq = dpaa_fq_alloc(dev, fq_base_aligned, DPAA_ETH_PCD_RXQ_NUM,
739 list, FQ_TYPE_RX_PCD);
740 if (!dpaa_fq)
741 goto fq_alloc_failed;
742
743 port_fqs->rx_pcdq = &dpaa_fq[0];
744
745 if (!dpaa_fq_alloc(dev, 0, dpaa_max_num_txqs(), list,
746 FQ_TYPE_TX_CONF_MQ))
747 goto fq_alloc_failed;
748
749 dpaa_fq = dpaa_fq_alloc(dev, 0, 1, list, FQ_TYPE_TX_ERROR);
750 if (!dpaa_fq)
751 goto fq_alloc_failed;
752
753 port_fqs->tx_errq = &dpaa_fq[0];
754
755 dpaa_fq = dpaa_fq_alloc(dev, 0, 1, list, FQ_TYPE_TX_CONFIRM);
756 if (!dpaa_fq)
757 goto fq_alloc_failed;
758
759 port_fqs->tx_defq = &dpaa_fq[0];
760
761 if (!dpaa_fq_alloc(dev, 0, dpaa_max_num_txqs(), list, FQ_TYPE_TX))
762 goto fq_alloc_failed;
763
764 return 0;
765
766 fq_alloc_failed:
767 dev_err(dev, "dpaa_fq_alloc() failed\n");
768 return -ENOMEM;
769 }
770
771 static u32 rx_pool_channel;
772 static DEFINE_SPINLOCK(rx_pool_channel_init);
773
dpaa_get_channel(void)774 static int dpaa_get_channel(void)
775 {
776 spin_lock(&rx_pool_channel_init);
777 if (!rx_pool_channel) {
778 u32 pool;
779 int ret;
780
781 ret = qman_alloc_pool(&pool);
782
783 if (!ret)
784 rx_pool_channel = pool;
785 }
786 spin_unlock(&rx_pool_channel_init);
787 if (!rx_pool_channel)
788 return -ENOMEM;
789 return rx_pool_channel;
790 }
791
dpaa_release_channel(void)792 static void dpaa_release_channel(void)
793 {
794 qman_release_pool(rx_pool_channel);
795 }
796
dpaa_eth_add_channel(u16 channel,struct device * dev)797 static void dpaa_eth_add_channel(u16 channel, struct device *dev)
798 {
799 u32 pool = QM_SDQCR_CHANNELS_POOL_CONV(channel);
800 const cpumask_t *cpus = qman_affine_cpus();
801 struct qman_portal *portal;
802 int cpu;
803
804 for_each_cpu_and(cpu, cpus, cpu_online_mask) {
805 portal = qman_get_affine_portal(cpu);
806 qman_p_static_dequeue_add(portal, pool);
807 qman_start_using_portal(portal, dev);
808 }
809 }
810
811 /* Congestion group state change notification callback.
812 * Stops the device's egress queues while they are congested and
813 * wakes them upon exiting congested state.
814 * Also updates some CGR-related stats.
815 */
dpaa_eth_cgscn(struct qman_portal * qm,struct qman_cgr * cgr,int congested)816 static void dpaa_eth_cgscn(struct qman_portal *qm, struct qman_cgr *cgr,
817 int congested)
818 {
819 struct dpaa_priv *priv = (struct dpaa_priv *)container_of(cgr,
820 struct dpaa_priv, cgr_data.cgr);
821
822 if (congested) {
823 priv->cgr_data.congestion_start_jiffies = jiffies;
824 netif_tx_stop_all_queues(priv->net_dev);
825 priv->cgr_data.cgr_congested_count++;
826 } else {
827 priv->cgr_data.congested_jiffies +=
828 (jiffies - priv->cgr_data.congestion_start_jiffies);
829 netif_tx_wake_all_queues(priv->net_dev);
830 }
831 }
832
dpaa_eth_cgr_init(struct dpaa_priv * priv)833 static int dpaa_eth_cgr_init(struct dpaa_priv *priv)
834 {
835 struct qm_mcc_initcgr initcgr;
836 u32 cs_th;
837 int err;
838
839 err = qman_alloc_cgrid(&priv->cgr_data.cgr.cgrid);
840 if (err < 0) {
841 if (netif_msg_drv(priv))
842 pr_err("%s: Error %d allocating CGR ID\n",
843 __func__, err);
844 goto out_error;
845 }
846 priv->cgr_data.cgr.cb = dpaa_eth_cgscn;
847
848 /* Enable Congestion State Change Notifications and CS taildrop */
849 memset(&initcgr, 0, sizeof(initcgr));
850 initcgr.we_mask = cpu_to_be16(QM_CGR_WE_CSCN_EN | QM_CGR_WE_CS_THRES);
851 initcgr.cgr.cscn_en = QM_CGR_EN;
852
853 /* Set different thresholds based on the configured MAC speed.
854 * This may turn suboptimal if the MAC is reconfigured at another
855 * speed, so MACs must call dpaa_eth_cgr_set_speed in their link_up
856 * callback.
857 */
858 if (priv->mac_dev->phylink_config.mac_capabilities & MAC_10000FD)
859 cs_th = DPAA_CS_THRESHOLD_10G;
860 else
861 cs_th = DPAA_CS_THRESHOLD_1G;
862 qm_cgr_cs_thres_set64(&initcgr.cgr.cs_thres, cs_th, 1);
863
864 initcgr.we_mask |= cpu_to_be16(QM_CGR_WE_CSTD_EN);
865 initcgr.cgr.cstd_en = QM_CGR_EN;
866
867 err = qman_create_cgr(&priv->cgr_data.cgr, QMAN_CGR_FLAG_USE_INIT,
868 &initcgr);
869 if (err < 0) {
870 if (netif_msg_drv(priv))
871 pr_err("%s: Error %d creating CGR with ID %d\n",
872 __func__, err, priv->cgr_data.cgr.cgrid);
873 qman_release_cgrid(priv->cgr_data.cgr.cgrid);
874 goto out_error;
875 }
876 if (netif_msg_drv(priv))
877 pr_debug("Created CGR %d for netdev with hwaddr %pM on QMan channel %d\n",
878 priv->cgr_data.cgr.cgrid, priv->mac_dev->addr,
879 priv->cgr_data.cgr.chan);
880
881 out_error:
882 return err;
883 }
884
dpaa_eth_cgr_set_speed(struct mac_device * mac_dev,int speed)885 static void dpaa_eth_cgr_set_speed(struct mac_device *mac_dev, int speed)
886 {
887 struct net_device *net_dev = to_net_dev(mac_dev->phylink_config.dev);
888 struct dpaa_priv *priv = netdev_priv(net_dev);
889 struct qm_mcc_initcgr opts = { };
890 u32 cs_th;
891 int err;
892
893 opts.we_mask = cpu_to_be16(QM_CGR_WE_CS_THRES);
894 switch (speed) {
895 case SPEED_10000:
896 cs_th = DPAA_CS_THRESHOLD_10G;
897 break;
898 case SPEED_1000:
899 default:
900 cs_th = DPAA_CS_THRESHOLD_1G;
901 break;
902 }
903 qm_cgr_cs_thres_set64(&opts.cgr.cs_thres, cs_th, 1);
904
905 err = qman_update_cgr_safe(&priv->cgr_data.cgr, &opts);
906 if (err)
907 netdev_err(net_dev, "could not update speed: %d\n", err);
908 }
909
dpaa_setup_ingress(const struct dpaa_priv * priv,struct dpaa_fq * fq,const struct qman_fq * template)910 static inline void dpaa_setup_ingress(const struct dpaa_priv *priv,
911 struct dpaa_fq *fq,
912 const struct qman_fq *template)
913 {
914 fq->fq_base = *template;
915 fq->net_dev = priv->net_dev;
916
917 fq->flags = QMAN_FQ_FLAG_NO_ENQUEUE;
918 fq->channel = priv->channel;
919 }
920
dpaa_setup_egress(const struct dpaa_priv * priv,struct dpaa_fq * fq,struct fman_port * port,const struct qman_fq * template)921 static inline void dpaa_setup_egress(const struct dpaa_priv *priv,
922 struct dpaa_fq *fq,
923 struct fman_port *port,
924 const struct qman_fq *template)
925 {
926 fq->fq_base = *template;
927 fq->net_dev = priv->net_dev;
928
929 if (port) {
930 fq->flags = QMAN_FQ_FLAG_TO_DCPORTAL;
931 fq->channel = (u16)fman_port_get_qman_channel_id(port);
932 } else {
933 fq->flags = QMAN_FQ_FLAG_NO_MODIFY;
934 }
935 }
936
dpaa_fq_setup(struct dpaa_priv * priv,const struct dpaa_fq_cbs * fq_cbs,struct fman_port * tx_port)937 static int dpaa_fq_setup(struct dpaa_priv *priv,
938 const struct dpaa_fq_cbs *fq_cbs,
939 struct fman_port *tx_port)
940 {
941 int egress_cnt = 0, conf_cnt = 0, num_portals = 0, portal_cnt = 0, cpu;
942 const cpumask_t *affine_cpus = qman_affine_cpus();
943 struct dpaa_fq *fq;
944 u16 *channels;
945
946 channels = kcalloc(num_possible_cpus(), sizeof(u16), GFP_KERNEL);
947 if (!channels)
948 return -ENOMEM;
949
950 for_each_cpu_and(cpu, affine_cpus, cpu_online_mask)
951 channels[num_portals++] = qman_affine_channel(cpu);
952
953 if (num_portals == 0)
954 dev_err(priv->net_dev->dev.parent,
955 "No Qman software (affine) channels found\n");
956
957 /* Initialize each FQ in the list */
958 list_for_each_entry(fq, &priv->dpaa_fq_list, list) {
959 switch (fq->fq_type) {
960 case FQ_TYPE_RX_DEFAULT:
961 dpaa_setup_ingress(priv, fq, &fq_cbs->rx_defq);
962 break;
963 case FQ_TYPE_RX_ERROR:
964 dpaa_setup_ingress(priv, fq, &fq_cbs->rx_errq);
965 break;
966 case FQ_TYPE_RX_PCD:
967 if (!num_portals)
968 continue;
969 dpaa_setup_ingress(priv, fq, &fq_cbs->rx_defq);
970 fq->channel = channels[portal_cnt++ % num_portals];
971 break;
972 case FQ_TYPE_TX:
973 dpaa_setup_egress(priv, fq, tx_port,
974 &fq_cbs->egress_ern);
975 priv->egress_fqs[egress_cnt++] = &fq->fq_base;
976 break;
977 case FQ_TYPE_TX_CONF_MQ:
978 priv->conf_fqs[conf_cnt++] = &fq->fq_base;
979 fallthrough;
980 case FQ_TYPE_TX_CONFIRM:
981 dpaa_setup_ingress(priv, fq, &fq_cbs->tx_defq);
982 break;
983 case FQ_TYPE_TX_ERROR:
984 dpaa_setup_ingress(priv, fq, &fq_cbs->tx_errq);
985 break;
986 default:
987 dev_warn(priv->net_dev->dev.parent,
988 "Unknown FQ type detected!\n");
989 break;
990 }
991 }
992
993 kfree(channels);
994
995 return 0;
996 }
997
dpaa_tx_fq_to_id(const struct dpaa_priv * priv,struct qman_fq * tx_fq)998 static inline int dpaa_tx_fq_to_id(const struct dpaa_priv *priv,
999 struct qman_fq *tx_fq)
1000 {
1001 int i;
1002
1003 for (i = 0; i < dpaa_max_num_txqs(); i++)
1004 if (priv->egress_fqs[i] == tx_fq)
1005 return i;
1006
1007 return -EINVAL;
1008 }
1009
dpaa_fq_init(struct dpaa_fq * dpaa_fq,bool td_enable)1010 static int dpaa_fq_init(struct dpaa_fq *dpaa_fq, bool td_enable)
1011 {
1012 const struct dpaa_priv *priv;
1013 struct qman_fq *confq = NULL;
1014 struct qm_mcc_initfq initfq;
1015 struct device *dev;
1016 struct qman_fq *fq;
1017 int queue_id;
1018 int err;
1019
1020 priv = netdev_priv(dpaa_fq->net_dev);
1021 dev = dpaa_fq->net_dev->dev.parent;
1022
1023 if (dpaa_fq->fqid == 0)
1024 dpaa_fq->flags |= QMAN_FQ_FLAG_DYNAMIC_FQID;
1025
1026 dpaa_fq->init = !(dpaa_fq->flags & QMAN_FQ_FLAG_NO_MODIFY);
1027
1028 err = qman_create_fq(dpaa_fq->fqid, dpaa_fq->flags, &dpaa_fq->fq_base);
1029 if (err) {
1030 dev_err(dev, "qman_create_fq() failed\n");
1031 return err;
1032 }
1033 fq = &dpaa_fq->fq_base;
1034
1035 if (dpaa_fq->init) {
1036 memset(&initfq, 0, sizeof(initfq));
1037
1038 initfq.we_mask = cpu_to_be16(QM_INITFQ_WE_FQCTRL);
1039 /* Note: we may get to keep an empty FQ in cache */
1040 initfq.fqd.fq_ctrl = cpu_to_be16(QM_FQCTRL_PREFERINCACHE);
1041
1042 /* Try to reduce the number of portal interrupts for
1043 * Tx Confirmation FQs.
1044 */
1045 if (dpaa_fq->fq_type == FQ_TYPE_TX_CONFIRM)
1046 initfq.fqd.fq_ctrl |= cpu_to_be16(QM_FQCTRL_AVOIDBLOCK);
1047
1048 /* FQ placement */
1049 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_DESTWQ);
1050
1051 qm_fqd_set_destwq(&initfq.fqd, dpaa_fq->channel, dpaa_fq->wq);
1052
1053 /* Put all egress queues in a congestion group of their own.
1054 * Sensu stricto, the Tx confirmation queues are Rx FQs,
1055 * rather than Tx - but they nonetheless account for the
1056 * memory footprint on behalf of egress traffic. We therefore
1057 * place them in the netdev's CGR, along with the Tx FQs.
1058 */
1059 if (dpaa_fq->fq_type == FQ_TYPE_TX ||
1060 dpaa_fq->fq_type == FQ_TYPE_TX_CONFIRM ||
1061 dpaa_fq->fq_type == FQ_TYPE_TX_CONF_MQ) {
1062 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_CGID);
1063 initfq.fqd.fq_ctrl |= cpu_to_be16(QM_FQCTRL_CGE);
1064 initfq.fqd.cgid = (u8)priv->cgr_data.cgr.cgrid;
1065 /* Set a fixed overhead accounting, in an attempt to
1066 * reduce the impact of fixed-size skb shells and the
1067 * driver's needed headroom on system memory. This is
1068 * especially the case when the egress traffic is
1069 * composed of small datagrams.
1070 * Unfortunately, QMan's OAL value is capped to an
1071 * insufficient value, but even that is better than
1072 * no overhead accounting at all.
1073 */
1074 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_OAC);
1075 qm_fqd_set_oac(&initfq.fqd, QM_OAC_CG);
1076 qm_fqd_set_oal(&initfq.fqd,
1077 min(sizeof(struct sk_buff) +
1078 priv->tx_headroom,
1079 (size_t)FSL_QMAN_MAX_OAL));
1080 }
1081
1082 if (td_enable) {
1083 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_TDTHRESH);
1084 qm_fqd_set_taildrop(&initfq.fqd, DPAA_FQ_TD, 1);
1085 initfq.fqd.fq_ctrl = cpu_to_be16(QM_FQCTRL_TDE);
1086 }
1087
1088 if (dpaa_fq->fq_type == FQ_TYPE_TX) {
1089 queue_id = dpaa_tx_fq_to_id(priv, &dpaa_fq->fq_base);
1090 if (queue_id >= 0)
1091 confq = priv->conf_fqs[queue_id];
1092 if (confq) {
1093 initfq.we_mask |=
1094 cpu_to_be16(QM_INITFQ_WE_CONTEXTA);
1095 /* ContextA: OVOM=1(use contextA2 bits instead of ICAD)
1096 * A2V=1 (contextA A2 field is valid)
1097 * A0V=1 (contextA A0 field is valid)
1098 * B0V=1 (contextB field is valid)
1099 * ContextA A2: EBD=1 (deallocate buffers inside FMan)
1100 * ContextB B0(ASPID): 0 (absolute Virtual Storage ID)
1101 */
1102 qm_fqd_context_a_set64(&initfq.fqd,
1103 0x1e00000080000000ULL);
1104 }
1105 }
1106
1107 /* Put all the ingress queues in our "ingress CGR". */
1108 if (priv->use_ingress_cgr &&
1109 (dpaa_fq->fq_type == FQ_TYPE_RX_DEFAULT ||
1110 dpaa_fq->fq_type == FQ_TYPE_RX_ERROR ||
1111 dpaa_fq->fq_type == FQ_TYPE_RX_PCD)) {
1112 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_CGID);
1113 initfq.fqd.fq_ctrl |= cpu_to_be16(QM_FQCTRL_CGE);
1114 initfq.fqd.cgid = (u8)priv->ingress_cgr.cgrid;
1115 /* Set a fixed overhead accounting, just like for the
1116 * egress CGR.
1117 */
1118 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_OAC);
1119 qm_fqd_set_oac(&initfq.fqd, QM_OAC_CG);
1120 qm_fqd_set_oal(&initfq.fqd,
1121 min(sizeof(struct sk_buff) +
1122 priv->tx_headroom,
1123 (size_t)FSL_QMAN_MAX_OAL));
1124 }
1125
1126 /* Initialization common to all ingress queues */
1127 if (dpaa_fq->flags & QMAN_FQ_FLAG_NO_ENQUEUE) {
1128 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_CONTEXTA);
1129 initfq.fqd.fq_ctrl |= cpu_to_be16(QM_FQCTRL_HOLDACTIVE |
1130 QM_FQCTRL_CTXASTASHING);
1131 initfq.fqd.context_a.stashing.exclusive =
1132 QM_STASHING_EXCL_DATA | QM_STASHING_EXCL_CTX |
1133 QM_STASHING_EXCL_ANNOTATION;
1134 qm_fqd_set_stashing(&initfq.fqd, 1, 2,
1135 DIV_ROUND_UP(sizeof(struct qman_fq),
1136 64));
1137 }
1138
1139 err = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &initfq);
1140 if (err < 0) {
1141 dev_err(dev, "qman_init_fq(%u) = %d\n",
1142 qman_fq_fqid(fq), err);
1143 qman_destroy_fq(fq);
1144 return err;
1145 }
1146 }
1147
1148 dpaa_fq->fqid = qman_fq_fqid(fq);
1149
1150 if (dpaa_fq->fq_type == FQ_TYPE_RX_DEFAULT ||
1151 dpaa_fq->fq_type == FQ_TYPE_RX_PCD) {
1152 err = xdp_rxq_info_reg(&dpaa_fq->xdp_rxq, dpaa_fq->net_dev,
1153 dpaa_fq->fqid, 0);
1154 if (err) {
1155 dev_err(dev, "xdp_rxq_info_reg() = %d\n", err);
1156 return err;
1157 }
1158
1159 err = xdp_rxq_info_reg_mem_model(&dpaa_fq->xdp_rxq,
1160 MEM_TYPE_PAGE_ORDER0, NULL);
1161 if (err) {
1162 dev_err(dev, "xdp_rxq_info_reg_mem_model() = %d\n",
1163 err);
1164 xdp_rxq_info_unreg(&dpaa_fq->xdp_rxq);
1165 return err;
1166 }
1167 }
1168
1169 return 0;
1170 }
1171
dpaa_fq_free_entry(struct device * dev,struct qman_fq * fq)1172 static int dpaa_fq_free_entry(struct device *dev, struct qman_fq *fq)
1173 {
1174 const struct dpaa_priv *priv;
1175 struct dpaa_fq *dpaa_fq;
1176 int err, error;
1177
1178 err = 0;
1179
1180 dpaa_fq = container_of(fq, struct dpaa_fq, fq_base);
1181 priv = netdev_priv(dpaa_fq->net_dev);
1182
1183 if (dpaa_fq->init) {
1184 err = qman_retire_fq(fq, NULL);
1185 if (err < 0 && netif_msg_drv(priv))
1186 dev_err(dev, "qman_retire_fq(%u) = %d\n",
1187 qman_fq_fqid(fq), err);
1188
1189 error = qman_oos_fq(fq);
1190 if (error < 0 && netif_msg_drv(priv)) {
1191 dev_err(dev, "qman_oos_fq(%u) = %d\n",
1192 qman_fq_fqid(fq), error);
1193 if (err >= 0)
1194 err = error;
1195 }
1196 }
1197
1198 if ((dpaa_fq->fq_type == FQ_TYPE_RX_DEFAULT ||
1199 dpaa_fq->fq_type == FQ_TYPE_RX_PCD) &&
1200 xdp_rxq_info_is_reg(&dpaa_fq->xdp_rxq))
1201 xdp_rxq_info_unreg(&dpaa_fq->xdp_rxq);
1202
1203 qman_destroy_fq(fq);
1204 list_del(&dpaa_fq->list);
1205
1206 return err;
1207 }
1208
dpaa_fq_free(struct device * dev,struct list_head * list)1209 static int dpaa_fq_free(struct device *dev, struct list_head *list)
1210 {
1211 struct dpaa_fq *dpaa_fq, *tmp;
1212 int err, error;
1213
1214 err = 0;
1215 list_for_each_entry_safe(dpaa_fq, tmp, list, list) {
1216 error = dpaa_fq_free_entry(dev, (struct qman_fq *)dpaa_fq);
1217 if (error < 0 && err >= 0)
1218 err = error;
1219 }
1220
1221 return err;
1222 }
1223
dpaa_eth_init_tx_port(struct fman_port * port,struct dpaa_fq * errq,struct dpaa_fq * defq,struct dpaa_buffer_layout * buf_layout)1224 static int dpaa_eth_init_tx_port(struct fman_port *port, struct dpaa_fq *errq,
1225 struct dpaa_fq *defq,
1226 struct dpaa_buffer_layout *buf_layout)
1227 {
1228 struct fman_buffer_prefix_content buf_prefix_content;
1229 struct fman_port_params params;
1230 int err;
1231
1232 memset(¶ms, 0, sizeof(params));
1233 memset(&buf_prefix_content, 0, sizeof(buf_prefix_content));
1234
1235 buf_prefix_content.priv_data_size = buf_layout->priv_data_size;
1236 buf_prefix_content.pass_prs_result = true;
1237 buf_prefix_content.pass_hash_result = true;
1238 buf_prefix_content.pass_time_stamp = true;
1239 buf_prefix_content.data_align = DPAA_FD_DATA_ALIGNMENT;
1240
1241 params.specific_params.non_rx_params.err_fqid = errq->fqid;
1242 params.specific_params.non_rx_params.dflt_fqid = defq->fqid;
1243
1244 err = fman_port_config(port, ¶ms);
1245 if (err) {
1246 pr_err("%s: fman_port_config failed\n", __func__);
1247 return err;
1248 }
1249
1250 err = fman_port_cfg_buf_prefix_content(port, &buf_prefix_content);
1251 if (err) {
1252 pr_err("%s: fman_port_cfg_buf_prefix_content failed\n",
1253 __func__);
1254 return err;
1255 }
1256
1257 err = fman_port_init(port);
1258 if (err)
1259 pr_err("%s: fm_port_init failed\n", __func__);
1260
1261 return err;
1262 }
1263
dpaa_eth_init_rx_port(struct fman_port * port,struct dpaa_bp * bp,struct dpaa_fq * errq,struct dpaa_fq * defq,struct dpaa_fq * pcdq,struct dpaa_buffer_layout * buf_layout)1264 static int dpaa_eth_init_rx_port(struct fman_port *port, struct dpaa_bp *bp,
1265 struct dpaa_fq *errq,
1266 struct dpaa_fq *defq, struct dpaa_fq *pcdq,
1267 struct dpaa_buffer_layout *buf_layout)
1268 {
1269 struct fman_buffer_prefix_content buf_prefix_content;
1270 struct fman_port_rx_params *rx_p;
1271 struct fman_port_params params;
1272 int err;
1273
1274 memset(¶ms, 0, sizeof(params));
1275 memset(&buf_prefix_content, 0, sizeof(buf_prefix_content));
1276
1277 buf_prefix_content.priv_data_size = buf_layout->priv_data_size;
1278 buf_prefix_content.pass_prs_result = true;
1279 buf_prefix_content.pass_hash_result = true;
1280 buf_prefix_content.pass_time_stamp = true;
1281 buf_prefix_content.data_align = DPAA_FD_RX_DATA_ALIGNMENT;
1282
1283 rx_p = ¶ms.specific_params.rx_params;
1284 rx_p->err_fqid = errq->fqid;
1285 rx_p->dflt_fqid = defq->fqid;
1286 if (pcdq) {
1287 rx_p->pcd_base_fqid = pcdq->fqid;
1288 rx_p->pcd_fqs_count = DPAA_ETH_PCD_RXQ_NUM;
1289 }
1290
1291 rx_p->ext_buf_pools.num_of_pools_used = 1;
1292 rx_p->ext_buf_pools.ext_buf_pool[0].id = bp->bpid;
1293 rx_p->ext_buf_pools.ext_buf_pool[0].size = (u16)bp->size;
1294
1295 err = fman_port_config(port, ¶ms);
1296 if (err) {
1297 pr_err("%s: fman_port_config failed\n", __func__);
1298 return err;
1299 }
1300
1301 err = fman_port_cfg_buf_prefix_content(port, &buf_prefix_content);
1302 if (err) {
1303 pr_err("%s: fman_port_cfg_buf_prefix_content failed\n",
1304 __func__);
1305 return err;
1306 }
1307
1308 err = fman_port_init(port);
1309 if (err)
1310 pr_err("%s: fm_port_init failed\n", __func__);
1311
1312 return err;
1313 }
1314
dpaa_eth_init_ports(struct mac_device * mac_dev,struct dpaa_bp * bp,struct fm_port_fqs * port_fqs,struct dpaa_buffer_layout * buf_layout,struct device * dev)1315 static int dpaa_eth_init_ports(struct mac_device *mac_dev,
1316 struct dpaa_bp *bp,
1317 struct fm_port_fqs *port_fqs,
1318 struct dpaa_buffer_layout *buf_layout,
1319 struct device *dev)
1320 {
1321 struct fman_port *rxport = mac_dev->port[RX];
1322 struct fman_port *txport = mac_dev->port[TX];
1323 int err;
1324
1325 err = dpaa_eth_init_tx_port(txport, port_fqs->tx_errq,
1326 port_fqs->tx_defq, &buf_layout[TX]);
1327 if (err)
1328 return err;
1329
1330 err = dpaa_eth_init_rx_port(rxport, bp, port_fqs->rx_errq,
1331 port_fqs->rx_defq, port_fqs->rx_pcdq,
1332 &buf_layout[RX]);
1333
1334 return err;
1335 }
1336
dpaa_bman_release(const struct dpaa_bp * dpaa_bp,struct bm_buffer * bmb,int cnt)1337 static int dpaa_bman_release(const struct dpaa_bp *dpaa_bp,
1338 struct bm_buffer *bmb, int cnt)
1339 {
1340 int err;
1341
1342 err = bman_release(dpaa_bp->pool, bmb, cnt);
1343 /* Should never occur, address anyway to avoid leaking the buffers */
1344 if (WARN_ON(err) && dpaa_bp->free_buf_cb)
1345 while (cnt-- > 0)
1346 dpaa_bp->free_buf_cb(dpaa_bp, &bmb[cnt]);
1347
1348 return cnt;
1349 }
1350
dpaa_release_sgt_members(struct qm_sg_entry * sgt)1351 static void dpaa_release_sgt_members(struct qm_sg_entry *sgt)
1352 {
1353 struct bm_buffer bmb[DPAA_BUFF_RELEASE_MAX];
1354 struct dpaa_bp *dpaa_bp;
1355 int i = 0, j;
1356
1357 memset(bmb, 0, sizeof(bmb));
1358
1359 do {
1360 dpaa_bp = dpaa_bpid2pool(sgt[i].bpid);
1361 if (!dpaa_bp)
1362 return;
1363
1364 j = 0;
1365 do {
1366 WARN_ON(qm_sg_entry_is_ext(&sgt[i]));
1367
1368 bm_buffer_set64(&bmb[j], qm_sg_entry_get64(&sgt[i]));
1369
1370 j++; i++;
1371 } while (j < ARRAY_SIZE(bmb) &&
1372 !qm_sg_entry_is_final(&sgt[i - 1]) &&
1373 sgt[i - 1].bpid == sgt[i].bpid);
1374
1375 dpaa_bman_release(dpaa_bp, bmb, j);
1376 } while (!qm_sg_entry_is_final(&sgt[i - 1]));
1377 }
1378
dpaa_fd_release(const struct net_device * net_dev,const struct qm_fd * fd)1379 static void dpaa_fd_release(const struct net_device *net_dev,
1380 const struct qm_fd *fd)
1381 {
1382 struct qm_sg_entry *sgt;
1383 struct dpaa_bp *dpaa_bp;
1384 struct bm_buffer bmb;
1385 dma_addr_t addr;
1386 void *vaddr;
1387
1388 bmb.data = 0;
1389 bm_buffer_set64(&bmb, qm_fd_addr(fd));
1390
1391 dpaa_bp = dpaa_bpid2pool(fd->bpid);
1392 if (!dpaa_bp)
1393 return;
1394
1395 if (qm_fd_get_format(fd) == qm_fd_sg) {
1396 vaddr = phys_to_virt(qm_fd_addr(fd));
1397 sgt = vaddr + qm_fd_get_offset(fd);
1398
1399 dma_unmap_page(dpaa_bp->priv->rx_dma_dev, qm_fd_addr(fd),
1400 DPAA_BP_RAW_SIZE, DMA_FROM_DEVICE);
1401
1402 dpaa_release_sgt_members(sgt);
1403
1404 addr = dma_map_page(dpaa_bp->priv->rx_dma_dev,
1405 virt_to_page(vaddr), 0, DPAA_BP_RAW_SIZE,
1406 DMA_FROM_DEVICE);
1407 if (dma_mapping_error(dpaa_bp->priv->rx_dma_dev, addr)) {
1408 netdev_err(net_dev, "DMA mapping failed\n");
1409 return;
1410 }
1411 bm_buffer_set64(&bmb, addr);
1412 }
1413
1414 dpaa_bman_release(dpaa_bp, &bmb, 1);
1415 }
1416
count_ern(struct dpaa_percpu_priv * percpu_priv,const union qm_mr_entry * msg)1417 static void count_ern(struct dpaa_percpu_priv *percpu_priv,
1418 const union qm_mr_entry *msg)
1419 {
1420 switch (msg->ern.rc & QM_MR_RC_MASK) {
1421 case QM_MR_RC_CGR_TAILDROP:
1422 percpu_priv->ern_cnt.cg_tdrop++;
1423 break;
1424 case QM_MR_RC_WRED:
1425 percpu_priv->ern_cnt.wred++;
1426 break;
1427 case QM_MR_RC_ERROR:
1428 percpu_priv->ern_cnt.err_cond++;
1429 break;
1430 case QM_MR_RC_ORPWINDOW_EARLY:
1431 percpu_priv->ern_cnt.early_window++;
1432 break;
1433 case QM_MR_RC_ORPWINDOW_LATE:
1434 percpu_priv->ern_cnt.late_window++;
1435 break;
1436 case QM_MR_RC_FQ_TAILDROP:
1437 percpu_priv->ern_cnt.fq_tdrop++;
1438 break;
1439 case QM_MR_RC_ORPWINDOW_RETIRED:
1440 percpu_priv->ern_cnt.fq_retired++;
1441 break;
1442 case QM_MR_RC_ORP_ZERO:
1443 percpu_priv->ern_cnt.orp_zero++;
1444 break;
1445 }
1446 }
1447
1448 /* Turn on HW checksum computation for this outgoing frame.
1449 * If the current protocol is not something we support in this regard
1450 * (or if the stack has already computed the SW checksum), we do nothing.
1451 *
1452 * Returns 0 if all goes well (or HW csum doesn't apply), and a negative value
1453 * otherwise.
1454 *
1455 * Note that this function may modify the fd->cmd field and the skb data buffer
1456 * (the Parse Results area).
1457 */
dpaa_enable_tx_csum(struct dpaa_priv * priv,struct sk_buff * skb,struct qm_fd * fd,void * parse_results)1458 static int dpaa_enable_tx_csum(struct dpaa_priv *priv,
1459 struct sk_buff *skb,
1460 struct qm_fd *fd,
1461 void *parse_results)
1462 {
1463 struct fman_prs_result *parse_result;
1464 u16 ethertype = ntohs(skb->protocol);
1465 struct ipv6hdr *ipv6h = NULL;
1466 struct iphdr *iph;
1467 int retval = 0;
1468 u8 l4_proto;
1469
1470 if (skb->ip_summed != CHECKSUM_PARTIAL)
1471 return 0;
1472
1473 /* Note: L3 csum seems to be already computed in sw, but we can't choose
1474 * L4 alone from the FM configuration anyway.
1475 */
1476
1477 /* Fill in some fields of the Parse Results array, so the FMan
1478 * can find them as if they came from the FMan Parser.
1479 */
1480 parse_result = (struct fman_prs_result *)parse_results;
1481
1482 /* If we're dealing with VLAN, get the real Ethernet type */
1483 if (ethertype == ETH_P_8021Q)
1484 ethertype = ntohs(skb_vlan_eth_hdr(skb)->h_vlan_encapsulated_proto);
1485
1486 /* Fill in the relevant L3 parse result fields
1487 * and read the L4 protocol type
1488 */
1489 switch (ethertype) {
1490 case ETH_P_IP:
1491 parse_result->l3r = cpu_to_be16(FM_L3_PARSE_RESULT_IPV4);
1492 iph = ip_hdr(skb);
1493 WARN_ON(!iph);
1494 l4_proto = iph->protocol;
1495 break;
1496 case ETH_P_IPV6:
1497 parse_result->l3r = cpu_to_be16(FM_L3_PARSE_RESULT_IPV6);
1498 ipv6h = ipv6_hdr(skb);
1499 WARN_ON(!ipv6h);
1500 l4_proto = ipv6h->nexthdr;
1501 break;
1502 default:
1503 /* We shouldn't even be here */
1504 if (net_ratelimit())
1505 netif_alert(priv, tx_err, priv->net_dev,
1506 "Can't compute HW csum for L3 proto 0x%x\n",
1507 ntohs(skb->protocol));
1508 retval = -EIO;
1509 goto return_error;
1510 }
1511
1512 /* Fill in the relevant L4 parse result fields */
1513 switch (l4_proto) {
1514 case IPPROTO_UDP:
1515 parse_result->l4r = FM_L4_PARSE_RESULT_UDP;
1516 break;
1517 case IPPROTO_TCP:
1518 parse_result->l4r = FM_L4_PARSE_RESULT_TCP;
1519 break;
1520 default:
1521 if (net_ratelimit())
1522 netif_alert(priv, tx_err, priv->net_dev,
1523 "Can't compute HW csum for L4 proto 0x%x\n",
1524 l4_proto);
1525 retval = -EIO;
1526 goto return_error;
1527 }
1528
1529 /* At index 0 is IPOffset_1 as defined in the Parse Results */
1530 parse_result->ip_off[0] = (u8)skb_network_offset(skb);
1531 parse_result->l4_off = (u8)skb_transport_offset(skb);
1532
1533 /* Enable L3 (and L4, if TCP or UDP) HW checksum. */
1534 fd->cmd |= cpu_to_be32(FM_FD_CMD_RPD | FM_FD_CMD_DTC);
1535
1536 /* On P1023 and similar platforms fd->cmd interpretation could
1537 * be disabled by setting CONTEXT_A bit ICMD; currently this bit
1538 * is not set so we do not need to check; in the future, if/when
1539 * using context_a we need to check this bit
1540 */
1541
1542 return_error:
1543 return retval;
1544 }
1545
dpaa_bp_add_8_bufs(const struct dpaa_bp * dpaa_bp)1546 static int dpaa_bp_add_8_bufs(const struct dpaa_bp *dpaa_bp)
1547 {
1548 struct net_device *net_dev = dpaa_bp->priv->net_dev;
1549 struct bm_buffer bmb[8];
1550 dma_addr_t addr;
1551 struct page *p;
1552 u8 i;
1553
1554 for (i = 0; i < 8; i++) {
1555 p = dev_alloc_pages(0);
1556 if (unlikely(!p)) {
1557 netdev_err(net_dev, "dev_alloc_pages() failed\n");
1558 goto release_previous_buffs;
1559 }
1560
1561 addr = dma_map_page(dpaa_bp->priv->rx_dma_dev, p, 0,
1562 DPAA_BP_RAW_SIZE, DMA_FROM_DEVICE);
1563 if (unlikely(dma_mapping_error(dpaa_bp->priv->rx_dma_dev,
1564 addr))) {
1565 netdev_err(net_dev, "DMA map failed\n");
1566 goto release_previous_buffs;
1567 }
1568
1569 bmb[i].data = 0;
1570 bm_buffer_set64(&bmb[i], addr);
1571 }
1572
1573 release_bufs:
1574 return dpaa_bman_release(dpaa_bp, bmb, i);
1575
1576 release_previous_buffs:
1577 WARN_ONCE(1, "dpaa_eth: failed to add buffers on Rx\n");
1578
1579 bm_buffer_set64(&bmb[i], 0);
1580 /* Avoid releasing a completely null buffer; bman_release() requires
1581 * at least one buffer.
1582 */
1583 if (likely(i))
1584 goto release_bufs;
1585
1586 return 0;
1587 }
1588
dpaa_bp_seed(struct dpaa_bp * dpaa_bp)1589 static int dpaa_bp_seed(struct dpaa_bp *dpaa_bp)
1590 {
1591 int i;
1592
1593 /* Give each CPU an allotment of "config_count" buffers */
1594 for_each_possible_cpu(i) {
1595 int *count_ptr = per_cpu_ptr(dpaa_bp->percpu_count, i);
1596 int j;
1597
1598 /* Although we access another CPU's counters here
1599 * we do it at boot time so it is safe
1600 */
1601 for (j = 0; j < dpaa_bp->config_count; j += 8)
1602 *count_ptr += dpaa_bp_add_8_bufs(dpaa_bp);
1603 }
1604 return 0;
1605 }
1606
1607 /* Add buffers/(pages) for Rx processing whenever bpool count falls below
1608 * REFILL_THRESHOLD.
1609 */
dpaa_eth_refill_bpool(struct dpaa_bp * dpaa_bp,int * countptr)1610 static int dpaa_eth_refill_bpool(struct dpaa_bp *dpaa_bp, int *countptr)
1611 {
1612 int count = *countptr;
1613 int new_bufs;
1614
1615 if (unlikely(count < FSL_DPAA_ETH_REFILL_THRESHOLD)) {
1616 do {
1617 new_bufs = dpaa_bp_add_8_bufs(dpaa_bp);
1618 if (unlikely(!new_bufs)) {
1619 /* Avoid looping forever if we've temporarily
1620 * run out of memory. We'll try again at the
1621 * next NAPI cycle.
1622 */
1623 break;
1624 }
1625 count += new_bufs;
1626 } while (count < FSL_DPAA_ETH_MAX_BUF_COUNT);
1627
1628 *countptr = count;
1629 if (unlikely(count < FSL_DPAA_ETH_MAX_BUF_COUNT))
1630 return -ENOMEM;
1631 }
1632
1633 return 0;
1634 }
1635
dpaa_eth_refill_bpools(struct dpaa_priv * priv)1636 static int dpaa_eth_refill_bpools(struct dpaa_priv *priv)
1637 {
1638 struct dpaa_bp *dpaa_bp;
1639 int *countptr;
1640
1641 dpaa_bp = priv->dpaa_bp;
1642 if (!dpaa_bp)
1643 return -EINVAL;
1644 countptr = this_cpu_ptr(dpaa_bp->percpu_count);
1645
1646 return dpaa_eth_refill_bpool(dpaa_bp, countptr);
1647 }
1648
1649 /* Cleanup function for outgoing frame descriptors that were built on Tx path,
1650 * either contiguous frames or scatter/gather ones.
1651 * Skb freeing is not handled here.
1652 *
1653 * This function may be called on error paths in the Tx function, so guard
1654 * against cases when not all fd relevant fields were filled in. To avoid
1655 * reading the invalid transmission timestamp for the error paths set ts to
1656 * false.
1657 *
1658 * Return the skb backpointer, since for S/G frames the buffer containing it
1659 * gets freed here.
1660 *
1661 * No skb backpointer is set when transmitting XDP frames. Cleanup the buffer
1662 * and return NULL in this case.
1663 */
dpaa_cleanup_tx_fd(const struct dpaa_priv * priv,const struct qm_fd * fd,bool ts)1664 static struct sk_buff *dpaa_cleanup_tx_fd(const struct dpaa_priv *priv,
1665 const struct qm_fd *fd, bool ts)
1666 {
1667 const enum dma_data_direction dma_dir = DMA_TO_DEVICE;
1668 struct device *dev = priv->net_dev->dev.parent;
1669 struct skb_shared_hwtstamps shhwtstamps;
1670 dma_addr_t addr = qm_fd_addr(fd);
1671 void *vaddr = phys_to_virt(addr);
1672 const struct qm_sg_entry *sgt;
1673 struct dpaa_eth_swbp *swbp;
1674 struct sk_buff *skb;
1675 u64 ns;
1676 int i;
1677
1678 if (unlikely(qm_fd_get_format(fd) == qm_fd_sg)) {
1679 dma_unmap_page(priv->tx_dma_dev, addr,
1680 qm_fd_get_offset(fd) + DPAA_SGT_SIZE,
1681 dma_dir);
1682
1683 /* The sgt buffer has been allocated with netdev_alloc_frag(),
1684 * it's from lowmem.
1685 */
1686 sgt = vaddr + qm_fd_get_offset(fd);
1687
1688 /* sgt[0] is from lowmem, was dma_map_single()-ed */
1689 dma_unmap_single(priv->tx_dma_dev, qm_sg_addr(&sgt[0]),
1690 qm_sg_entry_get_len(&sgt[0]), dma_dir);
1691
1692 /* remaining pages were mapped with skb_frag_dma_map() */
1693 for (i = 1; (i < DPAA_SGT_MAX_ENTRIES) &&
1694 !qm_sg_entry_is_final(&sgt[i - 1]); i++) {
1695 WARN_ON(qm_sg_entry_is_ext(&sgt[i]));
1696
1697 dma_unmap_page(priv->tx_dma_dev, qm_sg_addr(&sgt[i]),
1698 qm_sg_entry_get_len(&sgt[i]), dma_dir);
1699 }
1700 } else {
1701 dma_unmap_single(priv->tx_dma_dev, addr,
1702 qm_fd_get_offset(fd) + qm_fd_get_length(fd),
1703 dma_dir);
1704 }
1705
1706 swbp = (struct dpaa_eth_swbp *)vaddr;
1707 skb = swbp->skb;
1708
1709 /* No skb backpointer is set when running XDP. An xdp_frame
1710 * backpointer is saved instead.
1711 */
1712 if (!skb) {
1713 xdp_return_frame(swbp->xdpf);
1714 return NULL;
1715 }
1716
1717 /* DMA unmapping is required before accessing the HW provided info */
1718 if (ts && priv->tx_tstamp &&
1719 skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) {
1720 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
1721
1722 if (!fman_port_get_tstamp(priv->mac_dev->port[TX], vaddr,
1723 &ns)) {
1724 shhwtstamps.hwtstamp = ns_to_ktime(ns);
1725 skb_tstamp_tx(skb, &shhwtstamps);
1726 } else {
1727 dev_warn(dev, "fman_port_get_tstamp failed!\n");
1728 }
1729 }
1730
1731 if (qm_fd_get_format(fd) == qm_fd_sg)
1732 /* Free the page that we allocated on Tx for the SGT */
1733 free_pages((unsigned long)vaddr, 0);
1734
1735 return skb;
1736 }
1737
rx_csum_offload(const struct dpaa_priv * priv,const struct qm_fd * fd)1738 static u8 rx_csum_offload(const struct dpaa_priv *priv, const struct qm_fd *fd)
1739 {
1740 /* The parser has run and performed L4 checksum validation.
1741 * We know there were no parser errors (and implicitly no
1742 * L4 csum error), otherwise we wouldn't be here.
1743 */
1744 if ((priv->net_dev->features & NETIF_F_RXCSUM) &&
1745 (be32_to_cpu(fd->status) & FM_FD_STAT_L4CV))
1746 return CHECKSUM_UNNECESSARY;
1747
1748 /* We're here because either the parser didn't run or the L4 checksum
1749 * was not verified. This may include the case of a UDP frame with
1750 * checksum zero or an L4 proto other than TCP/UDP
1751 */
1752 return CHECKSUM_NONE;
1753 }
1754
1755 #define PTR_IS_ALIGNED(x, a) (IS_ALIGNED((unsigned long)(x), (a)))
1756
1757 /* Build a linear skb around the received buffer.
1758 * We are guaranteed there is enough room at the end of the data buffer to
1759 * accommodate the shared info area of the skb.
1760 */
contig_fd_to_skb(const struct dpaa_priv * priv,const struct qm_fd * fd)1761 static struct sk_buff *contig_fd_to_skb(const struct dpaa_priv *priv,
1762 const struct qm_fd *fd)
1763 {
1764 ssize_t fd_off = qm_fd_get_offset(fd);
1765 dma_addr_t addr = qm_fd_addr(fd);
1766 struct dpaa_bp *dpaa_bp;
1767 struct sk_buff *skb;
1768 void *vaddr;
1769
1770 vaddr = phys_to_virt(addr);
1771 WARN_ON(!IS_ALIGNED((unsigned long)vaddr, SMP_CACHE_BYTES));
1772
1773 dpaa_bp = dpaa_bpid2pool(fd->bpid);
1774 if (!dpaa_bp)
1775 goto free_buffer;
1776
1777 skb = build_skb(vaddr, dpaa_bp->size +
1778 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)));
1779 if (WARN_ONCE(!skb, "Build skb failure on Rx\n"))
1780 goto free_buffer;
1781 skb_reserve(skb, fd_off);
1782 skb_put(skb, qm_fd_get_length(fd));
1783
1784 skb->ip_summed = rx_csum_offload(priv, fd);
1785
1786 return skb;
1787
1788 free_buffer:
1789 free_pages((unsigned long)vaddr, 0);
1790 return NULL;
1791 }
1792
1793 /* Build an skb with the data of the first S/G entry in the linear portion and
1794 * the rest of the frame as skb fragments.
1795 *
1796 * The page fragment holding the S/G Table is recycled here.
1797 */
sg_fd_to_skb(const struct dpaa_priv * priv,const struct qm_fd * fd)1798 static struct sk_buff *sg_fd_to_skb(const struct dpaa_priv *priv,
1799 const struct qm_fd *fd)
1800 {
1801 ssize_t fd_off = qm_fd_get_offset(fd);
1802 dma_addr_t addr = qm_fd_addr(fd);
1803 const struct qm_sg_entry *sgt;
1804 struct page *page, *head_page;
1805 struct dpaa_bp *dpaa_bp;
1806 void *vaddr, *sg_vaddr;
1807 int frag_off, frag_len;
1808 struct sk_buff *skb;
1809 dma_addr_t sg_addr;
1810 int page_offset;
1811 unsigned int sz;
1812 int *count_ptr;
1813 int i, j;
1814
1815 vaddr = phys_to_virt(addr);
1816 WARN_ON(!IS_ALIGNED((unsigned long)vaddr, SMP_CACHE_BYTES));
1817
1818 /* Iterate through the SGT entries and add data buffers to the skb */
1819 sgt = vaddr + fd_off;
1820 skb = NULL;
1821 for (i = 0; i < DPAA_SGT_MAX_ENTRIES; i++) {
1822 /* Extension bit is not supported */
1823 WARN_ON(qm_sg_entry_is_ext(&sgt[i]));
1824
1825 sg_addr = qm_sg_addr(&sgt[i]);
1826 sg_vaddr = phys_to_virt(sg_addr);
1827 WARN_ON(!PTR_IS_ALIGNED(sg_vaddr, SMP_CACHE_BYTES));
1828
1829 dma_unmap_page(priv->rx_dma_dev, sg_addr,
1830 DPAA_BP_RAW_SIZE, DMA_FROM_DEVICE);
1831
1832 /* We may use multiple Rx pools */
1833 dpaa_bp = dpaa_bpid2pool(sgt[i].bpid);
1834 if (!dpaa_bp)
1835 goto free_buffers;
1836
1837 if (!skb) {
1838 sz = dpaa_bp->size +
1839 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
1840 skb = build_skb(sg_vaddr, sz);
1841 if (WARN_ON(!skb))
1842 goto free_buffers;
1843
1844 skb->ip_summed = rx_csum_offload(priv, fd);
1845
1846 /* Make sure forwarded skbs will have enough space
1847 * on Tx, if extra headers are added.
1848 */
1849 WARN_ON(fd_off != priv->rx_headroom);
1850 skb_reserve(skb, fd_off);
1851 skb_put(skb, qm_sg_entry_get_len(&sgt[i]));
1852 } else {
1853 /* Not the first S/G entry; all data from buffer will
1854 * be added in an skb fragment; fragment index is offset
1855 * by one since first S/G entry was incorporated in the
1856 * linear part of the skb.
1857 *
1858 * Caution: 'page' may be a tail page.
1859 */
1860 page = virt_to_page(sg_vaddr);
1861 head_page = virt_to_head_page(sg_vaddr);
1862
1863 /* Compute offset in (possibly tail) page */
1864 page_offset = ((unsigned long)sg_vaddr &
1865 (PAGE_SIZE - 1)) +
1866 (page_address(page) - page_address(head_page));
1867 /* page_offset only refers to the beginning of sgt[i];
1868 * but the buffer itself may have an internal offset.
1869 */
1870 frag_off = qm_sg_entry_get_off(&sgt[i]) + page_offset;
1871 frag_len = qm_sg_entry_get_len(&sgt[i]);
1872 /* skb_add_rx_frag() does no checking on the page; if
1873 * we pass it a tail page, we'll end up with
1874 * bad page accounting and eventually with segafults.
1875 */
1876 skb_add_rx_frag(skb, i - 1, head_page, frag_off,
1877 frag_len, dpaa_bp->size);
1878 }
1879
1880 /* Update the pool count for the current {cpu x bpool} */
1881 count_ptr = this_cpu_ptr(dpaa_bp->percpu_count);
1882 (*count_ptr)--;
1883
1884 if (qm_sg_entry_is_final(&sgt[i]))
1885 break;
1886 }
1887 WARN_ONCE(i == DPAA_SGT_MAX_ENTRIES, "No final bit on SGT\n");
1888
1889 /* free the SG table buffer */
1890 free_pages((unsigned long)vaddr, 0);
1891
1892 return skb;
1893
1894 free_buffers:
1895 /* free all the SG entries */
1896 for (j = 0; j < DPAA_SGT_MAX_ENTRIES ; j++) {
1897 sg_addr = qm_sg_addr(&sgt[j]);
1898 sg_vaddr = phys_to_virt(sg_addr);
1899 /* all pages 0..i were unmaped */
1900 if (j > i)
1901 dma_unmap_page(priv->rx_dma_dev, qm_sg_addr(&sgt[j]),
1902 DPAA_BP_RAW_SIZE, DMA_FROM_DEVICE);
1903 free_pages((unsigned long)sg_vaddr, 0);
1904 /* counters 0..i-1 were decremented */
1905 if (j >= i) {
1906 dpaa_bp = dpaa_bpid2pool(sgt[j].bpid);
1907 if (dpaa_bp) {
1908 count_ptr = this_cpu_ptr(dpaa_bp->percpu_count);
1909 (*count_ptr)--;
1910 }
1911 }
1912
1913 if (qm_sg_entry_is_final(&sgt[j]))
1914 break;
1915 }
1916 /* free the SGT fragment */
1917 free_pages((unsigned long)vaddr, 0);
1918
1919 return NULL;
1920 }
1921
skb_to_contig_fd(struct dpaa_priv * priv,struct sk_buff * skb,struct qm_fd * fd,int * offset)1922 static int skb_to_contig_fd(struct dpaa_priv *priv,
1923 struct sk_buff *skb, struct qm_fd *fd,
1924 int *offset)
1925 {
1926 struct net_device *net_dev = priv->net_dev;
1927 enum dma_data_direction dma_dir;
1928 struct dpaa_eth_swbp *swbp;
1929 unsigned char *buff_start;
1930 dma_addr_t addr;
1931 int err;
1932
1933 /* We are guaranteed to have at least tx_headroom bytes
1934 * available, so just use that for offset.
1935 */
1936 fd->bpid = FSL_DPAA_BPID_INV;
1937 buff_start = skb->data - priv->tx_headroom;
1938 dma_dir = DMA_TO_DEVICE;
1939
1940 swbp = (struct dpaa_eth_swbp *)buff_start;
1941 swbp->skb = skb;
1942
1943 /* Enable L3/L4 hardware checksum computation.
1944 *
1945 * We must do this before dma_map_single(DMA_TO_DEVICE), because we may
1946 * need to write into the skb.
1947 */
1948 err = dpaa_enable_tx_csum(priv, skb, fd,
1949 buff_start + DPAA_TX_PRIV_DATA_SIZE);
1950 if (unlikely(err < 0)) {
1951 if (net_ratelimit())
1952 netif_err(priv, tx_err, net_dev, "HW csum error: %d\n",
1953 err);
1954 return err;
1955 }
1956
1957 /* Fill in the rest of the FD fields */
1958 qm_fd_set_contig(fd, priv->tx_headroom, skb->len);
1959 fd->cmd |= cpu_to_be32(FM_FD_CMD_FCO);
1960
1961 /* Map the entire buffer size that may be seen by FMan, but no more */
1962 addr = dma_map_single(priv->tx_dma_dev, buff_start,
1963 priv->tx_headroom + skb->len, dma_dir);
1964 if (unlikely(dma_mapping_error(priv->tx_dma_dev, addr))) {
1965 if (net_ratelimit())
1966 netif_err(priv, tx_err, net_dev, "dma_map_single() failed\n");
1967 return -EINVAL;
1968 }
1969 qm_fd_addr_set64(fd, addr);
1970
1971 return 0;
1972 }
1973
skb_to_sg_fd(struct dpaa_priv * priv,struct sk_buff * skb,struct qm_fd * fd)1974 static int skb_to_sg_fd(struct dpaa_priv *priv,
1975 struct sk_buff *skb, struct qm_fd *fd)
1976 {
1977 const enum dma_data_direction dma_dir = DMA_TO_DEVICE;
1978 const int nr_frags = skb_shinfo(skb)->nr_frags;
1979 struct net_device *net_dev = priv->net_dev;
1980 struct dpaa_eth_swbp *swbp;
1981 struct qm_sg_entry *sgt;
1982 void *buff_start;
1983 skb_frag_t *frag;
1984 dma_addr_t addr;
1985 size_t frag_len;
1986 struct page *p;
1987 int i, j, err;
1988
1989 /* get a page to store the SGTable */
1990 p = dev_alloc_pages(0);
1991 if (unlikely(!p)) {
1992 netdev_err(net_dev, "dev_alloc_pages() failed\n");
1993 return -ENOMEM;
1994 }
1995 buff_start = page_address(p);
1996
1997 /* Enable L3/L4 hardware checksum computation.
1998 *
1999 * We must do this before dma_map_single(DMA_TO_DEVICE), because we may
2000 * need to write into the skb.
2001 */
2002 err = dpaa_enable_tx_csum(priv, skb, fd,
2003 buff_start + DPAA_TX_PRIV_DATA_SIZE);
2004 if (unlikely(err < 0)) {
2005 if (net_ratelimit())
2006 netif_err(priv, tx_err, net_dev, "HW csum error: %d\n",
2007 err);
2008 goto csum_failed;
2009 }
2010
2011 /* SGT[0] is used by the linear part */
2012 sgt = (struct qm_sg_entry *)(buff_start + priv->tx_headroom);
2013 frag_len = skb_headlen(skb);
2014 qm_sg_entry_set_len(&sgt[0], frag_len);
2015 sgt[0].bpid = FSL_DPAA_BPID_INV;
2016 sgt[0].offset = 0;
2017 addr = dma_map_single(priv->tx_dma_dev, skb->data,
2018 skb_headlen(skb), dma_dir);
2019 if (unlikely(dma_mapping_error(priv->tx_dma_dev, addr))) {
2020 netdev_err(priv->net_dev, "DMA mapping failed\n");
2021 err = -EINVAL;
2022 goto sg0_map_failed;
2023 }
2024 qm_sg_entry_set64(&sgt[0], addr);
2025
2026 /* populate the rest of SGT entries */
2027 for (i = 0; i < nr_frags; i++) {
2028 frag = &skb_shinfo(skb)->frags[i];
2029 frag_len = skb_frag_size(frag);
2030 WARN_ON(!skb_frag_page(frag));
2031 addr = skb_frag_dma_map(priv->tx_dma_dev, frag, 0,
2032 frag_len, dma_dir);
2033 if (unlikely(dma_mapping_error(priv->tx_dma_dev, addr))) {
2034 netdev_err(priv->net_dev, "DMA mapping failed\n");
2035 err = -EINVAL;
2036 goto sg_map_failed;
2037 }
2038
2039 qm_sg_entry_set_len(&sgt[i + 1], frag_len);
2040 sgt[i + 1].bpid = FSL_DPAA_BPID_INV;
2041 sgt[i + 1].offset = 0;
2042
2043 /* keep the offset in the address */
2044 qm_sg_entry_set64(&sgt[i + 1], addr);
2045 }
2046
2047 /* Set the final bit in the last used entry of the SGT */
2048 qm_sg_entry_set_f(&sgt[nr_frags], frag_len);
2049
2050 /* set fd offset to priv->tx_headroom */
2051 qm_fd_set_sg(fd, priv->tx_headroom, skb->len);
2052
2053 /* DMA map the SGT page */
2054 swbp = (struct dpaa_eth_swbp *)buff_start;
2055 swbp->skb = skb;
2056
2057 addr = dma_map_page(priv->tx_dma_dev, p, 0,
2058 priv->tx_headroom + DPAA_SGT_SIZE, dma_dir);
2059 if (unlikely(dma_mapping_error(priv->tx_dma_dev, addr))) {
2060 netdev_err(priv->net_dev, "DMA mapping failed\n");
2061 err = -EINVAL;
2062 goto sgt_map_failed;
2063 }
2064
2065 fd->bpid = FSL_DPAA_BPID_INV;
2066 fd->cmd |= cpu_to_be32(FM_FD_CMD_FCO);
2067 qm_fd_addr_set64(fd, addr);
2068
2069 return 0;
2070
2071 sgt_map_failed:
2072 sg_map_failed:
2073 for (j = 0; j < i; j++)
2074 dma_unmap_page(priv->tx_dma_dev, qm_sg_addr(&sgt[j]),
2075 qm_sg_entry_get_len(&sgt[j]), dma_dir);
2076 sg0_map_failed:
2077 csum_failed:
2078 free_pages((unsigned long)buff_start, 0);
2079
2080 return err;
2081 }
2082
dpaa_xmit(struct dpaa_priv * priv,struct rtnl_link_stats64 * percpu_stats,int queue,struct qm_fd * fd)2083 static inline int dpaa_xmit(struct dpaa_priv *priv,
2084 struct rtnl_link_stats64 *percpu_stats,
2085 int queue,
2086 struct qm_fd *fd)
2087 {
2088 struct qman_fq *egress_fq;
2089 int err, i;
2090
2091 egress_fq = priv->egress_fqs[queue];
2092 if (fd->bpid == FSL_DPAA_BPID_INV)
2093 fd->cmd |= cpu_to_be32(qman_fq_fqid(priv->conf_fqs[queue]));
2094
2095 /* Trace this Tx fd */
2096 trace_dpaa_tx_fd(priv->net_dev, egress_fq, fd);
2097
2098 for (i = 0; i < DPAA_ENQUEUE_RETRIES; i++) {
2099 err = qman_enqueue(egress_fq, fd);
2100 if (err != -EBUSY)
2101 break;
2102 }
2103
2104 if (unlikely(err < 0)) {
2105 percpu_stats->tx_fifo_errors++;
2106 return err;
2107 }
2108
2109 percpu_stats->tx_packets++;
2110 percpu_stats->tx_bytes += qm_fd_get_length(fd);
2111
2112 return 0;
2113 }
2114
2115 #ifdef CONFIG_DPAA_ERRATUM_A050385
dpaa_a050385_wa_skb(struct net_device * net_dev,struct sk_buff ** s)2116 static int dpaa_a050385_wa_skb(struct net_device *net_dev, struct sk_buff **s)
2117 {
2118 struct dpaa_priv *priv = netdev_priv(net_dev);
2119 struct sk_buff *new_skb, *skb = *s;
2120 unsigned char *start, i;
2121
2122 /* check linear buffer alignment */
2123 if (!PTR_IS_ALIGNED(skb->data, DPAA_A050385_ALIGN))
2124 goto workaround;
2125
2126 /* linear buffers just need to have an aligned start */
2127 if (!skb_is_nonlinear(skb))
2128 return 0;
2129
2130 /* linear data size for nonlinear skbs needs to be aligned */
2131 if (!IS_ALIGNED(skb_headlen(skb), DPAA_A050385_ALIGN))
2132 goto workaround;
2133
2134 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2135 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2136
2137 /* all fragments need to have aligned start addresses */
2138 if (!IS_ALIGNED(skb_frag_off(frag), DPAA_A050385_ALIGN))
2139 goto workaround;
2140
2141 /* all but last fragment need to have aligned sizes */
2142 if (!IS_ALIGNED(skb_frag_size(frag), DPAA_A050385_ALIGN) &&
2143 (i < skb_shinfo(skb)->nr_frags - 1))
2144 goto workaround;
2145 }
2146
2147 return 0;
2148
2149 workaround:
2150 /* copy all the skb content into a new linear buffer */
2151 new_skb = netdev_alloc_skb(net_dev, skb->len + DPAA_A050385_ALIGN - 1 +
2152 priv->tx_headroom);
2153 if (!new_skb)
2154 return -ENOMEM;
2155
2156 /* NET_SKB_PAD bytes already reserved, adding up to tx_headroom */
2157 skb_reserve(new_skb, priv->tx_headroom - NET_SKB_PAD);
2158
2159 /* Workaround for DPAA_A050385 requires data start to be aligned */
2160 start = PTR_ALIGN(new_skb->data, DPAA_A050385_ALIGN);
2161 if (start - new_skb->data)
2162 skb_reserve(new_skb, start - new_skb->data);
2163
2164 skb_put(new_skb, skb->len);
2165 skb_copy_bits(skb, 0, new_skb->data, skb->len);
2166 skb_copy_header(new_skb, skb);
2167 new_skb->dev = skb->dev;
2168
2169 /* Copy relevant timestamp info from the old skb to the new */
2170 if (priv->tx_tstamp) {
2171 skb_shinfo(new_skb)->tx_flags = skb_shinfo(skb)->tx_flags;
2172 skb_shinfo(new_skb)->hwtstamps = skb_shinfo(skb)->hwtstamps;
2173 skb_shinfo(new_skb)->tskey = skb_shinfo(skb)->tskey;
2174 if (skb->sk)
2175 skb_set_owner_w(new_skb, skb->sk);
2176 }
2177
2178 /* We move the headroom when we align it so we have to reset the
2179 * network and transport header offsets relative to the new data
2180 * pointer. The checksum offload relies on these offsets.
2181 */
2182 skb_set_network_header(new_skb, skb_network_offset(skb));
2183 skb_set_transport_header(new_skb, skb_transport_offset(skb));
2184
2185 dev_kfree_skb(skb);
2186 *s = new_skb;
2187
2188 return 0;
2189 }
2190
dpaa_a050385_wa_xdpf(struct dpaa_priv * priv,struct xdp_frame ** init_xdpf)2191 static int dpaa_a050385_wa_xdpf(struct dpaa_priv *priv,
2192 struct xdp_frame **init_xdpf)
2193 {
2194 struct xdp_frame *new_xdpf, *xdpf = *init_xdpf;
2195 void *new_buff, *aligned_data;
2196 struct page *p;
2197 u32 data_shift;
2198 int headroom;
2199
2200 /* Check the data alignment and make sure the headroom is large
2201 * enough to store the xdpf backpointer. Use an aligned headroom
2202 * value.
2203 *
2204 * Due to alignment constraints, we give XDP access to the full 256
2205 * byte frame headroom. If the XDP program uses all of it, copy the
2206 * data to a new buffer and make room for storing the backpointer.
2207 */
2208 if (PTR_IS_ALIGNED(xdpf->data, DPAA_FD_DATA_ALIGNMENT) &&
2209 xdpf->headroom >= priv->tx_headroom) {
2210 xdpf->headroom = priv->tx_headroom;
2211 return 0;
2212 }
2213
2214 /* Try to move the data inside the buffer just enough to align it and
2215 * store the xdpf backpointer. If the available headroom isn't large
2216 * enough, resort to allocating a new buffer and copying the data.
2217 */
2218 aligned_data = PTR_ALIGN_DOWN(xdpf->data, DPAA_FD_DATA_ALIGNMENT);
2219 data_shift = xdpf->data - aligned_data;
2220
2221 /* The XDP frame's headroom needs to be large enough to accommodate
2222 * shifting the data as well as storing the xdpf backpointer.
2223 */
2224 if (xdpf->headroom >= data_shift + priv->tx_headroom) {
2225 memmove(aligned_data, xdpf->data, xdpf->len);
2226 xdpf->data = aligned_data;
2227 xdpf->headroom = priv->tx_headroom;
2228 return 0;
2229 }
2230
2231 /* The new xdp_frame is stored in the new buffer. Reserve enough space
2232 * in the headroom for storing it along with the driver's private
2233 * info. The headroom needs to be aligned to DPAA_FD_DATA_ALIGNMENT to
2234 * guarantee the data's alignment in the buffer.
2235 */
2236 headroom = ALIGN(sizeof(*new_xdpf) + priv->tx_headroom,
2237 DPAA_FD_DATA_ALIGNMENT);
2238
2239 /* Assure the extended headroom and data don't overflow the buffer,
2240 * while maintaining the mandatory tailroom.
2241 */
2242 if (headroom + xdpf->len > DPAA_BP_RAW_SIZE -
2243 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
2244 return -ENOMEM;
2245
2246 p = dev_alloc_pages(0);
2247 if (unlikely(!p))
2248 return -ENOMEM;
2249
2250 /* Copy the data to the new buffer at a properly aligned offset */
2251 new_buff = page_address(p);
2252 memcpy(new_buff + headroom, xdpf->data, xdpf->len);
2253
2254 /* Create an XDP frame around the new buffer in a similar fashion
2255 * to xdp_convert_buff_to_frame.
2256 */
2257 new_xdpf = new_buff;
2258 new_xdpf->data = new_buff + headroom;
2259 new_xdpf->len = xdpf->len;
2260 new_xdpf->headroom = priv->tx_headroom;
2261 new_xdpf->frame_sz = DPAA_BP_RAW_SIZE;
2262 new_xdpf->mem.type = MEM_TYPE_PAGE_ORDER0;
2263
2264 /* Release the initial buffer */
2265 xdp_return_frame_rx_napi(xdpf);
2266
2267 *init_xdpf = new_xdpf;
2268 return 0;
2269 }
2270 #endif
2271
2272 static netdev_tx_t
dpaa_start_xmit(struct sk_buff * skb,struct net_device * net_dev)2273 dpaa_start_xmit(struct sk_buff *skb, struct net_device *net_dev)
2274 {
2275 const int queue_mapping = skb_get_queue_mapping(skb);
2276 struct rtnl_link_stats64 *percpu_stats;
2277 struct dpaa_percpu_priv *percpu_priv;
2278 struct netdev_queue *txq;
2279 struct dpaa_priv *priv;
2280 struct qm_fd fd;
2281 bool nonlinear;
2282 int offset = 0;
2283 int err = 0;
2284
2285 priv = netdev_priv(net_dev);
2286 percpu_priv = this_cpu_ptr(priv->percpu_priv);
2287 percpu_stats = &percpu_priv->stats;
2288
2289 qm_fd_clear_fd(&fd);
2290
2291 /* Packet data is always read as 32-bit words, so zero out any part of
2292 * the skb which might be sent if we have to pad the packet
2293 */
2294 if (__skb_put_padto(skb, ETH_ZLEN, false))
2295 goto enomem;
2296
2297 nonlinear = skb_is_nonlinear(skb);
2298 if (!nonlinear) {
2299 /* We're going to store the skb backpointer at the beginning
2300 * of the data buffer, so we need a privately owned skb
2301 *
2302 * We've made sure skb is not shared in dev->priv_flags,
2303 * we need to verify the skb head is not cloned
2304 */
2305 if (skb_cow_head(skb, priv->tx_headroom))
2306 goto enomem;
2307
2308 WARN_ON(skb_is_nonlinear(skb));
2309 }
2310
2311 /* MAX_SKB_FRAGS is equal or larger than our dpaa_SGT_MAX_ENTRIES;
2312 * make sure we don't feed FMan with more fragments than it supports.
2313 */
2314 if (unlikely(nonlinear &&
2315 (skb_shinfo(skb)->nr_frags >= DPAA_SGT_MAX_ENTRIES))) {
2316 /* If the egress skb contains more fragments than we support
2317 * we have no choice but to linearize it ourselves.
2318 */
2319 if (__skb_linearize(skb))
2320 goto enomem;
2321
2322 nonlinear = skb_is_nonlinear(skb);
2323 }
2324
2325 #ifdef CONFIG_DPAA_ERRATUM_A050385
2326 if (unlikely(fman_has_errata_a050385())) {
2327 if (dpaa_a050385_wa_skb(net_dev, &skb))
2328 goto enomem;
2329 nonlinear = skb_is_nonlinear(skb);
2330 }
2331 #endif
2332
2333 if (nonlinear) {
2334 /* Just create a S/G fd based on the skb */
2335 err = skb_to_sg_fd(priv, skb, &fd);
2336 percpu_priv->tx_frag_skbuffs++;
2337 } else {
2338 /* Create a contig FD from this skb */
2339 err = skb_to_contig_fd(priv, skb, &fd, &offset);
2340 }
2341 if (unlikely(err < 0))
2342 goto skb_to_fd_failed;
2343
2344 txq = netdev_get_tx_queue(net_dev, queue_mapping);
2345
2346 /* LLTX requires to do our own update of trans_start */
2347 txq_trans_cond_update(txq);
2348
2349 if (priv->tx_tstamp && skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) {
2350 fd.cmd |= cpu_to_be32(FM_FD_CMD_UPD);
2351 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2352 }
2353
2354 if (likely(dpaa_xmit(priv, percpu_stats, queue_mapping, &fd) == 0))
2355 return NETDEV_TX_OK;
2356
2357 dpaa_cleanup_tx_fd(priv, &fd, false);
2358 skb_to_fd_failed:
2359 enomem:
2360 percpu_stats->tx_errors++;
2361 dev_kfree_skb(skb);
2362 return NETDEV_TX_OK;
2363 }
2364
dpaa_rx_error(struct net_device * net_dev,const struct dpaa_priv * priv,struct dpaa_percpu_priv * percpu_priv,const struct qm_fd * fd,u32 fqid)2365 static void dpaa_rx_error(struct net_device *net_dev,
2366 const struct dpaa_priv *priv,
2367 struct dpaa_percpu_priv *percpu_priv,
2368 const struct qm_fd *fd,
2369 u32 fqid)
2370 {
2371 if (net_ratelimit())
2372 netif_err(priv, hw, net_dev, "Err FD status = 0x%08x\n",
2373 be32_to_cpu(fd->status) & FM_FD_STAT_RX_ERRORS);
2374
2375 percpu_priv->stats.rx_errors++;
2376
2377 if (be32_to_cpu(fd->status) & FM_FD_ERR_DMA)
2378 percpu_priv->rx_errors.dme++;
2379 if (be32_to_cpu(fd->status) & FM_FD_ERR_PHYSICAL)
2380 percpu_priv->rx_errors.fpe++;
2381 if (be32_to_cpu(fd->status) & FM_FD_ERR_SIZE)
2382 percpu_priv->rx_errors.fse++;
2383 if (be32_to_cpu(fd->status) & FM_FD_ERR_PRS_HDR_ERR)
2384 percpu_priv->rx_errors.phe++;
2385
2386 dpaa_fd_release(net_dev, fd);
2387 }
2388
dpaa_tx_error(struct net_device * net_dev,const struct dpaa_priv * priv,struct dpaa_percpu_priv * percpu_priv,const struct qm_fd * fd,u32 fqid)2389 static void dpaa_tx_error(struct net_device *net_dev,
2390 const struct dpaa_priv *priv,
2391 struct dpaa_percpu_priv *percpu_priv,
2392 const struct qm_fd *fd,
2393 u32 fqid)
2394 {
2395 struct sk_buff *skb;
2396
2397 if (net_ratelimit())
2398 netif_warn(priv, hw, net_dev, "FD status = 0x%08x\n",
2399 be32_to_cpu(fd->status) & FM_FD_STAT_TX_ERRORS);
2400
2401 percpu_priv->stats.tx_errors++;
2402
2403 skb = dpaa_cleanup_tx_fd(priv, fd, false);
2404 dev_kfree_skb(skb);
2405 }
2406
dpaa_eth_poll(struct napi_struct * napi,int budget)2407 static int dpaa_eth_poll(struct napi_struct *napi, int budget)
2408 {
2409 struct dpaa_napi_portal *np =
2410 container_of(napi, struct dpaa_napi_portal, napi);
2411 int cleaned;
2412
2413 np->xdp_act = 0;
2414
2415 cleaned = qman_p_poll_dqrr(np->p, budget);
2416
2417 if (np->xdp_act & XDP_REDIRECT)
2418 xdp_do_flush();
2419
2420 if (cleaned < budget) {
2421 napi_complete_done(napi, cleaned);
2422 qman_p_irqsource_add(np->p, QM_PIRQ_DQRI);
2423 } else if (np->down) {
2424 qman_p_irqsource_add(np->p, QM_PIRQ_DQRI);
2425 }
2426
2427 return cleaned;
2428 }
2429
dpaa_tx_conf(struct net_device * net_dev,const struct dpaa_priv * priv,struct dpaa_percpu_priv * percpu_priv,const struct qm_fd * fd,u32 fqid)2430 static void dpaa_tx_conf(struct net_device *net_dev,
2431 const struct dpaa_priv *priv,
2432 struct dpaa_percpu_priv *percpu_priv,
2433 const struct qm_fd *fd,
2434 u32 fqid)
2435 {
2436 struct sk_buff *skb;
2437
2438 if (unlikely(be32_to_cpu(fd->status) & FM_FD_STAT_TX_ERRORS)) {
2439 if (net_ratelimit())
2440 netif_warn(priv, hw, net_dev, "FD status = 0x%08x\n",
2441 be32_to_cpu(fd->status) &
2442 FM_FD_STAT_TX_ERRORS);
2443
2444 percpu_priv->stats.tx_errors++;
2445 }
2446
2447 percpu_priv->tx_confirm++;
2448
2449 skb = dpaa_cleanup_tx_fd(priv, fd, true);
2450
2451 consume_skb(skb);
2452 }
2453
dpaa_eth_napi_schedule(struct dpaa_percpu_priv * percpu_priv,struct qman_portal * portal,bool sched_napi)2454 static inline int dpaa_eth_napi_schedule(struct dpaa_percpu_priv *percpu_priv,
2455 struct qman_portal *portal, bool sched_napi)
2456 {
2457 if (sched_napi) {
2458 /* Disable QMan IRQ and invoke NAPI */
2459 qman_p_irqsource_remove(portal, QM_PIRQ_DQRI);
2460
2461 percpu_priv->np.p = portal;
2462 napi_schedule(&percpu_priv->np.napi);
2463 percpu_priv->in_interrupt++;
2464 return 1;
2465 }
2466 return 0;
2467 }
2468
rx_error_dqrr(struct qman_portal * portal,struct qman_fq * fq,const struct qm_dqrr_entry * dq,bool sched_napi)2469 static enum qman_cb_dqrr_result rx_error_dqrr(struct qman_portal *portal,
2470 struct qman_fq *fq,
2471 const struct qm_dqrr_entry *dq,
2472 bool sched_napi)
2473 {
2474 struct dpaa_fq *dpaa_fq = container_of(fq, struct dpaa_fq, fq_base);
2475 struct dpaa_percpu_priv *percpu_priv;
2476 struct net_device *net_dev;
2477 struct dpaa_bp *dpaa_bp;
2478 struct dpaa_priv *priv;
2479
2480 net_dev = dpaa_fq->net_dev;
2481 priv = netdev_priv(net_dev);
2482 dpaa_bp = dpaa_bpid2pool(dq->fd.bpid);
2483 if (!dpaa_bp)
2484 return qman_cb_dqrr_consume;
2485
2486 percpu_priv = this_cpu_ptr(priv->percpu_priv);
2487
2488 if (dpaa_eth_napi_schedule(percpu_priv, portal, sched_napi))
2489 return qman_cb_dqrr_stop;
2490
2491 dpaa_eth_refill_bpools(priv);
2492 dpaa_rx_error(net_dev, priv, percpu_priv, &dq->fd, fq->fqid);
2493
2494 return qman_cb_dqrr_consume;
2495 }
2496
dpaa_xdp_xmit_frame(struct net_device * net_dev,struct xdp_frame * xdpf)2497 static int dpaa_xdp_xmit_frame(struct net_device *net_dev,
2498 struct xdp_frame *xdpf)
2499 {
2500 struct dpaa_priv *priv = netdev_priv(net_dev);
2501 struct rtnl_link_stats64 *percpu_stats;
2502 struct dpaa_percpu_priv *percpu_priv;
2503 struct dpaa_eth_swbp *swbp;
2504 struct netdev_queue *txq;
2505 void *buff_start;
2506 struct qm_fd fd;
2507 dma_addr_t addr;
2508 int err;
2509
2510 percpu_priv = this_cpu_ptr(priv->percpu_priv);
2511 percpu_stats = &percpu_priv->stats;
2512
2513 #ifdef CONFIG_DPAA_ERRATUM_A050385
2514 if (unlikely(fman_has_errata_a050385())) {
2515 if (dpaa_a050385_wa_xdpf(priv, &xdpf)) {
2516 err = -ENOMEM;
2517 goto out_error;
2518 }
2519 }
2520 #endif
2521
2522 if (xdpf->headroom < DPAA_TX_PRIV_DATA_SIZE) {
2523 err = -EINVAL;
2524 goto out_error;
2525 }
2526
2527 buff_start = xdpf->data - xdpf->headroom;
2528
2529 /* Leave empty the skb backpointer at the start of the buffer.
2530 * Save the XDP frame for easy cleanup on confirmation.
2531 */
2532 swbp = (struct dpaa_eth_swbp *)buff_start;
2533 swbp->skb = NULL;
2534 swbp->xdpf = xdpf;
2535
2536 qm_fd_clear_fd(&fd);
2537 fd.bpid = FSL_DPAA_BPID_INV;
2538 fd.cmd |= cpu_to_be32(FM_FD_CMD_FCO);
2539 qm_fd_set_contig(&fd, xdpf->headroom, xdpf->len);
2540
2541 addr = dma_map_single(priv->tx_dma_dev, buff_start,
2542 xdpf->headroom + xdpf->len,
2543 DMA_TO_DEVICE);
2544 if (unlikely(dma_mapping_error(priv->tx_dma_dev, addr))) {
2545 err = -EINVAL;
2546 goto out_error;
2547 }
2548
2549 qm_fd_addr_set64(&fd, addr);
2550
2551 /* Bump the trans_start */
2552 txq = netdev_get_tx_queue(net_dev, smp_processor_id());
2553 txq_trans_cond_update(txq);
2554
2555 err = dpaa_xmit(priv, percpu_stats, smp_processor_id(), &fd);
2556 if (err) {
2557 dma_unmap_single(priv->tx_dma_dev, addr,
2558 qm_fd_get_offset(&fd) + qm_fd_get_length(&fd),
2559 DMA_TO_DEVICE);
2560 goto out_error;
2561 }
2562
2563 return 0;
2564
2565 out_error:
2566 percpu_stats->tx_errors++;
2567 return err;
2568 }
2569
dpaa_run_xdp(struct dpaa_priv * priv,struct qm_fd * fd,void * vaddr,struct dpaa_fq * dpaa_fq,unsigned int * xdp_meta_len)2570 static u32 dpaa_run_xdp(struct dpaa_priv *priv, struct qm_fd *fd, void *vaddr,
2571 struct dpaa_fq *dpaa_fq, unsigned int *xdp_meta_len)
2572 {
2573 ssize_t fd_off = qm_fd_get_offset(fd);
2574 struct bpf_prog *xdp_prog;
2575 struct xdp_frame *xdpf;
2576 struct xdp_buff xdp;
2577 u32 xdp_act;
2578 int err;
2579
2580 xdp_prog = READ_ONCE(priv->xdp_prog);
2581 if (!xdp_prog)
2582 return XDP_PASS;
2583
2584 xdp_init_buff(&xdp, DPAA_BP_RAW_SIZE - DPAA_TX_PRIV_DATA_SIZE,
2585 &dpaa_fq->xdp_rxq);
2586 xdp_prepare_buff(&xdp, vaddr + fd_off - XDP_PACKET_HEADROOM,
2587 XDP_PACKET_HEADROOM, qm_fd_get_length(fd), true);
2588
2589 /* We reserve a fixed headroom of 256 bytes under the erratum and we
2590 * offer it all to XDP programs to use. If no room is left for the
2591 * xdpf backpointer on TX, we will need to copy the data.
2592 * Disable metadata support since data realignments might be required
2593 * and the information can be lost.
2594 */
2595 #ifdef CONFIG_DPAA_ERRATUM_A050385
2596 if (unlikely(fman_has_errata_a050385())) {
2597 xdp_set_data_meta_invalid(&xdp);
2598 xdp.data_hard_start = vaddr;
2599 xdp.frame_sz = DPAA_BP_RAW_SIZE;
2600 }
2601 #endif
2602
2603 xdp_act = bpf_prog_run_xdp(xdp_prog, &xdp);
2604
2605 /* Update the length and the offset of the FD */
2606 qm_fd_set_contig(fd, xdp.data - vaddr, xdp.data_end - xdp.data);
2607
2608 switch (xdp_act) {
2609 case XDP_PASS:
2610 #ifdef CONFIG_DPAA_ERRATUM_A050385
2611 *xdp_meta_len = xdp_data_meta_unsupported(&xdp) ? 0 :
2612 xdp.data - xdp.data_meta;
2613 #else
2614 *xdp_meta_len = xdp.data - xdp.data_meta;
2615 #endif
2616 break;
2617 case XDP_TX:
2618 /* We can access the full headroom when sending the frame
2619 * back out
2620 */
2621 xdp.data_hard_start = vaddr;
2622 xdp.frame_sz = DPAA_BP_RAW_SIZE;
2623 xdpf = xdp_convert_buff_to_frame(&xdp);
2624 if (unlikely(!xdpf)) {
2625 free_pages((unsigned long)vaddr, 0);
2626 break;
2627 }
2628
2629 if (dpaa_xdp_xmit_frame(priv->net_dev, xdpf))
2630 xdp_return_frame_rx_napi(xdpf);
2631
2632 break;
2633 case XDP_REDIRECT:
2634 /* Allow redirect to use the full headroom */
2635 xdp.data_hard_start = vaddr;
2636 xdp.frame_sz = DPAA_BP_RAW_SIZE;
2637
2638 err = xdp_do_redirect(priv->net_dev, &xdp, xdp_prog);
2639 if (err) {
2640 trace_xdp_exception(priv->net_dev, xdp_prog, xdp_act);
2641 free_pages((unsigned long)vaddr, 0);
2642 }
2643 break;
2644 default:
2645 bpf_warn_invalid_xdp_action(priv->net_dev, xdp_prog, xdp_act);
2646 fallthrough;
2647 case XDP_ABORTED:
2648 trace_xdp_exception(priv->net_dev, xdp_prog, xdp_act);
2649 fallthrough;
2650 case XDP_DROP:
2651 /* Free the buffer */
2652 free_pages((unsigned long)vaddr, 0);
2653 break;
2654 }
2655
2656 return xdp_act;
2657 }
2658
rx_default_dqrr(struct qman_portal * portal,struct qman_fq * fq,const struct qm_dqrr_entry * dq,bool sched_napi)2659 static enum qman_cb_dqrr_result rx_default_dqrr(struct qman_portal *portal,
2660 struct qman_fq *fq,
2661 const struct qm_dqrr_entry *dq,
2662 bool sched_napi)
2663 {
2664 bool ts_valid = false, hash_valid = false;
2665 struct skb_shared_hwtstamps *shhwtstamps;
2666 unsigned int skb_len, xdp_meta_len = 0;
2667 struct rtnl_link_stats64 *percpu_stats;
2668 struct dpaa_percpu_priv *percpu_priv;
2669 const struct qm_fd *fd = &dq->fd;
2670 dma_addr_t addr = qm_fd_addr(fd);
2671 struct dpaa_napi_portal *np;
2672 enum qm_fd_format fd_format;
2673 struct net_device *net_dev;
2674 u32 fd_status, hash_offset;
2675 struct qm_sg_entry *sgt;
2676 struct dpaa_bp *dpaa_bp;
2677 struct dpaa_fq *dpaa_fq;
2678 struct dpaa_priv *priv;
2679 struct sk_buff *skb;
2680 int *count_ptr;
2681 u32 xdp_act;
2682 void *vaddr;
2683 u32 hash;
2684 u64 ns;
2685
2686 dpaa_fq = container_of(fq, struct dpaa_fq, fq_base);
2687 fd_status = be32_to_cpu(fd->status);
2688 fd_format = qm_fd_get_format(fd);
2689 net_dev = dpaa_fq->net_dev;
2690 priv = netdev_priv(net_dev);
2691 dpaa_bp = dpaa_bpid2pool(dq->fd.bpid);
2692 if (!dpaa_bp)
2693 return qman_cb_dqrr_consume;
2694
2695 /* Trace the Rx fd */
2696 trace_dpaa_rx_fd(net_dev, fq, &dq->fd);
2697
2698 percpu_priv = this_cpu_ptr(priv->percpu_priv);
2699 percpu_stats = &percpu_priv->stats;
2700 np = &percpu_priv->np;
2701
2702 if (unlikely(dpaa_eth_napi_schedule(percpu_priv, portal, sched_napi)))
2703 return qman_cb_dqrr_stop;
2704
2705 /* Make sure we didn't run out of buffers */
2706 if (unlikely(dpaa_eth_refill_bpools(priv))) {
2707 /* Unable to refill the buffer pool due to insufficient
2708 * system memory. Just release the frame back into the pool,
2709 * otherwise we'll soon end up with an empty buffer pool.
2710 */
2711 dpaa_fd_release(net_dev, &dq->fd);
2712 return qman_cb_dqrr_consume;
2713 }
2714
2715 if (unlikely(fd_status & FM_FD_STAT_RX_ERRORS) != 0) {
2716 if (net_ratelimit())
2717 netif_warn(priv, hw, net_dev, "FD status = 0x%08x\n",
2718 fd_status & FM_FD_STAT_RX_ERRORS);
2719
2720 percpu_stats->rx_errors++;
2721 dpaa_fd_release(net_dev, fd);
2722 return qman_cb_dqrr_consume;
2723 }
2724
2725 dma_unmap_page(dpaa_bp->priv->rx_dma_dev, addr, DPAA_BP_RAW_SIZE,
2726 DMA_FROM_DEVICE);
2727
2728 /* prefetch the first 64 bytes of the frame or the SGT start */
2729 vaddr = phys_to_virt(addr);
2730 prefetch(vaddr + qm_fd_get_offset(fd));
2731
2732 /* The only FD types that we may receive are contig and S/G */
2733 WARN_ON((fd_format != qm_fd_contig) && (fd_format != qm_fd_sg));
2734
2735 /* Account for either the contig buffer or the SGT buffer (depending on
2736 * which case we were in) having been removed from the pool.
2737 */
2738 count_ptr = this_cpu_ptr(dpaa_bp->percpu_count);
2739 (*count_ptr)--;
2740
2741 /* Extract the timestamp stored in the headroom before running XDP */
2742 if (priv->rx_tstamp) {
2743 if (!fman_port_get_tstamp(priv->mac_dev->port[RX], vaddr, &ns))
2744 ts_valid = true;
2745 else
2746 WARN_ONCE(1, "fman_port_get_tstamp failed!\n");
2747 }
2748
2749 /* Extract the hash stored in the headroom before running XDP */
2750 if (net_dev->features & NETIF_F_RXHASH && priv->keygen_in_use &&
2751 !fman_port_get_hash_result_offset(priv->mac_dev->port[RX],
2752 &hash_offset)) {
2753 hash = be32_to_cpu(*(u32 *)(vaddr + hash_offset));
2754 hash_valid = true;
2755 }
2756
2757 if (likely(fd_format == qm_fd_contig)) {
2758 xdp_act = dpaa_run_xdp(priv, (struct qm_fd *)fd, vaddr,
2759 dpaa_fq, &xdp_meta_len);
2760 np->xdp_act |= xdp_act;
2761 if (xdp_act != XDP_PASS) {
2762 percpu_stats->rx_packets++;
2763 percpu_stats->rx_bytes += qm_fd_get_length(fd);
2764 return qman_cb_dqrr_consume;
2765 }
2766 skb = contig_fd_to_skb(priv, fd);
2767 } else {
2768 /* XDP doesn't support S/G frames. Return the fragments to the
2769 * buffer pool and release the SGT.
2770 */
2771 if (READ_ONCE(priv->xdp_prog)) {
2772 WARN_ONCE(1, "S/G frames not supported under XDP\n");
2773 sgt = vaddr + qm_fd_get_offset(fd);
2774 dpaa_release_sgt_members(sgt);
2775 free_pages((unsigned long)vaddr, 0);
2776 return qman_cb_dqrr_consume;
2777 }
2778 skb = sg_fd_to_skb(priv, fd);
2779 }
2780 if (!skb)
2781 return qman_cb_dqrr_consume;
2782
2783 if (xdp_meta_len)
2784 skb_metadata_set(skb, xdp_meta_len);
2785
2786 /* Set the previously extracted timestamp */
2787 if (ts_valid) {
2788 shhwtstamps = skb_hwtstamps(skb);
2789 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2790 shhwtstamps->hwtstamp = ns_to_ktime(ns);
2791 }
2792
2793 skb->protocol = eth_type_trans(skb, net_dev);
2794
2795 /* Set the previously extracted hash */
2796 if (hash_valid) {
2797 enum pkt_hash_types type;
2798
2799 /* if L4 exists, it was used in the hash generation */
2800 type = be32_to_cpu(fd->status) & FM_FD_STAT_L4CV ?
2801 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3;
2802 skb_set_hash(skb, hash, type);
2803 }
2804
2805 skb_len = skb->len;
2806
2807 if (unlikely(netif_receive_skb(skb) == NET_RX_DROP)) {
2808 percpu_stats->rx_dropped++;
2809 return qman_cb_dqrr_consume;
2810 }
2811
2812 percpu_stats->rx_packets++;
2813 percpu_stats->rx_bytes += skb_len;
2814
2815 return qman_cb_dqrr_consume;
2816 }
2817
conf_error_dqrr(struct qman_portal * portal,struct qman_fq * fq,const struct qm_dqrr_entry * dq,bool sched_napi)2818 static enum qman_cb_dqrr_result conf_error_dqrr(struct qman_portal *portal,
2819 struct qman_fq *fq,
2820 const struct qm_dqrr_entry *dq,
2821 bool sched_napi)
2822 {
2823 struct dpaa_percpu_priv *percpu_priv;
2824 struct net_device *net_dev;
2825 struct dpaa_priv *priv;
2826
2827 net_dev = ((struct dpaa_fq *)fq)->net_dev;
2828 priv = netdev_priv(net_dev);
2829
2830 percpu_priv = this_cpu_ptr(priv->percpu_priv);
2831
2832 if (dpaa_eth_napi_schedule(percpu_priv, portal, sched_napi))
2833 return qman_cb_dqrr_stop;
2834
2835 dpaa_tx_error(net_dev, priv, percpu_priv, &dq->fd, fq->fqid);
2836
2837 return qman_cb_dqrr_consume;
2838 }
2839
conf_dflt_dqrr(struct qman_portal * portal,struct qman_fq * fq,const struct qm_dqrr_entry * dq,bool sched_napi)2840 static enum qman_cb_dqrr_result conf_dflt_dqrr(struct qman_portal *portal,
2841 struct qman_fq *fq,
2842 const struct qm_dqrr_entry *dq,
2843 bool sched_napi)
2844 {
2845 struct dpaa_percpu_priv *percpu_priv;
2846 struct net_device *net_dev;
2847 struct dpaa_priv *priv;
2848
2849 net_dev = ((struct dpaa_fq *)fq)->net_dev;
2850 priv = netdev_priv(net_dev);
2851
2852 /* Trace the fd */
2853 trace_dpaa_tx_conf_fd(net_dev, fq, &dq->fd);
2854
2855 percpu_priv = this_cpu_ptr(priv->percpu_priv);
2856
2857 if (dpaa_eth_napi_schedule(percpu_priv, portal, sched_napi))
2858 return qman_cb_dqrr_stop;
2859
2860 dpaa_tx_conf(net_dev, priv, percpu_priv, &dq->fd, fq->fqid);
2861
2862 return qman_cb_dqrr_consume;
2863 }
2864
egress_ern(struct qman_portal * portal,struct qman_fq * fq,const union qm_mr_entry * msg)2865 static void egress_ern(struct qman_portal *portal,
2866 struct qman_fq *fq,
2867 const union qm_mr_entry *msg)
2868 {
2869 const struct qm_fd *fd = &msg->ern.fd;
2870 struct dpaa_percpu_priv *percpu_priv;
2871 const struct dpaa_priv *priv;
2872 struct net_device *net_dev;
2873 struct sk_buff *skb;
2874
2875 net_dev = ((struct dpaa_fq *)fq)->net_dev;
2876 priv = netdev_priv(net_dev);
2877 percpu_priv = this_cpu_ptr(priv->percpu_priv);
2878
2879 percpu_priv->stats.tx_dropped++;
2880 percpu_priv->stats.tx_fifo_errors++;
2881 count_ern(percpu_priv, msg);
2882
2883 skb = dpaa_cleanup_tx_fd(priv, fd, false);
2884 dev_kfree_skb_any(skb);
2885 }
2886
2887 static const struct dpaa_fq_cbs dpaa_fq_cbs = {
2888 .rx_defq = { .cb = { .dqrr = rx_default_dqrr } },
2889 .tx_defq = { .cb = { .dqrr = conf_dflt_dqrr } },
2890 .rx_errq = { .cb = { .dqrr = rx_error_dqrr } },
2891 .tx_errq = { .cb = { .dqrr = conf_error_dqrr } },
2892 .egress_ern = { .cb = { .ern = egress_ern } }
2893 };
2894
dpaa_eth_napi_enable(struct dpaa_priv * priv)2895 static void dpaa_eth_napi_enable(struct dpaa_priv *priv)
2896 {
2897 struct dpaa_percpu_priv *percpu_priv;
2898 int i;
2899
2900 for_each_online_cpu(i) {
2901 percpu_priv = per_cpu_ptr(priv->percpu_priv, i);
2902
2903 percpu_priv->np.down = false;
2904 napi_enable(&percpu_priv->np.napi);
2905 }
2906 }
2907
dpaa_eth_napi_disable(struct dpaa_priv * priv)2908 static void dpaa_eth_napi_disable(struct dpaa_priv *priv)
2909 {
2910 struct dpaa_percpu_priv *percpu_priv;
2911 int i;
2912
2913 for_each_online_cpu(i) {
2914 percpu_priv = per_cpu_ptr(priv->percpu_priv, i);
2915
2916 percpu_priv->np.down = true;
2917 napi_disable(&percpu_priv->np.napi);
2918 }
2919 }
2920
dpaa_open(struct net_device * net_dev)2921 static int dpaa_open(struct net_device *net_dev)
2922 {
2923 struct mac_device *mac_dev;
2924 struct dpaa_priv *priv;
2925 int err, i;
2926
2927 priv = netdev_priv(net_dev);
2928 mac_dev = priv->mac_dev;
2929 dpaa_eth_napi_enable(priv);
2930
2931 err = phylink_of_phy_connect(mac_dev->phylink,
2932 mac_dev->dev->of_node, 0);
2933 if (err)
2934 goto phy_init_failed;
2935
2936 for (i = 0; i < ARRAY_SIZE(mac_dev->port); i++) {
2937 err = fman_port_enable(mac_dev->port[i]);
2938 if (err)
2939 goto mac_start_failed;
2940 }
2941
2942 err = priv->mac_dev->enable(mac_dev->fman_mac);
2943 if (err < 0) {
2944 netif_err(priv, ifup, net_dev, "mac_dev->enable() = %d\n", err);
2945 goto mac_start_failed;
2946 }
2947 phylink_start(mac_dev->phylink);
2948
2949 netif_tx_start_all_queues(net_dev);
2950
2951 return 0;
2952
2953 mac_start_failed:
2954 for (i = 0; i < ARRAY_SIZE(mac_dev->port); i++)
2955 fman_port_disable(mac_dev->port[i]);
2956 phylink_disconnect_phy(mac_dev->phylink);
2957
2958 phy_init_failed:
2959 dpaa_eth_napi_disable(priv);
2960
2961 return err;
2962 }
2963
dpaa_eth_stop(struct net_device * net_dev)2964 static int dpaa_eth_stop(struct net_device *net_dev)
2965 {
2966 struct dpaa_priv *priv;
2967 int err;
2968
2969 err = dpaa_stop(net_dev);
2970
2971 priv = netdev_priv(net_dev);
2972 dpaa_eth_napi_disable(priv);
2973
2974 return err;
2975 }
2976
xdp_validate_mtu(struct dpaa_priv * priv,int mtu)2977 static bool xdp_validate_mtu(struct dpaa_priv *priv, int mtu)
2978 {
2979 int max_contig_data = priv->dpaa_bp->size - priv->rx_headroom;
2980
2981 /* We do not support S/G fragments when XDP is enabled.
2982 * Limit the MTU in relation to the buffer size.
2983 */
2984 if (mtu + VLAN_ETH_HLEN + ETH_FCS_LEN > max_contig_data) {
2985 dev_warn(priv->net_dev->dev.parent,
2986 "The maximum MTU for XDP is %d\n",
2987 max_contig_data - VLAN_ETH_HLEN - ETH_FCS_LEN);
2988 return false;
2989 }
2990
2991 return true;
2992 }
2993
dpaa_change_mtu(struct net_device * net_dev,int new_mtu)2994 static int dpaa_change_mtu(struct net_device *net_dev, int new_mtu)
2995 {
2996 struct dpaa_priv *priv = netdev_priv(net_dev);
2997
2998 if (priv->xdp_prog && !xdp_validate_mtu(priv, new_mtu))
2999 return -EINVAL;
3000
3001 WRITE_ONCE(net_dev->mtu, new_mtu);
3002 return 0;
3003 }
3004
dpaa_setup_xdp(struct net_device * net_dev,struct netdev_bpf * bpf)3005 static int dpaa_setup_xdp(struct net_device *net_dev, struct netdev_bpf *bpf)
3006 {
3007 struct dpaa_priv *priv = netdev_priv(net_dev);
3008 struct bpf_prog *old_prog;
3009 int err;
3010 bool up;
3011
3012 /* S/G fragments are not supported in XDP-mode */
3013 if (bpf->prog && !xdp_validate_mtu(priv, net_dev->mtu)) {
3014 NL_SET_ERR_MSG_MOD(bpf->extack, "MTU too large for XDP");
3015 return -EINVAL;
3016 }
3017
3018 up = netif_running(net_dev);
3019
3020 if (up)
3021 dpaa_eth_stop(net_dev);
3022
3023 old_prog = xchg(&priv->xdp_prog, bpf->prog);
3024 if (old_prog)
3025 bpf_prog_put(old_prog);
3026
3027 if (up) {
3028 err = dpaa_open(net_dev);
3029 if (err) {
3030 NL_SET_ERR_MSG_MOD(bpf->extack, "dpaa_open() failed");
3031 return err;
3032 }
3033 }
3034
3035 return 0;
3036 }
3037
dpaa_xdp(struct net_device * net_dev,struct netdev_bpf * xdp)3038 static int dpaa_xdp(struct net_device *net_dev, struct netdev_bpf *xdp)
3039 {
3040 switch (xdp->command) {
3041 case XDP_SETUP_PROG:
3042 return dpaa_setup_xdp(net_dev, xdp);
3043 default:
3044 return -EINVAL;
3045 }
3046 }
3047
dpaa_xdp_xmit(struct net_device * net_dev,int n,struct xdp_frame ** frames,u32 flags)3048 static int dpaa_xdp_xmit(struct net_device *net_dev, int n,
3049 struct xdp_frame **frames, u32 flags)
3050 {
3051 struct xdp_frame *xdpf;
3052 int i, nxmit = 0;
3053
3054 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
3055 return -EINVAL;
3056
3057 if (!netif_running(net_dev))
3058 return -ENETDOWN;
3059
3060 for (i = 0; i < n; i++) {
3061 xdpf = frames[i];
3062 if (dpaa_xdp_xmit_frame(net_dev, xdpf))
3063 break;
3064 nxmit++;
3065 }
3066
3067 return nxmit;
3068 }
3069
dpaa_ts_ioctl(struct net_device * dev,struct ifreq * rq,int cmd)3070 static int dpaa_ts_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3071 {
3072 struct dpaa_priv *priv = netdev_priv(dev);
3073 struct hwtstamp_config config;
3074
3075 if (copy_from_user(&config, rq->ifr_data, sizeof(config)))
3076 return -EFAULT;
3077
3078 switch (config.tx_type) {
3079 case HWTSTAMP_TX_OFF:
3080 /* Couldn't disable rx/tx timestamping separately.
3081 * Do nothing here.
3082 */
3083 priv->tx_tstamp = false;
3084 break;
3085 case HWTSTAMP_TX_ON:
3086 priv->mac_dev->set_tstamp(priv->mac_dev->fman_mac, true);
3087 priv->tx_tstamp = true;
3088 break;
3089 default:
3090 return -ERANGE;
3091 }
3092
3093 if (config.rx_filter == HWTSTAMP_FILTER_NONE) {
3094 /* Couldn't disable rx/tx timestamping separately.
3095 * Do nothing here.
3096 */
3097 priv->rx_tstamp = false;
3098 } else {
3099 priv->mac_dev->set_tstamp(priv->mac_dev->fman_mac, true);
3100 priv->rx_tstamp = true;
3101 /* TS is set for all frame types, not only those requested */
3102 config.rx_filter = HWTSTAMP_FILTER_ALL;
3103 }
3104
3105 return copy_to_user(rq->ifr_data, &config, sizeof(config)) ?
3106 -EFAULT : 0;
3107 }
3108
dpaa_ioctl(struct net_device * net_dev,struct ifreq * rq,int cmd)3109 static int dpaa_ioctl(struct net_device *net_dev, struct ifreq *rq, int cmd)
3110 {
3111 int ret = -EINVAL;
3112 struct dpaa_priv *priv = netdev_priv(net_dev);
3113
3114 if (cmd == SIOCGMIIREG) {
3115 if (net_dev->phydev)
3116 return phylink_mii_ioctl(priv->mac_dev->phylink, rq,
3117 cmd);
3118 }
3119
3120 if (cmd == SIOCSHWTSTAMP)
3121 return dpaa_ts_ioctl(net_dev, rq, cmd);
3122
3123 return ret;
3124 }
3125
3126 static const struct net_device_ops dpaa_ops = {
3127 .ndo_open = dpaa_open,
3128 .ndo_start_xmit = dpaa_start_xmit,
3129 .ndo_stop = dpaa_eth_stop,
3130 .ndo_tx_timeout = dpaa_tx_timeout,
3131 .ndo_get_stats64 = dpaa_get_stats64,
3132 .ndo_change_carrier = fixed_phy_change_carrier,
3133 .ndo_set_mac_address = dpaa_set_mac_address,
3134 .ndo_validate_addr = eth_validate_addr,
3135 .ndo_set_rx_mode = dpaa_set_rx_mode,
3136 .ndo_eth_ioctl = dpaa_ioctl,
3137 .ndo_setup_tc = dpaa_setup_tc,
3138 .ndo_change_mtu = dpaa_change_mtu,
3139 .ndo_bpf = dpaa_xdp,
3140 .ndo_xdp_xmit = dpaa_xdp_xmit,
3141 };
3142
dpaa_napi_add(struct net_device * net_dev)3143 static int dpaa_napi_add(struct net_device *net_dev)
3144 {
3145 struct dpaa_priv *priv = netdev_priv(net_dev);
3146 struct dpaa_percpu_priv *percpu_priv;
3147 int cpu;
3148
3149 for_each_possible_cpu(cpu) {
3150 percpu_priv = per_cpu_ptr(priv->percpu_priv, cpu);
3151
3152 netif_napi_add(net_dev, &percpu_priv->np.napi, dpaa_eth_poll);
3153 }
3154
3155 return 0;
3156 }
3157
dpaa_napi_del(struct net_device * net_dev)3158 static void dpaa_napi_del(struct net_device *net_dev)
3159 {
3160 struct dpaa_priv *priv = netdev_priv(net_dev);
3161 struct dpaa_percpu_priv *percpu_priv;
3162 int cpu;
3163
3164 for_each_possible_cpu(cpu) {
3165 percpu_priv = per_cpu_ptr(priv->percpu_priv, cpu);
3166
3167 __netif_napi_del(&percpu_priv->np.napi);
3168 }
3169 synchronize_net();
3170 }
3171
dpaa_bp_free_pf(const struct dpaa_bp * bp,struct bm_buffer * bmb)3172 static inline void dpaa_bp_free_pf(const struct dpaa_bp *bp,
3173 struct bm_buffer *bmb)
3174 {
3175 dma_addr_t addr = bm_buf_addr(bmb);
3176
3177 dma_unmap_page(bp->priv->rx_dma_dev, addr, DPAA_BP_RAW_SIZE,
3178 DMA_FROM_DEVICE);
3179
3180 skb_free_frag(phys_to_virt(addr));
3181 }
3182
3183 /* Alloc the dpaa_bp struct and configure default values */
dpaa_bp_alloc(struct device * dev)3184 static struct dpaa_bp *dpaa_bp_alloc(struct device *dev)
3185 {
3186 struct dpaa_bp *dpaa_bp;
3187
3188 dpaa_bp = devm_kzalloc(dev, sizeof(*dpaa_bp), GFP_KERNEL);
3189 if (!dpaa_bp)
3190 return ERR_PTR(-ENOMEM);
3191
3192 dpaa_bp->bpid = FSL_DPAA_BPID_INV;
3193 dpaa_bp->percpu_count = devm_alloc_percpu(dev, *dpaa_bp->percpu_count);
3194 if (!dpaa_bp->percpu_count)
3195 return ERR_PTR(-ENOMEM);
3196
3197 dpaa_bp->config_count = FSL_DPAA_ETH_MAX_BUF_COUNT;
3198
3199 dpaa_bp->seed_cb = dpaa_bp_seed;
3200 dpaa_bp->free_buf_cb = dpaa_bp_free_pf;
3201
3202 return dpaa_bp;
3203 }
3204
3205 /* Place all ingress FQs (Rx Default, Rx Error) in a dedicated CGR.
3206 * We won't be sending congestion notifications to FMan; for now, we just use
3207 * this CGR to generate enqueue rejections to FMan in order to drop the frames
3208 * before they reach our ingress queues and eat up memory.
3209 */
dpaa_ingress_cgr_init(struct dpaa_priv * priv)3210 static int dpaa_ingress_cgr_init(struct dpaa_priv *priv)
3211 {
3212 struct qm_mcc_initcgr initcgr;
3213 u32 cs_th;
3214 int err;
3215
3216 err = qman_alloc_cgrid(&priv->ingress_cgr.cgrid);
3217 if (err < 0) {
3218 if (netif_msg_drv(priv))
3219 pr_err("Error %d allocating CGR ID\n", err);
3220 goto out_error;
3221 }
3222
3223 /* Enable CS TD, but disable Congestion State Change Notifications. */
3224 memset(&initcgr, 0, sizeof(initcgr));
3225 initcgr.we_mask = cpu_to_be16(QM_CGR_WE_CS_THRES);
3226 initcgr.cgr.cscn_en = QM_CGR_EN;
3227 cs_th = DPAA_INGRESS_CS_THRESHOLD;
3228 qm_cgr_cs_thres_set64(&initcgr.cgr.cs_thres, cs_th, 1);
3229
3230 initcgr.we_mask |= cpu_to_be16(QM_CGR_WE_CSTD_EN);
3231 initcgr.cgr.cstd_en = QM_CGR_EN;
3232
3233 /* This CGR will be associated with the SWP affined to the current CPU.
3234 * However, we'll place all our ingress FQs in it.
3235 */
3236 err = qman_create_cgr(&priv->ingress_cgr, QMAN_CGR_FLAG_USE_INIT,
3237 &initcgr);
3238 if (err < 0) {
3239 if (netif_msg_drv(priv))
3240 pr_err("Error %d creating ingress CGR with ID %d\n",
3241 err, priv->ingress_cgr.cgrid);
3242 qman_release_cgrid(priv->ingress_cgr.cgrid);
3243 goto out_error;
3244 }
3245 if (netif_msg_drv(priv))
3246 pr_debug("Created ingress CGR %d for netdev with hwaddr %pM\n",
3247 priv->ingress_cgr.cgrid, priv->mac_dev->addr);
3248
3249 priv->use_ingress_cgr = true;
3250
3251 out_error:
3252 return err;
3253 }
3254
dpaa_get_headroom(struct dpaa_buffer_layout * bl,enum port_type port)3255 static u16 dpaa_get_headroom(struct dpaa_buffer_layout *bl,
3256 enum port_type port)
3257 {
3258 u16 headroom;
3259
3260 /* The frame headroom must accommodate:
3261 * - the driver private data area
3262 * - parse results, hash results, timestamp if selected
3263 * If either hash results or time stamp are selected, both will
3264 * be copied to/from the frame headroom, as TS is located between PR and
3265 * HR in the IC and IC copy size has a granularity of 16bytes
3266 * (see description of FMBM_RICP and FMBM_TICP registers in DPAARM)
3267 *
3268 * Also make sure the headroom is a multiple of data_align bytes
3269 */
3270 headroom = (u16)(bl[port].priv_data_size + DPAA_HWA_SIZE);
3271
3272 if (port == RX) {
3273 #ifdef CONFIG_DPAA_ERRATUM_A050385
3274 if (unlikely(fman_has_errata_a050385()))
3275 headroom = XDP_PACKET_HEADROOM;
3276 #endif
3277
3278 return ALIGN(headroom, DPAA_FD_RX_DATA_ALIGNMENT);
3279 } else {
3280 return ALIGN(headroom, DPAA_FD_DATA_ALIGNMENT);
3281 }
3282 }
3283
dpaa_eth_probe(struct platform_device * pdev)3284 static int dpaa_eth_probe(struct platform_device *pdev)
3285 {
3286 struct net_device *net_dev = NULL;
3287 struct dpaa_bp *dpaa_bp = NULL;
3288 struct dpaa_fq *dpaa_fq, *tmp;
3289 struct dpaa_priv *priv = NULL;
3290 struct fm_port_fqs port_fqs;
3291 struct mac_device *mac_dev;
3292 int err = 0, channel;
3293 struct device *dev;
3294
3295 dev = &pdev->dev;
3296
3297 err = bman_is_probed();
3298 if (!err)
3299 return -EPROBE_DEFER;
3300 if (err < 0) {
3301 dev_err(dev, "failing probe due to bman probe error\n");
3302 return -ENODEV;
3303 }
3304 err = qman_is_probed();
3305 if (!err)
3306 return -EPROBE_DEFER;
3307 if (err < 0) {
3308 dev_err(dev, "failing probe due to qman probe error\n");
3309 return -ENODEV;
3310 }
3311 err = bman_portals_probed();
3312 if (!err)
3313 return -EPROBE_DEFER;
3314 if (err < 0) {
3315 dev_err(dev,
3316 "failing probe due to bman portals probe error\n");
3317 return -ENODEV;
3318 }
3319 err = qman_portals_probed();
3320 if (!err)
3321 return -EPROBE_DEFER;
3322 if (err < 0) {
3323 dev_err(dev,
3324 "failing probe due to qman portals probe error\n");
3325 return -ENODEV;
3326 }
3327
3328 /* Allocate this early, so we can store relevant information in
3329 * the private area
3330 */
3331 net_dev = alloc_etherdev_mq(sizeof(*priv), dpaa_max_num_txqs());
3332 if (!net_dev) {
3333 dev_err(dev, "alloc_etherdev_mq() failed\n");
3334 return -ENOMEM;
3335 }
3336
3337 /* Do this here, so we can be verbose early */
3338 SET_NETDEV_DEV(net_dev, dev->parent);
3339 dev_set_drvdata(dev, net_dev);
3340
3341 priv = netdev_priv(net_dev);
3342 priv->net_dev = net_dev;
3343
3344 priv->msg_enable = netif_msg_init(debug, DPAA_MSG_DEFAULT);
3345
3346 priv->egress_fqs = devm_kcalloc(dev, dpaa_max_num_txqs(),
3347 sizeof(*priv->egress_fqs),
3348 GFP_KERNEL);
3349 if (!priv->egress_fqs) {
3350 err = -ENOMEM;
3351 goto free_netdev;
3352 }
3353
3354 priv->conf_fqs = devm_kcalloc(dev, dpaa_max_num_txqs(),
3355 sizeof(*priv->conf_fqs),
3356 GFP_KERNEL);
3357 if (!priv->conf_fqs) {
3358 err = -ENOMEM;
3359 goto free_netdev;
3360 }
3361
3362 mac_dev = dpaa_mac_dev_get(pdev);
3363 if (IS_ERR(mac_dev)) {
3364 netdev_err(net_dev, "dpaa_mac_dev_get() failed\n");
3365 err = PTR_ERR(mac_dev);
3366 goto free_netdev;
3367 }
3368
3369 /* Devices used for DMA mapping */
3370 priv->rx_dma_dev = fman_port_get_device(mac_dev->port[RX]);
3371 priv->tx_dma_dev = fman_port_get_device(mac_dev->port[TX]);
3372 err = dma_coerce_mask_and_coherent(priv->rx_dma_dev, DMA_BIT_MASK(40));
3373 if (!err)
3374 err = dma_coerce_mask_and_coherent(priv->tx_dma_dev,
3375 DMA_BIT_MASK(40));
3376 if (err) {
3377 netdev_err(net_dev, "dma_coerce_mask_and_coherent() failed\n");
3378 goto free_netdev;
3379 }
3380
3381 /* If fsl_fm_max_frm is set to a higher value than the all-common 1500,
3382 * we choose conservatively and let the user explicitly set a higher
3383 * MTU via ifconfig. Otherwise, the user may end up with different MTUs
3384 * in the same LAN.
3385 * If on the other hand fsl_fm_max_frm has been chosen below 1500,
3386 * start with the maximum allowed.
3387 */
3388 net_dev->mtu = min(dpaa_get_max_mtu(), ETH_DATA_LEN);
3389
3390 netdev_dbg(net_dev, "Setting initial MTU on net device: %d\n",
3391 net_dev->mtu);
3392
3393 priv->buf_layout[RX].priv_data_size = DPAA_RX_PRIV_DATA_SIZE; /* Rx */
3394 priv->buf_layout[TX].priv_data_size = DPAA_TX_PRIV_DATA_SIZE; /* Tx */
3395
3396 /* bp init */
3397 dpaa_bp = dpaa_bp_alloc(dev);
3398 if (IS_ERR(dpaa_bp)) {
3399 err = PTR_ERR(dpaa_bp);
3400 goto free_dpaa_bps;
3401 }
3402 /* the raw size of the buffers used for reception */
3403 dpaa_bp->raw_size = DPAA_BP_RAW_SIZE;
3404 /* avoid runtime computations by keeping the usable size here */
3405 dpaa_bp->size = dpaa_bp_size(dpaa_bp->raw_size);
3406 dpaa_bp->priv = priv;
3407
3408 err = dpaa_bp_alloc_pool(dpaa_bp);
3409 if (err < 0)
3410 goto free_dpaa_bps;
3411 priv->dpaa_bp = dpaa_bp;
3412
3413 INIT_LIST_HEAD(&priv->dpaa_fq_list);
3414
3415 memset(&port_fqs, 0, sizeof(port_fqs));
3416
3417 err = dpaa_alloc_all_fqs(dev, &priv->dpaa_fq_list, &port_fqs);
3418 if (err < 0) {
3419 dev_err(dev, "dpaa_alloc_all_fqs() failed\n");
3420 goto free_dpaa_bps;
3421 }
3422
3423 priv->mac_dev = mac_dev;
3424
3425 channel = dpaa_get_channel();
3426 if (channel < 0) {
3427 dev_err(dev, "dpaa_get_channel() failed\n");
3428 err = channel;
3429 goto free_dpaa_bps;
3430 }
3431
3432 priv->channel = (u16)channel;
3433
3434 /* Walk the CPUs with affine portals
3435 * and add this pool channel to each's dequeue mask.
3436 */
3437 dpaa_eth_add_channel(priv->channel, &pdev->dev);
3438
3439 err = dpaa_fq_setup(priv, &dpaa_fq_cbs, priv->mac_dev->port[TX]);
3440 if (err)
3441 goto free_dpaa_bps;
3442
3443 /* Create a congestion group for this netdev, with
3444 * dynamically-allocated CGR ID.
3445 * Must be executed after probing the MAC, but before
3446 * assigning the egress FQs to the CGRs.
3447 */
3448 err = dpaa_eth_cgr_init(priv);
3449 if (err < 0) {
3450 dev_err(dev, "Error initializing CGR\n");
3451 goto free_dpaa_bps;
3452 }
3453
3454 err = dpaa_ingress_cgr_init(priv);
3455 if (err < 0) {
3456 dev_err(dev, "Error initializing ingress CGR\n");
3457 goto delete_egress_cgr;
3458 }
3459
3460 /* Add the FQs to the interface, and make them active */
3461 list_for_each_entry_safe(dpaa_fq, tmp, &priv->dpaa_fq_list, list) {
3462 err = dpaa_fq_init(dpaa_fq, false);
3463 if (err < 0)
3464 goto free_dpaa_fqs;
3465 }
3466
3467 priv->tx_headroom = dpaa_get_headroom(priv->buf_layout, TX);
3468 priv->rx_headroom = dpaa_get_headroom(priv->buf_layout, RX);
3469
3470 /* All real interfaces need their ports initialized */
3471 err = dpaa_eth_init_ports(mac_dev, dpaa_bp, &port_fqs,
3472 &priv->buf_layout[0], dev);
3473 if (err)
3474 goto free_dpaa_fqs;
3475
3476 /* Rx traffic distribution based on keygen hashing defaults to on */
3477 priv->keygen_in_use = true;
3478
3479 priv->percpu_priv = devm_alloc_percpu(dev, *priv->percpu_priv);
3480 if (!priv->percpu_priv) {
3481 dev_err(dev, "devm_alloc_percpu() failed\n");
3482 err = -ENOMEM;
3483 goto free_dpaa_fqs;
3484 }
3485
3486 priv->num_tc = 1;
3487 netif_set_real_num_tx_queues(net_dev,
3488 priv->num_tc * dpaa_num_txqs_per_tc());
3489
3490 /* Initialize NAPI */
3491 err = dpaa_napi_add(net_dev);
3492 if (err < 0)
3493 goto delete_dpaa_napi;
3494
3495 err = dpaa_netdev_init(net_dev, &dpaa_ops, tx_timeout);
3496 if (err < 0)
3497 goto delete_dpaa_napi;
3498
3499 dpaa_eth_sysfs_init(&net_dev->dev);
3500
3501 netif_info(priv, probe, net_dev, "Probed interface %s\n",
3502 net_dev->name);
3503
3504 return 0;
3505
3506 delete_dpaa_napi:
3507 dpaa_napi_del(net_dev);
3508 free_dpaa_fqs:
3509 dpaa_fq_free(dev, &priv->dpaa_fq_list);
3510 qman_delete_cgr_safe(&priv->ingress_cgr);
3511 qman_release_cgrid(priv->ingress_cgr.cgrid);
3512 delete_egress_cgr:
3513 qman_delete_cgr_safe(&priv->cgr_data.cgr);
3514 qman_release_cgrid(priv->cgr_data.cgr.cgrid);
3515 free_dpaa_bps:
3516 dpaa_bps_free(priv);
3517 free_netdev:
3518 dev_set_drvdata(dev, NULL);
3519 free_netdev(net_dev);
3520
3521 return err;
3522 }
3523
dpaa_remove(struct platform_device * pdev)3524 static void dpaa_remove(struct platform_device *pdev)
3525 {
3526 struct net_device *net_dev;
3527 struct dpaa_priv *priv;
3528 struct device *dev;
3529 int err;
3530
3531 dev = &pdev->dev;
3532 net_dev = dev_get_drvdata(dev);
3533
3534 priv = netdev_priv(net_dev);
3535
3536 dpaa_eth_sysfs_remove(dev);
3537
3538 dev_set_drvdata(dev, NULL);
3539 unregister_netdev(net_dev);
3540 phylink_destroy(priv->mac_dev->phylink);
3541
3542 err = dpaa_fq_free(dev, &priv->dpaa_fq_list);
3543 if (err)
3544 dev_err(dev, "Failed to free FQs on remove (%pE)\n",
3545 ERR_PTR(err));
3546
3547 qman_delete_cgr_safe(&priv->ingress_cgr);
3548 qman_release_cgrid(priv->ingress_cgr.cgrid);
3549 qman_delete_cgr_safe(&priv->cgr_data.cgr);
3550 qman_release_cgrid(priv->cgr_data.cgr.cgrid);
3551
3552 dpaa_napi_del(net_dev);
3553
3554 dpaa_bps_free(priv);
3555
3556 free_netdev(net_dev);
3557 }
3558
3559 static const struct platform_device_id dpaa_devtype[] = {
3560 {
3561 .name = "dpaa-ethernet",
3562 .driver_data = 0,
3563 }, {
3564 }
3565 };
3566 MODULE_DEVICE_TABLE(platform, dpaa_devtype);
3567
3568 static struct platform_driver dpaa_driver = {
3569 .driver = {
3570 .name = KBUILD_MODNAME,
3571 },
3572 .id_table = dpaa_devtype,
3573 .probe = dpaa_eth_probe,
3574 .remove_new = dpaa_remove
3575 };
3576
dpaa_load(void)3577 static int __init dpaa_load(void)
3578 {
3579 int err;
3580
3581 pr_debug("FSL DPAA Ethernet driver\n");
3582
3583 /* initialize dpaa_eth mirror values */
3584 dpaa_rx_extra_headroom = fman_get_rx_extra_headroom();
3585 dpaa_max_frm = fman_get_max_frm();
3586
3587 err = platform_driver_register(&dpaa_driver);
3588 if (err < 0)
3589 pr_err("Error, platform_driver_register() = %d\n", err);
3590
3591 return err;
3592 }
3593 module_init(dpaa_load);
3594
dpaa_unload(void)3595 static void __exit dpaa_unload(void)
3596 {
3597 platform_driver_unregister(&dpaa_driver);
3598
3599 /* Only one channel is used and needs to be released after all
3600 * interfaces are removed
3601 */
3602 dpaa_release_channel();
3603 }
3604 module_exit(dpaa_unload);
3605
3606 MODULE_LICENSE("Dual BSD/GPL");
3607 MODULE_DESCRIPTION("FSL DPAA Ethernet driver");
3608