1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell RVU Admin Function driver
3 *
4 * Copyright (C) 2018 Marvell.
5 *
6 */
7
8 #ifndef RVU_H
9 #define RVU_H
10
11 #include <linux/pci.h>
12 #include <net/devlink.h>
13 #include <linux/soc/marvell/silicons.h>
14
15 #include "rvu_struct.h"
16 #include "rvu_devlink.h"
17 #include "common.h"
18 #include "mbox.h"
19 #include "npc.h"
20 #include "rvu_reg.h"
21 #include "ptp.h"
22
23 /* PCI device IDs */
24 #define PCI_DEVID_OCTEONTX2_RVU_AF 0xA065
25 #define PCI_DEVID_OCTEONTX2_LBK 0xA061
26
27 /* Subsystem Device ID */
28 #define PCI_SUBSYS_DEVID_98XX 0xB100
29 #define PCI_SUBSYS_DEVID_96XX 0xB200
30 #define PCI_SUBSYS_DEVID_CN10K_A 0xB900
31 #define PCI_SUBSYS_DEVID_CNF10K_A 0xBA00
32 #define PCI_SUBSYS_DEVID_CNF10K_B 0xBC00
33 #define PCI_SUBSYS_DEVID_CN10K_B 0xBD00
34 #define PCI_SUBSYS_DEVID_CN20KA 0xC220
35 #define PCI_SUBSYS_DEVID_CNF20KA 0xC320
36
37 /* PCI BAR nos */
38 #define PCI_AF_REG_BAR_NUM 0
39 #define PCI_PF_REG_BAR_NUM 2
40 #define PCI_MBOX_BAR_NUM 4
41
42 #define NAME_SIZE 32
43 #define MAX_NIX_BLKS 2
44 #define MAX_CPT_BLKS 2
45
46 /* PF_FUNC */
47 #define RVU_OTX2_PFVF_PF_SHIFT 10
48 #define RVU_OTX2_PFVF_PF_MASK 0x3F
49 #define RVU_PFVF_FUNC_SHIFT 0
50 #define RVU_PFVF_FUNC_MASK 0x3FF
51 #define RVU_CN20K_PFVF_PF_SHIFT 9
52 #define RVU_CN20K_PFVF_PF_MASK 0x7F
53
rvu_make_pcifunc(struct pci_dev * pdev,int pf,int func)54 static inline u16 rvu_make_pcifunc(struct pci_dev *pdev, int pf, int func)
55 {
56 if (is_cn20k(pdev))
57 return ((pf & RVU_CN20K_PFVF_PF_MASK) <<
58 RVU_CN20K_PFVF_PF_SHIFT) |
59 ((func & RVU_PFVF_FUNC_MASK) <<
60 RVU_PFVF_FUNC_SHIFT);
61 else
62 return ((pf & RVU_OTX2_PFVF_PF_MASK) <<
63 RVU_OTX2_PFVF_PF_SHIFT) |
64 ((func & RVU_PFVF_FUNC_MASK) <<
65 RVU_PFVF_FUNC_SHIFT);
66 }
67
rvu_pcifunc_pf_mask(struct pci_dev * pdev)68 static inline int rvu_pcifunc_pf_mask(struct pci_dev *pdev)
69 {
70 if (is_cn20k(pdev))
71 return ~(RVU_CN20K_PFVF_PF_MASK << RVU_CN20K_PFVF_PF_SHIFT);
72 else
73 return ~(RVU_OTX2_PFVF_PF_MASK << RVU_OTX2_PFVF_PF_SHIFT);
74 }
75
76 #define RVU_AFPF 25
77
78 #ifdef CONFIG_DEBUG_FS
79
80 struct dump_ctx {
81 int lf;
82 int id;
83 bool all;
84 };
85
86 struct cpt_ctx {
87 int blkaddr;
88 struct rvu *rvu;
89 };
90
91 struct rvu_debugfs {
92 struct dentry *root;
93 struct dentry *cgx_root;
94 struct dentry *cgx;
95 struct dentry *lmac;
96 struct dentry *npa;
97 struct dentry *nix;
98 struct dentry *npc;
99 struct dentry *cpt;
100 struct dentry *mcs_root;
101 struct dentry *mcs;
102 struct dentry *mcs_rx;
103 struct dentry *mcs_tx;
104 struct dump_ctx npa_aura_ctx;
105 struct dump_ctx npa_pool_ctx;
106 struct dump_ctx nix_cq_ctx;
107 struct dump_ctx nix_rq_ctx;
108 struct dump_ctx nix_sq_ctx;
109 struct dump_ctx nix_tm_ctx;
110 struct cpt_ctx cpt_ctx[MAX_CPT_BLKS];
111 int npa_qsize_id;
112 int nix_qsize_id;
113 };
114 #endif
115
116 struct rvu_work {
117 struct work_struct work;
118 struct rvu *rvu;
119 int num_msgs;
120 int up_num_msgs;
121 };
122
123 struct rsrc_bmap {
124 unsigned long *bmap; /* Pointer to resource bitmap */
125 u16 max; /* Max resource id or count */
126 };
127
128 struct rvu_block {
129 struct rsrc_bmap lf;
130 struct admin_queue *aq; /* NIX/NPA AQ */
131 u16 *fn_map; /* LF to pcifunc mapping */
132 bool multislot;
133 bool implemented;
134 u8 addr; /* RVU_BLOCK_ADDR_E */
135 u8 type; /* RVU_BLOCK_TYPE_E */
136 u8 lfshift;
137 u64 lookup_reg;
138 u64 pf_lfcnt_reg;
139 u64 vf_lfcnt_reg;
140 u64 lfcfg_reg;
141 u64 msixcfg_reg;
142 u64 lfreset_reg;
143 unsigned char name[NAME_SIZE];
144 struct rvu *rvu;
145 u64 cpt_flt_eng_map[3];
146 u64 cpt_rcvrd_eng_map[3];
147 };
148
149 struct nix_mcast {
150 struct qmem *mce_ctx;
151 struct qmem *mcast_buf;
152 int replay_pkind;
153 struct rsrc_bmap mce_counter[2];
154 /* Counters for both ingress and egress mcast lists */
155 struct mutex mce_lock; /* Serialize MCE updates */
156 };
157
158 struct nix_mce_list {
159 struct hlist_head head;
160 int count;
161 int max;
162 };
163
164 struct nix_mcast_grp_elem {
165 struct nix_mce_list mcast_mce_list;
166 u32 mcast_grp_idx;
167 u32 pcifunc;
168 int mcam_index;
169 int mce_start_index;
170 struct list_head list;
171 u8 dir;
172 };
173
174 struct nix_mcast_grp {
175 struct list_head mcast_grp_head;
176 int count;
177 int next_grp_index;
178 struct mutex mcast_grp_lock; /* Serialize MCE updates */
179 };
180
181 /* layer metadata to uniquely identify a packet header field */
182 struct npc_layer_mdata {
183 u8 lid;
184 u8 ltype;
185 u8 hdr;
186 u8 key;
187 u8 len;
188 };
189
190 /* Structure to represent a field present in the
191 * generated key. A key field may present anywhere and can
192 * be of any size in the generated key. Once this structure
193 * is populated for fields of interest then field's presence
194 * and location (if present) can be known.
195 */
196 struct npc_key_field {
197 /* Masks where all set bits indicate position
198 * of a field in the key
199 */
200 u64 kw_mask[NPC_MAX_KWS_IN_KEY];
201 /* Number of words in the key a field spans. If a field is
202 * of 16 bytes and key offset is 4 then the field will use
203 * 4 bytes in KW0, 8 bytes in KW1 and 4 bytes in KW2 and
204 * nr_kws will be 3(KW0, KW1 and KW2).
205 */
206 int nr_kws;
207 /* used by packet header fields */
208 struct npc_layer_mdata layer_mdata;
209 };
210
211 struct npc_mcam {
212 struct rsrc_bmap counters;
213 struct mutex lock; /* MCAM entries and counters update lock */
214 unsigned long *bmap; /* bitmap, 0 => bmap_entries */
215 unsigned long *bmap_reverse; /* Reverse bitmap, bmap_entries => 0 */
216 u16 bmap_entries; /* Number of unreserved MCAM entries */
217 u16 bmap_fcnt; /* MCAM entries free count */
218 u16 *entry2pfvf_map;
219 u16 *entry2cntr_map;
220 u16 *cntr2pfvf_map;
221 u16 *cntr_refcnt;
222 u16 *entry2target_pffunc;
223 u8 keysize; /* MCAM keysize 112/224/448 bits */
224 u8 banks; /* Number of MCAM banks */
225 u8 banks_per_entry;/* Number of keywords in key */
226 u16 banksize; /* Number of MCAM entries in each bank */
227 u16 total_entries; /* Total number of MCAM entries */
228 u16 nixlf_offset; /* Offset of nixlf rsvd uncast entries */
229 u16 pf_offset; /* Offset of PF's rsvd bcast, promisc entries */
230 u16 lprio_count;
231 u16 lprio_start;
232 u16 hprio_count;
233 u16 hprio_end;
234 u16 rx_miss_act_cntr; /* Counter for RX MISS action */
235 /* fields present in the generated key */
236 struct npc_key_field tx_key_fields[NPC_KEY_FIELDS_MAX];
237 struct npc_key_field rx_key_fields[NPC_KEY_FIELDS_MAX];
238 u64 tx_features;
239 u64 rx_features;
240 struct list_head mcam_rules;
241 };
242
243 /* Structure for per RVU func info ie PF/VF */
244 struct rvu_pfvf {
245 bool npalf; /* Only one NPALF per RVU_FUNC */
246 bool nixlf; /* Only one NIXLF per RVU_FUNC */
247 u16 sso;
248 u16 ssow;
249 u16 cptlfs;
250 u16 timlfs;
251 u16 cpt1_lfs;
252 u8 cgx_lmac;
253
254 /* Block LF's MSIX vector info */
255 struct rsrc_bmap msix; /* Bitmap for MSIX vector alloc */
256 #define MSIX_BLKLF(blkaddr, lf) (((blkaddr) << 8) | ((lf) & 0xFF))
257 u16 *msix_lfmap; /* Vector to block LF mapping */
258
259 /* NPA contexts */
260 struct qmem *aura_ctx;
261 struct qmem *pool_ctx;
262 struct qmem *npa_qints_ctx;
263 unsigned long *aura_bmap;
264 unsigned long *pool_bmap;
265
266 /* NIX contexts */
267 struct qmem *rq_ctx;
268 struct qmem *sq_ctx;
269 struct qmem *cq_ctx;
270 struct qmem *rss_ctx;
271 struct qmem *cq_ints_ctx;
272 struct qmem *nix_qints_ctx;
273 unsigned long *sq_bmap;
274 unsigned long *rq_bmap;
275 unsigned long *cq_bmap;
276
277 u16 rx_chan_base;
278 u16 tx_chan_base;
279 u8 rx_chan_cnt; /* total number of RX channels */
280 u8 tx_chan_cnt; /* total number of TX channels */
281 u16 maxlen;
282 u16 minlen;
283
284 bool hw_rx_tstamp_en; /* Is rx_tstamp enabled */
285 u8 mac_addr[ETH_ALEN]; /* MAC address of this PF/VF */
286 u8 default_mac[ETH_ALEN]; /* MAC address from FWdata */
287
288 /* Broadcast/Multicast/Promisc pkt replication info */
289 u16 bcast_mce_idx;
290 u16 mcast_mce_idx;
291 u16 promisc_mce_idx;
292 struct nix_mce_list bcast_mce_list;
293 struct nix_mce_list mcast_mce_list;
294 struct nix_mce_list promisc_mce_list;
295 bool use_mce_list;
296
297 struct rvu_npc_mcam_rule *def_ucast_rule;
298
299 bool cgx_in_use; /* this PF/VF using CGX? */
300 int cgx_users; /* number of cgx users - used only by PFs */
301
302 int intf_mode;
303 u8 nix_blkaddr; /* BLKADDR_NIX0/1 assigned to this PF */
304 u8 nix_rx_intf; /* NIX0_RX/NIX1_RX interface to NPC */
305 u8 nix_tx_intf; /* NIX0_TX/NIX1_TX interface to NPC */
306 u8 lbkid; /* NIX0/1 lbk link ID */
307 u64 lmt_base_addr; /* Preseving the pcifunc's lmtst base addr*/
308 u64 lmt_map_ent_w1; /* Preseving the word1 of lmtst map table entry*/
309 unsigned long flags;
310 struct sdp_node_info *sdp_info;
311 };
312
313 enum rvu_pfvf_flags {
314 NIXLF_INITIALIZED = 0,
315 PF_SET_VF_MAC,
316 PF_SET_VF_CFG,
317 PF_SET_VF_TRUSTED,
318 };
319
320 #define RVU_CLEAR_VF_PERM ~GENMASK(PF_SET_VF_TRUSTED, PF_SET_VF_MAC)
321
322 struct nix_bp {
323 struct rsrc_bmap bpids; /* free bpids bitmap */
324 u16 cgx_bpid_cnt;
325 u16 sdp_bpid_cnt;
326 u16 free_pool_base;
327 u16 *fn_map; /* pcifunc mapping */
328 u8 *intf_map; /* interface type map */
329 u8 *ref_cnt;
330 };
331
332 struct nix_txsch {
333 struct rsrc_bmap schq;
334 u8 lvl;
335 #define NIX_TXSCHQ_FREE BIT_ULL(1)
336 #define NIX_TXSCHQ_CFG_DONE BIT_ULL(0)
337 #define TXSCH_MAP_FUNC(__pfvf_map) ((__pfvf_map) & 0xFFFF)
338 #define TXSCH_MAP_FLAGS(__pfvf_map) ((__pfvf_map) >> 16)
339 #define TXSCH_MAP(__func, __flags) (((__func) & 0xFFFF) | ((__flags) << 16))
340 #define TXSCH_SET_FLAG(__pfvf_map, flag) ((__pfvf_map) | ((flag) << 16))
341 u32 *pfvf_map;
342 };
343
344 struct nix_mark_format {
345 u8 total;
346 u8 in_use;
347 u32 *cfg;
348 };
349
350 /* smq(flush) to tl1 cir/pir info */
351 struct nix_smq_tree_ctx {
352 u16 schq;
353 u64 cir_off;
354 u64 cir_val;
355 u64 pir_off;
356 u64 pir_val;
357 };
358
359 /* smq flush context */
360 struct nix_smq_flush_ctx {
361 int smq;
362 struct nix_smq_tree_ctx smq_tree_ctx[NIX_TXSCH_LVL_CNT];
363 };
364
365 struct npc_pkind {
366 struct rsrc_bmap rsrc;
367 u32 *pfchan_map;
368 };
369
370 struct nix_flowkey {
371 #define NIX_FLOW_KEY_ALG_MAX 32
372 u32 flowkey[NIX_FLOW_KEY_ALG_MAX];
373 int in_use;
374 };
375
376 struct nix_lso {
377 u8 total;
378 u8 in_use;
379 };
380
381 struct nix_txvlan {
382 #define NIX_TX_VTAG_DEF_MAX 0x400
383 struct rsrc_bmap rsrc;
384 u16 *entry2pfvf_map;
385 struct mutex rsrc_lock; /* Serialize resource alloc/free */
386 };
387
388 struct nix_ipolicer {
389 struct rsrc_bmap band_prof;
390 u16 *pfvf_map;
391 u16 *match_id;
392 u16 *ref_count;
393 };
394
395 struct nix_hw {
396 int blkaddr;
397 struct rvu *rvu;
398 struct nix_txsch txsch[NIX_TXSCH_LVL_CNT]; /* Tx schedulers */
399 struct nix_mcast mcast;
400 struct nix_mcast_grp mcast_grp;
401 struct nix_flowkey flowkey;
402 struct nix_mark_format mark_format;
403 struct nix_lso lso;
404 struct nix_txvlan txvlan;
405 struct nix_ipolicer *ipolicer;
406 struct nix_bp bp;
407 u64 *tx_credits;
408 u8 cc_mcs_cnt;
409 };
410
411 /* RVU block's capabilities or functionality,
412 * which vary by silicon version/skew.
413 */
414 struct hw_cap {
415 /* Transmit side supported functionality */
416 u8 nix_tx_aggr_lvl; /* Tx link's traffic aggregation level */
417 u16 nix_txsch_per_cgx_lmac; /* Max Q's transmitting to CGX LMAC */
418 u16 nix_txsch_per_lbk_lmac; /* Max Q's transmitting to LBK LMAC */
419 u16 nix_txsch_per_sdp_lmac; /* Max Q's transmitting to SDP LMAC */
420 bool nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */
421 bool nix_shaping; /* Is shaping and coloring supported */
422 bool nix_shaper_toggle_wait; /* Shaping toggle needs poll/wait */
423 bool nix_tx_link_bp; /* Can link backpressure TL queues ? */
424 bool nix_rx_multicast; /* Rx packet replication support */
425 bool nix_common_dwrr_mtu; /* Common DWRR MTU for quantum config */
426 bool per_pf_mbox_regs; /* PF mbox specified in per PF registers ? */
427 bool programmable_chans; /* Channels programmable ? */
428 bool ipolicer;
429 bool nix_multiple_dwrr_mtu; /* Multiple DWRR_MTU to choose from */
430 bool npc_hash_extract; /* Hash extract enabled ? */
431 bool npc_exact_match_enabled; /* Exact match supported ? */
432 bool cpt_rxc; /* Is CPT-RXC supported */
433 };
434
435 struct rvu_hwinfo {
436 u8 total_pfs; /* MAX RVU PFs HW supports */
437 u16 total_vfs; /* Max RVU VFs HW supports */
438 u16 max_vfs_per_pf; /* Max VFs that can be attached to a PF */
439 u8 cgx;
440 u8 lmac_per_cgx;
441 u16 cgx_chan_base; /* CGX base channel number */
442 u16 lbk_chan_base; /* LBK base channel number */
443 u16 sdp_chan_base; /* SDP base channel number */
444 u16 cpt_chan_base; /* CPT base channel number */
445 u8 cgx_links;
446 u8 lbk_links;
447 u8 sdp_links;
448 u8 cpt_links; /* Number of CPT links */
449 u8 npc_kpus; /* No of parser units */
450 u8 npc_pkinds; /* No of port kinds */
451 u8 npc_intfs; /* No of interfaces */
452 u8 npc_kpu_entries; /* No of KPU entries */
453 u16 npc_counters; /* No of match stats counters */
454 u32 lbk_bufsize; /* FIFO size supported by LBK */
455 bool npc_ext_set; /* Extended register set */
456 u64 npc_stat_ena; /* Match stats enable bit */
457
458 struct hw_cap cap;
459 struct rvu_block block[BLK_COUNT]; /* Block info */
460 struct nix_hw *nix;
461 struct rvu *rvu;
462 struct npc_pkind pkind;
463 struct npc_mcam mcam;
464 struct npc_exact_table *table;
465 };
466
467 struct mbox_wq_info {
468 struct otx2_mbox mbox;
469 struct rvu_work *mbox_wrk;
470
471 struct otx2_mbox mbox_up;
472 struct rvu_work *mbox_wrk_up;
473
474 struct workqueue_struct *mbox_wq;
475 };
476
477 struct rvu_irq_data {
478 u64 intr_status;
479 void (*rvu_queue_work_hdlr)(struct mbox_wq_info *mw, int first,
480 int mdevs, u64 intr);
481 void (*afvf_queue_work_hdlr)(struct mbox_wq_info *mw, int first,
482 int mdevs, u64 intr);
483 struct rvu *rvu;
484 int vec_num;
485 int start;
486 int mdevs;
487 };
488
489 struct mbox_ops {
490 irqreturn_t (*pf_intr_handler)(int irq, void *rvu_irq);
491 irqreturn_t (*afvf_intr_handler)(int irq, void *rvu_irq);
492 };
493
494 struct channel_fwdata {
495 struct sdp_node_info info;
496 u8 valid;
497 #define RVU_CHANL_INFO_RESERVED 379
498 u8 reserved[RVU_CHANL_INFO_RESERVED];
499 };
500
501 struct rvu_fwdata {
502 #define RVU_FWDATA_HEADER_MAGIC 0xCFDA /* Custom Firmware Data*/
503 #define RVU_FWDATA_VERSION 0x0001
504 u32 header_magic;
505 u32 version; /* version id */
506
507 /* MAC address */
508 #define PF_MACNUM_MAX 32
509 #define VF_MACNUM_MAX 256
510 u64 pf_macs[PF_MACNUM_MAX];
511 u64 vf_macs[VF_MACNUM_MAX];
512 u64 sclk;
513 u64 rclk;
514 u64 mcam_addr;
515 u64 mcam_sz;
516 u64 msixtr_base;
517 u32 ptp_ext_clk_rate;
518 u32 ptp_ext_tstamp;
519 struct channel_fwdata channel_data;
520 #define FWDATA_RESERVED_MEM 958
521 u64 reserved[FWDATA_RESERVED_MEM];
522 #define CGX_MAX 9
523 #define CGX_LMACS_MAX 4
524 #define CGX_LMACS_USX 8
525 #define FWDATA_CGX_LMAC_OFFSET 10536
526 union {
527 struct cgx_lmac_fwdata_s
528 cgx_fw_data[CGX_MAX][CGX_LMACS_MAX];
529 struct cgx_lmac_fwdata_s
530 cgx_fw_data_usx[CGX_MAX][CGX_LMACS_USX];
531 };
532 /* Do not add new fields below this line */
533 };
534
535 struct ptp;
536
537 /* KPU profile adapter structure gathering all KPU configuration data and abstracting out the
538 * source where it came from.
539 */
540 struct npc_kpu_profile_adapter {
541 const char *name;
542 u64 version;
543 const struct npc_lt_def_cfg *lt_def;
544 const struct npc_kpu_profile_action *ikpu; /* array[pkinds] */
545 const struct npc_kpu_profile *kpu; /* array[kpus] */
546 struct npc_mcam_kex *mkex;
547 struct npc_mcam_kex_hash *mkex_hash;
548 bool custom;
549 size_t pkinds;
550 size_t kpus;
551 };
552
553 #define RVU_SWITCH_LBK_CHAN 63
554
555 struct rvu_switch {
556 struct mutex switch_lock; /* Serialize flow installation */
557 u32 used_entries;
558 u16 *entry2pcifunc;
559 u16 mode;
560 u16 start_entry;
561 };
562
563 struct rep_evtq_ent {
564 struct list_head node;
565 struct rep_event event;
566 };
567
568 struct rvu {
569 void __iomem *afreg_base;
570 void __iomem *pfreg_base;
571 struct pci_dev *pdev;
572 struct device *dev;
573 struct rvu_hwinfo *hw;
574 struct rvu_pfvf *pf;
575 struct rvu_pfvf *hwvf;
576 struct mutex rsrc_lock; /* Serialize resource alloc/free */
577 struct mutex alias_lock; /* Serialize bar2 alias access */
578 int vfs; /* Number of VFs attached to RVU */
579 u16 vf_devid; /* VF devices id */
580 bool def_rule_cntr_en;
581 int nix_blkaddr[MAX_NIX_BLKS];
582
583 /* Mbox */
584 struct mbox_wq_info afpf_wq_info;
585 struct mbox_wq_info afvf_wq_info;
586
587 /* PF FLR */
588 struct rvu_work *flr_wrk;
589 struct workqueue_struct *flr_wq;
590 struct mutex flr_lock; /* Serialize FLRs */
591
592 /* MSI-X */
593 u16 num_vec;
594 char *irq_name;
595 bool *irq_allocated;
596 dma_addr_t msix_base_iova;
597 u64 msixtr_base_phy; /* Register reset value */
598
599 /* CGX */
600 #define PF_CGXMAP_BASE 1 /* PF 0 is reserved for RVU PF */
601 u16 cgx_mapped_vfs; /* maximum CGX mapped VFs */
602 u8 cgx_mapped_pfs;
603 u8 cgx_cnt_max; /* CGX port count max */
604 u8 *pf2cgxlmac_map; /* pf to cgx_lmac map */
605 u64 *cgxlmac2pf_map; /* bitmap of mapped pfs for
606 * every cgx lmac port
607 */
608 unsigned long pf_notify_bmap; /* Flags for PF notification */
609 void **cgx_idmap; /* cgx id to cgx data map table */
610 struct work_struct cgx_evh_work;
611 struct workqueue_struct *cgx_evh_wq;
612 spinlock_t cgx_evq_lock; /* cgx event queue lock */
613 struct list_head cgx_evq_head; /* cgx event queue head */
614 struct mutex cgx_cfg_lock; /* serialize cgx configuration */
615
616 char mkex_pfl_name[MKEX_NAME_LEN]; /* Configured MKEX profile name */
617 char kpu_pfl_name[KPU_NAME_LEN]; /* Configured KPU profile name */
618
619 /* Firmware data */
620 struct rvu_fwdata *fwdata;
621 void *kpu_fwdata;
622 size_t kpu_fwdata_sz;
623 void __iomem *kpu_prfl_addr;
624
625 /* NPC KPU data */
626 struct npc_kpu_profile_adapter kpu;
627
628 struct ptp *ptp;
629
630 int mcs_blk_cnt;
631 int cpt_pf_num;
632
633 #ifdef CONFIG_DEBUG_FS
634 struct rvu_debugfs rvu_dbg;
635 #endif
636 struct rvu_devlink *rvu_dl;
637
638 /* RVU switch implementation over NPC with DMAC rules */
639 struct rvu_switch rswitch;
640
641 struct work_struct mcs_intr_work;
642 struct workqueue_struct *mcs_intr_wq;
643 struct list_head mcs_intrq_head;
644 /* mcs interrupt queue lock */
645 spinlock_t mcs_intrq_lock;
646 /* CPT interrupt lock */
647 spinlock_t cpt_intr_lock;
648
649 struct mutex mbox_lock; /* Serialize mbox up and down msgs */
650 u16 rep_pcifunc;
651 int rep_cnt;
652 u16 *rep2pfvf_map;
653 u8 rep_mode;
654 struct work_struct rep_evt_work;
655 struct workqueue_struct *rep_evt_wq;
656 struct list_head rep_evtq_head;
657 /* Representor event lock */
658 spinlock_t rep_evtq_lock;
659
660 struct ng_rvu *ng_rvu;
661 };
662
rvu_write64(struct rvu * rvu,u64 block,u64 offset,u64 val)663 static inline void rvu_write64(struct rvu *rvu, u64 block, u64 offset, u64 val)
664 {
665 writeq(val, rvu->afreg_base + ((block << 28) | offset));
666 }
667
rvu_read64(struct rvu * rvu,u64 block,u64 offset)668 static inline u64 rvu_read64(struct rvu *rvu, u64 block, u64 offset)
669 {
670 return readq(rvu->afreg_base + ((block << 28) | offset));
671 }
672
rvupf_write64(struct rvu * rvu,u64 offset,u64 val)673 static inline void rvupf_write64(struct rvu *rvu, u64 offset, u64 val)
674 {
675 writeq(val, rvu->pfreg_base + offset);
676 }
677
rvupf_read64(struct rvu * rvu,u64 offset)678 static inline u64 rvupf_read64(struct rvu *rvu, u64 offset)
679 {
680 return readq(rvu->pfreg_base + offset);
681 }
682
rvu_bar2_sel_write64(struct rvu * rvu,u64 block,u64 offset,u64 val)683 static inline void rvu_bar2_sel_write64(struct rvu *rvu, u64 block, u64 offset, u64 val)
684 {
685 /* HW requires read back of RVU_AF_BAR2_SEL register to make sure completion of
686 * write operation.
687 */
688 rvu_write64(rvu, block, offset, val);
689 rvu_read64(rvu, block, offset);
690 /* Barrier to ensure read completes before accessing LF registers */
691 mb();
692 }
693
694 /* Silicon revisions */
is_rvu_pre_96xx_C0(struct rvu * rvu)695 static inline bool is_rvu_pre_96xx_C0(struct rvu *rvu)
696 {
697 struct pci_dev *pdev = rvu->pdev;
698 /* 96XX A0/B0, 95XX A0/A1/B0 chips */
699 return ((pdev->revision == 0x00) || (pdev->revision == 0x01) ||
700 (pdev->revision == 0x10) || (pdev->revision == 0x11) ||
701 (pdev->revision == 0x14));
702 }
703
is_rvu_96xx_A0(struct rvu * rvu)704 static inline bool is_rvu_96xx_A0(struct rvu *rvu)
705 {
706 struct pci_dev *pdev = rvu->pdev;
707
708 return (pdev->revision == 0x00);
709 }
710
is_rvu_96xx_B0(struct rvu * rvu)711 static inline bool is_rvu_96xx_B0(struct rvu *rvu)
712 {
713 struct pci_dev *pdev = rvu->pdev;
714
715 return (pdev->revision == 0x00) || (pdev->revision == 0x01);
716 }
717
is_rvu_95xx_A0(struct rvu * rvu)718 static inline bool is_rvu_95xx_A0(struct rvu *rvu)
719 {
720 struct pci_dev *pdev = rvu->pdev;
721
722 return (pdev->revision == 0x10) || (pdev->revision == 0x11);
723 }
724
725 /* REVID for PCIe devices.
726 * Bits 0..1: minor pass, bit 3..2: major pass
727 * bits 7..4: midr id
728 */
729 #define PCI_REVISION_ID_96XX 0x00
730 #define PCI_REVISION_ID_95XX 0x10
731 #define PCI_REVISION_ID_95XXN 0x20
732 #define PCI_REVISION_ID_98XX 0x30
733 #define PCI_REVISION_ID_95XXMM 0x40
734 #define PCI_REVISION_ID_95XXO 0xE0
735
is_rvu_otx2(struct rvu * rvu)736 static inline bool is_rvu_otx2(struct rvu *rvu)
737 {
738 struct pci_dev *pdev = rvu->pdev;
739
740 u8 midr = pdev->revision & 0xF0;
741
742 return (midr == PCI_REVISION_ID_96XX || midr == PCI_REVISION_ID_95XX ||
743 midr == PCI_REVISION_ID_95XXN || midr == PCI_REVISION_ID_98XX ||
744 midr == PCI_REVISION_ID_95XXMM || midr == PCI_REVISION_ID_95XXO);
745 }
746
is_cnf10ka_a0(struct rvu * rvu)747 static inline bool is_cnf10ka_a0(struct rvu *rvu)
748 {
749 struct pci_dev *pdev = rvu->pdev;
750
751 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_CNF10K_A &&
752 (pdev->revision & 0x0F) == 0x0)
753 return true;
754 return false;
755 }
756
is_cn10ka_a0(struct rvu * rvu)757 static inline bool is_cn10ka_a0(struct rvu *rvu)
758 {
759 struct pci_dev *pdev = rvu->pdev;
760
761 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_CN10K_A &&
762 (pdev->revision & 0x0F) == 0x0)
763 return true;
764 return false;
765 }
766
is_cn10ka_a1(struct rvu * rvu)767 static inline bool is_cn10ka_a1(struct rvu *rvu)
768 {
769 struct pci_dev *pdev = rvu->pdev;
770
771 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_CN10K_A &&
772 (pdev->revision & 0x0F) == 0x1)
773 return true;
774 return false;
775 }
776
is_cn10kb(struct rvu * rvu)777 static inline bool is_cn10kb(struct rvu *rvu)
778 {
779 struct pci_dev *pdev = rvu->pdev;
780
781 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_CN10K_B)
782 return true;
783 return false;
784 }
785
is_rvu_npc_hash_extract_en(struct rvu * rvu)786 static inline bool is_rvu_npc_hash_extract_en(struct rvu *rvu)
787 {
788 u64 npc_const3;
789
790 npc_const3 = rvu_read64(rvu, BLKADDR_NPC, NPC_AF_CONST3);
791 if (!(npc_const3 & BIT_ULL(62)))
792 return false;
793
794 return true;
795 }
796
rvu_nix_chan_cgx(struct rvu * rvu,u8 cgxid,u8 lmacid,u8 chan)797 static inline u16 rvu_nix_chan_cgx(struct rvu *rvu, u8 cgxid,
798 u8 lmacid, u8 chan)
799 {
800 u64 nix_const = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST);
801 u16 cgx_chans = nix_const & 0xFFULL;
802 struct rvu_hwinfo *hw = rvu->hw;
803
804 if (!hw->cap.programmable_chans)
805 return NIX_CHAN_CGX_LMAC_CHX(cgxid, lmacid, chan);
806
807 return rvu->hw->cgx_chan_base +
808 (cgxid * hw->lmac_per_cgx + lmacid) * cgx_chans + chan;
809 }
810
rvu_nix_chan_lbk(struct rvu * rvu,u8 lbkid,u8 chan)811 static inline u16 rvu_nix_chan_lbk(struct rvu *rvu, u8 lbkid,
812 u8 chan)
813 {
814 u64 nix_const = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST);
815 u16 lbk_chans = (nix_const >> 16) & 0xFFULL;
816 struct rvu_hwinfo *hw = rvu->hw;
817
818 if (!hw->cap.programmable_chans)
819 return NIX_CHAN_LBK_CHX(lbkid, chan);
820
821 return rvu->hw->lbk_chan_base + lbkid * lbk_chans + chan;
822 }
823
rvu_nix_chan_sdp(struct rvu * rvu,u8 chan)824 static inline u16 rvu_nix_chan_sdp(struct rvu *rvu, u8 chan)
825 {
826 struct rvu_hwinfo *hw = rvu->hw;
827
828 if (!hw->cap.programmable_chans)
829 return NIX_CHAN_SDP_CHX(chan);
830
831 return hw->sdp_chan_base + chan;
832 }
833
rvu_nix_chan_cpt(struct rvu * rvu,u8 chan)834 static inline u16 rvu_nix_chan_cpt(struct rvu *rvu, u8 chan)
835 {
836 return rvu->hw->cpt_chan_base + chan;
837 }
838
is_rvu_supports_nix1(struct rvu * rvu)839 static inline bool is_rvu_supports_nix1(struct rvu *rvu)
840 {
841 struct pci_dev *pdev = rvu->pdev;
842
843 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_98XX)
844 return true;
845
846 return false;
847 }
848
849 /* Function Prototypes
850 * RVU
851 */
852 #define RVU_LBK_VF_DEVID 0xA0F8
is_lbk_vf(struct rvu * rvu,u16 pcifunc)853 static inline bool is_lbk_vf(struct rvu *rvu, u16 pcifunc)
854 {
855 return (!(pcifunc & ~RVU_PFVF_FUNC_MASK) &&
856 (rvu->vf_devid == RVU_LBK_VF_DEVID));
857 }
858
is_vf(u16 pcifunc)859 static inline bool is_vf(u16 pcifunc)
860 {
861 return !!(pcifunc & RVU_PFVF_FUNC_MASK);
862 }
863
864 /* check if PF_FUNC is AF */
is_pffunc_af(u16 pcifunc)865 static inline bool is_pffunc_af(u16 pcifunc)
866 {
867 return !pcifunc;
868 }
869
is_rvu_fwdata_valid(struct rvu * rvu)870 static inline bool is_rvu_fwdata_valid(struct rvu *rvu)
871 {
872 return (rvu->fwdata->header_magic == RVU_FWDATA_HEADER_MAGIC) &&
873 (rvu->fwdata->version == RVU_FWDATA_VERSION);
874 }
875
876 int rvu_alloc_bitmap(struct rsrc_bmap *rsrc);
877 void rvu_free_bitmap(struct rsrc_bmap *rsrc);
878 int rvu_alloc_rsrc(struct rsrc_bmap *rsrc);
879 void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id);
880 bool is_rsrc_free(struct rsrc_bmap *rsrc, int id);
881 int rvu_rsrc_free_count(struct rsrc_bmap *rsrc);
882 int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc);
883 void rvu_free_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc, int start);
884 bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc);
885 u16 rvu_get_rsrc_mapcount(struct rvu_pfvf *pfvf, int blkaddr);
886 struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc);
887 void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf);
888 bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr);
889 bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype);
890 int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot);
891 int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf);
892 int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc);
893 int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero);
894 int rvu_get_num_lbk_chans(void);
895 int rvu_ndc_sync(struct rvu *rvu, int lfblkid, int lfidx, u64 lfoffset);
896 int rvu_get_blkaddr_from_slot(struct rvu *rvu, int blktype, u16 pcifunc,
897 u16 global_slot, u16 *slot_in_block);
898
899 /* RVU HW reg validation */
900 enum regmap_block {
901 TXSCHQ_HWREGMAP = 0,
902 MAX_HWREGMAP,
903 };
904
905 bool rvu_check_valid_reg(int regmap, int regblk, u64 reg);
906
907 /* NPA/NIX AQ APIs */
908 int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue,
909 int qsize, int inst_size, int res_size);
910 void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq);
911
912 /* SDP APIs */
913 int rvu_sdp_init(struct rvu *rvu);
914 bool is_sdp_pfvf(struct rvu *rvu, u16 pcifunc);
915 bool is_sdp_pf(struct rvu *rvu, u16 pcifunc);
916 bool is_sdp_vf(struct rvu *rvu, u16 pcifunc);
917
is_rep_dev(struct rvu * rvu,u16 pcifunc)918 static inline bool is_rep_dev(struct rvu *rvu, u16 pcifunc)
919 {
920 if (rvu->rep_pcifunc && rvu->rep_pcifunc == pcifunc)
921 return true;
922
923 return false;
924 }
925
rvu_get_pf(struct pci_dev * pdev,u16 pcifunc)926 static inline int rvu_get_pf(struct pci_dev *pdev, u16 pcifunc)
927 {
928 if (is_cn20k(pdev))
929 return (pcifunc >> RVU_CN20K_PFVF_PF_SHIFT) &
930 RVU_CN20K_PFVF_PF_MASK;
931 else
932 return (pcifunc >> RVU_OTX2_PFVF_PF_SHIFT) &
933 RVU_OTX2_PFVF_PF_MASK;
934 }
935
936 /* CGX APIs */
is_pf_cgxmapped(struct rvu * rvu,u8 pf)937 static inline bool is_pf_cgxmapped(struct rvu *rvu, u8 pf)
938 {
939 return (pf >= PF_CGXMAP_BASE && pf <= rvu->cgx_mapped_pfs) &&
940 !is_sdp_pf(rvu, rvu_make_pcifunc(rvu->pdev, pf, 0));
941 }
942
rvu_get_cgx_lmac_id(u8 map,u8 * cgx_id,u8 * lmac_id)943 static inline void rvu_get_cgx_lmac_id(u8 map, u8 *cgx_id, u8 *lmac_id)
944 {
945 *cgx_id = (map >> 4) & 0xF;
946 *lmac_id = (map & 0xF);
947 }
948
is_cgx_vf(struct rvu * rvu,u16 pcifunc)949 static inline bool is_cgx_vf(struct rvu *rvu, u16 pcifunc)
950 {
951 return ((pcifunc & RVU_PFVF_FUNC_MASK) &&
952 is_pf_cgxmapped(rvu, rvu_get_pf(rvu->pdev, pcifunc)));
953 }
954
955 #define M(_name, _id, fn_name, req, rsp) \
956 int rvu_mbox_handler_ ## fn_name(struct rvu *, struct req *, struct rsp *);
957 MBOX_MESSAGES
958 #undef M
959
960 /* Mbox APIs */
961 void rvu_queue_work(struct mbox_wq_info *mw, int first,
962 int mdevs, u64 intr);
963
964 int rvu_cgx_init(struct rvu *rvu);
965 int rvu_cgx_exit(struct rvu *rvu);
966 void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu);
967 int rvu_cgx_config_rxtx(struct rvu *rvu, u16 pcifunc, bool start);
968 void rvu_cgx_enadis_rx_bp(struct rvu *rvu, int pf, bool enable);
969 int rvu_cgx_start_stop_io(struct rvu *rvu, u16 pcifunc, bool start);
970 int rvu_cgx_nix_cuml_stats(struct rvu *rvu, void *cgxd, int lmac_id, int index,
971 int rxtxflag, u64 *stat);
972 void rvu_cgx_disable_dmac_entries(struct rvu *rvu, u16 pcifunc);
973
974 /* NPA APIs */
975 int rvu_npa_init(struct rvu *rvu);
976 void rvu_npa_freemem(struct rvu *rvu);
977 void rvu_npa_lf_teardown(struct rvu *rvu, u16 pcifunc, int npalf);
978 int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_aq_enq_req *req,
979 struct npa_aq_enq_rsp *rsp);
980
981 /* NIX APIs */
982 bool is_nixlf_attached(struct rvu *rvu, u16 pcifunc);
983 int rvu_nix_init(struct rvu *rvu);
984 int rvu_nix_reserve_mark_format(struct rvu *rvu, struct nix_hw *nix_hw,
985 int blkaddr, u32 cfg);
986 void rvu_nix_freemem(struct rvu *rvu);
987 int rvu_get_nixlf_count(struct rvu *rvu);
988 void rvu_nix_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int npalf);
989 int nix_get_nixlf(struct rvu *rvu, u16 pcifunc, int *nixlf, int *nix_blkaddr);
990 int nix_update_mce_list(struct rvu *rvu, u16 pcifunc,
991 struct nix_mce_list *mce_list,
992 int mce_idx, int mcam_index, bool add);
993 void nix_get_mce_list(struct rvu *rvu, u16 pcifunc, int type,
994 struct nix_mce_list **mce_list, int *mce_idx);
995 struct nix_hw *get_nix_hw(struct rvu_hwinfo *hw, int blkaddr);
996 int rvu_get_next_nix_blkaddr(struct rvu *rvu, int blkaddr);
997 void rvu_nix_reset_mac(struct rvu_pfvf *pfvf, int pcifunc);
998 int nix_get_struct_ptrs(struct rvu *rvu, u16 pcifunc,
999 struct nix_hw **nix_hw, int *blkaddr);
1000 int rvu_nix_setup_ratelimit_aggr(struct rvu *rvu, u16 pcifunc,
1001 u16 rq_idx, u16 match_id);
1002 int nix_aq_context_read(struct rvu *rvu, struct nix_hw *nix_hw,
1003 struct nix_cn10k_aq_enq_req *aq_req,
1004 struct nix_cn10k_aq_enq_rsp *aq_rsp,
1005 u16 pcifunc, u8 ctype, u32 qidx);
1006 int rvu_get_nix_blkaddr(struct rvu *rvu, u16 pcifunc);
1007 int nix_get_dwrr_mtu_reg(struct rvu_hwinfo *hw, int smq_link_type);
1008 u32 convert_dwrr_mtu_to_bytes(u8 dwrr_mtu);
1009 u32 convert_bytes_to_dwrr_mtu(u32 bytes);
1010 void rvu_nix_tx_tl2_cfg(struct rvu *rvu, int blkaddr, u16 pcifunc,
1011 struct nix_txsch *txsch, bool enable);
1012 void rvu_nix_mcast_flr_free_entries(struct rvu *rvu, u16 pcifunc);
1013 int rvu_nix_mcast_get_mce_index(struct rvu *rvu, u16 pcifunc,
1014 u32 mcast_grp_idx);
1015 int rvu_nix_mcast_update_mcam_entry(struct rvu *rvu, u16 pcifunc,
1016 u32 mcast_grp_idx, u16 mcam_index);
1017 void rvu_nix_flr_free_bpids(struct rvu *rvu, u16 pcifunc);
1018 int rvu_alloc_cint_qint_mem(struct rvu *rvu, struct rvu_pfvf *pfvf,
1019 int blkaddr, int nixlf);
1020 /* NPC APIs */
1021 void rvu_npc_freemem(struct rvu *rvu);
1022 int rvu_npc_get_pkind(struct rvu *rvu, u16 pf);
1023 void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf);
1024 int npc_config_ts_kpuaction(struct rvu *rvu, int pf, u16 pcifunc, bool en);
1025 void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc,
1026 int nixlf, u64 chan, u8 *mac_addr);
1027 void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc,
1028 int nixlf, u64 chan, u8 chan_cnt);
1029 void rvu_npc_enable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
1030 bool enable);
1031 void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc,
1032 int nixlf, u64 chan);
1033 void rvu_npc_install_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
1034 u64 chan);
1035 void rvu_npc_enable_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
1036 bool enable);
1037
1038 void npc_enadis_default_mce_entry(struct rvu *rvu, u16 pcifunc,
1039 int nixlf, int type, bool enable);
1040 void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
1041 bool rvu_npc_enable_mcam_by_entry_index(struct rvu *rvu, int entry, int intf, bool enable);
1042 void rvu_npc_free_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
1043 void rvu_npc_disable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
1044 void rvu_npc_enable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
1045 void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf,
1046 int group, int alg_idx, int mcam_index);
1047 void __rvu_mcam_remove_counter_from_rule(struct rvu *rvu, u16 pcifunc,
1048 struct rvu_npc_mcam_rule *rule);
1049 void __rvu_mcam_add_counter_to_rule(struct rvu *rvu, u16 pcifunc,
1050 struct rvu_npc_mcam_rule *rule,
1051 struct npc_install_flow_rsp *rsp);
1052 void rvu_npc_get_mcam_entry_alloc_info(struct rvu *rvu, u16 pcifunc,
1053 int blkaddr, int *alloc_cnt,
1054 int *enable_cnt);
1055 void rvu_npc_get_mcam_counter_alloc_info(struct rvu *rvu, u16 pcifunc,
1056 int blkaddr, int *alloc_cnt,
1057 int *enable_cnt);
1058 void rvu_npc_clear_ucast_entry(struct rvu *rvu, int pcifunc, int nixlf);
1059
1060 bool is_npc_intf_tx(u8 intf);
1061 bool is_npc_intf_rx(u8 intf);
1062 bool is_npc_interface_valid(struct rvu *rvu, u8 intf);
1063 int rvu_npc_get_tx_nibble_cfg(struct rvu *rvu, u64 nibble_ena);
1064 int npc_flow_steering_init(struct rvu *rvu, int blkaddr);
1065 const char *npc_get_field_name(u8 hdr);
1066 int npc_get_bank(struct npc_mcam *mcam, int index);
1067 void npc_mcam_enable_flows(struct rvu *rvu, u16 target);
1068 void npc_mcam_disable_flows(struct rvu *rvu, u16 target);
1069 void npc_enable_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
1070 int blkaddr, int index, bool enable);
1071 u64 npc_get_mcam_action(struct rvu *rvu, struct npc_mcam *mcam,
1072 int blkaddr, int index);
1073 void npc_set_mcam_action(struct rvu *rvu, struct npc_mcam *mcam,
1074 int blkaddr, int index, u64 cfg);
1075 void npc_read_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
1076 int blkaddr, u16 src, struct mcam_entry *entry,
1077 u8 *intf, u8 *ena);
1078 int npc_config_cntr_default_entries(struct rvu *rvu, bool enable);
1079 bool is_cgx_config_permitted(struct rvu *rvu, u16 pcifunc);
1080 bool is_mac_feature_supported(struct rvu *rvu, int pf, int feature);
1081 u32 rvu_cgx_get_fifolen(struct rvu *rvu);
1082 void *rvu_first_cgx_pdata(struct rvu *rvu);
1083 int cgxlmac_to_pf(struct rvu *rvu, int cgx_id, int lmac_id);
1084 int rvu_cgx_config_tx(void *cgxd, int lmac_id, bool enable);
1085 int rvu_cgx_tx_enable(struct rvu *rvu, u16 pcifunc, bool enable);
1086 int rvu_cgx_prio_flow_ctrl_cfg(struct rvu *rvu, u16 pcifunc, u8 tx_pause, u8 rx_pause,
1087 u16 pfc_en);
1088 int rvu_cgx_cfg_pause_frm(struct rvu *rvu, u16 pcifunc, u8 tx_pause, u8 rx_pause);
1089 void rvu_mac_reset(struct rvu *rvu, u16 pcifunc);
1090 u32 rvu_cgx_get_lmac_fifolen(struct rvu *rvu, int cgx, int lmac);
1091 void cgx_start_linkup(struct rvu *rvu);
1092 int npc_get_nixlf_mcam_index(struct npc_mcam *mcam, u16 pcifunc, int nixlf,
1093 int type);
1094 bool is_mcam_entry_enabled(struct rvu *rvu, struct npc_mcam *mcam, int blkaddr,
1095 int index);
1096 int rvu_npc_init(struct rvu *rvu);
1097 int npc_install_mcam_drop_rule(struct rvu *rvu, int mcam_idx, u16 *counter_idx,
1098 u64 chan_val, u64 chan_mask, u64 exact_val, u64 exact_mask,
1099 u64 bcast_mcast_val, u64 bcast_mcast_mask);
1100 void npc_mcam_rsrcs_reserve(struct rvu *rvu, int blkaddr, int entry_idx);
1101 bool npc_is_feature_supported(struct rvu *rvu, u64 features, u8 intf);
1102 int npc_mcam_rsrcs_init(struct rvu *rvu, int blkaddr);
1103 void npc_mcam_rsrcs_deinit(struct rvu *rvu);
1104
1105 /* CPT APIs */
1106 int rvu_cpt_register_interrupts(struct rvu *rvu);
1107 void rvu_cpt_unregister_interrupts(struct rvu *rvu);
1108 int rvu_cpt_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int lf,
1109 int slot);
1110 int rvu_cpt_ctx_flush(struct rvu *rvu, u16 pcifunc);
1111 int rvu_cpt_init(struct rvu *rvu);
1112
1113 #define NDC_AF_BANK_MASK GENMASK_ULL(7, 0)
1114 #define NDC_AF_BANK_LINE_MASK GENMASK_ULL(31, 16)
1115
1116 /* CN10K RVU */
1117 int rvu_set_channels_base(struct rvu *rvu);
1118 void rvu_program_channels(struct rvu *rvu);
1119
1120 /* CN10K NIX */
1121 void rvu_nix_block_cn10k_init(struct rvu *rvu, struct nix_hw *nix_hw);
1122
1123 /* CN10K RVU - LMT*/
1124 void rvu_reset_lmt_map_tbl(struct rvu *rvu, u16 pcifunc);
1125 void rvu_apr_block_cn10k_init(struct rvu *rvu);
1126
1127 #ifdef CONFIG_DEBUG_FS
1128 void rvu_dbg_init(struct rvu *rvu);
1129 void rvu_dbg_exit(struct rvu *rvu);
1130 #else
rvu_dbg_init(struct rvu * rvu)1131 static inline void rvu_dbg_init(struct rvu *rvu) {}
rvu_dbg_exit(struct rvu * rvu)1132 static inline void rvu_dbg_exit(struct rvu *rvu) {}
1133 #endif
1134
1135 int rvu_ndc_fix_locked_cacheline(struct rvu *rvu, int blkaddr);
1136
1137 /* RVU Switch */
1138 void rvu_switch_enable(struct rvu *rvu);
1139 void rvu_switch_disable(struct rvu *rvu);
1140 void rvu_switch_update_rules(struct rvu *rvu, u16 pcifunc, bool ena);
1141 void rvu_switch_enable_lbk_link(struct rvu *rvu, u16 pcifunc, bool ena);
1142
1143 int rvu_npc_set_parse_mode(struct rvu *rvu, u16 pcifunc, u64 mode, u8 dir,
1144 u64 pkind, u8 var_len_off, u8 var_len_off_mask,
1145 u8 shift_dir);
1146 int rvu_get_hwvf(struct rvu *rvu, int pcifunc);
1147
1148 /* CN10K MCS */
1149 int rvu_mcs_init(struct rvu *rvu);
1150 int rvu_mcs_flr_handler(struct rvu *rvu, u16 pcifunc);
1151 void rvu_mcs_ptp_cfg(struct rvu *rvu, u8 rpm_id, u8 lmac_id, bool ena);
1152 void rvu_mcs_exit(struct rvu *rvu);
1153
1154 /* Representor APIs */
1155 int rvu_rep_pf_init(struct rvu *rvu);
1156 int rvu_rep_install_mcam_rules(struct rvu *rvu);
1157 void rvu_rep_update_rules(struct rvu *rvu, u16 pcifunc, bool ena);
1158 int rvu_rep_notify_pfvf_state(struct rvu *rvu, u16 pcifunc, bool enable);
1159 #endif /* RVU_H */
1160