1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #include <linux/bcd.h> 6 7 #include "main.h" 8 #include "reg.h" 9 #include "fw.h" 10 #include "phy.h" 11 #include "debug.h" 12 #include "regd.h" 13 #include "sar.h" 14 15 struct phy_cfg_pair { 16 u32 addr; 17 u32 data; 18 }; 19 20 union phy_table_tile { 21 struct { 22 struct rtw_phy_cond cond; 23 struct rtw_phy_cond2 cond2; 24 } __packed; 25 struct phy_cfg_pair cfg; 26 }; 27 28 static const u32 db_invert_table[12][8] = { 29 {10, 13, 16, 20, 30 25, 32, 40, 50}, 31 {64, 80, 101, 128, 32 160, 201, 256, 318}, 33 {401, 505, 635, 800, 34 1007, 1268, 1596, 2010}, 35 {316, 398, 501, 631, 36 794, 1000, 1259, 1585}, 37 {1995, 2512, 3162, 3981, 38 5012, 6310, 7943, 10000}, 39 {12589, 15849, 19953, 25119, 40 31623, 39811, 50119, 63098}, 41 {79433, 100000, 125893, 158489, 42 199526, 251189, 316228, 398107}, 43 {501187, 630957, 794328, 1000000, 44 1258925, 1584893, 1995262, 2511886}, 45 {3162278, 3981072, 5011872, 6309573, 46 7943282, 1000000, 12589254, 15848932}, 47 {19952623, 25118864, 31622777, 39810717, 48 50118723, 63095734, 79432823, 100000000}, 49 {125892541, 158489319, 199526232, 251188643, 50 316227766, 398107171, 501187234, 630957345}, 51 {794328235, 1000000000, 1258925412, 1584893192, 52 1995262315, 2511886432U, 3162277660U, 3981071706U} 53 }; 54 55 const u8 rtw_cck_rates[] = { DESC_RATE1M, DESC_RATE2M, DESC_RATE5_5M, DESC_RATE11M }; 56 57 const u8 rtw_ofdm_rates[] = { 58 DESC_RATE6M, DESC_RATE9M, DESC_RATE12M, 59 DESC_RATE18M, DESC_RATE24M, DESC_RATE36M, 60 DESC_RATE48M, DESC_RATE54M 61 }; 62 63 const u8 rtw_ht_1s_rates[] = { 64 DESC_RATEMCS0, DESC_RATEMCS1, DESC_RATEMCS2, 65 DESC_RATEMCS3, DESC_RATEMCS4, DESC_RATEMCS5, 66 DESC_RATEMCS6, DESC_RATEMCS7 67 }; 68 69 const u8 rtw_ht_2s_rates[] = { 70 DESC_RATEMCS8, DESC_RATEMCS9, DESC_RATEMCS10, 71 DESC_RATEMCS11, DESC_RATEMCS12, DESC_RATEMCS13, 72 DESC_RATEMCS14, DESC_RATEMCS15 73 }; 74 75 const u8 rtw_vht_1s_rates[] = { 76 DESC_RATEVHT1SS_MCS0, DESC_RATEVHT1SS_MCS1, 77 DESC_RATEVHT1SS_MCS2, DESC_RATEVHT1SS_MCS3, 78 DESC_RATEVHT1SS_MCS4, DESC_RATEVHT1SS_MCS5, 79 DESC_RATEVHT1SS_MCS6, DESC_RATEVHT1SS_MCS7, 80 DESC_RATEVHT1SS_MCS8, DESC_RATEVHT1SS_MCS9 81 }; 82 83 const u8 rtw_vht_2s_rates[] = { 84 DESC_RATEVHT2SS_MCS0, DESC_RATEVHT2SS_MCS1, 85 DESC_RATEVHT2SS_MCS2, DESC_RATEVHT2SS_MCS3, 86 DESC_RATEVHT2SS_MCS4, DESC_RATEVHT2SS_MCS5, 87 DESC_RATEVHT2SS_MCS6, DESC_RATEVHT2SS_MCS7, 88 DESC_RATEVHT2SS_MCS8, DESC_RATEVHT2SS_MCS9 89 }; 90 91 const u8 rtw_ht_3s_rates[] = { 92 DESC_RATEMCS16, DESC_RATEMCS17, DESC_RATEMCS18, 93 DESC_RATEMCS19, DESC_RATEMCS20, DESC_RATEMCS21, 94 DESC_RATEMCS22, DESC_RATEMCS23 95 }; 96 97 const u8 rtw_ht_4s_rates[] = { 98 DESC_RATEMCS24, DESC_RATEMCS25, DESC_RATEMCS26, 99 DESC_RATEMCS27, DESC_RATEMCS28, DESC_RATEMCS29, 100 DESC_RATEMCS30, DESC_RATEMCS31 101 }; 102 103 const u8 rtw_vht_3s_rates[] = { 104 DESC_RATEVHT3SS_MCS0, DESC_RATEVHT3SS_MCS1, 105 DESC_RATEVHT3SS_MCS2, DESC_RATEVHT3SS_MCS3, 106 DESC_RATEVHT3SS_MCS4, DESC_RATEVHT3SS_MCS5, 107 DESC_RATEVHT3SS_MCS6, DESC_RATEVHT3SS_MCS7, 108 DESC_RATEVHT3SS_MCS8, DESC_RATEVHT3SS_MCS9 109 }; 110 111 const u8 rtw_vht_4s_rates[] = { 112 DESC_RATEVHT4SS_MCS0, DESC_RATEVHT4SS_MCS1, 113 DESC_RATEVHT4SS_MCS2, DESC_RATEVHT4SS_MCS3, 114 DESC_RATEVHT4SS_MCS4, DESC_RATEVHT4SS_MCS5, 115 DESC_RATEVHT4SS_MCS6, DESC_RATEVHT4SS_MCS7, 116 DESC_RATEVHT4SS_MCS8, DESC_RATEVHT4SS_MCS9 117 }; 118 119 const u8 * const rtw_rate_section[RTW_RATE_SECTION_NUM] = { 120 rtw_cck_rates, rtw_ofdm_rates, 121 rtw_ht_1s_rates, rtw_ht_2s_rates, 122 rtw_vht_1s_rates, rtw_vht_2s_rates, 123 rtw_ht_3s_rates, rtw_ht_4s_rates, 124 rtw_vht_3s_rates, rtw_vht_4s_rates 125 }; 126 EXPORT_SYMBOL(rtw_rate_section); 127 128 const u8 rtw_rate_size[RTW_RATE_SECTION_NUM] = { 129 ARRAY_SIZE(rtw_cck_rates), 130 ARRAY_SIZE(rtw_ofdm_rates), 131 ARRAY_SIZE(rtw_ht_1s_rates), 132 ARRAY_SIZE(rtw_ht_2s_rates), 133 ARRAY_SIZE(rtw_vht_1s_rates), 134 ARRAY_SIZE(rtw_vht_2s_rates), 135 ARRAY_SIZE(rtw_ht_3s_rates), 136 ARRAY_SIZE(rtw_ht_4s_rates), 137 ARRAY_SIZE(rtw_vht_3s_rates), 138 ARRAY_SIZE(rtw_vht_4s_rates) 139 }; 140 EXPORT_SYMBOL(rtw_rate_size); 141 142 enum rtw_phy_band_type { 143 PHY_BAND_2G = 0, 144 PHY_BAND_5G = 1, 145 }; 146 147 static void rtw_phy_cck_pd_init(struct rtw_dev *rtwdev) 148 { 149 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 150 u8 i, j; 151 152 for (i = 0; i <= RTW_CHANNEL_WIDTH_40; i++) { 153 for (j = 0; j < RTW_RF_PATH_MAX; j++) 154 dm_info->cck_pd_lv[i][j] = CCK_PD_LV0; 155 } 156 157 dm_info->cck_fa_avg = CCK_FA_AVG_RESET; 158 } 159 160 void rtw_phy_set_edcca_th(struct rtw_dev *rtwdev, u8 l2h, u8 h2l) 161 { 162 const struct rtw_hw_reg_offset *edcca_th = rtwdev->chip->edcca_th; 163 164 rtw_write32_mask(rtwdev, 165 edcca_th[EDCCA_TH_L2H_IDX].hw_reg.addr, 166 edcca_th[EDCCA_TH_L2H_IDX].hw_reg.mask, 167 l2h + edcca_th[EDCCA_TH_L2H_IDX].offset); 168 rtw_write32_mask(rtwdev, 169 edcca_th[EDCCA_TH_H2L_IDX].hw_reg.addr, 170 edcca_th[EDCCA_TH_H2L_IDX].hw_reg.mask, 171 h2l + edcca_th[EDCCA_TH_H2L_IDX].offset); 172 } 173 EXPORT_SYMBOL(rtw_phy_set_edcca_th); 174 175 void rtw_phy_adaptivity_set_mode(struct rtw_dev *rtwdev) 176 { 177 const struct rtw_chip_info *chip = rtwdev->chip; 178 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 179 180 /* turn off in debugfs for debug usage */ 181 if (!rtw_edcca_enabled) { 182 dm_info->edcca_mode = RTW_EDCCA_NORMAL; 183 rtw_dbg(rtwdev, RTW_DBG_PHY, "EDCCA disabled, cannot be set\n"); 184 return; 185 } 186 187 switch (rtwdev->regd.dfs_region) { 188 case NL80211_DFS_ETSI: 189 dm_info->edcca_mode = RTW_EDCCA_ADAPTIVITY; 190 dm_info->l2h_th_ini = chip->l2h_th_ini_ad; 191 break; 192 case NL80211_DFS_JP: 193 dm_info->edcca_mode = RTW_EDCCA_ADAPTIVITY; 194 dm_info->l2h_th_ini = chip->l2h_th_ini_cs; 195 break; 196 default: 197 dm_info->edcca_mode = RTW_EDCCA_NORMAL; 198 break; 199 } 200 } 201 202 static void rtw_phy_adaptivity_init(struct rtw_dev *rtwdev) 203 { 204 const struct rtw_chip_info *chip = rtwdev->chip; 205 206 rtw_phy_adaptivity_set_mode(rtwdev); 207 if (chip->ops->adaptivity_init) 208 chip->ops->adaptivity_init(rtwdev); 209 } 210 211 static void rtw_phy_adaptivity(struct rtw_dev *rtwdev) 212 { 213 if (rtwdev->chip->ops->adaptivity) 214 rtwdev->chip->ops->adaptivity(rtwdev); 215 } 216 217 static void rtw_phy_cfo_init(struct rtw_dev *rtwdev) 218 { 219 const struct rtw_chip_info *chip = rtwdev->chip; 220 221 if (chip->ops->cfo_init) 222 chip->ops->cfo_init(rtwdev); 223 } 224 225 static void rtw_phy_tx_path_div_init(struct rtw_dev *rtwdev) 226 { 227 struct rtw_path_div *path_div = &rtwdev->dm_path_div; 228 229 path_div->current_tx_path = rtwdev->chip->default_1ss_tx_path; 230 path_div->path_a_cnt = 0; 231 path_div->path_a_sum = 0; 232 path_div->path_b_cnt = 0; 233 path_div->path_b_sum = 0; 234 } 235 236 void rtw_phy_init(struct rtw_dev *rtwdev) 237 { 238 const struct rtw_chip_info *chip = rtwdev->chip; 239 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 240 u32 addr, mask; 241 242 dm_info->fa_history[3] = 0; 243 dm_info->fa_history[2] = 0; 244 dm_info->fa_history[1] = 0; 245 dm_info->fa_history[0] = 0; 246 dm_info->igi_bitmap = 0; 247 dm_info->igi_history[3] = 0; 248 dm_info->igi_history[2] = 0; 249 dm_info->igi_history[1] = 0; 250 251 addr = chip->dig[0].addr; 252 mask = chip->dig[0].mask; 253 dm_info->igi_history[0] = rtw_read32_mask(rtwdev, addr, mask); 254 rtw_phy_cck_pd_init(rtwdev); 255 256 dm_info->iqk.done = false; 257 rtw_phy_adaptivity_init(rtwdev); 258 rtw_phy_cfo_init(rtwdev); 259 rtw_phy_tx_path_div_init(rtwdev); 260 } 261 EXPORT_SYMBOL(rtw_phy_init); 262 263 void rtw_phy_dig_write(struct rtw_dev *rtwdev, u8 igi) 264 { 265 const struct rtw_chip_info *chip = rtwdev->chip; 266 struct rtw_hal *hal = &rtwdev->hal; 267 u32 addr, mask; 268 u8 path; 269 270 if (chip->dig_cck) { 271 const struct rtw_hw_reg *dig_cck = &chip->dig_cck[0]; 272 rtw_write32_mask(rtwdev, dig_cck->addr, dig_cck->mask, igi >> 1); 273 } 274 275 for (path = 0; path < hal->rf_path_num; path++) { 276 addr = chip->dig[path].addr; 277 mask = chip->dig[path].mask; 278 rtw_write32_mask(rtwdev, addr, mask, igi); 279 } 280 } 281 282 static void rtw_phy_stat_false_alarm(struct rtw_dev *rtwdev) 283 { 284 const struct rtw_chip_info *chip = rtwdev->chip; 285 286 chip->ops->false_alarm_statistics(rtwdev); 287 } 288 289 #define RA_FLOOR_TABLE_SIZE 7 290 #define RA_FLOOR_UP_GAP 3 291 292 static u8 rtw_phy_get_rssi_level(u8 old_level, u8 rssi) 293 { 294 u8 table[RA_FLOOR_TABLE_SIZE] = {20, 34, 38, 42, 46, 50, 100}; 295 u8 new_level = 0; 296 int i; 297 298 for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) 299 if (i >= old_level) 300 table[i] += RA_FLOOR_UP_GAP; 301 302 for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) { 303 if (rssi < table[i]) { 304 new_level = i; 305 break; 306 } 307 } 308 309 return new_level; 310 } 311 312 struct rtw_phy_stat_iter_data { 313 struct rtw_dev *rtwdev; 314 u8 min_rssi; 315 }; 316 317 static void rtw_phy_stat_rssi_iter(void *data, struct ieee80211_sta *sta) 318 { 319 struct rtw_phy_stat_iter_data *iter_data = data; 320 struct rtw_dev *rtwdev = iter_data->rtwdev; 321 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; 322 u8 rssi; 323 324 rssi = ewma_rssi_read(&si->avg_rssi); 325 si->rssi_level = rtw_phy_get_rssi_level(si->rssi_level, rssi); 326 327 rtw_fw_send_rssi_info(rtwdev, si); 328 329 iter_data->min_rssi = min_t(u8, rssi, iter_data->min_rssi); 330 } 331 332 static void rtw_phy_stat_rssi(struct rtw_dev *rtwdev) 333 { 334 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 335 struct rtw_phy_stat_iter_data data = {}; 336 337 data.rtwdev = rtwdev; 338 data.min_rssi = U8_MAX; 339 rtw_iterate_stas(rtwdev, rtw_phy_stat_rssi_iter, &data); 340 341 dm_info->pre_min_rssi = dm_info->min_rssi; 342 dm_info->min_rssi = data.min_rssi; 343 } 344 345 static void rtw_phy_stat_rate_cnt(struct rtw_dev *rtwdev) 346 { 347 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 348 349 dm_info->last_pkt_count = dm_info->cur_pkt_count; 350 memset(&dm_info->cur_pkt_count, 0, sizeof(dm_info->cur_pkt_count)); 351 } 352 353 static void rtw_phy_statistics(struct rtw_dev *rtwdev) 354 { 355 rtw_phy_stat_rssi(rtwdev); 356 rtw_phy_stat_false_alarm(rtwdev); 357 rtw_phy_stat_rate_cnt(rtwdev); 358 } 359 360 #define DIG_PERF_FA_TH_LOW 250 361 #define DIG_PERF_FA_TH_HIGH 500 362 #define DIG_PERF_FA_TH_EXTRA_HIGH 750 363 #define DIG_PERF_MAX 0x5a 364 #define DIG_PERF_MID 0x40 365 #define DIG_CVRG_FA_TH_LOW 2000 366 #define DIG_CVRG_FA_TH_HIGH 4000 367 #define DIG_CVRG_FA_TH_EXTRA_HIGH 5000 368 #define DIG_CVRG_MAX 0x2a 369 #define DIG_CVRG_MID 0x26 370 #define DIG_CVRG_MIN 0x1c 371 #define DIG_RSSI_GAIN_OFFSET 15 372 373 void rtw_phy_dig_set_max_coverage(struct rtw_dev *rtwdev) 374 { 375 /* Lower values result in greater coverage. */ 376 rtw_dbg(rtwdev, RTW_DBG_PHY, "Setting IGI=%#x for max coverage\n", 377 DIG_CVRG_MIN); 378 379 rtw_phy_dig_write(rtwdev, DIG_CVRG_MIN); 380 } 381 382 void rtw_phy_dig_reset(struct rtw_dev *rtwdev) 383 { 384 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 385 u8 last_igi; 386 387 last_igi = dm_info->igi_history[0]; 388 rtw_dbg(rtwdev, RTW_DBG_PHY, "Resetting IGI=%#x\n", last_igi); 389 390 rtw_phy_dig_write(rtwdev, last_igi); 391 } 392 393 static bool 394 rtw_phy_dig_check_damping(struct rtw_dm_info *dm_info) 395 { 396 u16 fa_lo = DIG_PERF_FA_TH_LOW; 397 u16 fa_hi = DIG_PERF_FA_TH_HIGH; 398 u16 *fa_history; 399 u8 *igi_history; 400 u8 damping_rssi; 401 u8 min_rssi; 402 u8 diff; 403 u8 igi_bitmap; 404 bool damping = false; 405 406 min_rssi = dm_info->min_rssi; 407 if (dm_info->damping) { 408 damping_rssi = dm_info->damping_rssi; 409 diff = min_rssi > damping_rssi ? min_rssi - damping_rssi : 410 damping_rssi - min_rssi; 411 if (diff > 3 || dm_info->damping_cnt++ > 20) { 412 dm_info->damping = false; 413 return false; 414 } 415 416 return true; 417 } 418 419 igi_history = dm_info->igi_history; 420 fa_history = dm_info->fa_history; 421 igi_bitmap = dm_info->igi_bitmap & 0xf; 422 switch (igi_bitmap) { 423 case 5: 424 /* down -> up -> down -> up */ 425 if (igi_history[0] > igi_history[1] && 426 igi_history[2] > igi_history[3] && 427 igi_history[0] - igi_history[1] >= 2 && 428 igi_history[2] - igi_history[3] >= 2 && 429 fa_history[0] > fa_hi && fa_history[1] < fa_lo && 430 fa_history[2] > fa_hi && fa_history[3] < fa_lo) 431 damping = true; 432 break; 433 case 9: 434 /* up -> down -> down -> up */ 435 if (igi_history[0] > igi_history[1] && 436 igi_history[3] > igi_history[2] && 437 igi_history[0] - igi_history[1] >= 4 && 438 igi_history[3] - igi_history[2] >= 2 && 439 fa_history[0] > fa_hi && fa_history[1] < fa_lo && 440 fa_history[2] < fa_lo && fa_history[3] > fa_hi) 441 damping = true; 442 break; 443 default: 444 return false; 445 } 446 447 if (damping) { 448 dm_info->damping = true; 449 dm_info->damping_cnt = 0; 450 dm_info->damping_rssi = min_rssi; 451 } 452 453 return damping; 454 } 455 456 static void rtw_phy_dig_get_boundary(struct rtw_dev *rtwdev, 457 struct rtw_dm_info *dm_info, 458 u8 *upper, u8 *lower, bool linked) 459 { 460 u8 dig_max, dig_min, dig_mid; 461 u8 min_rssi; 462 463 if (linked) { 464 dig_max = DIG_PERF_MAX; 465 dig_mid = DIG_PERF_MID; 466 dig_min = rtwdev->chip->dig_min; 467 min_rssi = max_t(u8, dm_info->min_rssi, dig_min); 468 } else { 469 dig_max = DIG_CVRG_MAX; 470 dig_mid = DIG_CVRG_MID; 471 dig_min = DIG_CVRG_MIN; 472 min_rssi = dig_min; 473 } 474 475 /* DIG MAX should be bounded by minimum RSSI with offset +15 */ 476 dig_max = min_t(u8, dig_max, min_rssi + DIG_RSSI_GAIN_OFFSET); 477 478 *lower = clamp_t(u8, min_rssi, dig_min, dig_mid); 479 *upper = clamp_t(u8, *lower + DIG_RSSI_GAIN_OFFSET, dig_min, dig_max); 480 } 481 482 static void rtw_phy_dig_get_threshold(struct rtw_dm_info *dm_info, 483 u16 *fa_th, u8 *step, bool linked) 484 { 485 u8 min_rssi, pre_min_rssi; 486 487 min_rssi = dm_info->min_rssi; 488 pre_min_rssi = dm_info->pre_min_rssi; 489 step[0] = 4; 490 step[1] = 3; 491 step[2] = 2; 492 493 if (linked) { 494 fa_th[0] = DIG_PERF_FA_TH_EXTRA_HIGH; 495 fa_th[1] = DIG_PERF_FA_TH_HIGH; 496 fa_th[2] = DIG_PERF_FA_TH_LOW; 497 if (pre_min_rssi > min_rssi) { 498 step[0] = 6; 499 step[1] = 4; 500 step[2] = 2; 501 } 502 } else { 503 fa_th[0] = DIG_CVRG_FA_TH_EXTRA_HIGH; 504 fa_th[1] = DIG_CVRG_FA_TH_HIGH; 505 fa_th[2] = DIG_CVRG_FA_TH_LOW; 506 } 507 } 508 509 static void rtw_phy_dig_recorder(struct rtw_dm_info *dm_info, u8 igi, u16 fa) 510 { 511 u8 *igi_history; 512 u16 *fa_history; 513 u8 igi_bitmap; 514 bool up; 515 516 igi_bitmap = dm_info->igi_bitmap << 1 & 0xfe; 517 igi_history = dm_info->igi_history; 518 fa_history = dm_info->fa_history; 519 520 up = igi > igi_history[0]; 521 igi_bitmap |= up; 522 523 igi_history[3] = igi_history[2]; 524 igi_history[2] = igi_history[1]; 525 igi_history[1] = igi_history[0]; 526 igi_history[0] = igi; 527 528 fa_history[3] = fa_history[2]; 529 fa_history[2] = fa_history[1]; 530 fa_history[1] = fa_history[0]; 531 fa_history[0] = fa; 532 533 dm_info->igi_bitmap = igi_bitmap; 534 } 535 536 static void rtw_phy_dig(struct rtw_dev *rtwdev) 537 { 538 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 539 u8 upper_bound, lower_bound; 540 u8 pre_igi, cur_igi; 541 u16 fa_th[3], fa_cnt; 542 u8 level; 543 u8 step[3]; 544 bool linked; 545 546 if (test_bit(RTW_FLAG_DIG_DISABLE, rtwdev->flags)) 547 return; 548 549 if (rtw_phy_dig_check_damping(dm_info)) 550 return; 551 552 linked = !!rtwdev->sta_cnt; 553 554 fa_cnt = dm_info->total_fa_cnt; 555 pre_igi = dm_info->igi_history[0]; 556 557 rtw_phy_dig_get_threshold(dm_info, fa_th, step, linked); 558 559 /* test the false alarm count from the highest threshold level first, 560 * and increase it by corresponding step size 561 * 562 * note that the step size is offset by -2, compensate it afterall 563 */ 564 cur_igi = pre_igi; 565 for (level = 0; level < 3; level++) { 566 if (fa_cnt > fa_th[level]) { 567 cur_igi += step[level]; 568 break; 569 } 570 } 571 cur_igi -= 2; 572 573 /* calculate the upper/lower bound by the minimum rssi we have among 574 * the peers connected with us, meanwhile make sure the igi value does 575 * not beyond the hardware limitation 576 */ 577 rtw_phy_dig_get_boundary(rtwdev, dm_info, &upper_bound, &lower_bound, 578 linked); 579 cur_igi = clamp_t(u8, cur_igi, lower_bound, upper_bound); 580 581 /* record current igi value and false alarm statistics for further 582 * damping checks, and record the trend of igi values 583 */ 584 rtw_phy_dig_recorder(dm_info, cur_igi, fa_cnt); 585 586 /* Mitigate beacon loss and connectivity issues, mainly (only?) 587 * in the 5 GHz band 588 */ 589 if (rtwdev->chip->id == RTW_CHIP_TYPE_8812A && rtwdev->beacon_loss && 590 linked && dm_info->total_fa_cnt < DIG_PERF_FA_TH_EXTRA_HIGH) 591 cur_igi = DIG_CVRG_MIN; 592 593 if (cur_igi != pre_igi) 594 rtw_phy_dig_write(rtwdev, cur_igi); 595 } 596 597 static void rtw_phy_ra_info_update_iter(void *data, struct ieee80211_sta *sta) 598 { 599 struct rtw_dev *rtwdev = data; 600 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; 601 602 rtw_update_sta_info(rtwdev, si, false); 603 } 604 605 static void rtw_phy_ra_info_update(struct rtw_dev *rtwdev) 606 { 607 if (rtwdev->watch_dog_cnt & 0x3) 608 return; 609 610 rtw_iterate_stas(rtwdev, rtw_phy_ra_info_update_iter, rtwdev); 611 } 612 613 static u32 rtw_phy_get_rrsr_mask(struct rtw_dev *rtwdev, u8 rate_idx) 614 { 615 u8 rate_order; 616 617 rate_order = rate_idx; 618 619 if (rate_idx >= DESC_RATEVHT4SS_MCS0) 620 rate_order -= DESC_RATEVHT4SS_MCS0; 621 else if (rate_idx >= DESC_RATEVHT3SS_MCS0) 622 rate_order -= DESC_RATEVHT3SS_MCS0; 623 else if (rate_idx >= DESC_RATEVHT2SS_MCS0) 624 rate_order -= DESC_RATEVHT2SS_MCS0; 625 else if (rate_idx >= DESC_RATEVHT1SS_MCS0) 626 rate_order -= DESC_RATEVHT1SS_MCS0; 627 else if (rate_idx >= DESC_RATEMCS24) 628 rate_order -= DESC_RATEMCS24; 629 else if (rate_idx >= DESC_RATEMCS16) 630 rate_order -= DESC_RATEMCS16; 631 else if (rate_idx >= DESC_RATEMCS8) 632 rate_order -= DESC_RATEMCS8; 633 else if (rate_idx >= DESC_RATEMCS0) 634 rate_order -= DESC_RATEMCS0; 635 else if (rate_idx >= DESC_RATE6M) 636 rate_order -= DESC_RATE6M; 637 else 638 rate_order -= DESC_RATE1M; 639 640 if (rate_idx >= DESC_RATEMCS0 || rate_order == 0) 641 rate_order++; 642 643 return GENMASK(rate_order + RRSR_RATE_ORDER_CCK_LEN - 1, 0); 644 } 645 646 static void rtw_phy_rrsr_mask_min_iter(void *data, struct ieee80211_sta *sta) 647 { 648 struct rtw_dev *rtwdev = (struct rtw_dev *)data; 649 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; 650 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 651 u32 mask = 0; 652 653 mask = rtw_phy_get_rrsr_mask(rtwdev, si->ra_report.desc_rate); 654 if (mask < dm_info->rrsr_mask_min) 655 dm_info->rrsr_mask_min = mask; 656 } 657 658 static void rtw_phy_rrsr_update(struct rtw_dev *rtwdev) 659 { 660 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 661 662 dm_info->rrsr_mask_min = RRSR_RATE_ORDER_MAX; 663 rtw_iterate_stas(rtwdev, rtw_phy_rrsr_mask_min_iter, rtwdev); 664 rtw_write32(rtwdev, REG_RRSR, dm_info->rrsr_val_init & dm_info->rrsr_mask_min); 665 } 666 667 static void rtw_phy_dpk_track(struct rtw_dev *rtwdev) 668 { 669 const struct rtw_chip_info *chip = rtwdev->chip; 670 671 if (chip->ops->dpk_track) 672 chip->ops->dpk_track(rtwdev); 673 } 674 675 struct rtw_rx_addr_match_data { 676 struct rtw_dev *rtwdev; 677 struct ieee80211_hdr *hdr; 678 struct rtw_rx_pkt_stat *pkt_stat; 679 u8 *bssid; 680 }; 681 682 static void rtw_phy_parsing_cfo_iter(void *data, u8 *mac, 683 struct ieee80211_vif *vif) 684 { 685 struct rtw_rx_addr_match_data *iter_data = data; 686 struct rtw_dev *rtwdev = iter_data->rtwdev; 687 struct rtw_rx_pkt_stat *pkt_stat = iter_data->pkt_stat; 688 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 689 struct rtw_cfo_track *cfo = &dm_info->cfo_track; 690 u8 *bssid = iter_data->bssid; 691 u8 i; 692 693 if (!ether_addr_equal(vif->bss_conf.bssid, bssid)) 694 return; 695 696 for (i = 0; i < rtwdev->hal.rf_path_num; i++) { 697 cfo->cfo_tail[i] += pkt_stat->cfo_tail[i]; 698 cfo->cfo_cnt[i]++; 699 } 700 701 cfo->packet_count++; 702 } 703 704 void rtw_phy_parsing_cfo(struct rtw_dev *rtwdev, 705 struct rtw_rx_pkt_stat *pkt_stat) 706 { 707 struct ieee80211_hdr *hdr = pkt_stat->hdr; 708 struct rtw_rx_addr_match_data data = {}; 709 710 if (pkt_stat->crc_err || pkt_stat->icv_err || !pkt_stat->phy_status || 711 ieee80211_is_ctl(hdr->frame_control)) 712 return; 713 714 data.rtwdev = rtwdev; 715 data.hdr = hdr; 716 data.pkt_stat = pkt_stat; 717 data.bssid = get_hdr_bssid(hdr); 718 719 rtw_iterate_vifs_atomic(rtwdev, rtw_phy_parsing_cfo_iter, &data); 720 } 721 EXPORT_SYMBOL(rtw_phy_parsing_cfo); 722 723 static void rtw_phy_cfo_track(struct rtw_dev *rtwdev) 724 { 725 const struct rtw_chip_info *chip = rtwdev->chip; 726 727 if (chip->ops->cfo_track) 728 chip->ops->cfo_track(rtwdev); 729 } 730 731 #define CCK_PD_FA_LV1_MIN 1000 732 #define CCK_PD_FA_LV0_MAX 500 733 734 static u8 rtw_phy_cck_pd_lv_unlink(struct rtw_dev *rtwdev) 735 { 736 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 737 u32 cck_fa_avg = dm_info->cck_fa_avg; 738 739 if (cck_fa_avg > CCK_PD_FA_LV1_MIN) 740 return CCK_PD_LV1; 741 742 if (cck_fa_avg < CCK_PD_FA_LV0_MAX) 743 return CCK_PD_LV0; 744 745 return CCK_PD_LV_MAX; 746 } 747 748 #define CCK_PD_IGI_LV4_VAL 0x38 749 #define CCK_PD_IGI_LV3_VAL 0x2a 750 #define CCK_PD_IGI_LV2_VAL 0x24 751 #define CCK_PD_RSSI_LV4_VAL 32 752 #define CCK_PD_RSSI_LV3_VAL 32 753 #define CCK_PD_RSSI_LV2_VAL 24 754 755 static u8 rtw_phy_cck_pd_lv_link(struct rtw_dev *rtwdev) 756 { 757 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 758 u8 igi = dm_info->igi_history[0]; 759 u8 rssi = dm_info->min_rssi; 760 u32 cck_fa_avg = dm_info->cck_fa_avg; 761 762 if (igi > CCK_PD_IGI_LV4_VAL && rssi > CCK_PD_RSSI_LV4_VAL) 763 return CCK_PD_LV4; 764 if (igi > CCK_PD_IGI_LV3_VAL && rssi > CCK_PD_RSSI_LV3_VAL) 765 return CCK_PD_LV3; 766 if (igi > CCK_PD_IGI_LV2_VAL || rssi > CCK_PD_RSSI_LV2_VAL) 767 return CCK_PD_LV2; 768 if (cck_fa_avg > CCK_PD_FA_LV1_MIN) 769 return CCK_PD_LV1; 770 if (cck_fa_avg < CCK_PD_FA_LV0_MAX) 771 return CCK_PD_LV0; 772 773 return CCK_PD_LV_MAX; 774 } 775 776 static u8 rtw_phy_cck_pd_lv(struct rtw_dev *rtwdev) 777 { 778 if (!rtw_is_assoc(rtwdev)) 779 return rtw_phy_cck_pd_lv_unlink(rtwdev); 780 else 781 return rtw_phy_cck_pd_lv_link(rtwdev); 782 } 783 784 static void rtw_phy_cck_pd(struct rtw_dev *rtwdev) 785 { 786 const struct rtw_chip_info *chip = rtwdev->chip; 787 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 788 u32 cck_fa = dm_info->cck_fa_cnt; 789 u8 level; 790 791 if (rtwdev->hal.current_band_type != RTW_BAND_2G) 792 return; 793 794 if (dm_info->cck_fa_avg == CCK_FA_AVG_RESET) 795 dm_info->cck_fa_avg = cck_fa; 796 else 797 dm_info->cck_fa_avg = (dm_info->cck_fa_avg * 3 + cck_fa) >> 2; 798 799 rtw_dbg(rtwdev, RTW_DBG_PHY, "IGI=0x%x, rssi_min=%d, cck_fa=%d\n", 800 dm_info->igi_history[0], dm_info->min_rssi, 801 dm_info->fa_history[0]); 802 rtw_dbg(rtwdev, RTW_DBG_PHY, "cck_fa_avg=%d, cck_pd_default=%d\n", 803 dm_info->cck_fa_avg, dm_info->cck_pd_default); 804 805 level = rtw_phy_cck_pd_lv(rtwdev); 806 807 if (level >= CCK_PD_LV_MAX) 808 return; 809 810 if (chip->ops->cck_pd_set) 811 chip->ops->cck_pd_set(rtwdev, level); 812 } 813 814 static void rtw_phy_pwr_track(struct rtw_dev *rtwdev) 815 { 816 rtwdev->chip->ops->pwr_track(rtwdev); 817 } 818 819 static void rtw_phy_ra_track(struct rtw_dev *rtwdev) 820 { 821 rtw_fw_update_wl_phy_info(rtwdev); 822 rtw_phy_ra_info_update(rtwdev); 823 rtw_phy_rrsr_update(rtwdev); 824 } 825 826 void rtw_phy_dynamic_mechanism(struct rtw_dev *rtwdev) 827 { 828 /* for further calculation */ 829 rtw_phy_statistics(rtwdev); 830 rtw_phy_dig(rtwdev); 831 rtw_phy_cck_pd(rtwdev); 832 rtw_phy_ra_track(rtwdev); 833 rtw_phy_tx_path_diversity(rtwdev); 834 rtw_phy_cfo_track(rtwdev); 835 rtw_phy_dpk_track(rtwdev); 836 rtw_phy_pwr_track(rtwdev); 837 838 if (rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_ADAPTIVITY)) 839 rtw_fw_adaptivity(rtwdev); 840 else 841 rtw_phy_adaptivity(rtwdev); 842 } 843 844 #define FRAC_BITS 3 845 846 static u8 rtw_phy_power_2_db(s8 power) 847 { 848 if (power <= -100 || power >= 20) 849 return 0; 850 else if (power >= 0) 851 return 100; 852 else 853 return 100 + power; 854 } 855 856 static u64 rtw_phy_db_2_linear(u8 power_db) 857 { 858 u8 i, j; 859 u64 linear; 860 861 if (power_db > 96) 862 power_db = 96; 863 else if (power_db < 1) 864 return 1; 865 866 /* 1dB ~ 96dB */ 867 i = (power_db - 1) >> 3; 868 j = (power_db - 1) - (i << 3); 869 870 linear = db_invert_table[i][j]; 871 linear = i > 2 ? linear << FRAC_BITS : linear; 872 873 return linear; 874 } 875 876 static u8 rtw_phy_linear_2_db(u64 linear) 877 { 878 u8 i; 879 u8 j; 880 u32 dB; 881 882 for (i = 0; i < 12; i++) { 883 for (j = 0; j < 8; j++) { 884 if (i <= 2 && (linear << FRAC_BITS) <= db_invert_table[i][j]) 885 goto cnt; 886 else if (i > 2 && linear <= db_invert_table[i][j]) 887 goto cnt; 888 } 889 } 890 891 return 96; /* maximum 96 dB */ 892 893 cnt: 894 if (j == 0 && i == 0) 895 goto end; 896 897 if (j == 0) { 898 if (i != 3) { 899 if (db_invert_table[i][0] - linear > 900 linear - db_invert_table[i - 1][7]) { 901 i = i - 1; 902 j = 7; 903 } 904 } else { 905 if (db_invert_table[3][0] - linear > 906 linear - db_invert_table[2][7]) { 907 i = 2; 908 j = 7; 909 } 910 } 911 } else { 912 if (db_invert_table[i][j] - linear > 913 linear - db_invert_table[i][j - 1]) { 914 j = j - 1; 915 } 916 } 917 end: 918 dB = (i << 3) + j + 1; 919 920 return dB; 921 } 922 923 u8 rtw_phy_rf_power_2_rssi(s8 *rf_power, u8 path_num) 924 { 925 s8 power; 926 u8 power_db; 927 u64 linear; 928 u64 sum = 0; 929 u8 path; 930 931 for (path = 0; path < path_num; path++) { 932 power = rf_power[path]; 933 power_db = rtw_phy_power_2_db(power); 934 linear = rtw_phy_db_2_linear(power_db); 935 sum += linear; 936 } 937 938 sum = (sum + (1 << (FRAC_BITS - 1))) >> FRAC_BITS; 939 switch (path_num) { 940 case 2: 941 sum >>= 1; 942 break; 943 case 3: 944 sum = ((sum) + ((sum) << 1) + ((sum) << 3)) >> 5; 945 break; 946 case 4: 947 sum >>= 2; 948 break; 949 default: 950 break; 951 } 952 953 return rtw_phy_linear_2_db(sum); 954 } 955 EXPORT_SYMBOL(rtw_phy_rf_power_2_rssi); 956 957 u32 rtw_phy_read_rf(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 958 u32 addr, u32 mask) 959 { 960 struct rtw_hal *hal = &rtwdev->hal; 961 const struct rtw_chip_info *chip = rtwdev->chip; 962 const u32 *base_addr = chip->rf_base_addr; 963 u32 val, direct_addr; 964 965 if (rf_path >= hal->rf_phy_num) { 966 rtw_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 967 return INV_RF_DATA; 968 } 969 970 addr &= 0xff; 971 direct_addr = base_addr[rf_path] + (addr << 2); 972 mask &= RFREG_MASK; 973 974 val = rtw_read32_mask(rtwdev, direct_addr, mask); 975 976 return val; 977 } 978 EXPORT_SYMBOL(rtw_phy_read_rf); 979 980 u32 rtw_phy_read_rf_sipi(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 981 u32 addr, u32 mask) 982 { 983 struct rtw_hal *hal = &rtwdev->hal; 984 const struct rtw_chip_info *chip = rtwdev->chip; 985 const struct rtw_rf_sipi_addr *rf_sipi_addr; 986 const struct rtw_rf_sipi_addr *rf_sipi_addr_a; 987 u32 val32; 988 u32 en_pi; 989 u32 r_addr; 990 u32 shift; 991 992 if (rf_path >= hal->rf_phy_num) { 993 rtw_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 994 return INV_RF_DATA; 995 } 996 997 if (!chip->rf_sipi_read_addr) { 998 rtw_err(rtwdev, "rf_sipi_read_addr isn't defined\n"); 999 return INV_RF_DATA; 1000 } 1001 1002 rf_sipi_addr = &chip->rf_sipi_read_addr[rf_path]; 1003 rf_sipi_addr_a = &chip->rf_sipi_read_addr[RF_PATH_A]; 1004 1005 addr &= 0xff; 1006 1007 val32 = rtw_read32(rtwdev, rf_sipi_addr->hssi_2); 1008 val32 = (val32 & ~LSSI_READ_ADDR_MASK) | (addr << 23); 1009 rtw_write32(rtwdev, rf_sipi_addr->hssi_2, val32); 1010 1011 /* toggle read edge of path A */ 1012 val32 = rtw_read32(rtwdev, rf_sipi_addr_a->hssi_2); 1013 rtw_write32(rtwdev, rf_sipi_addr_a->hssi_2, val32 & ~LSSI_READ_EDGE_MASK); 1014 rtw_write32(rtwdev, rf_sipi_addr_a->hssi_2, val32 | LSSI_READ_EDGE_MASK); 1015 1016 udelay(120); 1017 1018 en_pi = rtw_read32_mask(rtwdev, rf_sipi_addr->hssi_1, BIT(8)); 1019 r_addr = en_pi ? rf_sipi_addr->lssi_read_pi : rf_sipi_addr->lssi_read; 1020 1021 val32 = rtw_read32_mask(rtwdev, r_addr, LSSI_READ_DATA_MASK); 1022 1023 shift = __ffs(mask); 1024 1025 return (val32 & mask) >> shift; 1026 } 1027 EXPORT_SYMBOL(rtw_phy_read_rf_sipi); 1028 1029 bool rtw_phy_write_rf_reg_sipi(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 1030 u32 addr, u32 mask, u32 data) 1031 { 1032 struct rtw_hal *hal = &rtwdev->hal; 1033 const struct rtw_chip_info *chip = rtwdev->chip; 1034 const u32 *sipi_addr = chip->rf_sipi_addr; 1035 u32 data_and_addr; 1036 u32 old_data = 0; 1037 u32 shift; 1038 1039 if (rf_path >= hal->rf_phy_num) { 1040 rtw_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 1041 return false; 1042 } 1043 1044 addr &= 0xff; 1045 mask &= RFREG_MASK; 1046 1047 if (mask != RFREG_MASK) { 1048 old_data = chip->ops->read_rf(rtwdev, rf_path, addr, RFREG_MASK); 1049 1050 if (old_data == INV_RF_DATA) { 1051 rtw_err(rtwdev, "Write fail, rf is disabled\n"); 1052 return false; 1053 } 1054 1055 shift = __ffs(mask); 1056 data = ((old_data) & (~mask)) | (data << shift); 1057 } 1058 1059 data_and_addr = ((addr << 20) | (data & 0x000fffff)) & 0x0fffffff; 1060 1061 rtw_write32(rtwdev, sipi_addr[rf_path], data_and_addr); 1062 1063 udelay(13); 1064 1065 return true; 1066 } 1067 EXPORT_SYMBOL(rtw_phy_write_rf_reg_sipi); 1068 1069 bool rtw_phy_write_rf_reg(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 1070 u32 addr, u32 mask, u32 data) 1071 { 1072 struct rtw_hal *hal = &rtwdev->hal; 1073 const struct rtw_chip_info *chip = rtwdev->chip; 1074 const u32 *base_addr = chip->rf_base_addr; 1075 u32 direct_addr; 1076 1077 if (rf_path >= hal->rf_phy_num) { 1078 rtw_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 1079 return false; 1080 } 1081 1082 addr &= 0xff; 1083 direct_addr = base_addr[rf_path] + (addr << 2); 1084 mask &= RFREG_MASK; 1085 1086 rtw_write32_mask(rtwdev, direct_addr, mask, data); 1087 1088 udelay(1); 1089 1090 return true; 1091 } 1092 1093 bool rtw_phy_write_rf_reg_mix(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 1094 u32 addr, u32 mask, u32 data) 1095 { 1096 if (addr != 0x00) 1097 return rtw_phy_write_rf_reg(rtwdev, rf_path, addr, mask, data); 1098 1099 return rtw_phy_write_rf_reg_sipi(rtwdev, rf_path, addr, mask, data); 1100 } 1101 EXPORT_SYMBOL(rtw_phy_write_rf_reg_mix); 1102 1103 void rtw_phy_setup_phy_cond(struct rtw_dev *rtwdev, u32 pkg) 1104 { 1105 struct rtw_hal *hal = &rtwdev->hal; 1106 struct rtw_efuse *efuse = &rtwdev->efuse; 1107 struct rtw_phy_cond cond = {}; 1108 struct rtw_phy_cond2 cond2 = {}; 1109 1110 cond.cut = hal->cut_version ? hal->cut_version : 15; 1111 cond.pkg = pkg ? pkg : 15; 1112 cond.plat = 0x04; 1113 cond.rfe = efuse->rfe_option; 1114 1115 switch (rtw_hci_type(rtwdev)) { 1116 case RTW_HCI_TYPE_USB: 1117 cond.intf = INTF_USB; 1118 break; 1119 case RTW_HCI_TYPE_SDIO: 1120 cond.intf = INTF_SDIO; 1121 break; 1122 case RTW_HCI_TYPE_PCIE: 1123 default: 1124 cond.intf = INTF_PCIE; 1125 break; 1126 } 1127 1128 if (rtwdev->chip->id == RTW_CHIP_TYPE_8812A || 1129 rtwdev->chip->id == RTW_CHIP_TYPE_8821A) { 1130 cond.rfe = 0; 1131 cond.rfe |= efuse->ext_lna_2g; 1132 cond.rfe |= efuse->ext_pa_2g << 1; 1133 cond.rfe |= efuse->ext_lna_5g << 2; 1134 cond.rfe |= efuse->ext_pa_5g << 3; 1135 cond.rfe |= efuse->btcoex << 4; 1136 1137 cond2.type_alna = efuse->alna_type; 1138 cond2.type_glna = efuse->glna_type; 1139 cond2.type_apa = efuse->apa_type; 1140 cond2.type_gpa = efuse->gpa_type; 1141 } 1142 1143 hal->phy_cond = cond; 1144 hal->phy_cond2 = cond2; 1145 1146 rtw_dbg(rtwdev, RTW_DBG_PHY, "phy cond=0x%08x cond2=0x%08x\n", 1147 *((u32 *)&hal->phy_cond), *((u32 *)&hal->phy_cond2)); 1148 } 1149 1150 static bool check_positive(struct rtw_dev *rtwdev, struct rtw_phy_cond cond, 1151 struct rtw_phy_cond2 cond2) 1152 { 1153 struct rtw_hal *hal = &rtwdev->hal; 1154 struct rtw_phy_cond drv_cond = hal->phy_cond; 1155 struct rtw_phy_cond2 drv_cond2 = hal->phy_cond2; 1156 1157 if (cond.cut && cond.cut != drv_cond.cut) 1158 return false; 1159 1160 if (cond.pkg && cond.pkg != drv_cond.pkg) 1161 return false; 1162 1163 if (cond.intf && cond.intf != drv_cond.intf) 1164 return false; 1165 1166 if (rtwdev->chip->id == RTW_CHIP_TYPE_8812A || 1167 rtwdev->chip->id == RTW_CHIP_TYPE_8821A) { 1168 if (!(cond.rfe & 0x0f)) 1169 return true; 1170 1171 if ((cond.rfe & drv_cond.rfe) != cond.rfe) 1172 return false; 1173 1174 if ((cond.rfe & BIT(0)) && cond2.type_glna != drv_cond2.type_glna) 1175 return false; 1176 1177 if ((cond.rfe & BIT(1)) && cond2.type_gpa != drv_cond2.type_gpa) 1178 return false; 1179 1180 if ((cond.rfe & BIT(2)) && cond2.type_alna != drv_cond2.type_alna) 1181 return false; 1182 1183 if ((cond.rfe & BIT(3)) && cond2.type_apa != drv_cond2.type_apa) 1184 return false; 1185 } else { 1186 if (cond.rfe != drv_cond.rfe) 1187 return false; 1188 } 1189 1190 return true; 1191 } 1192 1193 void rtw_parse_tbl_phy_cond(struct rtw_dev *rtwdev, const struct rtw_table *tbl) 1194 { 1195 const union phy_table_tile *p = tbl->data; 1196 const union phy_table_tile *end = p + tbl->size / 2; 1197 struct rtw_phy_cond pos_cond = {}; 1198 struct rtw_phy_cond2 pos_cond2 = {}; 1199 bool is_matched = true, is_skipped = false; 1200 1201 BUILD_BUG_ON(sizeof(union phy_table_tile) != sizeof(struct phy_cfg_pair)); 1202 1203 for (; p < end; p++) { 1204 if (p->cond.pos) { 1205 switch (p->cond.branch) { 1206 case BRANCH_ENDIF: 1207 is_matched = true; 1208 is_skipped = false; 1209 break; 1210 case BRANCH_ELSE: 1211 is_matched = is_skipped ? false : true; 1212 break; 1213 case BRANCH_IF: 1214 case BRANCH_ELIF: 1215 default: 1216 pos_cond = p->cond; 1217 pos_cond2 = p->cond2; 1218 break; 1219 } 1220 } else if (p->cond.neg) { 1221 if (!is_skipped) { 1222 if (check_positive(rtwdev, pos_cond, pos_cond2)) { 1223 is_matched = true; 1224 is_skipped = true; 1225 } else { 1226 is_matched = false; 1227 is_skipped = false; 1228 } 1229 } else { 1230 is_matched = false; 1231 } 1232 } else if (is_matched) { 1233 (*tbl->do_cfg)(rtwdev, tbl, p->cfg.addr, p->cfg.data); 1234 } 1235 } 1236 } 1237 EXPORT_SYMBOL(rtw_parse_tbl_phy_cond); 1238 1239 #define bcd_to_dec_pwr_by_rate(val, i) bcd2bin(val >> (i * 8)) 1240 1241 static u8 tbl_to_dec_pwr_by_rate(struct rtw_dev *rtwdev, u32 hex, u8 i) 1242 { 1243 if (rtwdev->chip->is_pwr_by_rate_dec) 1244 return bcd_to_dec_pwr_by_rate(hex, i); 1245 1246 return (hex >> (i * 8)) & 0xFF; 1247 } 1248 1249 static void 1250 rtw_phy_get_rate_values_of_txpwr_by_rate(struct rtw_dev *rtwdev, 1251 u32 addr, u32 mask, u32 val, u8 *rate, 1252 u8 *pwr_by_rate, u8 *rate_num) 1253 { 1254 int i; 1255 1256 switch (addr) { 1257 case 0xE00: 1258 case 0x830: 1259 rate[0] = DESC_RATE6M; 1260 rate[1] = DESC_RATE9M; 1261 rate[2] = DESC_RATE12M; 1262 rate[3] = DESC_RATE18M; 1263 for (i = 0; i < 4; ++i) 1264 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1265 *rate_num = 4; 1266 break; 1267 case 0xE04: 1268 case 0x834: 1269 rate[0] = DESC_RATE24M; 1270 rate[1] = DESC_RATE36M; 1271 rate[2] = DESC_RATE48M; 1272 rate[3] = DESC_RATE54M; 1273 for (i = 0; i < 4; ++i) 1274 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1275 *rate_num = 4; 1276 break; 1277 case 0xE08: 1278 rate[0] = DESC_RATE1M; 1279 pwr_by_rate[0] = bcd_to_dec_pwr_by_rate(val, 1); 1280 *rate_num = 1; 1281 break; 1282 case 0x86C: 1283 if (mask == 0xffffff00) { 1284 rate[0] = DESC_RATE2M; 1285 rate[1] = DESC_RATE5_5M; 1286 rate[2] = DESC_RATE11M; 1287 for (i = 1; i < 4; ++i) 1288 pwr_by_rate[i - 1] = 1289 tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1290 *rate_num = 3; 1291 } else if (mask == 0x000000ff) { 1292 rate[0] = DESC_RATE11M; 1293 pwr_by_rate[0] = bcd_to_dec_pwr_by_rate(val, 0); 1294 *rate_num = 1; 1295 } 1296 break; 1297 case 0xE10: 1298 case 0x83C: 1299 rate[0] = DESC_RATEMCS0; 1300 rate[1] = DESC_RATEMCS1; 1301 rate[2] = DESC_RATEMCS2; 1302 rate[3] = DESC_RATEMCS3; 1303 for (i = 0; i < 4; ++i) 1304 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1305 *rate_num = 4; 1306 break; 1307 case 0xE14: 1308 case 0x848: 1309 rate[0] = DESC_RATEMCS4; 1310 rate[1] = DESC_RATEMCS5; 1311 rate[2] = DESC_RATEMCS6; 1312 rate[3] = DESC_RATEMCS7; 1313 for (i = 0; i < 4; ++i) 1314 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1315 *rate_num = 4; 1316 break; 1317 case 0xE18: 1318 case 0x84C: 1319 rate[0] = DESC_RATEMCS8; 1320 rate[1] = DESC_RATEMCS9; 1321 rate[2] = DESC_RATEMCS10; 1322 rate[3] = DESC_RATEMCS11; 1323 for (i = 0; i < 4; ++i) 1324 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1325 *rate_num = 4; 1326 break; 1327 case 0xE1C: 1328 case 0x868: 1329 rate[0] = DESC_RATEMCS12; 1330 rate[1] = DESC_RATEMCS13; 1331 rate[2] = DESC_RATEMCS14; 1332 rate[3] = DESC_RATEMCS15; 1333 for (i = 0; i < 4; ++i) 1334 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1335 *rate_num = 4; 1336 break; 1337 case 0x838: 1338 rate[0] = DESC_RATE1M; 1339 rate[1] = DESC_RATE2M; 1340 rate[2] = DESC_RATE5_5M; 1341 for (i = 1; i < 4; ++i) 1342 pwr_by_rate[i - 1] = tbl_to_dec_pwr_by_rate(rtwdev, 1343 val, i); 1344 *rate_num = 3; 1345 break; 1346 case 0xC20: 1347 case 0xE20: 1348 case 0x1820: 1349 case 0x1A20: 1350 rate[0] = DESC_RATE1M; 1351 rate[1] = DESC_RATE2M; 1352 rate[2] = DESC_RATE5_5M; 1353 rate[3] = DESC_RATE11M; 1354 for (i = 0; i < 4; ++i) 1355 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1356 *rate_num = 4; 1357 break; 1358 case 0xC24: 1359 case 0xE24: 1360 case 0x1824: 1361 case 0x1A24: 1362 rate[0] = DESC_RATE6M; 1363 rate[1] = DESC_RATE9M; 1364 rate[2] = DESC_RATE12M; 1365 rate[3] = DESC_RATE18M; 1366 for (i = 0; i < 4; ++i) 1367 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1368 *rate_num = 4; 1369 break; 1370 case 0xC28: 1371 case 0xE28: 1372 case 0x1828: 1373 case 0x1A28: 1374 rate[0] = DESC_RATE24M; 1375 rate[1] = DESC_RATE36M; 1376 rate[2] = DESC_RATE48M; 1377 rate[3] = DESC_RATE54M; 1378 for (i = 0; i < 4; ++i) 1379 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1380 *rate_num = 4; 1381 break; 1382 case 0xC2C: 1383 case 0xE2C: 1384 case 0x182C: 1385 case 0x1A2C: 1386 rate[0] = DESC_RATEMCS0; 1387 rate[1] = DESC_RATEMCS1; 1388 rate[2] = DESC_RATEMCS2; 1389 rate[3] = DESC_RATEMCS3; 1390 for (i = 0; i < 4; ++i) 1391 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1392 *rate_num = 4; 1393 break; 1394 case 0xC30: 1395 case 0xE30: 1396 case 0x1830: 1397 case 0x1A30: 1398 rate[0] = DESC_RATEMCS4; 1399 rate[1] = DESC_RATEMCS5; 1400 rate[2] = DESC_RATEMCS6; 1401 rate[3] = DESC_RATEMCS7; 1402 for (i = 0; i < 4; ++i) 1403 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1404 *rate_num = 4; 1405 break; 1406 case 0xC34: 1407 case 0xE34: 1408 case 0x1834: 1409 case 0x1A34: 1410 rate[0] = DESC_RATEMCS8; 1411 rate[1] = DESC_RATEMCS9; 1412 rate[2] = DESC_RATEMCS10; 1413 rate[3] = DESC_RATEMCS11; 1414 for (i = 0; i < 4; ++i) 1415 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1416 *rate_num = 4; 1417 break; 1418 case 0xC38: 1419 case 0xE38: 1420 case 0x1838: 1421 case 0x1A38: 1422 rate[0] = DESC_RATEMCS12; 1423 rate[1] = DESC_RATEMCS13; 1424 rate[2] = DESC_RATEMCS14; 1425 rate[3] = DESC_RATEMCS15; 1426 for (i = 0; i < 4; ++i) 1427 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1428 *rate_num = 4; 1429 break; 1430 case 0xC3C: 1431 case 0xE3C: 1432 case 0x183C: 1433 case 0x1A3C: 1434 rate[0] = DESC_RATEVHT1SS_MCS0; 1435 rate[1] = DESC_RATEVHT1SS_MCS1; 1436 rate[2] = DESC_RATEVHT1SS_MCS2; 1437 rate[3] = DESC_RATEVHT1SS_MCS3; 1438 for (i = 0; i < 4; ++i) 1439 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1440 *rate_num = 4; 1441 break; 1442 case 0xC40: 1443 case 0xE40: 1444 case 0x1840: 1445 case 0x1A40: 1446 rate[0] = DESC_RATEVHT1SS_MCS4; 1447 rate[1] = DESC_RATEVHT1SS_MCS5; 1448 rate[2] = DESC_RATEVHT1SS_MCS6; 1449 rate[3] = DESC_RATEVHT1SS_MCS7; 1450 for (i = 0; i < 4; ++i) 1451 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1452 *rate_num = 4; 1453 break; 1454 case 0xC44: 1455 case 0xE44: 1456 case 0x1844: 1457 case 0x1A44: 1458 rate[0] = DESC_RATEVHT1SS_MCS8; 1459 rate[1] = DESC_RATEVHT1SS_MCS9; 1460 rate[2] = DESC_RATEVHT2SS_MCS0; 1461 rate[3] = DESC_RATEVHT2SS_MCS1; 1462 for (i = 0; i < 4; ++i) 1463 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1464 *rate_num = 4; 1465 break; 1466 case 0xC48: 1467 case 0xE48: 1468 case 0x1848: 1469 case 0x1A48: 1470 rate[0] = DESC_RATEVHT2SS_MCS2; 1471 rate[1] = DESC_RATEVHT2SS_MCS3; 1472 rate[2] = DESC_RATEVHT2SS_MCS4; 1473 rate[3] = DESC_RATEVHT2SS_MCS5; 1474 for (i = 0; i < 4; ++i) 1475 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1476 *rate_num = 4; 1477 break; 1478 case 0xC4C: 1479 case 0xE4C: 1480 case 0x184C: 1481 case 0x1A4C: 1482 rate[0] = DESC_RATEVHT2SS_MCS6; 1483 rate[1] = DESC_RATEVHT2SS_MCS7; 1484 rate[2] = DESC_RATEVHT2SS_MCS8; 1485 rate[3] = DESC_RATEVHT2SS_MCS9; 1486 for (i = 0; i < 4; ++i) 1487 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1488 *rate_num = 4; 1489 break; 1490 case 0xCD8: 1491 case 0xED8: 1492 case 0x18D8: 1493 case 0x1AD8: 1494 rate[0] = DESC_RATEMCS16; 1495 rate[1] = DESC_RATEMCS17; 1496 rate[2] = DESC_RATEMCS18; 1497 rate[3] = DESC_RATEMCS19; 1498 for (i = 0; i < 4; ++i) 1499 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1500 *rate_num = 4; 1501 break; 1502 case 0xCDC: 1503 case 0xEDC: 1504 case 0x18DC: 1505 case 0x1ADC: 1506 rate[0] = DESC_RATEMCS20; 1507 rate[1] = DESC_RATEMCS21; 1508 rate[2] = DESC_RATEMCS22; 1509 rate[3] = DESC_RATEMCS23; 1510 for (i = 0; i < 4; ++i) 1511 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1512 *rate_num = 4; 1513 break; 1514 case 0xCE0: 1515 case 0xEE0: 1516 case 0x18E0: 1517 case 0x1AE0: 1518 rate[0] = DESC_RATEVHT3SS_MCS0; 1519 rate[1] = DESC_RATEVHT3SS_MCS1; 1520 rate[2] = DESC_RATEVHT3SS_MCS2; 1521 rate[3] = DESC_RATEVHT3SS_MCS3; 1522 for (i = 0; i < 4; ++i) 1523 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1524 *rate_num = 4; 1525 break; 1526 case 0xCE4: 1527 case 0xEE4: 1528 case 0x18E4: 1529 case 0x1AE4: 1530 rate[0] = DESC_RATEVHT3SS_MCS4; 1531 rate[1] = DESC_RATEVHT3SS_MCS5; 1532 rate[2] = DESC_RATEVHT3SS_MCS6; 1533 rate[3] = DESC_RATEVHT3SS_MCS7; 1534 for (i = 0; i < 4; ++i) 1535 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1536 *rate_num = 4; 1537 break; 1538 case 0xCE8: 1539 case 0xEE8: 1540 case 0x18E8: 1541 case 0x1AE8: 1542 rate[0] = DESC_RATEVHT3SS_MCS8; 1543 rate[1] = DESC_RATEVHT3SS_MCS9; 1544 for (i = 0; i < 2; ++i) 1545 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i); 1546 *rate_num = 2; 1547 break; 1548 default: 1549 rtw_warn(rtwdev, "invalid tx power index addr 0x%08x\n", addr); 1550 break; 1551 } 1552 } 1553 1554 static void rtw_phy_store_tx_power_by_rate(struct rtw_dev *rtwdev, 1555 u32 band, u32 rfpath, u32 txnum, 1556 u32 regaddr, u32 bitmask, u32 data) 1557 { 1558 struct rtw_hal *hal = &rtwdev->hal; 1559 u8 rate_num = 0; 1560 u8 rate; 1561 u8 rates[RTW_RF_PATH_MAX] = {0}; 1562 s8 offset; 1563 s8 pwr_by_rate[RTW_RF_PATH_MAX] = {0}; 1564 int i; 1565 1566 rtw_phy_get_rate_values_of_txpwr_by_rate(rtwdev, regaddr, bitmask, data, 1567 rates, pwr_by_rate, &rate_num); 1568 1569 if (WARN_ON(rfpath >= RTW_RF_PATH_MAX || 1570 (band != PHY_BAND_2G && band != PHY_BAND_5G) || 1571 rate_num > RTW_RF_PATH_MAX)) 1572 return; 1573 1574 for (i = 0; i < rate_num; i++) { 1575 offset = pwr_by_rate[i]; 1576 rate = rates[i]; 1577 if (band == PHY_BAND_2G) 1578 hal->tx_pwr_by_rate_offset_2g[rfpath][rate] = offset; 1579 else 1580 hal->tx_pwr_by_rate_offset_5g[rfpath][rate] = offset; 1581 } 1582 } 1583 1584 void rtw_parse_tbl_bb_pg(struct rtw_dev *rtwdev, const struct rtw_table *tbl) 1585 { 1586 const struct rtw_phy_pg_cfg_pair *p = tbl->data; 1587 const struct rtw_phy_pg_cfg_pair *end = p + tbl->size; 1588 1589 for (; p < end; p++) { 1590 if (p->addr == 0xfe || p->addr == 0xffe) { 1591 msleep(50); 1592 continue; 1593 } 1594 rtw_phy_store_tx_power_by_rate(rtwdev, p->band, p->rf_path, 1595 p->tx_num, p->addr, p->bitmask, 1596 p->data); 1597 } 1598 } 1599 EXPORT_SYMBOL(rtw_parse_tbl_bb_pg); 1600 1601 static const u8 rtw_channel_idx_5g[RTW_MAX_CHANNEL_NUM_5G] = { 1602 36, 38, 40, 42, 44, 46, 48, /* Band 1 */ 1603 52, 54, 56, 58, 60, 62, 64, /* Band 2 */ 1604 100, 102, 104, 106, 108, 110, 112, /* Band 3 */ 1605 116, 118, 120, 122, 124, 126, 128, /* Band 3 */ 1606 132, 134, 136, 138, 140, 142, 144, /* Band 3 */ 1607 149, 151, 153, 155, 157, 159, 161, /* Band 4 */ 1608 165, 167, 169, 171, 173, 175, 177}; /* Band 4 */ 1609 1610 static int rtw_channel_to_idx(u8 band, u8 channel) 1611 { 1612 int ch_idx; 1613 u8 n_channel; 1614 1615 if (band == PHY_BAND_2G) { 1616 ch_idx = channel - 1; 1617 n_channel = RTW_MAX_CHANNEL_NUM_2G; 1618 } else if (band == PHY_BAND_5G) { 1619 n_channel = RTW_MAX_CHANNEL_NUM_5G; 1620 for (ch_idx = 0; ch_idx < n_channel; ch_idx++) 1621 if (rtw_channel_idx_5g[ch_idx] == channel) 1622 break; 1623 } else { 1624 return -1; 1625 } 1626 1627 if (ch_idx >= n_channel) 1628 return -1; 1629 1630 return ch_idx; 1631 } 1632 1633 static void rtw_phy_set_tx_power_limit(struct rtw_dev *rtwdev, u8 regd, u8 band, 1634 u8 bw, u8 rs, u8 ch, s8 pwr_limit) 1635 { 1636 struct rtw_hal *hal = &rtwdev->hal; 1637 u8 max_power_index = rtwdev->chip->max_power_index; 1638 s8 ww; 1639 int ch_idx; 1640 1641 pwr_limit = clamp_t(s8, pwr_limit, 1642 -max_power_index, max_power_index); 1643 ch_idx = rtw_channel_to_idx(band, ch); 1644 1645 if (regd >= RTW_REGD_MAX || bw >= RTW_CHANNEL_WIDTH_MAX || 1646 rs >= RTW_RATE_SECTION_NUM || ch_idx < 0) { 1647 WARN(1, 1648 "wrong txpwr_lmt regd=%u, band=%u bw=%u, rs=%u, ch_idx=%u, pwr_limit=%d\n", 1649 regd, band, bw, rs, ch_idx, pwr_limit); 1650 return; 1651 } 1652 1653 if (band == PHY_BAND_2G) { 1654 hal->tx_pwr_limit_2g[regd][bw][rs][ch_idx] = pwr_limit; 1655 ww = hal->tx_pwr_limit_2g[RTW_REGD_WW][bw][rs][ch_idx]; 1656 ww = min_t(s8, ww, pwr_limit); 1657 hal->tx_pwr_limit_2g[RTW_REGD_WW][bw][rs][ch_idx] = ww; 1658 } else if (band == PHY_BAND_5G) { 1659 hal->tx_pwr_limit_5g[regd][bw][rs][ch_idx] = pwr_limit; 1660 ww = hal->tx_pwr_limit_5g[RTW_REGD_WW][bw][rs][ch_idx]; 1661 ww = min_t(s8, ww, pwr_limit); 1662 hal->tx_pwr_limit_5g[RTW_REGD_WW][bw][rs][ch_idx] = ww; 1663 } 1664 } 1665 1666 /* cross-reference 5G power limits if values are not assigned */ 1667 static void 1668 rtw_xref_5g_txpwr_lmt(struct rtw_dev *rtwdev, u8 regd, 1669 u8 bw, u8 ch_idx, u8 rs_ht, u8 rs_vht) 1670 { 1671 struct rtw_hal *hal = &rtwdev->hal; 1672 u8 max_power_index = rtwdev->chip->max_power_index; 1673 s8 lmt_ht = hal->tx_pwr_limit_5g[regd][bw][rs_ht][ch_idx]; 1674 s8 lmt_vht = hal->tx_pwr_limit_5g[regd][bw][rs_vht][ch_idx]; 1675 1676 if (lmt_ht == lmt_vht) 1677 return; 1678 1679 if (lmt_ht == max_power_index) 1680 hal->tx_pwr_limit_5g[regd][bw][rs_ht][ch_idx] = lmt_vht; 1681 1682 else if (lmt_vht == max_power_index) 1683 hal->tx_pwr_limit_5g[regd][bw][rs_vht][ch_idx] = lmt_ht; 1684 } 1685 1686 /* cross-reference power limits for ht and vht */ 1687 static void 1688 rtw_xref_txpwr_lmt_by_rs(struct rtw_dev *rtwdev, u8 regd, u8 bw, u8 ch_idx) 1689 { 1690 static const u8 rs_cmp[4][2] = { 1691 {RTW_RATE_SECTION_HT_1S, RTW_RATE_SECTION_VHT_1S}, 1692 {RTW_RATE_SECTION_HT_2S, RTW_RATE_SECTION_VHT_2S}, 1693 {RTW_RATE_SECTION_HT_3S, RTW_RATE_SECTION_VHT_3S}, 1694 {RTW_RATE_SECTION_HT_4S, RTW_RATE_SECTION_VHT_4S} 1695 }; 1696 u8 rs_idx, rs_ht, rs_vht; 1697 1698 for (rs_idx = 0; rs_idx < 4; rs_idx++) { 1699 rs_ht = rs_cmp[rs_idx][0]; 1700 rs_vht = rs_cmp[rs_idx][1]; 1701 1702 rtw_xref_5g_txpwr_lmt(rtwdev, regd, bw, ch_idx, rs_ht, rs_vht); 1703 } 1704 } 1705 1706 /* cross-reference power limits for 5G channels */ 1707 static void 1708 rtw_xref_5g_txpwr_lmt_by_ch(struct rtw_dev *rtwdev, u8 regd, u8 bw) 1709 { 1710 u8 ch_idx; 1711 1712 for (ch_idx = 0; ch_idx < RTW_MAX_CHANNEL_NUM_5G; ch_idx++) 1713 rtw_xref_txpwr_lmt_by_rs(rtwdev, regd, bw, ch_idx); 1714 } 1715 1716 /* cross-reference power limits for 20/40M bandwidth */ 1717 static void 1718 rtw_xref_txpwr_lmt_by_bw(struct rtw_dev *rtwdev, u8 regd) 1719 { 1720 u8 bw; 1721 1722 for (bw = RTW_CHANNEL_WIDTH_20; bw <= RTW_CHANNEL_WIDTH_40; bw++) 1723 rtw_xref_5g_txpwr_lmt_by_ch(rtwdev, regd, bw); 1724 } 1725 1726 /* cross-reference power limits */ 1727 static void rtw_xref_txpwr_lmt(struct rtw_dev *rtwdev) 1728 { 1729 u8 regd; 1730 1731 for (regd = 0; regd < RTW_REGD_MAX; regd++) 1732 rtw_xref_txpwr_lmt_by_bw(rtwdev, regd); 1733 } 1734 1735 static void 1736 __cfg_txpwr_lmt_by_alt(struct rtw_hal *hal, u8 regd, u8 regd_alt, u8 bw, u8 rs) 1737 { 1738 u8 ch; 1739 1740 for (ch = 0; ch < RTW_MAX_CHANNEL_NUM_2G; ch++) 1741 hal->tx_pwr_limit_2g[regd][bw][rs][ch] = 1742 hal->tx_pwr_limit_2g[regd_alt][bw][rs][ch]; 1743 1744 for (ch = 0; ch < RTW_MAX_CHANNEL_NUM_5G; ch++) 1745 hal->tx_pwr_limit_5g[regd][bw][rs][ch] = 1746 hal->tx_pwr_limit_5g[regd_alt][bw][rs][ch]; 1747 } 1748 1749 static void 1750 rtw_cfg_txpwr_lmt_by_alt(struct rtw_dev *rtwdev, u8 regd, u8 regd_alt) 1751 { 1752 u8 bw, rs; 1753 1754 for (bw = 0; bw < RTW_CHANNEL_WIDTH_MAX; bw++) 1755 for (rs = 0; rs < RTW_RATE_SECTION_NUM; rs++) 1756 __cfg_txpwr_lmt_by_alt(&rtwdev->hal, regd, regd_alt, 1757 bw, rs); 1758 } 1759 1760 void rtw_parse_tbl_txpwr_lmt(struct rtw_dev *rtwdev, 1761 const struct rtw_table *tbl) 1762 { 1763 const struct rtw_txpwr_lmt_cfg_pair *p = tbl->data; 1764 const struct rtw_txpwr_lmt_cfg_pair *end = p + tbl->size; 1765 u32 regd_cfg_flag = 0; 1766 u8 regd_alt; 1767 u8 i; 1768 1769 for (; p < end; p++) { 1770 regd_cfg_flag |= BIT(p->regd); 1771 rtw_phy_set_tx_power_limit(rtwdev, p->regd, p->band, 1772 p->bw, p->rs, p->ch, p->txpwr_lmt); 1773 } 1774 1775 for (i = 0; i < RTW_REGD_MAX; i++) { 1776 if (i == RTW_REGD_WW) 1777 continue; 1778 1779 if (regd_cfg_flag & BIT(i)) 1780 continue; 1781 1782 rtw_dbg(rtwdev, RTW_DBG_REGD, 1783 "txpwr regd %d does not be configured\n", i); 1784 1785 if (rtw_regd_has_alt(i, ®d_alt) && 1786 regd_cfg_flag & BIT(regd_alt)) { 1787 rtw_dbg(rtwdev, RTW_DBG_REGD, 1788 "cfg txpwr regd %d by regd %d as alternative\n", 1789 i, regd_alt); 1790 1791 rtw_cfg_txpwr_lmt_by_alt(rtwdev, i, regd_alt); 1792 continue; 1793 } 1794 1795 rtw_dbg(rtwdev, RTW_DBG_REGD, "cfg txpwr regd %d by WW\n", i); 1796 rtw_cfg_txpwr_lmt_by_alt(rtwdev, i, RTW_REGD_WW); 1797 } 1798 1799 rtw_xref_txpwr_lmt(rtwdev); 1800 } 1801 EXPORT_SYMBOL(rtw_parse_tbl_txpwr_lmt); 1802 1803 void rtw_phy_cfg_mac(struct rtw_dev *rtwdev, const struct rtw_table *tbl, 1804 u32 addr, u32 data) 1805 { 1806 rtw_write8(rtwdev, addr, data); 1807 } 1808 EXPORT_SYMBOL(rtw_phy_cfg_mac); 1809 1810 void rtw_phy_cfg_agc(struct rtw_dev *rtwdev, const struct rtw_table *tbl, 1811 u32 addr, u32 data) 1812 { 1813 rtw_write32(rtwdev, addr, data); 1814 } 1815 EXPORT_SYMBOL(rtw_phy_cfg_agc); 1816 1817 void rtw_phy_cfg_bb(struct rtw_dev *rtwdev, const struct rtw_table *tbl, 1818 u32 addr, u32 data) 1819 { 1820 if (addr == 0xfe) 1821 msleep(50); 1822 else if (addr == 0xfd) 1823 mdelay(5); 1824 else if (addr == 0xfc) 1825 mdelay(1); 1826 else if (addr == 0xfb) 1827 usleep_range(50, 60); 1828 else if (addr == 0xfa) 1829 udelay(5); 1830 else if (addr == 0xf9) 1831 udelay(1); 1832 else 1833 rtw_write32(rtwdev, addr, data); 1834 } 1835 EXPORT_SYMBOL(rtw_phy_cfg_bb); 1836 1837 void rtw_phy_cfg_rf(struct rtw_dev *rtwdev, const struct rtw_table *tbl, 1838 u32 addr, u32 data) 1839 { 1840 if (addr == 0xffe) { 1841 msleep(50); 1842 } else if (addr == 0xfe) { 1843 usleep_range(100, 110); 1844 } else { 1845 rtw_write_rf(rtwdev, tbl->rf_path, addr, RFREG_MASK, data); 1846 udelay(1); 1847 } 1848 } 1849 EXPORT_SYMBOL(rtw_phy_cfg_rf); 1850 1851 static void rtw_load_rfk_table(struct rtw_dev *rtwdev) 1852 { 1853 const struct rtw_chip_info *chip = rtwdev->chip; 1854 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 1855 1856 if (!chip->rfk_init_tbl) 1857 return; 1858 1859 rtw_write32_mask(rtwdev, 0x1e24, BIT(17), 0x1); 1860 rtw_write32_mask(rtwdev, 0x1cd0, BIT(28), 0x1); 1861 rtw_write32_mask(rtwdev, 0x1cd0, BIT(29), 0x1); 1862 rtw_write32_mask(rtwdev, 0x1cd0, BIT(30), 0x1); 1863 rtw_write32_mask(rtwdev, 0x1cd0, BIT(31), 0x0); 1864 1865 rtw_load_table(rtwdev, chip->rfk_init_tbl); 1866 1867 dpk_info->is_dpk_pwr_on = true; 1868 } 1869 1870 void rtw_phy_load_tables(struct rtw_dev *rtwdev) 1871 { 1872 const struct rtw_rfe_def *rfe_def = rtw_get_rfe_def(rtwdev); 1873 const struct rtw_chip_info *chip = rtwdev->chip; 1874 u8 rf_path; 1875 1876 rtw_load_table(rtwdev, chip->mac_tbl); 1877 rtw_load_table(rtwdev, chip->bb_tbl); 1878 rtw_load_table(rtwdev, chip->agc_tbl); 1879 if (rfe_def->agc_btg_tbl) 1880 rtw_load_table(rtwdev, rfe_def->agc_btg_tbl); 1881 rtw_load_rfk_table(rtwdev); 1882 1883 for (rf_path = 0; rf_path < rtwdev->hal.rf_path_num; rf_path++) { 1884 const struct rtw_table *tbl; 1885 1886 tbl = chip->rf_tbl[rf_path]; 1887 rtw_load_table(rtwdev, tbl); 1888 } 1889 } 1890 EXPORT_SYMBOL(rtw_phy_load_tables); 1891 1892 static u8 rtw_get_channel_group(u8 channel, u8 rate) 1893 { 1894 switch (channel) { 1895 default: 1896 WARN_ON(1); 1897 fallthrough; 1898 case 1: 1899 case 2: 1900 case 36: 1901 case 38: 1902 case 40: 1903 case 42: 1904 return 0; 1905 case 3: 1906 case 4: 1907 case 5: 1908 case 44: 1909 case 46: 1910 case 48: 1911 case 50: 1912 return 1; 1913 case 6: 1914 case 7: 1915 case 8: 1916 case 52: 1917 case 54: 1918 case 56: 1919 case 58: 1920 return 2; 1921 case 9: 1922 case 10: 1923 case 11: 1924 case 60: 1925 case 62: 1926 case 64: 1927 return 3; 1928 case 12: 1929 case 13: 1930 case 100: 1931 case 102: 1932 case 104: 1933 case 106: 1934 return 4; 1935 case 14: 1936 return rate <= DESC_RATE11M ? 5 : 4; 1937 case 108: 1938 case 110: 1939 case 112: 1940 case 114: 1941 return 5; 1942 case 116: 1943 case 118: 1944 case 120: 1945 case 122: 1946 return 6; 1947 case 124: 1948 case 126: 1949 case 128: 1950 case 130: 1951 return 7; 1952 case 132: 1953 case 134: 1954 case 136: 1955 case 138: 1956 return 8; 1957 case 140: 1958 case 142: 1959 case 144: 1960 return 9; 1961 case 149: 1962 case 151: 1963 case 153: 1964 case 155: 1965 return 10; 1966 case 157: 1967 case 159: 1968 case 161: 1969 return 11; 1970 case 165: 1971 case 167: 1972 case 169: 1973 case 171: 1974 return 12; 1975 case 173: 1976 case 175: 1977 case 177: 1978 return 13; 1979 } 1980 } 1981 1982 static s8 rtw_phy_get_dis_dpd_by_rate_diff(struct rtw_dev *rtwdev, u16 rate) 1983 { 1984 const struct rtw_chip_info *chip = rtwdev->chip; 1985 s8 dpd_diff = 0; 1986 1987 if (!chip->en_dis_dpd) 1988 return 0; 1989 1990 #define RTW_DPD_RATE_CHECK(_rate) \ 1991 case DESC_RATE ## _rate: \ 1992 if (DIS_DPD_RATE ## _rate & chip->dpd_ratemask) \ 1993 dpd_diff = -6 * chip->txgi_factor; \ 1994 break 1995 1996 switch (rate) { 1997 RTW_DPD_RATE_CHECK(6M); 1998 RTW_DPD_RATE_CHECK(9M); 1999 RTW_DPD_RATE_CHECK(MCS0); 2000 RTW_DPD_RATE_CHECK(MCS1); 2001 RTW_DPD_RATE_CHECK(MCS8); 2002 RTW_DPD_RATE_CHECK(MCS9); 2003 RTW_DPD_RATE_CHECK(VHT1SS_MCS0); 2004 RTW_DPD_RATE_CHECK(VHT1SS_MCS1); 2005 RTW_DPD_RATE_CHECK(VHT2SS_MCS0); 2006 RTW_DPD_RATE_CHECK(VHT2SS_MCS1); 2007 } 2008 #undef RTW_DPD_RATE_CHECK 2009 2010 return dpd_diff; 2011 } 2012 2013 static u8 rtw_phy_get_2g_tx_power_index(struct rtw_dev *rtwdev, 2014 struct rtw_2g_txpwr_idx *pwr_idx_2g, 2015 enum rtw_bandwidth bandwidth, 2016 u8 rate, u8 group) 2017 { 2018 const struct rtw_chip_info *chip = rtwdev->chip; 2019 bool above_2ss, above_3ss, above_4ss; 2020 u8 factor = chip->txgi_factor; 2021 bool mcs_rate; 2022 u8 tx_power; 2023 2024 if (rate <= DESC_RATE11M) 2025 tx_power = pwr_idx_2g->cck_base[group]; 2026 else 2027 tx_power = pwr_idx_2g->bw40_base[group]; 2028 2029 if (rate >= DESC_RATE6M && rate <= DESC_RATE54M) 2030 tx_power += pwr_idx_2g->ht_1s_diff.ofdm * factor; 2031 2032 mcs_rate = (rate >= DESC_RATEMCS0 && rate <= DESC_RATEMCS31) || 2033 (rate >= DESC_RATEVHT1SS_MCS0 && 2034 rate <= DESC_RATEVHT4SS_MCS9); 2035 above_2ss = (rate >= DESC_RATEMCS8 && rate <= DESC_RATEMCS31) || 2036 (rate >= DESC_RATEVHT2SS_MCS0); 2037 above_3ss = (rate >= DESC_RATEMCS16 && rate <= DESC_RATEMCS31) || 2038 (rate >= DESC_RATEVHT3SS_MCS0); 2039 above_4ss = (rate >= DESC_RATEMCS24 && rate <= DESC_RATEMCS31) || 2040 (rate >= DESC_RATEVHT4SS_MCS0); 2041 2042 if (!mcs_rate) 2043 return tx_power; 2044 2045 switch (bandwidth) { 2046 default: 2047 WARN_ON(1); 2048 fallthrough; 2049 case RTW_CHANNEL_WIDTH_20: 2050 tx_power += pwr_idx_2g->ht_1s_diff.bw20 * factor; 2051 if (above_2ss) 2052 tx_power += pwr_idx_2g->ht_2s_diff.bw20 * factor; 2053 if (above_3ss) 2054 tx_power += pwr_idx_2g->ht_3s_diff.bw20 * factor; 2055 if (above_4ss) 2056 tx_power += pwr_idx_2g->ht_4s_diff.bw20 * factor; 2057 break; 2058 case RTW_CHANNEL_WIDTH_40: 2059 /* bw40 is the base power */ 2060 if (above_2ss) 2061 tx_power += pwr_idx_2g->ht_2s_diff.bw40 * factor; 2062 if (above_3ss) 2063 tx_power += pwr_idx_2g->ht_3s_diff.bw40 * factor; 2064 if (above_4ss) 2065 tx_power += pwr_idx_2g->ht_4s_diff.bw40 * factor; 2066 break; 2067 } 2068 2069 return tx_power; 2070 } 2071 2072 static u8 rtw_phy_get_5g_tx_power_index(struct rtw_dev *rtwdev, 2073 struct rtw_5g_txpwr_idx *pwr_idx_5g, 2074 enum rtw_bandwidth bandwidth, 2075 u8 rate, u8 group) 2076 { 2077 const struct rtw_chip_info *chip = rtwdev->chip; 2078 bool above_2ss, above_3ss, above_4ss; 2079 u8 factor = chip->txgi_factor; 2080 u8 upper, lower; 2081 bool mcs_rate; 2082 u8 tx_power; 2083 2084 tx_power = pwr_idx_5g->bw40_base[group]; 2085 2086 mcs_rate = (rate >= DESC_RATEMCS0 && rate <= DESC_RATEMCS31) || 2087 (rate >= DESC_RATEVHT1SS_MCS0 && 2088 rate <= DESC_RATEVHT4SS_MCS9); 2089 above_2ss = (rate >= DESC_RATEMCS8 && rate <= DESC_RATEMCS31) || 2090 (rate >= DESC_RATEVHT2SS_MCS0); 2091 above_3ss = (rate >= DESC_RATEMCS16 && rate <= DESC_RATEMCS31) || 2092 (rate >= DESC_RATEVHT3SS_MCS0); 2093 above_4ss = (rate >= DESC_RATEMCS24 && rate <= DESC_RATEMCS31) || 2094 (rate >= DESC_RATEVHT4SS_MCS0); 2095 2096 if (!mcs_rate) { 2097 tx_power += pwr_idx_5g->ht_1s_diff.ofdm * factor; 2098 return tx_power; 2099 } 2100 2101 switch (bandwidth) { 2102 default: 2103 WARN_ON(1); 2104 fallthrough; 2105 case RTW_CHANNEL_WIDTH_20: 2106 tx_power += pwr_idx_5g->ht_1s_diff.bw20 * factor; 2107 if (above_2ss) 2108 tx_power += pwr_idx_5g->ht_2s_diff.bw20 * factor; 2109 if (above_3ss) 2110 tx_power += pwr_idx_5g->ht_3s_diff.bw20 * factor; 2111 if (above_4ss) 2112 tx_power += pwr_idx_5g->ht_4s_diff.bw20 * factor; 2113 break; 2114 case RTW_CHANNEL_WIDTH_40: 2115 /* bw40 is the base power */ 2116 if (above_2ss) 2117 tx_power += pwr_idx_5g->ht_2s_diff.bw40 * factor; 2118 if (above_3ss) 2119 tx_power += pwr_idx_5g->ht_3s_diff.bw40 * factor; 2120 if (above_4ss) 2121 tx_power += pwr_idx_5g->ht_4s_diff.bw40 * factor; 2122 break; 2123 case RTW_CHANNEL_WIDTH_80: 2124 /* the base idx of bw80 is the average of bw40+/bw40- */ 2125 lower = pwr_idx_5g->bw40_base[group]; 2126 upper = pwr_idx_5g->bw40_base[group + 1]; 2127 2128 tx_power = (lower + upper) / 2; 2129 tx_power += pwr_idx_5g->vht_1s_diff.bw80 * factor; 2130 if (above_2ss) 2131 tx_power += pwr_idx_5g->vht_2s_diff.bw80 * factor; 2132 if (above_3ss) 2133 tx_power += pwr_idx_5g->vht_3s_diff.bw80 * factor; 2134 if (above_4ss) 2135 tx_power += pwr_idx_5g->vht_4s_diff.bw80 * factor; 2136 break; 2137 } 2138 2139 return tx_power; 2140 } 2141 2142 /* return RTW_RATE_SECTION_NUM to indicate rate is invalid */ 2143 static u8 rtw_phy_rate_to_rate_section(u8 rate) 2144 { 2145 if (rate >= DESC_RATE1M && rate <= DESC_RATE11M) 2146 return RTW_RATE_SECTION_CCK; 2147 else if (rate >= DESC_RATE6M && rate <= DESC_RATE54M) 2148 return RTW_RATE_SECTION_OFDM; 2149 else if (rate >= DESC_RATEMCS0 && rate <= DESC_RATEMCS7) 2150 return RTW_RATE_SECTION_HT_1S; 2151 else if (rate >= DESC_RATEMCS8 && rate <= DESC_RATEMCS15) 2152 return RTW_RATE_SECTION_HT_2S; 2153 else if (rate >= DESC_RATEMCS16 && rate <= DESC_RATEMCS23) 2154 return RTW_RATE_SECTION_HT_3S; 2155 else if (rate >= DESC_RATEMCS24 && rate <= DESC_RATEMCS31) 2156 return RTW_RATE_SECTION_HT_4S; 2157 else if (rate >= DESC_RATEVHT1SS_MCS0 && rate <= DESC_RATEVHT1SS_MCS9) 2158 return RTW_RATE_SECTION_VHT_1S; 2159 else if (rate >= DESC_RATEVHT2SS_MCS0 && rate <= DESC_RATEVHT2SS_MCS9) 2160 return RTW_RATE_SECTION_VHT_2S; 2161 else if (rate >= DESC_RATEVHT3SS_MCS0 && rate <= DESC_RATEVHT3SS_MCS9) 2162 return RTW_RATE_SECTION_VHT_3S; 2163 else if (rate >= DESC_RATEVHT4SS_MCS0 && rate <= DESC_RATEVHT4SS_MCS9) 2164 return RTW_RATE_SECTION_VHT_4S; 2165 else 2166 return RTW_RATE_SECTION_NUM; 2167 } 2168 2169 static s8 rtw_phy_get_tx_power_limit(struct rtw_dev *rtwdev, u8 band, 2170 enum rtw_bandwidth bw, u8 rf_path, 2171 u8 rate, u8 channel, u8 regd) 2172 { 2173 struct rtw_hal *hal = &rtwdev->hal; 2174 u8 *cch_by_bw = hal->cch_by_bw; 2175 s8 power_limit = (s8)rtwdev->chip->max_power_index; 2176 u8 rs = rtw_phy_rate_to_rate_section(rate); 2177 int ch_idx; 2178 u8 cur_bw, cur_ch; 2179 s8 cur_lmt; 2180 2181 if (regd > RTW_REGD_WW) 2182 return power_limit; 2183 2184 if (rs == RTW_RATE_SECTION_NUM) 2185 goto err; 2186 2187 /* only 20M BW with cck and ofdm */ 2188 if (rs == RTW_RATE_SECTION_CCK || rs == RTW_RATE_SECTION_OFDM) 2189 bw = RTW_CHANNEL_WIDTH_20; 2190 2191 /* only 20/40M BW with ht */ 2192 if (rate >= DESC_RATEMCS0 && rate <= DESC_RATEMCS31) 2193 bw = min_t(u8, bw, RTW_CHANNEL_WIDTH_40); 2194 2195 /* select min power limit among [20M BW ~ current BW] */ 2196 for (cur_bw = RTW_CHANNEL_WIDTH_20; cur_bw <= bw; cur_bw++) { 2197 cur_ch = cch_by_bw[cur_bw]; 2198 2199 ch_idx = rtw_channel_to_idx(band, cur_ch); 2200 if (ch_idx < 0) 2201 goto err; 2202 2203 cur_lmt = cur_ch <= RTW_MAX_CHANNEL_NUM_2G ? 2204 hal->tx_pwr_limit_2g[regd][cur_bw][rs][ch_idx] : 2205 hal->tx_pwr_limit_5g[regd][cur_bw][rs][ch_idx]; 2206 2207 power_limit = min_t(s8, cur_lmt, power_limit); 2208 } 2209 2210 return power_limit; 2211 2212 err: 2213 WARN(1, "invalid arguments, band=%d, bw=%d, path=%d, rate=%d, ch=%d\n", 2214 band, bw, rf_path, rate, channel); 2215 return (s8)rtwdev->chip->max_power_index; 2216 } 2217 2218 static s8 rtw_phy_get_tx_power_sar(struct rtw_dev *rtwdev, u8 sar_band, 2219 u8 rf_path, u8 rate) 2220 { 2221 u8 rs = rtw_phy_rate_to_rate_section(rate); 2222 struct rtw_sar_arg arg = { 2223 .sar_band = sar_band, 2224 .path = rf_path, 2225 .rs = rs, 2226 }; 2227 2228 if (rs == RTW_RATE_SECTION_NUM) 2229 goto err; 2230 2231 return rtw_query_sar(rtwdev, &arg); 2232 2233 err: 2234 WARN(1, "invalid arguments, sar_band=%d, path=%d, rate=%d\n", 2235 sar_band, rf_path, rate); 2236 return (s8)rtwdev->chip->max_power_index; 2237 } 2238 2239 void rtw_get_tx_power_params(struct rtw_dev *rtwdev, u8 path, u8 rate, u8 bw, 2240 u8 ch, u8 regd, struct rtw_power_params *pwr_param) 2241 { 2242 struct rtw_hal *hal = &rtwdev->hal; 2243 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 2244 struct rtw_txpwr_idx *pwr_idx; 2245 u8 group, band; 2246 u8 *base = &pwr_param->pwr_base; 2247 s8 *offset = &pwr_param->pwr_offset; 2248 s8 *limit = &pwr_param->pwr_limit; 2249 s8 *remnant = &pwr_param->pwr_remnant; 2250 s8 *sar = &pwr_param->pwr_sar; 2251 2252 pwr_idx = &rtwdev->efuse.txpwr_idx_table[path]; 2253 group = rtw_get_channel_group(ch, rate); 2254 2255 /* base power index for 2.4G/5G */ 2256 if (IS_CH_2G_BAND(ch)) { 2257 band = PHY_BAND_2G; 2258 *base = rtw_phy_get_2g_tx_power_index(rtwdev, 2259 &pwr_idx->pwr_idx_2g, 2260 bw, rate, group); 2261 *offset = hal->tx_pwr_by_rate_offset_2g[path][rate]; 2262 } else { 2263 band = PHY_BAND_5G; 2264 *base = rtw_phy_get_5g_tx_power_index(rtwdev, 2265 &pwr_idx->pwr_idx_5g, 2266 bw, rate, group); 2267 *offset = hal->tx_pwr_by_rate_offset_5g[path][rate]; 2268 } 2269 2270 *limit = rtw_phy_get_tx_power_limit(rtwdev, band, bw, path, 2271 rate, ch, regd); 2272 *remnant = rate <= DESC_RATE11M ? dm_info->txagc_remnant_cck : 2273 dm_info->txagc_remnant_ofdm[path]; 2274 *sar = rtw_phy_get_tx_power_sar(rtwdev, hal->sar_band, path, rate); 2275 } 2276 2277 u8 2278 rtw_phy_get_tx_power_index(struct rtw_dev *rtwdev, u8 rf_path, u8 rate, 2279 enum rtw_bandwidth bandwidth, u8 channel, u8 regd) 2280 { 2281 struct rtw_power_params pwr_param = {0}; 2282 u8 tx_power; 2283 s8 offset; 2284 2285 rtw_get_tx_power_params(rtwdev, rf_path, rate, bandwidth, 2286 channel, regd, &pwr_param); 2287 2288 tx_power = pwr_param.pwr_base; 2289 offset = min3(pwr_param.pwr_offset, 2290 pwr_param.pwr_limit, 2291 pwr_param.pwr_sar); 2292 2293 if (rtwdev->chip->en_dis_dpd) 2294 offset += rtw_phy_get_dis_dpd_by_rate_diff(rtwdev, rate); 2295 2296 tx_power += offset + pwr_param.pwr_remnant; 2297 2298 if (tx_power > rtwdev->chip->max_power_index) 2299 tx_power = rtwdev->chip->max_power_index; 2300 2301 return tx_power; 2302 } 2303 EXPORT_SYMBOL(rtw_phy_get_tx_power_index); 2304 2305 static void rtw_phy_set_tx_power_index_by_rs(struct rtw_dev *rtwdev, 2306 u8 ch, u8 path, u8 rs) 2307 { 2308 struct rtw_hal *hal = &rtwdev->hal; 2309 u8 regd = rtw_regd_get(rtwdev); 2310 const u8 *rates; 2311 u8 size; 2312 u8 rate; 2313 u8 pwr_idx; 2314 u8 bw; 2315 int i; 2316 2317 if (rs >= RTW_RATE_SECTION_NUM) 2318 return; 2319 2320 rates = rtw_rate_section[rs]; 2321 size = rtw_rate_size[rs]; 2322 bw = hal->current_band_width; 2323 for (i = 0; i < size; i++) { 2324 rate = rates[i]; 2325 pwr_idx = rtw_phy_get_tx_power_index(rtwdev, path, rate, 2326 bw, ch, regd); 2327 hal->tx_pwr_tbl[path][rate] = pwr_idx; 2328 } 2329 } 2330 2331 /* set tx power level by path for each rates, note that the order of the rates 2332 * are *very* important, bacause 8822B/8821C combines every four bytes of tx 2333 * power index into a four-byte power index register, and calls set_tx_agc to 2334 * write these values into hardware 2335 */ 2336 static void rtw_phy_set_tx_power_level_by_path(struct rtw_dev *rtwdev, 2337 u8 ch, u8 path) 2338 { 2339 struct rtw_hal *hal = &rtwdev->hal; 2340 u8 rs; 2341 2342 /* do not need cck rates if we are not in 2.4G */ 2343 if (hal->current_band_type == RTW_BAND_2G) 2344 rs = RTW_RATE_SECTION_CCK; 2345 else 2346 rs = RTW_RATE_SECTION_OFDM; 2347 2348 for (; rs < RTW_RATE_SECTION_NUM; rs++) 2349 rtw_phy_set_tx_power_index_by_rs(rtwdev, ch, path, rs); 2350 } 2351 2352 void rtw_phy_set_tx_power_level(struct rtw_dev *rtwdev, u8 channel) 2353 { 2354 const struct rtw_chip_info *chip = rtwdev->chip; 2355 struct rtw_hal *hal = &rtwdev->hal; 2356 u8 path; 2357 2358 mutex_lock(&hal->tx_power_mutex); 2359 2360 for (path = 0; path < hal->rf_path_num; path++) 2361 rtw_phy_set_tx_power_level_by_path(rtwdev, channel, path); 2362 2363 chip->ops->set_tx_power_index(rtwdev); 2364 mutex_unlock(&hal->tx_power_mutex); 2365 } 2366 EXPORT_SYMBOL(rtw_phy_set_tx_power_level); 2367 2368 static void 2369 rtw_phy_tx_power_by_rate_config_by_path(struct rtw_hal *hal, u8 path, 2370 u8 rs, u8 size, const u8 *rates) 2371 { 2372 u8 rate; 2373 u8 base_idx, rate_idx; 2374 s8 base_2g, base_5g; 2375 2376 if (size == 10) /* VHT rates */ 2377 base_idx = rates[size - 3]; 2378 else 2379 base_idx = rates[size - 1]; 2380 base_2g = hal->tx_pwr_by_rate_offset_2g[path][base_idx]; 2381 base_5g = hal->tx_pwr_by_rate_offset_5g[path][base_idx]; 2382 hal->tx_pwr_by_rate_base_2g[path][rs] = base_2g; 2383 hal->tx_pwr_by_rate_base_5g[path][rs] = base_5g; 2384 for (rate = 0; rate < size; rate++) { 2385 rate_idx = rates[rate]; 2386 hal->tx_pwr_by_rate_offset_2g[path][rate_idx] -= base_2g; 2387 hal->tx_pwr_by_rate_offset_5g[path][rate_idx] -= base_5g; 2388 } 2389 } 2390 2391 void rtw_phy_tx_power_by_rate_config(struct rtw_hal *hal) 2392 { 2393 u8 path, rs; 2394 2395 for (path = 0; path < RTW_RF_PATH_MAX; path++) 2396 for (rs = 0; rs < RTW_RATE_SECTION_NUM; rs++) 2397 rtw_phy_tx_power_by_rate_config_by_path(hal, path, rs, 2398 rtw_rate_size[rs], rtw_rate_section[rs]); 2399 } 2400 2401 static void 2402 __rtw_phy_tx_power_limit_config(struct rtw_hal *hal, u8 regd, u8 bw, u8 rs) 2403 { 2404 s8 base; 2405 u8 ch; 2406 2407 for (ch = 0; ch < RTW_MAX_CHANNEL_NUM_2G; ch++) { 2408 base = hal->tx_pwr_by_rate_base_2g[0][rs]; 2409 hal->tx_pwr_limit_2g[regd][bw][rs][ch] -= base; 2410 } 2411 2412 for (ch = 0; ch < RTW_MAX_CHANNEL_NUM_5G; ch++) { 2413 base = hal->tx_pwr_by_rate_base_5g[0][rs]; 2414 hal->tx_pwr_limit_5g[regd][bw][rs][ch] -= base; 2415 } 2416 } 2417 2418 void rtw_phy_tx_power_limit_config(struct rtw_hal *hal) 2419 { 2420 u8 regd, bw, rs; 2421 2422 /* default at channel 1 */ 2423 hal->cch_by_bw[RTW_CHANNEL_WIDTH_20] = 1; 2424 2425 for (regd = 0; regd < RTW_REGD_MAX; regd++) 2426 for (bw = 0; bw < RTW_CHANNEL_WIDTH_MAX; bw++) 2427 for (rs = 0; rs < RTW_RATE_SECTION_NUM; rs++) 2428 __rtw_phy_tx_power_limit_config(hal, regd, bw, rs); 2429 } 2430 2431 static void rtw_phy_init_tx_power_limit(struct rtw_dev *rtwdev, 2432 u8 regd, u8 bw, u8 rs) 2433 { 2434 struct rtw_hal *hal = &rtwdev->hal; 2435 s8 max_power_index = (s8)rtwdev->chip->max_power_index; 2436 u8 ch; 2437 2438 /* 2.4G channels */ 2439 for (ch = 0; ch < RTW_MAX_CHANNEL_NUM_2G; ch++) 2440 hal->tx_pwr_limit_2g[regd][bw][rs][ch] = max_power_index; 2441 2442 /* 5G channels */ 2443 for (ch = 0; ch < RTW_MAX_CHANNEL_NUM_5G; ch++) 2444 hal->tx_pwr_limit_5g[regd][bw][rs][ch] = max_power_index; 2445 } 2446 2447 void rtw_phy_init_tx_power(struct rtw_dev *rtwdev) 2448 { 2449 struct rtw_hal *hal = &rtwdev->hal; 2450 u8 regd, path, rate, rs, bw; 2451 2452 /* init tx power by rate offset */ 2453 for (path = 0; path < RTW_RF_PATH_MAX; path++) { 2454 for (rate = 0; rate < DESC_RATE_MAX; rate++) { 2455 hal->tx_pwr_by_rate_offset_2g[path][rate] = 0; 2456 hal->tx_pwr_by_rate_offset_5g[path][rate] = 0; 2457 } 2458 } 2459 2460 /* init tx power limit */ 2461 for (regd = 0; regd < RTW_REGD_MAX; regd++) 2462 for (bw = 0; bw < RTW_CHANNEL_WIDTH_MAX; bw++) 2463 for (rs = 0; rs < RTW_RATE_SECTION_NUM; rs++) 2464 rtw_phy_init_tx_power_limit(rtwdev, regd, bw, 2465 rs); 2466 } 2467 2468 void rtw_phy_config_swing_table(struct rtw_dev *rtwdev, 2469 struct rtw_swing_table *swing_table) 2470 { 2471 const struct rtw_rfe_def *rfe_def = rtw_get_rfe_def(rtwdev); 2472 const struct rtw_pwr_track_tbl *tbl = rfe_def->pwr_track_tbl; 2473 u8 channel = rtwdev->hal.current_channel; 2474 2475 if (IS_CH_2G_BAND(channel)) { 2476 if (rtwdev->dm_info.tx_rate <= DESC_RATE11M) { 2477 swing_table->p[RF_PATH_A] = tbl->pwrtrk_2g_ccka_p; 2478 swing_table->n[RF_PATH_A] = tbl->pwrtrk_2g_ccka_n; 2479 swing_table->p[RF_PATH_B] = tbl->pwrtrk_2g_cckb_p; 2480 swing_table->n[RF_PATH_B] = tbl->pwrtrk_2g_cckb_n; 2481 swing_table->p[RF_PATH_C] = tbl->pwrtrk_2g_cckc_p; 2482 swing_table->n[RF_PATH_C] = tbl->pwrtrk_2g_cckc_n; 2483 swing_table->p[RF_PATH_D] = tbl->pwrtrk_2g_cckd_p; 2484 swing_table->n[RF_PATH_D] = tbl->pwrtrk_2g_cckd_n; 2485 } else { 2486 swing_table->p[RF_PATH_A] = tbl->pwrtrk_2ga_p; 2487 swing_table->n[RF_PATH_A] = tbl->pwrtrk_2ga_n; 2488 swing_table->p[RF_PATH_B] = tbl->pwrtrk_2gb_p; 2489 swing_table->n[RF_PATH_B] = tbl->pwrtrk_2gb_n; 2490 swing_table->p[RF_PATH_C] = tbl->pwrtrk_2gc_p; 2491 swing_table->n[RF_PATH_C] = tbl->pwrtrk_2gc_n; 2492 swing_table->p[RF_PATH_D] = tbl->pwrtrk_2gd_p; 2493 swing_table->n[RF_PATH_D] = tbl->pwrtrk_2gd_n; 2494 } 2495 } else if (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel)) { 2496 swing_table->p[RF_PATH_A] = tbl->pwrtrk_5ga_p[RTW_PWR_TRK_5G_1]; 2497 swing_table->n[RF_PATH_A] = tbl->pwrtrk_5ga_n[RTW_PWR_TRK_5G_1]; 2498 swing_table->p[RF_PATH_B] = tbl->pwrtrk_5gb_p[RTW_PWR_TRK_5G_1]; 2499 swing_table->n[RF_PATH_B] = tbl->pwrtrk_5gb_n[RTW_PWR_TRK_5G_1]; 2500 swing_table->p[RF_PATH_C] = tbl->pwrtrk_5gc_p[RTW_PWR_TRK_5G_1]; 2501 swing_table->n[RF_PATH_C] = tbl->pwrtrk_5gc_n[RTW_PWR_TRK_5G_1]; 2502 swing_table->p[RF_PATH_D] = tbl->pwrtrk_5gd_p[RTW_PWR_TRK_5G_1]; 2503 swing_table->n[RF_PATH_D] = tbl->pwrtrk_5gd_n[RTW_PWR_TRK_5G_1]; 2504 } else if (IS_CH_5G_BAND_3(channel)) { 2505 swing_table->p[RF_PATH_A] = tbl->pwrtrk_5ga_p[RTW_PWR_TRK_5G_2]; 2506 swing_table->n[RF_PATH_A] = tbl->pwrtrk_5ga_n[RTW_PWR_TRK_5G_2]; 2507 swing_table->p[RF_PATH_B] = tbl->pwrtrk_5gb_p[RTW_PWR_TRK_5G_2]; 2508 swing_table->n[RF_PATH_B] = tbl->pwrtrk_5gb_n[RTW_PWR_TRK_5G_2]; 2509 swing_table->p[RF_PATH_C] = tbl->pwrtrk_5gc_p[RTW_PWR_TRK_5G_2]; 2510 swing_table->n[RF_PATH_C] = tbl->pwrtrk_5gc_n[RTW_PWR_TRK_5G_2]; 2511 swing_table->p[RF_PATH_D] = tbl->pwrtrk_5gd_p[RTW_PWR_TRK_5G_2]; 2512 swing_table->n[RF_PATH_D] = tbl->pwrtrk_5gd_n[RTW_PWR_TRK_5G_2]; 2513 } else if (IS_CH_5G_BAND_4(channel)) { 2514 swing_table->p[RF_PATH_A] = tbl->pwrtrk_5ga_p[RTW_PWR_TRK_5G_3]; 2515 swing_table->n[RF_PATH_A] = tbl->pwrtrk_5ga_n[RTW_PWR_TRK_5G_3]; 2516 swing_table->p[RF_PATH_B] = tbl->pwrtrk_5gb_p[RTW_PWR_TRK_5G_3]; 2517 swing_table->n[RF_PATH_B] = tbl->pwrtrk_5gb_n[RTW_PWR_TRK_5G_3]; 2518 swing_table->p[RF_PATH_C] = tbl->pwrtrk_5gc_p[RTW_PWR_TRK_5G_3]; 2519 swing_table->n[RF_PATH_C] = tbl->pwrtrk_5gc_n[RTW_PWR_TRK_5G_3]; 2520 swing_table->p[RF_PATH_D] = tbl->pwrtrk_5gd_p[RTW_PWR_TRK_5G_3]; 2521 swing_table->n[RF_PATH_D] = tbl->pwrtrk_5gd_n[RTW_PWR_TRK_5G_3]; 2522 } else { 2523 swing_table->p[RF_PATH_A] = tbl->pwrtrk_2ga_p; 2524 swing_table->n[RF_PATH_A] = tbl->pwrtrk_2ga_n; 2525 swing_table->p[RF_PATH_B] = tbl->pwrtrk_2gb_p; 2526 swing_table->n[RF_PATH_B] = tbl->pwrtrk_2gb_n; 2527 swing_table->p[RF_PATH_C] = tbl->pwrtrk_2gc_p; 2528 swing_table->n[RF_PATH_C] = tbl->pwrtrk_2gc_n; 2529 swing_table->p[RF_PATH_D] = tbl->pwrtrk_2gd_p; 2530 swing_table->n[RF_PATH_D] = tbl->pwrtrk_2gd_n; 2531 } 2532 } 2533 EXPORT_SYMBOL(rtw_phy_config_swing_table); 2534 2535 void rtw_phy_pwrtrack_avg(struct rtw_dev *rtwdev, u8 thermal, u8 path) 2536 { 2537 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 2538 2539 ewma_thermal_add(&dm_info->avg_thermal[path], thermal); 2540 dm_info->thermal_avg[path] = 2541 ewma_thermal_read(&dm_info->avg_thermal[path]); 2542 } 2543 EXPORT_SYMBOL(rtw_phy_pwrtrack_avg); 2544 2545 bool rtw_phy_pwrtrack_thermal_changed(struct rtw_dev *rtwdev, u8 thermal, 2546 u8 path) 2547 { 2548 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 2549 u8 avg = ewma_thermal_read(&dm_info->avg_thermal[path]); 2550 2551 if (avg == thermal) 2552 return false; 2553 2554 return true; 2555 } 2556 EXPORT_SYMBOL(rtw_phy_pwrtrack_thermal_changed); 2557 2558 u8 rtw_phy_pwrtrack_get_delta(struct rtw_dev *rtwdev, u8 path) 2559 { 2560 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 2561 u8 therm_avg, therm_efuse, therm_delta; 2562 2563 therm_avg = dm_info->thermal_avg[path]; 2564 therm_efuse = rtwdev->efuse.thermal_meter[path]; 2565 therm_delta = abs(therm_avg - therm_efuse); 2566 2567 return min_t(u8, therm_delta, RTW_PWR_TRK_TBL_SZ - 1); 2568 } 2569 EXPORT_SYMBOL(rtw_phy_pwrtrack_get_delta); 2570 2571 s8 rtw_phy_pwrtrack_get_pwridx(struct rtw_dev *rtwdev, 2572 struct rtw_swing_table *swing_table, 2573 u8 tbl_path, u8 therm_path, u8 delta) 2574 { 2575 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 2576 const u8 *delta_swing_table_idx_pos; 2577 const u8 *delta_swing_table_idx_neg; 2578 2579 if (delta >= RTW_PWR_TRK_TBL_SZ) { 2580 rtw_warn(rtwdev, "power track table overflow\n"); 2581 return 0; 2582 } 2583 2584 if (!swing_table) { 2585 rtw_warn(rtwdev, "swing table not configured\n"); 2586 return 0; 2587 } 2588 2589 delta_swing_table_idx_pos = swing_table->p[tbl_path]; 2590 delta_swing_table_idx_neg = swing_table->n[tbl_path]; 2591 2592 if (!delta_swing_table_idx_pos || !delta_swing_table_idx_neg) { 2593 rtw_warn(rtwdev, "invalid swing table index\n"); 2594 return 0; 2595 } 2596 2597 if (dm_info->thermal_avg[therm_path] > 2598 rtwdev->efuse.thermal_meter[therm_path]) 2599 return delta_swing_table_idx_pos[delta]; 2600 else 2601 return -delta_swing_table_idx_neg[delta]; 2602 } 2603 EXPORT_SYMBOL(rtw_phy_pwrtrack_get_pwridx); 2604 2605 bool rtw_phy_pwrtrack_need_lck(struct rtw_dev *rtwdev) 2606 { 2607 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 2608 u8 delta_lck; 2609 2610 delta_lck = abs(dm_info->thermal_avg[0] - dm_info->thermal_meter_lck); 2611 if (delta_lck >= rtwdev->chip->lck_threshold) { 2612 dm_info->thermal_meter_lck = dm_info->thermal_avg[0]; 2613 return true; 2614 } 2615 return false; 2616 } 2617 EXPORT_SYMBOL(rtw_phy_pwrtrack_need_lck); 2618 2619 bool rtw_phy_pwrtrack_need_iqk(struct rtw_dev *rtwdev) 2620 { 2621 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 2622 u8 delta_iqk; 2623 2624 delta_iqk = abs(dm_info->thermal_avg[0] - dm_info->thermal_meter_k); 2625 if (delta_iqk >= rtwdev->chip->iqk_threshold) { 2626 dm_info->thermal_meter_k = dm_info->thermal_avg[0]; 2627 return true; 2628 } 2629 return false; 2630 } 2631 EXPORT_SYMBOL(rtw_phy_pwrtrack_need_iqk); 2632 2633 static void rtw_phy_set_tx_path_by_reg(struct rtw_dev *rtwdev, 2634 enum rtw_bb_path tx_path_sel_1ss) 2635 { 2636 struct rtw_path_div *path_div = &rtwdev->dm_path_div; 2637 enum rtw_bb_path tx_path_sel_cck = tx_path_sel_1ss; 2638 const struct rtw_chip_info *chip = rtwdev->chip; 2639 2640 if (tx_path_sel_1ss == path_div->current_tx_path) 2641 return; 2642 2643 path_div->current_tx_path = tx_path_sel_1ss; 2644 rtw_dbg(rtwdev, RTW_DBG_PATH_DIV, "Switch TX path=%s\n", 2645 tx_path_sel_1ss == BB_PATH_A ? "A" : "B"); 2646 chip->ops->config_tx_path(rtwdev, rtwdev->hal.antenna_tx, 2647 tx_path_sel_1ss, tx_path_sel_cck, false); 2648 } 2649 2650 static void rtw_phy_tx_path_div_select(struct rtw_dev *rtwdev) 2651 { 2652 struct rtw_path_div *path_div = &rtwdev->dm_path_div; 2653 enum rtw_bb_path path = path_div->current_tx_path; 2654 s32 rssi_a = 0, rssi_b = 0; 2655 2656 if (path_div->path_a_cnt) 2657 rssi_a = path_div->path_a_sum / path_div->path_a_cnt; 2658 else 2659 rssi_a = 0; 2660 if (path_div->path_b_cnt) 2661 rssi_b = path_div->path_b_sum / path_div->path_b_cnt; 2662 else 2663 rssi_b = 0; 2664 2665 if (rssi_a != rssi_b) 2666 path = (rssi_a > rssi_b) ? BB_PATH_A : BB_PATH_B; 2667 2668 path_div->path_a_cnt = 0; 2669 path_div->path_a_sum = 0; 2670 path_div->path_b_cnt = 0; 2671 path_div->path_b_sum = 0; 2672 rtw_phy_set_tx_path_by_reg(rtwdev, path); 2673 } 2674 2675 static void rtw_phy_tx_path_diversity_2ss(struct rtw_dev *rtwdev) 2676 { 2677 if (rtwdev->hal.antenna_rx != BB_PATH_AB) { 2678 rtw_dbg(rtwdev, RTW_DBG_PATH_DIV, 2679 "[Return] tx_Path_en=%d, rx_Path_en=%d\n", 2680 rtwdev->hal.antenna_tx, rtwdev->hal.antenna_rx); 2681 return; 2682 } 2683 if (rtwdev->sta_cnt == 0) { 2684 rtw_dbg(rtwdev, RTW_DBG_PATH_DIV, "No Link\n"); 2685 return; 2686 } 2687 2688 rtw_phy_tx_path_div_select(rtwdev); 2689 } 2690 2691 void rtw_phy_tx_path_diversity(struct rtw_dev *rtwdev) 2692 { 2693 const struct rtw_chip_info *chip = rtwdev->chip; 2694 2695 if (!chip->path_div_supported) 2696 return; 2697 2698 rtw_phy_tx_path_diversity_2ss(rtwdev); 2699 } 2700