1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
3 */
4
5 #include <linux/bcd.h>
6
7 #include "main.h"
8 #include "reg.h"
9 #include "fw.h"
10 #include "phy.h"
11 #include "debug.h"
12 #include "regd.h"
13 #include "sar.h"
14
15 struct phy_cfg_pair {
16 u32 addr;
17 u32 data;
18 };
19
20 union phy_table_tile {
21 struct {
22 struct rtw_phy_cond cond;
23 struct rtw_phy_cond2 cond2;
24 } __packed;
25 struct phy_cfg_pair cfg;
26 };
27
28 static const u32 db_invert_table[12][8] = {
29 {10, 13, 16, 20,
30 25, 32, 40, 50},
31 {64, 80, 101, 128,
32 160, 201, 256, 318},
33 {401, 505, 635, 800,
34 1007, 1268, 1596, 2010},
35 {316, 398, 501, 631,
36 794, 1000, 1259, 1585},
37 {1995, 2512, 3162, 3981,
38 5012, 6310, 7943, 10000},
39 {12589, 15849, 19953, 25119,
40 31623, 39811, 50119, 63098},
41 {79433, 100000, 125893, 158489,
42 199526, 251189, 316228, 398107},
43 {501187, 630957, 794328, 1000000,
44 1258925, 1584893, 1995262, 2511886},
45 {3162278, 3981072, 5011872, 6309573,
46 7943282, 1000000, 12589254, 15848932},
47 {19952623, 25118864, 31622777, 39810717,
48 50118723, 63095734, 79432823, 100000000},
49 {125892541, 158489319, 199526232, 251188643,
50 316227766, 398107171, 501187234, 630957345},
51 {794328235, 1000000000, 1258925412, 1584893192,
52 1995262315, 2511886432U, 3162277660U, 3981071706U}
53 };
54
55 const u8 rtw_cck_rates[] = { DESC_RATE1M, DESC_RATE2M, DESC_RATE5_5M, DESC_RATE11M };
56
57 const u8 rtw_ofdm_rates[] = {
58 DESC_RATE6M, DESC_RATE9M, DESC_RATE12M,
59 DESC_RATE18M, DESC_RATE24M, DESC_RATE36M,
60 DESC_RATE48M, DESC_RATE54M
61 };
62
63 const u8 rtw_ht_1s_rates[] = {
64 DESC_RATEMCS0, DESC_RATEMCS1, DESC_RATEMCS2,
65 DESC_RATEMCS3, DESC_RATEMCS4, DESC_RATEMCS5,
66 DESC_RATEMCS6, DESC_RATEMCS7
67 };
68
69 const u8 rtw_ht_2s_rates[] = {
70 DESC_RATEMCS8, DESC_RATEMCS9, DESC_RATEMCS10,
71 DESC_RATEMCS11, DESC_RATEMCS12, DESC_RATEMCS13,
72 DESC_RATEMCS14, DESC_RATEMCS15
73 };
74
75 const u8 rtw_vht_1s_rates[] = {
76 DESC_RATEVHT1SS_MCS0, DESC_RATEVHT1SS_MCS1,
77 DESC_RATEVHT1SS_MCS2, DESC_RATEVHT1SS_MCS3,
78 DESC_RATEVHT1SS_MCS4, DESC_RATEVHT1SS_MCS5,
79 DESC_RATEVHT1SS_MCS6, DESC_RATEVHT1SS_MCS7,
80 DESC_RATEVHT1SS_MCS8, DESC_RATEVHT1SS_MCS9
81 };
82
83 const u8 rtw_vht_2s_rates[] = {
84 DESC_RATEVHT2SS_MCS0, DESC_RATEVHT2SS_MCS1,
85 DESC_RATEVHT2SS_MCS2, DESC_RATEVHT2SS_MCS3,
86 DESC_RATEVHT2SS_MCS4, DESC_RATEVHT2SS_MCS5,
87 DESC_RATEVHT2SS_MCS6, DESC_RATEVHT2SS_MCS7,
88 DESC_RATEVHT2SS_MCS8, DESC_RATEVHT2SS_MCS9
89 };
90
91 const u8 rtw_ht_3s_rates[] = {
92 DESC_RATEMCS16, DESC_RATEMCS17, DESC_RATEMCS18,
93 DESC_RATEMCS19, DESC_RATEMCS20, DESC_RATEMCS21,
94 DESC_RATEMCS22, DESC_RATEMCS23
95 };
96
97 const u8 rtw_ht_4s_rates[] = {
98 DESC_RATEMCS24, DESC_RATEMCS25, DESC_RATEMCS26,
99 DESC_RATEMCS27, DESC_RATEMCS28, DESC_RATEMCS29,
100 DESC_RATEMCS30, DESC_RATEMCS31
101 };
102
103 const u8 rtw_vht_3s_rates[] = {
104 DESC_RATEVHT3SS_MCS0, DESC_RATEVHT3SS_MCS1,
105 DESC_RATEVHT3SS_MCS2, DESC_RATEVHT3SS_MCS3,
106 DESC_RATEVHT3SS_MCS4, DESC_RATEVHT3SS_MCS5,
107 DESC_RATEVHT3SS_MCS6, DESC_RATEVHT3SS_MCS7,
108 DESC_RATEVHT3SS_MCS8, DESC_RATEVHT3SS_MCS9
109 };
110
111 const u8 rtw_vht_4s_rates[] = {
112 DESC_RATEVHT4SS_MCS0, DESC_RATEVHT4SS_MCS1,
113 DESC_RATEVHT4SS_MCS2, DESC_RATEVHT4SS_MCS3,
114 DESC_RATEVHT4SS_MCS4, DESC_RATEVHT4SS_MCS5,
115 DESC_RATEVHT4SS_MCS6, DESC_RATEVHT4SS_MCS7,
116 DESC_RATEVHT4SS_MCS8, DESC_RATEVHT4SS_MCS9
117 };
118
119 const u8 * const rtw_rate_section[RTW_RATE_SECTION_NUM] = {
120 rtw_cck_rates, rtw_ofdm_rates,
121 rtw_ht_1s_rates, rtw_ht_2s_rates,
122 rtw_vht_1s_rates, rtw_vht_2s_rates,
123 rtw_ht_3s_rates, rtw_ht_4s_rates,
124 rtw_vht_3s_rates, rtw_vht_4s_rates
125 };
126 EXPORT_SYMBOL(rtw_rate_section);
127
128 const u8 rtw_rate_size[RTW_RATE_SECTION_NUM] = {
129 ARRAY_SIZE(rtw_cck_rates),
130 ARRAY_SIZE(rtw_ofdm_rates),
131 ARRAY_SIZE(rtw_ht_1s_rates),
132 ARRAY_SIZE(rtw_ht_2s_rates),
133 ARRAY_SIZE(rtw_vht_1s_rates),
134 ARRAY_SIZE(rtw_vht_2s_rates),
135 ARRAY_SIZE(rtw_ht_3s_rates),
136 ARRAY_SIZE(rtw_ht_4s_rates),
137 ARRAY_SIZE(rtw_vht_3s_rates),
138 ARRAY_SIZE(rtw_vht_4s_rates)
139 };
140 EXPORT_SYMBOL(rtw_rate_size);
141
142 enum rtw_phy_band_type {
143 PHY_BAND_2G = 0,
144 PHY_BAND_5G = 1,
145 };
146
rtw_phy_cck_pd_init(struct rtw_dev * rtwdev)147 static void rtw_phy_cck_pd_init(struct rtw_dev *rtwdev)
148 {
149 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
150 u8 i, j;
151
152 for (i = 0; i <= RTW_CHANNEL_WIDTH_40; i++) {
153 for (j = 0; j < RTW_RF_PATH_MAX; j++)
154 dm_info->cck_pd_lv[i][j] = CCK_PD_LV0;
155 }
156
157 dm_info->cck_fa_avg = CCK_FA_AVG_RESET;
158 }
159
rtw_phy_set_edcca_th(struct rtw_dev * rtwdev,u8 l2h,u8 h2l)160 void rtw_phy_set_edcca_th(struct rtw_dev *rtwdev, u8 l2h, u8 h2l)
161 {
162 const struct rtw_hw_reg_offset *edcca_th = rtwdev->chip->edcca_th;
163
164 rtw_write32_mask(rtwdev,
165 edcca_th[EDCCA_TH_L2H_IDX].hw_reg.addr,
166 edcca_th[EDCCA_TH_L2H_IDX].hw_reg.mask,
167 l2h + edcca_th[EDCCA_TH_L2H_IDX].offset);
168 rtw_write32_mask(rtwdev,
169 edcca_th[EDCCA_TH_H2L_IDX].hw_reg.addr,
170 edcca_th[EDCCA_TH_H2L_IDX].hw_reg.mask,
171 h2l + edcca_th[EDCCA_TH_H2L_IDX].offset);
172 }
173 EXPORT_SYMBOL(rtw_phy_set_edcca_th);
174
rtw_phy_adaptivity_set_mode(struct rtw_dev * rtwdev)175 void rtw_phy_adaptivity_set_mode(struct rtw_dev *rtwdev)
176 {
177 const struct rtw_chip_info *chip = rtwdev->chip;
178 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
179
180 /* turn off in debugfs for debug usage */
181 if (!rtw_edcca_enabled) {
182 dm_info->edcca_mode = RTW_EDCCA_NORMAL;
183 rtw_dbg(rtwdev, RTW_DBG_PHY, "EDCCA disabled, cannot be set\n");
184 return;
185 }
186
187 switch (rtwdev->regd.dfs_region) {
188 case NL80211_DFS_ETSI:
189 dm_info->edcca_mode = RTW_EDCCA_ADAPTIVITY;
190 dm_info->l2h_th_ini = chip->l2h_th_ini_ad;
191 break;
192 case NL80211_DFS_JP:
193 dm_info->edcca_mode = RTW_EDCCA_ADAPTIVITY;
194 dm_info->l2h_th_ini = chip->l2h_th_ini_cs;
195 break;
196 default:
197 dm_info->edcca_mode = RTW_EDCCA_NORMAL;
198 break;
199 }
200 }
201
rtw_phy_adaptivity_init(struct rtw_dev * rtwdev)202 static void rtw_phy_adaptivity_init(struct rtw_dev *rtwdev)
203 {
204 const struct rtw_chip_info *chip = rtwdev->chip;
205
206 rtw_phy_adaptivity_set_mode(rtwdev);
207 if (chip->ops->adaptivity_init)
208 chip->ops->adaptivity_init(rtwdev);
209 }
210
rtw_phy_adaptivity(struct rtw_dev * rtwdev)211 static void rtw_phy_adaptivity(struct rtw_dev *rtwdev)
212 {
213 if (rtwdev->chip->ops->adaptivity)
214 rtwdev->chip->ops->adaptivity(rtwdev);
215 }
216
rtw_phy_cfo_init(struct rtw_dev * rtwdev)217 static void rtw_phy_cfo_init(struct rtw_dev *rtwdev)
218 {
219 const struct rtw_chip_info *chip = rtwdev->chip;
220
221 if (chip->ops->cfo_init)
222 chip->ops->cfo_init(rtwdev);
223 }
224
rtw_phy_tx_path_div_init(struct rtw_dev * rtwdev)225 static void rtw_phy_tx_path_div_init(struct rtw_dev *rtwdev)
226 {
227 struct rtw_path_div *path_div = &rtwdev->dm_path_div;
228
229 path_div->current_tx_path = rtwdev->chip->default_1ss_tx_path;
230 path_div->path_a_cnt = 0;
231 path_div->path_a_sum = 0;
232 path_div->path_b_cnt = 0;
233 path_div->path_b_sum = 0;
234 }
235
rtw_phy_init(struct rtw_dev * rtwdev)236 void rtw_phy_init(struct rtw_dev *rtwdev)
237 {
238 const struct rtw_chip_info *chip = rtwdev->chip;
239 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
240 u32 addr, mask;
241
242 dm_info->fa_history[3] = 0;
243 dm_info->fa_history[2] = 0;
244 dm_info->fa_history[1] = 0;
245 dm_info->fa_history[0] = 0;
246 dm_info->igi_bitmap = 0;
247 dm_info->igi_history[3] = 0;
248 dm_info->igi_history[2] = 0;
249 dm_info->igi_history[1] = 0;
250
251 addr = chip->dig[0].addr;
252 mask = chip->dig[0].mask;
253 dm_info->igi_history[0] = rtw_read32_mask(rtwdev, addr, mask);
254 rtw_phy_cck_pd_init(rtwdev);
255
256 dm_info->iqk.done = false;
257 rtw_phy_adaptivity_init(rtwdev);
258 rtw_phy_cfo_init(rtwdev);
259 rtw_phy_tx_path_div_init(rtwdev);
260 }
261 EXPORT_SYMBOL(rtw_phy_init);
262
rtw_phy_dig_write(struct rtw_dev * rtwdev,u8 igi)263 void rtw_phy_dig_write(struct rtw_dev *rtwdev, u8 igi)
264 {
265 const struct rtw_chip_info *chip = rtwdev->chip;
266 struct rtw_hal *hal = &rtwdev->hal;
267 u32 addr, mask;
268 u8 path;
269
270 if (chip->dig_cck) {
271 const struct rtw_hw_reg *dig_cck = &chip->dig_cck[0];
272 rtw_write32_mask(rtwdev, dig_cck->addr, dig_cck->mask, igi >> 1);
273 }
274
275 for (path = 0; path < hal->rf_path_num; path++) {
276 addr = chip->dig[path].addr;
277 mask = chip->dig[path].mask;
278 rtw_write32_mask(rtwdev, addr, mask, igi);
279 }
280 }
281
rtw_phy_stat_false_alarm(struct rtw_dev * rtwdev)282 static void rtw_phy_stat_false_alarm(struct rtw_dev *rtwdev)
283 {
284 const struct rtw_chip_info *chip = rtwdev->chip;
285
286 chip->ops->false_alarm_statistics(rtwdev);
287 }
288
289 #define RA_FLOOR_TABLE_SIZE 7
290 #define RA_FLOOR_UP_GAP 3
291
rtw_phy_get_rssi_level(u8 old_level,u8 rssi)292 static u8 rtw_phy_get_rssi_level(u8 old_level, u8 rssi)
293 {
294 u8 table[RA_FLOOR_TABLE_SIZE] = {20, 34, 38, 42, 46, 50, 100};
295 u8 new_level = 0;
296 int i;
297
298 for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++)
299 if (i >= old_level)
300 table[i] += RA_FLOOR_UP_GAP;
301
302 for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) {
303 if (rssi < table[i]) {
304 new_level = i;
305 break;
306 }
307 }
308
309 return new_level;
310 }
311
312 struct rtw_phy_stat_iter_data {
313 struct rtw_dev *rtwdev;
314 u8 min_rssi;
315 };
316
rtw_phy_stat_rssi_iter(void * data,struct ieee80211_sta * sta)317 static void rtw_phy_stat_rssi_iter(void *data, struct ieee80211_sta *sta)
318 {
319 struct rtw_phy_stat_iter_data *iter_data = data;
320 struct rtw_dev *rtwdev = iter_data->rtwdev;
321 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
322 u8 rssi;
323
324 rssi = ewma_rssi_read(&si->avg_rssi);
325 si->rssi_level = rtw_phy_get_rssi_level(si->rssi_level, rssi);
326
327 rtw_fw_send_rssi_info(rtwdev, si);
328
329 iter_data->min_rssi = min_t(u8, rssi, iter_data->min_rssi);
330 }
331
rtw_phy_stat_rssi(struct rtw_dev * rtwdev)332 static void rtw_phy_stat_rssi(struct rtw_dev *rtwdev)
333 {
334 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
335 struct rtw_phy_stat_iter_data data = {};
336
337 data.rtwdev = rtwdev;
338 data.min_rssi = U8_MAX;
339 rtw_iterate_stas(rtwdev, rtw_phy_stat_rssi_iter, &data);
340
341 dm_info->pre_min_rssi = dm_info->min_rssi;
342 dm_info->min_rssi = data.min_rssi;
343 }
344
rtw_phy_stat_rate_cnt(struct rtw_dev * rtwdev)345 static void rtw_phy_stat_rate_cnt(struct rtw_dev *rtwdev)
346 {
347 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
348
349 dm_info->last_pkt_count = dm_info->cur_pkt_count;
350 memset(&dm_info->cur_pkt_count, 0, sizeof(dm_info->cur_pkt_count));
351 }
352
rtw_phy_statistics(struct rtw_dev * rtwdev)353 static void rtw_phy_statistics(struct rtw_dev *rtwdev)
354 {
355 rtw_phy_stat_rssi(rtwdev);
356 rtw_phy_stat_false_alarm(rtwdev);
357 rtw_phy_stat_rate_cnt(rtwdev);
358 }
359
360 #define DIG_PERF_FA_TH_LOW 250
361 #define DIG_PERF_FA_TH_HIGH 500
362 #define DIG_PERF_FA_TH_EXTRA_HIGH 750
363 #define DIG_PERF_MAX 0x5a
364 #define DIG_PERF_MID 0x40
365 #define DIG_CVRG_FA_TH_LOW 2000
366 #define DIG_CVRG_FA_TH_HIGH 4000
367 #define DIG_CVRG_FA_TH_EXTRA_HIGH 5000
368 #define DIG_CVRG_MAX 0x2a
369 #define DIG_CVRG_MID 0x26
370 #define DIG_CVRG_MIN 0x1c
371 #define DIG_RSSI_GAIN_OFFSET 15
372
373 static bool
rtw_phy_dig_check_damping(struct rtw_dm_info * dm_info)374 rtw_phy_dig_check_damping(struct rtw_dm_info *dm_info)
375 {
376 u16 fa_lo = DIG_PERF_FA_TH_LOW;
377 u16 fa_hi = DIG_PERF_FA_TH_HIGH;
378 u16 *fa_history;
379 u8 *igi_history;
380 u8 damping_rssi;
381 u8 min_rssi;
382 u8 diff;
383 u8 igi_bitmap;
384 bool damping = false;
385
386 min_rssi = dm_info->min_rssi;
387 if (dm_info->damping) {
388 damping_rssi = dm_info->damping_rssi;
389 diff = min_rssi > damping_rssi ? min_rssi - damping_rssi :
390 damping_rssi - min_rssi;
391 if (diff > 3 || dm_info->damping_cnt++ > 20) {
392 dm_info->damping = false;
393 return false;
394 }
395
396 return true;
397 }
398
399 igi_history = dm_info->igi_history;
400 fa_history = dm_info->fa_history;
401 igi_bitmap = dm_info->igi_bitmap & 0xf;
402 switch (igi_bitmap) {
403 case 5:
404 /* down -> up -> down -> up */
405 if (igi_history[0] > igi_history[1] &&
406 igi_history[2] > igi_history[3] &&
407 igi_history[0] - igi_history[1] >= 2 &&
408 igi_history[2] - igi_history[3] >= 2 &&
409 fa_history[0] > fa_hi && fa_history[1] < fa_lo &&
410 fa_history[2] > fa_hi && fa_history[3] < fa_lo)
411 damping = true;
412 break;
413 case 9:
414 /* up -> down -> down -> up */
415 if (igi_history[0] > igi_history[1] &&
416 igi_history[3] > igi_history[2] &&
417 igi_history[0] - igi_history[1] >= 4 &&
418 igi_history[3] - igi_history[2] >= 2 &&
419 fa_history[0] > fa_hi && fa_history[1] < fa_lo &&
420 fa_history[2] < fa_lo && fa_history[3] > fa_hi)
421 damping = true;
422 break;
423 default:
424 return false;
425 }
426
427 if (damping) {
428 dm_info->damping = true;
429 dm_info->damping_cnt = 0;
430 dm_info->damping_rssi = min_rssi;
431 }
432
433 return damping;
434 }
435
rtw_phy_dig_get_boundary(struct rtw_dev * rtwdev,struct rtw_dm_info * dm_info,u8 * upper,u8 * lower,bool linked)436 static void rtw_phy_dig_get_boundary(struct rtw_dev *rtwdev,
437 struct rtw_dm_info *dm_info,
438 u8 *upper, u8 *lower, bool linked)
439 {
440 u8 dig_max, dig_min, dig_mid;
441 u8 min_rssi;
442
443 if (linked) {
444 dig_max = DIG_PERF_MAX;
445 dig_mid = DIG_PERF_MID;
446 dig_min = rtwdev->chip->dig_min;
447 min_rssi = max_t(u8, dm_info->min_rssi, dig_min);
448 } else {
449 dig_max = DIG_CVRG_MAX;
450 dig_mid = DIG_CVRG_MID;
451 dig_min = DIG_CVRG_MIN;
452 min_rssi = dig_min;
453 }
454
455 /* DIG MAX should be bounded by minimum RSSI with offset +15 */
456 dig_max = min_t(u8, dig_max, min_rssi + DIG_RSSI_GAIN_OFFSET);
457
458 *lower = clamp_t(u8, min_rssi, dig_min, dig_mid);
459 *upper = clamp_t(u8, *lower + DIG_RSSI_GAIN_OFFSET, dig_min, dig_max);
460 }
461
rtw_phy_dig_get_threshold(struct rtw_dm_info * dm_info,u16 * fa_th,u8 * step,bool linked)462 static void rtw_phy_dig_get_threshold(struct rtw_dm_info *dm_info,
463 u16 *fa_th, u8 *step, bool linked)
464 {
465 u8 min_rssi, pre_min_rssi;
466
467 min_rssi = dm_info->min_rssi;
468 pre_min_rssi = dm_info->pre_min_rssi;
469 step[0] = 4;
470 step[1] = 3;
471 step[2] = 2;
472
473 if (linked) {
474 fa_th[0] = DIG_PERF_FA_TH_EXTRA_HIGH;
475 fa_th[1] = DIG_PERF_FA_TH_HIGH;
476 fa_th[2] = DIG_PERF_FA_TH_LOW;
477 if (pre_min_rssi > min_rssi) {
478 step[0] = 6;
479 step[1] = 4;
480 step[2] = 2;
481 }
482 } else {
483 fa_th[0] = DIG_CVRG_FA_TH_EXTRA_HIGH;
484 fa_th[1] = DIG_CVRG_FA_TH_HIGH;
485 fa_th[2] = DIG_CVRG_FA_TH_LOW;
486 }
487 }
488
rtw_phy_dig_recorder(struct rtw_dm_info * dm_info,u8 igi,u16 fa)489 static void rtw_phy_dig_recorder(struct rtw_dm_info *dm_info, u8 igi, u16 fa)
490 {
491 u8 *igi_history;
492 u16 *fa_history;
493 u8 igi_bitmap;
494 bool up;
495
496 igi_bitmap = dm_info->igi_bitmap << 1 & 0xfe;
497 igi_history = dm_info->igi_history;
498 fa_history = dm_info->fa_history;
499
500 up = igi > igi_history[0];
501 igi_bitmap |= up;
502
503 igi_history[3] = igi_history[2];
504 igi_history[2] = igi_history[1];
505 igi_history[1] = igi_history[0];
506 igi_history[0] = igi;
507
508 fa_history[3] = fa_history[2];
509 fa_history[2] = fa_history[1];
510 fa_history[1] = fa_history[0];
511 fa_history[0] = fa;
512
513 dm_info->igi_bitmap = igi_bitmap;
514 }
515
rtw_phy_dig(struct rtw_dev * rtwdev)516 static void rtw_phy_dig(struct rtw_dev *rtwdev)
517 {
518 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
519 u8 upper_bound, lower_bound;
520 u8 pre_igi, cur_igi;
521 u16 fa_th[3], fa_cnt;
522 u8 level;
523 u8 step[3];
524 bool linked;
525
526 if (test_bit(RTW_FLAG_DIG_DISABLE, rtwdev->flags))
527 return;
528
529 if (rtw_phy_dig_check_damping(dm_info))
530 return;
531
532 linked = !!rtwdev->sta_cnt;
533
534 fa_cnt = dm_info->total_fa_cnt;
535 pre_igi = dm_info->igi_history[0];
536
537 rtw_phy_dig_get_threshold(dm_info, fa_th, step, linked);
538
539 /* test the false alarm count from the highest threshold level first,
540 * and increase it by corresponding step size
541 *
542 * note that the step size is offset by -2, compensate it afterall
543 */
544 cur_igi = pre_igi;
545 for (level = 0; level < 3; level++) {
546 if (fa_cnt > fa_th[level]) {
547 cur_igi += step[level];
548 break;
549 }
550 }
551 cur_igi -= 2;
552
553 /* calculate the upper/lower bound by the minimum rssi we have among
554 * the peers connected with us, meanwhile make sure the igi value does
555 * not beyond the hardware limitation
556 */
557 rtw_phy_dig_get_boundary(rtwdev, dm_info, &upper_bound, &lower_bound,
558 linked);
559 cur_igi = clamp_t(u8, cur_igi, lower_bound, upper_bound);
560
561 /* record current igi value and false alarm statistics for further
562 * damping checks, and record the trend of igi values
563 */
564 rtw_phy_dig_recorder(dm_info, cur_igi, fa_cnt);
565
566 /* Mitigate beacon loss and connectivity issues, mainly (only?)
567 * in the 5 GHz band
568 */
569 if (rtwdev->chip->id == RTW_CHIP_TYPE_8812A && rtwdev->beacon_loss &&
570 linked && dm_info->total_fa_cnt < DIG_PERF_FA_TH_EXTRA_HIGH)
571 cur_igi = DIG_CVRG_MIN;
572
573 if (cur_igi != pre_igi)
574 rtw_phy_dig_write(rtwdev, cur_igi);
575 }
576
rtw_phy_ra_info_update_iter(void * data,struct ieee80211_sta * sta)577 static void rtw_phy_ra_info_update_iter(void *data, struct ieee80211_sta *sta)
578 {
579 struct rtw_dev *rtwdev = data;
580 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
581
582 rtw_update_sta_info(rtwdev, si, false);
583 }
584
rtw_phy_ra_info_update(struct rtw_dev * rtwdev)585 static void rtw_phy_ra_info_update(struct rtw_dev *rtwdev)
586 {
587 if (rtwdev->watch_dog_cnt & 0x3)
588 return;
589
590 rtw_iterate_stas(rtwdev, rtw_phy_ra_info_update_iter, rtwdev);
591 }
592
rtw_phy_get_rrsr_mask(struct rtw_dev * rtwdev,u8 rate_idx)593 static u32 rtw_phy_get_rrsr_mask(struct rtw_dev *rtwdev, u8 rate_idx)
594 {
595 u8 rate_order;
596
597 rate_order = rate_idx;
598
599 if (rate_idx >= DESC_RATEVHT4SS_MCS0)
600 rate_order -= DESC_RATEVHT4SS_MCS0;
601 else if (rate_idx >= DESC_RATEVHT3SS_MCS0)
602 rate_order -= DESC_RATEVHT3SS_MCS0;
603 else if (rate_idx >= DESC_RATEVHT2SS_MCS0)
604 rate_order -= DESC_RATEVHT2SS_MCS0;
605 else if (rate_idx >= DESC_RATEVHT1SS_MCS0)
606 rate_order -= DESC_RATEVHT1SS_MCS0;
607 else if (rate_idx >= DESC_RATEMCS24)
608 rate_order -= DESC_RATEMCS24;
609 else if (rate_idx >= DESC_RATEMCS16)
610 rate_order -= DESC_RATEMCS16;
611 else if (rate_idx >= DESC_RATEMCS8)
612 rate_order -= DESC_RATEMCS8;
613 else if (rate_idx >= DESC_RATEMCS0)
614 rate_order -= DESC_RATEMCS0;
615 else if (rate_idx >= DESC_RATE6M)
616 rate_order -= DESC_RATE6M;
617 else
618 rate_order -= DESC_RATE1M;
619
620 if (rate_idx >= DESC_RATEMCS0 || rate_order == 0)
621 rate_order++;
622
623 return GENMASK(rate_order + RRSR_RATE_ORDER_CCK_LEN - 1, 0);
624 }
625
rtw_phy_rrsr_mask_min_iter(void * data,struct ieee80211_sta * sta)626 static void rtw_phy_rrsr_mask_min_iter(void *data, struct ieee80211_sta *sta)
627 {
628 struct rtw_dev *rtwdev = (struct rtw_dev *)data;
629 struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv;
630 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
631 u32 mask = 0;
632
633 mask = rtw_phy_get_rrsr_mask(rtwdev, si->ra_report.desc_rate);
634 if (mask < dm_info->rrsr_mask_min)
635 dm_info->rrsr_mask_min = mask;
636 }
637
rtw_phy_rrsr_update(struct rtw_dev * rtwdev)638 static void rtw_phy_rrsr_update(struct rtw_dev *rtwdev)
639 {
640 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
641
642 dm_info->rrsr_mask_min = RRSR_RATE_ORDER_MAX;
643 rtw_iterate_stas(rtwdev, rtw_phy_rrsr_mask_min_iter, rtwdev);
644 rtw_write32(rtwdev, REG_RRSR, dm_info->rrsr_val_init & dm_info->rrsr_mask_min);
645 }
646
rtw_phy_dpk_track(struct rtw_dev * rtwdev)647 static void rtw_phy_dpk_track(struct rtw_dev *rtwdev)
648 {
649 const struct rtw_chip_info *chip = rtwdev->chip;
650
651 if (chip->ops->dpk_track)
652 chip->ops->dpk_track(rtwdev);
653 }
654
655 struct rtw_rx_addr_match_data {
656 struct rtw_dev *rtwdev;
657 struct ieee80211_hdr *hdr;
658 struct rtw_rx_pkt_stat *pkt_stat;
659 u8 *bssid;
660 };
661
rtw_phy_parsing_cfo_iter(void * data,u8 * mac,struct ieee80211_vif * vif)662 static void rtw_phy_parsing_cfo_iter(void *data, u8 *mac,
663 struct ieee80211_vif *vif)
664 {
665 struct rtw_rx_addr_match_data *iter_data = data;
666 struct rtw_dev *rtwdev = iter_data->rtwdev;
667 struct rtw_rx_pkt_stat *pkt_stat = iter_data->pkt_stat;
668 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
669 struct rtw_cfo_track *cfo = &dm_info->cfo_track;
670 u8 *bssid = iter_data->bssid;
671 u8 i;
672
673 if (!ether_addr_equal(vif->bss_conf.bssid, bssid))
674 return;
675
676 for (i = 0; i < rtwdev->hal.rf_path_num; i++) {
677 cfo->cfo_tail[i] += pkt_stat->cfo_tail[i];
678 cfo->cfo_cnt[i]++;
679 }
680
681 cfo->packet_count++;
682 }
683
rtw_phy_parsing_cfo(struct rtw_dev * rtwdev,struct rtw_rx_pkt_stat * pkt_stat)684 void rtw_phy_parsing_cfo(struct rtw_dev *rtwdev,
685 struct rtw_rx_pkt_stat *pkt_stat)
686 {
687 struct ieee80211_hdr *hdr = pkt_stat->hdr;
688 struct rtw_rx_addr_match_data data = {};
689
690 if (pkt_stat->crc_err || pkt_stat->icv_err || !pkt_stat->phy_status ||
691 ieee80211_is_ctl(hdr->frame_control))
692 return;
693
694 data.rtwdev = rtwdev;
695 data.hdr = hdr;
696 data.pkt_stat = pkt_stat;
697 data.bssid = get_hdr_bssid(hdr);
698
699 rtw_iterate_vifs_atomic(rtwdev, rtw_phy_parsing_cfo_iter, &data);
700 }
701 EXPORT_SYMBOL(rtw_phy_parsing_cfo);
702
rtw_phy_cfo_track(struct rtw_dev * rtwdev)703 static void rtw_phy_cfo_track(struct rtw_dev *rtwdev)
704 {
705 const struct rtw_chip_info *chip = rtwdev->chip;
706
707 if (chip->ops->cfo_track)
708 chip->ops->cfo_track(rtwdev);
709 }
710
711 #define CCK_PD_FA_LV1_MIN 1000
712 #define CCK_PD_FA_LV0_MAX 500
713
rtw_phy_cck_pd_lv_unlink(struct rtw_dev * rtwdev)714 static u8 rtw_phy_cck_pd_lv_unlink(struct rtw_dev *rtwdev)
715 {
716 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
717 u32 cck_fa_avg = dm_info->cck_fa_avg;
718
719 if (cck_fa_avg > CCK_PD_FA_LV1_MIN)
720 return CCK_PD_LV1;
721
722 if (cck_fa_avg < CCK_PD_FA_LV0_MAX)
723 return CCK_PD_LV0;
724
725 return CCK_PD_LV_MAX;
726 }
727
728 #define CCK_PD_IGI_LV4_VAL 0x38
729 #define CCK_PD_IGI_LV3_VAL 0x2a
730 #define CCK_PD_IGI_LV2_VAL 0x24
731 #define CCK_PD_RSSI_LV4_VAL 32
732 #define CCK_PD_RSSI_LV3_VAL 32
733 #define CCK_PD_RSSI_LV2_VAL 24
734
rtw_phy_cck_pd_lv_link(struct rtw_dev * rtwdev)735 static u8 rtw_phy_cck_pd_lv_link(struct rtw_dev *rtwdev)
736 {
737 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
738 u8 igi = dm_info->igi_history[0];
739 u8 rssi = dm_info->min_rssi;
740 u32 cck_fa_avg = dm_info->cck_fa_avg;
741
742 if (igi > CCK_PD_IGI_LV4_VAL && rssi > CCK_PD_RSSI_LV4_VAL)
743 return CCK_PD_LV4;
744 if (igi > CCK_PD_IGI_LV3_VAL && rssi > CCK_PD_RSSI_LV3_VAL)
745 return CCK_PD_LV3;
746 if (igi > CCK_PD_IGI_LV2_VAL || rssi > CCK_PD_RSSI_LV2_VAL)
747 return CCK_PD_LV2;
748 if (cck_fa_avg > CCK_PD_FA_LV1_MIN)
749 return CCK_PD_LV1;
750 if (cck_fa_avg < CCK_PD_FA_LV0_MAX)
751 return CCK_PD_LV0;
752
753 return CCK_PD_LV_MAX;
754 }
755
rtw_phy_cck_pd_lv(struct rtw_dev * rtwdev)756 static u8 rtw_phy_cck_pd_lv(struct rtw_dev *rtwdev)
757 {
758 if (!rtw_is_assoc(rtwdev))
759 return rtw_phy_cck_pd_lv_unlink(rtwdev);
760 else
761 return rtw_phy_cck_pd_lv_link(rtwdev);
762 }
763
rtw_phy_cck_pd(struct rtw_dev * rtwdev)764 static void rtw_phy_cck_pd(struct rtw_dev *rtwdev)
765 {
766 const struct rtw_chip_info *chip = rtwdev->chip;
767 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
768 u32 cck_fa = dm_info->cck_fa_cnt;
769 u8 level;
770
771 if (rtwdev->hal.current_band_type != RTW_BAND_2G)
772 return;
773
774 if (dm_info->cck_fa_avg == CCK_FA_AVG_RESET)
775 dm_info->cck_fa_avg = cck_fa;
776 else
777 dm_info->cck_fa_avg = (dm_info->cck_fa_avg * 3 + cck_fa) >> 2;
778
779 rtw_dbg(rtwdev, RTW_DBG_PHY, "IGI=0x%x, rssi_min=%d, cck_fa=%d\n",
780 dm_info->igi_history[0], dm_info->min_rssi,
781 dm_info->fa_history[0]);
782 rtw_dbg(rtwdev, RTW_DBG_PHY, "cck_fa_avg=%d, cck_pd_default=%d\n",
783 dm_info->cck_fa_avg, dm_info->cck_pd_default);
784
785 level = rtw_phy_cck_pd_lv(rtwdev);
786
787 if (level >= CCK_PD_LV_MAX)
788 return;
789
790 if (chip->ops->cck_pd_set)
791 chip->ops->cck_pd_set(rtwdev, level);
792 }
793
rtw_phy_pwr_track(struct rtw_dev * rtwdev)794 static void rtw_phy_pwr_track(struct rtw_dev *rtwdev)
795 {
796 rtwdev->chip->ops->pwr_track(rtwdev);
797 }
798
rtw_phy_ra_track(struct rtw_dev * rtwdev)799 static void rtw_phy_ra_track(struct rtw_dev *rtwdev)
800 {
801 rtw_fw_update_wl_phy_info(rtwdev);
802 rtw_phy_ra_info_update(rtwdev);
803 rtw_phy_rrsr_update(rtwdev);
804 }
805
rtw_phy_dynamic_mechanism(struct rtw_dev * rtwdev)806 void rtw_phy_dynamic_mechanism(struct rtw_dev *rtwdev)
807 {
808 /* for further calculation */
809 rtw_phy_statistics(rtwdev);
810 rtw_phy_dig(rtwdev);
811 rtw_phy_cck_pd(rtwdev);
812 rtw_phy_ra_track(rtwdev);
813 rtw_phy_tx_path_diversity(rtwdev);
814 rtw_phy_cfo_track(rtwdev);
815 rtw_phy_dpk_track(rtwdev);
816 rtw_phy_pwr_track(rtwdev);
817
818 if (rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_ADAPTIVITY))
819 rtw_fw_adaptivity(rtwdev);
820 else
821 rtw_phy_adaptivity(rtwdev);
822 }
823
824 #define FRAC_BITS 3
825
rtw_phy_power_2_db(s8 power)826 static u8 rtw_phy_power_2_db(s8 power)
827 {
828 if (power <= -100 || power >= 20)
829 return 0;
830 else if (power >= 0)
831 return 100;
832 else
833 return 100 + power;
834 }
835
rtw_phy_db_2_linear(u8 power_db)836 static u64 rtw_phy_db_2_linear(u8 power_db)
837 {
838 u8 i, j;
839 u64 linear;
840
841 if (power_db > 96)
842 power_db = 96;
843 else if (power_db < 1)
844 return 1;
845
846 /* 1dB ~ 96dB */
847 i = (power_db - 1) >> 3;
848 j = (power_db - 1) - (i << 3);
849
850 linear = db_invert_table[i][j];
851 linear = i > 2 ? linear << FRAC_BITS : linear;
852
853 return linear;
854 }
855
rtw_phy_linear_2_db(u64 linear)856 static u8 rtw_phy_linear_2_db(u64 linear)
857 {
858 u8 i;
859 u8 j;
860 u32 dB;
861
862 for (i = 0; i < 12; i++) {
863 for (j = 0; j < 8; j++) {
864 if (i <= 2 && (linear << FRAC_BITS) <= db_invert_table[i][j])
865 goto cnt;
866 else if (i > 2 && linear <= db_invert_table[i][j])
867 goto cnt;
868 }
869 }
870
871 return 96; /* maximum 96 dB */
872
873 cnt:
874 if (j == 0 && i == 0)
875 goto end;
876
877 if (j == 0) {
878 if (i != 3) {
879 if (db_invert_table[i][0] - linear >
880 linear - db_invert_table[i - 1][7]) {
881 i = i - 1;
882 j = 7;
883 }
884 } else {
885 if (db_invert_table[3][0] - linear >
886 linear - db_invert_table[2][7]) {
887 i = 2;
888 j = 7;
889 }
890 }
891 } else {
892 if (db_invert_table[i][j] - linear >
893 linear - db_invert_table[i][j - 1]) {
894 j = j - 1;
895 }
896 }
897 end:
898 dB = (i << 3) + j + 1;
899
900 return dB;
901 }
902
rtw_phy_rf_power_2_rssi(s8 * rf_power,u8 path_num)903 u8 rtw_phy_rf_power_2_rssi(s8 *rf_power, u8 path_num)
904 {
905 s8 power;
906 u8 power_db;
907 u64 linear;
908 u64 sum = 0;
909 u8 path;
910
911 for (path = 0; path < path_num; path++) {
912 power = rf_power[path];
913 power_db = rtw_phy_power_2_db(power);
914 linear = rtw_phy_db_2_linear(power_db);
915 sum += linear;
916 }
917
918 sum = (sum + (1 << (FRAC_BITS - 1))) >> FRAC_BITS;
919 switch (path_num) {
920 case 2:
921 sum >>= 1;
922 break;
923 case 3:
924 sum = ((sum) + ((sum) << 1) + ((sum) << 3)) >> 5;
925 break;
926 case 4:
927 sum >>= 2;
928 break;
929 default:
930 break;
931 }
932
933 return rtw_phy_linear_2_db(sum);
934 }
935 EXPORT_SYMBOL(rtw_phy_rf_power_2_rssi);
936
rtw_phy_read_rf(struct rtw_dev * rtwdev,enum rtw_rf_path rf_path,u32 addr,u32 mask)937 u32 rtw_phy_read_rf(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
938 u32 addr, u32 mask)
939 {
940 struct rtw_hal *hal = &rtwdev->hal;
941 const struct rtw_chip_info *chip = rtwdev->chip;
942 const u32 *base_addr = chip->rf_base_addr;
943 u32 val, direct_addr;
944
945 if (rf_path >= hal->rf_phy_num) {
946 rtw_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
947 return INV_RF_DATA;
948 }
949
950 addr &= 0xff;
951 direct_addr = base_addr[rf_path] + (addr << 2);
952 mask &= RFREG_MASK;
953
954 val = rtw_read32_mask(rtwdev, direct_addr, mask);
955
956 return val;
957 }
958 EXPORT_SYMBOL(rtw_phy_read_rf);
959
rtw_phy_read_rf_sipi(struct rtw_dev * rtwdev,enum rtw_rf_path rf_path,u32 addr,u32 mask)960 u32 rtw_phy_read_rf_sipi(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
961 u32 addr, u32 mask)
962 {
963 struct rtw_hal *hal = &rtwdev->hal;
964 const struct rtw_chip_info *chip = rtwdev->chip;
965 const struct rtw_rf_sipi_addr *rf_sipi_addr;
966 const struct rtw_rf_sipi_addr *rf_sipi_addr_a;
967 u32 val32;
968 u32 en_pi;
969 u32 r_addr;
970 u32 shift;
971
972 if (rf_path >= hal->rf_phy_num) {
973 rtw_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
974 return INV_RF_DATA;
975 }
976
977 if (!chip->rf_sipi_read_addr) {
978 rtw_err(rtwdev, "rf_sipi_read_addr isn't defined\n");
979 return INV_RF_DATA;
980 }
981
982 rf_sipi_addr = &chip->rf_sipi_read_addr[rf_path];
983 rf_sipi_addr_a = &chip->rf_sipi_read_addr[RF_PATH_A];
984
985 addr &= 0xff;
986
987 val32 = rtw_read32(rtwdev, rf_sipi_addr->hssi_2);
988 val32 = (val32 & ~LSSI_READ_ADDR_MASK) | (addr << 23);
989 rtw_write32(rtwdev, rf_sipi_addr->hssi_2, val32);
990
991 /* toggle read edge of path A */
992 val32 = rtw_read32(rtwdev, rf_sipi_addr_a->hssi_2);
993 rtw_write32(rtwdev, rf_sipi_addr_a->hssi_2, val32 & ~LSSI_READ_EDGE_MASK);
994 rtw_write32(rtwdev, rf_sipi_addr_a->hssi_2, val32 | LSSI_READ_EDGE_MASK);
995
996 udelay(120);
997
998 en_pi = rtw_read32_mask(rtwdev, rf_sipi_addr->hssi_1, BIT(8));
999 r_addr = en_pi ? rf_sipi_addr->lssi_read_pi : rf_sipi_addr->lssi_read;
1000
1001 val32 = rtw_read32_mask(rtwdev, r_addr, LSSI_READ_DATA_MASK);
1002
1003 shift = __ffs(mask);
1004
1005 return (val32 & mask) >> shift;
1006 }
1007 EXPORT_SYMBOL(rtw_phy_read_rf_sipi);
1008
rtw_phy_write_rf_reg_sipi(struct rtw_dev * rtwdev,enum rtw_rf_path rf_path,u32 addr,u32 mask,u32 data)1009 bool rtw_phy_write_rf_reg_sipi(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
1010 u32 addr, u32 mask, u32 data)
1011 {
1012 struct rtw_hal *hal = &rtwdev->hal;
1013 const struct rtw_chip_info *chip = rtwdev->chip;
1014 const u32 *sipi_addr = chip->rf_sipi_addr;
1015 u32 data_and_addr;
1016 u32 old_data = 0;
1017 u32 shift;
1018
1019 if (rf_path >= hal->rf_phy_num) {
1020 rtw_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
1021 return false;
1022 }
1023
1024 addr &= 0xff;
1025 mask &= RFREG_MASK;
1026
1027 if (mask != RFREG_MASK) {
1028 old_data = chip->ops->read_rf(rtwdev, rf_path, addr, RFREG_MASK);
1029
1030 if (old_data == INV_RF_DATA) {
1031 rtw_err(rtwdev, "Write fail, rf is disabled\n");
1032 return false;
1033 }
1034
1035 shift = __ffs(mask);
1036 data = ((old_data) & (~mask)) | (data << shift);
1037 }
1038
1039 data_and_addr = ((addr << 20) | (data & 0x000fffff)) & 0x0fffffff;
1040
1041 rtw_write32(rtwdev, sipi_addr[rf_path], data_and_addr);
1042
1043 udelay(13);
1044
1045 return true;
1046 }
1047 EXPORT_SYMBOL(rtw_phy_write_rf_reg_sipi);
1048
rtw_phy_write_rf_reg(struct rtw_dev * rtwdev,enum rtw_rf_path rf_path,u32 addr,u32 mask,u32 data)1049 bool rtw_phy_write_rf_reg(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
1050 u32 addr, u32 mask, u32 data)
1051 {
1052 struct rtw_hal *hal = &rtwdev->hal;
1053 const struct rtw_chip_info *chip = rtwdev->chip;
1054 const u32 *base_addr = chip->rf_base_addr;
1055 u32 direct_addr;
1056
1057 if (rf_path >= hal->rf_phy_num) {
1058 rtw_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
1059 return false;
1060 }
1061
1062 addr &= 0xff;
1063 direct_addr = base_addr[rf_path] + (addr << 2);
1064 mask &= RFREG_MASK;
1065
1066 rtw_write32_mask(rtwdev, direct_addr, mask, data);
1067
1068 udelay(1);
1069
1070 return true;
1071 }
1072
rtw_phy_write_rf_reg_mix(struct rtw_dev * rtwdev,enum rtw_rf_path rf_path,u32 addr,u32 mask,u32 data)1073 bool rtw_phy_write_rf_reg_mix(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
1074 u32 addr, u32 mask, u32 data)
1075 {
1076 if (addr != 0x00)
1077 return rtw_phy_write_rf_reg(rtwdev, rf_path, addr, mask, data);
1078
1079 return rtw_phy_write_rf_reg_sipi(rtwdev, rf_path, addr, mask, data);
1080 }
1081 EXPORT_SYMBOL(rtw_phy_write_rf_reg_mix);
1082
rtw_phy_setup_phy_cond(struct rtw_dev * rtwdev,u32 pkg)1083 void rtw_phy_setup_phy_cond(struct rtw_dev *rtwdev, u32 pkg)
1084 {
1085 struct rtw_hal *hal = &rtwdev->hal;
1086 struct rtw_efuse *efuse = &rtwdev->efuse;
1087 struct rtw_phy_cond cond = {};
1088 struct rtw_phy_cond2 cond2 = {};
1089
1090 cond.cut = hal->cut_version ? hal->cut_version : 15;
1091 cond.pkg = pkg ? pkg : 15;
1092 cond.plat = 0x04;
1093 cond.rfe = efuse->rfe_option;
1094
1095 switch (rtw_hci_type(rtwdev)) {
1096 case RTW_HCI_TYPE_USB:
1097 cond.intf = INTF_USB;
1098 break;
1099 case RTW_HCI_TYPE_SDIO:
1100 cond.intf = INTF_SDIO;
1101 break;
1102 case RTW_HCI_TYPE_PCIE:
1103 default:
1104 cond.intf = INTF_PCIE;
1105 break;
1106 }
1107
1108 if (rtwdev->chip->id == RTW_CHIP_TYPE_8812A ||
1109 rtwdev->chip->id == RTW_CHIP_TYPE_8821A) {
1110 cond.rfe = 0;
1111 cond.rfe |= efuse->ext_lna_2g;
1112 cond.rfe |= efuse->ext_pa_2g << 1;
1113 cond.rfe |= efuse->ext_lna_5g << 2;
1114 cond.rfe |= efuse->ext_pa_5g << 3;
1115 cond.rfe |= efuse->btcoex << 4;
1116
1117 cond2.type_alna = efuse->alna_type;
1118 cond2.type_glna = efuse->glna_type;
1119 cond2.type_apa = efuse->apa_type;
1120 cond2.type_gpa = efuse->gpa_type;
1121 }
1122
1123 hal->phy_cond = cond;
1124 hal->phy_cond2 = cond2;
1125
1126 rtw_dbg(rtwdev, RTW_DBG_PHY, "phy cond=0x%08x cond2=0x%08x\n",
1127 *((u32 *)&hal->phy_cond), *((u32 *)&hal->phy_cond2));
1128 }
1129
check_positive(struct rtw_dev * rtwdev,struct rtw_phy_cond cond,struct rtw_phy_cond2 cond2)1130 static bool check_positive(struct rtw_dev *rtwdev, struct rtw_phy_cond cond,
1131 struct rtw_phy_cond2 cond2)
1132 {
1133 struct rtw_hal *hal = &rtwdev->hal;
1134 struct rtw_phy_cond drv_cond = hal->phy_cond;
1135 struct rtw_phy_cond2 drv_cond2 = hal->phy_cond2;
1136
1137 if (cond.cut && cond.cut != drv_cond.cut)
1138 return false;
1139
1140 if (cond.pkg && cond.pkg != drv_cond.pkg)
1141 return false;
1142
1143 if (cond.intf && cond.intf != drv_cond.intf)
1144 return false;
1145
1146 if (rtwdev->chip->id == RTW_CHIP_TYPE_8812A ||
1147 rtwdev->chip->id == RTW_CHIP_TYPE_8821A) {
1148 if (!(cond.rfe & 0x0f))
1149 return true;
1150
1151 if ((cond.rfe & drv_cond.rfe) != cond.rfe)
1152 return false;
1153
1154 if ((cond.rfe & BIT(0)) && cond2.type_glna != drv_cond2.type_glna)
1155 return false;
1156
1157 if ((cond.rfe & BIT(1)) && cond2.type_gpa != drv_cond2.type_gpa)
1158 return false;
1159
1160 if ((cond.rfe & BIT(2)) && cond2.type_alna != drv_cond2.type_alna)
1161 return false;
1162
1163 if ((cond.rfe & BIT(3)) && cond2.type_apa != drv_cond2.type_apa)
1164 return false;
1165 } else {
1166 if (cond.rfe != drv_cond.rfe)
1167 return false;
1168 }
1169
1170 return true;
1171 }
1172
rtw_parse_tbl_phy_cond(struct rtw_dev * rtwdev,const struct rtw_table * tbl)1173 void rtw_parse_tbl_phy_cond(struct rtw_dev *rtwdev, const struct rtw_table *tbl)
1174 {
1175 const union phy_table_tile *p = tbl->data;
1176 const union phy_table_tile *end = p + tbl->size / 2;
1177 struct rtw_phy_cond pos_cond = {};
1178 struct rtw_phy_cond2 pos_cond2 = {};
1179 bool is_matched = true, is_skipped = false;
1180
1181 BUILD_BUG_ON(sizeof(union phy_table_tile) != sizeof(struct phy_cfg_pair));
1182
1183 for (; p < end; p++) {
1184 if (p->cond.pos) {
1185 switch (p->cond.branch) {
1186 case BRANCH_ENDIF:
1187 is_matched = true;
1188 is_skipped = false;
1189 break;
1190 case BRANCH_ELSE:
1191 is_matched = is_skipped ? false : true;
1192 break;
1193 case BRANCH_IF:
1194 case BRANCH_ELIF:
1195 default:
1196 pos_cond = p->cond;
1197 pos_cond2 = p->cond2;
1198 break;
1199 }
1200 } else if (p->cond.neg) {
1201 if (!is_skipped) {
1202 if (check_positive(rtwdev, pos_cond, pos_cond2)) {
1203 is_matched = true;
1204 is_skipped = true;
1205 } else {
1206 is_matched = false;
1207 is_skipped = false;
1208 }
1209 } else {
1210 is_matched = false;
1211 }
1212 } else if (is_matched) {
1213 (*tbl->do_cfg)(rtwdev, tbl, p->cfg.addr, p->cfg.data);
1214 }
1215 }
1216 }
1217 EXPORT_SYMBOL(rtw_parse_tbl_phy_cond);
1218
1219 #define bcd_to_dec_pwr_by_rate(val, i) bcd2bin(val >> (i * 8))
1220
tbl_to_dec_pwr_by_rate(struct rtw_dev * rtwdev,u32 hex,u8 i)1221 static u8 tbl_to_dec_pwr_by_rate(struct rtw_dev *rtwdev, u32 hex, u8 i)
1222 {
1223 if (rtwdev->chip->is_pwr_by_rate_dec)
1224 return bcd_to_dec_pwr_by_rate(hex, i);
1225
1226 return (hex >> (i * 8)) & 0xFF;
1227 }
1228
1229 static void
rtw_phy_get_rate_values_of_txpwr_by_rate(struct rtw_dev * rtwdev,u32 addr,u32 mask,u32 val,u8 * rate,u8 * pwr_by_rate,u8 * rate_num)1230 rtw_phy_get_rate_values_of_txpwr_by_rate(struct rtw_dev *rtwdev,
1231 u32 addr, u32 mask, u32 val, u8 *rate,
1232 u8 *pwr_by_rate, u8 *rate_num)
1233 {
1234 int i;
1235
1236 switch (addr) {
1237 case 0xE00:
1238 case 0x830:
1239 rate[0] = DESC_RATE6M;
1240 rate[1] = DESC_RATE9M;
1241 rate[2] = DESC_RATE12M;
1242 rate[3] = DESC_RATE18M;
1243 for (i = 0; i < 4; ++i)
1244 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1245 *rate_num = 4;
1246 break;
1247 case 0xE04:
1248 case 0x834:
1249 rate[0] = DESC_RATE24M;
1250 rate[1] = DESC_RATE36M;
1251 rate[2] = DESC_RATE48M;
1252 rate[3] = DESC_RATE54M;
1253 for (i = 0; i < 4; ++i)
1254 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1255 *rate_num = 4;
1256 break;
1257 case 0xE08:
1258 rate[0] = DESC_RATE1M;
1259 pwr_by_rate[0] = bcd_to_dec_pwr_by_rate(val, 1);
1260 *rate_num = 1;
1261 break;
1262 case 0x86C:
1263 if (mask == 0xffffff00) {
1264 rate[0] = DESC_RATE2M;
1265 rate[1] = DESC_RATE5_5M;
1266 rate[2] = DESC_RATE11M;
1267 for (i = 1; i < 4; ++i)
1268 pwr_by_rate[i - 1] =
1269 tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1270 *rate_num = 3;
1271 } else if (mask == 0x000000ff) {
1272 rate[0] = DESC_RATE11M;
1273 pwr_by_rate[0] = bcd_to_dec_pwr_by_rate(val, 0);
1274 *rate_num = 1;
1275 }
1276 break;
1277 case 0xE10:
1278 case 0x83C:
1279 rate[0] = DESC_RATEMCS0;
1280 rate[1] = DESC_RATEMCS1;
1281 rate[2] = DESC_RATEMCS2;
1282 rate[3] = DESC_RATEMCS3;
1283 for (i = 0; i < 4; ++i)
1284 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1285 *rate_num = 4;
1286 break;
1287 case 0xE14:
1288 case 0x848:
1289 rate[0] = DESC_RATEMCS4;
1290 rate[1] = DESC_RATEMCS5;
1291 rate[2] = DESC_RATEMCS6;
1292 rate[3] = DESC_RATEMCS7;
1293 for (i = 0; i < 4; ++i)
1294 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1295 *rate_num = 4;
1296 break;
1297 case 0xE18:
1298 case 0x84C:
1299 rate[0] = DESC_RATEMCS8;
1300 rate[1] = DESC_RATEMCS9;
1301 rate[2] = DESC_RATEMCS10;
1302 rate[3] = DESC_RATEMCS11;
1303 for (i = 0; i < 4; ++i)
1304 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1305 *rate_num = 4;
1306 break;
1307 case 0xE1C:
1308 case 0x868:
1309 rate[0] = DESC_RATEMCS12;
1310 rate[1] = DESC_RATEMCS13;
1311 rate[2] = DESC_RATEMCS14;
1312 rate[3] = DESC_RATEMCS15;
1313 for (i = 0; i < 4; ++i)
1314 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1315 *rate_num = 4;
1316 break;
1317 case 0x838:
1318 rate[0] = DESC_RATE1M;
1319 rate[1] = DESC_RATE2M;
1320 rate[2] = DESC_RATE5_5M;
1321 for (i = 1; i < 4; ++i)
1322 pwr_by_rate[i - 1] = tbl_to_dec_pwr_by_rate(rtwdev,
1323 val, i);
1324 *rate_num = 3;
1325 break;
1326 case 0xC20:
1327 case 0xE20:
1328 case 0x1820:
1329 case 0x1A20:
1330 rate[0] = DESC_RATE1M;
1331 rate[1] = DESC_RATE2M;
1332 rate[2] = DESC_RATE5_5M;
1333 rate[3] = DESC_RATE11M;
1334 for (i = 0; i < 4; ++i)
1335 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1336 *rate_num = 4;
1337 break;
1338 case 0xC24:
1339 case 0xE24:
1340 case 0x1824:
1341 case 0x1A24:
1342 rate[0] = DESC_RATE6M;
1343 rate[1] = DESC_RATE9M;
1344 rate[2] = DESC_RATE12M;
1345 rate[3] = DESC_RATE18M;
1346 for (i = 0; i < 4; ++i)
1347 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1348 *rate_num = 4;
1349 break;
1350 case 0xC28:
1351 case 0xE28:
1352 case 0x1828:
1353 case 0x1A28:
1354 rate[0] = DESC_RATE24M;
1355 rate[1] = DESC_RATE36M;
1356 rate[2] = DESC_RATE48M;
1357 rate[3] = DESC_RATE54M;
1358 for (i = 0; i < 4; ++i)
1359 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1360 *rate_num = 4;
1361 break;
1362 case 0xC2C:
1363 case 0xE2C:
1364 case 0x182C:
1365 case 0x1A2C:
1366 rate[0] = DESC_RATEMCS0;
1367 rate[1] = DESC_RATEMCS1;
1368 rate[2] = DESC_RATEMCS2;
1369 rate[3] = DESC_RATEMCS3;
1370 for (i = 0; i < 4; ++i)
1371 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1372 *rate_num = 4;
1373 break;
1374 case 0xC30:
1375 case 0xE30:
1376 case 0x1830:
1377 case 0x1A30:
1378 rate[0] = DESC_RATEMCS4;
1379 rate[1] = DESC_RATEMCS5;
1380 rate[2] = DESC_RATEMCS6;
1381 rate[3] = DESC_RATEMCS7;
1382 for (i = 0; i < 4; ++i)
1383 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1384 *rate_num = 4;
1385 break;
1386 case 0xC34:
1387 case 0xE34:
1388 case 0x1834:
1389 case 0x1A34:
1390 rate[0] = DESC_RATEMCS8;
1391 rate[1] = DESC_RATEMCS9;
1392 rate[2] = DESC_RATEMCS10;
1393 rate[3] = DESC_RATEMCS11;
1394 for (i = 0; i < 4; ++i)
1395 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1396 *rate_num = 4;
1397 break;
1398 case 0xC38:
1399 case 0xE38:
1400 case 0x1838:
1401 case 0x1A38:
1402 rate[0] = DESC_RATEMCS12;
1403 rate[1] = DESC_RATEMCS13;
1404 rate[2] = DESC_RATEMCS14;
1405 rate[3] = DESC_RATEMCS15;
1406 for (i = 0; i < 4; ++i)
1407 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1408 *rate_num = 4;
1409 break;
1410 case 0xC3C:
1411 case 0xE3C:
1412 case 0x183C:
1413 case 0x1A3C:
1414 rate[0] = DESC_RATEVHT1SS_MCS0;
1415 rate[1] = DESC_RATEVHT1SS_MCS1;
1416 rate[2] = DESC_RATEVHT1SS_MCS2;
1417 rate[3] = DESC_RATEVHT1SS_MCS3;
1418 for (i = 0; i < 4; ++i)
1419 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1420 *rate_num = 4;
1421 break;
1422 case 0xC40:
1423 case 0xE40:
1424 case 0x1840:
1425 case 0x1A40:
1426 rate[0] = DESC_RATEVHT1SS_MCS4;
1427 rate[1] = DESC_RATEVHT1SS_MCS5;
1428 rate[2] = DESC_RATEVHT1SS_MCS6;
1429 rate[3] = DESC_RATEVHT1SS_MCS7;
1430 for (i = 0; i < 4; ++i)
1431 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1432 *rate_num = 4;
1433 break;
1434 case 0xC44:
1435 case 0xE44:
1436 case 0x1844:
1437 case 0x1A44:
1438 rate[0] = DESC_RATEVHT1SS_MCS8;
1439 rate[1] = DESC_RATEVHT1SS_MCS9;
1440 rate[2] = DESC_RATEVHT2SS_MCS0;
1441 rate[3] = DESC_RATEVHT2SS_MCS1;
1442 for (i = 0; i < 4; ++i)
1443 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1444 *rate_num = 4;
1445 break;
1446 case 0xC48:
1447 case 0xE48:
1448 case 0x1848:
1449 case 0x1A48:
1450 rate[0] = DESC_RATEVHT2SS_MCS2;
1451 rate[1] = DESC_RATEVHT2SS_MCS3;
1452 rate[2] = DESC_RATEVHT2SS_MCS4;
1453 rate[3] = DESC_RATEVHT2SS_MCS5;
1454 for (i = 0; i < 4; ++i)
1455 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1456 *rate_num = 4;
1457 break;
1458 case 0xC4C:
1459 case 0xE4C:
1460 case 0x184C:
1461 case 0x1A4C:
1462 rate[0] = DESC_RATEVHT2SS_MCS6;
1463 rate[1] = DESC_RATEVHT2SS_MCS7;
1464 rate[2] = DESC_RATEVHT2SS_MCS8;
1465 rate[3] = DESC_RATEVHT2SS_MCS9;
1466 for (i = 0; i < 4; ++i)
1467 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1468 *rate_num = 4;
1469 break;
1470 case 0xCD8:
1471 case 0xED8:
1472 case 0x18D8:
1473 case 0x1AD8:
1474 rate[0] = DESC_RATEMCS16;
1475 rate[1] = DESC_RATEMCS17;
1476 rate[2] = DESC_RATEMCS18;
1477 rate[3] = DESC_RATEMCS19;
1478 for (i = 0; i < 4; ++i)
1479 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1480 *rate_num = 4;
1481 break;
1482 case 0xCDC:
1483 case 0xEDC:
1484 case 0x18DC:
1485 case 0x1ADC:
1486 rate[0] = DESC_RATEMCS20;
1487 rate[1] = DESC_RATEMCS21;
1488 rate[2] = DESC_RATEMCS22;
1489 rate[3] = DESC_RATEMCS23;
1490 for (i = 0; i < 4; ++i)
1491 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1492 *rate_num = 4;
1493 break;
1494 case 0xCE0:
1495 case 0xEE0:
1496 case 0x18E0:
1497 case 0x1AE0:
1498 rate[0] = DESC_RATEVHT3SS_MCS0;
1499 rate[1] = DESC_RATEVHT3SS_MCS1;
1500 rate[2] = DESC_RATEVHT3SS_MCS2;
1501 rate[3] = DESC_RATEVHT3SS_MCS3;
1502 for (i = 0; i < 4; ++i)
1503 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1504 *rate_num = 4;
1505 break;
1506 case 0xCE4:
1507 case 0xEE4:
1508 case 0x18E4:
1509 case 0x1AE4:
1510 rate[0] = DESC_RATEVHT3SS_MCS4;
1511 rate[1] = DESC_RATEVHT3SS_MCS5;
1512 rate[2] = DESC_RATEVHT3SS_MCS6;
1513 rate[3] = DESC_RATEVHT3SS_MCS7;
1514 for (i = 0; i < 4; ++i)
1515 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1516 *rate_num = 4;
1517 break;
1518 case 0xCE8:
1519 case 0xEE8:
1520 case 0x18E8:
1521 case 0x1AE8:
1522 rate[0] = DESC_RATEVHT3SS_MCS8;
1523 rate[1] = DESC_RATEVHT3SS_MCS9;
1524 for (i = 0; i < 2; ++i)
1525 pwr_by_rate[i] = tbl_to_dec_pwr_by_rate(rtwdev, val, i);
1526 *rate_num = 2;
1527 break;
1528 default:
1529 rtw_warn(rtwdev, "invalid tx power index addr 0x%08x\n", addr);
1530 break;
1531 }
1532 }
1533
rtw_phy_store_tx_power_by_rate(struct rtw_dev * rtwdev,u32 band,u32 rfpath,u32 txnum,u32 regaddr,u32 bitmask,u32 data)1534 static void rtw_phy_store_tx_power_by_rate(struct rtw_dev *rtwdev,
1535 u32 band, u32 rfpath, u32 txnum,
1536 u32 regaddr, u32 bitmask, u32 data)
1537 {
1538 struct rtw_hal *hal = &rtwdev->hal;
1539 u8 rate_num = 0;
1540 u8 rate;
1541 u8 rates[RTW_RF_PATH_MAX] = {0};
1542 s8 offset;
1543 s8 pwr_by_rate[RTW_RF_PATH_MAX] = {0};
1544 int i;
1545
1546 rtw_phy_get_rate_values_of_txpwr_by_rate(rtwdev, regaddr, bitmask, data,
1547 rates, pwr_by_rate, &rate_num);
1548
1549 if (WARN_ON(rfpath >= RTW_RF_PATH_MAX ||
1550 (band != PHY_BAND_2G && band != PHY_BAND_5G) ||
1551 rate_num > RTW_RF_PATH_MAX))
1552 return;
1553
1554 for (i = 0; i < rate_num; i++) {
1555 offset = pwr_by_rate[i];
1556 rate = rates[i];
1557 if (band == PHY_BAND_2G)
1558 hal->tx_pwr_by_rate_offset_2g[rfpath][rate] = offset;
1559 else
1560 hal->tx_pwr_by_rate_offset_5g[rfpath][rate] = offset;
1561 }
1562 }
1563
rtw_parse_tbl_bb_pg(struct rtw_dev * rtwdev,const struct rtw_table * tbl)1564 void rtw_parse_tbl_bb_pg(struct rtw_dev *rtwdev, const struct rtw_table *tbl)
1565 {
1566 const struct rtw_phy_pg_cfg_pair *p = tbl->data;
1567 const struct rtw_phy_pg_cfg_pair *end = p + tbl->size;
1568
1569 for (; p < end; p++) {
1570 if (p->addr == 0xfe || p->addr == 0xffe) {
1571 msleep(50);
1572 continue;
1573 }
1574 rtw_phy_store_tx_power_by_rate(rtwdev, p->band, p->rf_path,
1575 p->tx_num, p->addr, p->bitmask,
1576 p->data);
1577 }
1578 }
1579 EXPORT_SYMBOL(rtw_parse_tbl_bb_pg);
1580
1581 static const u8 rtw_channel_idx_5g[RTW_MAX_CHANNEL_NUM_5G] = {
1582 36, 38, 40, 42, 44, 46, 48, /* Band 1 */
1583 52, 54, 56, 58, 60, 62, 64, /* Band 2 */
1584 100, 102, 104, 106, 108, 110, 112, /* Band 3 */
1585 116, 118, 120, 122, 124, 126, 128, /* Band 3 */
1586 132, 134, 136, 138, 140, 142, 144, /* Band 3 */
1587 149, 151, 153, 155, 157, 159, 161, /* Band 4 */
1588 165, 167, 169, 171, 173, 175, 177}; /* Band 4 */
1589
rtw_channel_to_idx(u8 band,u8 channel)1590 static int rtw_channel_to_idx(u8 band, u8 channel)
1591 {
1592 int ch_idx;
1593 u8 n_channel;
1594
1595 if (band == PHY_BAND_2G) {
1596 ch_idx = channel - 1;
1597 n_channel = RTW_MAX_CHANNEL_NUM_2G;
1598 } else if (band == PHY_BAND_5G) {
1599 n_channel = RTW_MAX_CHANNEL_NUM_5G;
1600 for (ch_idx = 0; ch_idx < n_channel; ch_idx++)
1601 if (rtw_channel_idx_5g[ch_idx] == channel)
1602 break;
1603 } else {
1604 return -1;
1605 }
1606
1607 if (ch_idx >= n_channel)
1608 return -1;
1609
1610 return ch_idx;
1611 }
1612
rtw_phy_set_tx_power_limit(struct rtw_dev * rtwdev,u8 regd,u8 band,u8 bw,u8 rs,u8 ch,s8 pwr_limit)1613 static void rtw_phy_set_tx_power_limit(struct rtw_dev *rtwdev, u8 regd, u8 band,
1614 u8 bw, u8 rs, u8 ch, s8 pwr_limit)
1615 {
1616 struct rtw_hal *hal = &rtwdev->hal;
1617 u8 max_power_index = rtwdev->chip->max_power_index;
1618 s8 ww;
1619 int ch_idx;
1620
1621 pwr_limit = clamp_t(s8, pwr_limit,
1622 -max_power_index, max_power_index);
1623 ch_idx = rtw_channel_to_idx(band, ch);
1624
1625 if (regd >= RTW_REGD_MAX || bw >= RTW_CHANNEL_WIDTH_MAX ||
1626 rs >= RTW_RATE_SECTION_NUM || ch_idx < 0) {
1627 WARN(1,
1628 "wrong txpwr_lmt regd=%u, band=%u bw=%u, rs=%u, ch_idx=%u, pwr_limit=%d\n",
1629 regd, band, bw, rs, ch_idx, pwr_limit);
1630 return;
1631 }
1632
1633 if (band == PHY_BAND_2G) {
1634 hal->tx_pwr_limit_2g[regd][bw][rs][ch_idx] = pwr_limit;
1635 ww = hal->tx_pwr_limit_2g[RTW_REGD_WW][bw][rs][ch_idx];
1636 ww = min_t(s8, ww, pwr_limit);
1637 hal->tx_pwr_limit_2g[RTW_REGD_WW][bw][rs][ch_idx] = ww;
1638 } else if (band == PHY_BAND_5G) {
1639 hal->tx_pwr_limit_5g[regd][bw][rs][ch_idx] = pwr_limit;
1640 ww = hal->tx_pwr_limit_5g[RTW_REGD_WW][bw][rs][ch_idx];
1641 ww = min_t(s8, ww, pwr_limit);
1642 hal->tx_pwr_limit_5g[RTW_REGD_WW][bw][rs][ch_idx] = ww;
1643 }
1644 }
1645
1646 /* cross-reference 5G power limits if values are not assigned */
1647 static void
rtw_xref_5g_txpwr_lmt(struct rtw_dev * rtwdev,u8 regd,u8 bw,u8 ch_idx,u8 rs_ht,u8 rs_vht)1648 rtw_xref_5g_txpwr_lmt(struct rtw_dev *rtwdev, u8 regd,
1649 u8 bw, u8 ch_idx, u8 rs_ht, u8 rs_vht)
1650 {
1651 struct rtw_hal *hal = &rtwdev->hal;
1652 u8 max_power_index = rtwdev->chip->max_power_index;
1653 s8 lmt_ht = hal->tx_pwr_limit_5g[regd][bw][rs_ht][ch_idx];
1654 s8 lmt_vht = hal->tx_pwr_limit_5g[regd][bw][rs_vht][ch_idx];
1655
1656 if (lmt_ht == lmt_vht)
1657 return;
1658
1659 if (lmt_ht == max_power_index)
1660 hal->tx_pwr_limit_5g[regd][bw][rs_ht][ch_idx] = lmt_vht;
1661
1662 else if (lmt_vht == max_power_index)
1663 hal->tx_pwr_limit_5g[regd][bw][rs_vht][ch_idx] = lmt_ht;
1664 }
1665
1666 /* cross-reference power limits for ht and vht */
1667 static void
rtw_xref_txpwr_lmt_by_rs(struct rtw_dev * rtwdev,u8 regd,u8 bw,u8 ch_idx)1668 rtw_xref_txpwr_lmt_by_rs(struct rtw_dev *rtwdev, u8 regd, u8 bw, u8 ch_idx)
1669 {
1670 static const u8 rs_cmp[4][2] = {
1671 {RTW_RATE_SECTION_HT_1S, RTW_RATE_SECTION_VHT_1S},
1672 {RTW_RATE_SECTION_HT_2S, RTW_RATE_SECTION_VHT_2S},
1673 {RTW_RATE_SECTION_HT_3S, RTW_RATE_SECTION_VHT_3S},
1674 {RTW_RATE_SECTION_HT_4S, RTW_RATE_SECTION_VHT_4S}
1675 };
1676 u8 rs_idx, rs_ht, rs_vht;
1677
1678 for (rs_idx = 0; rs_idx < 4; rs_idx++) {
1679 rs_ht = rs_cmp[rs_idx][0];
1680 rs_vht = rs_cmp[rs_idx][1];
1681
1682 rtw_xref_5g_txpwr_lmt(rtwdev, regd, bw, ch_idx, rs_ht, rs_vht);
1683 }
1684 }
1685
1686 /* cross-reference power limits for 5G channels */
1687 static void
rtw_xref_5g_txpwr_lmt_by_ch(struct rtw_dev * rtwdev,u8 regd,u8 bw)1688 rtw_xref_5g_txpwr_lmt_by_ch(struct rtw_dev *rtwdev, u8 regd, u8 bw)
1689 {
1690 u8 ch_idx;
1691
1692 for (ch_idx = 0; ch_idx < RTW_MAX_CHANNEL_NUM_5G; ch_idx++)
1693 rtw_xref_txpwr_lmt_by_rs(rtwdev, regd, bw, ch_idx);
1694 }
1695
1696 /* cross-reference power limits for 20/40M bandwidth */
1697 static void
rtw_xref_txpwr_lmt_by_bw(struct rtw_dev * rtwdev,u8 regd)1698 rtw_xref_txpwr_lmt_by_bw(struct rtw_dev *rtwdev, u8 regd)
1699 {
1700 u8 bw;
1701
1702 for (bw = RTW_CHANNEL_WIDTH_20; bw <= RTW_CHANNEL_WIDTH_40; bw++)
1703 rtw_xref_5g_txpwr_lmt_by_ch(rtwdev, regd, bw);
1704 }
1705
1706 /* cross-reference power limits */
rtw_xref_txpwr_lmt(struct rtw_dev * rtwdev)1707 static void rtw_xref_txpwr_lmt(struct rtw_dev *rtwdev)
1708 {
1709 u8 regd;
1710
1711 for (regd = 0; regd < RTW_REGD_MAX; regd++)
1712 rtw_xref_txpwr_lmt_by_bw(rtwdev, regd);
1713 }
1714
1715 static void
__cfg_txpwr_lmt_by_alt(struct rtw_hal * hal,u8 regd,u8 regd_alt,u8 bw,u8 rs)1716 __cfg_txpwr_lmt_by_alt(struct rtw_hal *hal, u8 regd, u8 regd_alt, u8 bw, u8 rs)
1717 {
1718 u8 ch;
1719
1720 for (ch = 0; ch < RTW_MAX_CHANNEL_NUM_2G; ch++)
1721 hal->tx_pwr_limit_2g[regd][bw][rs][ch] =
1722 hal->tx_pwr_limit_2g[regd_alt][bw][rs][ch];
1723
1724 for (ch = 0; ch < RTW_MAX_CHANNEL_NUM_5G; ch++)
1725 hal->tx_pwr_limit_5g[regd][bw][rs][ch] =
1726 hal->tx_pwr_limit_5g[regd_alt][bw][rs][ch];
1727 }
1728
1729 static void
rtw_cfg_txpwr_lmt_by_alt(struct rtw_dev * rtwdev,u8 regd,u8 regd_alt)1730 rtw_cfg_txpwr_lmt_by_alt(struct rtw_dev *rtwdev, u8 regd, u8 regd_alt)
1731 {
1732 u8 bw, rs;
1733
1734 for (bw = 0; bw < RTW_CHANNEL_WIDTH_MAX; bw++)
1735 for (rs = 0; rs < RTW_RATE_SECTION_NUM; rs++)
1736 __cfg_txpwr_lmt_by_alt(&rtwdev->hal, regd, regd_alt,
1737 bw, rs);
1738 }
1739
rtw_parse_tbl_txpwr_lmt(struct rtw_dev * rtwdev,const struct rtw_table * tbl)1740 void rtw_parse_tbl_txpwr_lmt(struct rtw_dev *rtwdev,
1741 const struct rtw_table *tbl)
1742 {
1743 const struct rtw_txpwr_lmt_cfg_pair *p = tbl->data;
1744 const struct rtw_txpwr_lmt_cfg_pair *end = p + tbl->size;
1745 u32 regd_cfg_flag = 0;
1746 u8 regd_alt;
1747 u8 i;
1748
1749 for (; p < end; p++) {
1750 regd_cfg_flag |= BIT(p->regd);
1751 rtw_phy_set_tx_power_limit(rtwdev, p->regd, p->band,
1752 p->bw, p->rs, p->ch, p->txpwr_lmt);
1753 }
1754
1755 for (i = 0; i < RTW_REGD_MAX; i++) {
1756 if (i == RTW_REGD_WW)
1757 continue;
1758
1759 if (regd_cfg_flag & BIT(i))
1760 continue;
1761
1762 rtw_dbg(rtwdev, RTW_DBG_REGD,
1763 "txpwr regd %d does not be configured\n", i);
1764
1765 if (rtw_regd_has_alt(i, ®d_alt) &&
1766 regd_cfg_flag & BIT(regd_alt)) {
1767 rtw_dbg(rtwdev, RTW_DBG_REGD,
1768 "cfg txpwr regd %d by regd %d as alternative\n",
1769 i, regd_alt);
1770
1771 rtw_cfg_txpwr_lmt_by_alt(rtwdev, i, regd_alt);
1772 continue;
1773 }
1774
1775 rtw_dbg(rtwdev, RTW_DBG_REGD, "cfg txpwr regd %d by WW\n", i);
1776 rtw_cfg_txpwr_lmt_by_alt(rtwdev, i, RTW_REGD_WW);
1777 }
1778
1779 rtw_xref_txpwr_lmt(rtwdev);
1780 }
1781 EXPORT_SYMBOL(rtw_parse_tbl_txpwr_lmt);
1782
rtw_phy_cfg_mac(struct rtw_dev * rtwdev,const struct rtw_table * tbl,u32 addr,u32 data)1783 void rtw_phy_cfg_mac(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
1784 u32 addr, u32 data)
1785 {
1786 rtw_write8(rtwdev, addr, data);
1787 }
1788 EXPORT_SYMBOL(rtw_phy_cfg_mac);
1789
rtw_phy_cfg_agc(struct rtw_dev * rtwdev,const struct rtw_table * tbl,u32 addr,u32 data)1790 void rtw_phy_cfg_agc(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
1791 u32 addr, u32 data)
1792 {
1793 rtw_write32(rtwdev, addr, data);
1794 }
1795 EXPORT_SYMBOL(rtw_phy_cfg_agc);
1796
rtw_phy_cfg_bb(struct rtw_dev * rtwdev,const struct rtw_table * tbl,u32 addr,u32 data)1797 void rtw_phy_cfg_bb(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
1798 u32 addr, u32 data)
1799 {
1800 if (addr == 0xfe)
1801 msleep(50);
1802 else if (addr == 0xfd)
1803 mdelay(5);
1804 else if (addr == 0xfc)
1805 mdelay(1);
1806 else if (addr == 0xfb)
1807 usleep_range(50, 60);
1808 else if (addr == 0xfa)
1809 udelay(5);
1810 else if (addr == 0xf9)
1811 udelay(1);
1812 else
1813 rtw_write32(rtwdev, addr, data);
1814 }
1815 EXPORT_SYMBOL(rtw_phy_cfg_bb);
1816
rtw_phy_cfg_rf(struct rtw_dev * rtwdev,const struct rtw_table * tbl,u32 addr,u32 data)1817 void rtw_phy_cfg_rf(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
1818 u32 addr, u32 data)
1819 {
1820 if (addr == 0xffe) {
1821 msleep(50);
1822 } else if (addr == 0xfe) {
1823 usleep_range(100, 110);
1824 } else {
1825 rtw_write_rf(rtwdev, tbl->rf_path, addr, RFREG_MASK, data);
1826 udelay(1);
1827 }
1828 }
1829 EXPORT_SYMBOL(rtw_phy_cfg_rf);
1830
rtw_load_rfk_table(struct rtw_dev * rtwdev)1831 static void rtw_load_rfk_table(struct rtw_dev *rtwdev)
1832 {
1833 const struct rtw_chip_info *chip = rtwdev->chip;
1834 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
1835
1836 if (!chip->rfk_init_tbl)
1837 return;
1838
1839 rtw_write32_mask(rtwdev, 0x1e24, BIT(17), 0x1);
1840 rtw_write32_mask(rtwdev, 0x1cd0, BIT(28), 0x1);
1841 rtw_write32_mask(rtwdev, 0x1cd0, BIT(29), 0x1);
1842 rtw_write32_mask(rtwdev, 0x1cd0, BIT(30), 0x1);
1843 rtw_write32_mask(rtwdev, 0x1cd0, BIT(31), 0x0);
1844
1845 rtw_load_table(rtwdev, chip->rfk_init_tbl);
1846
1847 dpk_info->is_dpk_pwr_on = true;
1848 }
1849
rtw_phy_load_tables(struct rtw_dev * rtwdev)1850 void rtw_phy_load_tables(struct rtw_dev *rtwdev)
1851 {
1852 const struct rtw_rfe_def *rfe_def = rtw_get_rfe_def(rtwdev);
1853 const struct rtw_chip_info *chip = rtwdev->chip;
1854 u8 rf_path;
1855
1856 rtw_load_table(rtwdev, chip->mac_tbl);
1857 rtw_load_table(rtwdev, chip->bb_tbl);
1858 rtw_load_table(rtwdev, chip->agc_tbl);
1859 if (rfe_def->agc_btg_tbl)
1860 rtw_load_table(rtwdev, rfe_def->agc_btg_tbl);
1861 rtw_load_rfk_table(rtwdev);
1862
1863 for (rf_path = 0; rf_path < rtwdev->hal.rf_path_num; rf_path++) {
1864 const struct rtw_table *tbl;
1865
1866 tbl = chip->rf_tbl[rf_path];
1867 rtw_load_table(rtwdev, tbl);
1868 }
1869 }
1870 EXPORT_SYMBOL(rtw_phy_load_tables);
1871
rtw_get_channel_group(u8 channel,u8 rate)1872 static u8 rtw_get_channel_group(u8 channel, u8 rate)
1873 {
1874 switch (channel) {
1875 default:
1876 WARN_ON(1);
1877 fallthrough;
1878 case 1:
1879 case 2:
1880 case 36:
1881 case 38:
1882 case 40:
1883 case 42:
1884 return 0;
1885 case 3:
1886 case 4:
1887 case 5:
1888 case 44:
1889 case 46:
1890 case 48:
1891 case 50:
1892 return 1;
1893 case 6:
1894 case 7:
1895 case 8:
1896 case 52:
1897 case 54:
1898 case 56:
1899 case 58:
1900 return 2;
1901 case 9:
1902 case 10:
1903 case 11:
1904 case 60:
1905 case 62:
1906 case 64:
1907 return 3;
1908 case 12:
1909 case 13:
1910 case 100:
1911 case 102:
1912 case 104:
1913 case 106:
1914 return 4;
1915 case 14:
1916 return rate <= DESC_RATE11M ? 5 : 4;
1917 case 108:
1918 case 110:
1919 case 112:
1920 case 114:
1921 return 5;
1922 case 116:
1923 case 118:
1924 case 120:
1925 case 122:
1926 return 6;
1927 case 124:
1928 case 126:
1929 case 128:
1930 case 130:
1931 return 7;
1932 case 132:
1933 case 134:
1934 case 136:
1935 case 138:
1936 return 8;
1937 case 140:
1938 case 142:
1939 case 144:
1940 return 9;
1941 case 149:
1942 case 151:
1943 case 153:
1944 case 155:
1945 return 10;
1946 case 157:
1947 case 159:
1948 case 161:
1949 return 11;
1950 case 165:
1951 case 167:
1952 case 169:
1953 case 171:
1954 return 12;
1955 case 173:
1956 case 175:
1957 case 177:
1958 return 13;
1959 }
1960 }
1961
rtw_phy_get_dis_dpd_by_rate_diff(struct rtw_dev * rtwdev,u16 rate)1962 static s8 rtw_phy_get_dis_dpd_by_rate_diff(struct rtw_dev *rtwdev, u16 rate)
1963 {
1964 const struct rtw_chip_info *chip = rtwdev->chip;
1965 s8 dpd_diff = 0;
1966
1967 if (!chip->en_dis_dpd)
1968 return 0;
1969
1970 #define RTW_DPD_RATE_CHECK(_rate) \
1971 case DESC_RATE ## _rate: \
1972 if (DIS_DPD_RATE ## _rate & chip->dpd_ratemask) \
1973 dpd_diff = -6 * chip->txgi_factor; \
1974 break
1975
1976 switch (rate) {
1977 RTW_DPD_RATE_CHECK(6M);
1978 RTW_DPD_RATE_CHECK(9M);
1979 RTW_DPD_RATE_CHECK(MCS0);
1980 RTW_DPD_RATE_CHECK(MCS1);
1981 RTW_DPD_RATE_CHECK(MCS8);
1982 RTW_DPD_RATE_CHECK(MCS9);
1983 RTW_DPD_RATE_CHECK(VHT1SS_MCS0);
1984 RTW_DPD_RATE_CHECK(VHT1SS_MCS1);
1985 RTW_DPD_RATE_CHECK(VHT2SS_MCS0);
1986 RTW_DPD_RATE_CHECK(VHT2SS_MCS1);
1987 }
1988 #undef RTW_DPD_RATE_CHECK
1989
1990 return dpd_diff;
1991 }
1992
rtw_phy_get_2g_tx_power_index(struct rtw_dev * rtwdev,struct rtw_2g_txpwr_idx * pwr_idx_2g,enum rtw_bandwidth bandwidth,u8 rate,u8 group)1993 static u8 rtw_phy_get_2g_tx_power_index(struct rtw_dev *rtwdev,
1994 struct rtw_2g_txpwr_idx *pwr_idx_2g,
1995 enum rtw_bandwidth bandwidth,
1996 u8 rate, u8 group)
1997 {
1998 const struct rtw_chip_info *chip = rtwdev->chip;
1999 bool above_2ss, above_3ss, above_4ss;
2000 u8 factor = chip->txgi_factor;
2001 bool mcs_rate;
2002 u8 tx_power;
2003
2004 if (rate <= DESC_RATE11M)
2005 tx_power = pwr_idx_2g->cck_base[group];
2006 else
2007 tx_power = pwr_idx_2g->bw40_base[group];
2008
2009 if (rate >= DESC_RATE6M && rate <= DESC_RATE54M)
2010 tx_power += pwr_idx_2g->ht_1s_diff.ofdm * factor;
2011
2012 mcs_rate = (rate >= DESC_RATEMCS0 && rate <= DESC_RATEMCS31) ||
2013 (rate >= DESC_RATEVHT1SS_MCS0 &&
2014 rate <= DESC_RATEVHT4SS_MCS9);
2015 above_2ss = (rate >= DESC_RATEMCS8 && rate <= DESC_RATEMCS31) ||
2016 (rate >= DESC_RATEVHT2SS_MCS0);
2017 above_3ss = (rate >= DESC_RATEMCS16 && rate <= DESC_RATEMCS31) ||
2018 (rate >= DESC_RATEVHT3SS_MCS0);
2019 above_4ss = (rate >= DESC_RATEMCS24 && rate <= DESC_RATEMCS31) ||
2020 (rate >= DESC_RATEVHT4SS_MCS0);
2021
2022 if (!mcs_rate)
2023 return tx_power;
2024
2025 switch (bandwidth) {
2026 default:
2027 WARN_ON(1);
2028 fallthrough;
2029 case RTW_CHANNEL_WIDTH_20:
2030 tx_power += pwr_idx_2g->ht_1s_diff.bw20 * factor;
2031 if (above_2ss)
2032 tx_power += pwr_idx_2g->ht_2s_diff.bw20 * factor;
2033 if (above_3ss)
2034 tx_power += pwr_idx_2g->ht_3s_diff.bw20 * factor;
2035 if (above_4ss)
2036 tx_power += pwr_idx_2g->ht_4s_diff.bw20 * factor;
2037 break;
2038 case RTW_CHANNEL_WIDTH_40:
2039 /* bw40 is the base power */
2040 if (above_2ss)
2041 tx_power += pwr_idx_2g->ht_2s_diff.bw40 * factor;
2042 if (above_3ss)
2043 tx_power += pwr_idx_2g->ht_3s_diff.bw40 * factor;
2044 if (above_4ss)
2045 tx_power += pwr_idx_2g->ht_4s_diff.bw40 * factor;
2046 break;
2047 }
2048
2049 return tx_power;
2050 }
2051
rtw_phy_get_5g_tx_power_index(struct rtw_dev * rtwdev,struct rtw_5g_txpwr_idx * pwr_idx_5g,enum rtw_bandwidth bandwidth,u8 rate,u8 group)2052 static u8 rtw_phy_get_5g_tx_power_index(struct rtw_dev *rtwdev,
2053 struct rtw_5g_txpwr_idx *pwr_idx_5g,
2054 enum rtw_bandwidth bandwidth,
2055 u8 rate, u8 group)
2056 {
2057 const struct rtw_chip_info *chip = rtwdev->chip;
2058 bool above_2ss, above_3ss, above_4ss;
2059 u8 factor = chip->txgi_factor;
2060 u8 upper, lower;
2061 bool mcs_rate;
2062 u8 tx_power;
2063
2064 tx_power = pwr_idx_5g->bw40_base[group];
2065
2066 mcs_rate = (rate >= DESC_RATEMCS0 && rate <= DESC_RATEMCS31) ||
2067 (rate >= DESC_RATEVHT1SS_MCS0 &&
2068 rate <= DESC_RATEVHT4SS_MCS9);
2069 above_2ss = (rate >= DESC_RATEMCS8 && rate <= DESC_RATEMCS31) ||
2070 (rate >= DESC_RATEVHT2SS_MCS0);
2071 above_3ss = (rate >= DESC_RATEMCS16 && rate <= DESC_RATEMCS31) ||
2072 (rate >= DESC_RATEVHT3SS_MCS0);
2073 above_4ss = (rate >= DESC_RATEMCS24 && rate <= DESC_RATEMCS31) ||
2074 (rate >= DESC_RATEVHT4SS_MCS0);
2075
2076 if (!mcs_rate) {
2077 tx_power += pwr_idx_5g->ht_1s_diff.ofdm * factor;
2078 return tx_power;
2079 }
2080
2081 switch (bandwidth) {
2082 default:
2083 WARN_ON(1);
2084 fallthrough;
2085 case RTW_CHANNEL_WIDTH_20:
2086 tx_power += pwr_idx_5g->ht_1s_diff.bw20 * factor;
2087 if (above_2ss)
2088 tx_power += pwr_idx_5g->ht_2s_diff.bw20 * factor;
2089 if (above_3ss)
2090 tx_power += pwr_idx_5g->ht_3s_diff.bw20 * factor;
2091 if (above_4ss)
2092 tx_power += pwr_idx_5g->ht_4s_diff.bw20 * factor;
2093 break;
2094 case RTW_CHANNEL_WIDTH_40:
2095 /* bw40 is the base power */
2096 if (above_2ss)
2097 tx_power += pwr_idx_5g->ht_2s_diff.bw40 * factor;
2098 if (above_3ss)
2099 tx_power += pwr_idx_5g->ht_3s_diff.bw40 * factor;
2100 if (above_4ss)
2101 tx_power += pwr_idx_5g->ht_4s_diff.bw40 * factor;
2102 break;
2103 case RTW_CHANNEL_WIDTH_80:
2104 /* the base idx of bw80 is the average of bw40+/bw40- */
2105 lower = pwr_idx_5g->bw40_base[group];
2106 upper = pwr_idx_5g->bw40_base[group + 1];
2107
2108 tx_power = (lower + upper) / 2;
2109 tx_power += pwr_idx_5g->vht_1s_diff.bw80 * factor;
2110 if (above_2ss)
2111 tx_power += pwr_idx_5g->vht_2s_diff.bw80 * factor;
2112 if (above_3ss)
2113 tx_power += pwr_idx_5g->vht_3s_diff.bw80 * factor;
2114 if (above_4ss)
2115 tx_power += pwr_idx_5g->vht_4s_diff.bw80 * factor;
2116 break;
2117 }
2118
2119 return tx_power;
2120 }
2121
2122 /* return RTW_RATE_SECTION_NUM to indicate rate is invalid */
rtw_phy_rate_to_rate_section(u8 rate)2123 static u8 rtw_phy_rate_to_rate_section(u8 rate)
2124 {
2125 if (rate >= DESC_RATE1M && rate <= DESC_RATE11M)
2126 return RTW_RATE_SECTION_CCK;
2127 else if (rate >= DESC_RATE6M && rate <= DESC_RATE54M)
2128 return RTW_RATE_SECTION_OFDM;
2129 else if (rate >= DESC_RATEMCS0 && rate <= DESC_RATEMCS7)
2130 return RTW_RATE_SECTION_HT_1S;
2131 else if (rate >= DESC_RATEMCS8 && rate <= DESC_RATEMCS15)
2132 return RTW_RATE_SECTION_HT_2S;
2133 else if (rate >= DESC_RATEMCS16 && rate <= DESC_RATEMCS23)
2134 return RTW_RATE_SECTION_HT_3S;
2135 else if (rate >= DESC_RATEMCS24 && rate <= DESC_RATEMCS31)
2136 return RTW_RATE_SECTION_HT_4S;
2137 else if (rate >= DESC_RATEVHT1SS_MCS0 && rate <= DESC_RATEVHT1SS_MCS9)
2138 return RTW_RATE_SECTION_VHT_1S;
2139 else if (rate >= DESC_RATEVHT2SS_MCS0 && rate <= DESC_RATEVHT2SS_MCS9)
2140 return RTW_RATE_SECTION_VHT_2S;
2141 else if (rate >= DESC_RATEVHT3SS_MCS0 && rate <= DESC_RATEVHT3SS_MCS9)
2142 return RTW_RATE_SECTION_VHT_3S;
2143 else if (rate >= DESC_RATEVHT4SS_MCS0 && rate <= DESC_RATEVHT4SS_MCS9)
2144 return RTW_RATE_SECTION_VHT_4S;
2145 else
2146 return RTW_RATE_SECTION_NUM;
2147 }
2148
rtw_phy_get_tx_power_limit(struct rtw_dev * rtwdev,u8 band,enum rtw_bandwidth bw,u8 rf_path,u8 rate,u8 channel,u8 regd)2149 static s8 rtw_phy_get_tx_power_limit(struct rtw_dev *rtwdev, u8 band,
2150 enum rtw_bandwidth bw, u8 rf_path,
2151 u8 rate, u8 channel, u8 regd)
2152 {
2153 struct rtw_hal *hal = &rtwdev->hal;
2154 u8 *cch_by_bw = hal->cch_by_bw;
2155 s8 power_limit = (s8)rtwdev->chip->max_power_index;
2156 u8 rs = rtw_phy_rate_to_rate_section(rate);
2157 int ch_idx;
2158 u8 cur_bw, cur_ch;
2159 s8 cur_lmt;
2160
2161 if (regd > RTW_REGD_WW)
2162 return power_limit;
2163
2164 if (rs == RTW_RATE_SECTION_NUM)
2165 goto err;
2166
2167 /* only 20M BW with cck and ofdm */
2168 if (rs == RTW_RATE_SECTION_CCK || rs == RTW_RATE_SECTION_OFDM)
2169 bw = RTW_CHANNEL_WIDTH_20;
2170
2171 /* only 20/40M BW with ht */
2172 if (rate >= DESC_RATEMCS0 && rate <= DESC_RATEMCS31)
2173 bw = min_t(u8, bw, RTW_CHANNEL_WIDTH_40);
2174
2175 /* select min power limit among [20M BW ~ current BW] */
2176 for (cur_bw = RTW_CHANNEL_WIDTH_20; cur_bw <= bw; cur_bw++) {
2177 cur_ch = cch_by_bw[cur_bw];
2178
2179 ch_idx = rtw_channel_to_idx(band, cur_ch);
2180 if (ch_idx < 0)
2181 goto err;
2182
2183 cur_lmt = cur_ch <= RTW_MAX_CHANNEL_NUM_2G ?
2184 hal->tx_pwr_limit_2g[regd][cur_bw][rs][ch_idx] :
2185 hal->tx_pwr_limit_5g[regd][cur_bw][rs][ch_idx];
2186
2187 power_limit = min_t(s8, cur_lmt, power_limit);
2188 }
2189
2190 return power_limit;
2191
2192 err:
2193 WARN(1, "invalid arguments, band=%d, bw=%d, path=%d, rate=%d, ch=%d\n",
2194 band, bw, rf_path, rate, channel);
2195 return (s8)rtwdev->chip->max_power_index;
2196 }
2197
rtw_phy_get_tx_power_sar(struct rtw_dev * rtwdev,u8 sar_band,u8 rf_path,u8 rate)2198 static s8 rtw_phy_get_tx_power_sar(struct rtw_dev *rtwdev, u8 sar_band,
2199 u8 rf_path, u8 rate)
2200 {
2201 u8 rs = rtw_phy_rate_to_rate_section(rate);
2202 struct rtw_sar_arg arg = {
2203 .sar_band = sar_band,
2204 .path = rf_path,
2205 .rs = rs,
2206 };
2207
2208 if (rs == RTW_RATE_SECTION_NUM)
2209 goto err;
2210
2211 return rtw_query_sar(rtwdev, &arg);
2212
2213 err:
2214 WARN(1, "invalid arguments, sar_band=%d, path=%d, rate=%d\n",
2215 sar_band, rf_path, rate);
2216 return (s8)rtwdev->chip->max_power_index;
2217 }
2218
rtw_get_tx_power_params(struct rtw_dev * rtwdev,u8 path,u8 rate,u8 bw,u8 ch,u8 regd,struct rtw_power_params * pwr_param)2219 void rtw_get_tx_power_params(struct rtw_dev *rtwdev, u8 path, u8 rate, u8 bw,
2220 u8 ch, u8 regd, struct rtw_power_params *pwr_param)
2221 {
2222 struct rtw_hal *hal = &rtwdev->hal;
2223 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
2224 struct rtw_txpwr_idx *pwr_idx;
2225 u8 group, band;
2226 u8 *base = &pwr_param->pwr_base;
2227 s8 *offset = &pwr_param->pwr_offset;
2228 s8 *limit = &pwr_param->pwr_limit;
2229 s8 *remnant = &pwr_param->pwr_remnant;
2230 s8 *sar = &pwr_param->pwr_sar;
2231
2232 pwr_idx = &rtwdev->efuse.txpwr_idx_table[path];
2233 group = rtw_get_channel_group(ch, rate);
2234
2235 /* base power index for 2.4G/5G */
2236 if (IS_CH_2G_BAND(ch)) {
2237 band = PHY_BAND_2G;
2238 *base = rtw_phy_get_2g_tx_power_index(rtwdev,
2239 &pwr_idx->pwr_idx_2g,
2240 bw, rate, group);
2241 *offset = hal->tx_pwr_by_rate_offset_2g[path][rate];
2242 } else {
2243 band = PHY_BAND_5G;
2244 *base = rtw_phy_get_5g_tx_power_index(rtwdev,
2245 &pwr_idx->pwr_idx_5g,
2246 bw, rate, group);
2247 *offset = hal->tx_pwr_by_rate_offset_5g[path][rate];
2248 }
2249
2250 *limit = rtw_phy_get_tx_power_limit(rtwdev, band, bw, path,
2251 rate, ch, regd);
2252 *remnant = rate <= DESC_RATE11M ? dm_info->txagc_remnant_cck :
2253 dm_info->txagc_remnant_ofdm[path];
2254 *sar = rtw_phy_get_tx_power_sar(rtwdev, hal->sar_band, path, rate);
2255 }
2256
2257 u8
rtw_phy_get_tx_power_index(struct rtw_dev * rtwdev,u8 rf_path,u8 rate,enum rtw_bandwidth bandwidth,u8 channel,u8 regd)2258 rtw_phy_get_tx_power_index(struct rtw_dev *rtwdev, u8 rf_path, u8 rate,
2259 enum rtw_bandwidth bandwidth, u8 channel, u8 regd)
2260 {
2261 struct rtw_power_params pwr_param = {0};
2262 u8 tx_power;
2263 s8 offset;
2264
2265 rtw_get_tx_power_params(rtwdev, rf_path, rate, bandwidth,
2266 channel, regd, &pwr_param);
2267
2268 tx_power = pwr_param.pwr_base;
2269 offset = min3(pwr_param.pwr_offset,
2270 pwr_param.pwr_limit,
2271 pwr_param.pwr_sar);
2272
2273 if (rtwdev->chip->en_dis_dpd)
2274 offset += rtw_phy_get_dis_dpd_by_rate_diff(rtwdev, rate);
2275
2276 tx_power += offset + pwr_param.pwr_remnant;
2277
2278 if (tx_power > rtwdev->chip->max_power_index)
2279 tx_power = rtwdev->chip->max_power_index;
2280
2281 return tx_power;
2282 }
2283 EXPORT_SYMBOL(rtw_phy_get_tx_power_index);
2284
rtw_phy_set_tx_power_index_by_rs(struct rtw_dev * rtwdev,u8 ch,u8 path,u8 rs)2285 static void rtw_phy_set_tx_power_index_by_rs(struct rtw_dev *rtwdev,
2286 u8 ch, u8 path, u8 rs)
2287 {
2288 struct rtw_hal *hal = &rtwdev->hal;
2289 u8 regd = rtw_regd_get(rtwdev);
2290 const u8 *rates;
2291 u8 size;
2292 u8 rate;
2293 u8 pwr_idx;
2294 u8 bw;
2295 int i;
2296
2297 if (rs >= RTW_RATE_SECTION_NUM)
2298 return;
2299
2300 rates = rtw_rate_section[rs];
2301 size = rtw_rate_size[rs];
2302 bw = hal->current_band_width;
2303 for (i = 0; i < size; i++) {
2304 rate = rates[i];
2305 pwr_idx = rtw_phy_get_tx_power_index(rtwdev, path, rate,
2306 bw, ch, regd);
2307 hal->tx_pwr_tbl[path][rate] = pwr_idx;
2308 }
2309 }
2310
2311 /* set tx power level by path for each rates, note that the order of the rates
2312 * are *very* important, bacause 8822B/8821C combines every four bytes of tx
2313 * power index into a four-byte power index register, and calls set_tx_agc to
2314 * write these values into hardware
2315 */
rtw_phy_set_tx_power_level_by_path(struct rtw_dev * rtwdev,u8 ch,u8 path)2316 static void rtw_phy_set_tx_power_level_by_path(struct rtw_dev *rtwdev,
2317 u8 ch, u8 path)
2318 {
2319 struct rtw_hal *hal = &rtwdev->hal;
2320 u8 rs;
2321
2322 /* do not need cck rates if we are not in 2.4G */
2323 if (hal->current_band_type == RTW_BAND_2G)
2324 rs = RTW_RATE_SECTION_CCK;
2325 else
2326 rs = RTW_RATE_SECTION_OFDM;
2327
2328 for (; rs < RTW_RATE_SECTION_NUM; rs++)
2329 rtw_phy_set_tx_power_index_by_rs(rtwdev, ch, path, rs);
2330 }
2331
rtw_phy_set_tx_power_level(struct rtw_dev * rtwdev,u8 channel)2332 void rtw_phy_set_tx_power_level(struct rtw_dev *rtwdev, u8 channel)
2333 {
2334 const struct rtw_chip_info *chip = rtwdev->chip;
2335 struct rtw_hal *hal = &rtwdev->hal;
2336 u8 path;
2337
2338 mutex_lock(&hal->tx_power_mutex);
2339
2340 for (path = 0; path < hal->rf_path_num; path++)
2341 rtw_phy_set_tx_power_level_by_path(rtwdev, channel, path);
2342
2343 chip->ops->set_tx_power_index(rtwdev);
2344 mutex_unlock(&hal->tx_power_mutex);
2345 }
2346 EXPORT_SYMBOL(rtw_phy_set_tx_power_level);
2347
2348 static void
rtw_phy_tx_power_by_rate_config_by_path(struct rtw_hal * hal,u8 path,u8 rs,u8 size,const u8 * rates)2349 rtw_phy_tx_power_by_rate_config_by_path(struct rtw_hal *hal, u8 path,
2350 u8 rs, u8 size, const u8 *rates)
2351 {
2352 u8 rate;
2353 u8 base_idx, rate_idx;
2354 s8 base_2g, base_5g;
2355
2356 if (size == 10) /* VHT rates */
2357 base_idx = rates[size - 3];
2358 else
2359 base_idx = rates[size - 1];
2360 base_2g = hal->tx_pwr_by_rate_offset_2g[path][base_idx];
2361 base_5g = hal->tx_pwr_by_rate_offset_5g[path][base_idx];
2362 hal->tx_pwr_by_rate_base_2g[path][rs] = base_2g;
2363 hal->tx_pwr_by_rate_base_5g[path][rs] = base_5g;
2364 for (rate = 0; rate < size; rate++) {
2365 rate_idx = rates[rate];
2366 hal->tx_pwr_by_rate_offset_2g[path][rate_idx] -= base_2g;
2367 hal->tx_pwr_by_rate_offset_5g[path][rate_idx] -= base_5g;
2368 }
2369 }
2370
rtw_phy_tx_power_by_rate_config(struct rtw_hal * hal)2371 void rtw_phy_tx_power_by_rate_config(struct rtw_hal *hal)
2372 {
2373 u8 path, rs;
2374
2375 for (path = 0; path < RTW_RF_PATH_MAX; path++)
2376 for (rs = 0; rs < RTW_RATE_SECTION_NUM; rs++)
2377 rtw_phy_tx_power_by_rate_config_by_path(hal, path, rs,
2378 rtw_rate_size[rs], rtw_rate_section[rs]);
2379 }
2380
2381 static void
__rtw_phy_tx_power_limit_config(struct rtw_hal * hal,u8 regd,u8 bw,u8 rs)2382 __rtw_phy_tx_power_limit_config(struct rtw_hal *hal, u8 regd, u8 bw, u8 rs)
2383 {
2384 s8 base;
2385 u8 ch;
2386
2387 for (ch = 0; ch < RTW_MAX_CHANNEL_NUM_2G; ch++) {
2388 base = hal->tx_pwr_by_rate_base_2g[0][rs];
2389 hal->tx_pwr_limit_2g[regd][bw][rs][ch] -= base;
2390 }
2391
2392 for (ch = 0; ch < RTW_MAX_CHANNEL_NUM_5G; ch++) {
2393 base = hal->tx_pwr_by_rate_base_5g[0][rs];
2394 hal->tx_pwr_limit_5g[regd][bw][rs][ch] -= base;
2395 }
2396 }
2397
rtw_phy_tx_power_limit_config(struct rtw_hal * hal)2398 void rtw_phy_tx_power_limit_config(struct rtw_hal *hal)
2399 {
2400 u8 regd, bw, rs;
2401
2402 /* default at channel 1 */
2403 hal->cch_by_bw[RTW_CHANNEL_WIDTH_20] = 1;
2404
2405 for (regd = 0; regd < RTW_REGD_MAX; regd++)
2406 for (bw = 0; bw < RTW_CHANNEL_WIDTH_MAX; bw++)
2407 for (rs = 0; rs < RTW_RATE_SECTION_NUM; rs++)
2408 __rtw_phy_tx_power_limit_config(hal, regd, bw, rs);
2409 }
2410
rtw_phy_init_tx_power_limit(struct rtw_dev * rtwdev,u8 regd,u8 bw,u8 rs)2411 static void rtw_phy_init_tx_power_limit(struct rtw_dev *rtwdev,
2412 u8 regd, u8 bw, u8 rs)
2413 {
2414 struct rtw_hal *hal = &rtwdev->hal;
2415 s8 max_power_index = (s8)rtwdev->chip->max_power_index;
2416 u8 ch;
2417
2418 /* 2.4G channels */
2419 for (ch = 0; ch < RTW_MAX_CHANNEL_NUM_2G; ch++)
2420 hal->tx_pwr_limit_2g[regd][bw][rs][ch] = max_power_index;
2421
2422 /* 5G channels */
2423 for (ch = 0; ch < RTW_MAX_CHANNEL_NUM_5G; ch++)
2424 hal->tx_pwr_limit_5g[regd][bw][rs][ch] = max_power_index;
2425 }
2426
rtw_phy_init_tx_power(struct rtw_dev * rtwdev)2427 void rtw_phy_init_tx_power(struct rtw_dev *rtwdev)
2428 {
2429 struct rtw_hal *hal = &rtwdev->hal;
2430 u8 regd, path, rate, rs, bw;
2431
2432 /* init tx power by rate offset */
2433 for (path = 0; path < RTW_RF_PATH_MAX; path++) {
2434 for (rate = 0; rate < DESC_RATE_MAX; rate++) {
2435 hal->tx_pwr_by_rate_offset_2g[path][rate] = 0;
2436 hal->tx_pwr_by_rate_offset_5g[path][rate] = 0;
2437 }
2438 }
2439
2440 /* init tx power limit */
2441 for (regd = 0; regd < RTW_REGD_MAX; regd++)
2442 for (bw = 0; bw < RTW_CHANNEL_WIDTH_MAX; bw++)
2443 for (rs = 0; rs < RTW_RATE_SECTION_NUM; rs++)
2444 rtw_phy_init_tx_power_limit(rtwdev, regd, bw,
2445 rs);
2446 }
2447
rtw_phy_config_swing_table(struct rtw_dev * rtwdev,struct rtw_swing_table * swing_table)2448 void rtw_phy_config_swing_table(struct rtw_dev *rtwdev,
2449 struct rtw_swing_table *swing_table)
2450 {
2451 const struct rtw_rfe_def *rfe_def = rtw_get_rfe_def(rtwdev);
2452 const struct rtw_pwr_track_tbl *tbl = rfe_def->pwr_track_tbl;
2453 u8 channel = rtwdev->hal.current_channel;
2454
2455 if (IS_CH_2G_BAND(channel)) {
2456 if (rtwdev->dm_info.tx_rate <= DESC_RATE11M) {
2457 swing_table->p[RF_PATH_A] = tbl->pwrtrk_2g_ccka_p;
2458 swing_table->n[RF_PATH_A] = tbl->pwrtrk_2g_ccka_n;
2459 swing_table->p[RF_PATH_B] = tbl->pwrtrk_2g_cckb_p;
2460 swing_table->n[RF_PATH_B] = tbl->pwrtrk_2g_cckb_n;
2461 swing_table->p[RF_PATH_C] = tbl->pwrtrk_2g_cckc_p;
2462 swing_table->n[RF_PATH_C] = tbl->pwrtrk_2g_cckc_n;
2463 swing_table->p[RF_PATH_D] = tbl->pwrtrk_2g_cckd_p;
2464 swing_table->n[RF_PATH_D] = tbl->pwrtrk_2g_cckd_n;
2465 } else {
2466 swing_table->p[RF_PATH_A] = tbl->pwrtrk_2ga_p;
2467 swing_table->n[RF_PATH_A] = tbl->pwrtrk_2ga_n;
2468 swing_table->p[RF_PATH_B] = tbl->pwrtrk_2gb_p;
2469 swing_table->n[RF_PATH_B] = tbl->pwrtrk_2gb_n;
2470 swing_table->p[RF_PATH_C] = tbl->pwrtrk_2gc_p;
2471 swing_table->n[RF_PATH_C] = tbl->pwrtrk_2gc_n;
2472 swing_table->p[RF_PATH_D] = tbl->pwrtrk_2gd_p;
2473 swing_table->n[RF_PATH_D] = tbl->pwrtrk_2gd_n;
2474 }
2475 } else if (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel)) {
2476 swing_table->p[RF_PATH_A] = tbl->pwrtrk_5ga_p[RTW_PWR_TRK_5G_1];
2477 swing_table->n[RF_PATH_A] = tbl->pwrtrk_5ga_n[RTW_PWR_TRK_5G_1];
2478 swing_table->p[RF_PATH_B] = tbl->pwrtrk_5gb_p[RTW_PWR_TRK_5G_1];
2479 swing_table->n[RF_PATH_B] = tbl->pwrtrk_5gb_n[RTW_PWR_TRK_5G_1];
2480 swing_table->p[RF_PATH_C] = tbl->pwrtrk_5gc_p[RTW_PWR_TRK_5G_1];
2481 swing_table->n[RF_PATH_C] = tbl->pwrtrk_5gc_n[RTW_PWR_TRK_5G_1];
2482 swing_table->p[RF_PATH_D] = tbl->pwrtrk_5gd_p[RTW_PWR_TRK_5G_1];
2483 swing_table->n[RF_PATH_D] = tbl->pwrtrk_5gd_n[RTW_PWR_TRK_5G_1];
2484 } else if (IS_CH_5G_BAND_3(channel)) {
2485 swing_table->p[RF_PATH_A] = tbl->pwrtrk_5ga_p[RTW_PWR_TRK_5G_2];
2486 swing_table->n[RF_PATH_A] = tbl->pwrtrk_5ga_n[RTW_PWR_TRK_5G_2];
2487 swing_table->p[RF_PATH_B] = tbl->pwrtrk_5gb_p[RTW_PWR_TRK_5G_2];
2488 swing_table->n[RF_PATH_B] = tbl->pwrtrk_5gb_n[RTW_PWR_TRK_5G_2];
2489 swing_table->p[RF_PATH_C] = tbl->pwrtrk_5gc_p[RTW_PWR_TRK_5G_2];
2490 swing_table->n[RF_PATH_C] = tbl->pwrtrk_5gc_n[RTW_PWR_TRK_5G_2];
2491 swing_table->p[RF_PATH_D] = tbl->pwrtrk_5gd_p[RTW_PWR_TRK_5G_2];
2492 swing_table->n[RF_PATH_D] = tbl->pwrtrk_5gd_n[RTW_PWR_TRK_5G_2];
2493 } else if (IS_CH_5G_BAND_4(channel)) {
2494 swing_table->p[RF_PATH_A] = tbl->pwrtrk_5ga_p[RTW_PWR_TRK_5G_3];
2495 swing_table->n[RF_PATH_A] = tbl->pwrtrk_5ga_n[RTW_PWR_TRK_5G_3];
2496 swing_table->p[RF_PATH_B] = tbl->pwrtrk_5gb_p[RTW_PWR_TRK_5G_3];
2497 swing_table->n[RF_PATH_B] = tbl->pwrtrk_5gb_n[RTW_PWR_TRK_5G_3];
2498 swing_table->p[RF_PATH_C] = tbl->pwrtrk_5gc_p[RTW_PWR_TRK_5G_3];
2499 swing_table->n[RF_PATH_C] = tbl->pwrtrk_5gc_n[RTW_PWR_TRK_5G_3];
2500 swing_table->p[RF_PATH_D] = tbl->pwrtrk_5gd_p[RTW_PWR_TRK_5G_3];
2501 swing_table->n[RF_PATH_D] = tbl->pwrtrk_5gd_n[RTW_PWR_TRK_5G_3];
2502 } else {
2503 swing_table->p[RF_PATH_A] = tbl->pwrtrk_2ga_p;
2504 swing_table->n[RF_PATH_A] = tbl->pwrtrk_2ga_n;
2505 swing_table->p[RF_PATH_B] = tbl->pwrtrk_2gb_p;
2506 swing_table->n[RF_PATH_B] = tbl->pwrtrk_2gb_n;
2507 swing_table->p[RF_PATH_C] = tbl->pwrtrk_2gc_p;
2508 swing_table->n[RF_PATH_C] = tbl->pwrtrk_2gc_n;
2509 swing_table->p[RF_PATH_D] = tbl->pwrtrk_2gd_p;
2510 swing_table->n[RF_PATH_D] = tbl->pwrtrk_2gd_n;
2511 }
2512 }
2513 EXPORT_SYMBOL(rtw_phy_config_swing_table);
2514
rtw_phy_pwrtrack_avg(struct rtw_dev * rtwdev,u8 thermal,u8 path)2515 void rtw_phy_pwrtrack_avg(struct rtw_dev *rtwdev, u8 thermal, u8 path)
2516 {
2517 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
2518
2519 ewma_thermal_add(&dm_info->avg_thermal[path], thermal);
2520 dm_info->thermal_avg[path] =
2521 ewma_thermal_read(&dm_info->avg_thermal[path]);
2522 }
2523 EXPORT_SYMBOL(rtw_phy_pwrtrack_avg);
2524
rtw_phy_pwrtrack_thermal_changed(struct rtw_dev * rtwdev,u8 thermal,u8 path)2525 bool rtw_phy_pwrtrack_thermal_changed(struct rtw_dev *rtwdev, u8 thermal,
2526 u8 path)
2527 {
2528 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
2529 u8 avg = ewma_thermal_read(&dm_info->avg_thermal[path]);
2530
2531 if (avg == thermal)
2532 return false;
2533
2534 return true;
2535 }
2536 EXPORT_SYMBOL(rtw_phy_pwrtrack_thermal_changed);
2537
rtw_phy_pwrtrack_get_delta(struct rtw_dev * rtwdev,u8 path)2538 u8 rtw_phy_pwrtrack_get_delta(struct rtw_dev *rtwdev, u8 path)
2539 {
2540 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
2541 u8 therm_avg, therm_efuse, therm_delta;
2542
2543 therm_avg = dm_info->thermal_avg[path];
2544 therm_efuse = rtwdev->efuse.thermal_meter[path];
2545 therm_delta = abs(therm_avg - therm_efuse);
2546
2547 return min_t(u8, therm_delta, RTW_PWR_TRK_TBL_SZ - 1);
2548 }
2549 EXPORT_SYMBOL(rtw_phy_pwrtrack_get_delta);
2550
rtw_phy_pwrtrack_get_pwridx(struct rtw_dev * rtwdev,struct rtw_swing_table * swing_table,u8 tbl_path,u8 therm_path,u8 delta)2551 s8 rtw_phy_pwrtrack_get_pwridx(struct rtw_dev *rtwdev,
2552 struct rtw_swing_table *swing_table,
2553 u8 tbl_path, u8 therm_path, u8 delta)
2554 {
2555 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
2556 const u8 *delta_swing_table_idx_pos;
2557 const u8 *delta_swing_table_idx_neg;
2558
2559 if (delta >= RTW_PWR_TRK_TBL_SZ) {
2560 rtw_warn(rtwdev, "power track table overflow\n");
2561 return 0;
2562 }
2563
2564 if (!swing_table) {
2565 rtw_warn(rtwdev, "swing table not configured\n");
2566 return 0;
2567 }
2568
2569 delta_swing_table_idx_pos = swing_table->p[tbl_path];
2570 delta_swing_table_idx_neg = swing_table->n[tbl_path];
2571
2572 if (!delta_swing_table_idx_pos || !delta_swing_table_idx_neg) {
2573 rtw_warn(rtwdev, "invalid swing table index\n");
2574 return 0;
2575 }
2576
2577 if (dm_info->thermal_avg[therm_path] >
2578 rtwdev->efuse.thermal_meter[therm_path])
2579 return delta_swing_table_idx_pos[delta];
2580 else
2581 return -delta_swing_table_idx_neg[delta];
2582 }
2583 EXPORT_SYMBOL(rtw_phy_pwrtrack_get_pwridx);
2584
rtw_phy_pwrtrack_need_lck(struct rtw_dev * rtwdev)2585 bool rtw_phy_pwrtrack_need_lck(struct rtw_dev *rtwdev)
2586 {
2587 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
2588 u8 delta_lck;
2589
2590 delta_lck = abs(dm_info->thermal_avg[0] - dm_info->thermal_meter_lck);
2591 if (delta_lck >= rtwdev->chip->lck_threshold) {
2592 dm_info->thermal_meter_lck = dm_info->thermal_avg[0];
2593 return true;
2594 }
2595 return false;
2596 }
2597 EXPORT_SYMBOL(rtw_phy_pwrtrack_need_lck);
2598
rtw_phy_pwrtrack_need_iqk(struct rtw_dev * rtwdev)2599 bool rtw_phy_pwrtrack_need_iqk(struct rtw_dev *rtwdev)
2600 {
2601 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
2602 u8 delta_iqk;
2603
2604 delta_iqk = abs(dm_info->thermal_avg[0] - dm_info->thermal_meter_k);
2605 if (delta_iqk >= rtwdev->chip->iqk_threshold) {
2606 dm_info->thermal_meter_k = dm_info->thermal_avg[0];
2607 return true;
2608 }
2609 return false;
2610 }
2611 EXPORT_SYMBOL(rtw_phy_pwrtrack_need_iqk);
2612
rtw_phy_set_tx_path_by_reg(struct rtw_dev * rtwdev,enum rtw_bb_path tx_path_sel_1ss)2613 static void rtw_phy_set_tx_path_by_reg(struct rtw_dev *rtwdev,
2614 enum rtw_bb_path tx_path_sel_1ss)
2615 {
2616 struct rtw_path_div *path_div = &rtwdev->dm_path_div;
2617 enum rtw_bb_path tx_path_sel_cck = tx_path_sel_1ss;
2618 const struct rtw_chip_info *chip = rtwdev->chip;
2619
2620 if (tx_path_sel_1ss == path_div->current_tx_path)
2621 return;
2622
2623 path_div->current_tx_path = tx_path_sel_1ss;
2624 rtw_dbg(rtwdev, RTW_DBG_PATH_DIV, "Switch TX path=%s\n",
2625 tx_path_sel_1ss == BB_PATH_A ? "A" : "B");
2626 chip->ops->config_tx_path(rtwdev, rtwdev->hal.antenna_tx,
2627 tx_path_sel_1ss, tx_path_sel_cck, false);
2628 }
2629
rtw_phy_tx_path_div_select(struct rtw_dev * rtwdev)2630 static void rtw_phy_tx_path_div_select(struct rtw_dev *rtwdev)
2631 {
2632 struct rtw_path_div *path_div = &rtwdev->dm_path_div;
2633 enum rtw_bb_path path = path_div->current_tx_path;
2634 s32 rssi_a = 0, rssi_b = 0;
2635
2636 if (path_div->path_a_cnt)
2637 rssi_a = path_div->path_a_sum / path_div->path_a_cnt;
2638 else
2639 rssi_a = 0;
2640 if (path_div->path_b_cnt)
2641 rssi_b = path_div->path_b_sum / path_div->path_b_cnt;
2642 else
2643 rssi_b = 0;
2644
2645 if (rssi_a != rssi_b)
2646 path = (rssi_a > rssi_b) ? BB_PATH_A : BB_PATH_B;
2647
2648 path_div->path_a_cnt = 0;
2649 path_div->path_a_sum = 0;
2650 path_div->path_b_cnt = 0;
2651 path_div->path_b_sum = 0;
2652 rtw_phy_set_tx_path_by_reg(rtwdev, path);
2653 }
2654
rtw_phy_tx_path_diversity_2ss(struct rtw_dev * rtwdev)2655 static void rtw_phy_tx_path_diversity_2ss(struct rtw_dev *rtwdev)
2656 {
2657 if (rtwdev->hal.antenna_rx != BB_PATH_AB) {
2658 rtw_dbg(rtwdev, RTW_DBG_PATH_DIV,
2659 "[Return] tx_Path_en=%d, rx_Path_en=%d\n",
2660 rtwdev->hal.antenna_tx, rtwdev->hal.antenna_rx);
2661 return;
2662 }
2663 if (rtwdev->sta_cnt == 0) {
2664 rtw_dbg(rtwdev, RTW_DBG_PATH_DIV, "No Link\n");
2665 return;
2666 }
2667
2668 rtw_phy_tx_path_div_select(rtwdev);
2669 }
2670
rtw_phy_tx_path_diversity(struct rtw_dev * rtwdev)2671 void rtw_phy_tx_path_diversity(struct rtw_dev *rtwdev)
2672 {
2673 const struct rtw_chip_info *chip = rtwdev->chip;
2674
2675 if (!chip->path_div_supported)
2676 return;
2677
2678 rtw_phy_tx_path_diversity_2ss(rtwdev);
2679 }
2680