1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation. 3 */ 4 5 #include "main.h" 6 #include "reg.h" 7 #include "bf.h" 8 #include "debug.h" 9 10 void rtw_bf_disassoc(struct rtw_dev *rtwdev, struct ieee80211_vif *vif, 11 struct ieee80211_bss_conf *bss_conf) 12 { 13 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; 14 struct rtw_bfee *bfee = &rtwvif->bfee; 15 struct rtw_bf_info *bfinfo = &rtwdev->bf_info; 16 17 if (bfee->role == RTW_BFEE_NONE) 18 return; 19 20 if (bfee->role == RTW_BFEE_MU) 21 bfinfo->bfer_mu_cnt--; 22 else if (bfee->role == RTW_BFEE_SU) 23 bfinfo->bfer_su_cnt--; 24 25 rtw_chip_config_bfee(rtwdev, rtwvif, bfee, false); 26 27 bfee->role = RTW_BFEE_NONE; 28 } 29 30 void rtw_bf_assoc(struct rtw_dev *rtwdev, struct ieee80211_vif *vif, 31 struct ieee80211_bss_conf *bss_conf) 32 { 33 const struct rtw_chip_info *chip = rtwdev->chip; 34 struct ieee80211_hw *hw = rtwdev->hw; 35 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; 36 struct rtw_bfee *bfee = &rtwvif->bfee; 37 struct rtw_bf_info *bfinfo = &rtwdev->bf_info; 38 struct ieee80211_sta *sta; 39 struct ieee80211_sta_vht_cap *vht_cap; 40 struct ieee80211_sta_vht_cap *ic_vht_cap; 41 const u8 *bssid = bss_conf->bssid; 42 u32 sound_dim; 43 u8 i; 44 45 if (!(chip->band & RTW_BAND_5G)) 46 return; 47 48 rcu_read_lock(); 49 50 sta = ieee80211_find_sta(vif, bssid); 51 if (!sta) { 52 rcu_read_unlock(); 53 54 rtw_warn(rtwdev, "failed to find station entry for bss %pM\n", 55 bssid); 56 return; 57 } 58 59 ic_vht_cap = &hw->wiphy->bands[NL80211_BAND_5GHZ]->vht_cap; 60 vht_cap = &sta->deflink.vht_cap; 61 62 rcu_read_unlock(); 63 64 if ((ic_vht_cap->cap & IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE) && 65 (vht_cap->cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE)) { 66 if (bfinfo->bfer_mu_cnt >= chip->bfer_mu_max_num) { 67 rtw_dbg(rtwdev, RTW_DBG_BF, "mu bfer number over limit\n"); 68 return; 69 } 70 71 ether_addr_copy(bfee->mac_addr, bssid); 72 bfee->role = RTW_BFEE_MU; 73 bfee->p_aid = (bssid[5] << 1) | (bssid[4] >> 7); 74 bfee->aid = vif->cfg.aid; 75 bfinfo->bfer_mu_cnt++; 76 77 rtw_chip_config_bfee(rtwdev, rtwvif, bfee, true); 78 } else if ((ic_vht_cap->cap & IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE) && 79 (vht_cap->cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) { 80 if (bfinfo->bfer_su_cnt >= chip->bfer_su_max_num) { 81 rtw_dbg(rtwdev, RTW_DBG_BF, "su bfer number over limit\n"); 82 return; 83 } 84 85 sound_dim = vht_cap->cap & 86 IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK; 87 sound_dim >>= IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_SHIFT; 88 89 ether_addr_copy(bfee->mac_addr, bssid); 90 bfee->role = RTW_BFEE_SU; 91 bfee->sound_dim = (u8)sound_dim; 92 bfee->g_id = 0; 93 bfee->p_aid = (bssid[5] << 1) | (bssid[4] >> 7); 94 bfinfo->bfer_su_cnt++; 95 for (i = 0; i < chip->bfer_su_max_num; i++) { 96 if (!test_bit(i, bfinfo->bfer_su_reg_maping)) { 97 set_bit(i, bfinfo->bfer_su_reg_maping); 98 bfee->su_reg_index = i; 99 break; 100 } 101 } 102 103 rtw_chip_config_bfee(rtwdev, rtwvif, bfee, true); 104 } 105 } 106 107 void rtw_bf_init_bfer_entry_mu(struct rtw_dev *rtwdev, 108 struct mu_bfer_init_para *param) 109 { 110 u16 mu_bf_ctl = 0; 111 u8 *addr = param->bfer_address; 112 int i; 113 114 for (i = 0; i < ETH_ALEN; i++) 115 rtw_write8(rtwdev, REG_ASSOCIATED_BFMER0_INFO + i, addr[i]); 116 rtw_write16(rtwdev, REG_ASSOCIATED_BFMER0_INFO + 6, param->paid); 117 rtw_write16(rtwdev, REG_TX_CSI_RPT_PARAM_BW20, param->csi_para); 118 119 mu_bf_ctl = rtw_read16(rtwdev, REG_WMAC_MU_BF_CTL) & 0xC000; 120 mu_bf_ctl |= param->my_aid | (param->csi_length_sel << 12); 121 rtw_write16(rtwdev, REG_WMAC_MU_BF_CTL, mu_bf_ctl); 122 } 123 124 void rtw_bf_cfg_sounding(struct rtw_dev *rtwdev, struct rtw_vif *vif, 125 enum rtw_trx_desc_rate rate) 126 { 127 u8 csi_rsc = CSI_RSC_FOLLOW_RX_PACKET_BW; 128 u32 psf_ctl = 0; 129 130 if (rtwdev->chip->id == RTW_CHIP_TYPE_8822C) 131 csi_rsc = CSI_RSC_PRIMARY_20M_BW; 132 133 psf_ctl = rtw_read32(rtwdev, REG_BBPSF_CTRL) | 134 BIT_WMAC_USE_NDPARATE | 135 (csi_rsc << 13); 136 137 rtw_write8_mask(rtwdev, REG_SND_PTCL_CTRL, BIT_MASK_BEAMFORM, 138 RTW_SND_CTRL_SOUNDING); 139 rtw_write8(rtwdev, REG_SND_PTCL_CTRL + 3, 0x26); 140 rtw_write8_clr(rtwdev, REG_RXFLTMAP1, BIT_RXFLTMAP1_BF_REPORT_POLL); 141 rtw_write8_clr(rtwdev, REG_RXFLTMAP4, BIT_RXFLTMAP4_BF_REPORT_POLL); 142 143 if (vif->net_type == RTW_NET_AP_MODE) 144 rtw_write32(rtwdev, REG_BBPSF_CTRL, psf_ctl | BIT(12)); 145 else 146 rtw_write32(rtwdev, REG_BBPSF_CTRL, psf_ctl & ~BIT(12)); 147 } 148 149 void rtw_bf_cfg_mu_bfee(struct rtw_dev *rtwdev, struct cfg_mumimo_para *param) 150 { 151 u8 mu_tbl_sel; 152 u8 mu_valid; 153 154 mu_valid = rtw_read8(rtwdev, REG_MU_TX_CTL) & 155 ~BIT_MASK_R_MU_TABLE_VALID; 156 157 rtw_write8(rtwdev, REG_MU_TX_CTL, 158 (mu_valid | BIT(0) | BIT(1)) & ~(BIT(7))); 159 160 mu_tbl_sel = rtw_read8(rtwdev, REG_MU_TX_CTL + 1) & 0xF8; 161 162 rtw_write8(rtwdev, REG_MU_TX_CTL + 1, mu_tbl_sel); 163 rtw_write32(rtwdev, REG_MU_STA_GID_VLD, param->given_gid_tab[0]); 164 rtw_write32(rtwdev, REG_MU_STA_USER_POS_INFO, param->given_user_pos[0]); 165 rtw_write32(rtwdev, REG_MU_STA_USER_POS_INFO + 4, 166 param->given_user_pos[1]); 167 168 rtw_write8(rtwdev, REG_MU_TX_CTL + 1, mu_tbl_sel | 1); 169 rtw_write32(rtwdev, REG_MU_STA_GID_VLD, param->given_gid_tab[1]); 170 rtw_write32(rtwdev, REG_MU_STA_USER_POS_INFO, param->given_user_pos[2]); 171 rtw_write32(rtwdev, REG_MU_STA_USER_POS_INFO + 4, 172 param->given_user_pos[3]); 173 } 174 175 void rtw_bf_del_bfer_entry_mu(struct rtw_dev *rtwdev) 176 { 177 rtw_write32(rtwdev, REG_ASSOCIATED_BFMER0_INFO, 0); 178 rtw_write32(rtwdev, REG_ASSOCIATED_BFMER0_INFO + 4, 0); 179 rtw_write16(rtwdev, REG_WMAC_MU_BF_CTL, 0); 180 rtw_write8(rtwdev, REG_MU_TX_CTL, 0); 181 } 182 183 void rtw_bf_del_sounding(struct rtw_dev *rtwdev) 184 { 185 rtw_write8_mask(rtwdev, REG_SND_PTCL_CTRL, BIT_MASK_BEAMFORM, 0); 186 } 187 188 void rtw_bf_enable_bfee_su(struct rtw_dev *rtwdev, struct rtw_vif *vif, 189 struct rtw_bfee *bfee) 190 { 191 u8 nc_index = hweight8(rtwdev->hal.antenna_rx) - 1; 192 u8 nr_index = bfee->sound_dim; 193 u8 grouping = 0, codebookinfo = 1, coefficientsize = 3; 194 u32 addr_bfer_info, addr_csi_rpt, csi_param; 195 u8 i; 196 197 rtw_dbg(rtwdev, RTW_DBG_BF, "config as an su bfee\n"); 198 199 switch (bfee->su_reg_index) { 200 case 1: 201 addr_bfer_info = REG_ASSOCIATED_BFMER1_INFO; 202 addr_csi_rpt = REG_TX_CSI_RPT_PARAM_BW20 + 2; 203 break; 204 case 0: 205 default: 206 addr_bfer_info = REG_ASSOCIATED_BFMER0_INFO; 207 addr_csi_rpt = REG_TX_CSI_RPT_PARAM_BW20; 208 break; 209 } 210 211 /* Sounding protocol control */ 212 rtw_write8_mask(rtwdev, REG_SND_PTCL_CTRL, BIT_MASK_BEAMFORM, 213 RTW_SND_CTRL_SOUNDING); 214 215 /* MAC address/Partial AID of Beamformer */ 216 for (i = 0; i < ETH_ALEN; i++) 217 rtw_write8(rtwdev, addr_bfer_info + i, bfee->mac_addr[i]); 218 219 csi_param = (u16)((coefficientsize << 10) | 220 (codebookinfo << 8) | 221 (grouping << 6) | 222 (nr_index << 3) | 223 nc_index); 224 rtw_write16(rtwdev, addr_csi_rpt, csi_param); 225 226 /* ndp rx standby timer */ 227 rtw_write8(rtwdev, REG_SND_PTCL_CTRL + 3, RTW_NDP_RX_STANDBY_TIME); 228 } 229 EXPORT_SYMBOL(rtw_bf_enable_bfee_su); 230 231 /* nc index: 1 2T2R 0 1T1R 232 * nr index: 1 use Nsts 0 use reg setting 233 * codebookinfo: 1 802.11ac 3 802.11n 234 */ 235 void rtw_bf_enable_bfee_mu(struct rtw_dev *rtwdev, struct rtw_vif *vif, 236 struct rtw_bfee *bfee) 237 { 238 struct rtw_bf_info *bf_info = &rtwdev->bf_info; 239 struct mu_bfer_init_para param; 240 u8 nc_index = hweight8(rtwdev->hal.antenna_rx) - 1; 241 u8 nr_index = 1; 242 u8 grouping = 0, codebookinfo = 1, coefficientsize = 0; 243 u32 csi_param; 244 245 rtw_dbg(rtwdev, RTW_DBG_BF, "config as an mu bfee\n"); 246 247 csi_param = (u16)((coefficientsize << 10) | 248 (codebookinfo << 8) | 249 (grouping << 6) | 250 (nr_index << 3) | 251 nc_index); 252 253 rtw_dbg(rtwdev, RTW_DBG_BF, "nc=%d nr=%d group=%d codebookinfo=%d coefficientsize=%d\n", 254 nc_index, nr_index, grouping, codebookinfo, 255 coefficientsize); 256 257 param.paid = bfee->p_aid; 258 param.csi_para = csi_param; 259 param.my_aid = bfee->aid & 0xfff; 260 param.csi_length_sel = HAL_CSI_SEG_4K; 261 ether_addr_copy(param.bfer_address, bfee->mac_addr); 262 263 rtw_bf_init_bfer_entry_mu(rtwdev, ¶m); 264 265 bf_info->cur_csi_rpt_rate = DESC_RATE6M; 266 rtw_bf_cfg_sounding(rtwdev, vif, DESC_RATE6M); 267 268 /* accept action_no_ack */ 269 rtw_write16_set(rtwdev, REG_RXFLTMAP0, BIT_RXFLTMAP0_ACTIONNOACK); 270 271 /* accept NDPA and BF report poll */ 272 rtw_write16_set(rtwdev, REG_RXFLTMAP1, BIT_RXFLTMAP1_BF); 273 } 274 EXPORT_SYMBOL(rtw_bf_enable_bfee_mu); 275 276 void rtw_bf_remove_bfee_su(struct rtw_dev *rtwdev, 277 struct rtw_bfee *bfee) 278 { 279 struct rtw_bf_info *bfinfo = &rtwdev->bf_info; 280 281 rtw_dbg(rtwdev, RTW_DBG_BF, "remove as a su bfee\n"); 282 rtw_write8_mask(rtwdev, REG_SND_PTCL_CTRL, BIT_MASK_BEAMFORM, 283 RTW_SND_CTRL_REMOVE); 284 285 switch (bfee->su_reg_index) { 286 case 0: 287 rtw_write32(rtwdev, REG_ASSOCIATED_BFMER0_INFO, 0); 288 rtw_write16(rtwdev, REG_ASSOCIATED_BFMER0_INFO + 4, 0); 289 rtw_write16(rtwdev, REG_TX_CSI_RPT_PARAM_BW20, 0); 290 break; 291 case 1: 292 rtw_write32(rtwdev, REG_ASSOCIATED_BFMER1_INFO, 0); 293 rtw_write16(rtwdev, REG_ASSOCIATED_BFMER1_INFO + 4, 0); 294 rtw_write16(rtwdev, REG_TX_CSI_RPT_PARAM_BW20 + 2, 0); 295 break; 296 } 297 298 clear_bit(bfee->su_reg_index, bfinfo->bfer_su_reg_maping); 299 bfee->su_reg_index = 0xFF; 300 } 301 EXPORT_SYMBOL(rtw_bf_remove_bfee_su); 302 303 void rtw_bf_remove_bfee_mu(struct rtw_dev *rtwdev, 304 struct rtw_bfee *bfee) 305 { 306 struct rtw_bf_info *bfinfo = &rtwdev->bf_info; 307 308 rtw_write8_mask(rtwdev, REG_SND_PTCL_CTRL, BIT_MASK_BEAMFORM, 309 RTW_SND_CTRL_REMOVE); 310 311 rtw_bf_del_bfer_entry_mu(rtwdev); 312 313 if (bfinfo->bfer_su_cnt == 0 && bfinfo->bfer_mu_cnt == 0) 314 rtw_bf_del_sounding(rtwdev); 315 } 316 EXPORT_SYMBOL(rtw_bf_remove_bfee_mu); 317 318 void rtw_bf_set_gid_table(struct rtw_dev *rtwdev, struct ieee80211_vif *vif, 319 struct ieee80211_bss_conf *conf) 320 { 321 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; 322 struct rtw_bfee *bfee = &rtwvif->bfee; 323 struct cfg_mumimo_para param; 324 325 if (bfee->role != RTW_BFEE_MU) { 326 rtw_dbg(rtwdev, RTW_DBG_BF, "this vif is not mu bfee\n"); 327 return; 328 } 329 330 param.grouping_bitmap = 0; 331 param.mu_tx_en = 0; 332 memset(param.sounding_sts, 0, 6); 333 memcpy(param.given_gid_tab, conf->mu_group.membership, 8); 334 memcpy(param.given_user_pos, conf->mu_group.position, 16); 335 rtw_dbg(rtwdev, RTW_DBG_BF, "STA0: gid_valid=0x%x, user_position_l=0x%x, user_position_h=0x%x\n", 336 param.given_gid_tab[0], param.given_user_pos[0], 337 param.given_user_pos[1]); 338 339 rtw_dbg(rtwdev, RTW_DBG_BF, "STA1: gid_valid=0x%x, user_position_l=0x%x, user_position_h=0x%x\n", 340 param.given_gid_tab[1], param.given_user_pos[2], 341 param.given_user_pos[3]); 342 343 rtw_bf_cfg_mu_bfee(rtwdev, ¶m); 344 } 345 EXPORT_SYMBOL(rtw_bf_set_gid_table); 346 347 void rtw_bf_phy_init(struct rtw_dev *rtwdev) 348 { 349 u8 tmp8; 350 u32 tmp32; 351 u8 retry_limit = 0xA; 352 u8 ndpa_rate = 0x10; 353 u8 ack_policy = 3; 354 355 tmp32 = rtw_read32(rtwdev, REG_MU_TX_CTL); 356 /* Enable P1 aggr new packet according to P0 transfer time */ 357 tmp32 |= BIT_MU_P1_WAIT_STATE_EN; 358 /* MU Retry Limit */ 359 tmp32 &= ~BIT_MASK_R_MU_RL; 360 tmp32 |= (retry_limit << BIT_SHIFT_R_MU_RL) & BIT_MASK_R_MU_RL; 361 /* Disable Tx MU-MIMO until sounding done */ 362 tmp32 &= ~BIT_EN_MU_MIMO; 363 /* Clear validity of MU STAs */ 364 tmp32 &= ~BIT_MASK_R_MU_TABLE_VALID; 365 rtw_write32(rtwdev, REG_MU_TX_CTL, tmp32); 366 367 /* MU-MIMO Option as default value */ 368 tmp8 = ack_policy << BIT_SHIFT_WMAC_TXMU_ACKPOLICY; 369 tmp8 |= BIT_WMAC_TXMU_ACKPOLICY_EN; 370 rtw_write8(rtwdev, REG_WMAC_MU_BF_OPTION, tmp8); 371 372 /* MU-MIMO Control as default value */ 373 rtw_write16(rtwdev, REG_WMAC_MU_BF_CTL, 0); 374 /* Set MU NDPA rate & BW source */ 375 rtw_write32_set(rtwdev, REG_TXBF_CTRL, BIT_USE_NDPA_PARAMETER); 376 /* Set NDPA Rate */ 377 rtw_write8(rtwdev, REG_NDPA_OPT_CTRL, ndpa_rate); 378 379 rtw_write32_mask(rtwdev, REG_BBPSF_CTRL, BIT_MASK_CSI_RATE, 380 DESC_RATE6M); 381 } 382 EXPORT_SYMBOL(rtw_bf_phy_init); 383 384 void rtw_bf_cfg_csi_rate(struct rtw_dev *rtwdev, u8 rssi, u8 cur_rate, 385 u8 fixrate_en, u8 *new_rate) 386 { 387 u32 csi_cfg; 388 u16 cur_rrsr; 389 390 csi_cfg = rtw_read32(rtwdev, REG_BBPSF_CTRL) & ~BIT_MASK_CSI_RATE; 391 cur_rrsr = rtw_read16(rtwdev, REG_RRSR); 392 393 if (rtwdev->chip->id == RTW_CHIP_TYPE_8822C) 394 csi_cfg |= BIT_CSI_FORCE_RATE; 395 396 if (rssi >= 40) { 397 if (cur_rate != DESC_RATE54M) { 398 cur_rrsr |= BIT(DESC_RATE54M); 399 csi_cfg |= (DESC_RATE54M & BIT_MASK_CSI_RATE_VAL) << 400 BIT_SHIFT_CSI_RATE; 401 rtw_write16(rtwdev, REG_RRSR, cur_rrsr); 402 rtw_write32(rtwdev, REG_BBPSF_CTRL, csi_cfg); 403 } 404 *new_rate = DESC_RATE54M; 405 } else { 406 if (cur_rate != DESC_RATE24M) { 407 cur_rrsr &= ~BIT(DESC_RATE54M); 408 csi_cfg |= (DESC_RATE54M & BIT_MASK_CSI_RATE_VAL) << 409 BIT_SHIFT_CSI_RATE; 410 rtw_write16(rtwdev, REG_RRSR, cur_rrsr); 411 rtw_write32(rtwdev, REG_BBPSF_CTRL, csi_cfg); 412 } 413 *new_rate = DESC_RATE24M; 414 } 415 } 416 EXPORT_SYMBOL(rtw_bf_cfg_csi_rate); 417