1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #include "acpi.h"
6 #include "chan.h"
7 #include "coex.h"
8 #include "debug.h"
9 #include "fw.h"
10 #include "mac.h"
11 #include "phy.h"
12 #include "ps.h"
13 #include "reg.h"
14 #include "sar.h"
15 #include "txrx.h"
16 #include "util.h"
17
rtw89_phy0_phy1_offset(struct rtw89_dev * rtwdev,u32 addr)18 static u32 rtw89_phy0_phy1_offset(struct rtw89_dev *rtwdev, u32 addr)
19 {
20 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
21
22 return phy->phy0_phy1_offset(rtwdev, addr);
23 }
24
get_max_amsdu_len(struct rtw89_dev * rtwdev,const struct rtw89_ra_report * report)25 static u16 get_max_amsdu_len(struct rtw89_dev *rtwdev,
26 const struct rtw89_ra_report *report)
27 {
28 u32 bit_rate = report->bit_rate;
29
30 /* lower than ofdm, do not aggregate */
31 if (bit_rate < 550)
32 return 1;
33
34 /* avoid AMSDU for legacy rate */
35 if (report->might_fallback_legacy)
36 return 1;
37
38 /* lower than 20M vht 2ss mcs8, make it small */
39 if (bit_rate < 1800)
40 return 1200;
41
42 /* lower than 40M vht 2ss mcs9, make it medium */
43 if (bit_rate < 4000)
44 return 2600;
45
46 /* not yet 80M vht 2ss mcs8/9, make it twice regular packet size */
47 if (bit_rate < 7000)
48 return 3500;
49
50 return rtwdev->chip->max_amsdu_limit;
51 }
52
get_mcs_ra_mask(u16 mcs_map,u8 highest_mcs,u8 gap)53 static u64 get_mcs_ra_mask(u16 mcs_map, u8 highest_mcs, u8 gap)
54 {
55 u64 ra_mask = 0;
56 u8 mcs_cap;
57 int i, nss;
58
59 for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 12) {
60 mcs_cap = mcs_map & 0x3;
61 switch (mcs_cap) {
62 case 2:
63 ra_mask |= GENMASK_ULL(highest_mcs, 0) << nss;
64 break;
65 case 1:
66 ra_mask |= GENMASK_ULL(highest_mcs - gap, 0) << nss;
67 break;
68 case 0:
69 ra_mask |= GENMASK_ULL(highest_mcs - gap * 2, 0) << nss;
70 break;
71 default:
72 break;
73 }
74 }
75
76 return ra_mask;
77 }
78
get_he_ra_mask(struct ieee80211_link_sta * link_sta)79 static u64 get_he_ra_mask(struct ieee80211_link_sta *link_sta)
80 {
81 struct ieee80211_sta_he_cap cap = link_sta->he_cap;
82 u16 mcs_map;
83
84 switch (link_sta->bandwidth) {
85 case IEEE80211_STA_RX_BW_160:
86 if (cap.he_cap_elem.phy_cap_info[0] &
87 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G)
88 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80p80);
89 else
90 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_160);
91 break;
92 default:
93 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80);
94 }
95
96 /* MCS11, MCS9, MCS7 */
97 return get_mcs_ra_mask(mcs_map, 11, 2);
98 }
99
get_eht_mcs_ra_mask(u8 * max_nss,u8 start_mcs,u8 n_nss)100 static u64 get_eht_mcs_ra_mask(u8 *max_nss, u8 start_mcs, u8 n_nss)
101 {
102 u64 nss_mcs_shift;
103 u64 nss_mcs_val;
104 u64 mask = 0;
105 int i, j;
106 u8 nss;
107
108 for (i = 0; i < n_nss; i++) {
109 nss = u8_get_bits(max_nss[i], IEEE80211_EHT_MCS_NSS_RX);
110 if (!nss)
111 continue;
112
113 nss_mcs_val = GENMASK_ULL(start_mcs + i * 2, 0);
114
115 for (j = 0, nss_mcs_shift = 12; j < nss; j++, nss_mcs_shift += 16)
116 mask |= nss_mcs_val << nss_mcs_shift;
117 }
118
119 return mask;
120 }
121
get_eht_ra_mask(struct ieee80211_link_sta * link_sta)122 static u64 get_eht_ra_mask(struct ieee80211_link_sta *link_sta)
123 {
124 struct ieee80211_sta_eht_cap *eht_cap = &link_sta->eht_cap;
125 struct ieee80211_eht_mcs_nss_supp_20mhz_only *mcs_nss_20mhz;
126 struct ieee80211_eht_mcs_nss_supp_bw *mcs_nss;
127 u8 *he_phy_cap = link_sta->he_cap.he_cap_elem.phy_cap_info;
128
129 switch (link_sta->bandwidth) {
130 case IEEE80211_STA_RX_BW_320:
131 mcs_nss = &eht_cap->eht_mcs_nss_supp.bw._320;
132 /* MCS 9, 11, 13 */
133 return get_eht_mcs_ra_mask(mcs_nss->rx_tx_max_nss, 9, 3);
134 case IEEE80211_STA_RX_BW_160:
135 mcs_nss = &eht_cap->eht_mcs_nss_supp.bw._160;
136 /* MCS 9, 11, 13 */
137 return get_eht_mcs_ra_mask(mcs_nss->rx_tx_max_nss, 9, 3);
138 case IEEE80211_STA_RX_BW_20:
139 if (!(he_phy_cap[0] &
140 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_MASK_ALL)) {
141 mcs_nss_20mhz = &eht_cap->eht_mcs_nss_supp.only_20mhz;
142 /* MCS 7, 9, 11, 13 */
143 return get_eht_mcs_ra_mask(mcs_nss_20mhz->rx_tx_max_nss, 7, 4);
144 }
145 fallthrough;
146 case IEEE80211_STA_RX_BW_80:
147 default:
148 mcs_nss = &eht_cap->eht_mcs_nss_supp.bw._80;
149 /* MCS 9, 11, 13 */
150 return get_eht_mcs_ra_mask(mcs_nss->rx_tx_max_nss, 9, 3);
151 }
152 }
153
154 #define RA_FLOOR_TABLE_SIZE 7
155 #define RA_FLOOR_UP_GAP 3
rtw89_phy_ra_mask_rssi(struct rtw89_dev * rtwdev,u8 rssi,u8 ratr_state)156 static u64 rtw89_phy_ra_mask_rssi(struct rtw89_dev *rtwdev, u8 rssi,
157 u8 ratr_state)
158 {
159 u8 rssi_lv_t[RA_FLOOR_TABLE_SIZE] = {30, 44, 48, 52, 56, 60, 100};
160 u8 rssi_lv = 0;
161 u8 i;
162
163 rssi >>= 1;
164 for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) {
165 if (i >= ratr_state)
166 rssi_lv_t[i] += RA_FLOOR_UP_GAP;
167 if (rssi < rssi_lv_t[i]) {
168 rssi_lv = i;
169 break;
170 }
171 }
172 if (rssi_lv == 0)
173 return 0xffffffffffffffffULL;
174 else if (rssi_lv == 1)
175 return 0xfffffffffffffff0ULL;
176 else if (rssi_lv == 2)
177 return 0xffffffffffffefe0ULL;
178 else if (rssi_lv == 3)
179 return 0xffffffffffffcfc0ULL;
180 else if (rssi_lv == 4)
181 return 0xffffffffffff8f80ULL;
182 else if (rssi_lv >= 5)
183 return 0xffffffffffff0f00ULL;
184
185 return 0xffffffffffffffffULL;
186 }
187
rtw89_phy_ra_mask_recover(u64 ra_mask,u64 ra_mask_bak)188 static u64 rtw89_phy_ra_mask_recover(u64 ra_mask, u64 ra_mask_bak)
189 {
190 if ((ra_mask & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)) == 0)
191 ra_mask |= (ra_mask_bak & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES));
192
193 if (ra_mask == 0)
194 ra_mask |= (ra_mask_bak & (RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES));
195
196 return ra_mask;
197 }
198
rtw89_phy_ra_mask_cfg(struct rtw89_dev * rtwdev,struct rtw89_sta_link * rtwsta_link,struct ieee80211_link_sta * link_sta,const struct rtw89_chan * chan)199 static u64 rtw89_phy_ra_mask_cfg(struct rtw89_dev *rtwdev,
200 struct rtw89_sta_link *rtwsta_link,
201 struct ieee80211_link_sta *link_sta,
202 const struct rtw89_chan *chan)
203 {
204 struct cfg80211_bitrate_mask *mask = &rtwsta_link->mask;
205 enum nl80211_band band;
206 u64 cfg_mask;
207
208 if (!rtwsta_link->use_cfg_mask)
209 return -1;
210
211 switch (chan->band_type) {
212 case RTW89_BAND_2G:
213 band = NL80211_BAND_2GHZ;
214 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_2GHZ].legacy,
215 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES);
216 break;
217 case RTW89_BAND_5G:
218 band = NL80211_BAND_5GHZ;
219 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_5GHZ].legacy,
220 RA_MASK_OFDM_RATES);
221 break;
222 case RTW89_BAND_6G:
223 band = NL80211_BAND_6GHZ;
224 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_6GHZ].legacy,
225 RA_MASK_OFDM_RATES);
226 break;
227 default:
228 rtw89_warn(rtwdev, "unhandled band type %d\n", chan->band_type);
229 return -1;
230 }
231
232 if (link_sta->he_cap.has_he) {
233 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[0],
234 RA_MASK_HE_1SS_RATES);
235 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[1],
236 RA_MASK_HE_2SS_RATES);
237 } else if (link_sta->vht_cap.vht_supported) {
238 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0],
239 RA_MASK_VHT_1SS_RATES);
240 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1],
241 RA_MASK_VHT_2SS_RATES);
242 } else if (link_sta->ht_cap.ht_supported) {
243 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0],
244 RA_MASK_HT_1SS_RATES);
245 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1],
246 RA_MASK_HT_2SS_RATES);
247 }
248
249 return cfg_mask;
250 }
251
252 static const u64
253 rtw89_ra_mask_ht_rates[4] = {RA_MASK_HT_1SS_RATES, RA_MASK_HT_2SS_RATES,
254 RA_MASK_HT_3SS_RATES, RA_MASK_HT_4SS_RATES};
255 static const u64
256 rtw89_ra_mask_vht_rates[4] = {RA_MASK_VHT_1SS_RATES, RA_MASK_VHT_2SS_RATES,
257 RA_MASK_VHT_3SS_RATES, RA_MASK_VHT_4SS_RATES};
258 static const u64
259 rtw89_ra_mask_he_rates[4] = {RA_MASK_HE_1SS_RATES, RA_MASK_HE_2SS_RATES,
260 RA_MASK_HE_3SS_RATES, RA_MASK_HE_4SS_RATES};
261 static const u64
262 rtw89_ra_mask_eht_rates[4] = {RA_MASK_EHT_1SS_RATES, RA_MASK_EHT_2SS_RATES,
263 RA_MASK_EHT_3SS_RATES, RA_MASK_EHT_4SS_RATES};
264 static const u64
265 rtw89_ra_mask_eht_mcs0_11[4] = {RA_MASK_EHT_1SS_MCS0_11, RA_MASK_EHT_2SS_MCS0_11,
266 RA_MASK_EHT_3SS_MCS0_11, RA_MASK_EHT_4SS_MCS0_11};
267
rtw89_phy_ra_gi_ltf(struct rtw89_dev * rtwdev,struct rtw89_sta_link * rtwsta_link,struct ieee80211_link_sta * link_sta,const struct rtw89_chan * chan,bool * fix_giltf_en,u8 * fix_giltf)268 static void rtw89_phy_ra_gi_ltf(struct rtw89_dev *rtwdev,
269 struct rtw89_sta_link *rtwsta_link,
270 struct ieee80211_link_sta *link_sta,
271 const struct rtw89_chan *chan,
272 bool *fix_giltf_en, u8 *fix_giltf)
273 {
274 struct cfg80211_bitrate_mask *mask = &rtwsta_link->mask;
275 u8 band = chan->band_type;
276 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band);
277 u8 he_ltf = mask->control[nl_band].he_ltf;
278 u8 he_gi = mask->control[nl_band].he_gi;
279
280 *fix_giltf_en = true;
281
282 if (rtwdev->chip->chip_id == RTL8852C &&
283 chan->band_width == RTW89_CHANNEL_WIDTH_160 &&
284 rtw89_sta_link_has_su_mu_4xhe08(link_sta))
285 *fix_giltf = RTW89_GILTF_SGI_4XHE08;
286 else
287 *fix_giltf = RTW89_GILTF_2XHE08;
288
289 if (!(rtwsta_link->use_cfg_mask && link_sta->he_cap.has_he))
290 return;
291
292 if (he_ltf == 2 && he_gi == 2) {
293 *fix_giltf = RTW89_GILTF_LGI_4XHE32;
294 } else if (he_ltf == 2 && he_gi == 0) {
295 *fix_giltf = RTW89_GILTF_SGI_4XHE08;
296 } else if (he_ltf == 1 && he_gi == 1) {
297 *fix_giltf = RTW89_GILTF_2XHE16;
298 } else if (he_ltf == 1 && he_gi == 0) {
299 *fix_giltf = RTW89_GILTF_2XHE08;
300 } else if (he_ltf == 0 && he_gi == 1) {
301 *fix_giltf = RTW89_GILTF_1XHE16;
302 } else if (he_ltf == 0 && he_gi == 0) {
303 *fix_giltf = RTW89_GILTF_1XHE08;
304 }
305 }
306
rtw89_phy_ra_sta_update(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link,struct ieee80211_link_sta * link_sta,bool p2p,bool csi)307 static void rtw89_phy_ra_sta_update(struct rtw89_dev *rtwdev,
308 struct rtw89_vif_link *rtwvif_link,
309 struct rtw89_sta_link *rtwsta_link,
310 struct ieee80211_link_sta *link_sta,
311 bool p2p, bool csi)
312 {
313 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif_link->rate_pattern;
314 struct rtw89_ra_info *ra = &rtwsta_link->ra;
315 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev,
316 rtwvif_link->chanctx_idx);
317 const u64 *high_rate_masks = rtw89_ra_mask_ht_rates;
318 u8 rssi = ewma_rssi_read(&rtwsta_link->avg_rssi);
319 u64 ra_mask = 0;
320 u64 ra_mask_bak;
321 u8 mode = 0;
322 u8 csi_mode = RTW89_RA_RPT_MODE_LEGACY;
323 u8 bw_mode = 0;
324 u8 stbc_en = 0;
325 u8 ldpc_en = 0;
326 u8 fix_giltf = 0;
327 u8 i;
328 bool sgi = false;
329 bool fix_giltf_en = false;
330
331 memset(ra, 0, sizeof(*ra));
332 /* Set the ra mask from sta's capability */
333 if (link_sta->eht_cap.has_eht) {
334 mode |= RTW89_RA_MODE_EHT;
335 ra_mask |= get_eht_ra_mask(link_sta);
336
337 if (rtwdev->hal.no_mcs_12_13)
338 high_rate_masks = rtw89_ra_mask_eht_mcs0_11;
339 else
340 high_rate_masks = rtw89_ra_mask_eht_rates;
341
342 rtw89_phy_ra_gi_ltf(rtwdev, rtwsta_link, link_sta,
343 chan, &fix_giltf_en, &fix_giltf);
344 } else if (link_sta->he_cap.has_he) {
345 mode |= RTW89_RA_MODE_HE;
346 csi_mode = RTW89_RA_RPT_MODE_HE;
347 ra_mask |= get_he_ra_mask(link_sta);
348 high_rate_masks = rtw89_ra_mask_he_rates;
349 if (link_sta->he_cap.he_cap_elem.phy_cap_info[2] &
350 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ)
351 stbc_en = 1;
352 if (link_sta->he_cap.he_cap_elem.phy_cap_info[1] &
353 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD)
354 ldpc_en = 1;
355 rtw89_phy_ra_gi_ltf(rtwdev, rtwsta_link, link_sta,
356 chan, &fix_giltf_en, &fix_giltf);
357 } else if (link_sta->vht_cap.vht_supported) {
358 u16 mcs_map = le16_to_cpu(link_sta->vht_cap.vht_mcs.rx_mcs_map);
359
360 mode |= RTW89_RA_MODE_VHT;
361 csi_mode = RTW89_RA_RPT_MODE_VHT;
362 /* MCS9 (non-20MHz), MCS8, MCS7 */
363 if (link_sta->bandwidth == IEEE80211_STA_RX_BW_20)
364 ra_mask |= get_mcs_ra_mask(mcs_map, 8, 1);
365 else
366 ra_mask |= get_mcs_ra_mask(mcs_map, 9, 1);
367 high_rate_masks = rtw89_ra_mask_vht_rates;
368 if (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK)
369 stbc_en = 1;
370 if (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC)
371 ldpc_en = 1;
372 } else if (link_sta->ht_cap.ht_supported) {
373 mode |= RTW89_RA_MODE_HT;
374 csi_mode = RTW89_RA_RPT_MODE_HT;
375 ra_mask |= ((u64)link_sta->ht_cap.mcs.rx_mask[3] << 48) |
376 ((u64)link_sta->ht_cap.mcs.rx_mask[2] << 36) |
377 ((u64)link_sta->ht_cap.mcs.rx_mask[1] << 24) |
378 ((u64)link_sta->ht_cap.mcs.rx_mask[0] << 12);
379 high_rate_masks = rtw89_ra_mask_ht_rates;
380 if (link_sta->ht_cap.cap & IEEE80211_HT_CAP_RX_STBC)
381 stbc_en = 1;
382 if (link_sta->ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING)
383 ldpc_en = 1;
384 }
385
386 switch (chan->band_type) {
387 case RTW89_BAND_2G:
388 ra_mask |= link_sta->supp_rates[NL80211_BAND_2GHZ];
389 if (link_sta->supp_rates[NL80211_BAND_2GHZ] & 0xf)
390 mode |= RTW89_RA_MODE_CCK;
391 if (link_sta->supp_rates[NL80211_BAND_2GHZ] & 0xff0)
392 mode |= RTW89_RA_MODE_OFDM;
393 break;
394 case RTW89_BAND_5G:
395 ra_mask |= (u64)link_sta->supp_rates[NL80211_BAND_5GHZ] << 4;
396 mode |= RTW89_RA_MODE_OFDM;
397 break;
398 case RTW89_BAND_6G:
399 ra_mask |= (u64)link_sta->supp_rates[NL80211_BAND_6GHZ] << 4;
400 mode |= RTW89_RA_MODE_OFDM;
401 break;
402 default:
403 rtw89_err(rtwdev, "Unknown band type\n");
404 break;
405 }
406
407 ra_mask_bak = ra_mask;
408
409 if (mode >= RTW89_RA_MODE_HT) {
410 u64 mask = 0;
411 for (i = 0; i < rtwdev->hal.tx_nss; i++)
412 mask |= high_rate_masks[i];
413 if (mode & RTW89_RA_MODE_OFDM)
414 mask |= RA_MASK_SUBOFDM_RATES;
415 if (mode & RTW89_RA_MODE_CCK)
416 mask |= RA_MASK_SUBCCK_RATES;
417 ra_mask &= mask;
418 } else if (mode & RTW89_RA_MODE_OFDM) {
419 ra_mask &= (RA_MASK_OFDM_RATES | RA_MASK_SUBCCK_RATES);
420 }
421
422 if (mode != RTW89_RA_MODE_CCK)
423 ra_mask &= rtw89_phy_ra_mask_rssi(rtwdev, rssi, 0);
424
425 ra_mask = rtw89_phy_ra_mask_recover(ra_mask, ra_mask_bak);
426 ra_mask &= rtw89_phy_ra_mask_cfg(rtwdev, rtwsta_link, link_sta, chan);
427
428 switch (link_sta->bandwidth) {
429 case IEEE80211_STA_RX_BW_160:
430 bw_mode = RTW89_CHANNEL_WIDTH_160;
431 sgi = link_sta->vht_cap.vht_supported &&
432 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_160);
433 break;
434 case IEEE80211_STA_RX_BW_80:
435 bw_mode = RTW89_CHANNEL_WIDTH_80;
436 sgi = link_sta->vht_cap.vht_supported &&
437 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80);
438 break;
439 case IEEE80211_STA_RX_BW_40:
440 bw_mode = RTW89_CHANNEL_WIDTH_40;
441 sgi = link_sta->ht_cap.ht_supported &&
442 (link_sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40);
443 break;
444 default:
445 bw_mode = RTW89_CHANNEL_WIDTH_20;
446 sgi = link_sta->ht_cap.ht_supported &&
447 (link_sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20);
448 break;
449 }
450
451 if (link_sta->he_cap.he_cap_elem.phy_cap_info[3] &
452 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM)
453 ra->dcm_cap = 1;
454
455 if (rate_pattern->enable && !p2p) {
456 ra_mask = rtw89_phy_ra_mask_cfg(rtwdev, rtwsta_link, link_sta, chan);
457 ra_mask &= rate_pattern->ra_mask;
458 mode = rate_pattern->ra_mode;
459 }
460
461 ra->bw_cap = bw_mode;
462 ra->er_cap = rtwsta_link->er_cap;
463 ra->mode_ctrl = mode;
464 ra->macid = rtwsta_link->mac_id;
465 ra->stbc_cap = stbc_en;
466 ra->ldpc_cap = ldpc_en;
467 ra->ss_num = min(link_sta->rx_nss, rtwdev->hal.tx_nss) - 1;
468 ra->en_sgi = sgi;
469 ra->ra_mask = ra_mask;
470 ra->fix_giltf_en = fix_giltf_en;
471 ra->fix_giltf = fix_giltf;
472
473 if (!csi)
474 return;
475
476 ra->fixed_csi_rate_en = false;
477 ra->ra_csi_rate_en = true;
478 ra->cr_tbl_sel = false;
479 ra->band_num = rtwvif_link->phy_idx;
480 ra->csi_bw = bw_mode;
481 ra->csi_gi_ltf = RTW89_GILTF_LGI_4XHE32;
482 ra->csi_mcs_ss_idx = 5;
483 ra->csi_mode = csi_mode;
484 }
485
rtw89_phy_ra_update_sta_link(struct rtw89_dev * rtwdev,struct rtw89_sta_link * rtwsta_link,u32 changed)486 void rtw89_phy_ra_update_sta_link(struct rtw89_dev *rtwdev,
487 struct rtw89_sta_link *rtwsta_link,
488 u32 changed)
489 {
490 struct rtw89_vif_link *rtwvif_link = rtwsta_link->rtwvif_link;
491 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
492 struct rtw89_ra_info *ra = &rtwsta_link->ra;
493 struct ieee80211_link_sta *link_sta;
494
495 rcu_read_lock();
496
497 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false);
498 rtw89_phy_ra_sta_update(rtwdev, rtwvif_link, rtwsta_link,
499 link_sta, vif->p2p, false);
500
501 rcu_read_unlock();
502
503 if (changed & IEEE80211_RC_SUPP_RATES_CHANGED)
504 ra->upd_mask = 1;
505 if (changed & (IEEE80211_RC_BW_CHANGED | IEEE80211_RC_NSS_CHANGED))
506 ra->upd_bw_nss_mask = 1;
507
508 rtw89_debug(rtwdev, RTW89_DBG_RA,
509 "ra updat: macid = %d, bw = %d, nss = %d, gi = %d %d",
510 ra->macid,
511 ra->bw_cap,
512 ra->ss_num,
513 ra->en_sgi,
514 ra->giltf);
515
516 rtw89_fw_h2c_ra(rtwdev, ra, false);
517 }
518
rtw89_phy_ra_update_sta(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta,u32 changed)519 void rtw89_phy_ra_update_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta,
520 u32 changed)
521 {
522 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
523 struct rtw89_sta_link *rtwsta_link;
524 unsigned int link_id;
525
526 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id)
527 rtw89_phy_ra_update_sta_link(rtwdev, rtwsta_link, changed);
528 }
529
__check_rate_pattern(struct rtw89_phy_rate_pattern * next,u16 rate_base,u64 ra_mask,u8 ra_mode,u32 rate_ctrl,u32 ctrl_skip,bool force)530 static bool __check_rate_pattern(struct rtw89_phy_rate_pattern *next,
531 u16 rate_base, u64 ra_mask, u8 ra_mode,
532 u32 rate_ctrl, u32 ctrl_skip, bool force)
533 {
534 u8 n, c;
535
536 if (rate_ctrl == ctrl_skip)
537 return true;
538
539 n = hweight32(rate_ctrl);
540 if (n == 0)
541 return true;
542
543 if (force && n != 1)
544 return false;
545
546 if (next->enable)
547 return false;
548
549 c = __fls(rate_ctrl);
550 next->rate = rate_base + c;
551 next->ra_mode = ra_mode;
552 next->ra_mask = ra_mask;
553 next->enable = true;
554
555 return true;
556 }
557
558 #define RTW89_HW_RATE_BY_CHIP_GEN(rate) \
559 { \
560 [RTW89_CHIP_AX] = RTW89_HW_RATE_ ## rate, \
561 [RTW89_CHIP_BE] = RTW89_HW_RATE_V1_ ## rate, \
562 }
563
564 static
__rtw89_phy_rate_pattern_vif(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,const struct cfg80211_bitrate_mask * mask)565 void __rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev,
566 struct rtw89_vif_link *rtwvif_link,
567 const struct cfg80211_bitrate_mask *mask)
568 {
569 struct ieee80211_supported_band *sband;
570 struct rtw89_phy_rate_pattern next_pattern = {0};
571 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev,
572 rtwvif_link->chanctx_idx);
573 static const u16 hw_rate_he[][RTW89_CHIP_GEN_NUM] = {
574 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS1_MCS0),
575 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS2_MCS0),
576 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS3_MCS0),
577 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS4_MCS0),
578 };
579 static const u16 hw_rate_vht[][RTW89_CHIP_GEN_NUM] = {
580 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS1_MCS0),
581 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS2_MCS0),
582 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS3_MCS0),
583 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS4_MCS0),
584 };
585 static const u16 hw_rate_ht[][RTW89_CHIP_GEN_NUM] = {
586 RTW89_HW_RATE_BY_CHIP_GEN(MCS0),
587 RTW89_HW_RATE_BY_CHIP_GEN(MCS8),
588 RTW89_HW_RATE_BY_CHIP_GEN(MCS16),
589 RTW89_HW_RATE_BY_CHIP_GEN(MCS24),
590 };
591 u8 band = chan->band_type;
592 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band);
593 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen;
594 u8 tx_nss = rtwdev->hal.tx_nss;
595 u8 i;
596
597 for (i = 0; i < tx_nss; i++)
598 if (!__check_rate_pattern(&next_pattern, hw_rate_he[i][chip_gen],
599 RA_MASK_HE_RATES, RTW89_RA_MODE_HE,
600 mask->control[nl_band].he_mcs[i],
601 0, true))
602 goto out;
603
604 for (i = 0; i < tx_nss; i++)
605 if (!__check_rate_pattern(&next_pattern, hw_rate_vht[i][chip_gen],
606 RA_MASK_VHT_RATES, RTW89_RA_MODE_VHT,
607 mask->control[nl_band].vht_mcs[i],
608 0, true))
609 goto out;
610
611 for (i = 0; i < tx_nss; i++)
612 if (!__check_rate_pattern(&next_pattern, hw_rate_ht[i][chip_gen],
613 RA_MASK_HT_RATES, RTW89_RA_MODE_HT,
614 mask->control[nl_band].ht_mcs[i],
615 0, true))
616 goto out;
617
618 /* lagacy cannot be empty for nl80211_parse_tx_bitrate_mask, and
619 * require at least one basic rate for ieee80211_set_bitrate_mask,
620 * so the decision just depends on if all bitrates are set or not.
621 */
622 sband = rtwdev->hw->wiphy->bands[nl_band];
623 if (band == RTW89_BAND_2G) {
624 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_CCK1,
625 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES,
626 RTW89_RA_MODE_CCK | RTW89_RA_MODE_OFDM,
627 mask->control[nl_band].legacy,
628 BIT(sband->n_bitrates) - 1, false))
629 goto out;
630 } else {
631 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_OFDM6,
632 RA_MASK_OFDM_RATES, RTW89_RA_MODE_OFDM,
633 mask->control[nl_band].legacy,
634 BIT(sband->n_bitrates) - 1, false))
635 goto out;
636 }
637
638 if (!next_pattern.enable)
639 goto out;
640
641 rtwvif_link->rate_pattern = next_pattern;
642 rtw89_debug(rtwdev, RTW89_DBG_RA,
643 "configure pattern: rate 0x%x, mask 0x%llx, mode 0x%x\n",
644 next_pattern.rate,
645 next_pattern.ra_mask,
646 next_pattern.ra_mode);
647 return;
648
649 out:
650 rtwvif_link->rate_pattern.enable = false;
651 rtw89_debug(rtwdev, RTW89_DBG_RA, "unset rate pattern\n");
652 }
653
rtw89_phy_rate_pattern_vif(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,const struct cfg80211_bitrate_mask * mask)654 void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev,
655 struct ieee80211_vif *vif,
656 const struct cfg80211_bitrate_mask *mask)
657 {
658 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif);
659 struct rtw89_vif_link *rtwvif_link;
660 unsigned int link_id;
661
662 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id)
663 __rtw89_phy_rate_pattern_vif(rtwdev, rtwvif_link, mask);
664 }
665
rtw89_phy_ra_update_sta_iter(void * data,struct ieee80211_sta * sta)666 static void rtw89_phy_ra_update_sta_iter(void *data, struct ieee80211_sta *sta)
667 {
668 struct rtw89_dev *rtwdev = (struct rtw89_dev *)data;
669
670 rtw89_phy_ra_update_sta(rtwdev, sta, IEEE80211_RC_SUPP_RATES_CHANGED);
671 }
672
rtw89_phy_ra_update(struct rtw89_dev * rtwdev)673 void rtw89_phy_ra_update(struct rtw89_dev *rtwdev)
674 {
675 ieee80211_iterate_stations_atomic(rtwdev->hw,
676 rtw89_phy_ra_update_sta_iter,
677 rtwdev);
678 }
679
rtw89_phy_ra_assoc(struct rtw89_dev * rtwdev,struct rtw89_sta_link * rtwsta_link)680 void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link)
681 {
682 struct rtw89_vif_link *rtwvif_link = rtwsta_link->rtwvif_link;
683 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
684 struct rtw89_ra_info *ra = &rtwsta_link->ra;
685 u8 rssi = ewma_rssi_read(&rtwsta_link->avg_rssi) >> RSSI_FACTOR;
686 struct ieee80211_link_sta *link_sta;
687 bool csi;
688
689 rcu_read_lock();
690
691 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true);
692 csi = rtw89_sta_has_beamformer_cap(link_sta);
693
694 rtw89_phy_ra_sta_update(rtwdev, rtwvif_link, rtwsta_link,
695 link_sta, vif->p2p, csi);
696
697 rcu_read_unlock();
698
699 if (rssi > 40)
700 ra->init_rate_lv = 1;
701 else if (rssi > 20)
702 ra->init_rate_lv = 2;
703 else if (rssi > 1)
704 ra->init_rate_lv = 3;
705 else
706 ra->init_rate_lv = 0;
707 ra->upd_all = 1;
708 rtw89_debug(rtwdev, RTW89_DBG_RA,
709 "ra assoc: macid = %d, mode = %d, bw = %d, nss = %d, lv = %d",
710 ra->macid,
711 ra->mode_ctrl,
712 ra->bw_cap,
713 ra->ss_num,
714 ra->init_rate_lv);
715 rtw89_debug(rtwdev, RTW89_DBG_RA,
716 "ra assoc: dcm = %d, er = %d, ldpc = %d, stbc = %d, gi = %d %d",
717 ra->dcm_cap,
718 ra->er_cap,
719 ra->ldpc_cap,
720 ra->stbc_cap,
721 ra->en_sgi,
722 ra->giltf);
723
724 rtw89_fw_h2c_ra(rtwdev, ra, csi);
725 }
726
rtw89_phy_get_txsc(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_bandwidth dbw)727 u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev,
728 const struct rtw89_chan *chan,
729 enum rtw89_bandwidth dbw)
730 {
731 enum rtw89_bandwidth cbw = chan->band_width;
732 u8 pri_ch = chan->primary_channel;
733 u8 central_ch = chan->channel;
734 u8 txsc_idx = 0;
735 u8 tmp = 0;
736
737 if (cbw == dbw || cbw == RTW89_CHANNEL_WIDTH_20)
738 return txsc_idx;
739
740 switch (cbw) {
741 case RTW89_CHANNEL_WIDTH_40:
742 txsc_idx = pri_ch > central_ch ? 1 : 2;
743 break;
744 case RTW89_CHANNEL_WIDTH_80:
745 if (dbw == RTW89_CHANNEL_WIDTH_20) {
746 if (pri_ch > central_ch)
747 txsc_idx = (pri_ch - central_ch) >> 1;
748 else
749 txsc_idx = ((central_ch - pri_ch) >> 1) + 1;
750 } else {
751 txsc_idx = pri_ch > central_ch ? 9 : 10;
752 }
753 break;
754 case RTW89_CHANNEL_WIDTH_160:
755 if (pri_ch > central_ch)
756 tmp = (pri_ch - central_ch) >> 1;
757 else
758 tmp = ((central_ch - pri_ch) >> 1) + 1;
759
760 if (dbw == RTW89_CHANNEL_WIDTH_20) {
761 txsc_idx = tmp;
762 } else if (dbw == RTW89_CHANNEL_WIDTH_40) {
763 if (tmp == 1 || tmp == 3)
764 txsc_idx = 9;
765 else if (tmp == 5 || tmp == 7)
766 txsc_idx = 11;
767 else if (tmp == 2 || tmp == 4)
768 txsc_idx = 10;
769 else if (tmp == 6 || tmp == 8)
770 txsc_idx = 12;
771 else
772 return 0xff;
773 } else {
774 txsc_idx = pri_ch > central_ch ? 13 : 14;
775 }
776 break;
777 case RTW89_CHANNEL_WIDTH_80_80:
778 if (dbw == RTW89_CHANNEL_WIDTH_20) {
779 if (pri_ch > central_ch)
780 txsc_idx = (10 - (pri_ch - central_ch)) >> 1;
781 else
782 txsc_idx = ((central_ch - pri_ch) >> 1) + 5;
783 } else if (dbw == RTW89_CHANNEL_WIDTH_40) {
784 txsc_idx = pri_ch > central_ch ? 10 : 12;
785 } else {
786 txsc_idx = 14;
787 }
788 break;
789 default:
790 break;
791 }
792
793 return txsc_idx;
794 }
795 EXPORT_SYMBOL(rtw89_phy_get_txsc);
796
rtw89_phy_get_txsb(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_bandwidth dbw)797 u8 rtw89_phy_get_txsb(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan,
798 enum rtw89_bandwidth dbw)
799 {
800 enum rtw89_bandwidth cbw = chan->band_width;
801 u8 pri_ch = chan->primary_channel;
802 u8 central_ch = chan->channel;
803 u8 txsb_idx = 0;
804
805 if (cbw == dbw || cbw == RTW89_CHANNEL_WIDTH_20)
806 return txsb_idx;
807
808 switch (cbw) {
809 case RTW89_CHANNEL_WIDTH_40:
810 txsb_idx = pri_ch > central_ch ? 1 : 0;
811 break;
812 case RTW89_CHANNEL_WIDTH_80:
813 if (dbw == RTW89_CHANNEL_WIDTH_20)
814 txsb_idx = (pri_ch - central_ch + 6) / 4;
815 else
816 txsb_idx = pri_ch > central_ch ? 1 : 0;
817 break;
818 case RTW89_CHANNEL_WIDTH_160:
819 if (dbw == RTW89_CHANNEL_WIDTH_20)
820 txsb_idx = (pri_ch - central_ch + 14) / 4;
821 else if (dbw == RTW89_CHANNEL_WIDTH_40)
822 txsb_idx = (pri_ch - central_ch + 12) / 8;
823 else
824 txsb_idx = pri_ch > central_ch ? 1 : 0;
825 break;
826 case RTW89_CHANNEL_WIDTH_320:
827 if (dbw == RTW89_CHANNEL_WIDTH_20)
828 txsb_idx = (pri_ch - central_ch + 30) / 4;
829 else if (dbw == RTW89_CHANNEL_WIDTH_40)
830 txsb_idx = (pri_ch - central_ch + 28) / 8;
831 else if (dbw == RTW89_CHANNEL_WIDTH_80)
832 txsb_idx = (pri_ch - central_ch + 24) / 16;
833 else
834 txsb_idx = pri_ch > central_ch ? 1 : 0;
835 break;
836 default:
837 break;
838 }
839
840 return txsb_idx;
841 }
842 EXPORT_SYMBOL(rtw89_phy_get_txsb);
843
rtw89_phy_check_swsi_busy(struct rtw89_dev * rtwdev)844 static bool rtw89_phy_check_swsi_busy(struct rtw89_dev *rtwdev)
845 {
846 return !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_W_BUSY_V1) ||
847 !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_R_BUSY_V1);
848 }
849
rtw89_phy_read_rf(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask)850 u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
851 u32 addr, u32 mask)
852 {
853 const struct rtw89_chip_info *chip = rtwdev->chip;
854 const u32 *base_addr = chip->rf_base_addr;
855 u32 val, direct_addr;
856
857 if (rf_path >= rtwdev->chip->rf_path_num) {
858 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
859 return INV_RF_DATA;
860 }
861
862 addr &= 0xff;
863 direct_addr = base_addr[rf_path] + (addr << 2);
864 mask &= RFREG_MASK;
865
866 val = rtw89_phy_read32_mask(rtwdev, direct_addr, mask);
867
868 return val;
869 }
870 EXPORT_SYMBOL(rtw89_phy_read_rf);
871
rtw89_phy_read_rf_a(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask)872 static u32 rtw89_phy_read_rf_a(struct rtw89_dev *rtwdev,
873 enum rtw89_rf_path rf_path, u32 addr, u32 mask)
874 {
875 bool busy;
876 bool done;
877 u32 val;
878 int ret;
879
880 ret = read_poll_timeout_atomic(rtw89_phy_check_swsi_busy, busy, !busy,
881 1, 30, false, rtwdev);
882 if (ret) {
883 rtw89_err(rtwdev, "read rf busy swsi\n");
884 return INV_RF_DATA;
885 }
886
887 mask &= RFREG_MASK;
888
889 val = FIELD_PREP(B_SWSI_READ_ADDR_PATH_V1, rf_path) |
890 FIELD_PREP(B_SWSI_READ_ADDR_ADDR_V1, addr);
891 rtw89_phy_write32_mask(rtwdev, R_SWSI_READ_ADDR_V1, B_SWSI_READ_ADDR_V1, val);
892 udelay(2);
893
894 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, done, done, 1,
895 30, false, rtwdev, R_SWSI_V1,
896 B_SWSI_R_DATA_DONE_V1);
897 if (ret) {
898 rtw89_err(rtwdev, "read swsi busy\n");
899 return INV_RF_DATA;
900 }
901
902 return rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, mask);
903 }
904
rtw89_phy_read_rf_v1(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask)905 u32 rtw89_phy_read_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
906 u32 addr, u32 mask)
907 {
908 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr);
909
910 if (rf_path >= rtwdev->chip->rf_path_num) {
911 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
912 return INV_RF_DATA;
913 }
914
915 if (ad_sel)
916 return rtw89_phy_read_rf(rtwdev, rf_path, addr, mask);
917 else
918 return rtw89_phy_read_rf_a(rtwdev, rf_path, addr, mask);
919 }
920 EXPORT_SYMBOL(rtw89_phy_read_rf_v1);
921
rtw89_phy_read_full_rf_v2_a(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr)922 static u32 rtw89_phy_read_full_rf_v2_a(struct rtw89_dev *rtwdev,
923 enum rtw89_rf_path rf_path, u32 addr)
924 {
925 static const u16 r_addr_ofst[2] = {0x2C24, 0x2D24};
926 static const u16 addr_ofst[2] = {0x2ADC, 0x2BDC};
927 bool busy, done;
928 int ret;
929 u32 val;
930
931 rtw89_phy_write32_mask(rtwdev, addr_ofst[rf_path], B_HWSI_ADD_CTL_MASK, 0x1);
932 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, busy, !busy,
933 1, 3800, false,
934 rtwdev, r_addr_ofst[rf_path], B_HWSI_VAL_BUSY);
935 if (ret) {
936 rtw89_warn(rtwdev, "poll HWSI is busy\n");
937 return INV_RF_DATA;
938 }
939
940 rtw89_phy_write32_mask(rtwdev, addr_ofst[rf_path], B_HWSI_ADD_MASK, addr);
941 rtw89_phy_write32_mask(rtwdev, addr_ofst[rf_path], B_HWSI_ADD_RD, 0x1);
942 udelay(2);
943
944 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, done, done,
945 1, 3800, false,
946 rtwdev, r_addr_ofst[rf_path], B_HWSI_VAL_RDONE);
947 if (ret) {
948 rtw89_warn(rtwdev, "read HWSI is busy\n");
949 val = INV_RF_DATA;
950 goto out;
951 }
952
953 val = rtw89_phy_read32_mask(rtwdev, r_addr_ofst[rf_path], RFREG_MASK);
954 out:
955 rtw89_phy_write32_mask(rtwdev, addr_ofst[rf_path], B_HWSI_ADD_POLL_MASK, 0);
956
957 return val;
958 }
959
rtw89_phy_read_rf_v2_a(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask)960 static u32 rtw89_phy_read_rf_v2_a(struct rtw89_dev *rtwdev,
961 enum rtw89_rf_path rf_path, u32 addr, u32 mask)
962 {
963 u32 val;
964
965 val = rtw89_phy_read_full_rf_v2_a(rtwdev, rf_path, addr);
966
967 return (val & mask) >> __ffs(mask);
968 }
969
rtw89_phy_read_rf_v2(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask)970 u32 rtw89_phy_read_rf_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
971 u32 addr, u32 mask)
972 {
973 bool ad_sel = u32_get_bits(addr, RTW89_RF_ADDR_ADSEL_MASK);
974
975 if (rf_path >= rtwdev->chip->rf_path_num) {
976 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
977 return INV_RF_DATA;
978 }
979
980 if (ad_sel)
981 return rtw89_phy_read_rf(rtwdev, rf_path, addr, mask);
982 else
983 return rtw89_phy_read_rf_v2_a(rtwdev, rf_path, addr, mask);
984 }
985 EXPORT_SYMBOL(rtw89_phy_read_rf_v2);
986
rtw89_phy_write_rf(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask,u32 data)987 bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
988 u32 addr, u32 mask, u32 data)
989 {
990 const struct rtw89_chip_info *chip = rtwdev->chip;
991 const u32 *base_addr = chip->rf_base_addr;
992 u32 direct_addr;
993
994 if (rf_path >= rtwdev->chip->rf_path_num) {
995 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
996 return false;
997 }
998
999 addr &= 0xff;
1000 direct_addr = base_addr[rf_path] + (addr << 2);
1001 mask &= RFREG_MASK;
1002
1003 rtw89_phy_write32_mask(rtwdev, direct_addr, mask, data);
1004
1005 /* delay to ensure writing properly */
1006 udelay(1);
1007
1008 return true;
1009 }
1010 EXPORT_SYMBOL(rtw89_phy_write_rf);
1011
rtw89_phy_write_rf_a(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask,u32 data)1012 static bool rtw89_phy_write_rf_a(struct rtw89_dev *rtwdev,
1013 enum rtw89_rf_path rf_path, u32 addr, u32 mask,
1014 u32 data)
1015 {
1016 u8 bit_shift;
1017 u32 val;
1018 bool busy, b_msk_en = false;
1019 int ret;
1020
1021 ret = read_poll_timeout_atomic(rtw89_phy_check_swsi_busy, busy, !busy,
1022 1, 30, false, rtwdev);
1023 if (ret) {
1024 rtw89_err(rtwdev, "write rf busy swsi\n");
1025 return false;
1026 }
1027
1028 data &= RFREG_MASK;
1029 mask &= RFREG_MASK;
1030
1031 if (mask != RFREG_MASK) {
1032 b_msk_en = true;
1033 rtw89_phy_write32_mask(rtwdev, R_SWSI_BIT_MASK_V1, RFREG_MASK,
1034 mask);
1035 bit_shift = __ffs(mask);
1036 data = (data << bit_shift) & RFREG_MASK;
1037 }
1038
1039 val = FIELD_PREP(B_SWSI_DATA_BIT_MASK_EN_V1, b_msk_en) |
1040 FIELD_PREP(B_SWSI_DATA_PATH_V1, rf_path) |
1041 FIELD_PREP(B_SWSI_DATA_ADDR_V1, addr) |
1042 FIELD_PREP(B_SWSI_DATA_VAL_V1, data);
1043
1044 rtw89_phy_write32_mask(rtwdev, R_SWSI_DATA_V1, MASKDWORD, val);
1045
1046 return true;
1047 }
1048
rtw89_phy_write_rf_v1(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask,u32 data)1049 bool rtw89_phy_write_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
1050 u32 addr, u32 mask, u32 data)
1051 {
1052 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr);
1053
1054 if (rf_path >= rtwdev->chip->rf_path_num) {
1055 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
1056 return false;
1057 }
1058
1059 if (ad_sel)
1060 return rtw89_phy_write_rf(rtwdev, rf_path, addr, mask, data);
1061 else
1062 return rtw89_phy_write_rf_a(rtwdev, rf_path, addr, mask, data);
1063 }
1064 EXPORT_SYMBOL(rtw89_phy_write_rf_v1);
1065
1066 static
rtw89_phy_write_full_rf_v2_a(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 data)1067 bool rtw89_phy_write_full_rf_v2_a(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
1068 u32 addr, u32 data)
1069 {
1070 static const u32 addr_is_idle[2] = {0x2C24, 0x2D24};
1071 static const u32 addr_ofst[2] = {0x2AE0, 0x2BE0};
1072 bool busy;
1073 u32 val;
1074 int ret;
1075
1076 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, busy, !busy,
1077 1, 3800, false,
1078 rtwdev, addr_is_idle[rf_path], BIT(29));
1079 if (ret) {
1080 rtw89_warn(rtwdev, "[%s] HWSI is busy\n", __func__);
1081 return false;
1082 }
1083
1084 val = u32_encode_bits(addr, B_HWSI_DATA_ADDR) |
1085 u32_encode_bits(data, B_HWSI_DATA_VAL);
1086
1087 rtw89_phy_write32(rtwdev, addr_ofst[rf_path], val);
1088
1089 return true;
1090 }
1091
1092 static
rtw89_phy_write_rf_a_v2(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask,u32 data)1093 bool rtw89_phy_write_rf_a_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
1094 u32 addr, u32 mask, u32 data)
1095 {
1096 u32 val;
1097
1098 if (mask == RFREG_MASK) {
1099 val = data;
1100 } else {
1101 val = rtw89_phy_read_full_rf_v2_a(rtwdev, rf_path, addr);
1102 val &= ~mask;
1103 val |= (data << __ffs(mask)) & mask;
1104 }
1105
1106 return rtw89_phy_write_full_rf_v2_a(rtwdev, rf_path, addr, val);
1107 }
1108
rtw89_phy_write_rf_v2(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask,u32 data)1109 bool rtw89_phy_write_rf_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
1110 u32 addr, u32 mask, u32 data)
1111 {
1112 bool ad_sel = u32_get_bits(addr, RTW89_RF_ADDR_ADSEL_MASK);
1113
1114 if (rf_path >= rtwdev->chip->rf_path_num) {
1115 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
1116 return INV_RF_DATA;
1117 }
1118
1119 if (ad_sel)
1120 return rtw89_phy_write_rf(rtwdev, rf_path, addr, mask, data);
1121 else
1122 return rtw89_phy_write_rf_a_v2(rtwdev, rf_path, addr, mask, data);
1123 }
1124 EXPORT_SYMBOL(rtw89_phy_write_rf_v2);
1125
rtw89_chip_rf_v1(struct rtw89_dev * rtwdev)1126 static bool rtw89_chip_rf_v1(struct rtw89_dev *rtwdev)
1127 {
1128 return rtwdev->chip->ops->write_rf == rtw89_phy_write_rf_v1;
1129 }
1130
__rtw89_phy_bb_reset(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1131 static void __rtw89_phy_bb_reset(struct rtw89_dev *rtwdev,
1132 enum rtw89_phy_idx phy_idx)
1133 {
1134 const struct rtw89_chip_info *chip = rtwdev->chip;
1135
1136 chip->ops->bb_reset(rtwdev, phy_idx);
1137 }
1138
rtw89_phy_bb_reset(struct rtw89_dev * rtwdev)1139 static void rtw89_phy_bb_reset(struct rtw89_dev *rtwdev)
1140 {
1141 __rtw89_phy_bb_reset(rtwdev, RTW89_PHY_0);
1142 if (rtwdev->dbcc_en)
1143 __rtw89_phy_bb_reset(rtwdev, RTW89_PHY_1);
1144 }
1145
rtw89_phy_config_bb_reg(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,void * extra_data)1146 static void rtw89_phy_config_bb_reg(struct rtw89_dev *rtwdev,
1147 const struct rtw89_reg2_def *reg,
1148 enum rtw89_rf_path rf_path,
1149 void *extra_data)
1150 {
1151 u32 addr;
1152
1153 if (reg->addr == 0xfe) {
1154 mdelay(50);
1155 } else if (reg->addr == 0xfd) {
1156 mdelay(5);
1157 } else if (reg->addr == 0xfc) {
1158 mdelay(1);
1159 } else if (reg->addr == 0xfb) {
1160 udelay(50);
1161 } else if (reg->addr == 0xfa) {
1162 udelay(5);
1163 } else if (reg->addr == 0xf9) {
1164 udelay(1);
1165 } else if (reg->data == BYPASS_CR_DATA) {
1166 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "Bypass CR 0x%x\n", reg->addr);
1167 } else {
1168 addr = reg->addr;
1169
1170 if ((uintptr_t)extra_data == RTW89_PHY_1)
1171 addr += rtw89_phy0_phy1_offset(rtwdev, reg->addr);
1172
1173 rtw89_phy_write32(rtwdev, addr, reg->data);
1174 }
1175 }
1176
1177 union rtw89_phy_bb_gain_arg {
1178 u32 addr;
1179 struct {
1180 union {
1181 u8 type;
1182 struct {
1183 u8 rxsc_start:4;
1184 u8 bw:4;
1185 };
1186 };
1187 u8 path;
1188 u8 gain_band;
1189 u8 cfg_type;
1190 };
1191 } __packed;
1192
1193 static void
rtw89_phy_cfg_bb_gain_error(struct rtw89_dev * rtwdev,union rtw89_phy_bb_gain_arg arg,u32 data)1194 rtw89_phy_cfg_bb_gain_error(struct rtw89_dev *rtwdev,
1195 union rtw89_phy_bb_gain_arg arg, u32 data)
1196 {
1197 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax;
1198 u8 type = arg.type;
1199 u8 path = arg.path;
1200 u8 gband = arg.gain_band;
1201 int i;
1202
1203 switch (type) {
1204 case 0:
1205 for (i = 0; i < 4; i++, data >>= 8)
1206 gain->lna_gain[gband][path][i] = data & 0xff;
1207 break;
1208 case 1:
1209 for (i = 4; i < 7; i++, data >>= 8)
1210 gain->lna_gain[gband][path][i] = data & 0xff;
1211 break;
1212 case 2:
1213 for (i = 0; i < 2; i++, data >>= 8)
1214 gain->tia_gain[gband][path][i] = data & 0xff;
1215 break;
1216 default:
1217 rtw89_warn(rtwdev,
1218 "bb gain error {0x%x:0x%x} with unknown type: %d\n",
1219 arg.addr, data, type);
1220 break;
1221 }
1222 }
1223
1224 enum rtw89_phy_bb_rxsc_start_idx {
1225 RTW89_BB_RXSC_START_IDX_FULL = 0,
1226 RTW89_BB_RXSC_START_IDX_20 = 1,
1227 RTW89_BB_RXSC_START_IDX_20_1 = 5,
1228 RTW89_BB_RXSC_START_IDX_40 = 9,
1229 RTW89_BB_RXSC_START_IDX_80 = 13,
1230 };
1231
1232 static void
rtw89_phy_cfg_bb_rpl_ofst(struct rtw89_dev * rtwdev,union rtw89_phy_bb_gain_arg arg,u32 data)1233 rtw89_phy_cfg_bb_rpl_ofst(struct rtw89_dev *rtwdev,
1234 union rtw89_phy_bb_gain_arg arg, u32 data)
1235 {
1236 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax;
1237 u8 rxsc_start = arg.rxsc_start;
1238 u8 bw = arg.bw;
1239 u8 path = arg.path;
1240 u8 gband = arg.gain_band;
1241 u8 rxsc;
1242 s8 ofst;
1243 int i;
1244
1245 switch (bw) {
1246 case RTW89_CHANNEL_WIDTH_20:
1247 gain->rpl_ofst_20[gband][path] = (s8)data;
1248 break;
1249 case RTW89_CHANNEL_WIDTH_40:
1250 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) {
1251 gain->rpl_ofst_40[gband][path][0] = (s8)data;
1252 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) {
1253 for (i = 0; i < 2; i++, data >>= 8) {
1254 rxsc = RTW89_BB_RXSC_START_IDX_20 + i;
1255 ofst = (s8)(data & 0xff);
1256 gain->rpl_ofst_40[gband][path][rxsc] = ofst;
1257 }
1258 }
1259 break;
1260 case RTW89_CHANNEL_WIDTH_80:
1261 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) {
1262 gain->rpl_ofst_80[gband][path][0] = (s8)data;
1263 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) {
1264 for (i = 0; i < 4; i++, data >>= 8) {
1265 rxsc = RTW89_BB_RXSC_START_IDX_20 + i;
1266 ofst = (s8)(data & 0xff);
1267 gain->rpl_ofst_80[gband][path][rxsc] = ofst;
1268 }
1269 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_40) {
1270 for (i = 0; i < 2; i++, data >>= 8) {
1271 rxsc = RTW89_BB_RXSC_START_IDX_40 + i;
1272 ofst = (s8)(data & 0xff);
1273 gain->rpl_ofst_80[gband][path][rxsc] = ofst;
1274 }
1275 }
1276 break;
1277 case RTW89_CHANNEL_WIDTH_160:
1278 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) {
1279 gain->rpl_ofst_160[gband][path][0] = (s8)data;
1280 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) {
1281 for (i = 0; i < 4; i++, data >>= 8) {
1282 rxsc = RTW89_BB_RXSC_START_IDX_20 + i;
1283 ofst = (s8)(data & 0xff);
1284 gain->rpl_ofst_160[gband][path][rxsc] = ofst;
1285 }
1286 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20_1) {
1287 for (i = 0; i < 4; i++, data >>= 8) {
1288 rxsc = RTW89_BB_RXSC_START_IDX_20_1 + i;
1289 ofst = (s8)(data & 0xff);
1290 gain->rpl_ofst_160[gband][path][rxsc] = ofst;
1291 }
1292 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_40) {
1293 for (i = 0; i < 4; i++, data >>= 8) {
1294 rxsc = RTW89_BB_RXSC_START_IDX_40 + i;
1295 ofst = (s8)(data & 0xff);
1296 gain->rpl_ofst_160[gband][path][rxsc] = ofst;
1297 }
1298 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_80) {
1299 for (i = 0; i < 2; i++, data >>= 8) {
1300 rxsc = RTW89_BB_RXSC_START_IDX_80 + i;
1301 ofst = (s8)(data & 0xff);
1302 gain->rpl_ofst_160[gband][path][rxsc] = ofst;
1303 }
1304 }
1305 break;
1306 default:
1307 rtw89_warn(rtwdev,
1308 "bb rpl ofst {0x%x:0x%x} with unknown bw: %d\n",
1309 arg.addr, data, bw);
1310 break;
1311 }
1312 }
1313
1314 static void
rtw89_phy_cfg_bb_gain_bypass(struct rtw89_dev * rtwdev,union rtw89_phy_bb_gain_arg arg,u32 data)1315 rtw89_phy_cfg_bb_gain_bypass(struct rtw89_dev *rtwdev,
1316 union rtw89_phy_bb_gain_arg arg, u32 data)
1317 {
1318 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax;
1319 u8 type = arg.type;
1320 u8 path = arg.path;
1321 u8 gband = arg.gain_band;
1322 int i;
1323
1324 switch (type) {
1325 case 0:
1326 for (i = 0; i < 4; i++, data >>= 8)
1327 gain->lna_gain_bypass[gband][path][i] = data & 0xff;
1328 break;
1329 case 1:
1330 for (i = 4; i < 7; i++, data >>= 8)
1331 gain->lna_gain_bypass[gband][path][i] = data & 0xff;
1332 break;
1333 default:
1334 rtw89_warn(rtwdev,
1335 "bb gain bypass {0x%x:0x%x} with unknown type: %d\n",
1336 arg.addr, data, type);
1337 break;
1338 }
1339 }
1340
1341 static void
rtw89_phy_cfg_bb_gain_op1db(struct rtw89_dev * rtwdev,union rtw89_phy_bb_gain_arg arg,u32 data)1342 rtw89_phy_cfg_bb_gain_op1db(struct rtw89_dev *rtwdev,
1343 union rtw89_phy_bb_gain_arg arg, u32 data)
1344 {
1345 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax;
1346 u8 type = arg.type;
1347 u8 path = arg.path;
1348 u8 gband = arg.gain_band;
1349 int i;
1350
1351 switch (type) {
1352 case 0:
1353 for (i = 0; i < 4; i++, data >>= 8)
1354 gain->lna_op1db[gband][path][i] = data & 0xff;
1355 break;
1356 case 1:
1357 for (i = 4; i < 7; i++, data >>= 8)
1358 gain->lna_op1db[gband][path][i] = data & 0xff;
1359 break;
1360 case 2:
1361 for (i = 0; i < 4; i++, data >>= 8)
1362 gain->tia_lna_op1db[gband][path][i] = data & 0xff;
1363 break;
1364 case 3:
1365 for (i = 4; i < 8; i++, data >>= 8)
1366 gain->tia_lna_op1db[gband][path][i] = data & 0xff;
1367 break;
1368 default:
1369 rtw89_warn(rtwdev,
1370 "bb gain op1db {0x%x:0x%x} with unknown type: %d\n",
1371 arg.addr, data, type);
1372 break;
1373 }
1374 }
1375
rtw89_phy_config_bb_gain_ax(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,void * extra_data)1376 static void rtw89_phy_config_bb_gain_ax(struct rtw89_dev *rtwdev,
1377 const struct rtw89_reg2_def *reg,
1378 enum rtw89_rf_path rf_path,
1379 void *extra_data)
1380 {
1381 const struct rtw89_chip_info *chip = rtwdev->chip;
1382 union rtw89_phy_bb_gain_arg arg = { .addr = reg->addr };
1383 struct rtw89_efuse *efuse = &rtwdev->efuse;
1384
1385 if (arg.gain_band >= RTW89_BB_GAIN_BAND_NR)
1386 return;
1387
1388 if (arg.path >= chip->rf_path_num)
1389 return;
1390
1391 if (arg.addr >= 0xf9 && arg.addr <= 0xfe) {
1392 rtw89_warn(rtwdev, "bb gain table with flow ctrl\n");
1393 return;
1394 }
1395
1396 switch (arg.cfg_type) {
1397 case 0:
1398 rtw89_phy_cfg_bb_gain_error(rtwdev, arg, reg->data);
1399 break;
1400 case 1:
1401 rtw89_phy_cfg_bb_rpl_ofst(rtwdev, arg, reg->data);
1402 break;
1403 case 2:
1404 rtw89_phy_cfg_bb_gain_bypass(rtwdev, arg, reg->data);
1405 break;
1406 case 3:
1407 rtw89_phy_cfg_bb_gain_op1db(rtwdev, arg, reg->data);
1408 break;
1409 case 4:
1410 /* This cfg_type is only used by rfe_type >= 50 with eFEM */
1411 if (efuse->rfe_type < 50)
1412 break;
1413 fallthrough;
1414 default:
1415 rtw89_warn(rtwdev,
1416 "bb gain {0x%x:0x%x} with unknown cfg type: %d\n",
1417 arg.addr, reg->data, arg.cfg_type);
1418 break;
1419 }
1420 }
1421
1422 static void
rtw89_phy_cofig_rf_reg_store(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,struct rtw89_fw_h2c_rf_reg_info * info)1423 rtw89_phy_cofig_rf_reg_store(struct rtw89_dev *rtwdev,
1424 const struct rtw89_reg2_def *reg,
1425 enum rtw89_rf_path rf_path,
1426 struct rtw89_fw_h2c_rf_reg_info *info)
1427 {
1428 u16 idx = info->curr_idx % RTW89_H2C_RF_PAGE_SIZE;
1429 u8 page = info->curr_idx / RTW89_H2C_RF_PAGE_SIZE;
1430
1431 if (page >= RTW89_H2C_RF_PAGE_NUM) {
1432 rtw89_warn(rtwdev, "RF parameters exceed size. path=%d, idx=%d",
1433 rf_path, info->curr_idx);
1434 return;
1435 }
1436
1437 info->rtw89_phy_config_rf_h2c[page][idx] =
1438 cpu_to_le32((reg->addr << 20) | reg->data);
1439 info->curr_idx++;
1440 }
1441
rtw89_phy_config_rf_reg_fw(struct rtw89_dev * rtwdev,struct rtw89_fw_h2c_rf_reg_info * info)1442 static int rtw89_phy_config_rf_reg_fw(struct rtw89_dev *rtwdev,
1443 struct rtw89_fw_h2c_rf_reg_info *info)
1444 {
1445 u16 remain = info->curr_idx;
1446 u16 len = 0;
1447 u8 i;
1448 int ret = 0;
1449
1450 if (remain > RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE) {
1451 rtw89_warn(rtwdev,
1452 "rf reg h2c total len %d larger than %d\n",
1453 remain, RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE);
1454 ret = -EINVAL;
1455 goto out;
1456 }
1457
1458 for (i = 0; i < RTW89_H2C_RF_PAGE_NUM && remain; i++, remain -= len) {
1459 len = remain > RTW89_H2C_RF_PAGE_SIZE ? RTW89_H2C_RF_PAGE_SIZE : remain;
1460 ret = rtw89_fw_h2c_rf_reg(rtwdev, info, len * 4, i);
1461 if (ret)
1462 goto out;
1463 }
1464 out:
1465 info->curr_idx = 0;
1466
1467 return ret;
1468 }
1469
rtw89_phy_config_rf_reg_noio(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,void * extra_data)1470 static void rtw89_phy_config_rf_reg_noio(struct rtw89_dev *rtwdev,
1471 const struct rtw89_reg2_def *reg,
1472 enum rtw89_rf_path rf_path,
1473 void *extra_data)
1474 {
1475 u32 addr = reg->addr;
1476
1477 if (addr == 0xfe || addr == 0xfd || addr == 0xfc || addr == 0xfb ||
1478 addr == 0xfa || addr == 0xf9)
1479 return;
1480
1481 if (rtw89_chip_rf_v1(rtwdev) && addr < 0x100)
1482 return;
1483
1484 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path,
1485 (struct rtw89_fw_h2c_rf_reg_info *)extra_data);
1486 }
1487
rtw89_phy_config_rf_reg(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,void * extra_data)1488 static void rtw89_phy_config_rf_reg(struct rtw89_dev *rtwdev,
1489 const struct rtw89_reg2_def *reg,
1490 enum rtw89_rf_path rf_path,
1491 void *extra_data)
1492 {
1493 if (reg->addr == 0xfe) {
1494 mdelay(50);
1495 } else if (reg->addr == 0xfd) {
1496 mdelay(5);
1497 } else if (reg->addr == 0xfc) {
1498 mdelay(1);
1499 } else if (reg->addr == 0xfb) {
1500 udelay(50);
1501 } else if (reg->addr == 0xfa) {
1502 udelay(5);
1503 } else if (reg->addr == 0xf9) {
1504 udelay(1);
1505 } else {
1506 rtw89_write_rf(rtwdev, rf_path, reg->addr, 0xfffff, reg->data);
1507 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path,
1508 (struct rtw89_fw_h2c_rf_reg_info *)extra_data);
1509 }
1510 }
1511
rtw89_phy_config_rf_reg_v1(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,void * extra_data)1512 void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev,
1513 const struct rtw89_reg2_def *reg,
1514 enum rtw89_rf_path rf_path,
1515 void *extra_data)
1516 {
1517 rtw89_write_rf(rtwdev, rf_path, reg->addr, RFREG_MASK, reg->data);
1518
1519 if (reg->addr < 0x100)
1520 return;
1521
1522 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path,
1523 (struct rtw89_fw_h2c_rf_reg_info *)extra_data);
1524 }
1525 EXPORT_SYMBOL(rtw89_phy_config_rf_reg_v1);
1526
rtw89_phy_sel_headline(struct rtw89_dev * rtwdev,const struct rtw89_phy_table * table,u32 * headline_size,u32 * headline_idx,u8 rfe,u8 cv)1527 static int rtw89_phy_sel_headline(struct rtw89_dev *rtwdev,
1528 const struct rtw89_phy_table *table,
1529 u32 *headline_size, u32 *headline_idx,
1530 u8 rfe, u8 cv)
1531 {
1532 const struct rtw89_reg2_def *reg;
1533 u32 headline;
1534 u32 compare, target;
1535 u8 rfe_para, cv_para;
1536 u8 cv_max = 0;
1537 bool case_matched = false;
1538 u32 i;
1539
1540 for (i = 0; i < table->n_regs; i++) {
1541 reg = &table->regs[i];
1542 headline = get_phy_headline(reg->addr);
1543 if (headline != PHY_HEADLINE_VALID)
1544 break;
1545 }
1546 *headline_size = i;
1547 if (*headline_size == 0)
1548 return 0;
1549
1550 /* case 1: RFE match, CV match */
1551 compare = get_phy_compare(rfe, cv);
1552 for (i = 0; i < *headline_size; i++) {
1553 reg = &table->regs[i];
1554 target = get_phy_target(reg->addr);
1555 if (target == compare) {
1556 *headline_idx = i;
1557 return 0;
1558 }
1559 }
1560
1561 /* case 2: RFE match, CV don't care */
1562 compare = get_phy_compare(rfe, PHY_COND_DONT_CARE);
1563 for (i = 0; i < *headline_size; i++) {
1564 reg = &table->regs[i];
1565 target = get_phy_target(reg->addr);
1566 if (target == compare) {
1567 *headline_idx = i;
1568 return 0;
1569 }
1570 }
1571
1572 /* case 3: RFE match, CV max in table */
1573 for (i = 0; i < *headline_size; i++) {
1574 reg = &table->regs[i];
1575 rfe_para = get_phy_cond_rfe(reg->addr);
1576 cv_para = get_phy_cond_cv(reg->addr);
1577 if (rfe_para == rfe) {
1578 if (cv_para >= cv_max) {
1579 cv_max = cv_para;
1580 *headline_idx = i;
1581 case_matched = true;
1582 }
1583 }
1584 }
1585
1586 if (case_matched)
1587 return 0;
1588
1589 /* case 4: RFE don't care, CV max in table */
1590 for (i = 0; i < *headline_size; i++) {
1591 reg = &table->regs[i];
1592 rfe_para = get_phy_cond_rfe(reg->addr);
1593 cv_para = get_phy_cond_cv(reg->addr);
1594 if (rfe_para == PHY_COND_DONT_CARE) {
1595 if (cv_para >= cv_max) {
1596 cv_max = cv_para;
1597 *headline_idx = i;
1598 case_matched = true;
1599 }
1600 }
1601 }
1602
1603 if (case_matched)
1604 return 0;
1605
1606 return -EINVAL;
1607 }
1608
rtw89_phy_init_reg(struct rtw89_dev * rtwdev,const struct rtw89_phy_table * table,void (* config)(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,void * data),void * extra_data)1609 static void rtw89_phy_init_reg(struct rtw89_dev *rtwdev,
1610 const struct rtw89_phy_table *table,
1611 void (*config)(struct rtw89_dev *rtwdev,
1612 const struct rtw89_reg2_def *reg,
1613 enum rtw89_rf_path rf_path,
1614 void *data),
1615 void *extra_data)
1616 {
1617 const struct rtw89_reg2_def *reg;
1618 enum rtw89_rf_path rf_path = table->rf_path;
1619 u8 rfe = rtwdev->efuse.rfe_type;
1620 u8 cv = rtwdev->hal.cv;
1621 u32 i;
1622 u32 headline_size = 0, headline_idx = 0;
1623 u32 target = 0, cfg_target;
1624 u8 cond;
1625 bool is_matched = true;
1626 bool target_found = false;
1627 int ret;
1628
1629 ret = rtw89_phy_sel_headline(rtwdev, table, &headline_size,
1630 &headline_idx, rfe, cv);
1631 if (ret) {
1632 rtw89_err(rtwdev, "invalid PHY package: %d/%d\n", rfe, cv);
1633 return;
1634 }
1635
1636 cfg_target = get_phy_target(table->regs[headline_idx].addr);
1637 for (i = headline_size; i < table->n_regs; i++) {
1638 reg = &table->regs[i];
1639 cond = get_phy_cond(reg->addr);
1640 switch (cond) {
1641 case PHY_COND_BRANCH_IF:
1642 case PHY_COND_BRANCH_ELIF:
1643 target = get_phy_target(reg->addr);
1644 break;
1645 case PHY_COND_BRANCH_ELSE:
1646 is_matched = false;
1647 if (!target_found) {
1648 rtw89_warn(rtwdev, "failed to load CR %x/%x\n",
1649 reg->addr, reg->data);
1650 return;
1651 }
1652 break;
1653 case PHY_COND_BRANCH_END:
1654 is_matched = true;
1655 target_found = false;
1656 break;
1657 case PHY_COND_CHECK:
1658 if (target_found) {
1659 is_matched = false;
1660 break;
1661 }
1662
1663 if (target == cfg_target) {
1664 is_matched = true;
1665 target_found = true;
1666 } else {
1667 is_matched = false;
1668 target_found = false;
1669 }
1670 break;
1671 default:
1672 if (is_matched)
1673 config(rtwdev, reg, rf_path, extra_data);
1674 break;
1675 }
1676 }
1677 }
1678
rtw89_phy_init_bb_reg(struct rtw89_dev * rtwdev)1679 void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev)
1680 {
1681 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info;
1682 const struct rtw89_chip_info *chip = rtwdev->chip;
1683 const struct rtw89_phy_table *bb_table;
1684 const struct rtw89_phy_table *bb_gain_table;
1685
1686 bb_table = elm_info->bb_tbl ? elm_info->bb_tbl : chip->bb_table;
1687 rtw89_phy_init_reg(rtwdev, bb_table, rtw89_phy_config_bb_reg, NULL);
1688 if (rtwdev->dbcc_en)
1689 rtw89_phy_init_reg(rtwdev, bb_table, rtw89_phy_config_bb_reg,
1690 (void *)RTW89_PHY_1);
1691
1692 rtw89_chip_init_txpwr_unit(rtwdev);
1693
1694 bb_gain_table = elm_info->bb_gain ? elm_info->bb_gain : chip->bb_gain_table;
1695 if (bb_gain_table)
1696 rtw89_phy_init_reg(rtwdev, bb_gain_table,
1697 chip->phy_def->config_bb_gain, NULL);
1698
1699 rtw89_phy_bb_reset(rtwdev);
1700 }
1701
rtw89_phy_nctl_poll(struct rtw89_dev * rtwdev)1702 static u32 rtw89_phy_nctl_poll(struct rtw89_dev *rtwdev)
1703 {
1704 rtw89_phy_write32(rtwdev, 0x8080, 0x4);
1705 udelay(1);
1706 return rtw89_phy_read32(rtwdev, 0x8080);
1707 }
1708
rtw89_phy_init_rf_reg(struct rtw89_dev * rtwdev,bool noio)1709 void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev, bool noio)
1710 {
1711 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg,
1712 enum rtw89_rf_path rf_path, void *data);
1713 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info;
1714 const struct rtw89_chip_info *chip = rtwdev->chip;
1715 const struct rtw89_phy_table *rf_table;
1716 struct rtw89_fw_h2c_rf_reg_info *rf_reg_info;
1717 u8 path;
1718
1719 rf_reg_info = kzalloc(sizeof(*rf_reg_info), GFP_KERNEL);
1720 if (!rf_reg_info)
1721 return;
1722
1723 for (path = RF_PATH_A; path < chip->rf_path_num; path++) {
1724 rf_table = elm_info->rf_radio[path] ?
1725 elm_info->rf_radio[path] : chip->rf_table[path];
1726 rf_reg_info->rf_path = rf_table->rf_path;
1727 if (noio)
1728 config = rtw89_phy_config_rf_reg_noio;
1729 else
1730 config = rf_table->config ? rf_table->config :
1731 rtw89_phy_config_rf_reg;
1732 rtw89_phy_init_reg(rtwdev, rf_table, config, (void *)rf_reg_info);
1733 if (rtw89_phy_config_rf_reg_fw(rtwdev, rf_reg_info))
1734 rtw89_warn(rtwdev, "rf path %d reg h2c config failed\n",
1735 rf_reg_info->rf_path);
1736 }
1737 kfree(rf_reg_info);
1738 }
1739
rtw89_phy_preinit_rf_nctl_ax(struct rtw89_dev * rtwdev)1740 static void rtw89_phy_preinit_rf_nctl_ax(struct rtw89_dev *rtwdev)
1741 {
1742 const struct rtw89_chip_info *chip = rtwdev->chip;
1743 u32 val;
1744 int ret;
1745
1746 /* IQK/DPK clock & reset */
1747 rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x3);
1748 rtw89_phy_write32_set(rtwdev, R_GNT_BT_WGT_EN, 0x1);
1749 rtw89_phy_write32_set(rtwdev, R_P0_PATH_RST, 0x8000000);
1750 if (chip->chip_id != RTL8851B)
1751 rtw89_phy_write32_set(rtwdev, R_P1_PATH_RST, 0x8000000);
1752 if (chip->chip_id == RTL8852B || chip->chip_id == RTL8852BT)
1753 rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x2);
1754
1755 /* check 0x8080 */
1756 rtw89_phy_write32(rtwdev, R_NCTL_CFG, 0x8);
1757
1758 ret = read_poll_timeout(rtw89_phy_nctl_poll, val, val == 0x4, 10,
1759 1000, false, rtwdev);
1760 if (ret)
1761 rtw89_err(rtwdev, "failed to poll nctl block\n");
1762 }
1763
rtw89_phy_init_rf_nctl(struct rtw89_dev * rtwdev)1764 static void rtw89_phy_init_rf_nctl(struct rtw89_dev *rtwdev)
1765 {
1766 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info;
1767 const struct rtw89_chip_info *chip = rtwdev->chip;
1768 const struct rtw89_phy_table *nctl_table;
1769
1770 rtw89_phy_preinit_rf_nctl(rtwdev);
1771
1772 nctl_table = elm_info->rf_nctl ? elm_info->rf_nctl : chip->nctl_table;
1773 rtw89_phy_init_reg(rtwdev, nctl_table, rtw89_phy_config_bb_reg, NULL);
1774
1775 if (chip->nctl_post_table)
1776 rtw89_rfk_parser(rtwdev, chip->nctl_post_table);
1777 }
1778
rtw89_phy0_phy1_offset_ax(struct rtw89_dev * rtwdev,u32 addr)1779 static u32 rtw89_phy0_phy1_offset_ax(struct rtw89_dev *rtwdev, u32 addr)
1780 {
1781 u32 phy_page = addr >> 8;
1782 u32 ofst = 0;
1783
1784 switch (phy_page) {
1785 case 0x6:
1786 case 0x7:
1787 case 0x8:
1788 case 0x9:
1789 case 0xa:
1790 case 0xb:
1791 case 0xc:
1792 case 0xd:
1793 case 0x19:
1794 case 0x1a:
1795 case 0x1b:
1796 ofst = 0x2000;
1797 break;
1798 default:
1799 /* warning case */
1800 ofst = 0;
1801 break;
1802 }
1803
1804 if (phy_page >= 0x40 && phy_page <= 0x4f)
1805 ofst = 0x2000;
1806
1807 return ofst;
1808 }
1809
rtw89_phy_write32_idx(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u32 data,enum rtw89_phy_idx phy_idx)1810 void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
1811 u32 data, enum rtw89_phy_idx phy_idx)
1812 {
1813 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1)
1814 addr += rtw89_phy0_phy1_offset(rtwdev, addr);
1815 rtw89_phy_write32_mask(rtwdev, addr, mask, data);
1816 }
1817 EXPORT_SYMBOL(rtw89_phy_write32_idx);
1818
rtw89_phy_write32_idx_set(struct rtw89_dev * rtwdev,u32 addr,u32 bits,enum rtw89_phy_idx phy_idx)1819 void rtw89_phy_write32_idx_set(struct rtw89_dev *rtwdev, u32 addr, u32 bits,
1820 enum rtw89_phy_idx phy_idx)
1821 {
1822 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1)
1823 addr += rtw89_phy0_phy1_offset(rtwdev, addr);
1824 rtw89_phy_write32_set(rtwdev, addr, bits);
1825 }
1826 EXPORT_SYMBOL(rtw89_phy_write32_idx_set);
1827
rtw89_phy_write32_idx_clr(struct rtw89_dev * rtwdev,u32 addr,u32 bits,enum rtw89_phy_idx phy_idx)1828 void rtw89_phy_write32_idx_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bits,
1829 enum rtw89_phy_idx phy_idx)
1830 {
1831 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1)
1832 addr += rtw89_phy0_phy1_offset(rtwdev, addr);
1833 rtw89_phy_write32_clr(rtwdev, addr, bits);
1834 }
1835 EXPORT_SYMBOL(rtw89_phy_write32_idx_clr);
1836
rtw89_phy_read32_idx(struct rtw89_dev * rtwdev,u32 addr,u32 mask,enum rtw89_phy_idx phy_idx)1837 u32 rtw89_phy_read32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
1838 enum rtw89_phy_idx phy_idx)
1839 {
1840 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1)
1841 addr += rtw89_phy0_phy1_offset(rtwdev, addr);
1842 return rtw89_phy_read32_mask(rtwdev, addr, mask);
1843 }
1844 EXPORT_SYMBOL(rtw89_phy_read32_idx);
1845
rtw89_phy_set_phy_regs(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u32 val)1846 void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
1847 u32 val)
1848 {
1849 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_0);
1850
1851 if (!rtwdev->dbcc_en)
1852 return;
1853
1854 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_1);
1855 }
1856 EXPORT_SYMBOL(rtw89_phy_set_phy_regs);
1857
rtw89_phy_write_reg3_tbl(struct rtw89_dev * rtwdev,const struct rtw89_phy_reg3_tbl * tbl)1858 void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev,
1859 const struct rtw89_phy_reg3_tbl *tbl)
1860 {
1861 const struct rtw89_reg3_def *reg3;
1862 int i;
1863
1864 for (i = 0; i < tbl->size; i++) {
1865 reg3 = &tbl->reg3[i];
1866 rtw89_phy_write32_mask(rtwdev, reg3->addr, reg3->mask, reg3->data);
1867 }
1868 }
1869 EXPORT_SYMBOL(rtw89_phy_write_reg3_tbl);
1870
rtw89_phy_ant_gain_domain_to_regd(struct rtw89_dev * rtwdev,u8 ant_gain_regd)1871 static u8 rtw89_phy_ant_gain_domain_to_regd(struct rtw89_dev *rtwdev, u8 ant_gain_regd)
1872 {
1873 switch (ant_gain_regd) {
1874 case RTW89_ANT_GAIN_ETSI:
1875 return RTW89_ETSI;
1876 default:
1877 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1878 "unknown antenna gain domain: %d\n",
1879 ant_gain_regd);
1880 return RTW89_REGD_NUM;
1881 }
1882 }
1883
1884 /* antenna gain in unit of 0.25 dbm */
1885 #define RTW89_ANT_GAIN_2GHZ_MIN -8
1886 #define RTW89_ANT_GAIN_2GHZ_MAX 14
1887 #define RTW89_ANT_GAIN_5GHZ_MIN -8
1888 #define RTW89_ANT_GAIN_5GHZ_MAX 20
1889 #define RTW89_ANT_GAIN_6GHZ_MIN -8
1890 #define RTW89_ANT_GAIN_6GHZ_MAX 20
1891
1892 #define RTW89_ANT_GAIN_REF_2GHZ 14
1893 #define RTW89_ANT_GAIN_REF_5GHZ 20
1894 #define RTW89_ANT_GAIN_REF_6GHZ 20
1895
rtw89_phy_ant_gain_init(struct rtw89_dev * rtwdev)1896 void rtw89_phy_ant_gain_init(struct rtw89_dev *rtwdev)
1897 {
1898 struct rtw89_ant_gain_info *ant_gain = &rtwdev->ant_gain;
1899 const struct rtw89_chip_info *chip = rtwdev->chip;
1900 struct rtw89_acpi_rtag_result res = {};
1901 u32 domain;
1902 int ret;
1903 u8 i, j;
1904 u8 regd;
1905 u8 val;
1906
1907 if (!chip->support_ant_gain)
1908 return;
1909
1910 ret = rtw89_acpi_evaluate_rtag(rtwdev, &res);
1911 if (ret) {
1912 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1913 "acpi: cannot eval rtag: %d\n", ret);
1914 return;
1915 }
1916
1917 if (res.revision != 0) {
1918 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1919 "unknown rtag revision: %d\n", res.revision);
1920 return;
1921 }
1922
1923 domain = get_unaligned_le32(&res.domain);
1924
1925 for (i = 0; i < RTW89_ANT_GAIN_DOMAIN_NUM; i++) {
1926 if (!(domain & BIT(i)))
1927 continue;
1928
1929 regd = rtw89_phy_ant_gain_domain_to_regd(rtwdev, i);
1930 if (regd >= RTW89_REGD_NUM)
1931 continue;
1932 ant_gain->regd_enabled |= BIT(regd);
1933 }
1934
1935 for (i = 0; i < RTW89_ANT_GAIN_CHAIN_NUM; i++) {
1936 for (j = 0; j < RTW89_ANT_GAIN_SUBBAND_NR; j++) {
1937 val = res.ant_gain_table[i][j];
1938 switch (j) {
1939 default:
1940 case RTW89_ANT_GAIN_2GHZ_SUBBAND:
1941 val = RTW89_ANT_GAIN_REF_2GHZ -
1942 clamp_t(s8, val,
1943 RTW89_ANT_GAIN_2GHZ_MIN,
1944 RTW89_ANT_GAIN_2GHZ_MAX);
1945 break;
1946 case RTW89_ANT_GAIN_5GHZ_SUBBAND_1:
1947 case RTW89_ANT_GAIN_5GHZ_SUBBAND_2:
1948 case RTW89_ANT_GAIN_5GHZ_SUBBAND_2E:
1949 case RTW89_ANT_GAIN_5GHZ_SUBBAND_3_4:
1950 val = RTW89_ANT_GAIN_REF_5GHZ -
1951 clamp_t(s8, val,
1952 RTW89_ANT_GAIN_5GHZ_MIN,
1953 RTW89_ANT_GAIN_5GHZ_MAX);
1954 break;
1955 case RTW89_ANT_GAIN_6GHZ_SUBBAND_5_L:
1956 case RTW89_ANT_GAIN_6GHZ_SUBBAND_5_H:
1957 case RTW89_ANT_GAIN_6GHZ_SUBBAND_6:
1958 case RTW89_ANT_GAIN_6GHZ_SUBBAND_7_L:
1959 case RTW89_ANT_GAIN_6GHZ_SUBBAND_7_H:
1960 case RTW89_ANT_GAIN_6GHZ_SUBBAND_8:
1961 val = RTW89_ANT_GAIN_REF_6GHZ -
1962 clamp_t(s8, val,
1963 RTW89_ANT_GAIN_6GHZ_MIN,
1964 RTW89_ANT_GAIN_6GHZ_MAX);
1965 }
1966 ant_gain->offset[i][j] = val;
1967 }
1968 }
1969 }
1970
1971 static
rtw89_phy_ant_gain_get_subband(struct rtw89_dev * rtwdev,u32 center_freq)1972 enum rtw89_ant_gain_subband rtw89_phy_ant_gain_get_subband(struct rtw89_dev *rtwdev,
1973 u32 center_freq)
1974 {
1975 switch (center_freq) {
1976 default:
1977 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1978 "center freq: %u to antenna gain subband is unhandled\n",
1979 center_freq);
1980 fallthrough;
1981 case 2412 ... 2484:
1982 return RTW89_ANT_GAIN_2GHZ_SUBBAND;
1983 case 5180 ... 5240:
1984 return RTW89_ANT_GAIN_5GHZ_SUBBAND_1;
1985 case 5250 ... 5320:
1986 return RTW89_ANT_GAIN_5GHZ_SUBBAND_2;
1987 case 5500 ... 5720:
1988 return RTW89_ANT_GAIN_5GHZ_SUBBAND_2E;
1989 case 5745 ... 5885:
1990 return RTW89_ANT_GAIN_5GHZ_SUBBAND_3_4;
1991 case 5955 ... 6155:
1992 return RTW89_ANT_GAIN_6GHZ_SUBBAND_5_L;
1993 case 6175 ... 6415:
1994 return RTW89_ANT_GAIN_6GHZ_SUBBAND_5_H;
1995 case 6435 ... 6515:
1996 return RTW89_ANT_GAIN_6GHZ_SUBBAND_6;
1997 case 6535 ... 6695:
1998 return RTW89_ANT_GAIN_6GHZ_SUBBAND_7_L;
1999 case 6715 ... 6855:
2000 return RTW89_ANT_GAIN_6GHZ_SUBBAND_7_H;
2001
2002 /* freq 6875 (ch 185, 20MHz) spans RTW89_ANT_GAIN_6GHZ_SUBBAND_7_H
2003 * and RTW89_ANT_GAIN_6GHZ_SUBBAND_8, so directly describe it with
2004 * struct rtw89_6ghz_span.
2005 */
2006
2007 case 6895 ... 7115:
2008 return RTW89_ANT_GAIN_6GHZ_SUBBAND_8;
2009 }
2010 }
2011
rtw89_phy_ant_gain_query(struct rtw89_dev * rtwdev,enum rtw89_rf_path path,u32 center_freq)2012 static s8 rtw89_phy_ant_gain_query(struct rtw89_dev *rtwdev,
2013 enum rtw89_rf_path path, u32 center_freq)
2014 {
2015 struct rtw89_ant_gain_info *ant_gain = &rtwdev->ant_gain;
2016 enum rtw89_ant_gain_subband subband_l, subband_h;
2017 const struct rtw89_6ghz_span *span;
2018
2019 span = rtw89_get_6ghz_span(rtwdev, center_freq);
2020
2021 if (span && RTW89_ANT_GAIN_SPAN_VALID(span)) {
2022 subband_l = span->ant_gain_subband_low;
2023 subband_h = span->ant_gain_subband_high;
2024 } else {
2025 subband_l = rtw89_phy_ant_gain_get_subband(rtwdev, center_freq);
2026 subband_h = subband_l;
2027 }
2028
2029 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
2030 "center_freq %u: antenna gain subband {%u, %u}\n",
2031 center_freq, subband_l, subband_h);
2032
2033 return min(ant_gain->offset[path][subband_l],
2034 ant_gain->offset[path][subband_h]);
2035 }
2036
rtw89_phy_ant_gain_offset(struct rtw89_dev * rtwdev,u8 band,u32 center_freq)2037 static s8 rtw89_phy_ant_gain_offset(struct rtw89_dev *rtwdev, u8 band, u32 center_freq)
2038 {
2039 struct rtw89_ant_gain_info *ant_gain = &rtwdev->ant_gain;
2040 const struct rtw89_chip_info *chip = rtwdev->chip;
2041 u8 regd = rtw89_regd_get(rtwdev, band);
2042 s8 offset_patha, offset_pathb;
2043
2044 if (!chip->support_ant_gain)
2045 return 0;
2046
2047 if (ant_gain->block_country || !(ant_gain->regd_enabled & BIT(regd)))
2048 return 0;
2049
2050 offset_patha = rtw89_phy_ant_gain_query(rtwdev, RF_PATH_A, center_freq);
2051 offset_pathb = rtw89_phy_ant_gain_query(rtwdev, RF_PATH_B, center_freq);
2052
2053 if (RTW89_CHK_FW_FEATURE(NO_POWER_DIFFERENCE, &rtwdev->fw))
2054 return min(offset_patha, offset_pathb);
2055
2056 return max(offset_patha, offset_pathb);
2057 }
2058
rtw89_phy_ant_gain_pwr_offset(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan)2059 s16 rtw89_phy_ant_gain_pwr_offset(struct rtw89_dev *rtwdev,
2060 const struct rtw89_chan *chan)
2061 {
2062 struct rtw89_ant_gain_info *ant_gain = &rtwdev->ant_gain;
2063 const struct rtw89_chip_info *chip = rtwdev->chip;
2064 u8 regd = rtw89_regd_get(rtwdev, chan->band_type);
2065 s8 offset_patha, offset_pathb;
2066
2067 if (!chip->support_ant_gain)
2068 return 0;
2069
2070 if (ant_gain->block_country || !(ant_gain->regd_enabled & BIT(regd)))
2071 return 0;
2072
2073 if (RTW89_CHK_FW_FEATURE(NO_POWER_DIFFERENCE, &rtwdev->fw))
2074 return 0;
2075
2076 offset_patha = rtw89_phy_ant_gain_query(rtwdev, RF_PATH_A, chan->freq);
2077 offset_pathb = rtw89_phy_ant_gain_query(rtwdev, RF_PATH_B, chan->freq);
2078
2079 return rtw89_phy_txpwr_rf_to_bb(rtwdev, offset_patha - offset_pathb);
2080 }
2081 EXPORT_SYMBOL(rtw89_phy_ant_gain_pwr_offset);
2082
rtw89_print_ant_gain(struct rtw89_dev * rtwdev,char * buf,size_t bufsz,const struct rtw89_chan * chan)2083 int rtw89_print_ant_gain(struct rtw89_dev *rtwdev, char *buf, size_t bufsz,
2084 const struct rtw89_chan *chan)
2085 {
2086 struct rtw89_ant_gain_info *ant_gain = &rtwdev->ant_gain;
2087 const struct rtw89_chip_info *chip = rtwdev->chip;
2088 u8 regd = rtw89_regd_get(rtwdev, chan->band_type);
2089 char *p = buf, *end = buf + bufsz;
2090 s8 offset_patha, offset_pathb;
2091
2092 if (!(chip->support_ant_gain && (ant_gain->regd_enabled & BIT(regd))) ||
2093 ant_gain->block_country) {
2094 p += scnprintf(p, end - p, "no DAG is applied\n");
2095 goto out;
2096 }
2097
2098 offset_patha = rtw89_phy_ant_gain_query(rtwdev, RF_PATH_A, chan->freq);
2099 offset_pathb = rtw89_phy_ant_gain_query(rtwdev, RF_PATH_B, chan->freq);
2100
2101 p += scnprintf(p, end - p, "ChainA offset: %d dBm\n", offset_patha);
2102 p += scnprintf(p, end - p, "ChainB offset: %d dBm\n", offset_pathb);
2103
2104 out:
2105 return p - buf;
2106 }
2107
2108 static const u8 rtw89_rs_idx_num_ax[] = {
2109 [RTW89_RS_CCK] = RTW89_RATE_CCK_NUM,
2110 [RTW89_RS_OFDM] = RTW89_RATE_OFDM_NUM,
2111 [RTW89_RS_MCS] = RTW89_RATE_MCS_NUM_AX,
2112 [RTW89_RS_HEDCM] = RTW89_RATE_HEDCM_NUM,
2113 [RTW89_RS_OFFSET] = RTW89_RATE_OFFSET_NUM_AX,
2114 };
2115
2116 static const u8 rtw89_rs_nss_num_ax[] = {
2117 [RTW89_RS_CCK] = 1,
2118 [RTW89_RS_OFDM] = 1,
2119 [RTW89_RS_MCS] = RTW89_NSS_NUM,
2120 [RTW89_RS_HEDCM] = RTW89_NSS_HEDCM_NUM,
2121 [RTW89_RS_OFFSET] = 1,
2122 };
2123
rtw89_phy_raw_byr_seek(struct rtw89_dev * rtwdev,struct rtw89_txpwr_byrate * head,const struct rtw89_rate_desc * desc)2124 s8 *rtw89_phy_raw_byr_seek(struct rtw89_dev *rtwdev,
2125 struct rtw89_txpwr_byrate *head,
2126 const struct rtw89_rate_desc *desc)
2127 {
2128 switch (desc->rs) {
2129 case RTW89_RS_CCK:
2130 return &head->cck[desc->idx];
2131 case RTW89_RS_OFDM:
2132 return &head->ofdm[desc->idx];
2133 case RTW89_RS_MCS:
2134 return &head->mcs[desc->ofdma][desc->nss][desc->idx];
2135 case RTW89_RS_HEDCM:
2136 return &head->hedcm[desc->ofdma][desc->nss][desc->idx];
2137 case RTW89_RS_OFFSET:
2138 return &head->offset[desc->idx];
2139 default:
2140 rtw89_warn(rtwdev, "unrecognized byr rs: %d\n", desc->rs);
2141 return &head->trap;
2142 }
2143 }
2144
rtw89_phy_load_txpwr_byrate(struct rtw89_dev * rtwdev,const struct rtw89_txpwr_table * tbl)2145 void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev,
2146 const struct rtw89_txpwr_table *tbl)
2147 {
2148 const struct rtw89_txpwr_byrate_cfg *cfg = tbl->data;
2149 const struct rtw89_txpwr_byrate_cfg *end = cfg + tbl->size;
2150 struct rtw89_txpwr_byrate *byr_head;
2151 struct rtw89_rate_desc desc = {};
2152 s8 *byr;
2153 u32 data;
2154 u8 i;
2155
2156 for (; cfg < end; cfg++) {
2157 byr_head = &rtwdev->byr[cfg->band][0];
2158 desc.rs = cfg->rs;
2159 desc.nss = cfg->nss;
2160 data = cfg->data;
2161
2162 for (i = 0; i < cfg->len; i++, data >>= 8) {
2163 desc.idx = cfg->shf + i;
2164 byr = rtw89_phy_raw_byr_seek(rtwdev, byr_head, &desc);
2165 *byr = data & 0xff;
2166 }
2167 }
2168 }
2169 EXPORT_SYMBOL(rtw89_phy_load_txpwr_byrate);
2170
rtw89_phy_txpwr_dbm_without_tolerance(s8 dbm)2171 static s8 rtw89_phy_txpwr_dbm_without_tolerance(s8 dbm)
2172 {
2173 const u8 tssi_deviation_point = 0;
2174 const u8 tssi_max_deviation = 2;
2175
2176 if (dbm <= tssi_deviation_point)
2177 dbm -= tssi_max_deviation;
2178
2179 return dbm;
2180 }
2181
rtw89_phy_get_tpe_constraint(struct rtw89_dev * rtwdev,u8 band)2182 static s8 rtw89_phy_get_tpe_constraint(struct rtw89_dev *rtwdev, u8 band)
2183 {
2184 struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory;
2185 const struct rtw89_reg_6ghz_tpe *tpe = ®ulatory->reg_6ghz_tpe;
2186 s8 cstr = S8_MAX;
2187
2188 if (band == RTW89_BAND_6G && tpe->valid)
2189 cstr = rtw89_phy_txpwr_dbm_without_tolerance(tpe->constraint);
2190
2191 return rtw89_phy_txpwr_dbm_to_mac(rtwdev, cstr);
2192 }
2193
rtw89_phy_read_txpwr_byrate(struct rtw89_dev * rtwdev,u8 band,u8 bw,const struct rtw89_rate_desc * rate_desc)2194 s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, u8 band, u8 bw,
2195 const struct rtw89_rate_desc *rate_desc)
2196 {
2197 struct rtw89_txpwr_byrate *byr_head;
2198 s8 *byr;
2199
2200 if (rate_desc->rs == RTW89_RS_CCK)
2201 band = RTW89_BAND_2G;
2202
2203 byr_head = &rtwdev->byr[band][bw];
2204 byr = rtw89_phy_raw_byr_seek(rtwdev, byr_head, rate_desc);
2205
2206 return rtw89_phy_txpwr_rf_to_mac(rtwdev, *byr);
2207 }
2208
rtw89_channel_6g_to_idx(struct rtw89_dev * rtwdev,u8 channel_6g)2209 static u8 rtw89_channel_6g_to_idx(struct rtw89_dev *rtwdev, u8 channel_6g)
2210 {
2211 switch (channel_6g) {
2212 case 1 ... 29:
2213 return (channel_6g - 1) / 2;
2214 case 33 ... 61:
2215 return (channel_6g - 3) / 2;
2216 case 65 ... 93:
2217 return (channel_6g - 5) / 2;
2218 case 97 ... 125:
2219 return (channel_6g - 7) / 2;
2220 case 129 ... 157:
2221 return (channel_6g - 9) / 2;
2222 case 161 ... 189:
2223 return (channel_6g - 11) / 2;
2224 case 193 ... 221:
2225 return (channel_6g - 13) / 2;
2226 case 225 ... 253:
2227 return (channel_6g - 15) / 2;
2228 default:
2229 rtw89_warn(rtwdev, "unknown 6g channel: %d\n", channel_6g);
2230 return 0;
2231 }
2232 }
2233
rtw89_channel_to_idx(struct rtw89_dev * rtwdev,u8 band,u8 channel)2234 static u8 rtw89_channel_to_idx(struct rtw89_dev *rtwdev, u8 band, u8 channel)
2235 {
2236 if (band == RTW89_BAND_6G)
2237 return rtw89_channel_6g_to_idx(rtwdev, channel);
2238
2239 switch (channel) {
2240 case 1 ... 14:
2241 return channel - 1;
2242 case 36 ... 64:
2243 return (channel - 36) / 2;
2244 case 100 ... 144:
2245 return ((channel - 100) / 2) + 15;
2246 case 149 ... 177:
2247 return ((channel - 149) / 2) + 38;
2248 default:
2249 rtw89_warn(rtwdev, "unknown channel: %d\n", channel);
2250 return 0;
2251 }
2252 }
2253
rtw89_phy_read_txpwr_limit(struct rtw89_dev * rtwdev,u8 band,u8 bw,u8 ntx,u8 rs,u8 bf,u8 ch)2254 s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, u8 band,
2255 u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch)
2256 {
2257 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms;
2258 const struct rtw89_txpwr_rule_2ghz *rule_2ghz = &rfe_parms->rule_2ghz;
2259 const struct rtw89_txpwr_rule_5ghz *rule_5ghz = &rfe_parms->rule_5ghz;
2260 const struct rtw89_txpwr_rule_6ghz *rule_6ghz = &rfe_parms->rule_6ghz;
2261 struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory;
2262 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band);
2263 u32 freq = ieee80211_channel_to_frequency(ch, nl_band);
2264 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch);
2265 u8 regd = rtw89_regd_get(rtwdev, band);
2266 u8 reg6 = regulatory->reg_6ghz_power;
2267 s8 lmt = 0, sar, offset;
2268 s8 cstr;
2269
2270 switch (band) {
2271 case RTW89_BAND_2G:
2272 lmt = (*rule_2ghz->lmt)[bw][ntx][rs][bf][regd][ch_idx];
2273 if (lmt)
2274 break;
2275
2276 lmt = (*rule_2ghz->lmt)[bw][ntx][rs][bf][RTW89_WW][ch_idx];
2277 break;
2278 case RTW89_BAND_5G:
2279 lmt = (*rule_5ghz->lmt)[bw][ntx][rs][bf][regd][ch_idx];
2280 if (lmt)
2281 break;
2282
2283 lmt = (*rule_5ghz->lmt)[bw][ntx][rs][bf][RTW89_WW][ch_idx];
2284 break;
2285 case RTW89_BAND_6G:
2286 lmt = (*rule_6ghz->lmt)[bw][ntx][rs][bf][regd][reg6][ch_idx];
2287 if (lmt)
2288 break;
2289
2290 lmt = (*rule_6ghz->lmt)[bw][ntx][rs][bf][RTW89_WW]
2291 [RTW89_REG_6GHZ_POWER_DFLT]
2292 [ch_idx];
2293 break;
2294 default:
2295 rtw89_warn(rtwdev, "unknown band type: %d\n", band);
2296 return 0;
2297 }
2298
2299 offset = rtw89_phy_ant_gain_offset(rtwdev, band, freq);
2300 lmt = rtw89_phy_txpwr_rf_to_mac(rtwdev, lmt + offset);
2301 sar = rtw89_query_sar(rtwdev, freq);
2302 cstr = rtw89_phy_get_tpe_constraint(rtwdev, band);
2303
2304 return min3(lmt, sar, cstr);
2305 }
2306 EXPORT_SYMBOL(rtw89_phy_read_txpwr_limit);
2307
2308 #define __fill_txpwr_limit_nonbf_bf(ptr, band, bw, ntx, rs, ch) \
2309 do { \
2310 u8 __i; \
2311 for (__i = 0; __i < RTW89_BF_NUM; __i++) \
2312 ptr[__i] = rtw89_phy_read_txpwr_limit(rtwdev, \
2313 band, \
2314 bw, ntx, \
2315 rs, __i, \
2316 (ch)); \
2317 } while (0)
2318
rtw89_phy_fill_txpwr_limit_20m_ax(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ax * lmt,u8 band,u8 ntx,u8 ch)2319 static void rtw89_phy_fill_txpwr_limit_20m_ax(struct rtw89_dev *rtwdev,
2320 struct rtw89_txpwr_limit_ax *lmt,
2321 u8 band, u8 ntx, u8 ch)
2322 {
2323 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, band, RTW89_CHANNEL_WIDTH_20,
2324 ntx, RTW89_RS_CCK, ch);
2325 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, band, RTW89_CHANNEL_WIDTH_40,
2326 ntx, RTW89_RS_CCK, ch);
2327 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20,
2328 ntx, RTW89_RS_OFDM, ch);
2329 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band,
2330 RTW89_CHANNEL_WIDTH_20,
2331 ntx, RTW89_RS_MCS, ch);
2332 }
2333
rtw89_phy_fill_txpwr_limit_40m_ax(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ax * lmt,u8 band,u8 ntx,u8 ch,u8 pri_ch)2334 static void rtw89_phy_fill_txpwr_limit_40m_ax(struct rtw89_dev *rtwdev,
2335 struct rtw89_txpwr_limit_ax *lmt,
2336 u8 band, u8 ntx, u8 ch, u8 pri_ch)
2337 {
2338 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, band, RTW89_CHANNEL_WIDTH_20,
2339 ntx, RTW89_RS_CCK, ch - 2);
2340 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, band, RTW89_CHANNEL_WIDTH_40,
2341 ntx, RTW89_RS_CCK, ch);
2342 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20,
2343 ntx, RTW89_RS_OFDM, pri_ch);
2344 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band,
2345 RTW89_CHANNEL_WIDTH_20,
2346 ntx, RTW89_RS_MCS, ch - 2);
2347 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band,
2348 RTW89_CHANNEL_WIDTH_20,
2349 ntx, RTW89_RS_MCS, ch + 2);
2350 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band,
2351 RTW89_CHANNEL_WIDTH_40,
2352 ntx, RTW89_RS_MCS, ch);
2353 }
2354
rtw89_phy_fill_txpwr_limit_80m_ax(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ax * lmt,u8 band,u8 ntx,u8 ch,u8 pri_ch)2355 static void rtw89_phy_fill_txpwr_limit_80m_ax(struct rtw89_dev *rtwdev,
2356 struct rtw89_txpwr_limit_ax *lmt,
2357 u8 band, u8 ntx, u8 ch, u8 pri_ch)
2358 {
2359 s8 val_0p5_n[RTW89_BF_NUM];
2360 s8 val_0p5_p[RTW89_BF_NUM];
2361 u8 i;
2362
2363 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20,
2364 ntx, RTW89_RS_OFDM, pri_ch);
2365 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band,
2366 RTW89_CHANNEL_WIDTH_20,
2367 ntx, RTW89_RS_MCS, ch - 6);
2368 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band,
2369 RTW89_CHANNEL_WIDTH_20,
2370 ntx, RTW89_RS_MCS, ch - 2);
2371 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], band,
2372 RTW89_CHANNEL_WIDTH_20,
2373 ntx, RTW89_RS_MCS, ch + 2);
2374 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], band,
2375 RTW89_CHANNEL_WIDTH_20,
2376 ntx, RTW89_RS_MCS, ch + 6);
2377 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band,
2378 RTW89_CHANNEL_WIDTH_40,
2379 ntx, RTW89_RS_MCS, ch - 4);
2380 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], band,
2381 RTW89_CHANNEL_WIDTH_40,
2382 ntx, RTW89_RS_MCS, ch + 4);
2383 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], band,
2384 RTW89_CHANNEL_WIDTH_80,
2385 ntx, RTW89_RS_MCS, ch);
2386
2387 __fill_txpwr_limit_nonbf_bf(val_0p5_n, band, RTW89_CHANNEL_WIDTH_40,
2388 ntx, RTW89_RS_MCS, ch - 4);
2389 __fill_txpwr_limit_nonbf_bf(val_0p5_p, band, RTW89_CHANNEL_WIDTH_40,
2390 ntx, RTW89_RS_MCS, ch + 4);
2391
2392 for (i = 0; i < RTW89_BF_NUM; i++)
2393 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]);
2394 }
2395
rtw89_phy_fill_txpwr_limit_160m_ax(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ax * lmt,u8 band,u8 ntx,u8 ch,u8 pri_ch)2396 static void rtw89_phy_fill_txpwr_limit_160m_ax(struct rtw89_dev *rtwdev,
2397 struct rtw89_txpwr_limit_ax *lmt,
2398 u8 band, u8 ntx, u8 ch, u8 pri_ch)
2399 {
2400 s8 val_0p5_n[RTW89_BF_NUM];
2401 s8 val_0p5_p[RTW89_BF_NUM];
2402 s8 val_2p5_n[RTW89_BF_NUM];
2403 s8 val_2p5_p[RTW89_BF_NUM];
2404 u8 i;
2405
2406 /* fill ofdm section */
2407 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20,
2408 ntx, RTW89_RS_OFDM, pri_ch);
2409
2410 /* fill mcs 20m section */
2411 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band,
2412 RTW89_CHANNEL_WIDTH_20,
2413 ntx, RTW89_RS_MCS, ch - 14);
2414 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band,
2415 RTW89_CHANNEL_WIDTH_20,
2416 ntx, RTW89_RS_MCS, ch - 10);
2417 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], band,
2418 RTW89_CHANNEL_WIDTH_20,
2419 ntx, RTW89_RS_MCS, ch - 6);
2420 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], band,
2421 RTW89_CHANNEL_WIDTH_20,
2422 ntx, RTW89_RS_MCS, ch - 2);
2423 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[4], band,
2424 RTW89_CHANNEL_WIDTH_20,
2425 ntx, RTW89_RS_MCS, ch + 2);
2426 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[5], band,
2427 RTW89_CHANNEL_WIDTH_20,
2428 ntx, RTW89_RS_MCS, ch + 6);
2429 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[6], band,
2430 RTW89_CHANNEL_WIDTH_20,
2431 ntx, RTW89_RS_MCS, ch + 10);
2432 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[7], band,
2433 RTW89_CHANNEL_WIDTH_20,
2434 ntx, RTW89_RS_MCS, ch + 14);
2435
2436 /* fill mcs 40m section */
2437 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band,
2438 RTW89_CHANNEL_WIDTH_40,
2439 ntx, RTW89_RS_MCS, ch - 12);
2440 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], band,
2441 RTW89_CHANNEL_WIDTH_40,
2442 ntx, RTW89_RS_MCS, ch - 4);
2443 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[2], band,
2444 RTW89_CHANNEL_WIDTH_40,
2445 ntx, RTW89_RS_MCS, ch + 4);
2446 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[3], band,
2447 RTW89_CHANNEL_WIDTH_40,
2448 ntx, RTW89_RS_MCS, ch + 12);
2449
2450 /* fill mcs 80m section */
2451 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], band,
2452 RTW89_CHANNEL_WIDTH_80,
2453 ntx, RTW89_RS_MCS, ch - 8);
2454 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[1], band,
2455 RTW89_CHANNEL_WIDTH_80,
2456 ntx, RTW89_RS_MCS, ch + 8);
2457
2458 /* fill mcs 160m section */
2459 __fill_txpwr_limit_nonbf_bf(lmt->mcs_160m, band,
2460 RTW89_CHANNEL_WIDTH_160,
2461 ntx, RTW89_RS_MCS, ch);
2462
2463 /* fill mcs 40m 0p5 section */
2464 __fill_txpwr_limit_nonbf_bf(val_0p5_n, band, RTW89_CHANNEL_WIDTH_40,
2465 ntx, RTW89_RS_MCS, ch - 4);
2466 __fill_txpwr_limit_nonbf_bf(val_0p5_p, band, RTW89_CHANNEL_WIDTH_40,
2467 ntx, RTW89_RS_MCS, ch + 4);
2468
2469 for (i = 0; i < RTW89_BF_NUM; i++)
2470 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]);
2471
2472 /* fill mcs 40m 2p5 section */
2473 __fill_txpwr_limit_nonbf_bf(val_2p5_n, band, RTW89_CHANNEL_WIDTH_40,
2474 ntx, RTW89_RS_MCS, ch - 8);
2475 __fill_txpwr_limit_nonbf_bf(val_2p5_p, band, RTW89_CHANNEL_WIDTH_40,
2476 ntx, RTW89_RS_MCS, ch + 8);
2477
2478 for (i = 0; i < RTW89_BF_NUM; i++)
2479 lmt->mcs_40m_2p5[i] = min_t(s8, val_2p5_n[i], val_2p5_p[i]);
2480 }
2481
2482 static
rtw89_phy_fill_txpwr_limit_ax(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,struct rtw89_txpwr_limit_ax * lmt,u8 ntx)2483 void rtw89_phy_fill_txpwr_limit_ax(struct rtw89_dev *rtwdev,
2484 const struct rtw89_chan *chan,
2485 struct rtw89_txpwr_limit_ax *lmt,
2486 u8 ntx)
2487 {
2488 u8 band = chan->band_type;
2489 u8 pri_ch = chan->primary_channel;
2490 u8 ch = chan->channel;
2491 u8 bw = chan->band_width;
2492
2493 memset(lmt, 0, sizeof(*lmt));
2494
2495 switch (bw) {
2496 case RTW89_CHANNEL_WIDTH_20:
2497 rtw89_phy_fill_txpwr_limit_20m_ax(rtwdev, lmt, band, ntx, ch);
2498 break;
2499 case RTW89_CHANNEL_WIDTH_40:
2500 rtw89_phy_fill_txpwr_limit_40m_ax(rtwdev, lmt, band, ntx, ch,
2501 pri_ch);
2502 break;
2503 case RTW89_CHANNEL_WIDTH_80:
2504 rtw89_phy_fill_txpwr_limit_80m_ax(rtwdev, lmt, band, ntx, ch,
2505 pri_ch);
2506 break;
2507 case RTW89_CHANNEL_WIDTH_160:
2508 rtw89_phy_fill_txpwr_limit_160m_ax(rtwdev, lmt, band, ntx, ch,
2509 pri_ch);
2510 break;
2511 }
2512 }
2513
rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev * rtwdev,u8 band,u8 ru,u8 ntx,u8 ch)2514 s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, u8 band,
2515 u8 ru, u8 ntx, u8 ch)
2516 {
2517 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms;
2518 const struct rtw89_txpwr_rule_2ghz *rule_2ghz = &rfe_parms->rule_2ghz;
2519 const struct rtw89_txpwr_rule_5ghz *rule_5ghz = &rfe_parms->rule_5ghz;
2520 const struct rtw89_txpwr_rule_6ghz *rule_6ghz = &rfe_parms->rule_6ghz;
2521 struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory;
2522 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band);
2523 u32 freq = ieee80211_channel_to_frequency(ch, nl_band);
2524 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch);
2525 u8 regd = rtw89_regd_get(rtwdev, band);
2526 u8 reg6 = regulatory->reg_6ghz_power;
2527 s8 lmt_ru = 0, sar, offset;
2528 s8 cstr;
2529
2530 switch (band) {
2531 case RTW89_BAND_2G:
2532 lmt_ru = (*rule_2ghz->lmt_ru)[ru][ntx][regd][ch_idx];
2533 if (lmt_ru)
2534 break;
2535
2536 lmt_ru = (*rule_2ghz->lmt_ru)[ru][ntx][RTW89_WW][ch_idx];
2537 break;
2538 case RTW89_BAND_5G:
2539 lmt_ru = (*rule_5ghz->lmt_ru)[ru][ntx][regd][ch_idx];
2540 if (lmt_ru)
2541 break;
2542
2543 lmt_ru = (*rule_5ghz->lmt_ru)[ru][ntx][RTW89_WW][ch_idx];
2544 break;
2545 case RTW89_BAND_6G:
2546 lmt_ru = (*rule_6ghz->lmt_ru)[ru][ntx][regd][reg6][ch_idx];
2547 if (lmt_ru)
2548 break;
2549
2550 lmt_ru = (*rule_6ghz->lmt_ru)[ru][ntx][RTW89_WW]
2551 [RTW89_REG_6GHZ_POWER_DFLT]
2552 [ch_idx];
2553 break;
2554 default:
2555 rtw89_warn(rtwdev, "unknown band type: %d\n", band);
2556 return 0;
2557 }
2558
2559 offset = rtw89_phy_ant_gain_offset(rtwdev, band, freq);
2560 lmt_ru = rtw89_phy_txpwr_rf_to_mac(rtwdev, lmt_ru + offset);
2561 sar = rtw89_query_sar(rtwdev, freq);
2562 cstr = rtw89_phy_get_tpe_constraint(rtwdev, band);
2563
2564 return min3(lmt_ru, sar, cstr);
2565 }
2566
2567 static void
rtw89_phy_fill_txpwr_limit_ru_20m_ax(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ru_ax * lmt_ru,u8 band,u8 ntx,u8 ch)2568 rtw89_phy_fill_txpwr_limit_ru_20m_ax(struct rtw89_dev *rtwdev,
2569 struct rtw89_txpwr_limit_ru_ax *lmt_ru,
2570 u8 band, u8 ntx, u8 ch)
2571 {
2572 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2573 RTW89_RU26,
2574 ntx, ch);
2575 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2576 RTW89_RU52,
2577 ntx, ch);
2578 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2579 RTW89_RU106,
2580 ntx, ch);
2581 }
2582
2583 static void
rtw89_phy_fill_txpwr_limit_ru_40m_ax(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ru_ax * lmt_ru,u8 band,u8 ntx,u8 ch)2584 rtw89_phy_fill_txpwr_limit_ru_40m_ax(struct rtw89_dev *rtwdev,
2585 struct rtw89_txpwr_limit_ru_ax *lmt_ru,
2586 u8 band, u8 ntx, u8 ch)
2587 {
2588 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2589 RTW89_RU26,
2590 ntx, ch - 2);
2591 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2592 RTW89_RU26,
2593 ntx, ch + 2);
2594 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2595 RTW89_RU52,
2596 ntx, ch - 2);
2597 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2598 RTW89_RU52,
2599 ntx, ch + 2);
2600 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2601 RTW89_RU106,
2602 ntx, ch - 2);
2603 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2604 RTW89_RU106,
2605 ntx, ch + 2);
2606 }
2607
2608 static void
rtw89_phy_fill_txpwr_limit_ru_80m_ax(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ru_ax * lmt_ru,u8 band,u8 ntx,u8 ch)2609 rtw89_phy_fill_txpwr_limit_ru_80m_ax(struct rtw89_dev *rtwdev,
2610 struct rtw89_txpwr_limit_ru_ax *lmt_ru,
2611 u8 band, u8 ntx, u8 ch)
2612 {
2613 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2614 RTW89_RU26,
2615 ntx, ch - 6);
2616 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2617 RTW89_RU26,
2618 ntx, ch - 2);
2619 lmt_ru->ru26[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2620 RTW89_RU26,
2621 ntx, ch + 2);
2622 lmt_ru->ru26[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2623 RTW89_RU26,
2624 ntx, ch + 6);
2625 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2626 RTW89_RU52,
2627 ntx, ch - 6);
2628 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2629 RTW89_RU52,
2630 ntx, ch - 2);
2631 lmt_ru->ru52[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2632 RTW89_RU52,
2633 ntx, ch + 2);
2634 lmt_ru->ru52[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2635 RTW89_RU52,
2636 ntx, ch + 6);
2637 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2638 RTW89_RU106,
2639 ntx, ch - 6);
2640 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2641 RTW89_RU106,
2642 ntx, ch - 2);
2643 lmt_ru->ru106[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2644 RTW89_RU106,
2645 ntx, ch + 2);
2646 lmt_ru->ru106[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2647 RTW89_RU106,
2648 ntx, ch + 6);
2649 }
2650
2651 static void
rtw89_phy_fill_txpwr_limit_ru_160m_ax(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ru_ax * lmt_ru,u8 band,u8 ntx,u8 ch)2652 rtw89_phy_fill_txpwr_limit_ru_160m_ax(struct rtw89_dev *rtwdev,
2653 struct rtw89_txpwr_limit_ru_ax *lmt_ru,
2654 u8 band, u8 ntx, u8 ch)
2655 {
2656 static const int ofst[] = { -14, -10, -6, -2, 2, 6, 10, 14 };
2657 int i;
2658
2659 static_assert(ARRAY_SIZE(ofst) == RTW89_RU_SEC_NUM_AX);
2660 for (i = 0; i < RTW89_RU_SEC_NUM_AX; i++) {
2661 lmt_ru->ru26[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2662 RTW89_RU26,
2663 ntx,
2664 ch + ofst[i]);
2665 lmt_ru->ru52[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2666 RTW89_RU52,
2667 ntx,
2668 ch + ofst[i]);
2669 lmt_ru->ru106[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2670 RTW89_RU106,
2671 ntx,
2672 ch + ofst[i]);
2673 }
2674 }
2675
2676 static
rtw89_phy_fill_txpwr_limit_ru_ax(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,struct rtw89_txpwr_limit_ru_ax * lmt_ru,u8 ntx)2677 void rtw89_phy_fill_txpwr_limit_ru_ax(struct rtw89_dev *rtwdev,
2678 const struct rtw89_chan *chan,
2679 struct rtw89_txpwr_limit_ru_ax *lmt_ru,
2680 u8 ntx)
2681 {
2682 u8 band = chan->band_type;
2683 u8 ch = chan->channel;
2684 u8 bw = chan->band_width;
2685
2686 memset(lmt_ru, 0, sizeof(*lmt_ru));
2687
2688 switch (bw) {
2689 case RTW89_CHANNEL_WIDTH_20:
2690 rtw89_phy_fill_txpwr_limit_ru_20m_ax(rtwdev, lmt_ru, band, ntx,
2691 ch);
2692 break;
2693 case RTW89_CHANNEL_WIDTH_40:
2694 rtw89_phy_fill_txpwr_limit_ru_40m_ax(rtwdev, lmt_ru, band, ntx,
2695 ch);
2696 break;
2697 case RTW89_CHANNEL_WIDTH_80:
2698 rtw89_phy_fill_txpwr_limit_ru_80m_ax(rtwdev, lmt_ru, band, ntx,
2699 ch);
2700 break;
2701 case RTW89_CHANNEL_WIDTH_160:
2702 rtw89_phy_fill_txpwr_limit_ru_160m_ax(rtwdev, lmt_ru, band, ntx,
2703 ch);
2704 break;
2705 }
2706 }
2707
rtw89_phy_set_txpwr_byrate_ax(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)2708 static void rtw89_phy_set_txpwr_byrate_ax(struct rtw89_dev *rtwdev,
2709 const struct rtw89_chan *chan,
2710 enum rtw89_phy_idx phy_idx)
2711 {
2712 u8 max_nss_num = rtwdev->chip->rf_path_num;
2713 static const u8 rs[] = {
2714 RTW89_RS_CCK,
2715 RTW89_RS_OFDM,
2716 RTW89_RS_MCS,
2717 RTW89_RS_HEDCM,
2718 };
2719 struct rtw89_rate_desc cur = {};
2720 u8 band = chan->band_type;
2721 u8 ch = chan->channel;
2722 u32 addr, val;
2723 s8 v[4] = {};
2724 u8 i;
2725
2726 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
2727 "[TXPWR] set txpwr byrate with ch=%d\n", ch);
2728
2729 BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_CCK] % 4);
2730 BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_OFDM] % 4);
2731 BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_MCS] % 4);
2732 BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_HEDCM] % 4);
2733
2734 addr = R_AX_PWR_BY_RATE;
2735 for (cur.nss = 0; cur.nss < max_nss_num; cur.nss++) {
2736 for (i = 0; i < ARRAY_SIZE(rs); i++) {
2737 if (cur.nss >= rtw89_rs_nss_num_ax[rs[i]])
2738 continue;
2739
2740 cur.rs = rs[i];
2741 for (cur.idx = 0; cur.idx < rtw89_rs_idx_num_ax[rs[i]];
2742 cur.idx++) {
2743 v[cur.idx % 4] =
2744 rtw89_phy_read_txpwr_byrate(rtwdev,
2745 band, 0,
2746 &cur);
2747
2748 if ((cur.idx + 1) % 4)
2749 continue;
2750
2751 val = FIELD_PREP(GENMASK(7, 0), v[0]) |
2752 FIELD_PREP(GENMASK(15, 8), v[1]) |
2753 FIELD_PREP(GENMASK(23, 16), v[2]) |
2754 FIELD_PREP(GENMASK(31, 24), v[3]);
2755
2756 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr,
2757 val);
2758 addr += 4;
2759 }
2760 }
2761 }
2762 }
2763
2764 static
rtw89_phy_set_txpwr_offset_ax(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)2765 void rtw89_phy_set_txpwr_offset_ax(struct rtw89_dev *rtwdev,
2766 const struct rtw89_chan *chan,
2767 enum rtw89_phy_idx phy_idx)
2768 {
2769 struct rtw89_rate_desc desc = {
2770 .nss = RTW89_NSS_1,
2771 .rs = RTW89_RS_OFFSET,
2772 };
2773 u8 band = chan->band_type;
2774 s8 v[RTW89_RATE_OFFSET_NUM_AX] = {};
2775 u32 val;
2776
2777 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr offset\n");
2778
2779 for (desc.idx = 0; desc.idx < RTW89_RATE_OFFSET_NUM_AX; desc.idx++)
2780 v[desc.idx] = rtw89_phy_read_txpwr_byrate(rtwdev, band, 0, &desc);
2781
2782 BUILD_BUG_ON(RTW89_RATE_OFFSET_NUM_AX != 5);
2783 val = FIELD_PREP(GENMASK(3, 0), v[0]) |
2784 FIELD_PREP(GENMASK(7, 4), v[1]) |
2785 FIELD_PREP(GENMASK(11, 8), v[2]) |
2786 FIELD_PREP(GENMASK(15, 12), v[3]) |
2787 FIELD_PREP(GENMASK(19, 16), v[4]);
2788
2789 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_OFST_CTRL,
2790 GENMASK(19, 0), val);
2791 }
2792
rtw89_phy_set_txpwr_limit_ax(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)2793 static void rtw89_phy_set_txpwr_limit_ax(struct rtw89_dev *rtwdev,
2794 const struct rtw89_chan *chan,
2795 enum rtw89_phy_idx phy_idx)
2796 {
2797 u8 max_ntx_num = rtwdev->chip->rf_path_num;
2798 struct rtw89_txpwr_limit_ax lmt;
2799 u8 ch = chan->channel;
2800 u8 bw = chan->band_width;
2801 const s8 *ptr;
2802 u32 addr, val;
2803 u8 i, j;
2804
2805 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
2806 "[TXPWR] set txpwr limit with ch=%d bw=%d\n", ch, bw);
2807
2808 BUILD_BUG_ON(sizeof(struct rtw89_txpwr_limit_ax) !=
2809 RTW89_TXPWR_LMT_PAGE_SIZE_AX);
2810
2811 addr = R_AX_PWR_LMT;
2812 for (i = 0; i < max_ntx_num; i++) {
2813 rtw89_phy_fill_txpwr_limit_ax(rtwdev, chan, &lmt, i);
2814
2815 ptr = (s8 *)&lmt;
2816 for (j = 0; j < RTW89_TXPWR_LMT_PAGE_SIZE_AX;
2817 j += 4, addr += 4, ptr += 4) {
2818 val = FIELD_PREP(GENMASK(7, 0), ptr[0]) |
2819 FIELD_PREP(GENMASK(15, 8), ptr[1]) |
2820 FIELD_PREP(GENMASK(23, 16), ptr[2]) |
2821 FIELD_PREP(GENMASK(31, 24), ptr[3]);
2822
2823 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
2824 }
2825 }
2826 }
2827
rtw89_phy_set_txpwr_limit_ru_ax(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)2828 static void rtw89_phy_set_txpwr_limit_ru_ax(struct rtw89_dev *rtwdev,
2829 const struct rtw89_chan *chan,
2830 enum rtw89_phy_idx phy_idx)
2831 {
2832 u8 max_ntx_num = rtwdev->chip->rf_path_num;
2833 struct rtw89_txpwr_limit_ru_ax lmt_ru;
2834 u8 ch = chan->channel;
2835 u8 bw = chan->band_width;
2836 const s8 *ptr;
2837 u32 addr, val;
2838 u8 i, j;
2839
2840 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
2841 "[TXPWR] set txpwr limit ru with ch=%d bw=%d\n", ch, bw);
2842
2843 BUILD_BUG_ON(sizeof(struct rtw89_txpwr_limit_ru_ax) !=
2844 RTW89_TXPWR_LMT_RU_PAGE_SIZE_AX);
2845
2846 addr = R_AX_PWR_RU_LMT;
2847 for (i = 0; i < max_ntx_num; i++) {
2848 rtw89_phy_fill_txpwr_limit_ru_ax(rtwdev, chan, &lmt_ru, i);
2849
2850 ptr = (s8 *)&lmt_ru;
2851 for (j = 0; j < RTW89_TXPWR_LMT_RU_PAGE_SIZE_AX;
2852 j += 4, addr += 4, ptr += 4) {
2853 val = FIELD_PREP(GENMASK(7, 0), ptr[0]) |
2854 FIELD_PREP(GENMASK(15, 8), ptr[1]) |
2855 FIELD_PREP(GENMASK(23, 16), ptr[2]) |
2856 FIELD_PREP(GENMASK(31, 24), ptr[3]);
2857
2858 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
2859 }
2860 }
2861 }
2862
2863 struct rtw89_phy_iter_ra_data {
2864 struct rtw89_dev *rtwdev;
2865 struct sk_buff *c2h;
2866 };
2867
__rtw89_phy_c2h_ra_rpt_iter(struct rtw89_sta_link * rtwsta_link,struct ieee80211_link_sta * link_sta,struct rtw89_phy_iter_ra_data * ra_data)2868 static void __rtw89_phy_c2h_ra_rpt_iter(struct rtw89_sta_link *rtwsta_link,
2869 struct ieee80211_link_sta *link_sta,
2870 struct rtw89_phy_iter_ra_data *ra_data)
2871 {
2872 struct rtw89_dev *rtwdev = ra_data->rtwdev;
2873 const struct rtw89_c2h_ra_rpt *c2h =
2874 (const struct rtw89_c2h_ra_rpt *)ra_data->c2h->data;
2875 struct rtw89_ra_report *ra_report = &rtwsta_link->ra_report;
2876 const struct rtw89_chip_info *chip = rtwdev->chip;
2877 bool format_v1 = chip->chip_gen == RTW89_CHIP_BE;
2878 u8 mode, rate, bw, giltf, mac_id;
2879 u16 legacy_bitrate;
2880 bool valid;
2881 u8 mcs = 0;
2882 u8 t;
2883
2884 mac_id = le32_get_bits(c2h->w2, RTW89_C2H_RA_RPT_W2_MACID);
2885 if (mac_id != rtwsta_link->mac_id)
2886 return;
2887
2888 rate = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_MCSNSS);
2889 bw = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_BW);
2890 giltf = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_GILTF);
2891 mode = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_MD_SEL);
2892
2893 if (format_v1) {
2894 t = le32_get_bits(c2h->w2, RTW89_C2H_RA_RPT_W2_MCSNSS_B7);
2895 rate |= u8_encode_bits(t, BIT(7));
2896 t = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_BW_B2);
2897 bw |= u8_encode_bits(t, BIT(2));
2898 t = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_MD_SEL_B2);
2899 mode |= u8_encode_bits(t, BIT(2));
2900 }
2901
2902 if (mode == RTW89_RA_RPT_MODE_LEGACY) {
2903 valid = rtw89_ra_report_to_bitrate(rtwdev, rate, &legacy_bitrate);
2904 if (!valid)
2905 return;
2906 }
2907
2908 memset(&ra_report->txrate, 0, sizeof(ra_report->txrate));
2909
2910 switch (mode) {
2911 case RTW89_RA_RPT_MODE_LEGACY:
2912 ra_report->txrate.legacy = legacy_bitrate;
2913 break;
2914 case RTW89_RA_RPT_MODE_HT:
2915 ra_report->txrate.flags |= RATE_INFO_FLAGS_MCS;
2916 if (RTW89_CHK_FW_FEATURE(OLD_HT_RA_FORMAT, &rtwdev->fw))
2917 rate = RTW89_MK_HT_RATE(FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate),
2918 FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate));
2919 else
2920 rate = FIELD_GET(RTW89_RA_RATE_MASK_HT_MCS, rate);
2921 ra_report->txrate.mcs = rate;
2922 if (giltf)
2923 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
2924 mcs = ra_report->txrate.mcs & 0x07;
2925 break;
2926 case RTW89_RA_RPT_MODE_VHT:
2927 ra_report->txrate.flags |= RATE_INFO_FLAGS_VHT_MCS;
2928 ra_report->txrate.mcs = format_v1 ?
2929 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS_V1) :
2930 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS);
2931 ra_report->txrate.nss = format_v1 ?
2932 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS_V1) + 1 :
2933 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS) + 1;
2934 if (giltf)
2935 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
2936 mcs = ra_report->txrate.mcs;
2937 break;
2938 case RTW89_RA_RPT_MODE_HE:
2939 ra_report->txrate.flags |= RATE_INFO_FLAGS_HE_MCS;
2940 ra_report->txrate.mcs = format_v1 ?
2941 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS_V1) :
2942 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS);
2943 ra_report->txrate.nss = format_v1 ?
2944 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS_V1) + 1 :
2945 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS) + 1;
2946 if (giltf == RTW89_GILTF_2XHE08 || giltf == RTW89_GILTF_1XHE08)
2947 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_0_8;
2948 else if (giltf == RTW89_GILTF_2XHE16 || giltf == RTW89_GILTF_1XHE16)
2949 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_1_6;
2950 else
2951 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_3_2;
2952 mcs = ra_report->txrate.mcs;
2953 break;
2954 case RTW89_RA_RPT_MODE_EHT:
2955 ra_report->txrate.flags |= RATE_INFO_FLAGS_EHT_MCS;
2956 ra_report->txrate.mcs = u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS_V1);
2957 ra_report->txrate.nss = u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS_V1) + 1;
2958 if (giltf == RTW89_GILTF_2XHE08 || giltf == RTW89_GILTF_1XHE08)
2959 ra_report->txrate.eht_gi = NL80211_RATE_INFO_EHT_GI_0_8;
2960 else if (giltf == RTW89_GILTF_2XHE16 || giltf == RTW89_GILTF_1XHE16)
2961 ra_report->txrate.eht_gi = NL80211_RATE_INFO_EHT_GI_1_6;
2962 else
2963 ra_report->txrate.eht_gi = NL80211_RATE_INFO_EHT_GI_3_2;
2964 mcs = ra_report->txrate.mcs;
2965 break;
2966 }
2967
2968 ra_report->txrate.bw = rtw89_hw_to_rate_info_bw(bw);
2969 ra_report->bit_rate = cfg80211_calculate_bitrate(&ra_report->txrate);
2970 ra_report->hw_rate = format_v1 ?
2971 u16_encode_bits(mode, RTW89_HW_RATE_V1_MASK_MOD) |
2972 u16_encode_bits(rate, RTW89_HW_RATE_V1_MASK_VAL) :
2973 u16_encode_bits(mode, RTW89_HW_RATE_MASK_MOD) |
2974 u16_encode_bits(rate, RTW89_HW_RATE_MASK_VAL);
2975 ra_report->might_fallback_legacy = mcs <= 2;
2976 link_sta->agg.max_rc_amsdu_len = get_max_amsdu_len(rtwdev, ra_report);
2977 rtwsta_link->max_agg_wait = link_sta->agg.max_rc_amsdu_len / 1500 - 1;
2978 }
2979
rtw89_phy_c2h_ra_rpt_iter(void * data,struct ieee80211_sta * sta)2980 static void rtw89_phy_c2h_ra_rpt_iter(void *data, struct ieee80211_sta *sta)
2981 {
2982 struct rtw89_phy_iter_ra_data *ra_data = (struct rtw89_phy_iter_ra_data *)data;
2983 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
2984 struct rtw89_sta_link *rtwsta_link;
2985 struct ieee80211_link_sta *link_sta;
2986 unsigned int link_id;
2987
2988 rcu_read_lock();
2989
2990 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) {
2991 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false);
2992 __rtw89_phy_c2h_ra_rpt_iter(rtwsta_link, link_sta, ra_data);
2993 }
2994
2995 rcu_read_unlock();
2996 }
2997
2998 static void
rtw89_phy_c2h_ra_rpt(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)2999 rtw89_phy_c2h_ra_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3000 {
3001 struct rtw89_phy_iter_ra_data ra_data;
3002
3003 ra_data.rtwdev = rtwdev;
3004 ra_data.c2h = c2h;
3005 ieee80211_iterate_stations_atomic(rtwdev->hw,
3006 rtw89_phy_c2h_ra_rpt_iter,
3007 &ra_data);
3008 }
3009
3010 static
3011 void (* const rtw89_phy_c2h_ra_handler[])(struct rtw89_dev *rtwdev,
3012 struct sk_buff *c2h, u32 len) = {
3013 [RTW89_PHY_C2H_FUNC_STS_RPT] = rtw89_phy_c2h_ra_rpt,
3014 [RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT] = NULL,
3015 [RTW89_PHY_C2H_FUNC_TXSTS] = NULL,
3016 };
3017
rtw89_phy_c2h_rfk_rpt_log(struct rtw89_dev * rtwdev,enum rtw89_phy_c2h_rfk_log_func func,void * content,u16 len)3018 static void rtw89_phy_c2h_rfk_rpt_log(struct rtw89_dev *rtwdev,
3019 enum rtw89_phy_c2h_rfk_log_func func,
3020 void *content, u16 len)
3021 {
3022 struct rtw89_c2h_rf_txgapk_rpt_log *txgapk;
3023 struct rtw89_c2h_rf_rxdck_rpt_log *rxdck;
3024 struct rtw89_c2h_rf_dack_rpt_log *dack;
3025 struct rtw89_c2h_rf_tssi_rpt_log *tssi;
3026 struct rtw89_c2h_rf_dpk_rpt_log *dpk;
3027 struct rtw89_c2h_rf_iqk_rpt_log *iqk;
3028 int i, j, k;
3029
3030 switch (func) {
3031 case RTW89_PHY_C2H_RFK_LOG_FUNC_IQK:
3032 if (len != sizeof(*iqk))
3033 goto out;
3034
3035 iqk = content;
3036 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3037 "[IQK] iqk->is_iqk_init = %x\n", iqk->is_iqk_init);
3038 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3039 "[IQK] iqk->is_reload = %x\n", iqk->is_reload);
3040 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3041 "[IQK] iqk->is_nbiqk = %x\n", iqk->is_nbiqk);
3042 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3043 "[IQK] iqk->txiqk_en = %x\n", iqk->txiqk_en);
3044 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3045 "[IQK] iqk->rxiqk_en = %x\n", iqk->rxiqk_en);
3046 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3047 "[IQK] iqk->lok_en = %x\n", iqk->lok_en);
3048 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3049 "[IQK] iqk->iqk_xym_en = %x\n", iqk->iqk_xym_en);
3050 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3051 "[IQK] iqk->iqk_sram_en = %x\n", iqk->iqk_sram_en);
3052 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3053 "[IQK] iqk->iqk_fft_en = %x\n", iqk->iqk_fft_en);
3054 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3055 "[IQK] iqk->is_fw_iqk = %x\n", iqk->is_fw_iqk);
3056 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3057 "[IQK] iqk->is_iqk_enable = %x\n", iqk->is_iqk_enable);
3058 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3059 "[IQK] iqk->iqk_cfir_en = %x\n", iqk->iqk_cfir_en);
3060 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3061 "[IQK] iqk->thermal_rek_en = %x\n", iqk->thermal_rek_en);
3062 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3063 "[IQK] iqk->version = %x\n", iqk->version);
3064 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3065 "[IQK] iqk->phy = %x\n", iqk->phy);
3066 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3067 "[IQK] iqk->fwk_status = %x\n", iqk->fwk_status);
3068
3069 for (i = 0; i < 2; i++) {
3070 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3071 "[IQK] ======== Path %x ========\n", i);
3072 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->iqk_band[%d] = %x\n",
3073 i, iqk->iqk_band[i]);
3074 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->iqk_ch[%d] = %x\n",
3075 i, iqk->iqk_ch[i]);
3076 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->iqk_bw[%d] = %x\n",
3077 i, iqk->iqk_bw[i]);
3078 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->lok_idac[%d] = %x\n",
3079 i, le32_to_cpu(iqk->lok_idac[i]));
3080 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->lok_vbuf[%d] = %x\n",
3081 i, le32_to_cpu(iqk->lok_vbuf[i]));
3082 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->iqk_tx_fail[%d] = %x\n",
3083 i, iqk->iqk_tx_fail[i]);
3084 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->iqk_rx_fail[%d] = %x\n",
3085 i, iqk->iqk_rx_fail[i]);
3086 for (j = 0; j < 4; j++)
3087 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3088 "[IQK] iqk->rftxgain[%d][%d] = %x\n",
3089 i, j, le32_to_cpu(iqk->rftxgain[i][j]));
3090 for (j = 0; j < 4; j++)
3091 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3092 "[IQK] iqk->tx_xym[%d][%d] = %x\n",
3093 i, j, le32_to_cpu(iqk->tx_xym[i][j]));
3094 for (j = 0; j < 4; j++)
3095 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3096 "[IQK] iqk->rfrxgain[%d][%d] = %x\n",
3097 i, j, le32_to_cpu(iqk->rfrxgain[i][j]));
3098 for (j = 0; j < 4; j++)
3099 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3100 "[IQK] iqk->rx_xym[%d][%d] = %x\n",
3101 i, j, le32_to_cpu(iqk->rx_xym[i][j]));
3102 }
3103 return;
3104 case RTW89_PHY_C2H_RFK_LOG_FUNC_DPK:
3105 if (len != sizeof(*dpk))
3106 goto out;
3107
3108 dpk = content;
3109 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3110 "DPK ver:%d idx:%2ph band:%2ph bw:%2ph ch:%2ph path:%2ph\n",
3111 dpk->ver, dpk->idx, dpk->band, dpk->bw, dpk->ch, dpk->path_ok);
3112 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3113 "DPK txagc:%2ph ther:%2ph gs:%2ph dc_i:%4ph dc_q:%4ph\n",
3114 dpk->txagc, dpk->ther, dpk->gs, dpk->dc_i, dpk->dc_q);
3115 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3116 "DPK corr_v:%2ph corr_i:%2ph to:%2ph ov:%2ph\n",
3117 dpk->corr_val, dpk->corr_idx, dpk->is_timeout, dpk->rxbb_ov);
3118 return;
3119 case RTW89_PHY_C2H_RFK_LOG_FUNC_DACK:
3120 if (len != sizeof(*dack))
3121 goto out;
3122
3123 dack = content;
3124
3125 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]FWDACK SUMMARY!!!!!\n");
3126 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3127 "[DACK]FWDACK ver = 0x%x, FWDACK rpt_ver = 0x%x, driver rpt_ver = 0x%x\n",
3128 dack->fwdack_ver, dack->fwdack_info_ver, 0x2);
3129
3130 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3131 "[DACK]timeout code = [0x%x 0x%x 0x%x 0x%x 0x%x]\n",
3132 dack->addck_timeout, dack->cdack_timeout, dack->dadck_timeout,
3133 dack->adgaink_timeout, dack->msbk_timeout);
3134 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3135 "[DACK]DACK fail = 0x%x\n", dack->dack_fail);
3136 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3137 "[DACK]S0 WBADCK = [0x%x]\n", dack->wbdck_d[0]);
3138 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3139 "[DACK]S1 WBADCK = [0x%x]\n", dack->wbdck_d[1]);
3140 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3141 "[DACK]DRCK = [0x%x]\n", dack->rck_d);
3142 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 CDACK ic = [0x%x, 0x%x]\n",
3143 dack->cdack_d[0][0][0], dack->cdack_d[0][0][1]);
3144 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 CDACK qc = [0x%x, 0x%x]\n",
3145 dack->cdack_d[0][1][0], dack->cdack_d[0][1][1]);
3146 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 CDACK ic = [0x%x, 0x%x]\n",
3147 dack->cdack_d[1][0][0], dack->cdack_d[1][0][1]);
3148 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 CDACK qc = [0x%x, 0x%x]\n",
3149 dack->cdack_d[1][1][0], dack->cdack_d[1][1][1]);
3150
3151 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 ADC_DCK ic = [0x%x, 0x%x]\n",
3152 ((u32)dack->addck2_hd[0][0][0] << 8) | dack->addck2_ld[0][0][0],
3153 ((u32)dack->addck2_hd[0][0][1] << 8) | dack->addck2_ld[0][0][1]);
3154 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 ADC_DCK qc = [0x%x, 0x%x]\n",
3155 ((u32)dack->addck2_hd[0][1][0] << 8) | dack->addck2_ld[0][1][0],
3156 ((u32)dack->addck2_hd[0][1][1] << 8) | dack->addck2_ld[0][1][1]);
3157 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 ADC_DCK ic = [0x%x, 0x%x]\n",
3158 ((u32)dack->addck2_hd[1][0][0] << 8) | dack->addck2_ld[1][0][0],
3159 ((u32)dack->addck2_hd[1][0][1] << 8) | dack->addck2_ld[1][0][1]);
3160 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 ADC_DCK qc = [0x%x, 0x%x]\n",
3161 ((u32)dack->addck2_hd[1][1][0] << 8) | dack->addck2_ld[1][1][0],
3162 ((u32)dack->addck2_hd[1][1][1] << 8) | dack->addck2_ld[1][1][1]);
3163
3164 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 ADC_GAINK ic = 0x%x, qc = 0x%x\n",
3165 dack->adgaink_d[0][0], dack->adgaink_d[0][1]);
3166 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 ADC_GAINK ic = 0x%x, qc = 0x%x\n",
3167 dack->adgaink_d[1][0], dack->adgaink_d[1][1]);
3168
3169 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 DAC_DCK ic = 0x%x, qc = 0x%x\n",
3170 dack->dadck_d[0][0], dack->dadck_d[0][1]);
3171 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 DAC_DCK ic = 0x%x, qc = 0x%x\n",
3172 dack->dadck_d[1][0], dack->dadck_d[1][1]);
3173
3174 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 biask iqc = 0x%x\n",
3175 ((u32)dack->biask_hd[0][0] << 8) | dack->biask_ld[0][0]);
3176 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 biask iqc = 0x%x\n",
3177 ((u32)dack->biask_hd[1][0] << 8) | dack->biask_ld[1][0]);
3178
3179 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK ic:\n");
3180 for (i = 0; i < 0x10; i++)
3181 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n",
3182 dack->msbk_d[0][0][i]);
3183
3184 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK qc:\n");
3185 for (i = 0; i < 0x10; i++)
3186 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n",
3187 dack->msbk_d[0][1][i]);
3188
3189 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 MSBK ic:\n");
3190 for (i = 0; i < 0x10; i++)
3191 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n",
3192 dack->msbk_d[1][0][i]);
3193
3194 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 MSBK qc:\n");
3195 for (i = 0; i < 0x10; i++)
3196 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n",
3197 dack->msbk_d[1][1][i]);
3198 return;
3199 case RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK:
3200 if (len != sizeof(*rxdck))
3201 goto out;
3202
3203 rxdck = content;
3204 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3205 "RXDCK ver:%d band:%2ph bw:%2ph ch:%2ph to:%2ph\n",
3206 rxdck->ver, rxdck->band, rxdck->bw, rxdck->ch,
3207 rxdck->timeout);
3208 return;
3209 case RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI:
3210 if (len != sizeof(*tssi))
3211 goto out;
3212
3213 tssi = content;
3214 for (i = 0; i < 2; i++) {
3215 for (j = 0; j < 2; j++) {
3216 for (k = 0; k < 4; k++) {
3217 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3218 "[TSSI] alignment_power_cw_h[%d][%d][%d]=%d\n",
3219 i, j, k, tssi->alignment_power_cw_h[i][j][k]);
3220 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3221 "[TSSI] alignment_power_cw_l[%d][%d][%d]=%d\n",
3222 i, j, k, tssi->alignment_power_cw_l[i][j][k]);
3223 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3224 "[TSSI] alignment_power[%d][%d][%d]=%d\n",
3225 i, j, k, tssi->alignment_power[i][j][k]);
3226 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3227 "[TSSI] alignment_power_cw[%d][%d][%d]=%d\n",
3228 i, j, k,
3229 (tssi->alignment_power_cw_h[i][j][k] << 8) +
3230 tssi->alignment_power_cw_l[i][j][k]);
3231 }
3232
3233 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3234 "[TSSI] tssi_alimk_state[%d][%d]=%d\n",
3235 i, j, tssi->tssi_alimk_state[i][j]);
3236 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3237 "[TSSI] default_txagc_offset[%d]=%d\n",
3238 j, tssi->default_txagc_offset[0][j]);
3239 }
3240 }
3241 return;
3242 case RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK:
3243 if (len != sizeof(*txgapk))
3244 goto out;
3245
3246 txgapk = content;
3247 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3248 "[TXGAPK]rpt r0x8010[0]=0x%x, r0x8010[1]=0x%x\n",
3249 le32_to_cpu(txgapk->r0x8010[0]),
3250 le32_to_cpu(txgapk->r0x8010[1]));
3251 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt chk_id = %d\n",
3252 txgapk->chk_id);
3253 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt chk_cnt = %d\n",
3254 le32_to_cpu(txgapk->chk_cnt));
3255 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt ver = 0x%x\n",
3256 txgapk->ver);
3257 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt rsv1 = %d\n",
3258 txgapk->rsv1);
3259
3260 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt track_d[0] = %*ph\n",
3261 (int)sizeof(txgapk->track_d[0]), txgapk->track_d[0]);
3262 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt power_d[0] = %*ph\n",
3263 (int)sizeof(txgapk->power_d[0]), txgapk->power_d[0]);
3264 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt track_d[1] = %*ph\n",
3265 (int)sizeof(txgapk->track_d[1]), txgapk->track_d[1]);
3266 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt power_d[1] = %*ph\n",
3267 (int)sizeof(txgapk->power_d[1]), txgapk->power_d[1]);
3268 return;
3269 default:
3270 break;
3271 }
3272
3273 out:
3274 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3275 "unexpected RFK func %d report log with length %d\n", func, len);
3276 }
3277
rtw89_phy_c2h_rfk_run_log(struct rtw89_dev * rtwdev,enum rtw89_phy_c2h_rfk_log_func func,void * content,u16 len)3278 static bool rtw89_phy_c2h_rfk_run_log(struct rtw89_dev *rtwdev,
3279 enum rtw89_phy_c2h_rfk_log_func func,
3280 void *content, u16 len)
3281 {
3282 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info;
3283 const struct rtw89_c2h_rf_run_log *log = content;
3284 const struct rtw89_fw_element_hdr *elm;
3285 u32 fmt_idx;
3286 u16 offset;
3287
3288 if (sizeof(*log) != len)
3289 return false;
3290
3291 if (!elm_info->rfk_log_fmt)
3292 return false;
3293
3294 elm = elm_info->rfk_log_fmt->elm[func];
3295 fmt_idx = le32_to_cpu(log->fmt_idx);
3296 if (!elm || fmt_idx >= elm->u.rfk_log_fmt.nr)
3297 return false;
3298
3299 offset = le16_to_cpu(elm->u.rfk_log_fmt.offset[fmt_idx]);
3300 if (offset == 0)
3301 return false;
3302
3303 rtw89_debug(rtwdev, RTW89_DBG_RFK, &elm->u.common.contents[offset],
3304 le32_to_cpu(log->arg[0]), le32_to_cpu(log->arg[1]),
3305 le32_to_cpu(log->arg[2]), le32_to_cpu(log->arg[3]));
3306
3307 return true;
3308 }
3309
rtw89_phy_c2h_rfk_log(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len,enum rtw89_phy_c2h_rfk_log_func func,const char * rfk_name)3310 static void rtw89_phy_c2h_rfk_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h,
3311 u32 len, enum rtw89_phy_c2h_rfk_log_func func,
3312 const char *rfk_name)
3313 {
3314 struct rtw89_c2h_hdr *c2h_hdr = (struct rtw89_c2h_hdr *)c2h->data;
3315 struct rtw89_c2h_rf_log_hdr *log_hdr;
3316 void *log_ptr = c2h_hdr;
3317 u16 content_len;
3318 u16 chunk_len;
3319 bool handled;
3320
3321 if (!rtw89_debug_is_enabled(rtwdev, RTW89_DBG_RFK))
3322 return;
3323
3324 log_ptr += sizeof(*c2h_hdr);
3325 len -= sizeof(*c2h_hdr);
3326
3327 while (len > sizeof(*log_hdr)) {
3328 log_hdr = log_ptr;
3329 content_len = le16_to_cpu(log_hdr->len);
3330 chunk_len = content_len + sizeof(*log_hdr);
3331
3332 if (chunk_len > len)
3333 break;
3334
3335 switch (log_hdr->type) {
3336 case RTW89_RF_RUN_LOG:
3337 handled = rtw89_phy_c2h_rfk_run_log(rtwdev, func,
3338 log_hdr->content, content_len);
3339 if (handled)
3340 break;
3341
3342 rtw89_debug(rtwdev, RTW89_DBG_RFK, "%s run: %*ph\n",
3343 rfk_name, content_len, log_hdr->content);
3344 break;
3345 case RTW89_RF_RPT_LOG:
3346 rtw89_phy_c2h_rfk_rpt_log(rtwdev, func,
3347 log_hdr->content, content_len);
3348 break;
3349 default:
3350 return;
3351 }
3352
3353 log_ptr += chunk_len;
3354 len -= chunk_len;
3355 }
3356 }
3357
3358 static void
rtw89_phy_c2h_rfk_log_iqk(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3359 rtw89_phy_c2h_rfk_log_iqk(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3360 {
3361 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len,
3362 RTW89_PHY_C2H_RFK_LOG_FUNC_IQK, "IQK");
3363 }
3364
3365 static void
rtw89_phy_c2h_rfk_log_dpk(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3366 rtw89_phy_c2h_rfk_log_dpk(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3367 {
3368 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len,
3369 RTW89_PHY_C2H_RFK_LOG_FUNC_DPK, "DPK");
3370 }
3371
3372 static void
rtw89_phy_c2h_rfk_log_dack(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3373 rtw89_phy_c2h_rfk_log_dack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3374 {
3375 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len,
3376 RTW89_PHY_C2H_RFK_LOG_FUNC_DACK, "DACK");
3377 }
3378
3379 static void
rtw89_phy_c2h_rfk_log_rxdck(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3380 rtw89_phy_c2h_rfk_log_rxdck(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3381 {
3382 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len,
3383 RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK, "RX_DCK");
3384 }
3385
3386 static void
rtw89_phy_c2h_rfk_log_tssi(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3387 rtw89_phy_c2h_rfk_log_tssi(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3388 {
3389 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len,
3390 RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI, "TSSI");
3391 }
3392
3393 static void
rtw89_phy_c2h_rfk_log_txgapk(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3394 rtw89_phy_c2h_rfk_log_txgapk(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3395 {
3396 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len,
3397 RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK, "TXGAPK");
3398 }
3399
3400 static
3401 void (* const rtw89_phy_c2h_rfk_log_handler[])(struct rtw89_dev *rtwdev,
3402 struct sk_buff *c2h, u32 len) = {
3403 [RTW89_PHY_C2H_RFK_LOG_FUNC_IQK] = rtw89_phy_c2h_rfk_log_iqk,
3404 [RTW89_PHY_C2H_RFK_LOG_FUNC_DPK] = rtw89_phy_c2h_rfk_log_dpk,
3405 [RTW89_PHY_C2H_RFK_LOG_FUNC_DACK] = rtw89_phy_c2h_rfk_log_dack,
3406 [RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK] = rtw89_phy_c2h_rfk_log_rxdck,
3407 [RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI] = rtw89_phy_c2h_rfk_log_tssi,
3408 [RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK] = rtw89_phy_c2h_rfk_log_txgapk,
3409 };
3410
3411 static
rtw89_phy_rfk_report_prep(struct rtw89_dev * rtwdev)3412 void rtw89_phy_rfk_report_prep(struct rtw89_dev *rtwdev)
3413 {
3414 struct rtw89_rfk_wait_info *wait = &rtwdev->rfk_wait;
3415
3416 wait->state = RTW89_RFK_STATE_START;
3417 wait->start_time = ktime_get();
3418 reinit_completion(&wait->completion);
3419 }
3420
3421 static
rtw89_phy_rfk_report_wait(struct rtw89_dev * rtwdev,const char * rfk_name,unsigned int ms)3422 int rtw89_phy_rfk_report_wait(struct rtw89_dev *rtwdev, const char *rfk_name,
3423 unsigned int ms)
3424 {
3425 struct rtw89_rfk_wait_info *wait = &rtwdev->rfk_wait;
3426 unsigned long time_left;
3427
3428 /* Since we can't receive C2H event during SER, use a fixed delay. */
3429 if (test_bit(RTW89_FLAG_SER_HANDLING, rtwdev->flags)) {
3430 fsleep(1000 * ms / 2);
3431 goto out;
3432 }
3433
3434 time_left = wait_for_completion_timeout(&wait->completion,
3435 msecs_to_jiffies(ms));
3436 if (time_left == 0) {
3437 rtw89_warn(rtwdev, "failed to wait RF %s\n", rfk_name);
3438 return -ETIMEDOUT;
3439 } else if (wait->state != RTW89_RFK_STATE_OK) {
3440 rtw89_warn(rtwdev, "failed to do RF %s result from state %d\n",
3441 rfk_name, wait->state);
3442 return -EFAULT;
3443 }
3444
3445 out:
3446 rtw89_debug(rtwdev, RTW89_DBG_RFK, "RF %s takes %lld ms to complete\n",
3447 rfk_name, ktime_ms_delta(ktime_get(), wait->start_time));
3448
3449 return 0;
3450 }
3451
3452 static void
rtw89_phy_c2h_rfk_report_state(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3453 rtw89_phy_c2h_rfk_report_state(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3454 {
3455 const struct rtw89_c2h_rfk_report *report =
3456 (const struct rtw89_c2h_rfk_report *)c2h->data;
3457 struct rtw89_rfk_wait_info *wait = &rtwdev->rfk_wait;
3458
3459 wait->state = report->state;
3460 wait->version = report->version;
3461
3462 complete(&wait->completion);
3463
3464 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3465 "RFK report state %d with version %d (%*ph)\n",
3466 wait->state, wait->version,
3467 (int)(len - sizeof(report->hdr)), &report->state);
3468 }
3469
3470 static void
rtw89_phy_c2h_rfk_log_tas_pwr(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3471 rtw89_phy_c2h_rfk_log_tas_pwr(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3472 {
3473 const struct rtw89_c2h_rf_tas_info *rf_tas =
3474 (const struct rtw89_c2h_rf_tas_info *)c2h->data;
3475 const enum rtw89_sar_sources src = rtwdev->sar.src;
3476 struct rtw89_tas_info *tas = &rtwdev->tas;
3477 u64 linear = 0;
3478 u32 i, cur_idx;
3479 s16 txpwr;
3480
3481 if (!tas->enable || src == RTW89_SAR_SOURCE_NONE)
3482 return;
3483
3484 cur_idx = le32_to_cpu(rf_tas->cur_idx);
3485 for (i = 0; i < cur_idx; i++) {
3486 txpwr = (s16)le16_to_cpu(rf_tas->txpwr_history[i]);
3487 linear += rtw89_db_quarter_to_linear(txpwr);
3488
3489 rtw89_debug(rtwdev, RTW89_DBG_SAR,
3490 "tas: index: %u, txpwr: %d\n", i, txpwr);
3491 }
3492
3493 if (cur_idx == 0)
3494 tas->instant_txpwr = rtw89_db_to_linear(0);
3495 else
3496 tas->instant_txpwr = DIV_ROUND_DOWN_ULL(linear, cur_idx);
3497 }
3498
3499 static
3500 void (* const rtw89_phy_c2h_rfk_report_handler[])(struct rtw89_dev *rtwdev,
3501 struct sk_buff *c2h, u32 len) = {
3502 [RTW89_PHY_C2H_RFK_REPORT_FUNC_STATE] = rtw89_phy_c2h_rfk_report_state,
3503 [RTW89_PHY_C2H_RFK_LOG_TAS_PWR] = rtw89_phy_c2h_rfk_log_tas_pwr,
3504 };
3505
rtw89_phy_c2h_chk_atomic(struct rtw89_dev * rtwdev,u8 class,u8 func)3506 bool rtw89_phy_c2h_chk_atomic(struct rtw89_dev *rtwdev, u8 class, u8 func)
3507 {
3508 switch (class) {
3509 case RTW89_PHY_C2H_RFK_LOG:
3510 switch (func) {
3511 case RTW89_PHY_C2H_RFK_LOG_FUNC_IQK:
3512 case RTW89_PHY_C2H_RFK_LOG_FUNC_DPK:
3513 case RTW89_PHY_C2H_RFK_LOG_FUNC_DACK:
3514 case RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK:
3515 case RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI:
3516 case RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK:
3517 return true;
3518 default:
3519 return false;
3520 }
3521 case RTW89_PHY_C2H_RFK_REPORT:
3522 switch (func) {
3523 case RTW89_PHY_C2H_RFK_REPORT_FUNC_STATE:
3524 return true;
3525 default:
3526 return false;
3527 }
3528 default:
3529 return false;
3530 }
3531 }
3532
rtw89_phy_c2h_handle(struct rtw89_dev * rtwdev,struct sk_buff * skb,u32 len,u8 class,u8 func)3533 void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb,
3534 u32 len, u8 class, u8 func)
3535 {
3536 void (*handler)(struct rtw89_dev *rtwdev,
3537 struct sk_buff *c2h, u32 len) = NULL;
3538
3539 switch (class) {
3540 case RTW89_PHY_C2H_CLASS_RA:
3541 if (func < RTW89_PHY_C2H_FUNC_RA_MAX)
3542 handler = rtw89_phy_c2h_ra_handler[func];
3543 break;
3544 case RTW89_PHY_C2H_RFK_LOG:
3545 if (func < ARRAY_SIZE(rtw89_phy_c2h_rfk_log_handler))
3546 handler = rtw89_phy_c2h_rfk_log_handler[func];
3547 break;
3548 case RTW89_PHY_C2H_RFK_REPORT:
3549 if (func < ARRAY_SIZE(rtw89_phy_c2h_rfk_report_handler))
3550 handler = rtw89_phy_c2h_rfk_report_handler[func];
3551 break;
3552 case RTW89_PHY_C2H_CLASS_DM:
3553 if (func == RTW89_PHY_C2H_DM_FUNC_LOWRT_RTY)
3554 return;
3555 fallthrough;
3556 default:
3557 rtw89_info(rtwdev, "PHY c2h class %d not support\n", class);
3558 return;
3559 }
3560 if (!handler) {
3561 rtw89_info(rtwdev, "PHY c2h class %d func %d not support\n", class,
3562 func);
3563 return;
3564 }
3565 handler(rtwdev, skb, len);
3566 }
3567
rtw89_phy_rfk_pre_ntfy_and_wait(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,unsigned int ms)3568 int rtw89_phy_rfk_pre_ntfy_and_wait(struct rtw89_dev *rtwdev,
3569 enum rtw89_phy_idx phy_idx,
3570 unsigned int ms)
3571 {
3572 int ret;
3573
3574 rtw89_phy_rfk_report_prep(rtwdev);
3575
3576 ret = rtw89_fw_h2c_rf_pre_ntfy(rtwdev, phy_idx);
3577 if (ret)
3578 return ret;
3579
3580 return rtw89_phy_rfk_report_wait(rtwdev, "PRE_NTFY", ms);
3581 }
3582 EXPORT_SYMBOL(rtw89_phy_rfk_pre_ntfy_and_wait);
3583
rtw89_phy_rfk_tssi_and_wait(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan,enum rtw89_tssi_mode tssi_mode,unsigned int ms)3584 int rtw89_phy_rfk_tssi_and_wait(struct rtw89_dev *rtwdev,
3585 enum rtw89_phy_idx phy_idx,
3586 const struct rtw89_chan *chan,
3587 enum rtw89_tssi_mode tssi_mode,
3588 unsigned int ms)
3589 {
3590 int ret;
3591
3592 rtw89_phy_rfk_report_prep(rtwdev);
3593
3594 ret = rtw89_fw_h2c_rf_tssi(rtwdev, phy_idx, chan, tssi_mode);
3595 if (ret)
3596 return ret;
3597
3598 return rtw89_phy_rfk_report_wait(rtwdev, "TSSI", ms);
3599 }
3600 EXPORT_SYMBOL(rtw89_phy_rfk_tssi_and_wait);
3601
rtw89_phy_rfk_iqk_and_wait(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan,unsigned int ms)3602 int rtw89_phy_rfk_iqk_and_wait(struct rtw89_dev *rtwdev,
3603 enum rtw89_phy_idx phy_idx,
3604 const struct rtw89_chan *chan,
3605 unsigned int ms)
3606 {
3607 int ret;
3608
3609 rtw89_phy_rfk_report_prep(rtwdev);
3610
3611 ret = rtw89_fw_h2c_rf_iqk(rtwdev, phy_idx, chan);
3612 if (ret)
3613 return ret;
3614
3615 return rtw89_phy_rfk_report_wait(rtwdev, "IQK", ms);
3616 }
3617 EXPORT_SYMBOL(rtw89_phy_rfk_iqk_and_wait);
3618
rtw89_phy_rfk_dpk_and_wait(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan,unsigned int ms)3619 int rtw89_phy_rfk_dpk_and_wait(struct rtw89_dev *rtwdev,
3620 enum rtw89_phy_idx phy_idx,
3621 const struct rtw89_chan *chan,
3622 unsigned int ms)
3623 {
3624 int ret;
3625
3626 rtw89_phy_rfk_report_prep(rtwdev);
3627
3628 ret = rtw89_fw_h2c_rf_dpk(rtwdev, phy_idx, chan);
3629 if (ret)
3630 return ret;
3631
3632 return rtw89_phy_rfk_report_wait(rtwdev, "DPK", ms);
3633 }
3634 EXPORT_SYMBOL(rtw89_phy_rfk_dpk_and_wait);
3635
rtw89_phy_rfk_txgapk_and_wait(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan,unsigned int ms)3636 int rtw89_phy_rfk_txgapk_and_wait(struct rtw89_dev *rtwdev,
3637 enum rtw89_phy_idx phy_idx,
3638 const struct rtw89_chan *chan,
3639 unsigned int ms)
3640 {
3641 int ret;
3642
3643 rtw89_phy_rfk_report_prep(rtwdev);
3644
3645 ret = rtw89_fw_h2c_rf_txgapk(rtwdev, phy_idx, chan);
3646 if (ret)
3647 return ret;
3648
3649 return rtw89_phy_rfk_report_wait(rtwdev, "TXGAPK", ms);
3650 }
3651 EXPORT_SYMBOL(rtw89_phy_rfk_txgapk_and_wait);
3652
rtw89_phy_rfk_dack_and_wait(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan,unsigned int ms)3653 int rtw89_phy_rfk_dack_and_wait(struct rtw89_dev *rtwdev,
3654 enum rtw89_phy_idx phy_idx,
3655 const struct rtw89_chan *chan,
3656 unsigned int ms)
3657 {
3658 int ret;
3659
3660 rtw89_phy_rfk_report_prep(rtwdev);
3661
3662 ret = rtw89_fw_h2c_rf_dack(rtwdev, phy_idx, chan);
3663 if (ret)
3664 return ret;
3665
3666 return rtw89_phy_rfk_report_wait(rtwdev, "DACK", ms);
3667 }
3668 EXPORT_SYMBOL(rtw89_phy_rfk_dack_and_wait);
3669
rtw89_phy_rfk_rxdck_and_wait(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan,bool is_chl_k,unsigned int ms)3670 int rtw89_phy_rfk_rxdck_and_wait(struct rtw89_dev *rtwdev,
3671 enum rtw89_phy_idx phy_idx,
3672 const struct rtw89_chan *chan,
3673 bool is_chl_k, unsigned int ms)
3674 {
3675 int ret;
3676
3677 rtw89_phy_rfk_report_prep(rtwdev);
3678
3679 ret = rtw89_fw_h2c_rf_rxdck(rtwdev, phy_idx, chan, is_chl_k);
3680 if (ret)
3681 return ret;
3682
3683 return rtw89_phy_rfk_report_wait(rtwdev, "RX_DCK", ms);
3684 }
3685 EXPORT_SYMBOL(rtw89_phy_rfk_rxdck_and_wait);
3686
phy_tssi_get_cck_group(u8 ch)3687 static u32 phy_tssi_get_cck_group(u8 ch)
3688 {
3689 switch (ch) {
3690 case 1 ... 2:
3691 return 0;
3692 case 3 ... 5:
3693 return 1;
3694 case 6 ... 8:
3695 return 2;
3696 case 9 ... 11:
3697 return 3;
3698 case 12 ... 13:
3699 return 4;
3700 case 14:
3701 return 5;
3702 }
3703
3704 return 0;
3705 }
3706
3707 #define PHY_TSSI_EXTRA_GROUP_BIT BIT(31)
3708 #define PHY_TSSI_EXTRA_GROUP(idx) (PHY_TSSI_EXTRA_GROUP_BIT | (idx))
3709 #define PHY_IS_TSSI_EXTRA_GROUP(group) ((group) & PHY_TSSI_EXTRA_GROUP_BIT)
3710 #define PHY_TSSI_EXTRA_GET_GROUP_IDX1(group) \
3711 ((group) & ~PHY_TSSI_EXTRA_GROUP_BIT)
3712 #define PHY_TSSI_EXTRA_GET_GROUP_IDX2(group) \
3713 (PHY_TSSI_EXTRA_GET_GROUP_IDX1(group) + 1)
3714
phy_tssi_get_ofdm_group(u8 ch)3715 static u32 phy_tssi_get_ofdm_group(u8 ch)
3716 {
3717 switch (ch) {
3718 case 1 ... 2:
3719 return 0;
3720 case 3 ... 5:
3721 return 1;
3722 case 6 ... 8:
3723 return 2;
3724 case 9 ... 11:
3725 return 3;
3726 case 12 ... 14:
3727 return 4;
3728 case 36 ... 40:
3729 return 5;
3730 case 41 ... 43:
3731 return PHY_TSSI_EXTRA_GROUP(5);
3732 case 44 ... 48:
3733 return 6;
3734 case 49 ... 51:
3735 return PHY_TSSI_EXTRA_GROUP(6);
3736 case 52 ... 56:
3737 return 7;
3738 case 57 ... 59:
3739 return PHY_TSSI_EXTRA_GROUP(7);
3740 case 60 ... 64:
3741 return 8;
3742 case 100 ... 104:
3743 return 9;
3744 case 105 ... 107:
3745 return PHY_TSSI_EXTRA_GROUP(9);
3746 case 108 ... 112:
3747 return 10;
3748 case 113 ... 115:
3749 return PHY_TSSI_EXTRA_GROUP(10);
3750 case 116 ... 120:
3751 return 11;
3752 case 121 ... 123:
3753 return PHY_TSSI_EXTRA_GROUP(11);
3754 case 124 ... 128:
3755 return 12;
3756 case 129 ... 131:
3757 return PHY_TSSI_EXTRA_GROUP(12);
3758 case 132 ... 136:
3759 return 13;
3760 case 137 ... 139:
3761 return PHY_TSSI_EXTRA_GROUP(13);
3762 case 140 ... 144:
3763 return 14;
3764 case 149 ... 153:
3765 return 15;
3766 case 154 ... 156:
3767 return PHY_TSSI_EXTRA_GROUP(15);
3768 case 157 ... 161:
3769 return 16;
3770 case 162 ... 164:
3771 return PHY_TSSI_EXTRA_GROUP(16);
3772 case 165 ... 169:
3773 return 17;
3774 case 170 ... 172:
3775 return PHY_TSSI_EXTRA_GROUP(17);
3776 case 173 ... 177:
3777 return 18;
3778 }
3779
3780 return 0;
3781 }
3782
phy_tssi_get_6g_ofdm_group(u8 ch)3783 static u32 phy_tssi_get_6g_ofdm_group(u8 ch)
3784 {
3785 switch (ch) {
3786 case 1 ... 5:
3787 return 0;
3788 case 6 ... 8:
3789 return PHY_TSSI_EXTRA_GROUP(0);
3790 case 9 ... 13:
3791 return 1;
3792 case 14 ... 16:
3793 return PHY_TSSI_EXTRA_GROUP(1);
3794 case 17 ... 21:
3795 return 2;
3796 case 22 ... 24:
3797 return PHY_TSSI_EXTRA_GROUP(2);
3798 case 25 ... 29:
3799 return 3;
3800 case 33 ... 37:
3801 return 4;
3802 case 38 ... 40:
3803 return PHY_TSSI_EXTRA_GROUP(4);
3804 case 41 ... 45:
3805 return 5;
3806 case 46 ... 48:
3807 return PHY_TSSI_EXTRA_GROUP(5);
3808 case 49 ... 53:
3809 return 6;
3810 case 54 ... 56:
3811 return PHY_TSSI_EXTRA_GROUP(6);
3812 case 57 ... 61:
3813 return 7;
3814 case 65 ... 69:
3815 return 8;
3816 case 70 ... 72:
3817 return PHY_TSSI_EXTRA_GROUP(8);
3818 case 73 ... 77:
3819 return 9;
3820 case 78 ... 80:
3821 return PHY_TSSI_EXTRA_GROUP(9);
3822 case 81 ... 85:
3823 return 10;
3824 case 86 ... 88:
3825 return PHY_TSSI_EXTRA_GROUP(10);
3826 case 89 ... 93:
3827 return 11;
3828 case 97 ... 101:
3829 return 12;
3830 case 102 ... 104:
3831 return PHY_TSSI_EXTRA_GROUP(12);
3832 case 105 ... 109:
3833 return 13;
3834 case 110 ... 112:
3835 return PHY_TSSI_EXTRA_GROUP(13);
3836 case 113 ... 117:
3837 return 14;
3838 case 118 ... 120:
3839 return PHY_TSSI_EXTRA_GROUP(14);
3840 case 121 ... 125:
3841 return 15;
3842 case 129 ... 133:
3843 return 16;
3844 case 134 ... 136:
3845 return PHY_TSSI_EXTRA_GROUP(16);
3846 case 137 ... 141:
3847 return 17;
3848 case 142 ... 144:
3849 return PHY_TSSI_EXTRA_GROUP(17);
3850 case 145 ... 149:
3851 return 18;
3852 case 150 ... 152:
3853 return PHY_TSSI_EXTRA_GROUP(18);
3854 case 153 ... 157:
3855 return 19;
3856 case 161 ... 165:
3857 return 20;
3858 case 166 ... 168:
3859 return PHY_TSSI_EXTRA_GROUP(20);
3860 case 169 ... 173:
3861 return 21;
3862 case 174 ... 176:
3863 return PHY_TSSI_EXTRA_GROUP(21);
3864 case 177 ... 181:
3865 return 22;
3866 case 182 ... 184:
3867 return PHY_TSSI_EXTRA_GROUP(22);
3868 case 185 ... 189:
3869 return 23;
3870 case 193 ... 197:
3871 return 24;
3872 case 198 ... 200:
3873 return PHY_TSSI_EXTRA_GROUP(24);
3874 case 201 ... 205:
3875 return 25;
3876 case 206 ... 208:
3877 return PHY_TSSI_EXTRA_GROUP(25);
3878 case 209 ... 213:
3879 return 26;
3880 case 214 ... 216:
3881 return PHY_TSSI_EXTRA_GROUP(26);
3882 case 217 ... 221:
3883 return 27;
3884 case 225 ... 229:
3885 return 28;
3886 case 230 ... 232:
3887 return PHY_TSSI_EXTRA_GROUP(28);
3888 case 233 ... 237:
3889 return 29;
3890 case 238 ... 240:
3891 return PHY_TSSI_EXTRA_GROUP(29);
3892 case 241 ... 245:
3893 return 30;
3894 case 246 ... 248:
3895 return PHY_TSSI_EXTRA_GROUP(30);
3896 case 249 ... 253:
3897 return 31;
3898 }
3899
3900 return 0;
3901 }
3902
phy_tssi_get_trim_group(u8 ch)3903 static u32 phy_tssi_get_trim_group(u8 ch)
3904 {
3905 switch (ch) {
3906 case 1 ... 8:
3907 return 0;
3908 case 9 ... 14:
3909 return 1;
3910 case 36 ... 48:
3911 return 2;
3912 case 49 ... 51:
3913 return PHY_TSSI_EXTRA_GROUP(2);
3914 case 52 ... 64:
3915 return 3;
3916 case 100 ... 112:
3917 return 4;
3918 case 113 ... 115:
3919 return PHY_TSSI_EXTRA_GROUP(4);
3920 case 116 ... 128:
3921 return 5;
3922 case 132 ... 144:
3923 return 6;
3924 case 149 ... 177:
3925 return 7;
3926 }
3927
3928 return 0;
3929 }
3930
phy_tssi_get_6g_trim_group(u8 ch)3931 static u32 phy_tssi_get_6g_trim_group(u8 ch)
3932 {
3933 switch (ch) {
3934 case 1 ... 13:
3935 return 0;
3936 case 14 ... 16:
3937 return PHY_TSSI_EXTRA_GROUP(0);
3938 case 17 ... 29:
3939 return 1;
3940 case 33 ... 45:
3941 return 2;
3942 case 46 ... 48:
3943 return PHY_TSSI_EXTRA_GROUP(2);
3944 case 49 ... 61:
3945 return 3;
3946 case 65 ... 77:
3947 return 4;
3948 case 78 ... 80:
3949 return PHY_TSSI_EXTRA_GROUP(4);
3950 case 81 ... 93:
3951 return 5;
3952 case 97 ... 109:
3953 return 6;
3954 case 110 ... 112:
3955 return PHY_TSSI_EXTRA_GROUP(6);
3956 case 113 ... 125:
3957 return 7;
3958 case 129 ... 141:
3959 return 8;
3960 case 142 ... 144:
3961 return PHY_TSSI_EXTRA_GROUP(8);
3962 case 145 ... 157:
3963 return 9;
3964 case 161 ... 173:
3965 return 10;
3966 case 174 ... 176:
3967 return PHY_TSSI_EXTRA_GROUP(10);
3968 case 177 ... 189:
3969 return 11;
3970 case 193 ... 205:
3971 return 12;
3972 case 206 ... 208:
3973 return PHY_TSSI_EXTRA_GROUP(12);
3974 case 209 ... 221:
3975 return 13;
3976 case 225 ... 237:
3977 return 14;
3978 case 238 ... 240:
3979 return PHY_TSSI_EXTRA_GROUP(14);
3980 case 241 ... 253:
3981 return 15;
3982 }
3983
3984 return 0;
3985 }
3986
phy_tssi_get_ofdm_de(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,const struct rtw89_chan * chan,enum rtw89_rf_path path)3987 static s8 phy_tssi_get_ofdm_de(struct rtw89_dev *rtwdev,
3988 enum rtw89_phy_idx phy,
3989 const struct rtw89_chan *chan,
3990 enum rtw89_rf_path path)
3991 {
3992 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
3993 enum rtw89_band band = chan->band_type;
3994 u8 ch = chan->channel;
3995 u32 gidx_1st;
3996 u32 gidx_2nd;
3997 s8 de_1st;
3998 s8 de_2nd;
3999 u32 gidx;
4000 s8 val;
4001
4002 if (band == RTW89_BAND_6G)
4003 goto calc_6g;
4004
4005 gidx = phy_tssi_get_ofdm_group(ch);
4006
4007 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4008 "[TSSI][TRIM]: path=%d mcs group_idx=0x%x\n",
4009 path, gidx);
4010
4011 if (PHY_IS_TSSI_EXTRA_GROUP(gidx)) {
4012 gidx_1st = PHY_TSSI_EXTRA_GET_GROUP_IDX1(gidx);
4013 gidx_2nd = PHY_TSSI_EXTRA_GET_GROUP_IDX2(gidx);
4014 de_1st = tssi_info->tssi_mcs[path][gidx_1st];
4015 de_2nd = tssi_info->tssi_mcs[path][gidx_2nd];
4016 val = (de_1st + de_2nd) / 2;
4017
4018 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4019 "[TSSI][TRIM]: path=%d mcs de=%d 1st=%d 2nd=%d\n",
4020 path, val, de_1st, de_2nd);
4021 } else {
4022 val = tssi_info->tssi_mcs[path][gidx];
4023
4024 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4025 "[TSSI][TRIM]: path=%d mcs de=%d\n", path, val);
4026 }
4027
4028 return val;
4029
4030 calc_6g:
4031 gidx = phy_tssi_get_6g_ofdm_group(ch);
4032
4033 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4034 "[TSSI][TRIM]: path=%d mcs group_idx=0x%x\n",
4035 path, gidx);
4036
4037 if (PHY_IS_TSSI_EXTRA_GROUP(gidx)) {
4038 gidx_1st = PHY_TSSI_EXTRA_GET_GROUP_IDX1(gidx);
4039 gidx_2nd = PHY_TSSI_EXTRA_GET_GROUP_IDX2(gidx);
4040 de_1st = tssi_info->tssi_6g_mcs[path][gidx_1st];
4041 de_2nd = tssi_info->tssi_6g_mcs[path][gidx_2nd];
4042 val = (de_1st + de_2nd) / 2;
4043
4044 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4045 "[TSSI][TRIM]: path=%d mcs de=%d 1st=%d 2nd=%d\n",
4046 path, val, de_1st, de_2nd);
4047 } else {
4048 val = tssi_info->tssi_6g_mcs[path][gidx];
4049
4050 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4051 "[TSSI][TRIM]: path=%d mcs de=%d\n", path, val);
4052 }
4053
4054 return val;
4055 }
4056
phy_tssi_get_ofdm_trim_de(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,const struct rtw89_chan * chan,enum rtw89_rf_path path)4057 static s8 phy_tssi_get_ofdm_trim_de(struct rtw89_dev *rtwdev,
4058 enum rtw89_phy_idx phy,
4059 const struct rtw89_chan *chan,
4060 enum rtw89_rf_path path)
4061 {
4062 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
4063 enum rtw89_band band = chan->band_type;
4064 u8 ch = chan->channel;
4065 u32 tgidx_1st;
4066 u32 tgidx_2nd;
4067 s8 tde_1st;
4068 s8 tde_2nd;
4069 u32 tgidx;
4070 s8 val;
4071
4072 if (band == RTW89_BAND_6G)
4073 goto calc_6g;
4074
4075 tgidx = phy_tssi_get_trim_group(ch);
4076
4077 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4078 "[TSSI][TRIM]: path=%d mcs trim_group_idx=0x%x\n",
4079 path, tgidx);
4080
4081 if (PHY_IS_TSSI_EXTRA_GROUP(tgidx)) {
4082 tgidx_1st = PHY_TSSI_EXTRA_GET_GROUP_IDX1(tgidx);
4083 tgidx_2nd = PHY_TSSI_EXTRA_GET_GROUP_IDX2(tgidx);
4084 tde_1st = tssi_info->tssi_trim[path][tgidx_1st];
4085 tde_2nd = tssi_info->tssi_trim[path][tgidx_2nd];
4086 val = (tde_1st + tde_2nd) / 2;
4087
4088 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4089 "[TSSI][TRIM]: path=%d mcs trim_de=%d 1st=%d 2nd=%d\n",
4090 path, val, tde_1st, tde_2nd);
4091 } else {
4092 val = tssi_info->tssi_trim[path][tgidx];
4093
4094 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4095 "[TSSI][TRIM]: path=%d mcs trim_de=%d\n",
4096 path, val);
4097 }
4098
4099 return val;
4100
4101 calc_6g:
4102 tgidx = phy_tssi_get_6g_trim_group(ch);
4103
4104 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4105 "[TSSI][TRIM]: path=%d mcs trim_group_idx=0x%x\n",
4106 path, tgidx);
4107
4108 if (PHY_IS_TSSI_EXTRA_GROUP(tgidx)) {
4109 tgidx_1st = PHY_TSSI_EXTRA_GET_GROUP_IDX1(tgidx);
4110 tgidx_2nd = PHY_TSSI_EXTRA_GET_GROUP_IDX2(tgidx);
4111 tde_1st = tssi_info->tssi_trim_6g[path][tgidx_1st];
4112 tde_2nd = tssi_info->tssi_trim_6g[path][tgidx_2nd];
4113 val = (tde_1st + tde_2nd) / 2;
4114
4115 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4116 "[TSSI][TRIM]: path=%d mcs trim_de=%d 1st=%d 2nd=%d\n",
4117 path, val, tde_1st, tde_2nd);
4118 } else {
4119 val = tssi_info->tssi_trim_6g[path][tgidx];
4120
4121 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4122 "[TSSI][TRIM]: path=%d mcs trim_de=%d\n",
4123 path, val);
4124 }
4125
4126 return val;
4127 }
4128
rtw89_phy_rfk_tssi_fill_fwcmd_efuse_to_de(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,const struct rtw89_chan * chan,struct rtw89_h2c_rf_tssi * h2c)4129 void rtw89_phy_rfk_tssi_fill_fwcmd_efuse_to_de(struct rtw89_dev *rtwdev,
4130 enum rtw89_phy_idx phy,
4131 const struct rtw89_chan *chan,
4132 struct rtw89_h2c_rf_tssi *h2c)
4133 {
4134 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
4135 u8 ch = chan->channel;
4136 s8 trim_de;
4137 s8 ofdm_de;
4138 s8 cck_de;
4139 u8 gidx;
4140 s8 val;
4141 int i;
4142
4143 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "[TSSI][TRIM]: phy=%d ch=%d\n",
4144 phy, ch);
4145
4146 for (i = RF_PATH_A; i <= RF_PATH_B; i++) {
4147 trim_de = phy_tssi_get_ofdm_trim_de(rtwdev, phy, chan, i);
4148 h2c->curr_tssi_trim_de[i] = trim_de;
4149
4150 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4151 "[TSSI][TRIM]: path=%d trim_de=0x%x\n", i, trim_de);
4152
4153 gidx = phy_tssi_get_cck_group(ch);
4154 cck_de = tssi_info->tssi_cck[i][gidx];
4155 val = u32_get_bits(cck_de + trim_de, 0xff);
4156
4157 h2c->curr_tssi_cck_de[i] = 0x0;
4158 h2c->curr_tssi_cck_de_20m[i] = val;
4159 h2c->curr_tssi_cck_de_40m[i] = val;
4160 h2c->curr_tssi_efuse_cck_de[i] = cck_de;
4161
4162 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4163 "[TSSI][TRIM]: path=%d cck_de=0x%x\n", i, cck_de);
4164
4165 ofdm_de = phy_tssi_get_ofdm_de(rtwdev, phy, chan, i);
4166 val = u32_get_bits(ofdm_de + trim_de, 0xff);
4167
4168 h2c->curr_tssi_ofdm_de[i] = 0x0;
4169 h2c->curr_tssi_ofdm_de_20m[i] = val;
4170 h2c->curr_tssi_ofdm_de_40m[i] = val;
4171 h2c->curr_tssi_ofdm_de_80m[i] = val;
4172 h2c->curr_tssi_ofdm_de_160m[i] = val;
4173 h2c->curr_tssi_ofdm_de_320m[i] = val;
4174 h2c->curr_tssi_efuse_ofdm_de[i] = ofdm_de;
4175
4176 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4177 "[TSSI][TRIM]: path=%d ofdm_de=0x%x\n", i, ofdm_de);
4178 }
4179 }
4180
rtw89_phy_rfk_tssi_fill_fwcmd_tmeter_tbl(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,const struct rtw89_chan * chan,struct rtw89_h2c_rf_tssi * h2c)4181 void rtw89_phy_rfk_tssi_fill_fwcmd_tmeter_tbl(struct rtw89_dev *rtwdev,
4182 enum rtw89_phy_idx phy,
4183 const struct rtw89_chan *chan,
4184 struct rtw89_h2c_rf_tssi *h2c)
4185 {
4186 struct rtw89_fw_txpwr_track_cfg *trk = rtwdev->fw.elm_info.txpwr_trk;
4187 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
4188 const s8 *thm_up[RF_PATH_B + 1] = {};
4189 const s8 *thm_down[RF_PATH_B + 1] = {};
4190 u8 subband = chan->subband_type;
4191 s8 thm_ofst[128] = {0};
4192 u8 thermal;
4193 u8 path;
4194 u8 i, j;
4195
4196 switch (subband) {
4197 default:
4198 case RTW89_CH_2G:
4199 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GA_P][0];
4200 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GA_N][0];
4201 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GB_P][0];
4202 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GB_N][0];
4203 break;
4204 case RTW89_CH_5G_BAND_1:
4205 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P][0];
4206 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N][0];
4207 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_P][0];
4208 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_N][0];
4209 break;
4210 case RTW89_CH_5G_BAND_3:
4211 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P][1];
4212 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N][1];
4213 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_P][1];
4214 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_N][1];
4215 break;
4216 case RTW89_CH_5G_BAND_4:
4217 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P][2];
4218 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N][2];
4219 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_P][2];
4220 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_N][2];
4221 break;
4222 case RTW89_CH_6G_BAND_IDX0:
4223 case RTW89_CH_6G_BAND_IDX1:
4224 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][0];
4225 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][0];
4226 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][0];
4227 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][0];
4228 break;
4229 case RTW89_CH_6G_BAND_IDX2:
4230 case RTW89_CH_6G_BAND_IDX3:
4231 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][1];
4232 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][1];
4233 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][1];
4234 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][1];
4235 break;
4236 case RTW89_CH_6G_BAND_IDX4:
4237 case RTW89_CH_6G_BAND_IDX5:
4238 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][2];
4239 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][2];
4240 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][2];
4241 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][2];
4242 break;
4243 case RTW89_CH_6G_BAND_IDX6:
4244 case RTW89_CH_6G_BAND_IDX7:
4245 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][3];
4246 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][3];
4247 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][3];
4248 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][3];
4249 break;
4250 }
4251
4252 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4253 "[TSSI] tmeter tbl on subband: %u\n", subband);
4254
4255 for (path = RF_PATH_A; path <= RF_PATH_B; path++) {
4256 thermal = tssi_info->thermal[path];
4257 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4258 "path: %u, pg thermal: 0x%x\n", path, thermal);
4259
4260 if (thermal == 0xff) {
4261 h2c->pg_thermal[path] = 0x38;
4262 memset(h2c->ftable[path], 0, sizeof(h2c->ftable[path]));
4263 continue;
4264 }
4265
4266 h2c->pg_thermal[path] = thermal;
4267
4268 i = 0;
4269 for (j = 0; j < 64; j++)
4270 thm_ofst[j] = i < DELTA_SWINGIDX_SIZE ?
4271 thm_up[path][i++] :
4272 thm_up[path][DELTA_SWINGIDX_SIZE - 1];
4273
4274 i = 1;
4275 for (j = 127; j >= 64; j--)
4276 thm_ofst[j] = i < DELTA_SWINGIDX_SIZE ?
4277 -thm_down[path][i++] :
4278 -thm_down[path][DELTA_SWINGIDX_SIZE - 1];
4279
4280 for (i = 0; i < 128; i += 4) {
4281 h2c->ftable[path][i + 0] = thm_ofst[i + 3];
4282 h2c->ftable[path][i + 1] = thm_ofst[i + 2];
4283 h2c->ftable[path][i + 2] = thm_ofst[i + 1];
4284 h2c->ftable[path][i + 3] = thm_ofst[i + 0];
4285
4286 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4287 "thm ofst [%x]: %02x %02x %02x %02x\n",
4288 i, thm_ofst[i], thm_ofst[i + 1],
4289 thm_ofst[i + 2], thm_ofst[i + 3]);
4290 }
4291 }
4292 }
4293
rtw89_phy_cfo_get_xcap_reg(struct rtw89_dev * rtwdev,bool sc_xo)4294 static u8 rtw89_phy_cfo_get_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo)
4295 {
4296 const struct rtw89_xtal_info *xtal = rtwdev->chip->xtal_info;
4297 u32 reg_mask;
4298
4299 if (sc_xo)
4300 reg_mask = xtal->sc_xo_mask;
4301 else
4302 reg_mask = xtal->sc_xi_mask;
4303
4304 return (u8)rtw89_read32_mask(rtwdev, xtal->xcap_reg, reg_mask);
4305 }
4306
rtw89_phy_cfo_set_xcap_reg(struct rtw89_dev * rtwdev,bool sc_xo,u8 val)4307 static void rtw89_phy_cfo_set_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo,
4308 u8 val)
4309 {
4310 const struct rtw89_xtal_info *xtal = rtwdev->chip->xtal_info;
4311 u32 reg_mask;
4312
4313 if (sc_xo)
4314 reg_mask = xtal->sc_xo_mask;
4315 else
4316 reg_mask = xtal->sc_xi_mask;
4317
4318 rtw89_write32_mask(rtwdev, xtal->xcap_reg, reg_mask, val);
4319 }
4320
rtw89_phy_cfo_set_crystal_cap(struct rtw89_dev * rtwdev,u8 crystal_cap,bool force)4321 static void rtw89_phy_cfo_set_crystal_cap(struct rtw89_dev *rtwdev,
4322 u8 crystal_cap, bool force)
4323 {
4324 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4325 const struct rtw89_chip_info *chip = rtwdev->chip;
4326 u8 sc_xi_val, sc_xo_val;
4327
4328 if (!force && cfo->crystal_cap == crystal_cap)
4329 return;
4330 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8851B) {
4331 rtw89_phy_cfo_set_xcap_reg(rtwdev, true, crystal_cap);
4332 rtw89_phy_cfo_set_xcap_reg(rtwdev, false, crystal_cap);
4333 sc_xo_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, true);
4334 sc_xi_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, false);
4335 } else {
4336 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO,
4337 crystal_cap, XTAL_SC_XO_MASK);
4338 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI,
4339 crystal_cap, XTAL_SC_XI_MASK);
4340 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO, &sc_xo_val);
4341 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI, &sc_xi_val);
4342 }
4343 cfo->crystal_cap = sc_xi_val;
4344 cfo->x_cap_ofst = (s8)((int)cfo->crystal_cap - cfo->def_x_cap);
4345
4346 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xi=0x%x\n", sc_xi_val);
4347 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xo=0x%x\n", sc_xo_val);
4348 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Get xcap_ofst=%d\n",
4349 cfo->x_cap_ofst);
4350 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set xcap OK\n");
4351 }
4352
rtw89_phy_cfo_reset(struct rtw89_dev * rtwdev)4353 static void rtw89_phy_cfo_reset(struct rtw89_dev *rtwdev)
4354 {
4355 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4356 u8 cap;
4357
4358 cfo->def_x_cap = cfo->crystal_cap_default & B_AX_XTAL_SC_MASK;
4359 cfo->is_adjust = false;
4360 if (cfo->crystal_cap == cfo->def_x_cap)
4361 return;
4362 cap = cfo->crystal_cap;
4363 cap += (cap > cfo->def_x_cap ? -1 : 1);
4364 rtw89_phy_cfo_set_crystal_cap(rtwdev, cap, false);
4365 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4366 "(0x%x) approach to dflt_val=(0x%x)\n", cfo->crystal_cap,
4367 cfo->def_x_cap);
4368 }
4369
rtw89_dcfo_comp(struct rtw89_dev * rtwdev,s32 curr_cfo)4370 static void rtw89_dcfo_comp(struct rtw89_dev *rtwdev, s32 curr_cfo)
4371 {
4372 const struct rtw89_reg_def *dcfo_comp = rtwdev->chip->dcfo_comp;
4373 bool is_linked = rtwdev->total_sta_assoc > 0;
4374 s32 cfo_avg_312;
4375 s32 dcfo_comp_val;
4376 int sign;
4377
4378 if (rtwdev->chip->chip_id == RTL8922A)
4379 return;
4380
4381 if (!is_linked) {
4382 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: is_linked=%d\n",
4383 is_linked);
4384 return;
4385 }
4386 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: curr_cfo=%d\n", curr_cfo);
4387 if (curr_cfo == 0)
4388 return;
4389 dcfo_comp_val = rtw89_phy_read32_mask(rtwdev, R_DCFO, B_DCFO);
4390 sign = curr_cfo > 0 ? 1 : -1;
4391 cfo_avg_312 = curr_cfo / 625 + sign * dcfo_comp_val;
4392 rtw89_debug(rtwdev, RTW89_DBG_CFO, "avg_cfo_312=%d step\n", cfo_avg_312);
4393 if (rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV)
4394 cfo_avg_312 = -cfo_avg_312;
4395 rtw89_phy_set_phy_regs(rtwdev, dcfo_comp->addr, dcfo_comp->mask,
4396 cfo_avg_312);
4397 }
4398
rtw89_dcfo_comp_init(struct rtw89_dev * rtwdev)4399 static void rtw89_dcfo_comp_init(struct rtw89_dev *rtwdev)
4400 {
4401 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
4402 const struct rtw89_chip_info *chip = rtwdev->chip;
4403 const struct rtw89_cfo_regs *cfo = phy->cfo;
4404
4405 rtw89_phy_set_phy_regs(rtwdev, cfo->comp_seg0, cfo->valid_0_mask, 1);
4406 rtw89_phy_set_phy_regs(rtwdev, cfo->comp, cfo->weighting_mask, 8);
4407
4408 if (chip->chip_gen == RTW89_CHIP_AX) {
4409 if (chip->cfo_hw_comp) {
4410 rtw89_write32_mask(rtwdev, R_AX_PWR_UL_CTRL2,
4411 B_AX_PWR_UL_CFO_MASK, 0x6);
4412 } else {
4413 rtw89_phy_set_phy_regs(rtwdev, R_DCFO, B_DCFO, 1);
4414 rtw89_write32_clr(rtwdev, R_AX_PWR_UL_CTRL2,
4415 B_AX_PWR_UL_CFO_MASK);
4416 }
4417 }
4418 }
4419
rtw89_phy_cfo_init(struct rtw89_dev * rtwdev)4420 static void rtw89_phy_cfo_init(struct rtw89_dev *rtwdev)
4421 {
4422 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4423 struct rtw89_efuse *efuse = &rtwdev->efuse;
4424
4425 cfo->crystal_cap_default = efuse->xtal_cap & B_AX_XTAL_SC_MASK;
4426 cfo->crystal_cap = cfo->crystal_cap_default;
4427 cfo->def_x_cap = cfo->crystal_cap;
4428 cfo->x_cap_ub = min_t(int, cfo->def_x_cap + CFO_BOUND, 0x7f);
4429 cfo->x_cap_lb = max_t(int, cfo->def_x_cap - CFO_BOUND, 0x1);
4430 cfo->is_adjust = false;
4431 cfo->divergence_lock_en = false;
4432 cfo->x_cap_ofst = 0;
4433 cfo->lock_cnt = 0;
4434 cfo->rtw89_multi_cfo_mode = RTW89_TP_BASED_AVG_MODE;
4435 cfo->apply_compensation = false;
4436 cfo->residual_cfo_acc = 0;
4437 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Default xcap=%0x\n",
4438 cfo->crystal_cap_default);
4439 rtw89_phy_cfo_set_crystal_cap(rtwdev, cfo->crystal_cap_default, true);
4440 rtw89_dcfo_comp_init(rtwdev);
4441 cfo->cfo_timer_ms = 2000;
4442 cfo->cfo_trig_by_timer_en = false;
4443 cfo->phy_cfo_trk_cnt = 0;
4444 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL;
4445 cfo->cfo_ul_ofdma_acc_mode = RTW89_CFO_UL_OFDMA_ACC_ENABLE;
4446 }
4447
rtw89_phy_cfo_crystal_cap_adjust(struct rtw89_dev * rtwdev,s32 curr_cfo)4448 static void rtw89_phy_cfo_crystal_cap_adjust(struct rtw89_dev *rtwdev,
4449 s32 curr_cfo)
4450 {
4451 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4452 int crystal_cap = cfo->crystal_cap;
4453 s32 cfo_abs = abs(curr_cfo);
4454 int sign;
4455
4456 if (curr_cfo == 0) {
4457 rtw89_debug(rtwdev, RTW89_DBG_CFO, "curr_cfo=0\n");
4458 return;
4459 }
4460 if (!cfo->is_adjust) {
4461 if (cfo_abs > CFO_TRK_ENABLE_TH)
4462 cfo->is_adjust = true;
4463 } else {
4464 if (cfo_abs <= CFO_TRK_STOP_TH)
4465 cfo->is_adjust = false;
4466 }
4467 if (!cfo->is_adjust) {
4468 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Stop CFO tracking\n");
4469 return;
4470 }
4471 sign = curr_cfo > 0 ? 1 : -1;
4472 if (cfo_abs > CFO_TRK_STOP_TH_4)
4473 crystal_cap += 3 * sign;
4474 else if (cfo_abs > CFO_TRK_STOP_TH_3)
4475 crystal_cap += 3 * sign;
4476 else if (cfo_abs > CFO_TRK_STOP_TH_2)
4477 crystal_cap += 1 * sign;
4478 else if (cfo_abs > CFO_TRK_STOP_TH_1)
4479 crystal_cap += 1 * sign;
4480 else
4481 return;
4482
4483 crystal_cap = clamp(crystal_cap, 0, 127);
4484 rtw89_phy_cfo_set_crystal_cap(rtwdev, (u8)crystal_cap, false);
4485 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4486 "X_cap{Curr,Default}={0x%x,0x%x}\n",
4487 cfo->crystal_cap, cfo->def_x_cap);
4488 }
4489
rtw89_phy_average_cfo_calc(struct rtw89_dev * rtwdev)4490 static s32 rtw89_phy_average_cfo_calc(struct rtw89_dev *rtwdev)
4491 {
4492 const struct rtw89_chip_info *chip = rtwdev->chip;
4493 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4494 s32 cfo_khz_all = 0;
4495 s32 cfo_cnt_all = 0;
4496 s32 cfo_all_avg = 0;
4497 u8 i;
4498
4499 if (rtwdev->total_sta_assoc != 1)
4500 return 0;
4501 rtw89_debug(rtwdev, RTW89_DBG_CFO, "one_entry_only\n");
4502 for (i = 0; i < CFO_TRACK_MAX_USER; i++) {
4503 if (cfo->cfo_cnt[i] == 0)
4504 continue;
4505 cfo_khz_all += cfo->cfo_tail[i];
4506 cfo_cnt_all += cfo->cfo_cnt[i];
4507 cfo_all_avg = phy_div(cfo_khz_all, cfo_cnt_all);
4508 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i];
4509 cfo->dcfo_avg = phy_div(cfo_khz_all << chip->dcfo_comp_sft,
4510 cfo_cnt_all);
4511 }
4512 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4513 "CFO track for macid = %d\n", i);
4514 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4515 "Total cfo=%dK, pkt_cnt=%d, avg_cfo=%dK\n",
4516 cfo_khz_all, cfo_cnt_all, cfo_all_avg);
4517 return cfo_all_avg;
4518 }
4519
rtw89_phy_multi_sta_cfo_calc(struct rtw89_dev * rtwdev)4520 static s32 rtw89_phy_multi_sta_cfo_calc(struct rtw89_dev *rtwdev)
4521 {
4522 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4523 struct rtw89_traffic_stats *stats = &rtwdev->stats;
4524 s32 target_cfo = 0;
4525 s32 cfo_khz_all = 0;
4526 s32 cfo_khz_all_tp_wgt = 0;
4527 s32 cfo_avg = 0;
4528 s32 max_cfo_lb = BIT(31);
4529 s32 min_cfo_ub = GENMASK(30, 0);
4530 u16 cfo_cnt_all = 0;
4531 u8 active_entry_cnt = 0;
4532 u8 sta_cnt = 0;
4533 u32 tp_all = 0;
4534 u8 i;
4535 u8 cfo_tol = 0;
4536
4537 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Multi entry cfo_trk\n");
4538 if (cfo->rtw89_multi_cfo_mode == RTW89_PKT_BASED_AVG_MODE) {
4539 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt based avg mode\n");
4540 for (i = 0; i < CFO_TRACK_MAX_USER; i++) {
4541 if (cfo->cfo_cnt[i] == 0)
4542 continue;
4543 cfo_khz_all += cfo->cfo_tail[i];
4544 cfo_cnt_all += cfo->cfo_cnt[i];
4545 cfo_avg = phy_div(cfo_khz_all, (s32)cfo_cnt_all);
4546 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4547 "Msta cfo=%d, pkt_cnt=%d, avg_cfo=%d\n",
4548 cfo_khz_all, cfo_cnt_all, cfo_avg);
4549 target_cfo = cfo_avg;
4550 }
4551 } else if (cfo->rtw89_multi_cfo_mode == RTW89_ENTRY_BASED_AVG_MODE) {
4552 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Entry based avg mode\n");
4553 for (i = 0; i < CFO_TRACK_MAX_USER; i++) {
4554 if (cfo->cfo_cnt[i] == 0)
4555 continue;
4556 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i],
4557 (s32)cfo->cfo_cnt[i]);
4558 cfo_khz_all += cfo->cfo_avg[i];
4559 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4560 "Macid=%d, cfo_avg=%d\n", i,
4561 cfo->cfo_avg[i]);
4562 }
4563 sta_cnt = rtwdev->total_sta_assoc;
4564 cfo_avg = phy_div(cfo_khz_all, (s32)sta_cnt);
4565 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4566 "Msta cfo_acc=%d, ent_cnt=%d, avg_cfo=%d\n",
4567 cfo_khz_all, sta_cnt, cfo_avg);
4568 target_cfo = cfo_avg;
4569 } else if (cfo->rtw89_multi_cfo_mode == RTW89_TP_BASED_AVG_MODE) {
4570 rtw89_debug(rtwdev, RTW89_DBG_CFO, "TP based avg mode\n");
4571 cfo_tol = cfo->sta_cfo_tolerance;
4572 for (i = 0; i < CFO_TRACK_MAX_USER; i++) {
4573 sta_cnt++;
4574 if (cfo->cfo_cnt[i] != 0) {
4575 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i],
4576 (s32)cfo->cfo_cnt[i]);
4577 active_entry_cnt++;
4578 } else {
4579 cfo->cfo_avg[i] = cfo->pre_cfo_avg[i];
4580 }
4581 max_cfo_lb = max(cfo->cfo_avg[i] - cfo_tol, max_cfo_lb);
4582 min_cfo_ub = min(cfo->cfo_avg[i] + cfo_tol, min_cfo_ub);
4583 cfo_khz_all += cfo->cfo_avg[i];
4584 /* need tp for each entry */
4585 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4586 "[%d] cfo_avg=%d, tp=tbd\n",
4587 i, cfo->cfo_avg[i]);
4588 if (sta_cnt >= rtwdev->total_sta_assoc)
4589 break;
4590 }
4591 tp_all = stats->rx_throughput; /* need tp for each entry */
4592 cfo_avg = phy_div(cfo_khz_all_tp_wgt, (s32)tp_all);
4593
4594 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Assoc sta cnt=%d\n",
4595 sta_cnt);
4596 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Active sta cnt=%d\n",
4597 active_entry_cnt);
4598 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4599 "Msta cfo with tp_wgt=%d, avg_cfo=%d\n",
4600 cfo_khz_all_tp_wgt, cfo_avg);
4601 rtw89_debug(rtwdev, RTW89_DBG_CFO, "cfo_lb=%d,cfo_ub=%d\n",
4602 max_cfo_lb, min_cfo_ub);
4603 if (max_cfo_lb <= min_cfo_ub) {
4604 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4605 "cfo win_size=%d\n",
4606 min_cfo_ub - max_cfo_lb);
4607 target_cfo = clamp(cfo_avg, max_cfo_lb, min_cfo_ub);
4608 } else {
4609 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4610 "No intersection of cfo tolerance windows\n");
4611 target_cfo = phy_div(cfo_khz_all, (s32)sta_cnt);
4612 }
4613 for (i = 0; i < CFO_TRACK_MAX_USER; i++)
4614 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i];
4615 }
4616 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Target cfo=%d\n", target_cfo);
4617 return target_cfo;
4618 }
4619
rtw89_phy_cfo_statistics_reset(struct rtw89_dev * rtwdev)4620 static void rtw89_phy_cfo_statistics_reset(struct rtw89_dev *rtwdev)
4621 {
4622 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4623
4624 memset(&cfo->cfo_tail, 0, sizeof(cfo->cfo_tail));
4625 memset(&cfo->cfo_cnt, 0, sizeof(cfo->cfo_cnt));
4626 cfo->packet_count = 0;
4627 cfo->packet_count_pre = 0;
4628 cfo->cfo_avg_pre = 0;
4629 }
4630
rtw89_phy_cfo_dm(struct rtw89_dev * rtwdev)4631 static void rtw89_phy_cfo_dm(struct rtw89_dev *rtwdev)
4632 {
4633 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4634 s32 new_cfo = 0;
4635 bool x_cap_update = false;
4636 u8 pre_x_cap = cfo->crystal_cap;
4637 u8 dcfo_comp_sft = rtwdev->chip->dcfo_comp_sft;
4638
4639 cfo->dcfo_avg = 0;
4640 rtw89_debug(rtwdev, RTW89_DBG_CFO, "CFO:total_sta_assoc=%d\n",
4641 rtwdev->total_sta_assoc);
4642 if (rtwdev->total_sta_assoc == 0 || rtw89_is_mlo_1_1(rtwdev)) {
4643 rtw89_phy_cfo_reset(rtwdev);
4644 return;
4645 }
4646 if (cfo->packet_count == 0) {
4647 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt = 0\n");
4648 return;
4649 }
4650 if (cfo->packet_count == cfo->packet_count_pre) {
4651 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt doesn't change\n");
4652 return;
4653 }
4654 if (rtwdev->total_sta_assoc == 1)
4655 new_cfo = rtw89_phy_average_cfo_calc(rtwdev);
4656 else
4657 new_cfo = rtw89_phy_multi_sta_cfo_calc(rtwdev);
4658 if (cfo->divergence_lock_en) {
4659 cfo->lock_cnt++;
4660 if (cfo->lock_cnt > CFO_PERIOD_CNT) {
4661 cfo->divergence_lock_en = false;
4662 cfo->lock_cnt = 0;
4663 } else {
4664 rtw89_phy_cfo_reset(rtwdev);
4665 }
4666 return;
4667 }
4668 if (cfo->crystal_cap >= cfo->x_cap_ub ||
4669 cfo->crystal_cap <= cfo->x_cap_lb) {
4670 cfo->divergence_lock_en = true;
4671 rtw89_phy_cfo_reset(rtwdev);
4672 return;
4673 }
4674
4675 rtw89_phy_cfo_crystal_cap_adjust(rtwdev, new_cfo);
4676 cfo->cfo_avg_pre = new_cfo;
4677 cfo->dcfo_avg_pre = cfo->dcfo_avg;
4678 x_cap_update = cfo->crystal_cap != pre_x_cap;
4679 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap_up=%d\n", x_cap_update);
4680 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap: D:%x C:%x->%x, ofst=%d\n",
4681 cfo->def_x_cap, pre_x_cap, cfo->crystal_cap,
4682 cfo->x_cap_ofst);
4683 if (x_cap_update) {
4684 if (cfo->dcfo_avg > 0)
4685 cfo->dcfo_avg -= CFO_SW_COMP_FINE_TUNE << dcfo_comp_sft;
4686 else
4687 cfo->dcfo_avg += CFO_SW_COMP_FINE_TUNE << dcfo_comp_sft;
4688 }
4689 rtw89_dcfo_comp(rtwdev, cfo->dcfo_avg);
4690 rtw89_phy_cfo_statistics_reset(rtwdev);
4691 }
4692
rtw89_phy_cfo_track_work(struct wiphy * wiphy,struct wiphy_work * work)4693 void rtw89_phy_cfo_track_work(struct wiphy *wiphy, struct wiphy_work *work)
4694 {
4695 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
4696 cfo_track_work.work);
4697 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4698
4699 lockdep_assert_wiphy(wiphy);
4700
4701 if (!cfo->cfo_trig_by_timer_en)
4702 return;
4703 rtw89_leave_ps_mode(rtwdev);
4704 rtw89_phy_cfo_dm(rtwdev);
4705 wiphy_delayed_work_queue(wiphy, &rtwdev->cfo_track_work,
4706 msecs_to_jiffies(cfo->cfo_timer_ms));
4707 }
4708
rtw89_phy_cfo_start_work(struct rtw89_dev * rtwdev)4709 static void rtw89_phy_cfo_start_work(struct rtw89_dev *rtwdev)
4710 {
4711 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4712
4713 wiphy_delayed_work_queue(rtwdev->hw->wiphy, &rtwdev->cfo_track_work,
4714 msecs_to_jiffies(cfo->cfo_timer_ms));
4715 }
4716
rtw89_phy_cfo_track(struct rtw89_dev * rtwdev)4717 void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev)
4718 {
4719 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4720 struct rtw89_traffic_stats *stats = &rtwdev->stats;
4721 bool is_ul_ofdma = false, ofdma_acc_en = false;
4722
4723 if (stats->rx_tf_periodic > CFO_TF_CNT_TH)
4724 is_ul_ofdma = true;
4725 if (cfo->cfo_ul_ofdma_acc_mode == RTW89_CFO_UL_OFDMA_ACC_ENABLE &&
4726 is_ul_ofdma)
4727 ofdma_acc_en = true;
4728
4729 switch (cfo->phy_cfo_status) {
4730 case RTW89_PHY_DCFO_STATE_NORMAL:
4731 if (stats->tx_throughput >= CFO_TP_UPPER) {
4732 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_ENHANCE;
4733 cfo->cfo_trig_by_timer_en = true;
4734 cfo->cfo_timer_ms = CFO_COMP_PERIOD;
4735 rtw89_phy_cfo_start_work(rtwdev);
4736 }
4737 break;
4738 case RTW89_PHY_DCFO_STATE_ENHANCE:
4739 if (stats->tx_throughput <= CFO_TP_LOWER)
4740 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL;
4741 else if (ofdma_acc_en &&
4742 cfo->phy_cfo_trk_cnt >= CFO_PERIOD_CNT)
4743 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_HOLD;
4744 else
4745 cfo->phy_cfo_trk_cnt++;
4746
4747 if (cfo->phy_cfo_status == RTW89_PHY_DCFO_STATE_NORMAL) {
4748 cfo->phy_cfo_trk_cnt = 0;
4749 cfo->cfo_trig_by_timer_en = false;
4750 }
4751 break;
4752 case RTW89_PHY_DCFO_STATE_HOLD:
4753 if (stats->tx_throughput <= CFO_TP_LOWER) {
4754 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL;
4755 cfo->phy_cfo_trk_cnt = 0;
4756 cfo->cfo_trig_by_timer_en = false;
4757 } else {
4758 cfo->phy_cfo_trk_cnt++;
4759 }
4760 break;
4761 default:
4762 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL;
4763 cfo->phy_cfo_trk_cnt = 0;
4764 break;
4765 }
4766 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4767 "[CFO]WatchDog tp=%d,state=%d,timer_en=%d,trk_cnt=%d,thermal=%ld\n",
4768 stats->tx_throughput, cfo->phy_cfo_status,
4769 cfo->cfo_trig_by_timer_en, cfo->phy_cfo_trk_cnt,
4770 ewma_thermal_read(&rtwdev->phystat.avg_thermal[0]));
4771 if (cfo->cfo_trig_by_timer_en)
4772 return;
4773 rtw89_phy_cfo_dm(rtwdev);
4774 }
4775
rtw89_phy_cfo_parse(struct rtw89_dev * rtwdev,s16 cfo_val,struct rtw89_rx_phy_ppdu * phy_ppdu)4776 void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val,
4777 struct rtw89_rx_phy_ppdu *phy_ppdu)
4778 {
4779 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4780 u8 macid = phy_ppdu->mac_id;
4781
4782 if (macid >= CFO_TRACK_MAX_USER) {
4783 rtw89_warn(rtwdev, "mac_id %d is out of range\n", macid);
4784 return;
4785 }
4786
4787 cfo->cfo_tail[macid] += cfo_val;
4788 cfo->cfo_cnt[macid]++;
4789 cfo->packet_count++;
4790 }
4791
rtw89_phy_ul_tb_assoc(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)4792 void rtw89_phy_ul_tb_assoc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link)
4793 {
4794 const struct rtw89_chip_info *chip = rtwdev->chip;
4795 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev,
4796 rtwvif_link->chanctx_idx);
4797 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info;
4798
4799 if (!chip->ul_tb_waveform_ctrl)
4800 return;
4801
4802 rtwvif_link->def_tri_idx =
4803 rtw89_phy_read32_mask(rtwdev, R_DCFO_OPT, B_TXSHAPE_TRIANGULAR_CFG);
4804
4805 if (chip->chip_id == RTL8852B && rtwdev->hal.cv > CHIP_CBV)
4806 rtwvif_link->dyn_tb_bedge_en = false;
4807 else if (chan->band_type >= RTW89_BAND_5G &&
4808 chan->band_width >= RTW89_CHANNEL_WIDTH_40)
4809 rtwvif_link->dyn_tb_bedge_en = true;
4810 else
4811 rtwvif_link->dyn_tb_bedge_en = false;
4812
4813 rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
4814 "[ULTB] def_if_bandedge=%d, def_tri_idx=%d\n",
4815 ul_tb_info->def_if_bandedge, rtwvif_link->def_tri_idx);
4816 rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
4817 "[ULTB] dyn_tb_begde_en=%d, dyn_tb_tri_en=%d\n",
4818 rtwvif_link->dyn_tb_bedge_en, ul_tb_info->dyn_tb_tri_en);
4819 }
4820
4821 struct rtw89_phy_ul_tb_check_data {
4822 bool valid;
4823 bool high_tf_client;
4824 bool low_tf_client;
4825 bool dyn_tb_bedge_en;
4826 u8 def_tri_idx;
4827 };
4828
4829 struct rtw89_phy_power_diff {
4830 u32 q_00;
4831 u32 q_11;
4832 u32 q_matrix_en;
4833 u32 ultb_1t_norm_160;
4834 u32 ultb_2t_norm_160;
4835 u32 com1_norm_1sts;
4836 u32 com2_resp_1sts_path;
4837 };
4838
rtw89_phy_ofdma_power_diff(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)4839 static void rtw89_phy_ofdma_power_diff(struct rtw89_dev *rtwdev,
4840 struct rtw89_vif_link *rtwvif_link)
4841 {
4842 static const struct rtw89_phy_power_diff table[2] = {
4843 {0x0, 0x0, 0x0, 0x0, 0xf4, 0x3, 0x3},
4844 {0xb50, 0xb50, 0x1, 0xc, 0x0, 0x1, 0x1},
4845 };
4846 const struct rtw89_phy_power_diff *param;
4847 u32 reg;
4848
4849 if (!rtwdev->chip->ul_tb_pwr_diff)
4850 return;
4851
4852 if (rtwvif_link->pwr_diff_en == rtwvif_link->pre_pwr_diff_en) {
4853 rtwvif_link->pwr_diff_en = false;
4854 return;
4855 }
4856
4857 rtwvif_link->pre_pwr_diff_en = rtwvif_link->pwr_diff_en;
4858 param = &table[rtwvif_link->pwr_diff_en];
4859
4860 rtw89_phy_write32_mask(rtwdev, R_Q_MATRIX_00, B_Q_MATRIX_00_REAL,
4861 param->q_00);
4862 rtw89_phy_write32_mask(rtwdev, R_Q_MATRIX_11, B_Q_MATRIX_11_REAL,
4863 param->q_11);
4864 rtw89_phy_write32_mask(rtwdev, R_CUSTOMIZE_Q_MATRIX,
4865 B_CUSTOMIZE_Q_MATRIX_EN, param->q_matrix_en);
4866
4867 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, rtwvif_link->mac_idx);
4868 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_NORM_BW160,
4869 param->ultb_1t_norm_160);
4870
4871 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, rtwvif_link->mac_idx);
4872 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_NORM_BW160,
4873 param->ultb_2t_norm_160);
4874
4875 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PATH_COM1, rtwvif_link->mac_idx);
4876 rtw89_write32_mask(rtwdev, reg, B_AX_PATH_COM1_NORM_1STS,
4877 param->com1_norm_1sts);
4878
4879 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PATH_COM2, rtwvif_link->mac_idx);
4880 rtw89_write32_mask(rtwdev, reg, B_AX_PATH_COM2_RESP_1STS_PATH,
4881 param->com2_resp_1sts_path);
4882 }
4883
4884 static
rtw89_phy_ul_tb_ctrl_check(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_phy_ul_tb_check_data * ul_tb_data)4885 void rtw89_phy_ul_tb_ctrl_check(struct rtw89_dev *rtwdev,
4886 struct rtw89_vif_link *rtwvif_link,
4887 struct rtw89_phy_ul_tb_check_data *ul_tb_data)
4888 {
4889 struct rtw89_traffic_stats *stats = &rtwdev->stats;
4890 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
4891
4892 if (rtwvif_link->wifi_role != RTW89_WIFI_ROLE_STATION)
4893 return;
4894
4895 if (!vif->cfg.assoc)
4896 return;
4897
4898 if (rtwdev->chip->ul_tb_waveform_ctrl) {
4899 if (stats->rx_tf_periodic > UL_TB_TF_CNT_L2H_TH)
4900 ul_tb_data->high_tf_client = true;
4901 else if (stats->rx_tf_periodic < UL_TB_TF_CNT_H2L_TH)
4902 ul_tb_data->low_tf_client = true;
4903
4904 ul_tb_data->valid = true;
4905 ul_tb_data->def_tri_idx = rtwvif_link->def_tri_idx;
4906 ul_tb_data->dyn_tb_bedge_en = rtwvif_link->dyn_tb_bedge_en;
4907 }
4908
4909 rtw89_phy_ofdma_power_diff(rtwdev, rtwvif_link);
4910 }
4911
rtw89_phy_ul_tb_waveform_ctrl(struct rtw89_dev * rtwdev,struct rtw89_phy_ul_tb_check_data * ul_tb_data)4912 static void rtw89_phy_ul_tb_waveform_ctrl(struct rtw89_dev *rtwdev,
4913 struct rtw89_phy_ul_tb_check_data *ul_tb_data)
4914 {
4915 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info;
4916
4917 if (!rtwdev->chip->ul_tb_waveform_ctrl)
4918 return;
4919
4920 if (ul_tb_data->dyn_tb_bedge_en) {
4921 if (ul_tb_data->high_tf_client) {
4922 rtw89_phy_write32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 0);
4923 rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
4924 "[ULTB] Turn off if_bandedge\n");
4925 } else if (ul_tb_data->low_tf_client) {
4926 rtw89_phy_write32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN,
4927 ul_tb_info->def_if_bandedge);
4928 rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
4929 "[ULTB] Set to default if_bandedge = %d\n",
4930 ul_tb_info->def_if_bandedge);
4931 }
4932 }
4933
4934 if (ul_tb_info->dyn_tb_tri_en) {
4935 if (ul_tb_data->high_tf_client) {
4936 rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT,
4937 B_TXSHAPE_TRIANGULAR_CFG, 0);
4938 rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
4939 "[ULTB] Turn off Tx triangle\n");
4940 } else if (ul_tb_data->low_tf_client) {
4941 rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT,
4942 B_TXSHAPE_TRIANGULAR_CFG,
4943 ul_tb_data->def_tri_idx);
4944 rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
4945 "[ULTB] Set to default tx_shap_idx = %d\n",
4946 ul_tb_data->def_tri_idx);
4947 }
4948 }
4949 }
4950
rtw89_phy_ul_tb_ctrl_track(struct rtw89_dev * rtwdev)4951 void rtw89_phy_ul_tb_ctrl_track(struct rtw89_dev *rtwdev)
4952 {
4953 const struct rtw89_chip_info *chip = rtwdev->chip;
4954 struct rtw89_phy_ul_tb_check_data ul_tb_data = {};
4955 struct rtw89_vif_link *rtwvif_link;
4956 struct rtw89_vif *rtwvif;
4957 unsigned int link_id;
4958
4959 if (!chip->ul_tb_waveform_ctrl && !chip->ul_tb_pwr_diff)
4960 return;
4961
4962 if (rtwdev->total_sta_assoc != 1)
4963 return;
4964
4965 rtw89_for_each_rtwvif(rtwdev, rtwvif)
4966 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id)
4967 rtw89_phy_ul_tb_ctrl_check(rtwdev, rtwvif_link, &ul_tb_data);
4968
4969 if (!ul_tb_data.valid)
4970 return;
4971
4972 rtw89_phy_ul_tb_waveform_ctrl(rtwdev, &ul_tb_data);
4973 }
4974
rtw89_phy_ul_tb_info_init(struct rtw89_dev * rtwdev)4975 static void rtw89_phy_ul_tb_info_init(struct rtw89_dev *rtwdev)
4976 {
4977 const struct rtw89_chip_info *chip = rtwdev->chip;
4978 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info;
4979
4980 if (!chip->ul_tb_waveform_ctrl)
4981 return;
4982
4983 ul_tb_info->dyn_tb_tri_en = true;
4984 ul_tb_info->def_if_bandedge =
4985 rtw89_phy_read32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN);
4986 }
4987
4988 static
rtw89_phy_antdiv_sts_instance_reset(struct rtw89_antdiv_stats * antdiv_sts)4989 void rtw89_phy_antdiv_sts_instance_reset(struct rtw89_antdiv_stats *antdiv_sts)
4990 {
4991 ewma_rssi_init(&antdiv_sts->cck_rssi_avg);
4992 ewma_rssi_init(&antdiv_sts->ofdm_rssi_avg);
4993 ewma_rssi_init(&antdiv_sts->non_legacy_rssi_avg);
4994 antdiv_sts->pkt_cnt_cck = 0;
4995 antdiv_sts->pkt_cnt_ofdm = 0;
4996 antdiv_sts->pkt_cnt_non_legacy = 0;
4997 antdiv_sts->evm = 0;
4998 }
4999
rtw89_phy_antdiv_sts_instance_add(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct rtw89_antdiv_stats * stats)5000 static void rtw89_phy_antdiv_sts_instance_add(struct rtw89_dev *rtwdev,
5001 struct rtw89_rx_phy_ppdu *phy_ppdu,
5002 struct rtw89_antdiv_stats *stats)
5003 {
5004 if (rtw89_get_data_rate_mode(rtwdev, phy_ppdu->rate) == DATA_RATE_MODE_NON_HT) {
5005 if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6) {
5006 ewma_rssi_add(&stats->cck_rssi_avg, phy_ppdu->rssi_avg);
5007 stats->pkt_cnt_cck++;
5008 } else {
5009 ewma_rssi_add(&stats->ofdm_rssi_avg, phy_ppdu->rssi_avg);
5010 stats->pkt_cnt_ofdm++;
5011 stats->evm += phy_ppdu->ofdm.evm_min;
5012 }
5013 } else {
5014 ewma_rssi_add(&stats->non_legacy_rssi_avg, phy_ppdu->rssi_avg);
5015 stats->pkt_cnt_non_legacy++;
5016 stats->evm += phy_ppdu->ofdm.evm_min;
5017 }
5018 }
5019
rtw89_phy_antdiv_sts_instance_get_rssi(struct rtw89_antdiv_stats * stats)5020 static u8 rtw89_phy_antdiv_sts_instance_get_rssi(struct rtw89_antdiv_stats *stats)
5021 {
5022 if (stats->pkt_cnt_non_legacy >= stats->pkt_cnt_cck &&
5023 stats->pkt_cnt_non_legacy >= stats->pkt_cnt_ofdm)
5024 return ewma_rssi_read(&stats->non_legacy_rssi_avg);
5025 else if (stats->pkt_cnt_ofdm >= stats->pkt_cnt_cck &&
5026 stats->pkt_cnt_ofdm >= stats->pkt_cnt_non_legacy)
5027 return ewma_rssi_read(&stats->ofdm_rssi_avg);
5028 else
5029 return ewma_rssi_read(&stats->cck_rssi_avg);
5030 }
5031
rtw89_phy_antdiv_sts_instance_get_evm(struct rtw89_antdiv_stats * stats)5032 static u8 rtw89_phy_antdiv_sts_instance_get_evm(struct rtw89_antdiv_stats *stats)
5033 {
5034 return phy_div(stats->evm, stats->pkt_cnt_non_legacy + stats->pkt_cnt_ofdm);
5035 }
5036
rtw89_phy_antdiv_parse(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu)5037 void rtw89_phy_antdiv_parse(struct rtw89_dev *rtwdev,
5038 struct rtw89_rx_phy_ppdu *phy_ppdu)
5039 {
5040 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
5041 struct rtw89_hal *hal = &rtwdev->hal;
5042
5043 if (!hal->ant_diversity || hal->ant_diversity_fixed)
5044 return;
5045
5046 rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->target_stats);
5047
5048 if (!antdiv->get_stats)
5049 return;
5050
5051 if (hal->antenna_rx == RF_A)
5052 rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->main_stats);
5053 else if (hal->antenna_rx == RF_B)
5054 rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->aux_stats);
5055 }
5056
rtw89_phy_antdiv_reg_init(struct rtw89_dev * rtwdev)5057 static void rtw89_phy_antdiv_reg_init(struct rtw89_dev *rtwdev)
5058 {
5059 rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_ANT_TRAIN_EN,
5060 0x0, RTW89_PHY_0);
5061 rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_TX_ANT_SEL,
5062 0x0, RTW89_PHY_0);
5063
5064 rtw89_phy_write32_idx(rtwdev, R_P0_ANT_SW, B_P0_TRSW_TX_EXTEND,
5065 0x0, RTW89_PHY_0);
5066 rtw89_phy_write32_idx(rtwdev, R_P0_ANT_SW, B_P0_HW_ANTSW_DIS_BY_GNT_BT,
5067 0x0, RTW89_PHY_0);
5068
5069 rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_BT_FORCE_ANTIDX_EN,
5070 0x0, RTW89_PHY_0);
5071
5072 rtw89_phy_write32_idx(rtwdev, R_RFSW_CTRL_ANT0_BASE, B_RFSW_CTRL_ANT_MAPPING,
5073 0x0100, RTW89_PHY_0);
5074
5075 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_BTG_TRX,
5076 0x1, RTW89_PHY_0);
5077 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_HW_CTRL,
5078 0x0, RTW89_PHY_0);
5079 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_SW_2G,
5080 0x0, RTW89_PHY_0);
5081 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_SW_5G,
5082 0x0, RTW89_PHY_0);
5083 }
5084
rtw89_phy_antdiv_sts_reset(struct rtw89_dev * rtwdev)5085 static void rtw89_phy_antdiv_sts_reset(struct rtw89_dev *rtwdev)
5086 {
5087 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
5088
5089 rtw89_phy_antdiv_sts_instance_reset(&antdiv->target_stats);
5090 rtw89_phy_antdiv_sts_instance_reset(&antdiv->main_stats);
5091 rtw89_phy_antdiv_sts_instance_reset(&antdiv->aux_stats);
5092 }
5093
rtw89_phy_antdiv_init(struct rtw89_dev * rtwdev)5094 static void rtw89_phy_antdiv_init(struct rtw89_dev *rtwdev)
5095 {
5096 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
5097 struct rtw89_hal *hal = &rtwdev->hal;
5098
5099 if (!hal->ant_diversity)
5100 return;
5101
5102 antdiv->get_stats = false;
5103 antdiv->rssi_pre = 0;
5104 rtw89_phy_antdiv_sts_reset(rtwdev);
5105 rtw89_phy_antdiv_reg_init(rtwdev);
5106 }
5107
rtw89_phy_thermal_protect(struct rtw89_dev * rtwdev)5108 static void rtw89_phy_thermal_protect(struct rtw89_dev *rtwdev)
5109 {
5110 struct rtw89_phy_stat *phystat = &rtwdev->phystat;
5111 struct rtw89_hal *hal = &rtwdev->hal;
5112 u8 th_max = phystat->last_thermal_max;
5113 u8 lv = hal->thermal_prot_lv;
5114
5115 if (!hal->thermal_prot_th ||
5116 (hal->disabled_dm_bitmap & BIT(RTW89_DM_THERMAL_PROTECT)))
5117 return;
5118
5119 if (th_max > hal->thermal_prot_th && lv < RTW89_THERMAL_PROT_LV_MAX)
5120 lv++;
5121 else if (th_max < hal->thermal_prot_th - 2 && lv > 0)
5122 lv--;
5123 else
5124 return;
5125
5126 hal->thermal_prot_lv = lv;
5127
5128 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, "thermal protection lv=%d\n", lv);
5129
5130 rtw89_fw_h2c_tx_duty(rtwdev, hal->thermal_prot_lv);
5131 }
5132
rtw89_phy_stat_thermal_update(struct rtw89_dev * rtwdev)5133 static void rtw89_phy_stat_thermal_update(struct rtw89_dev *rtwdev)
5134 {
5135 struct rtw89_phy_stat *phystat = &rtwdev->phystat;
5136 u8 th, th_max = 0;
5137 int i;
5138
5139 for (i = 0; i < rtwdev->chip->rf_path_num; i++) {
5140 th = rtw89_chip_get_thermal(rtwdev, i);
5141 if (th)
5142 ewma_thermal_add(&phystat->avg_thermal[i], th);
5143
5144 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
5145 "path(%d) thermal cur=%u avg=%ld", i, th,
5146 ewma_thermal_read(&phystat->avg_thermal[i]));
5147
5148 th_max = max(th_max, th);
5149 }
5150
5151 phystat->last_thermal_max = th_max;
5152 }
5153
5154 struct rtw89_phy_iter_rssi_data {
5155 struct rtw89_dev *rtwdev;
5156 bool rssi_changed;
5157 };
5158
5159 static
__rtw89_phy_stat_rssi_update_iter(struct rtw89_sta_link * rtwsta_link,struct rtw89_phy_iter_rssi_data * rssi_data)5160 void __rtw89_phy_stat_rssi_update_iter(struct rtw89_sta_link *rtwsta_link,
5161 struct rtw89_phy_iter_rssi_data *rssi_data)
5162 {
5163 struct rtw89_vif_link *rtwvif_link = rtwsta_link->rtwvif_link;
5164 struct rtw89_dev *rtwdev = rssi_data->rtwdev;
5165 struct rtw89_phy_ch_info *ch_info;
5166 struct rtw89_bb_ctx *bb;
5167 unsigned long rssi_curr;
5168
5169 rssi_curr = ewma_rssi_read(&rtwsta_link->avg_rssi);
5170 bb = rtw89_get_bb_ctx(rtwdev, rtwvif_link->phy_idx);
5171 ch_info = &bb->ch_info;
5172
5173 if (rssi_curr < ch_info->rssi_min) {
5174 ch_info->rssi_min = rssi_curr;
5175 ch_info->rssi_min_macid = rtwsta_link->mac_id;
5176 }
5177
5178 if (rtwsta_link->prev_rssi == 0) {
5179 rtwsta_link->prev_rssi = rssi_curr;
5180 } else if (abs((int)rtwsta_link->prev_rssi - (int)rssi_curr) >
5181 (3 << RSSI_FACTOR)) {
5182 rtwsta_link->prev_rssi = rssi_curr;
5183 rssi_data->rssi_changed = true;
5184 }
5185 }
5186
rtw89_phy_stat_rssi_update_iter(void * data,struct ieee80211_sta * sta)5187 static void rtw89_phy_stat_rssi_update_iter(void *data,
5188 struct ieee80211_sta *sta)
5189 {
5190 struct rtw89_phy_iter_rssi_data *rssi_data =
5191 (struct rtw89_phy_iter_rssi_data *)data;
5192 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
5193 struct rtw89_sta_link *rtwsta_link;
5194 unsigned int link_id;
5195
5196 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id)
5197 __rtw89_phy_stat_rssi_update_iter(rtwsta_link, rssi_data);
5198 }
5199
rtw89_phy_stat_rssi_update(struct rtw89_dev * rtwdev)5200 static void rtw89_phy_stat_rssi_update(struct rtw89_dev *rtwdev)
5201 {
5202 struct rtw89_phy_iter_rssi_data rssi_data = {};
5203 struct rtw89_bb_ctx *bb;
5204
5205 rssi_data.rtwdev = rtwdev;
5206 rtw89_for_each_active_bb(rtwdev, bb)
5207 bb->ch_info.rssi_min = U8_MAX;
5208
5209 ieee80211_iterate_stations_atomic(rtwdev->hw,
5210 rtw89_phy_stat_rssi_update_iter,
5211 &rssi_data);
5212 if (rssi_data.rssi_changed)
5213 rtw89_btc_ntfy_wl_sta(rtwdev);
5214 }
5215
rtw89_phy_stat_init(struct rtw89_dev * rtwdev)5216 static void rtw89_phy_stat_init(struct rtw89_dev *rtwdev)
5217 {
5218 struct rtw89_phy_stat *phystat = &rtwdev->phystat;
5219 int i;
5220
5221 for (i = 0; i < rtwdev->chip->rf_path_num; i++)
5222 ewma_thermal_init(&phystat->avg_thermal[i]);
5223
5224 rtw89_phy_stat_thermal_update(rtwdev);
5225
5226 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat));
5227 memset(&phystat->last_pkt_stat, 0, sizeof(phystat->last_pkt_stat));
5228
5229 ewma_rssi_init(&phystat->bcn_rssi);
5230
5231 rtwdev->hal.thermal_prot_lv = 0;
5232 }
5233
rtw89_phy_stat_track(struct rtw89_dev * rtwdev)5234 void rtw89_phy_stat_track(struct rtw89_dev *rtwdev)
5235 {
5236 struct rtw89_phy_stat *phystat = &rtwdev->phystat;
5237
5238 rtw89_phy_stat_thermal_update(rtwdev);
5239 rtw89_phy_thermal_protect(rtwdev);
5240 rtw89_phy_stat_rssi_update(rtwdev);
5241
5242 phystat->last_pkt_stat = phystat->cur_pkt_stat;
5243 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat));
5244 }
5245
rtw89_phy_ccx_us_to_idx(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,u32 time_us)5246 static u16 rtw89_phy_ccx_us_to_idx(struct rtw89_dev *rtwdev,
5247 struct rtw89_bb_ctx *bb, u32 time_us)
5248 {
5249 struct rtw89_env_monitor_info *env = &bb->env_monitor;
5250
5251 return time_us >> (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx);
5252 }
5253
rtw89_phy_ccx_idx_to_us(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,u16 idx)5254 static u32 rtw89_phy_ccx_idx_to_us(struct rtw89_dev *rtwdev,
5255 struct rtw89_bb_ctx *bb, u16 idx)
5256 {
5257 struct rtw89_env_monitor_info *env = &bb->env_monitor;
5258
5259 return idx << (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx);
5260 }
5261
rtw89_phy_ccx_top_setting_init(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)5262 static void rtw89_phy_ccx_top_setting_init(struct rtw89_dev *rtwdev,
5263 struct rtw89_bb_ctx *bb)
5264 {
5265 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
5266 struct rtw89_env_monitor_info *env = &bb->env_monitor;
5267 const struct rtw89_ccx_regs *ccx = phy->ccx;
5268
5269 env->ccx_manual_ctrl = false;
5270 env->ccx_ongoing = false;
5271 env->ccx_rac_lv = RTW89_RAC_RELEASE;
5272 env->ccx_period = 0;
5273 env->ccx_unit_idx = RTW89_CCX_32_US;
5274
5275 rtw89_phy_write32_idx(rtwdev, ccx->setting_addr, ccx->en_mask, 1, bb->phy_idx);
5276 rtw89_phy_write32_idx(rtwdev, ccx->setting_addr, ccx->trig_opt_mask, 1,
5277 bb->phy_idx);
5278 rtw89_phy_write32_idx(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 1,
5279 bb->phy_idx);
5280 rtw89_phy_write32_idx(rtwdev, ccx->setting_addr, ccx->edcca_opt_mask,
5281 RTW89_CCX_EDCCA_BW20_0, bb->phy_idx);
5282 }
5283
rtw89_phy_ccx_get_report(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,u16 report,u16 score)5284 static u16 rtw89_phy_ccx_get_report(struct rtw89_dev *rtwdev,
5285 struct rtw89_bb_ctx *bb,
5286 u16 report, u16 score)
5287 {
5288 struct rtw89_env_monitor_info *env = &bb->env_monitor;
5289 u32 numer = 0;
5290 u16 ret = 0;
5291
5292 numer = report * score + (env->ccx_period >> 1);
5293 if (env->ccx_period)
5294 ret = numer / env->ccx_period;
5295
5296 return ret >= score ? score - 1 : ret;
5297 }
5298
rtw89_phy_ccx_ms_to_period_unit(struct rtw89_dev * rtwdev,u16 time_ms,u32 * period,u32 * unit_idx)5299 static void rtw89_phy_ccx_ms_to_period_unit(struct rtw89_dev *rtwdev,
5300 u16 time_ms, u32 *period,
5301 u32 *unit_idx)
5302 {
5303 u32 idx;
5304 u8 quotient;
5305
5306 if (time_ms >= CCX_MAX_PERIOD)
5307 time_ms = CCX_MAX_PERIOD;
5308
5309 quotient = CCX_MAX_PERIOD_UNIT * time_ms / CCX_MAX_PERIOD;
5310
5311 if (quotient < 4)
5312 idx = RTW89_CCX_4_US;
5313 else if (quotient < 8)
5314 idx = RTW89_CCX_8_US;
5315 else if (quotient < 16)
5316 idx = RTW89_CCX_16_US;
5317 else
5318 idx = RTW89_CCX_32_US;
5319
5320 *unit_idx = idx;
5321 *period = (time_ms * MS_TO_4US_RATIO) >> idx;
5322
5323 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5324 "[Trigger Time] period:%d, unit_idx:%d\n",
5325 *period, *unit_idx);
5326 }
5327
rtw89_phy_ccx_racing_release(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)5328 static void rtw89_phy_ccx_racing_release(struct rtw89_dev *rtwdev,
5329 struct rtw89_bb_ctx *bb)
5330 {
5331 struct rtw89_env_monitor_info *env = &bb->env_monitor;
5332
5333 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5334 "lv:(%d)->(0)\n", env->ccx_rac_lv);
5335
5336 env->ccx_ongoing = false;
5337 env->ccx_rac_lv = RTW89_RAC_RELEASE;
5338 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND;
5339 }
5340
rtw89_phy_ifs_clm_th_update_check(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,struct rtw89_ccx_para_info * para)5341 static bool rtw89_phy_ifs_clm_th_update_check(struct rtw89_dev *rtwdev,
5342 struct rtw89_bb_ctx *bb,
5343 struct rtw89_ccx_para_info *para)
5344 {
5345 struct rtw89_env_monitor_info *env = &bb->env_monitor;
5346 bool is_update = env->ifs_clm_app != para->ifs_clm_app;
5347 u8 i = 0;
5348 u16 *ifs_th_l = env->ifs_clm_th_l;
5349 u16 *ifs_th_h = env->ifs_clm_th_h;
5350 u32 ifs_th0_us = 0, ifs_th_times = 0;
5351 u32 ifs_th_h_us[RTW89_IFS_CLM_NUM] = {0};
5352
5353 if (!is_update)
5354 goto ifs_update_finished;
5355
5356 switch (para->ifs_clm_app) {
5357 case RTW89_IFS_CLM_INIT:
5358 case RTW89_IFS_CLM_BACKGROUND:
5359 case RTW89_IFS_CLM_ACS:
5360 case RTW89_IFS_CLM_DBG:
5361 case RTW89_IFS_CLM_DIG:
5362 case RTW89_IFS_CLM_TDMA_DIG:
5363 ifs_th0_us = IFS_CLM_TH0_UPPER;
5364 ifs_th_times = IFS_CLM_TH_MUL;
5365 break;
5366 case RTW89_IFS_CLM_DBG_MANUAL:
5367 ifs_th0_us = para->ifs_clm_manual_th0;
5368 ifs_th_times = para->ifs_clm_manual_th_times;
5369 break;
5370 default:
5371 break;
5372 }
5373
5374 /* Set sampling threshold for 4 different regions, unit in idx_cnt.
5375 * low[i] = high[i-1] + 1
5376 * high[i] = high[i-1] * ifs_th_times
5377 */
5378 ifs_th_l[IFS_CLM_TH_START_IDX] = 0;
5379 ifs_th_h_us[IFS_CLM_TH_START_IDX] = ifs_th0_us;
5380 ifs_th_h[IFS_CLM_TH_START_IDX] = rtw89_phy_ccx_us_to_idx(rtwdev, bb,
5381 ifs_th0_us);
5382 for (i = 1; i < RTW89_IFS_CLM_NUM; i++) {
5383 ifs_th_l[i] = ifs_th_h[i - 1] + 1;
5384 ifs_th_h_us[i] = ifs_th_h_us[i - 1] * ifs_th_times;
5385 ifs_th_h[i] = rtw89_phy_ccx_us_to_idx(rtwdev, bb, ifs_th_h_us[i]);
5386 }
5387
5388 ifs_update_finished:
5389 if (!is_update)
5390 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5391 "No need to update IFS_TH\n");
5392
5393 return is_update;
5394 }
5395
rtw89_phy_ifs_clm_set_th_reg(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)5396 static void rtw89_phy_ifs_clm_set_th_reg(struct rtw89_dev *rtwdev,
5397 struct rtw89_bb_ctx *bb)
5398 {
5399 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
5400 struct rtw89_env_monitor_info *env = &bb->env_monitor;
5401 const struct rtw89_ccx_regs *ccx = phy->ccx;
5402 u8 i = 0;
5403
5404 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t1_addr, ccx->ifs_t1_th_l_mask,
5405 env->ifs_clm_th_l[0], bb->phy_idx);
5406 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t2_addr, ccx->ifs_t2_th_l_mask,
5407 env->ifs_clm_th_l[1], bb->phy_idx);
5408 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t3_addr, ccx->ifs_t3_th_l_mask,
5409 env->ifs_clm_th_l[2], bb->phy_idx);
5410 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t4_addr, ccx->ifs_t4_th_l_mask,
5411 env->ifs_clm_th_l[3], bb->phy_idx);
5412
5413 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t1_addr, ccx->ifs_t1_th_h_mask,
5414 env->ifs_clm_th_h[0], bb->phy_idx);
5415 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t2_addr, ccx->ifs_t2_th_h_mask,
5416 env->ifs_clm_th_h[1], bb->phy_idx);
5417 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t3_addr, ccx->ifs_t3_th_h_mask,
5418 env->ifs_clm_th_h[2], bb->phy_idx);
5419 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t4_addr, ccx->ifs_t4_th_h_mask,
5420 env->ifs_clm_th_h[3], bb->phy_idx);
5421
5422 for (i = 0; i < RTW89_IFS_CLM_NUM; i++)
5423 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5424 "Update IFS_T%d_th{low, high} : {%d, %d}\n",
5425 i + 1, env->ifs_clm_th_l[i], env->ifs_clm_th_h[i]);
5426 }
5427
rtw89_phy_ifs_clm_setting_init(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)5428 static void rtw89_phy_ifs_clm_setting_init(struct rtw89_dev *rtwdev,
5429 struct rtw89_bb_ctx *bb)
5430 {
5431 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
5432 struct rtw89_env_monitor_info *env = &bb->env_monitor;
5433 const struct rtw89_ccx_regs *ccx = phy->ccx;
5434 struct rtw89_ccx_para_info para = {};
5435
5436 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND;
5437 env->ifs_clm_mntr_time = 0;
5438
5439 para.ifs_clm_app = RTW89_IFS_CLM_INIT;
5440 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, bb, ¶))
5441 rtw89_phy_ifs_clm_set_th_reg(rtwdev, bb);
5442
5443 rtw89_phy_write32_idx(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_collect_en_mask, true,
5444 bb->phy_idx);
5445 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t1_addr, ccx->ifs_t1_en_mask, true,
5446 bb->phy_idx);
5447 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t2_addr, ccx->ifs_t2_en_mask, true,
5448 bb->phy_idx);
5449 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t3_addr, ccx->ifs_t3_en_mask, true,
5450 bb->phy_idx);
5451 rtw89_phy_write32_idx(rtwdev, ccx->ifs_t4_addr, ccx->ifs_t4_en_mask, true,
5452 bb->phy_idx);
5453 }
5454
rtw89_phy_ccx_racing_ctrl(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,enum rtw89_env_racing_lv level)5455 static int rtw89_phy_ccx_racing_ctrl(struct rtw89_dev *rtwdev,
5456 struct rtw89_bb_ctx *bb,
5457 enum rtw89_env_racing_lv level)
5458 {
5459 struct rtw89_env_monitor_info *env = &bb->env_monitor;
5460 int ret = 0;
5461
5462 if (level >= RTW89_RAC_MAX_NUM) {
5463 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5464 "[WARNING] Wrong LV=%d\n", level);
5465 return -EINVAL;
5466 }
5467
5468 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5469 "ccx_ongoing=%d, level:(%d)->(%d)\n", env->ccx_ongoing,
5470 env->ccx_rac_lv, level);
5471
5472 if (env->ccx_ongoing) {
5473 if (level <= env->ccx_rac_lv)
5474 ret = -EINVAL;
5475 else
5476 env->ccx_ongoing = false;
5477 }
5478
5479 if (ret == 0)
5480 env->ccx_rac_lv = level;
5481
5482 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "ccx racing success=%d\n",
5483 !ret);
5484
5485 return ret;
5486 }
5487
rtw89_phy_ccx_trigger(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)5488 static void rtw89_phy_ccx_trigger(struct rtw89_dev *rtwdev,
5489 struct rtw89_bb_ctx *bb)
5490 {
5491 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
5492 struct rtw89_env_monitor_info *env = &bb->env_monitor;
5493 const struct rtw89_ccx_regs *ccx = phy->ccx;
5494
5495 rtw89_phy_write32_idx(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_clm_cnt_clear_mask, 0,
5496 bb->phy_idx);
5497 rtw89_phy_write32_idx(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 0,
5498 bb->phy_idx);
5499 rtw89_phy_write32_idx(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_clm_cnt_clear_mask, 1,
5500 bb->phy_idx);
5501 rtw89_phy_write32_idx(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 1,
5502 bb->phy_idx);
5503
5504 env->ccx_ongoing = true;
5505 }
5506
rtw89_phy_ifs_clm_get_utility(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)5507 static void rtw89_phy_ifs_clm_get_utility(struct rtw89_dev *rtwdev,
5508 struct rtw89_bb_ctx *bb)
5509 {
5510 struct rtw89_env_monitor_info *env = &bb->env_monitor;
5511 u8 i = 0;
5512 u32 res = 0;
5513
5514 env->ifs_clm_tx_ratio =
5515 rtw89_phy_ccx_get_report(rtwdev, bb, env->ifs_clm_tx, PERCENT);
5516 env->ifs_clm_edcca_excl_cca_ratio =
5517 rtw89_phy_ccx_get_report(rtwdev, bb, env->ifs_clm_edcca_excl_cca,
5518 PERCENT);
5519 env->ifs_clm_cck_fa_ratio =
5520 rtw89_phy_ccx_get_report(rtwdev, bb, env->ifs_clm_cckfa, PERCENT);
5521 env->ifs_clm_ofdm_fa_ratio =
5522 rtw89_phy_ccx_get_report(rtwdev, bb, env->ifs_clm_ofdmfa, PERCENT);
5523 env->ifs_clm_cck_cca_excl_fa_ratio =
5524 rtw89_phy_ccx_get_report(rtwdev, bb, env->ifs_clm_cckcca_excl_fa,
5525 PERCENT);
5526 env->ifs_clm_ofdm_cca_excl_fa_ratio =
5527 rtw89_phy_ccx_get_report(rtwdev, bb, env->ifs_clm_ofdmcca_excl_fa,
5528 PERCENT);
5529 env->ifs_clm_cck_fa_permil =
5530 rtw89_phy_ccx_get_report(rtwdev, bb, env->ifs_clm_cckfa, PERMIL);
5531 env->ifs_clm_ofdm_fa_permil =
5532 rtw89_phy_ccx_get_report(rtwdev, bb, env->ifs_clm_ofdmfa, PERMIL);
5533
5534 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) {
5535 if (env->ifs_clm_his[i] > ENV_MNTR_IFSCLM_HIS_MAX) {
5536 env->ifs_clm_ifs_avg[i] = ENV_MNTR_FAIL_DWORD;
5537 } else {
5538 env->ifs_clm_ifs_avg[i] =
5539 rtw89_phy_ccx_idx_to_us(rtwdev, bb,
5540 env->ifs_clm_avg[i]);
5541 }
5542
5543 res = rtw89_phy_ccx_idx_to_us(rtwdev, bb, env->ifs_clm_cca[i]);
5544 res += env->ifs_clm_his[i] >> 1;
5545 if (env->ifs_clm_his[i])
5546 res /= env->ifs_clm_his[i];
5547 else
5548 res = 0;
5549 env->ifs_clm_cca_avg[i] = res;
5550 }
5551
5552 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5553 "IFS-CLM ratio {Tx, EDCCA_exclu_cca} = {%d, %d}\n",
5554 env->ifs_clm_tx_ratio, env->ifs_clm_edcca_excl_cca_ratio);
5555 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5556 "IFS-CLM FA ratio {CCK, OFDM} = {%d, %d}\n",
5557 env->ifs_clm_cck_fa_ratio, env->ifs_clm_ofdm_fa_ratio);
5558 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5559 "IFS-CLM FA permil {CCK, OFDM} = {%d, %d}\n",
5560 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil);
5561 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5562 "IFS-CLM CCA_exclu_FA ratio {CCK, OFDM} = {%d, %d}\n",
5563 env->ifs_clm_cck_cca_excl_fa_ratio,
5564 env->ifs_clm_ofdm_cca_excl_fa_ratio);
5565 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5566 "Time:[his, ifs_avg(us), cca_avg(us)]\n");
5567 for (i = 0; i < RTW89_IFS_CLM_NUM; i++)
5568 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "T%d:[%d, %d, %d]\n",
5569 i + 1, env->ifs_clm_his[i], env->ifs_clm_ifs_avg[i],
5570 env->ifs_clm_cca_avg[i]);
5571 }
5572
rtw89_phy_ifs_clm_get_result(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)5573 static bool rtw89_phy_ifs_clm_get_result(struct rtw89_dev *rtwdev,
5574 struct rtw89_bb_ctx *bb)
5575 {
5576 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
5577 struct rtw89_env_monitor_info *env = &bb->env_monitor;
5578 const struct rtw89_ccx_regs *ccx = phy->ccx;
5579 u8 i = 0;
5580
5581 if (rtw89_phy_read32_idx(rtwdev, ccx->ifs_total_addr,
5582 ccx->ifs_cnt_done_mask, bb->phy_idx) == 0) {
5583 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5584 "Get IFS_CLM report Fail\n");
5585 return false;
5586 }
5587
5588 env->ifs_clm_tx =
5589 rtw89_phy_read32_idx(rtwdev, ccx->ifs_clm_tx_cnt_addr,
5590 ccx->ifs_clm_tx_cnt_msk, bb->phy_idx);
5591 env->ifs_clm_edcca_excl_cca =
5592 rtw89_phy_read32_idx(rtwdev, ccx->ifs_clm_tx_cnt_addr,
5593 ccx->ifs_clm_edcca_excl_cca_fa_mask, bb->phy_idx);
5594 env->ifs_clm_cckcca_excl_fa =
5595 rtw89_phy_read32_idx(rtwdev, ccx->ifs_clm_cca_addr,
5596 ccx->ifs_clm_cckcca_excl_fa_mask, bb->phy_idx);
5597 env->ifs_clm_ofdmcca_excl_fa =
5598 rtw89_phy_read32_idx(rtwdev, ccx->ifs_clm_cca_addr,
5599 ccx->ifs_clm_ofdmcca_excl_fa_mask, bb->phy_idx);
5600 env->ifs_clm_cckfa =
5601 rtw89_phy_read32_idx(rtwdev, ccx->ifs_clm_fa_addr,
5602 ccx->ifs_clm_cck_fa_mask, bb->phy_idx);
5603 env->ifs_clm_ofdmfa =
5604 rtw89_phy_read32_idx(rtwdev, ccx->ifs_clm_fa_addr,
5605 ccx->ifs_clm_ofdm_fa_mask, bb->phy_idx);
5606
5607 env->ifs_clm_his[0] =
5608 rtw89_phy_read32_idx(rtwdev, ccx->ifs_his_addr,
5609 ccx->ifs_t1_his_mask, bb->phy_idx);
5610 env->ifs_clm_his[1] =
5611 rtw89_phy_read32_idx(rtwdev, ccx->ifs_his_addr,
5612 ccx->ifs_t2_his_mask, bb->phy_idx);
5613 env->ifs_clm_his[2] =
5614 rtw89_phy_read32_idx(rtwdev, ccx->ifs_his_addr,
5615 ccx->ifs_t3_his_mask, bb->phy_idx);
5616 env->ifs_clm_his[3] =
5617 rtw89_phy_read32_idx(rtwdev, ccx->ifs_his_addr,
5618 ccx->ifs_t4_his_mask, bb->phy_idx);
5619
5620 env->ifs_clm_avg[0] =
5621 rtw89_phy_read32_idx(rtwdev, ccx->ifs_avg_l_addr,
5622 ccx->ifs_t1_avg_mask, bb->phy_idx);
5623 env->ifs_clm_avg[1] =
5624 rtw89_phy_read32_idx(rtwdev, ccx->ifs_avg_l_addr,
5625 ccx->ifs_t2_avg_mask, bb->phy_idx);
5626 env->ifs_clm_avg[2] =
5627 rtw89_phy_read32_idx(rtwdev, ccx->ifs_avg_h_addr,
5628 ccx->ifs_t3_avg_mask, bb->phy_idx);
5629 env->ifs_clm_avg[3] =
5630 rtw89_phy_read32_idx(rtwdev, ccx->ifs_avg_h_addr,
5631 ccx->ifs_t4_avg_mask, bb->phy_idx);
5632
5633 env->ifs_clm_cca[0] =
5634 rtw89_phy_read32_idx(rtwdev, ccx->ifs_cca_l_addr,
5635 ccx->ifs_t1_cca_mask, bb->phy_idx);
5636 env->ifs_clm_cca[1] =
5637 rtw89_phy_read32_idx(rtwdev, ccx->ifs_cca_l_addr,
5638 ccx->ifs_t2_cca_mask, bb->phy_idx);
5639 env->ifs_clm_cca[2] =
5640 rtw89_phy_read32_idx(rtwdev, ccx->ifs_cca_h_addr,
5641 ccx->ifs_t3_cca_mask, bb->phy_idx);
5642 env->ifs_clm_cca[3] =
5643 rtw89_phy_read32_idx(rtwdev, ccx->ifs_cca_h_addr,
5644 ccx->ifs_t4_cca_mask, bb->phy_idx);
5645
5646 env->ifs_clm_total_ifs =
5647 rtw89_phy_read32_idx(rtwdev, ccx->ifs_total_addr,
5648 ccx->ifs_total_mask, bb->phy_idx);
5649
5650 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "IFS-CLM total_ifs = %d\n",
5651 env->ifs_clm_total_ifs);
5652 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5653 "{Tx, EDCCA_exclu_cca} = {%d, %d}\n",
5654 env->ifs_clm_tx, env->ifs_clm_edcca_excl_cca);
5655 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5656 "IFS-CLM FA{CCK, OFDM} = {%d, %d}\n",
5657 env->ifs_clm_cckfa, env->ifs_clm_ofdmfa);
5658 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5659 "IFS-CLM CCA_exclu_FA{CCK, OFDM} = {%d, %d}\n",
5660 env->ifs_clm_cckcca_excl_fa, env->ifs_clm_ofdmcca_excl_fa);
5661
5662 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "Time:[his, avg, cca]\n");
5663 for (i = 0; i < RTW89_IFS_CLM_NUM; i++)
5664 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5665 "T%d:[%d, %d, %d]\n", i + 1, env->ifs_clm_his[i],
5666 env->ifs_clm_avg[i], env->ifs_clm_cca[i]);
5667
5668 rtw89_phy_ifs_clm_get_utility(rtwdev, bb);
5669
5670 return true;
5671 }
5672
rtw89_phy_ifs_clm_set(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,struct rtw89_ccx_para_info * para)5673 static int rtw89_phy_ifs_clm_set(struct rtw89_dev *rtwdev,
5674 struct rtw89_bb_ctx *bb,
5675 struct rtw89_ccx_para_info *para)
5676 {
5677 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
5678 struct rtw89_env_monitor_info *env = &bb->env_monitor;
5679 const struct rtw89_ccx_regs *ccx = phy->ccx;
5680 u32 period = 0;
5681 u32 unit_idx = 0;
5682
5683 if (para->mntr_time == 0) {
5684 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5685 "[WARN] MNTR_TIME is 0\n");
5686 return -EINVAL;
5687 }
5688
5689 if (rtw89_phy_ccx_racing_ctrl(rtwdev, bb, para->rac_lv))
5690 return -EINVAL;
5691
5692 if (para->mntr_time != env->ifs_clm_mntr_time) {
5693 rtw89_phy_ccx_ms_to_period_unit(rtwdev, para->mntr_time,
5694 &period, &unit_idx);
5695 rtw89_phy_write32_idx(rtwdev, ccx->ifs_cnt_addr,
5696 ccx->ifs_clm_period_mask, period, bb->phy_idx);
5697 rtw89_phy_write32_idx(rtwdev, ccx->ifs_cnt_addr,
5698 ccx->ifs_clm_cnt_unit_mask,
5699 unit_idx, bb->phy_idx);
5700
5701 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5702 "Update IFS-CLM time ((%d)) -> ((%d))\n",
5703 env->ifs_clm_mntr_time, para->mntr_time);
5704
5705 env->ifs_clm_mntr_time = para->mntr_time;
5706 env->ccx_period = (u16)period;
5707 env->ccx_unit_idx = (u8)unit_idx;
5708 }
5709
5710 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, bb, para)) {
5711 env->ifs_clm_app = para->ifs_clm_app;
5712 rtw89_phy_ifs_clm_set_th_reg(rtwdev, bb);
5713 }
5714
5715 return 0;
5716 }
5717
__rtw89_phy_env_monitor_track(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)5718 static void __rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev,
5719 struct rtw89_bb_ctx *bb)
5720 {
5721 struct rtw89_env_monitor_info *env = &bb->env_monitor;
5722 struct rtw89_ccx_para_info para = {};
5723 u8 chk_result = RTW89_PHY_ENV_MON_CCX_FAIL;
5724
5725 env->ccx_watchdog_result = RTW89_PHY_ENV_MON_CCX_FAIL;
5726 if (env->ccx_manual_ctrl) {
5727 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5728 "CCX in manual ctrl\n");
5729 return;
5730 }
5731
5732 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5733 "BB-%d env_monitor track\n", bb->phy_idx);
5734
5735 /* only ifs_clm for now */
5736 if (rtw89_phy_ifs_clm_get_result(rtwdev, bb))
5737 env->ccx_watchdog_result |= RTW89_PHY_ENV_MON_IFS_CLM;
5738
5739 rtw89_phy_ccx_racing_release(rtwdev, bb);
5740 para.mntr_time = 1900;
5741 para.rac_lv = RTW89_RAC_LV_1;
5742 para.ifs_clm_app = RTW89_IFS_CLM_BACKGROUND;
5743
5744 if (rtw89_phy_ifs_clm_set(rtwdev, bb, ¶) == 0)
5745 chk_result |= RTW89_PHY_ENV_MON_IFS_CLM;
5746 if (chk_result)
5747 rtw89_phy_ccx_trigger(rtwdev, bb);
5748
5749 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5750 "get_result=0x%x, chk_result:0x%x\n",
5751 env->ccx_watchdog_result, chk_result);
5752 }
5753
rtw89_phy_env_monitor_track(struct rtw89_dev * rtwdev)5754 void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev)
5755 {
5756 struct rtw89_bb_ctx *bb;
5757
5758 rtw89_for_each_active_bb(rtwdev, bb)
5759 __rtw89_phy_env_monitor_track(rtwdev, bb);
5760 }
5761
rtw89_physts_ie_page_valid(enum rtw89_phy_status_bitmap * ie_page)5762 static bool rtw89_physts_ie_page_valid(enum rtw89_phy_status_bitmap *ie_page)
5763 {
5764 if (*ie_page >= RTW89_PHYSTS_BITMAP_NUM ||
5765 *ie_page == RTW89_RSVD_9)
5766 return false;
5767 else if (*ie_page > RTW89_RSVD_9)
5768 *ie_page -= 1;
5769
5770 return true;
5771 }
5772
rtw89_phy_get_ie_bitmap_addr(enum rtw89_phy_status_bitmap ie_page)5773 static u32 rtw89_phy_get_ie_bitmap_addr(enum rtw89_phy_status_bitmap ie_page)
5774 {
5775 static const u8 ie_page_shift = 2;
5776
5777 return R_PHY_STS_BITMAP_ADDR_START + (ie_page << ie_page_shift);
5778 }
5779
rtw89_physts_get_ie_bitmap(struct rtw89_dev * rtwdev,enum rtw89_phy_status_bitmap ie_page,enum rtw89_phy_idx phy_idx)5780 static u32 rtw89_physts_get_ie_bitmap(struct rtw89_dev *rtwdev,
5781 enum rtw89_phy_status_bitmap ie_page,
5782 enum rtw89_phy_idx phy_idx)
5783 {
5784 u32 addr;
5785
5786 if (!rtw89_physts_ie_page_valid(&ie_page))
5787 return 0;
5788
5789 addr = rtw89_phy_get_ie_bitmap_addr(ie_page);
5790
5791 return rtw89_phy_read32_idx(rtwdev, addr, MASKDWORD, phy_idx);
5792 }
5793
rtw89_physts_set_ie_bitmap(struct rtw89_dev * rtwdev,enum rtw89_phy_status_bitmap ie_page,u32 val,enum rtw89_phy_idx phy_idx)5794 static void rtw89_physts_set_ie_bitmap(struct rtw89_dev *rtwdev,
5795 enum rtw89_phy_status_bitmap ie_page,
5796 u32 val, enum rtw89_phy_idx phy_idx)
5797 {
5798 const struct rtw89_chip_info *chip = rtwdev->chip;
5799 u32 addr;
5800
5801 if (!rtw89_physts_ie_page_valid(&ie_page))
5802 return;
5803
5804 if (chip->chip_id == RTL8852A)
5805 val &= B_PHY_STS_BITMAP_MSK_52A;
5806
5807 addr = rtw89_phy_get_ie_bitmap_addr(ie_page);
5808 rtw89_phy_write32_idx(rtwdev, addr, MASKDWORD, val, phy_idx);
5809 }
5810
rtw89_physts_enable_ie_bitmap(struct rtw89_dev * rtwdev,enum rtw89_phy_status_bitmap bitmap,enum rtw89_phy_status_ie_type ie,bool enable,enum rtw89_phy_idx phy_idx)5811 static void rtw89_physts_enable_ie_bitmap(struct rtw89_dev *rtwdev,
5812 enum rtw89_phy_status_bitmap bitmap,
5813 enum rtw89_phy_status_ie_type ie,
5814 bool enable, enum rtw89_phy_idx phy_idx)
5815 {
5816 u32 val = rtw89_physts_get_ie_bitmap(rtwdev, bitmap, phy_idx);
5817
5818 if (enable)
5819 val |= BIT(ie);
5820 else
5821 val &= ~BIT(ie);
5822
5823 rtw89_physts_set_ie_bitmap(rtwdev, bitmap, val, phy_idx);
5824 }
5825
rtw89_physts_enable_fail_report(struct rtw89_dev * rtwdev,bool enable,enum rtw89_phy_idx phy_idx)5826 static void rtw89_physts_enable_fail_report(struct rtw89_dev *rtwdev,
5827 bool enable,
5828 enum rtw89_phy_idx phy_idx)
5829 {
5830 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
5831 const struct rtw89_physts_regs *physts = phy->physts;
5832
5833 if (enable) {
5834 rtw89_phy_write32_idx_clr(rtwdev, physts->setting_addr,
5835 physts->dis_trigger_fail_mask, phy_idx);
5836 rtw89_phy_write32_idx_clr(rtwdev, physts->setting_addr,
5837 physts->dis_trigger_brk_mask, phy_idx);
5838 } else {
5839 rtw89_phy_write32_idx_set(rtwdev, physts->setting_addr,
5840 physts->dis_trigger_fail_mask, phy_idx);
5841 rtw89_phy_write32_idx_set(rtwdev, physts->setting_addr,
5842 physts->dis_trigger_brk_mask, phy_idx);
5843 }
5844 }
5845
__rtw89_physts_parsing_init(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)5846 static void __rtw89_physts_parsing_init(struct rtw89_dev *rtwdev,
5847 enum rtw89_phy_idx phy_idx)
5848 {
5849 u8 i;
5850
5851 rtw89_physts_enable_fail_report(rtwdev, false, phy_idx);
5852
5853 for (i = 0; i < RTW89_PHYSTS_BITMAP_NUM; i++) {
5854 if (i >= RTW89_CCK_PKT)
5855 rtw89_physts_enable_ie_bitmap(rtwdev, i,
5856 RTW89_PHYSTS_IE09_FTR_0,
5857 true, phy_idx);
5858 if ((i >= RTW89_CCK_BRK && i <= RTW89_VHT_MU) ||
5859 (i >= RTW89_RSVD_9 && i <= RTW89_CCK_PKT))
5860 continue;
5861 rtw89_physts_enable_ie_bitmap(rtwdev, i,
5862 RTW89_PHYSTS_IE24_OFDM_TD_PATH_A,
5863 true, phy_idx);
5864 }
5865 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_VHT_PKT,
5866 RTW89_PHYSTS_IE13_DL_MU_DEF, true, phy_idx);
5867 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_HE_PKT,
5868 RTW89_PHYSTS_IE13_DL_MU_DEF, true, phy_idx);
5869
5870 /* force IE01 for channel index, only channel field is valid */
5871 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_CCK_PKT,
5872 RTW89_PHYSTS_IE01_CMN_OFDM, true, phy_idx);
5873 }
5874
rtw89_physts_parsing_init(struct rtw89_dev * rtwdev)5875 static void rtw89_physts_parsing_init(struct rtw89_dev *rtwdev)
5876 {
5877 __rtw89_physts_parsing_init(rtwdev, RTW89_PHY_0);
5878 if (rtwdev->dbcc_en)
5879 __rtw89_physts_parsing_init(rtwdev, RTW89_PHY_1);
5880 }
5881
rtw89_phy_dig_read_gain_table(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,int type)5882 static void rtw89_phy_dig_read_gain_table(struct rtw89_dev *rtwdev,
5883 struct rtw89_bb_ctx *bb, int type)
5884 {
5885 const struct rtw89_chip_info *chip = rtwdev->chip;
5886 const struct rtw89_phy_dig_gain_cfg *cfg;
5887 struct rtw89_dig_info *dig = &bb->dig;
5888 const char *msg;
5889 u8 i;
5890 s8 gain_base;
5891 s8 *gain_arr;
5892 u32 tmp;
5893
5894 switch (type) {
5895 case RTW89_DIG_GAIN_LNA_G:
5896 gain_arr = dig->lna_gain_g;
5897 gain_base = LNA0_GAIN;
5898 cfg = chip->dig_table->cfg_lna_g;
5899 msg = "lna_gain_g";
5900 break;
5901 case RTW89_DIG_GAIN_TIA_G:
5902 gain_arr = dig->tia_gain_g;
5903 gain_base = TIA0_GAIN_G;
5904 cfg = chip->dig_table->cfg_tia_g;
5905 msg = "tia_gain_g";
5906 break;
5907 case RTW89_DIG_GAIN_LNA_A:
5908 gain_arr = dig->lna_gain_a;
5909 gain_base = LNA0_GAIN;
5910 cfg = chip->dig_table->cfg_lna_a;
5911 msg = "lna_gain_a";
5912 break;
5913 case RTW89_DIG_GAIN_TIA_A:
5914 gain_arr = dig->tia_gain_a;
5915 gain_base = TIA0_GAIN_A;
5916 cfg = chip->dig_table->cfg_tia_a;
5917 msg = "tia_gain_a";
5918 break;
5919 default:
5920 return;
5921 }
5922
5923 for (i = 0; i < cfg->size; i++) {
5924 tmp = rtw89_phy_read32_idx(rtwdev, cfg->table[i].addr,
5925 cfg->table[i].mask, bb->phy_idx);
5926 tmp >>= DIG_GAIN_SHIFT;
5927 gain_arr[i] = sign_extend32(tmp, U4_MAX_BIT) + gain_base;
5928 gain_base += DIG_GAIN;
5929
5930 rtw89_debug(rtwdev, RTW89_DBG_DIG, "%s[%d]=%d\n",
5931 msg, i, gain_arr[i]);
5932 }
5933 }
5934
rtw89_phy_dig_update_gain_para(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)5935 static void rtw89_phy_dig_update_gain_para(struct rtw89_dev *rtwdev,
5936 struct rtw89_bb_ctx *bb)
5937 {
5938 struct rtw89_dig_info *dig = &bb->dig;
5939 u32 tmp;
5940 u8 i;
5941
5942 if (!rtwdev->hal.support_igi)
5943 return;
5944
5945 tmp = rtw89_phy_read32_idx(rtwdev, R_PATH0_IB_PKPW,
5946 B_PATH0_IB_PKPW_MSK, bb->phy_idx);
5947 dig->ib_pkpwr = sign_extend32(tmp >> DIG_GAIN_SHIFT, U8_MAX_BIT);
5948 dig->ib_pbk = rtw89_phy_read32_idx(rtwdev, R_PATH0_IB_PBK,
5949 B_PATH0_IB_PBK_MSK, bb->phy_idx);
5950 rtw89_debug(rtwdev, RTW89_DBG_DIG, "ib_pkpwr=%d, ib_pbk=%d\n",
5951 dig->ib_pkpwr, dig->ib_pbk);
5952
5953 for (i = RTW89_DIG_GAIN_LNA_G; i < RTW89_DIG_GAIN_MAX; i++)
5954 rtw89_phy_dig_read_gain_table(rtwdev, bb, i);
5955 }
5956
5957 static const u8 rssi_nolink = 22;
5958 static const u8 igi_rssi_th[IGI_RSSI_TH_NUM] = {68, 84, 90, 98, 104};
5959 static const u16 fa_th_2g[FA_TH_NUM] = {22, 44, 66, 88};
5960 static const u16 fa_th_5g[FA_TH_NUM] = {4, 8, 12, 16};
5961 static const u16 fa_th_nolink[FA_TH_NUM] = {196, 352, 440, 528};
5962
rtw89_phy_dig_update_rssi_info(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)5963 static void rtw89_phy_dig_update_rssi_info(struct rtw89_dev *rtwdev,
5964 struct rtw89_bb_ctx *bb)
5965 {
5966 struct rtw89_phy_ch_info *ch_info = &bb->ch_info;
5967 struct rtw89_dig_info *dig = &bb->dig;
5968 bool is_linked = rtwdev->total_sta_assoc > 0;
5969
5970 if (is_linked) {
5971 dig->igi_rssi = ch_info->rssi_min >> 1;
5972 } else {
5973 rtw89_debug(rtwdev, RTW89_DBG_DIG, "RSSI update : NO Link\n");
5974 dig->igi_rssi = rssi_nolink;
5975 }
5976 }
5977
rtw89_phy_dig_update_para(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)5978 static void rtw89_phy_dig_update_para(struct rtw89_dev *rtwdev,
5979 struct rtw89_bb_ctx *bb)
5980 {
5981 const struct rtw89_chan *chan = rtw89_mgnt_chan_get(rtwdev, bb->phy_idx);
5982 struct rtw89_dig_info *dig = &bb->dig;
5983 bool is_linked = rtwdev->total_sta_assoc > 0;
5984 const u16 *fa_th_src = NULL;
5985
5986 switch (chan->band_type) {
5987 case RTW89_BAND_2G:
5988 dig->lna_gain = dig->lna_gain_g;
5989 dig->tia_gain = dig->tia_gain_g;
5990 fa_th_src = is_linked ? fa_th_2g : fa_th_nolink;
5991 dig->force_gaincode_idx_en = false;
5992 dig->dyn_pd_th_en = true;
5993 break;
5994 case RTW89_BAND_5G:
5995 default:
5996 dig->lna_gain = dig->lna_gain_a;
5997 dig->tia_gain = dig->tia_gain_a;
5998 fa_th_src = is_linked ? fa_th_5g : fa_th_nolink;
5999 dig->force_gaincode_idx_en = true;
6000 dig->dyn_pd_th_en = true;
6001 break;
6002 }
6003 memcpy(dig->fa_th, fa_th_src, sizeof(dig->fa_th));
6004 memcpy(dig->igi_rssi_th, igi_rssi_th, sizeof(dig->igi_rssi_th));
6005 }
6006
6007 static const u8 pd_low_th_offset = 16, dynamic_igi_min = 0x20;
6008 static const u8 igi_max_performance_mode = 0x5a;
6009 static const u8 dynamic_pd_threshold_max;
6010
rtw89_phy_dig_para_reset(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)6011 static void rtw89_phy_dig_para_reset(struct rtw89_dev *rtwdev,
6012 struct rtw89_bb_ctx *bb)
6013 {
6014 struct rtw89_dig_info *dig = &bb->dig;
6015
6016 dig->cur_gaincode.lna_idx = LNA_IDX_MAX;
6017 dig->cur_gaincode.tia_idx = TIA_IDX_MAX;
6018 dig->cur_gaincode.rxb_idx = RXB_IDX_MAX;
6019 dig->force_gaincode.lna_idx = LNA_IDX_MAX;
6020 dig->force_gaincode.tia_idx = TIA_IDX_MAX;
6021 dig->force_gaincode.rxb_idx = RXB_IDX_MAX;
6022
6023 dig->dyn_igi_max = igi_max_performance_mode;
6024 dig->dyn_igi_min = dynamic_igi_min;
6025 dig->dyn_pd_th_max = dynamic_pd_threshold_max;
6026 dig->pd_low_th_ofst = pd_low_th_offset;
6027 dig->is_linked_pre = false;
6028 }
6029
__rtw89_phy_dig_init(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)6030 static void __rtw89_phy_dig_init(struct rtw89_dev *rtwdev,
6031 struct rtw89_bb_ctx *bb)
6032 {
6033 rtw89_debug(rtwdev, RTW89_DBG_DIG, "BB-%d dig_init\n", bb->phy_idx);
6034
6035 rtw89_phy_dig_update_gain_para(rtwdev, bb);
6036 rtw89_phy_dig_reset(rtwdev, bb);
6037 }
6038
rtw89_phy_dig_init(struct rtw89_dev * rtwdev)6039 static void rtw89_phy_dig_init(struct rtw89_dev *rtwdev)
6040 {
6041 struct rtw89_bb_ctx *bb;
6042
6043 rtw89_for_each_capab_bb(rtwdev, bb)
6044 __rtw89_phy_dig_init(rtwdev, bb);
6045 }
6046
rtw89_phy_dig_lna_idx_by_rssi(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,u8 rssi)6047 static u8 rtw89_phy_dig_lna_idx_by_rssi(struct rtw89_dev *rtwdev,
6048 struct rtw89_bb_ctx *bb, u8 rssi)
6049 {
6050 struct rtw89_dig_info *dig = &bb->dig;
6051 u8 lna_idx;
6052
6053 if (rssi < dig->igi_rssi_th[0])
6054 lna_idx = RTW89_DIG_GAIN_LNA_IDX6;
6055 else if (rssi < dig->igi_rssi_th[1])
6056 lna_idx = RTW89_DIG_GAIN_LNA_IDX5;
6057 else if (rssi < dig->igi_rssi_th[2])
6058 lna_idx = RTW89_DIG_GAIN_LNA_IDX4;
6059 else if (rssi < dig->igi_rssi_th[3])
6060 lna_idx = RTW89_DIG_GAIN_LNA_IDX3;
6061 else if (rssi < dig->igi_rssi_th[4])
6062 lna_idx = RTW89_DIG_GAIN_LNA_IDX2;
6063 else
6064 lna_idx = RTW89_DIG_GAIN_LNA_IDX1;
6065
6066 return lna_idx;
6067 }
6068
rtw89_phy_dig_tia_idx_by_rssi(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,u8 rssi)6069 static u8 rtw89_phy_dig_tia_idx_by_rssi(struct rtw89_dev *rtwdev,
6070 struct rtw89_bb_ctx *bb, u8 rssi)
6071 {
6072 struct rtw89_dig_info *dig = &bb->dig;
6073 u8 tia_idx;
6074
6075 if (rssi < dig->igi_rssi_th[0])
6076 tia_idx = RTW89_DIG_GAIN_TIA_IDX1;
6077 else
6078 tia_idx = RTW89_DIG_GAIN_TIA_IDX0;
6079
6080 return tia_idx;
6081 }
6082
6083 #define IB_PBK_BASE 110
6084 #define WB_RSSI_BASE 10
rtw89_phy_dig_rxb_idx_by_rssi(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,u8 rssi,struct rtw89_agc_gaincode_set * set)6085 static u8 rtw89_phy_dig_rxb_idx_by_rssi(struct rtw89_dev *rtwdev,
6086 struct rtw89_bb_ctx *bb, u8 rssi,
6087 struct rtw89_agc_gaincode_set *set)
6088 {
6089 struct rtw89_dig_info *dig = &bb->dig;
6090 s8 lna_gain = dig->lna_gain[set->lna_idx];
6091 s8 tia_gain = dig->tia_gain[set->tia_idx];
6092 s32 wb_rssi = rssi + lna_gain + tia_gain;
6093 s32 rxb_idx_tmp = IB_PBK_BASE + WB_RSSI_BASE;
6094 u8 rxb_idx;
6095
6096 rxb_idx_tmp += dig->ib_pkpwr - dig->ib_pbk - wb_rssi;
6097 rxb_idx = clamp_t(s32, rxb_idx_tmp, RXB_IDX_MIN, RXB_IDX_MAX);
6098
6099 rtw89_debug(rtwdev, RTW89_DBG_DIG, "wb_rssi=%03d, rxb_idx_tmp=%03d\n",
6100 wb_rssi, rxb_idx_tmp);
6101
6102 return rxb_idx;
6103 }
6104
rtw89_phy_dig_gaincode_by_rssi(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,u8 rssi,struct rtw89_agc_gaincode_set * set)6105 static void rtw89_phy_dig_gaincode_by_rssi(struct rtw89_dev *rtwdev,
6106 struct rtw89_bb_ctx *bb, u8 rssi,
6107 struct rtw89_agc_gaincode_set *set)
6108 {
6109 set->lna_idx = rtw89_phy_dig_lna_idx_by_rssi(rtwdev, bb, rssi);
6110 set->tia_idx = rtw89_phy_dig_tia_idx_by_rssi(rtwdev, bb, rssi);
6111 set->rxb_idx = rtw89_phy_dig_rxb_idx_by_rssi(rtwdev, bb, rssi, set);
6112
6113 rtw89_debug(rtwdev, RTW89_DBG_DIG,
6114 "final_rssi=%03d, (lna,tia,rab)=(%d,%d,%02d)\n",
6115 rssi, set->lna_idx, set->tia_idx, set->rxb_idx);
6116 }
6117
6118 #define IGI_OFFSET_MAX 25
6119 #define IGI_OFFSET_MUL 2
rtw89_phy_dig_igi_offset_by_env(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)6120 static void rtw89_phy_dig_igi_offset_by_env(struct rtw89_dev *rtwdev,
6121 struct rtw89_bb_ctx *bb)
6122 {
6123 struct rtw89_dig_info *dig = &bb->dig;
6124 struct rtw89_env_monitor_info *env = &bb->env_monitor;
6125 enum rtw89_dig_noisy_level noisy_lv;
6126 u8 igi_offset = dig->fa_rssi_ofst;
6127 u16 fa_ratio = 0;
6128
6129 fa_ratio = env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil;
6130
6131 if (fa_ratio < dig->fa_th[0])
6132 noisy_lv = RTW89_DIG_NOISY_LEVEL0;
6133 else if (fa_ratio < dig->fa_th[1])
6134 noisy_lv = RTW89_DIG_NOISY_LEVEL1;
6135 else if (fa_ratio < dig->fa_th[2])
6136 noisy_lv = RTW89_DIG_NOISY_LEVEL2;
6137 else if (fa_ratio < dig->fa_th[3])
6138 noisy_lv = RTW89_DIG_NOISY_LEVEL3;
6139 else
6140 noisy_lv = RTW89_DIG_NOISY_LEVEL_MAX;
6141
6142 if (noisy_lv == RTW89_DIG_NOISY_LEVEL0 && igi_offset < 2)
6143 igi_offset = 0;
6144 else
6145 igi_offset += noisy_lv * IGI_OFFSET_MUL;
6146
6147 igi_offset = min_t(u8, igi_offset, IGI_OFFSET_MAX);
6148 dig->fa_rssi_ofst = igi_offset;
6149
6150 rtw89_debug(rtwdev, RTW89_DBG_DIG,
6151 "fa_th: [+6 (%d) +4 (%d) +2 (%d) 0 (%d) -2 ]\n",
6152 dig->fa_th[3], dig->fa_th[2], dig->fa_th[1], dig->fa_th[0]);
6153
6154 rtw89_debug(rtwdev, RTW89_DBG_DIG,
6155 "fa(CCK,OFDM,ALL)=(%d,%d,%d)%%, noisy_lv=%d, ofst=%d\n",
6156 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil,
6157 env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil,
6158 noisy_lv, igi_offset);
6159 }
6160
rtw89_phy_dig_set_lna_idx(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,u8 lna_idx)6161 static void rtw89_phy_dig_set_lna_idx(struct rtw89_dev *rtwdev,
6162 struct rtw89_bb_ctx *bb, u8 lna_idx)
6163 {
6164 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs;
6165
6166 rtw89_phy_write32_idx(rtwdev, dig_regs->p0_lna_init.addr,
6167 dig_regs->p0_lna_init.mask, lna_idx, bb->phy_idx);
6168 rtw89_phy_write32_idx(rtwdev, dig_regs->p1_lna_init.addr,
6169 dig_regs->p1_lna_init.mask, lna_idx, bb->phy_idx);
6170 }
6171
rtw89_phy_dig_set_tia_idx(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,u8 tia_idx)6172 static void rtw89_phy_dig_set_tia_idx(struct rtw89_dev *rtwdev,
6173 struct rtw89_bb_ctx *bb, u8 tia_idx)
6174 {
6175 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs;
6176
6177 rtw89_phy_write32_idx(rtwdev, dig_regs->p0_tia_init.addr,
6178 dig_regs->p0_tia_init.mask, tia_idx, bb->phy_idx);
6179 rtw89_phy_write32_idx(rtwdev, dig_regs->p1_tia_init.addr,
6180 dig_regs->p1_tia_init.mask, tia_idx, bb->phy_idx);
6181 }
6182
rtw89_phy_dig_set_rxb_idx(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,u8 rxb_idx)6183 static void rtw89_phy_dig_set_rxb_idx(struct rtw89_dev *rtwdev,
6184 struct rtw89_bb_ctx *bb, u8 rxb_idx)
6185 {
6186 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs;
6187
6188 rtw89_phy_write32_idx(rtwdev, dig_regs->p0_rxb_init.addr,
6189 dig_regs->p0_rxb_init.mask, rxb_idx, bb->phy_idx);
6190 rtw89_phy_write32_idx(rtwdev, dig_regs->p1_rxb_init.addr,
6191 dig_regs->p1_rxb_init.mask, rxb_idx, bb->phy_idx);
6192 }
6193
rtw89_phy_dig_set_igi_cr(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,const struct rtw89_agc_gaincode_set set)6194 static void rtw89_phy_dig_set_igi_cr(struct rtw89_dev *rtwdev,
6195 struct rtw89_bb_ctx *bb,
6196 const struct rtw89_agc_gaincode_set set)
6197 {
6198 if (!rtwdev->hal.support_igi)
6199 return;
6200
6201 rtw89_phy_dig_set_lna_idx(rtwdev, bb, set.lna_idx);
6202 rtw89_phy_dig_set_tia_idx(rtwdev, bb, set.tia_idx);
6203 rtw89_phy_dig_set_rxb_idx(rtwdev, bb, set.rxb_idx);
6204
6205 rtw89_debug(rtwdev, RTW89_DBG_DIG, "Set (lna,tia,rxb)=((%d,%d,%02d))\n",
6206 set.lna_idx, set.tia_idx, set.rxb_idx);
6207 }
6208
rtw89_phy_dig_sdagc_follow_pagc_config(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,bool enable)6209 static void rtw89_phy_dig_sdagc_follow_pagc_config(struct rtw89_dev *rtwdev,
6210 struct rtw89_bb_ctx *bb,
6211 bool enable)
6212 {
6213 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs;
6214
6215 rtw89_phy_write32_idx(rtwdev, dig_regs->p0_p20_pagcugc_en.addr,
6216 dig_regs->p0_p20_pagcugc_en.mask, enable, bb->phy_idx);
6217 rtw89_phy_write32_idx(rtwdev, dig_regs->p0_s20_pagcugc_en.addr,
6218 dig_regs->p0_s20_pagcugc_en.mask, enable, bb->phy_idx);
6219 rtw89_phy_write32_idx(rtwdev, dig_regs->p1_p20_pagcugc_en.addr,
6220 dig_regs->p1_p20_pagcugc_en.mask, enable, bb->phy_idx);
6221 rtw89_phy_write32_idx(rtwdev, dig_regs->p1_s20_pagcugc_en.addr,
6222 dig_regs->p1_s20_pagcugc_en.mask, enable, bb->phy_idx);
6223
6224 rtw89_debug(rtwdev, RTW89_DBG_DIG, "sdagc_follow_pagc=%d\n", enable);
6225 }
6226
rtw89_phy_dig_config_igi(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)6227 static void rtw89_phy_dig_config_igi(struct rtw89_dev *rtwdev,
6228 struct rtw89_bb_ctx *bb)
6229 {
6230 struct rtw89_dig_info *dig = &bb->dig;
6231
6232 if (!rtwdev->hal.support_igi)
6233 return;
6234
6235 if (dig->force_gaincode_idx_en) {
6236 rtw89_phy_dig_set_igi_cr(rtwdev, bb, dig->force_gaincode);
6237 rtw89_debug(rtwdev, RTW89_DBG_DIG,
6238 "Force gaincode index enabled.\n");
6239 } else {
6240 rtw89_phy_dig_gaincode_by_rssi(rtwdev, bb, dig->igi_fa_rssi,
6241 &dig->cur_gaincode);
6242 rtw89_phy_dig_set_igi_cr(rtwdev, bb, dig->cur_gaincode);
6243 }
6244 }
6245
rtw89_phy_dig_dyn_pd_th(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,u8 rssi,bool enable)6246 static void rtw89_phy_dig_dyn_pd_th(struct rtw89_dev *rtwdev,
6247 struct rtw89_bb_ctx *bb,
6248 u8 rssi, bool enable)
6249 {
6250 const struct rtw89_chan *chan = rtw89_mgnt_chan_get(rtwdev, bb->phy_idx);
6251 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs;
6252 enum rtw89_bandwidth cbw = chan->band_width;
6253 struct rtw89_dig_info *dig = &bb->dig;
6254 u8 final_rssi = 0, under_region = dig->pd_low_th_ofst;
6255 u8 ofdm_cca_th;
6256 s8 cck_cca_th;
6257 u32 pd_val = 0;
6258
6259 if (rtwdev->chip->chip_gen == RTW89_CHIP_AX)
6260 under_region += PD_TH_SB_FLTR_CMP_VAL;
6261
6262 switch (cbw) {
6263 case RTW89_CHANNEL_WIDTH_40:
6264 under_region += PD_TH_BW40_CMP_VAL;
6265 break;
6266 case RTW89_CHANNEL_WIDTH_80:
6267 under_region += PD_TH_BW80_CMP_VAL;
6268 break;
6269 case RTW89_CHANNEL_WIDTH_160:
6270 under_region += PD_TH_BW160_CMP_VAL;
6271 break;
6272 case RTW89_CHANNEL_WIDTH_20:
6273 fallthrough;
6274 default:
6275 under_region += PD_TH_BW20_CMP_VAL;
6276 break;
6277 }
6278
6279 dig->dyn_pd_th_max = dig->igi_rssi;
6280
6281 final_rssi = min_t(u8, rssi, dig->igi_rssi);
6282 ofdm_cca_th = clamp_t(u8, final_rssi, PD_TH_MIN_RSSI + under_region,
6283 PD_TH_MAX_RSSI + under_region);
6284
6285 if (enable) {
6286 pd_val = (ofdm_cca_th - under_region - PD_TH_MIN_RSSI) >> 1;
6287 rtw89_debug(rtwdev, RTW89_DBG_DIG,
6288 "igi=%d, ofdm_ccaTH=%d, backoff=%d, PD_low=%d\n",
6289 final_rssi, ofdm_cca_th, under_region, pd_val);
6290 } else {
6291 rtw89_debug(rtwdev, RTW89_DBG_DIG,
6292 "Dynamic PD th disabled, Set PD_low_bd=0\n");
6293 }
6294
6295 rtw89_phy_write32_idx(rtwdev, dig_regs->seg0_pd_reg,
6296 dig_regs->pd_lower_bound_mask, pd_val, bb->phy_idx);
6297 rtw89_phy_write32_idx(rtwdev, dig_regs->seg0_pd_reg,
6298 dig_regs->pd_spatial_reuse_en, enable, bb->phy_idx);
6299
6300 if (!rtwdev->hal.support_cckpd)
6301 return;
6302
6303 cck_cca_th = max_t(s8, final_rssi - under_region, CCKPD_TH_MIN_RSSI);
6304 pd_val = (u32)(cck_cca_th - IGI_RSSI_MAX);
6305
6306 rtw89_debug(rtwdev, RTW89_DBG_DIG,
6307 "igi=%d, cck_ccaTH=%d, backoff=%d, cck_PD_low=((%d))dB\n",
6308 final_rssi, cck_cca_th, under_region, pd_val);
6309
6310 rtw89_phy_write32_idx(rtwdev, dig_regs->bmode_pd_reg,
6311 dig_regs->bmode_cca_rssi_limit_en, enable, bb->phy_idx);
6312 rtw89_phy_write32_idx(rtwdev, dig_regs->bmode_pd_lower_bound_reg,
6313 dig_regs->bmode_rssi_nocca_low_th_mask, pd_val, bb->phy_idx);
6314 }
6315
rtw89_phy_dig_reset(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)6316 void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb)
6317 {
6318 struct rtw89_dig_info *dig = &bb->dig;
6319
6320 dig->bypass_dig = false;
6321 rtw89_phy_dig_para_reset(rtwdev, bb);
6322 rtw89_phy_dig_set_igi_cr(rtwdev, bb, dig->force_gaincode);
6323 rtw89_phy_dig_dyn_pd_th(rtwdev, bb, rssi_nolink, false);
6324 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, bb, false);
6325 rtw89_phy_dig_update_para(rtwdev, bb);
6326 }
6327
6328 #define IGI_RSSI_MIN 10
6329 #define ABS_IGI_MIN 0xc
__rtw89_phy_dig(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)6330 static void __rtw89_phy_dig(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb)
6331 {
6332 struct rtw89_dig_info *dig = &bb->dig;
6333 bool is_linked = rtwdev->total_sta_assoc > 0;
6334 u8 igi_min;
6335
6336 if (unlikely(dig->bypass_dig)) {
6337 dig->bypass_dig = false;
6338 return;
6339 }
6340
6341 rtw89_debug(rtwdev, RTW89_DBG_DIG, "BB-%d dig track\n", bb->phy_idx);
6342
6343 rtw89_phy_dig_update_rssi_info(rtwdev, bb);
6344
6345 if (!dig->is_linked_pre && is_linked) {
6346 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First connected\n");
6347 rtw89_phy_dig_update_para(rtwdev, bb);
6348 dig->igi_fa_rssi = dig->igi_rssi;
6349 } else if (dig->is_linked_pre && !is_linked) {
6350 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First disconnected\n");
6351 rtw89_phy_dig_update_para(rtwdev, bb);
6352 dig->igi_fa_rssi = dig->igi_rssi;
6353 }
6354 dig->is_linked_pre = is_linked;
6355
6356 rtw89_phy_dig_igi_offset_by_env(rtwdev, bb);
6357
6358 igi_min = max_t(int, dig->igi_rssi - IGI_RSSI_MIN, 0);
6359 dig->dyn_igi_max = min(igi_min + IGI_OFFSET_MAX, igi_max_performance_mode);
6360 dig->dyn_igi_min = max(igi_min, ABS_IGI_MIN);
6361
6362 if (dig->dyn_igi_max >= dig->dyn_igi_min) {
6363 dig->igi_fa_rssi += dig->fa_rssi_ofst;
6364 dig->igi_fa_rssi = clamp(dig->igi_fa_rssi, dig->dyn_igi_min,
6365 dig->dyn_igi_max);
6366 } else {
6367 dig->igi_fa_rssi = dig->dyn_igi_max;
6368 }
6369
6370 rtw89_debug(rtwdev, RTW89_DBG_DIG,
6371 "rssi=%03d, dyn_joint(max,min)=(%d,%d), final_rssi=%d\n",
6372 dig->igi_rssi, dig->dyn_igi_max, dig->dyn_igi_min,
6373 dig->igi_fa_rssi);
6374
6375 rtw89_phy_dig_config_igi(rtwdev, bb);
6376
6377 rtw89_phy_dig_dyn_pd_th(rtwdev, bb, dig->igi_fa_rssi, dig->dyn_pd_th_en);
6378
6379 if (dig->dyn_pd_th_en && dig->igi_fa_rssi > dig->dyn_pd_th_max)
6380 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, bb, true);
6381 else
6382 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, bb, false);
6383 }
6384
rtw89_phy_dig(struct rtw89_dev * rtwdev)6385 void rtw89_phy_dig(struct rtw89_dev *rtwdev)
6386 {
6387 struct rtw89_bb_ctx *bb;
6388
6389 rtw89_for_each_active_bb(rtwdev, bb)
6390 __rtw89_phy_dig(rtwdev, bb);
6391 }
6392
__rtw89_phy_tx_path_div_sta_iter(struct rtw89_dev * rtwdev,struct rtw89_sta_link * rtwsta_link)6393 static void __rtw89_phy_tx_path_div_sta_iter(struct rtw89_dev *rtwdev,
6394 struct rtw89_sta_link *rtwsta_link)
6395 {
6396 struct rtw89_hal *hal = &rtwdev->hal;
6397 u8 rssi_a, rssi_b;
6398 u32 candidate;
6399
6400 rssi_a = ewma_rssi_read(&rtwsta_link->rssi[RF_PATH_A]);
6401 rssi_b = ewma_rssi_read(&rtwsta_link->rssi[RF_PATH_B]);
6402
6403 if (rssi_a > rssi_b + RTW89_TX_DIV_RSSI_RAW_TH)
6404 candidate = RF_A;
6405 else if (rssi_b > rssi_a + RTW89_TX_DIV_RSSI_RAW_TH)
6406 candidate = RF_B;
6407 else
6408 return;
6409
6410 if (hal->antenna_tx == candidate)
6411 return;
6412
6413 hal->antenna_tx = candidate;
6414 rtw89_fw_h2c_txpath_cmac_tbl(rtwdev, rtwsta_link);
6415
6416 if (hal->antenna_tx == RF_A) {
6417 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, B_P0_RFMODE_MUX, 0x12);
6418 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, B_P1_RFMODE_MUX, 0x11);
6419 } else if (hal->antenna_tx == RF_B) {
6420 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, B_P0_RFMODE_MUX, 0x11);
6421 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, B_P1_RFMODE_MUX, 0x12);
6422 }
6423 }
6424
rtw89_phy_tx_path_div_sta_iter(void * data,struct ieee80211_sta * sta)6425 static void rtw89_phy_tx_path_div_sta_iter(void *data, struct ieee80211_sta *sta)
6426 {
6427 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
6428 struct rtw89_dev *rtwdev = rtwsta->rtwdev;
6429 struct rtw89_vif *rtwvif = rtwsta->rtwvif;
6430 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
6431 struct rtw89_vif_link *rtwvif_link;
6432 struct rtw89_sta_link *rtwsta_link;
6433 unsigned int link_id;
6434 bool *done = data;
6435
6436 if (WARN(ieee80211_vif_is_mld(vif), "MLD mix path_div\n"))
6437 return;
6438
6439 if (sta->tdls)
6440 return;
6441
6442 if (*done)
6443 return;
6444
6445 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) {
6446 rtwvif_link = rtwsta_link->rtwvif_link;
6447 if (rtwvif_link->wifi_role != RTW89_WIFI_ROLE_STATION)
6448 continue;
6449
6450 *done = true;
6451 __rtw89_phy_tx_path_div_sta_iter(rtwdev, rtwsta_link);
6452 return;
6453 }
6454 }
6455
rtw89_phy_tx_path_div_track(struct rtw89_dev * rtwdev)6456 void rtw89_phy_tx_path_div_track(struct rtw89_dev *rtwdev)
6457 {
6458 struct rtw89_hal *hal = &rtwdev->hal;
6459 bool done = false;
6460
6461 if (!hal->tx_path_diversity)
6462 return;
6463
6464 ieee80211_iterate_stations_atomic(rtwdev->hw,
6465 rtw89_phy_tx_path_div_sta_iter,
6466 &done);
6467 }
6468
6469 #define ANTDIV_MAIN 0
6470 #define ANTDIV_AUX 1
6471
rtw89_phy_antdiv_set_ant(struct rtw89_dev * rtwdev)6472 static void rtw89_phy_antdiv_set_ant(struct rtw89_dev *rtwdev)
6473 {
6474 struct rtw89_hal *hal = &rtwdev->hal;
6475 u8 default_ant, optional_ant;
6476
6477 if (!hal->ant_diversity || hal->antenna_tx == 0)
6478 return;
6479
6480 if (hal->antenna_tx == RF_B) {
6481 default_ant = ANTDIV_AUX;
6482 optional_ant = ANTDIV_MAIN;
6483 } else {
6484 default_ant = ANTDIV_MAIN;
6485 optional_ant = ANTDIV_AUX;
6486 }
6487
6488 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_CGCS_CTRL,
6489 default_ant, RTW89_PHY_0);
6490 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_RX_ORI,
6491 default_ant, RTW89_PHY_0);
6492 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_RX_ALT,
6493 optional_ant, RTW89_PHY_0);
6494 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_TX_ORI,
6495 default_ant, RTW89_PHY_0);
6496 }
6497
rtw89_phy_swap_hal_antenna(struct rtw89_dev * rtwdev)6498 static void rtw89_phy_swap_hal_antenna(struct rtw89_dev *rtwdev)
6499 {
6500 struct rtw89_hal *hal = &rtwdev->hal;
6501
6502 hal->antenna_rx = hal->antenna_rx == RF_A ? RF_B : RF_A;
6503 hal->antenna_tx = hal->antenna_rx;
6504 }
6505
rtw89_phy_antdiv_decision_state(struct rtw89_dev * rtwdev)6506 static void rtw89_phy_antdiv_decision_state(struct rtw89_dev *rtwdev)
6507 {
6508 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
6509 struct rtw89_hal *hal = &rtwdev->hal;
6510 bool no_change = false;
6511 u8 main_rssi, aux_rssi;
6512 u8 main_evm, aux_evm;
6513 u32 candidate;
6514
6515 antdiv->get_stats = false;
6516 antdiv->training_count = 0;
6517
6518 main_rssi = rtw89_phy_antdiv_sts_instance_get_rssi(&antdiv->main_stats);
6519 main_evm = rtw89_phy_antdiv_sts_instance_get_evm(&antdiv->main_stats);
6520 aux_rssi = rtw89_phy_antdiv_sts_instance_get_rssi(&antdiv->aux_stats);
6521 aux_evm = rtw89_phy_antdiv_sts_instance_get_evm(&antdiv->aux_stats);
6522
6523 if (main_evm > aux_evm + ANTDIV_EVM_DIFF_TH)
6524 candidate = RF_A;
6525 else if (aux_evm > main_evm + ANTDIV_EVM_DIFF_TH)
6526 candidate = RF_B;
6527 else if (main_rssi > aux_rssi + RTW89_TX_DIV_RSSI_RAW_TH)
6528 candidate = RF_A;
6529 else if (aux_rssi > main_rssi + RTW89_TX_DIV_RSSI_RAW_TH)
6530 candidate = RF_B;
6531 else
6532 no_change = true;
6533
6534 if (no_change) {
6535 /* swap back from training antenna to original */
6536 rtw89_phy_swap_hal_antenna(rtwdev);
6537 return;
6538 }
6539
6540 hal->antenna_tx = candidate;
6541 hal->antenna_rx = candidate;
6542 }
6543
rtw89_phy_antdiv_training_state(struct rtw89_dev * rtwdev)6544 static void rtw89_phy_antdiv_training_state(struct rtw89_dev *rtwdev)
6545 {
6546 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
6547 u64 state_period;
6548
6549 if (antdiv->training_count % 2 == 0) {
6550 if (antdiv->training_count == 0)
6551 rtw89_phy_antdiv_sts_reset(rtwdev);
6552
6553 antdiv->get_stats = true;
6554 state_period = msecs_to_jiffies(ANTDIV_TRAINNING_INTVL);
6555 } else {
6556 antdiv->get_stats = false;
6557 state_period = msecs_to_jiffies(ANTDIV_DELAY);
6558
6559 rtw89_phy_swap_hal_antenna(rtwdev);
6560 rtw89_phy_antdiv_set_ant(rtwdev);
6561 }
6562
6563 antdiv->training_count++;
6564 wiphy_delayed_work_queue(rtwdev->hw->wiphy, &rtwdev->antdiv_work,
6565 state_period);
6566 }
6567
rtw89_phy_antdiv_work(struct wiphy * wiphy,struct wiphy_work * work)6568 void rtw89_phy_antdiv_work(struct wiphy *wiphy, struct wiphy_work *work)
6569 {
6570 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
6571 antdiv_work.work);
6572 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
6573
6574 lockdep_assert_wiphy(wiphy);
6575
6576 if (antdiv->training_count <= ANTDIV_TRAINNING_CNT) {
6577 rtw89_phy_antdiv_training_state(rtwdev);
6578 } else {
6579 rtw89_phy_antdiv_decision_state(rtwdev);
6580 rtw89_phy_antdiv_set_ant(rtwdev);
6581 }
6582 }
6583
rtw89_phy_antdiv_track(struct rtw89_dev * rtwdev)6584 void rtw89_phy_antdiv_track(struct rtw89_dev *rtwdev)
6585 {
6586 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
6587 struct rtw89_hal *hal = &rtwdev->hal;
6588 u8 rssi, rssi_pre;
6589
6590 if (!hal->ant_diversity || hal->ant_diversity_fixed)
6591 return;
6592
6593 rssi = rtw89_phy_antdiv_sts_instance_get_rssi(&antdiv->target_stats);
6594 rssi_pre = antdiv->rssi_pre;
6595 antdiv->rssi_pre = rssi;
6596 rtw89_phy_antdiv_sts_instance_reset(&antdiv->target_stats);
6597
6598 if (abs((int)rssi - (int)rssi_pre) < ANTDIV_RSSI_DIFF_TH)
6599 return;
6600
6601 antdiv->training_count = 0;
6602 wiphy_delayed_work_queue(rtwdev->hw->wiphy, &rtwdev->antdiv_work, 0);
6603 }
6604
__rtw89_phy_env_monitor_init(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)6605 static void __rtw89_phy_env_monitor_init(struct rtw89_dev *rtwdev,
6606 struct rtw89_bb_ctx *bb)
6607 {
6608 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
6609 "BB-%d env_monitor init\n", bb->phy_idx);
6610
6611 rtw89_phy_ccx_top_setting_init(rtwdev, bb);
6612 rtw89_phy_ifs_clm_setting_init(rtwdev, bb);
6613 }
6614
rtw89_phy_env_monitor_init(struct rtw89_dev * rtwdev)6615 static void rtw89_phy_env_monitor_init(struct rtw89_dev *rtwdev)
6616 {
6617 struct rtw89_bb_ctx *bb;
6618
6619 rtw89_for_each_capab_bb(rtwdev, bb)
6620 __rtw89_phy_env_monitor_init(rtwdev, bb);
6621 }
6622
__rtw89_phy_edcca_init(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)6623 static void __rtw89_phy_edcca_init(struct rtw89_dev *rtwdev,
6624 struct rtw89_bb_ctx *bb)
6625 {
6626 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs;
6627 struct rtw89_edcca_bak *edcca_bak = &bb->edcca_bak;
6628
6629 rtw89_debug(rtwdev, RTW89_DBG_EDCCA, "BB-%d edcca init\n", bb->phy_idx);
6630
6631 memset(edcca_bak, 0, sizeof(*edcca_bak));
6632
6633 if (rtwdev->chip->chip_id == RTL8922A && rtwdev->hal.cv == CHIP_CAV) {
6634 rtw89_phy_set_phy_regs(rtwdev, R_TXGATING, B_TXGATING_EN, 0);
6635 rtw89_phy_set_phy_regs(rtwdev, R_CTLTOP, B_CTLTOP_VAL, 2);
6636 rtw89_phy_set_phy_regs(rtwdev, R_CTLTOP, B_CTLTOP_ON, 1);
6637 rtw89_phy_set_phy_regs(rtwdev, R_SPOOF_CG, B_SPOOF_CG_EN, 0);
6638 rtw89_phy_set_phy_regs(rtwdev, R_DFS_FFT_CG, B_DFS_CG_EN, 0);
6639 rtw89_phy_set_phy_regs(rtwdev, R_DFS_FFT_CG, B_DFS_FFT_EN, 0);
6640 rtw89_phy_set_phy_regs(rtwdev, R_SEGSND, B_SEGSND_EN, 0);
6641 rtw89_phy_set_phy_regs(rtwdev, R_SEGSND, B_SEGSND_EN, 1);
6642 rtw89_phy_set_phy_regs(rtwdev, R_DFS_FFT_CG, B_DFS_FFT_EN, 1);
6643 }
6644
6645 rtw89_phy_write32_idx(rtwdev, edcca_regs->tx_collision_t2r_st,
6646 edcca_regs->tx_collision_t2r_st_mask, 0x29, bb->phy_idx);
6647 }
6648
rtw89_phy_edcca_init(struct rtw89_dev * rtwdev)6649 static void rtw89_phy_edcca_init(struct rtw89_dev *rtwdev)
6650 {
6651 struct rtw89_bb_ctx *bb;
6652
6653 rtw89_for_each_capab_bb(rtwdev, bb)
6654 __rtw89_phy_edcca_init(rtwdev, bb);
6655 }
6656
rtw89_phy_dm_init(struct rtw89_dev * rtwdev)6657 void rtw89_phy_dm_init(struct rtw89_dev *rtwdev)
6658 {
6659 rtw89_phy_stat_init(rtwdev);
6660
6661 rtw89_chip_bb_sethw(rtwdev);
6662
6663 rtw89_phy_env_monitor_init(rtwdev);
6664 rtw89_physts_parsing_init(rtwdev);
6665 rtw89_phy_dig_init(rtwdev);
6666 rtw89_phy_cfo_init(rtwdev);
6667 rtw89_phy_bb_wrap_init(rtwdev);
6668 rtw89_phy_edcca_init(rtwdev);
6669 rtw89_phy_ch_info_init(rtwdev);
6670 rtw89_phy_ul_tb_info_init(rtwdev);
6671 rtw89_phy_antdiv_init(rtwdev);
6672 rtw89_chip_rfe_gpio(rtwdev);
6673 rtw89_phy_antdiv_set_ant(rtwdev);
6674
6675 rtw89_chip_rfk_hw_init(rtwdev);
6676 rtw89_phy_init_rf_nctl(rtwdev);
6677 rtw89_chip_rfk_init(rtwdev);
6678 rtw89_chip_set_txpwr_ctrl(rtwdev);
6679 rtw89_chip_power_trim(rtwdev);
6680 rtw89_chip_cfg_txrx_path(rtwdev);
6681 }
6682
rtw89_phy_dm_reinit(struct rtw89_dev * rtwdev)6683 void rtw89_phy_dm_reinit(struct rtw89_dev *rtwdev)
6684 {
6685 rtw89_phy_env_monitor_init(rtwdev);
6686 rtw89_physts_parsing_init(rtwdev);
6687 }
6688
rtw89_phy_set_bss_color(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)6689 void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev,
6690 struct rtw89_vif_link *rtwvif_link)
6691 {
6692 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
6693 const struct rtw89_chip_info *chip = rtwdev->chip;
6694 const struct rtw89_reg_def *bss_clr_vld = &chip->bss_clr_vld;
6695 enum rtw89_phy_idx phy_idx = rtwvif_link->phy_idx;
6696 struct ieee80211_bss_conf *bss_conf;
6697 u8 bss_color;
6698
6699 rcu_read_lock();
6700
6701 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true);
6702 if (!bss_conf->he_support || !vif->cfg.assoc) {
6703 rcu_read_unlock();
6704 return;
6705 }
6706
6707 bss_color = bss_conf->he_bss_color.color;
6708
6709 rcu_read_unlock();
6710
6711 rtw89_phy_write32_idx(rtwdev, bss_clr_vld->addr, bss_clr_vld->mask, 0x1,
6712 phy_idx);
6713 rtw89_phy_write32_idx(rtwdev, chip->bss_clr_map_reg, B_BSS_CLR_MAP_TGT,
6714 bss_color, phy_idx);
6715 rtw89_phy_write32_idx(rtwdev, chip->bss_clr_map_reg, B_BSS_CLR_MAP_STAID,
6716 vif->cfg.aid, phy_idx);
6717 }
6718
rfk_chan_validate_desc(const struct rtw89_rfk_chan_desc * desc)6719 static bool rfk_chan_validate_desc(const struct rtw89_rfk_chan_desc *desc)
6720 {
6721 return desc->ch != 0;
6722 }
6723
rfk_chan_is_equivalent(const struct rtw89_rfk_chan_desc * desc,const struct rtw89_chan * chan)6724 static bool rfk_chan_is_equivalent(const struct rtw89_rfk_chan_desc *desc,
6725 const struct rtw89_chan *chan)
6726 {
6727 if (!rfk_chan_validate_desc(desc))
6728 return false;
6729
6730 if (desc->ch != chan->channel)
6731 return false;
6732
6733 if (desc->has_band && desc->band != chan->band_type)
6734 return false;
6735
6736 if (desc->has_bw && desc->bw != chan->band_width)
6737 return false;
6738
6739 return true;
6740 }
6741
6742 struct rfk_chan_iter_data {
6743 const struct rtw89_rfk_chan_desc desc;
6744 unsigned int found;
6745 };
6746
rfk_chan_iter_search(const struct rtw89_chan * chan,void * data)6747 static int rfk_chan_iter_search(const struct rtw89_chan *chan, void *data)
6748 {
6749 struct rfk_chan_iter_data *iter_data = data;
6750
6751 if (rfk_chan_is_equivalent(&iter_data->desc, chan))
6752 iter_data->found++;
6753
6754 return 0;
6755 }
6756
rtw89_rfk_chan_lookup(struct rtw89_dev * rtwdev,const struct rtw89_rfk_chan_desc * desc,u8 desc_nr,const struct rtw89_chan * target_chan)6757 u8 rtw89_rfk_chan_lookup(struct rtw89_dev *rtwdev,
6758 const struct rtw89_rfk_chan_desc *desc, u8 desc_nr,
6759 const struct rtw89_chan *target_chan)
6760 {
6761 int sel = -1;
6762 u8 i;
6763
6764 for (i = 0; i < desc_nr; i++) {
6765 struct rfk_chan_iter_data iter_data = {
6766 .desc = desc[i],
6767 };
6768
6769 if (rfk_chan_is_equivalent(&desc[i], target_chan))
6770 return i;
6771
6772 rtw89_iterate_entity_chan(rtwdev, rfk_chan_iter_search, &iter_data);
6773 if (!iter_data.found && sel == -1)
6774 sel = i;
6775 }
6776
6777 if (sel == -1) {
6778 rtw89_debug(rtwdev, RTW89_DBG_RFK,
6779 "no idle rfk entry; force replace the first\n");
6780 sel = 0;
6781 }
6782
6783 return sel;
6784 }
6785 EXPORT_SYMBOL(rtw89_rfk_chan_lookup);
6786
6787 static void
_rfk_write_rf(struct rtw89_dev * rtwdev,const struct rtw89_reg5_def * def)6788 _rfk_write_rf(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)
6789 {
6790 rtw89_write_rf(rtwdev, def->path, def->addr, def->mask, def->data);
6791 }
6792
6793 static void
_rfk_write32_mask(struct rtw89_dev * rtwdev,const struct rtw89_reg5_def * def)6794 _rfk_write32_mask(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)
6795 {
6796 rtw89_phy_write32_mask(rtwdev, def->addr, def->mask, def->data);
6797 }
6798
6799 static void
_rfk_write32_set(struct rtw89_dev * rtwdev,const struct rtw89_reg5_def * def)6800 _rfk_write32_set(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)
6801 {
6802 rtw89_phy_write32_set(rtwdev, def->addr, def->mask);
6803 }
6804
6805 static void
_rfk_write32_clr(struct rtw89_dev * rtwdev,const struct rtw89_reg5_def * def)6806 _rfk_write32_clr(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)
6807 {
6808 rtw89_phy_write32_clr(rtwdev, def->addr, def->mask);
6809 }
6810
6811 static void
_rfk_delay(struct rtw89_dev * rtwdev,const struct rtw89_reg5_def * def)6812 _rfk_delay(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)
6813 {
6814 udelay(def->data);
6815 }
6816
6817 static void
6818 (*_rfk_handler[])(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) = {
6819 [RTW89_RFK_F_WRF] = _rfk_write_rf,
6820 [RTW89_RFK_F_WM] = _rfk_write32_mask,
6821 [RTW89_RFK_F_WS] = _rfk_write32_set,
6822 [RTW89_RFK_F_WC] = _rfk_write32_clr,
6823 [RTW89_RFK_F_DELAY] = _rfk_delay,
6824 };
6825
6826 static_assert(ARRAY_SIZE(_rfk_handler) == RTW89_RFK_F_NUM);
6827
6828 void
rtw89_rfk_parser(struct rtw89_dev * rtwdev,const struct rtw89_rfk_tbl * tbl)6829 rtw89_rfk_parser(struct rtw89_dev *rtwdev, const struct rtw89_rfk_tbl *tbl)
6830 {
6831 const struct rtw89_reg5_def *p = tbl->defs;
6832 const struct rtw89_reg5_def *end = tbl->defs + tbl->size;
6833
6834 for (; p < end; p++)
6835 _rfk_handler[p->flag](rtwdev, p);
6836 }
6837 EXPORT_SYMBOL(rtw89_rfk_parser);
6838
6839 #define RTW89_TSSI_FAST_MODE_NUM 4
6840
6841 static const struct rtw89_reg_def rtw89_tssi_fastmode_regs_flat[RTW89_TSSI_FAST_MODE_NUM] = {
6842 {0xD934, 0xff0000},
6843 {0xD934, 0xff000000},
6844 {0xD938, 0xff},
6845 {0xD934, 0xff00},
6846 };
6847
6848 static const struct rtw89_reg_def rtw89_tssi_fastmode_regs_level[RTW89_TSSI_FAST_MODE_NUM] = {
6849 {0xD930, 0xff0000},
6850 {0xD930, 0xff000000},
6851 {0xD934, 0xff},
6852 {0xD930, 0xff00},
6853 };
6854
6855 static
rtw89_phy_tssi_ctrl_set_fast_mode_cfg(struct rtw89_dev * rtwdev,enum rtw89_mac_idx mac_idx,enum rtw89_tssi_bandedge_cfg bandedge_cfg,u32 val)6856 void rtw89_phy_tssi_ctrl_set_fast_mode_cfg(struct rtw89_dev *rtwdev,
6857 enum rtw89_mac_idx mac_idx,
6858 enum rtw89_tssi_bandedge_cfg bandedge_cfg,
6859 u32 val)
6860 {
6861 const struct rtw89_reg_def *regs;
6862 u32 reg;
6863 int i;
6864
6865 if (bandedge_cfg == RTW89_TSSI_BANDEDGE_FLAT)
6866 regs = rtw89_tssi_fastmode_regs_flat;
6867 else
6868 regs = rtw89_tssi_fastmode_regs_level;
6869
6870 for (i = 0; i < RTW89_TSSI_FAST_MODE_NUM; i++) {
6871 reg = rtw89_mac_reg_by_idx(rtwdev, regs[i].addr, mac_idx);
6872 rtw89_write32_mask(rtwdev, reg, regs[i].mask, val);
6873 }
6874 }
6875
6876 static const struct rtw89_reg_def rtw89_tssi_bandedge_regs_flat[RTW89_TSSI_SBW_NUM] = {
6877 {0xD91C, 0xff000000},
6878 {0xD920, 0xff},
6879 {0xD920, 0xff00},
6880 {0xD920, 0xff0000},
6881 {0xD920, 0xff000000},
6882 {0xD924, 0xff},
6883 {0xD924, 0xff00},
6884 {0xD914, 0xff000000},
6885 {0xD918, 0xff},
6886 {0xD918, 0xff00},
6887 {0xD918, 0xff0000},
6888 {0xD918, 0xff000000},
6889 {0xD91C, 0xff},
6890 {0xD91C, 0xff00},
6891 {0xD91C, 0xff0000},
6892 };
6893
6894 static const struct rtw89_reg_def rtw89_tssi_bandedge_regs_level[RTW89_TSSI_SBW_NUM] = {
6895 {0xD910, 0xff},
6896 {0xD910, 0xff00},
6897 {0xD910, 0xff0000},
6898 {0xD910, 0xff000000},
6899 {0xD914, 0xff},
6900 {0xD914, 0xff00},
6901 {0xD914, 0xff0000},
6902 {0xD908, 0xff},
6903 {0xD908, 0xff00},
6904 {0xD908, 0xff0000},
6905 {0xD908, 0xff000000},
6906 {0xD90C, 0xff},
6907 {0xD90C, 0xff00},
6908 {0xD90C, 0xff0000},
6909 {0xD90C, 0xff000000},
6910 };
6911
rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev * rtwdev,enum rtw89_mac_idx mac_idx,enum rtw89_tssi_bandedge_cfg bandedge_cfg)6912 void rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev *rtwdev,
6913 enum rtw89_mac_idx mac_idx,
6914 enum rtw89_tssi_bandedge_cfg bandedge_cfg)
6915 {
6916 const struct rtw89_chip_info *chip = rtwdev->chip;
6917 const struct rtw89_reg_def *regs;
6918 const u32 *data;
6919 u32 reg;
6920 int i;
6921
6922 if (bandedge_cfg >= RTW89_TSSI_CFG_NUM)
6923 return;
6924
6925 if (bandedge_cfg == RTW89_TSSI_BANDEDGE_FLAT)
6926 regs = rtw89_tssi_bandedge_regs_flat;
6927 else
6928 regs = rtw89_tssi_bandedge_regs_level;
6929
6930 data = chip->tssi_dbw_table->data[bandedge_cfg];
6931
6932 for (i = 0; i < RTW89_TSSI_SBW_NUM; i++) {
6933 reg = rtw89_mac_reg_by_idx(rtwdev, regs[i].addr, mac_idx);
6934 rtw89_write32_mask(rtwdev, reg, regs[i].mask, data[i]);
6935 }
6936
6937 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BANDEDGE_CFG, mac_idx);
6938 rtw89_write32_mask(rtwdev, reg, B_AX_BANDEDGE_CFG_IDX_MASK, bandedge_cfg);
6939
6940 rtw89_phy_tssi_ctrl_set_fast_mode_cfg(rtwdev, mac_idx, bandedge_cfg,
6941 data[RTW89_TSSI_SBW20]);
6942 }
6943 EXPORT_SYMBOL(rtw89_phy_tssi_ctrl_set_bandedge_cfg);
6944
6945 static
6946 const u8 rtw89_ch_base_table[16] = {1, 0xff,
6947 36, 100, 132, 149, 0xff,
6948 1, 33, 65, 97, 129, 161, 193, 225, 0xff};
6949 #define RTW89_CH_BASE_IDX_2G 0
6950 #define RTW89_CH_BASE_IDX_5G_FIRST 2
6951 #define RTW89_CH_BASE_IDX_5G_LAST 5
6952 #define RTW89_CH_BASE_IDX_6G_FIRST 7
6953 #define RTW89_CH_BASE_IDX_6G_LAST 14
6954
6955 #define RTW89_CH_BASE_IDX_MASK GENMASK(7, 4)
6956 #define RTW89_CH_OFFSET_MASK GENMASK(3, 0)
6957
rtw89_encode_chan_idx(struct rtw89_dev * rtwdev,u8 central_ch,u8 band)6958 u8 rtw89_encode_chan_idx(struct rtw89_dev *rtwdev, u8 central_ch, u8 band)
6959 {
6960 u8 chan_idx;
6961 u8 last, first;
6962 u8 idx;
6963
6964 switch (band) {
6965 case RTW89_BAND_2G:
6966 chan_idx = FIELD_PREP(RTW89_CH_BASE_IDX_MASK, RTW89_CH_BASE_IDX_2G) |
6967 FIELD_PREP(RTW89_CH_OFFSET_MASK, central_ch);
6968 return chan_idx;
6969 case RTW89_BAND_5G:
6970 first = RTW89_CH_BASE_IDX_5G_FIRST;
6971 last = RTW89_CH_BASE_IDX_5G_LAST;
6972 break;
6973 case RTW89_BAND_6G:
6974 first = RTW89_CH_BASE_IDX_6G_FIRST;
6975 last = RTW89_CH_BASE_IDX_6G_LAST;
6976 break;
6977 default:
6978 rtw89_warn(rtwdev, "Unsupported band %d\n", band);
6979 return 0;
6980 }
6981
6982 for (idx = last; idx >= first; idx--)
6983 if (central_ch >= rtw89_ch_base_table[idx])
6984 break;
6985
6986 if (idx < first) {
6987 rtw89_warn(rtwdev, "Unknown band %d channel %d\n", band, central_ch);
6988 return 0;
6989 }
6990
6991 chan_idx = FIELD_PREP(RTW89_CH_BASE_IDX_MASK, idx) |
6992 FIELD_PREP(RTW89_CH_OFFSET_MASK,
6993 (central_ch - rtw89_ch_base_table[idx]) >> 1);
6994 return chan_idx;
6995 }
6996 EXPORT_SYMBOL(rtw89_encode_chan_idx);
6997
rtw89_decode_chan_idx(struct rtw89_dev * rtwdev,u8 chan_idx,u8 * ch,enum nl80211_band * band)6998 void rtw89_decode_chan_idx(struct rtw89_dev *rtwdev, u8 chan_idx,
6999 u8 *ch, enum nl80211_band *band)
7000 {
7001 u8 idx, offset;
7002
7003 idx = FIELD_GET(RTW89_CH_BASE_IDX_MASK, chan_idx);
7004 offset = FIELD_GET(RTW89_CH_OFFSET_MASK, chan_idx);
7005
7006 if (idx == RTW89_CH_BASE_IDX_2G) {
7007 *band = NL80211_BAND_2GHZ;
7008 *ch = offset;
7009 return;
7010 }
7011
7012 *band = idx <= RTW89_CH_BASE_IDX_5G_LAST ? NL80211_BAND_5GHZ : NL80211_BAND_6GHZ;
7013 *ch = rtw89_ch_base_table[idx] + (offset << 1);
7014 }
7015 EXPORT_SYMBOL(rtw89_decode_chan_idx);
7016
rtw89_phy_config_edcca(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb,bool scan)7017 void rtw89_phy_config_edcca(struct rtw89_dev *rtwdev,
7018 struct rtw89_bb_ctx *bb, bool scan)
7019 {
7020 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs;
7021 struct rtw89_edcca_bak *edcca_bak = &bb->edcca_bak;
7022
7023 if (scan) {
7024 edcca_bak->a =
7025 rtw89_phy_read32_idx(rtwdev, edcca_regs->edcca_level,
7026 edcca_regs->edcca_mask, bb->phy_idx);
7027 edcca_bak->p =
7028 rtw89_phy_read32_idx(rtwdev, edcca_regs->edcca_level,
7029 edcca_regs->edcca_p_mask, bb->phy_idx);
7030 edcca_bak->ppdu =
7031 rtw89_phy_read32_idx(rtwdev, edcca_regs->ppdu_level,
7032 edcca_regs->ppdu_mask, bb->phy_idx);
7033
7034 rtw89_phy_write32_idx(rtwdev, edcca_regs->edcca_level,
7035 edcca_regs->edcca_mask, EDCCA_MAX, bb->phy_idx);
7036 rtw89_phy_write32_idx(rtwdev, edcca_regs->edcca_level,
7037 edcca_regs->edcca_p_mask, EDCCA_MAX, bb->phy_idx);
7038 rtw89_phy_write32_idx(rtwdev, edcca_regs->ppdu_level,
7039 edcca_regs->ppdu_mask, EDCCA_MAX, bb->phy_idx);
7040 } else {
7041 rtw89_phy_write32_idx(rtwdev, edcca_regs->edcca_level,
7042 edcca_regs->edcca_mask,
7043 edcca_bak->a, bb->phy_idx);
7044 rtw89_phy_write32_idx(rtwdev, edcca_regs->edcca_level,
7045 edcca_regs->edcca_p_mask,
7046 edcca_bak->p, bb->phy_idx);
7047 rtw89_phy_write32_idx(rtwdev, edcca_regs->ppdu_level,
7048 edcca_regs->ppdu_mask,
7049 edcca_bak->ppdu, bb->phy_idx);
7050 }
7051 }
7052
rtw89_phy_edcca_log(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)7053 static void rtw89_phy_edcca_log(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb)
7054 {
7055 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs;
7056 const struct rtw89_edcca_p_regs *edcca_p_regs;
7057 bool flag_fb, flag_p20, flag_s20, flag_s40, flag_s80;
7058 s8 pwdb_fb, pwdb_p20, pwdb_s20, pwdb_s40, pwdb_s80;
7059 u8 path, per20_bitmap;
7060 u8 pwdb[8];
7061 u32 tmp;
7062
7063 if (!rtw89_debug_is_enabled(rtwdev, RTW89_DBG_EDCCA))
7064 return;
7065
7066 if (bb->phy_idx == RTW89_PHY_1)
7067 edcca_p_regs = &edcca_regs->p[RTW89_PHY_1];
7068 else
7069 edcca_p_regs = &edcca_regs->p[RTW89_PHY_0];
7070
7071 if (rtwdev->chip->chip_id == RTL8922A)
7072 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel_be,
7073 edcca_regs->rpt_sel_be_mask, 0);
7074
7075 rtw89_phy_write32_mask(rtwdev, edcca_p_regs->rpt_sel,
7076 edcca_p_regs->rpt_sel_mask, 0);
7077 tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_b);
7078 path = u32_get_bits(tmp, B_EDCCA_RPT_B_PATH_MASK);
7079 flag_s80 = u32_get_bits(tmp, B_EDCCA_RPT_B_S80);
7080 flag_s40 = u32_get_bits(tmp, B_EDCCA_RPT_B_S40);
7081 flag_s20 = u32_get_bits(tmp, B_EDCCA_RPT_B_S20);
7082 flag_p20 = u32_get_bits(tmp, B_EDCCA_RPT_B_P20);
7083 flag_fb = u32_get_bits(tmp, B_EDCCA_RPT_B_FB);
7084 pwdb_s20 = u32_get_bits(tmp, MASKBYTE1);
7085 pwdb_p20 = u32_get_bits(tmp, MASKBYTE2);
7086 pwdb_fb = u32_get_bits(tmp, MASKBYTE3);
7087
7088 rtw89_phy_write32_mask(rtwdev, edcca_p_regs->rpt_sel,
7089 edcca_p_regs->rpt_sel_mask, 4);
7090 tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_b);
7091 pwdb_s80 = u32_get_bits(tmp, MASKBYTE1);
7092 pwdb_s40 = u32_get_bits(tmp, MASKBYTE2);
7093
7094 per20_bitmap = rtw89_phy_read32_mask(rtwdev, edcca_p_regs->rpt_a,
7095 MASKBYTE0);
7096
7097 if (rtwdev->chip->chip_id == RTL8922A) {
7098 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel_be,
7099 edcca_regs->rpt_sel_be_mask, 4);
7100 tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_b);
7101 pwdb[0] = u32_get_bits(tmp, MASKBYTE3);
7102 pwdb[1] = u32_get_bits(tmp, MASKBYTE2);
7103 pwdb[2] = u32_get_bits(tmp, MASKBYTE1);
7104 pwdb[3] = u32_get_bits(tmp, MASKBYTE0);
7105
7106 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel_be,
7107 edcca_regs->rpt_sel_be_mask, 5);
7108 tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_b);
7109 pwdb[4] = u32_get_bits(tmp, MASKBYTE3);
7110 pwdb[5] = u32_get_bits(tmp, MASKBYTE2);
7111 pwdb[6] = u32_get_bits(tmp, MASKBYTE1);
7112 pwdb[7] = u32_get_bits(tmp, MASKBYTE0);
7113 } else {
7114 rtw89_phy_write32_mask(rtwdev, edcca_p_regs->rpt_sel,
7115 edcca_p_regs->rpt_sel_mask, 0);
7116 tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_a);
7117 pwdb[0] = u32_get_bits(tmp, MASKBYTE3);
7118 pwdb[1] = u32_get_bits(tmp, MASKBYTE2);
7119
7120 rtw89_phy_write32_mask(rtwdev, edcca_p_regs->rpt_sel,
7121 edcca_p_regs->rpt_sel_mask, 1);
7122 tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_a);
7123 pwdb[2] = u32_get_bits(tmp, MASKBYTE3);
7124 pwdb[3] = u32_get_bits(tmp, MASKBYTE2);
7125
7126 rtw89_phy_write32_mask(rtwdev, edcca_p_regs->rpt_sel,
7127 edcca_p_regs->rpt_sel_mask, 2);
7128 tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_a);
7129 pwdb[4] = u32_get_bits(tmp, MASKBYTE3);
7130 pwdb[5] = u32_get_bits(tmp, MASKBYTE2);
7131
7132 rtw89_phy_write32_mask(rtwdev, edcca_p_regs->rpt_sel,
7133 edcca_p_regs->rpt_sel_mask, 3);
7134 tmp = rtw89_phy_read32(rtwdev, edcca_p_regs->rpt_a);
7135 pwdb[6] = u32_get_bits(tmp, MASKBYTE3);
7136 pwdb[7] = u32_get_bits(tmp, MASKBYTE2);
7137 }
7138
7139 rtw89_debug(rtwdev, RTW89_DBG_EDCCA,
7140 "[EDCCA]: edcca_bitmap = %04x\n", per20_bitmap);
7141
7142 rtw89_debug(rtwdev, RTW89_DBG_EDCCA,
7143 "[EDCCA]: pwdb per20{0,1,2,3,4,5,6,7} = {%d,%d,%d,%d,%d,%d,%d,%d}(dBm)\n",
7144 pwdb[0], pwdb[1], pwdb[2], pwdb[3], pwdb[4], pwdb[5],
7145 pwdb[6], pwdb[7]);
7146
7147 rtw89_debug(rtwdev, RTW89_DBG_EDCCA,
7148 "[EDCCA]: path=%d, flag {FB,p20,s20,s40,s80} = {%d,%d,%d,%d,%d}\n",
7149 path, flag_fb, flag_p20, flag_s20, flag_s40, flag_s80);
7150
7151 rtw89_debug(rtwdev, RTW89_DBG_EDCCA,
7152 "[EDCCA]: pwdb {FB,p20,s20,s40,s80} = {%d,%d,%d,%d,%d}(dBm)\n",
7153 pwdb_fb, pwdb_p20, pwdb_s20, pwdb_s40, pwdb_s80);
7154 }
7155
rtw89_phy_edcca_get_thre_by_rssi(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)7156 static u8 rtw89_phy_edcca_get_thre_by_rssi(struct rtw89_dev *rtwdev,
7157 struct rtw89_bb_ctx *bb)
7158 {
7159 struct rtw89_phy_ch_info *ch_info = &bb->ch_info;
7160 bool is_linked = rtwdev->total_sta_assoc > 0;
7161 u8 rssi_min = ch_info->rssi_min >> 1;
7162 u8 edcca_thre;
7163
7164 if (!is_linked) {
7165 edcca_thre = EDCCA_MAX;
7166 } else {
7167 edcca_thre = rssi_min - RSSI_UNIT_CONVER + EDCCA_UNIT_CONVER -
7168 EDCCA_TH_REF;
7169 edcca_thre = max_t(u8, edcca_thre, EDCCA_TH_L2H_LB);
7170 }
7171
7172 return edcca_thre;
7173 }
7174
rtw89_phy_edcca_thre_calc(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)7175 void rtw89_phy_edcca_thre_calc(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb)
7176 {
7177 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs;
7178 struct rtw89_edcca_bak *edcca_bak = &bb->edcca_bak;
7179 u8 th;
7180
7181 th = rtw89_phy_edcca_get_thre_by_rssi(rtwdev, bb);
7182 if (th == edcca_bak->th_old)
7183 return;
7184
7185 edcca_bak->th_old = th;
7186
7187 rtw89_debug(rtwdev, RTW89_DBG_EDCCA,
7188 "[EDCCA]: Normal Mode, EDCCA_th = %d\n", th);
7189
7190 rtw89_phy_write32_idx(rtwdev, edcca_regs->edcca_level,
7191 edcca_regs->edcca_mask, th, bb->phy_idx);
7192 rtw89_phy_write32_idx(rtwdev, edcca_regs->edcca_level,
7193 edcca_regs->edcca_p_mask, th, bb->phy_idx);
7194 rtw89_phy_write32_idx(rtwdev, edcca_regs->ppdu_level,
7195 edcca_regs->ppdu_mask, th, bb->phy_idx);
7196 }
7197
7198 static
__rtw89_phy_edcca_track(struct rtw89_dev * rtwdev,struct rtw89_bb_ctx * bb)7199 void __rtw89_phy_edcca_track(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb)
7200 {
7201 rtw89_debug(rtwdev, RTW89_DBG_EDCCA, "BB-%d edcca track\n", bb->phy_idx);
7202
7203 rtw89_phy_edcca_thre_calc(rtwdev, bb);
7204 rtw89_phy_edcca_log(rtwdev, bb);
7205 }
7206
rtw89_phy_edcca_track(struct rtw89_dev * rtwdev)7207 void rtw89_phy_edcca_track(struct rtw89_dev *rtwdev)
7208 {
7209 struct rtw89_hal *hal = &rtwdev->hal;
7210 struct rtw89_bb_ctx *bb;
7211
7212 if (hal->disabled_dm_bitmap & BIT(RTW89_DM_DYNAMIC_EDCCA))
7213 return;
7214
7215 rtw89_for_each_active_bb(rtwdev, bb)
7216 __rtw89_phy_edcca_track(rtwdev, bb);
7217 }
7218
rtw89_phy_get_kpath(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)7219 enum rtw89_rf_path_bit rtw89_phy_get_kpath(struct rtw89_dev *rtwdev,
7220 enum rtw89_phy_idx phy_idx)
7221 {
7222 rtw89_debug(rtwdev, RTW89_DBG_RFK,
7223 "[RFK] kpath dbcc_en: 0x%x, mode=0x%x, PHY%d\n",
7224 rtwdev->dbcc_en, rtwdev->mlo_dbcc_mode, phy_idx);
7225
7226 switch (rtwdev->mlo_dbcc_mode) {
7227 case MLO_1_PLUS_1_1RF:
7228 if (phy_idx == RTW89_PHY_0)
7229 return RF_A;
7230 else
7231 return RF_B;
7232 case MLO_1_PLUS_1_2RF:
7233 if (phy_idx == RTW89_PHY_0)
7234 return RF_A;
7235 else
7236 return RF_D;
7237 case MLO_0_PLUS_2_1RF:
7238 case MLO_2_PLUS_0_1RF:
7239 /* for both PHY 0/1 */
7240 return RF_AB;
7241 case MLO_0_PLUS_2_2RF:
7242 case MLO_2_PLUS_0_2RF:
7243 case MLO_2_PLUS_2_2RF:
7244 default:
7245 if (phy_idx == RTW89_PHY_0)
7246 return RF_AB;
7247 else
7248 return RF_CD;
7249 }
7250 }
7251 EXPORT_SYMBOL(rtw89_phy_get_kpath);
7252
rtw89_phy_get_syn_sel(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)7253 enum rtw89_rf_path rtw89_phy_get_syn_sel(struct rtw89_dev *rtwdev,
7254 enum rtw89_phy_idx phy_idx)
7255 {
7256 rtw89_debug(rtwdev, RTW89_DBG_RFK,
7257 "[RFK] kpath dbcc_en: 0x%x, mode=0x%x, PHY%d\n",
7258 rtwdev->dbcc_en, rtwdev->mlo_dbcc_mode, phy_idx);
7259
7260 switch (rtwdev->mlo_dbcc_mode) {
7261 case MLO_1_PLUS_1_1RF:
7262 if (phy_idx == RTW89_PHY_0)
7263 return RF_PATH_A;
7264 else
7265 return RF_PATH_B;
7266 case MLO_1_PLUS_1_2RF:
7267 if (phy_idx == RTW89_PHY_0)
7268 return RF_PATH_A;
7269 else
7270 return RF_PATH_D;
7271 case MLO_0_PLUS_2_1RF:
7272 case MLO_2_PLUS_0_1RF:
7273 if (phy_idx == RTW89_PHY_0)
7274 return RF_PATH_A;
7275 else
7276 return RF_PATH_B;
7277 case MLO_0_PLUS_2_2RF:
7278 case MLO_2_PLUS_0_2RF:
7279 case MLO_2_PLUS_2_2RF:
7280 default:
7281 if (phy_idx == RTW89_PHY_0)
7282 return RF_PATH_A;
7283 else
7284 return RF_PATH_C;
7285 }
7286 }
7287 EXPORT_SYMBOL(rtw89_phy_get_syn_sel);
7288
7289 static const struct rtw89_ccx_regs rtw89_ccx_regs_ax = {
7290 .setting_addr = R_CCX,
7291 .edcca_opt_mask = B_CCX_EDCCA_OPT_MSK,
7292 .measurement_trig_mask = B_MEASUREMENT_TRIG_MSK,
7293 .trig_opt_mask = B_CCX_TRIG_OPT_MSK,
7294 .en_mask = B_CCX_EN_MSK,
7295 .ifs_cnt_addr = R_IFS_COUNTER,
7296 .ifs_clm_period_mask = B_IFS_CLM_PERIOD_MSK,
7297 .ifs_clm_cnt_unit_mask = B_IFS_CLM_COUNTER_UNIT_MSK,
7298 .ifs_clm_cnt_clear_mask = B_IFS_COUNTER_CLR_MSK,
7299 .ifs_collect_en_mask = B_IFS_COLLECT_EN,
7300 .ifs_t1_addr = R_IFS_T1,
7301 .ifs_t1_th_h_mask = B_IFS_T1_TH_HIGH_MSK,
7302 .ifs_t1_en_mask = B_IFS_T1_EN_MSK,
7303 .ifs_t1_th_l_mask = B_IFS_T1_TH_LOW_MSK,
7304 .ifs_t2_addr = R_IFS_T2,
7305 .ifs_t2_th_h_mask = B_IFS_T2_TH_HIGH_MSK,
7306 .ifs_t2_en_mask = B_IFS_T2_EN_MSK,
7307 .ifs_t2_th_l_mask = B_IFS_T2_TH_LOW_MSK,
7308 .ifs_t3_addr = R_IFS_T3,
7309 .ifs_t3_th_h_mask = B_IFS_T3_TH_HIGH_MSK,
7310 .ifs_t3_en_mask = B_IFS_T3_EN_MSK,
7311 .ifs_t3_th_l_mask = B_IFS_T3_TH_LOW_MSK,
7312 .ifs_t4_addr = R_IFS_T4,
7313 .ifs_t4_th_h_mask = B_IFS_T4_TH_HIGH_MSK,
7314 .ifs_t4_en_mask = B_IFS_T4_EN_MSK,
7315 .ifs_t4_th_l_mask = B_IFS_T4_TH_LOW_MSK,
7316 .ifs_clm_tx_cnt_addr = R_IFS_CLM_TX_CNT,
7317 .ifs_clm_edcca_excl_cca_fa_mask = B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK,
7318 .ifs_clm_tx_cnt_msk = B_IFS_CLM_TX_CNT_MSK,
7319 .ifs_clm_cca_addr = R_IFS_CLM_CCA,
7320 .ifs_clm_ofdmcca_excl_fa_mask = B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK,
7321 .ifs_clm_cckcca_excl_fa_mask = B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK,
7322 .ifs_clm_fa_addr = R_IFS_CLM_FA,
7323 .ifs_clm_ofdm_fa_mask = B_IFS_CLM_OFDM_FA_MSK,
7324 .ifs_clm_cck_fa_mask = B_IFS_CLM_CCK_FA_MSK,
7325 .ifs_his_addr = R_IFS_HIS,
7326 .ifs_t4_his_mask = B_IFS_T4_HIS_MSK,
7327 .ifs_t3_his_mask = B_IFS_T3_HIS_MSK,
7328 .ifs_t2_his_mask = B_IFS_T2_HIS_MSK,
7329 .ifs_t1_his_mask = B_IFS_T1_HIS_MSK,
7330 .ifs_avg_l_addr = R_IFS_AVG_L,
7331 .ifs_t2_avg_mask = B_IFS_T2_AVG_MSK,
7332 .ifs_t1_avg_mask = B_IFS_T1_AVG_MSK,
7333 .ifs_avg_h_addr = R_IFS_AVG_H,
7334 .ifs_t4_avg_mask = B_IFS_T4_AVG_MSK,
7335 .ifs_t3_avg_mask = B_IFS_T3_AVG_MSK,
7336 .ifs_cca_l_addr = R_IFS_CCA_L,
7337 .ifs_t2_cca_mask = B_IFS_T2_CCA_MSK,
7338 .ifs_t1_cca_mask = B_IFS_T1_CCA_MSK,
7339 .ifs_cca_h_addr = R_IFS_CCA_H,
7340 .ifs_t4_cca_mask = B_IFS_T4_CCA_MSK,
7341 .ifs_t3_cca_mask = B_IFS_T3_CCA_MSK,
7342 .ifs_total_addr = R_IFSCNT,
7343 .ifs_cnt_done_mask = B_IFSCNT_DONE_MSK,
7344 .ifs_total_mask = B_IFSCNT_TOTAL_CNT_MSK,
7345 };
7346
7347 static const struct rtw89_physts_regs rtw89_physts_regs_ax = {
7348 .setting_addr = R_PLCP_HISTOGRAM,
7349 .dis_trigger_fail_mask = B_STS_DIS_TRIG_BY_FAIL,
7350 .dis_trigger_brk_mask = B_STS_DIS_TRIG_BY_BRK,
7351 };
7352
7353 static const struct rtw89_cfo_regs rtw89_cfo_regs_ax = {
7354 .comp = R_DCFO_WEIGHT,
7355 .weighting_mask = B_DCFO_WEIGHT_MSK,
7356 .comp_seg0 = R_DCFO_OPT,
7357 .valid_0_mask = B_DCFO_OPT_EN,
7358 };
7359
7360 const struct rtw89_phy_gen_def rtw89_phy_gen_ax = {
7361 .cr_base = 0x10000,
7362 .ccx = &rtw89_ccx_regs_ax,
7363 .physts = &rtw89_physts_regs_ax,
7364 .cfo = &rtw89_cfo_regs_ax,
7365 .phy0_phy1_offset = rtw89_phy0_phy1_offset_ax,
7366 .config_bb_gain = rtw89_phy_config_bb_gain_ax,
7367 .preinit_rf_nctl = rtw89_phy_preinit_rf_nctl_ax,
7368 .bb_wrap_init = NULL,
7369 .ch_info_init = NULL,
7370
7371 .set_txpwr_byrate = rtw89_phy_set_txpwr_byrate_ax,
7372 .set_txpwr_offset = rtw89_phy_set_txpwr_offset_ax,
7373 .set_txpwr_limit = rtw89_phy_set_txpwr_limit_ax,
7374 .set_txpwr_limit_ru = rtw89_phy_set_txpwr_limit_ru_ax,
7375 };
7376 EXPORT_SYMBOL(rtw89_phy_gen_ax);
7377