1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "cam.h" 6 #include "chan.h" 7 #include "debug.h" 8 #include "efuse.h" 9 #include "fw.h" 10 #include "mac.h" 11 #include "pci.h" 12 #include "phy.h" 13 #include "ps.h" 14 #include "reg.h" 15 #include "ser.h" 16 #include "util.h" 17 18 static const u32 rtw89_mac_mem_base_addrs_ax[RTW89_MAC_MEM_NUM] = { 19 [RTW89_MAC_MEM_AXIDMA] = AXIDMA_BASE_ADDR, 20 [RTW89_MAC_MEM_SHARED_BUF] = SHARED_BUF_BASE_ADDR, 21 [RTW89_MAC_MEM_DMAC_TBL] = DMAC_TBL_BASE_ADDR, 22 [RTW89_MAC_MEM_SHCUT_MACHDR] = SHCUT_MACHDR_BASE_ADDR, 23 [RTW89_MAC_MEM_STA_SCHED] = STA_SCHED_BASE_ADDR, 24 [RTW89_MAC_MEM_RXPLD_FLTR_CAM] = RXPLD_FLTR_CAM_BASE_ADDR, 25 [RTW89_MAC_MEM_SECURITY_CAM] = SECURITY_CAM_BASE_ADDR, 26 [RTW89_MAC_MEM_WOW_CAM] = WOW_CAM_BASE_ADDR, 27 [RTW89_MAC_MEM_CMAC_TBL] = CMAC_TBL_BASE_ADDR, 28 [RTW89_MAC_MEM_ADDR_CAM] = ADDR_CAM_BASE_ADDR, 29 [RTW89_MAC_MEM_BA_CAM] = BA_CAM_BASE_ADDR, 30 [RTW89_MAC_MEM_BCN_IE_CAM0] = BCN_IE_CAM0_BASE_ADDR, 31 [RTW89_MAC_MEM_BCN_IE_CAM1] = BCN_IE_CAM1_BASE_ADDR, 32 [RTW89_MAC_MEM_TXD_FIFO_0] = TXD_FIFO_0_BASE_ADDR, 33 [RTW89_MAC_MEM_TXD_FIFO_1] = TXD_FIFO_1_BASE_ADDR, 34 [RTW89_MAC_MEM_TXDATA_FIFO_0] = TXDATA_FIFO_0_BASE_ADDR, 35 [RTW89_MAC_MEM_TXDATA_FIFO_1] = TXDATA_FIFO_1_BASE_ADDR, 36 [RTW89_MAC_MEM_CPU_LOCAL] = CPU_LOCAL_BASE_ADDR, 37 [RTW89_MAC_MEM_BSSID_CAM] = BSSID_CAM_BASE_ADDR, 38 [RTW89_MAC_MEM_TXD_FIFO_0_V1] = TXD_FIFO_0_BASE_ADDR_V1, 39 [RTW89_MAC_MEM_TXD_FIFO_1_V1] = TXD_FIFO_1_BASE_ADDR_V1, 40 }; 41 42 static void rtw89_mac_mem_write(struct rtw89_dev *rtwdev, u32 offset, 43 u32 val, enum rtw89_mac_mem_sel sel) 44 { 45 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 46 u32 addr = rtw89_mac_mem_base_addrs(rtwdev, sel) + offset; 47 48 rtw89_write32(rtwdev, mac->filter_model_addr, addr); 49 rtw89_write32(rtwdev, mac->indir_access_addr, val); 50 } 51 52 static u32 rtw89_mac_mem_read(struct rtw89_dev *rtwdev, u32 offset, 53 enum rtw89_mac_mem_sel sel) 54 { 55 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 56 u32 addr = rtw89_mac_mem_base_addrs(rtwdev, sel) + offset; 57 58 rtw89_write32(rtwdev, mac->filter_model_addr, addr); 59 return rtw89_read32(rtwdev, mac->indir_access_addr); 60 } 61 62 static int rtw89_mac_check_mac_en_ax(struct rtw89_dev *rtwdev, u8 mac_idx, 63 enum rtw89_mac_hwmod_sel sel) 64 { 65 u32 val, r_val; 66 67 if (sel == RTW89_DMAC_SEL) { 68 r_val = rtw89_read32(rtwdev, R_AX_DMAC_FUNC_EN); 69 val = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN); 70 } else if (sel == RTW89_CMAC_SEL && mac_idx == 0) { 71 r_val = rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN); 72 val = B_AX_CMAC_EN; 73 } else if (sel == RTW89_CMAC_SEL && mac_idx == 1) { 74 r_val = rtw89_read32(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND); 75 val = B_AX_CMAC1_FEN; 76 } else { 77 return -EINVAL; 78 } 79 if (r_val == RTW89_R32_EA || r_val == RTW89_R32_DEAD || 80 (val & r_val) != val) 81 return -EFAULT; 82 83 return 0; 84 } 85 86 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val) 87 { 88 u8 lte_ctrl; 89 int ret; 90 91 ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 92 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 93 if (ret && !test_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags)) 94 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 95 96 rtw89_write32(rtwdev, R_AX_LTE_WDATA, val); 97 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0xC00F0000 | offset); 98 99 return ret; 100 } 101 102 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val) 103 { 104 u8 lte_ctrl; 105 int ret; 106 107 ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 108 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 109 if (ret && !test_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags)) 110 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 111 112 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0x800F0000 | offset); 113 *val = rtw89_read32(rtwdev, R_AX_LTE_RDATA); 114 115 return ret; 116 } 117 118 int rtw89_mac_dle_dfi_cfg(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl) 119 { 120 u32 ctrl_reg, data_reg, ctrl_data; 121 u32 val; 122 int ret; 123 124 switch (ctrl->type) { 125 case DLE_CTRL_TYPE_WDE: 126 ctrl_reg = R_AX_WDE_DBG_FUN_INTF_CTL; 127 data_reg = R_AX_WDE_DBG_FUN_INTF_DATA; 128 ctrl_data = FIELD_PREP(B_AX_WDE_DFI_TRGSEL_MASK, ctrl->target) | 129 FIELD_PREP(B_AX_WDE_DFI_ADDR_MASK, ctrl->addr) | 130 B_AX_WDE_DFI_ACTIVE; 131 break; 132 case DLE_CTRL_TYPE_PLE: 133 ctrl_reg = R_AX_PLE_DBG_FUN_INTF_CTL; 134 data_reg = R_AX_PLE_DBG_FUN_INTF_DATA; 135 ctrl_data = FIELD_PREP(B_AX_PLE_DFI_TRGSEL_MASK, ctrl->target) | 136 FIELD_PREP(B_AX_PLE_DFI_ADDR_MASK, ctrl->addr) | 137 B_AX_PLE_DFI_ACTIVE; 138 break; 139 default: 140 rtw89_warn(rtwdev, "[ERR] dfi ctrl type %d\n", ctrl->type); 141 return -EINVAL; 142 } 143 144 rtw89_write32(rtwdev, ctrl_reg, ctrl_data); 145 146 ret = read_poll_timeout_atomic(rtw89_read32, val, !(val & B_AX_WDE_DFI_ACTIVE), 147 1, 1000, false, rtwdev, ctrl_reg); 148 if (ret) { 149 rtw89_warn(rtwdev, "[ERR] dle dfi ctrl 0x%X set 0x%X timeout\n", 150 ctrl_reg, ctrl_data); 151 return ret; 152 } 153 154 ctrl->out_data = rtw89_read32(rtwdev, data_reg); 155 return 0; 156 } 157 158 int rtw89_mac_dle_dfi_quota_cfg(struct rtw89_dev *rtwdev, 159 struct rtw89_mac_dle_dfi_quota *quota) 160 { 161 struct rtw89_mac_dle_dfi_ctrl ctrl; 162 int ret; 163 164 ctrl.type = quota->dle_type; 165 ctrl.target = DLE_DFI_TYPE_QUOTA; 166 ctrl.addr = quota->qtaid; 167 ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl); 168 if (ret) { 169 rtw89_warn(rtwdev, "[ERR] dle dfi quota %d\n", ret); 170 return ret; 171 } 172 173 quota->rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, ctrl.out_data); 174 quota->use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, ctrl.out_data); 175 return 0; 176 } 177 178 int rtw89_mac_dle_dfi_qempty_cfg(struct rtw89_dev *rtwdev, 179 struct rtw89_mac_dle_dfi_qempty *qempty) 180 { 181 struct rtw89_mac_dle_dfi_ctrl ctrl; 182 int ret; 183 184 ctrl.type = qempty->dle_type; 185 ctrl.target = DLE_DFI_TYPE_QEMPTY; 186 ctrl.addr = qempty->grpsel; 187 ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl); 188 if (ret) { 189 rtw89_warn(rtwdev, "[ERR] dle dfi qempty %d\n", ret); 190 return ret; 191 } 192 193 qempty->qempty = FIELD_GET(B_AX_DLE_QEMPTY_GRP, ctrl.out_data); 194 return 0; 195 } 196 197 static void dump_err_status_dispatcher_ax(struct rtw89_dev *rtwdev) 198 { 199 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_IMR=0x%08x ", 200 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 201 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_ISR=0x%08x\n", 202 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 203 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_IMR=0x%08x ", 204 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 205 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_ISR=0x%08x\n", 206 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 207 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_IMR=0x%08x ", 208 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 209 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_ISR=0x%08x\n", 210 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 211 } 212 213 static void rtw89_mac_dump_qta_lost_ax(struct rtw89_dev *rtwdev) 214 { 215 struct rtw89_mac_dle_dfi_qempty qempty; 216 struct rtw89_mac_dle_dfi_quota quota; 217 struct rtw89_mac_dle_dfi_ctrl ctrl; 218 u32 val, not_empty, i; 219 int ret; 220 221 qempty.dle_type = DLE_CTRL_TYPE_PLE; 222 qempty.grpsel = 0; 223 qempty.qempty = ~(u32)0; 224 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty); 225 if (ret) 226 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 227 else 228 rtw89_info(rtwdev, "DLE group0 empty: 0x%x\n", qempty.qempty); 229 230 for (not_empty = ~qempty.qempty, i = 0; not_empty != 0; not_empty >>= 1, i++) { 231 if (!(not_empty & BIT(0))) 232 continue; 233 ctrl.type = DLE_CTRL_TYPE_PLE; 234 ctrl.target = DLE_DFI_TYPE_QLNKTBL; 235 ctrl.addr = (QLNKTBL_ADDR_INFO_SEL_0 ? QLNKTBL_ADDR_INFO_SEL : 0) | 236 u32_encode_bits(i, QLNKTBL_ADDR_TBL_IDX_MASK); 237 ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl); 238 if (ret) 239 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 240 else 241 rtw89_info(rtwdev, "qidx%d pktcnt = %d\n", i, 242 u32_get_bits(ctrl.out_data, 243 QLNKTBL_DATA_SEL1_PKT_CNT_MASK)); 244 } 245 246 quota.dle_type = DLE_CTRL_TYPE_PLE; 247 quota.qtaid = 6; 248 ret = rtw89_mac_dle_dfi_quota_cfg(rtwdev, "a); 249 if (ret) 250 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 251 else 252 rtw89_info(rtwdev, "quota6 rsv/use: 0x%x/0x%x\n", 253 quota.rsv_pgnum, quota.use_pgnum); 254 255 val = rtw89_read32(rtwdev, R_AX_PLE_QTA6_CFG); 256 rtw89_info(rtwdev, "[PLE][CMAC0_RX]min_pgnum=0x%x\n", 257 u32_get_bits(val, B_AX_PLE_Q6_MIN_SIZE_MASK)); 258 rtw89_info(rtwdev, "[PLE][CMAC0_RX]max_pgnum=0x%x\n", 259 u32_get_bits(val, B_AX_PLE_Q6_MAX_SIZE_MASK)); 260 val = rtw89_read32(rtwdev, R_AX_RX_FLTR_OPT); 261 rtw89_info(rtwdev, "[PLE][CMAC0_RX]B_AX_RX_MPDU_MAX_LEN=0x%x\n", 262 u32_get_bits(val, B_AX_RX_MPDU_MAX_LEN_MASK)); 263 rtw89_info(rtwdev, "R_AX_RSP_CHK_SIG=0x%08x\n", 264 rtw89_read32(rtwdev, R_AX_RSP_CHK_SIG)); 265 rtw89_info(rtwdev, "R_AX_TRXPTCL_RESP_0=0x%08x\n", 266 rtw89_read32(rtwdev, R_AX_TRXPTCL_RESP_0)); 267 rtw89_info(rtwdev, "R_AX_CCA_CONTROL=0x%08x\n", 268 rtw89_read32(rtwdev, R_AX_CCA_CONTROL)); 269 270 if (!rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL)) { 271 quota.dle_type = DLE_CTRL_TYPE_PLE; 272 quota.qtaid = 7; 273 ret = rtw89_mac_dle_dfi_quota_cfg(rtwdev, "a); 274 if (ret) 275 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 276 else 277 rtw89_info(rtwdev, "quota7 rsv/use: 0x%x/0x%x\n", 278 quota.rsv_pgnum, quota.use_pgnum); 279 280 val = rtw89_read32(rtwdev, R_AX_PLE_QTA7_CFG); 281 rtw89_info(rtwdev, "[PLE][CMAC1_RX]min_pgnum=0x%x\n", 282 u32_get_bits(val, B_AX_PLE_Q7_MIN_SIZE_MASK)); 283 rtw89_info(rtwdev, "[PLE][CMAC1_RX]max_pgnum=0x%x\n", 284 u32_get_bits(val, B_AX_PLE_Q7_MAX_SIZE_MASK)); 285 val = rtw89_read32(rtwdev, R_AX_RX_FLTR_OPT_C1); 286 rtw89_info(rtwdev, "[PLE][CMAC1_RX]B_AX_RX_MPDU_MAX_LEN=0x%x\n", 287 u32_get_bits(val, B_AX_RX_MPDU_MAX_LEN_MASK)); 288 rtw89_info(rtwdev, "R_AX_RSP_CHK_SIG_C1=0x%08x\n", 289 rtw89_read32(rtwdev, R_AX_RSP_CHK_SIG_C1)); 290 rtw89_info(rtwdev, "R_AX_TRXPTCL_RESP_0_C1=0x%08x\n", 291 rtw89_read32(rtwdev, R_AX_TRXPTCL_RESP_0_C1)); 292 rtw89_info(rtwdev, "R_AX_CCA_CONTROL_C1=0x%08x\n", 293 rtw89_read32(rtwdev, R_AX_CCA_CONTROL_C1)); 294 } 295 296 rtw89_info(rtwdev, "R_AX_DLE_EMPTY0=0x%08x\n", 297 rtw89_read32(rtwdev, R_AX_DLE_EMPTY0)); 298 rtw89_info(rtwdev, "R_AX_DLE_EMPTY1=0x%08x\n", 299 rtw89_read32(rtwdev, R_AX_DLE_EMPTY1)); 300 301 dump_err_status_dispatcher_ax(rtwdev); 302 } 303 304 void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev, 305 enum mac_ax_err_info err) 306 { 307 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 308 u32 dbg, event; 309 310 dbg = rtw89_read32(rtwdev, R_AX_SER_DBG_INFO); 311 event = u32_get_bits(dbg, B_AX_L0_TO_L1_EVENT_MASK); 312 313 switch (event) { 314 case MAC_AX_L0_TO_L1_RX_QTA_LOST: 315 rtw89_info(rtwdev, "quota lost!\n"); 316 mac->dump_qta_lost(rtwdev); 317 break; 318 default: 319 break; 320 } 321 } 322 323 void rtw89_mac_dump_dmac_err_status(struct rtw89_dev *rtwdev) 324 { 325 const struct rtw89_chip_info *chip = rtwdev->chip; 326 u32 dmac_err; 327 int i, ret; 328 329 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 330 if (ret) { 331 rtw89_warn(rtwdev, "[DMAC] : DMAC not enabled\n"); 332 return; 333 } 334 335 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 336 rtw89_info(rtwdev, "R_AX_DMAC_ERR_ISR=0x%08x\n", dmac_err); 337 rtw89_info(rtwdev, "R_AX_DMAC_ERR_IMR=0x%08x\n", 338 rtw89_read32(rtwdev, R_AX_DMAC_ERR_IMR)); 339 340 if (dmac_err) { 341 rtw89_info(rtwdev, "R_AX_WDE_ERR_FLAG_CFG=0x%08x\n", 342 rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG_NUM1)); 343 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_CFG=0x%08x\n", 344 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG_NUM1)); 345 if (chip->chip_id == RTL8852C) { 346 rtw89_info(rtwdev, "R_AX_PLE_ERRFLAG_MSG=0x%08x\n", 347 rtw89_read32(rtwdev, R_AX_PLE_ERRFLAG_MSG)); 348 rtw89_info(rtwdev, "R_AX_WDE_ERRFLAG_MSG=0x%08x\n", 349 rtw89_read32(rtwdev, R_AX_WDE_ERRFLAG_MSG)); 350 rtw89_info(rtwdev, "R_AX_PLE_DBGERR_LOCKEN=0x%08x\n", 351 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_LOCKEN)); 352 rtw89_info(rtwdev, "R_AX_PLE_DBGERR_STS=0x%08x\n", 353 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_STS)); 354 } 355 } 356 357 if (dmac_err & B_AX_WDRLS_ERR_FLAG) { 358 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_IMR=0x%08x\n", 359 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR)); 360 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_ISR=0x%08x\n", 361 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); 362 if (chip->chip_id == RTL8852C) 363 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 364 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX_V1)); 365 else 366 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 367 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX)); 368 } 369 370 if (dmac_err & B_AX_WSEC_ERR_FLAG) { 371 if (chip->chip_id == RTL8852C) { 372 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR=0x%08x\n", 373 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG_IMR)); 374 rtw89_info(rtwdev, "R_AX_SEC_ERR_ISR=0x%08x\n", 375 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG)); 376 rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n", 377 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 378 rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n", 379 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 380 rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 381 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 382 rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n", 383 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 384 rtw89_info(rtwdev, "R_AX_SEC_DEBUG1=0x%08x\n", 385 rtw89_read32(rtwdev, R_AX_SEC_DEBUG1)); 386 rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n", 387 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 388 rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n", 389 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 390 391 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 392 B_AX_DBG_SEL0, 0x8B); 393 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 394 B_AX_DBG_SEL1, 0x8B); 395 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 396 B_AX_SEL_0XC0_MASK, 1); 397 for (i = 0; i < 0x10; i++) { 398 rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 399 B_AX_SEC_DBG_PORT_FIELD_MASK, i); 400 rtw89_info(rtwdev, "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n", 401 i, rtw89_read32(rtwdev, R_AX_SEC_DEBUG2)); 402 } 403 } else if (chip->chip_id == RTL8922A) { 404 rtw89_info(rtwdev, "R_BE_SEC_ERROR_FLAG=0x%08x\n", 405 rtw89_read32(rtwdev, R_BE_SEC_ERROR_FLAG)); 406 rtw89_info(rtwdev, "R_BE_SEC_ERROR_IMR=0x%08x\n", 407 rtw89_read32(rtwdev, R_BE_SEC_ERROR_IMR)); 408 rtw89_info(rtwdev, "R_BE_SEC_ENG_CTRL=0x%08x\n", 409 rtw89_read32(rtwdev, R_BE_SEC_ENG_CTRL)); 410 rtw89_info(rtwdev, "R_BE_SEC_MPDU_PROC=0x%08x\n", 411 rtw89_read32(rtwdev, R_BE_SEC_MPDU_PROC)); 412 rtw89_info(rtwdev, "R_BE_SEC_CAM_ACCESS=0x%08x\n", 413 rtw89_read32(rtwdev, R_BE_SEC_CAM_ACCESS)); 414 rtw89_info(rtwdev, "R_BE_SEC_CAM_RDATA=0x%08x\n", 415 rtw89_read32(rtwdev, R_BE_SEC_CAM_RDATA)); 416 rtw89_info(rtwdev, "R_BE_SEC_DEBUG2=0x%08x\n", 417 rtw89_read32(rtwdev, R_BE_SEC_DEBUG2)); 418 } else { 419 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR_ISR=0x%08x\n", 420 rtw89_read32(rtwdev, R_AX_SEC_DEBUG)); 421 rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n", 422 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 423 rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n", 424 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 425 rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 426 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 427 rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n", 428 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 429 rtw89_info(rtwdev, "R_AX_SEC_CAM_WDATA=0x%08x\n", 430 rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA)); 431 rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n", 432 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 433 rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n", 434 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 435 rtw89_info(rtwdev, "R_AX_SEC_TRX_PKT_CNT=0x%08x\n", 436 rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT)); 437 rtw89_info(rtwdev, "R_AX_SEC_TRX_BLK_CNT=0x%08x\n", 438 rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT)); 439 } 440 } 441 442 if (dmac_err & B_AX_MPDU_ERR_FLAG) { 443 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_IMR=0x%08x\n", 444 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR)); 445 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_ISR=0x%08x\n", 446 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); 447 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_IMR=0x%08x\n", 448 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR)); 449 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_ISR=0x%08x\n", 450 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); 451 } 452 453 if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) { 454 if (chip->chip_id == RTL8922A) { 455 rtw89_info(rtwdev, "R_BE_INTERRUPT_MASK_REG=0x%08x\n", 456 rtw89_read32(rtwdev, R_BE_INTERRUPT_MASK_REG)); 457 rtw89_info(rtwdev, "R_BE_INTERRUPT_STS_REG=0x%08x\n", 458 rtw89_read32(rtwdev, R_BE_INTERRUPT_STS_REG)); 459 } else { 460 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_IMR=0x%08x\n", 461 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR)); 462 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n", 463 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); 464 } 465 } 466 467 if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) { 468 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n", 469 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 470 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 471 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 472 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n", 473 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 474 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 475 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 476 } 477 478 if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) { 479 if (chip->chip_id == RTL8852C || chip->chip_id == RTL8922A) { 480 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n", 481 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR)); 482 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n", 483 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR)); 484 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n", 485 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_IMR)); 486 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n", 487 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_ISR)); 488 } else { 489 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", 490 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); 491 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", 492 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); 493 } 494 } 495 496 if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) { 497 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n", 498 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 499 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 500 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 501 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n", 502 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 503 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 504 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 505 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_0=0x%08x\n", 506 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0)); 507 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_1=0x%08x\n", 508 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1)); 509 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_2=0x%08x\n", 510 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2)); 511 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_0=0x%08x\n", 512 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0)); 513 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_1=0x%08x\n", 514 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1)); 515 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_2=0x%08x\n", 516 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2)); 517 if (chip->chip_id == RTL8922A) { 518 rtw89_info(rtwdev, "R_BE_WD_CPUQ_OP_3=0x%08x\n", 519 rtw89_read32(rtwdev, R_BE_WD_CPUQ_OP_3)); 520 rtw89_info(rtwdev, "R_BE_WD_CPUQ_OP_STATUS=0x%08x\n", 521 rtw89_read32(rtwdev, R_BE_WD_CPUQ_OP_STATUS)); 522 rtw89_info(rtwdev, "R_BE_PLE_CPUQ_OP_3=0x%08x\n", 523 rtw89_read32(rtwdev, R_BE_PL_CPUQ_OP_3)); 524 rtw89_info(rtwdev, "R_BE_PL_CPUQ_OP_STATUS=0x%08x\n", 525 rtw89_read32(rtwdev, R_BE_PL_CPUQ_OP_STATUS)); 526 } else { 527 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n", 528 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS)); 529 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n", 530 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS)); 531 if (chip->chip_id == RTL8852C) { 532 rtw89_info(rtwdev, "R_AX_RX_CTRL0=0x%08x\n", 533 rtw89_read32(rtwdev, R_AX_RX_CTRL0)); 534 rtw89_info(rtwdev, "R_AX_RX_CTRL1=0x%08x\n", 535 rtw89_read32(rtwdev, R_AX_RX_CTRL1)); 536 rtw89_info(rtwdev, "R_AX_RX_CTRL2=0x%08x\n", 537 rtw89_read32(rtwdev, R_AX_RX_CTRL2)); 538 } else { 539 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n", 540 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0)); 541 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n", 542 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1)); 543 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n", 544 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2)); 545 } 546 } 547 } 548 549 if (dmac_err & B_AX_PKTIN_ERR_FLAG) { 550 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR=0x%08x\n", 551 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); 552 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR=0x%08x\n", 553 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 554 } 555 556 if (dmac_err & B_AX_DISPATCH_ERR_FLAG) { 557 if (chip->chip_id == RTL8922A) { 558 rtw89_info(rtwdev, "R_BE_DISP_HOST_IMR=0x%08x\n", 559 rtw89_read32(rtwdev, R_BE_DISP_HOST_IMR)); 560 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR1=0x%08x\n", 561 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR1)); 562 rtw89_info(rtwdev, "R_BE_DISP_CPU_IMR=0x%08x\n", 563 rtw89_read32(rtwdev, R_BE_DISP_CPU_IMR)); 564 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR2=0x%08x\n", 565 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR2)); 566 rtw89_info(rtwdev, "R_BE_DISP_OTHER_IMR=0x%08x\n", 567 rtw89_read32(rtwdev, R_BE_DISP_OTHER_IMR)); 568 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR0=0x%08x\n", 569 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR0)); 570 } else { 571 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n", 572 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 573 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n", 574 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 575 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n", 576 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 577 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n", 578 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 579 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x\n", 580 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 581 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n", 582 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 583 } 584 } 585 586 if (dmac_err & B_AX_BBRPT_ERR_FLAG) { 587 if (chip->chip_id == RTL8852C || chip->chip_id == RTL8922A) { 588 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR=0x%08x\n", 589 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR)); 590 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_ISR=0x%08x\n", 591 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_ISR)); 592 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 593 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 594 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 595 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 596 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 597 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 598 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 599 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 600 } else { 601 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", 602 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); 603 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 604 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 605 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 606 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 607 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 608 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 609 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 610 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 611 } 612 if (chip->chip_id == RTL8922A) { 613 rtw89_info(rtwdev, "R_BE_LA_ERRFLAG_IMR=0x%08x\n", 614 rtw89_read32(rtwdev, R_BE_LA_ERRFLAG_IMR)); 615 rtw89_info(rtwdev, "R_BE_LA_ERRFLAG_ISR=0x%08x\n", 616 rtw89_read32(rtwdev, R_BE_LA_ERRFLAG_ISR)); 617 } 618 } 619 620 if (dmac_err & B_AX_HAXIDMA_ERR_FLAG) { 621 if (chip->chip_id == RTL8922A) { 622 rtw89_info(rtwdev, "R_BE_HAXI_IDCT_MSK=0x%08x\n", 623 rtw89_read32(rtwdev, R_BE_HAXI_IDCT_MSK)); 624 rtw89_info(rtwdev, "R_BE_HAXI_IDCT=0x%08x\n", 625 rtw89_read32(rtwdev, R_BE_HAXI_IDCT)); 626 } else if (chip->chip_id == RTL8852C) { 627 rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_IMR=0x%08x\n", 628 rtw89_read32(rtwdev, R_AX_HAXI_IDCT_MSK)); 629 rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_ISR=0x%08x\n", 630 rtw89_read32(rtwdev, R_AX_HAXI_IDCT)); 631 } 632 } 633 634 if (dmac_err & B_BE_P_AXIDMA_ERR_INT) { 635 rtw89_info(rtwdev, "R_BE_PL_AXIDMA_IDCT_MSK=0x%08x\n", 636 rtw89_mac_mem_read(rtwdev, R_BE_PL_AXIDMA_IDCT_MSK, 637 RTW89_MAC_MEM_AXIDMA)); 638 rtw89_info(rtwdev, "R_BE_PL_AXIDMA_IDCT=0x%08x\n", 639 rtw89_mac_mem_read(rtwdev, R_BE_PL_AXIDMA_IDCT, 640 RTW89_MAC_MEM_AXIDMA)); 641 } 642 643 if (dmac_err & B_BE_MLO_ERR_INT) { 644 rtw89_info(rtwdev, "R_BE_MLO_ERR_IDCT_IMR=0x%08x\n", 645 rtw89_read32(rtwdev, R_BE_MLO_ERR_IDCT_IMR)); 646 rtw89_info(rtwdev, "R_BE_PKTIN_ERR_ISR=0x%08x\n", 647 rtw89_read32(rtwdev, R_BE_MLO_ERR_IDCT_ISR)); 648 } 649 650 if (dmac_err & B_BE_PLRLS_ERR_INT) { 651 rtw89_info(rtwdev, "R_BE_PLRLS_ERR_IMR=0x%08x\n", 652 rtw89_read32(rtwdev, R_BE_PLRLS_ERR_IMR)); 653 rtw89_info(rtwdev, "R_BE_PLRLS_ERR_ISR=0x%08x\n", 654 rtw89_read32(rtwdev, R_BE_PLRLS_ERR_ISR)); 655 } 656 } 657 658 static void rtw89_mac_dump_cmac_err_status_ax(struct rtw89_dev *rtwdev, 659 u8 band) 660 { 661 const struct rtw89_chip_info *chip = rtwdev->chip; 662 u32 offset = 0; 663 u32 cmac_err; 664 int ret; 665 666 ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL); 667 if (ret) { 668 if (band) 669 rtw89_warn(rtwdev, "[CMAC] : CMAC1 not enabled\n"); 670 else 671 rtw89_warn(rtwdev, "[CMAC] : CMAC0 not enabled\n"); 672 return; 673 } 674 675 if (band) 676 offset = RTW89_MAC_AX_BAND_REG_OFFSET; 677 678 cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset); 679 rtw89_info(rtwdev, "R_AX_CMAC_ERR_ISR [%d]=0x%08x\n", band, 680 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset)); 681 rtw89_info(rtwdev, "R_AX_CMAC_FUNC_EN [%d]=0x%08x\n", band, 682 rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN + offset)); 683 rtw89_info(rtwdev, "R_AX_CK_EN [%d]=0x%08x\n", band, 684 rtw89_read32(rtwdev, R_AX_CK_EN + offset)); 685 686 if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) { 687 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band, 688 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR + offset)); 689 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band, 690 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR + offset)); 691 } 692 693 if (cmac_err & B_AX_PTCL_TOP_ERR_IND) { 694 rtw89_info(rtwdev, "R_AX_PTCL_IMR0 [%d]=0x%08x\n", band, 695 rtw89_read32(rtwdev, R_AX_PTCL_IMR0 + offset)); 696 rtw89_info(rtwdev, "R_AX_PTCL_ISR0 [%d]=0x%08x\n", band, 697 rtw89_read32(rtwdev, R_AX_PTCL_ISR0 + offset)); 698 } 699 700 if (cmac_err & B_AX_DMA_TOP_ERR_IND) { 701 if (chip->chip_id == RTL8852C) { 702 rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG [%d]=0x%08x\n", band, 703 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG + offset)); 704 rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG_IMR [%d]=0x%08x\n", band, 705 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG_IMR + offset)); 706 } else { 707 rtw89_info(rtwdev, "R_AX_DLE_CTRL [%d]=0x%08x\n", band, 708 rtw89_read32(rtwdev, R_AX_DLE_CTRL + offset)); 709 } 710 } 711 712 if (cmac_err & B_AX_DMA_TOP_ERR_IND || cmac_err & B_AX_WMAC_RX_ERR_IND) { 713 if (chip->chip_id == RTL8852C) { 714 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_ISR [%d]=0x%08x\n", band, 715 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR + offset)); 716 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 717 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 718 } else { 719 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 720 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 721 } 722 } 723 724 if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) { 725 rtw89_info(rtwdev, "R_AX_TXPWR_IMR [%d]=0x%08x\n", band, 726 rtw89_read32(rtwdev, R_AX_TXPWR_IMR + offset)); 727 rtw89_info(rtwdev, "R_AX_TXPWR_ISR [%d]=0x%08x\n", band, 728 rtw89_read32(rtwdev, R_AX_TXPWR_ISR + offset)); 729 } 730 731 if (cmac_err & B_AX_WMAC_TX_ERR_IND) { 732 if (chip->chip_id == RTL8852C) { 733 rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", band, 734 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA + offset)); 735 rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", band, 736 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA_MASK + offset)); 737 } else { 738 rtw89_info(rtwdev, "R_AX_TMAC_ERR_IMR_ISR [%d]=0x%08x\n", band, 739 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR + offset)); 740 } 741 rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL [%d]=0x%08x\n", band, 742 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL + offset)); 743 } 744 745 rtw89_info(rtwdev, "R_AX_CMAC_ERR_IMR [%d]=0x%08x\n", band, 746 rtw89_read32(rtwdev, R_AX_CMAC_ERR_IMR + offset)); 747 } 748 749 static void rtw89_mac_dump_err_status_ax(struct rtw89_dev *rtwdev, 750 enum mac_ax_err_info err) 751 { 752 if (err != MAC_AX_ERR_L1_ERR_DMAC && 753 err != MAC_AX_ERR_L0_PROMOTE_TO_L1 && 754 err != MAC_AX_ERR_L0_ERR_CMAC0 && 755 err != MAC_AX_ERR_L0_ERR_CMAC1 && 756 err != MAC_AX_ERR_RXI300) 757 return; 758 759 rtw89_info(rtwdev, "--->\nerr=0x%x\n", err); 760 rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n", 761 rtw89_read32(rtwdev, R_AX_SER_DBG_INFO)); 762 rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n", 763 rtw89_read32(rtwdev, R_AX_SER_DBG_INFO)); 764 rtw89_info(rtwdev, "DBG Counter 1 (R_AX_DRV_FW_HSK_4)=0x%08x\n", 765 rtw89_read32(rtwdev, R_AX_DRV_FW_HSK_4)); 766 rtw89_info(rtwdev, "DBG Counter 2 (R_AX_DRV_FW_HSK_5)=0x%08x\n", 767 rtw89_read32(rtwdev, R_AX_DRV_FW_HSK_5)); 768 769 rtw89_mac_dump_dmac_err_status(rtwdev); 770 rtw89_mac_dump_cmac_err_status_ax(rtwdev, RTW89_MAC_0); 771 rtw89_mac_dump_cmac_err_status_ax(rtwdev, RTW89_MAC_1); 772 773 rtwdev->hci.ops->dump_err_status(rtwdev); 774 775 if (err == MAC_AX_ERR_L0_PROMOTE_TO_L1) 776 rtw89_mac_dump_l0_to_l1(rtwdev, err); 777 778 rtw89_info(rtwdev, "<---\n"); 779 } 780 781 static bool rtw89_mac_suppress_log(struct rtw89_dev *rtwdev, u32 err) 782 { 783 struct rtw89_ser *ser = &rtwdev->ser; 784 u32 dmac_err, imr, isr; 785 int ret; 786 787 if (rtwdev->chip->chip_id == RTL8852C) { 788 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 789 if (ret) 790 return true; 791 792 if (err == MAC_AX_ERR_L1_ERR_DMAC) { 793 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 794 imr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR); 795 isr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR); 796 797 if ((dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) && 798 ((isr & imr) & B_AX_B0_ISR_ERR_CMDPSR_FRZTO)) { 799 set_bit(RTW89_SER_SUPPRESS_LOG, ser->flags); 800 return true; 801 } 802 } else if (err == MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE) { 803 if (test_bit(RTW89_SER_SUPPRESS_LOG, ser->flags)) 804 return true; 805 } else if (err == MAC_AX_ERR_L1_RESET_RECOVERY_DONE) { 806 if (test_and_clear_bit(RTW89_SER_SUPPRESS_LOG, ser->flags)) 807 return true; 808 } 809 } 810 811 return false; 812 } 813 814 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev) 815 { 816 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 817 const struct rtw89_chip_info *chip = rtwdev->chip; 818 u32 err, err_scnr; 819 int ret; 820 821 ret = read_poll_timeout(rtw89_read32, err, (err != 0), 1000, 100000, 822 false, rtwdev, R_AX_HALT_C2H_CTRL); 823 if (ret) { 824 rtw89_warn(rtwdev, "Polling FW err status fail\n"); 825 return ret; 826 } 827 828 err = rtw89_read32(rtwdev, R_AX_HALT_C2H); 829 830 if (!RTW89_CHK_FW_FEATURE(SER_POST_RECOVER_DMAC, &rtwdev->fw)) 831 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 832 833 err_scnr = RTW89_ERROR_SCENARIO(err); 834 if (err_scnr == RTW89_WCPU_CPU_EXCEPTION) 835 err = MAC_AX_ERR_CPU_EXCEPTION; 836 else if (err_scnr == RTW89_WCPU_ASSERTION) 837 err = MAC_AX_ERR_ASSERTION; 838 else if (err_scnr == RTW89_RXI300_ERROR) 839 err = MAC_AX_ERR_RXI300; 840 841 if (rtw89_mac_suppress_log(rtwdev, err)) 842 goto bottom; 843 844 rtw89_fw_st_dbg_dump(rtwdev); 845 mac->dump_err_status(rtwdev, err); 846 847 bottom: 848 if (chip->chip_gen != RTW89_CHIP_AX) 849 rtw89_write32(rtwdev, R_AX_HALT_C2H, 0); 850 851 if (RTW89_CHK_FW_FEATURE(SER_POST_RECOVER_DMAC, &rtwdev->fw)) 852 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 853 854 return err; 855 } 856 EXPORT_SYMBOL(rtw89_mac_get_err_status); 857 858 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err) 859 { 860 struct rtw89_ser *ser = &rtwdev->ser; 861 bool ser_l1_hdl = false; 862 u32 halt; 863 int ret = 0; 864 865 if (err > MAC_AX_SET_ERR_MAX) { 866 rtw89_err(rtwdev, "Bad set-err-status value 0x%08x\n", err); 867 return -EINVAL; 868 } 869 870 if (err == MAC_AX_ERR_L1_DISABLE_EN || err == MAC_AX_ERR_L1_RCVY_EN) 871 ser_l1_hdl = true; 872 873 if (RTW89_CHK_FW_FEATURE(SER_L1_BY_EVENT, &rtwdev->fw) && ser_l1_hdl) 874 goto set; 875 876 ret = read_poll_timeout(rtw89_read32, halt, (halt == 0x0), 1000, 877 100000, false, rtwdev, R_AX_HALT_H2C_CTRL); 878 if (ret) { 879 rtw89_err(rtwdev, "FW doesn't receive previous msg\n"); 880 return -EFAULT; 881 } 882 883 set: 884 rtw89_write32(rtwdev, R_AX_HALT_H2C, err); 885 886 if (ser->prehandle_l1 && ser_l1_hdl) 887 return 0; 888 889 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, B_AX_HALT_H2C_TRIGGER); 890 891 return 0; 892 } 893 EXPORT_SYMBOL(rtw89_mac_set_err_status); 894 895 static int hfc_reset_param(struct rtw89_dev *rtwdev) 896 { 897 const struct rtw89_qta_def *qta_def = rtw89_chip_get_qta_def(rtwdev); 898 const struct rtw89_hfc_param_ini *param_ini, *param_inis; 899 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 900 u8 qta_mode = rtwdev->mac.dle_info.qta_mode; 901 902 param_inis = qta_def->hfc_param_ini[rtwdev->hci.dle_type]; 903 if (!param_inis) 904 return -EINVAL; 905 906 param_ini = ¶m_inis[qta_mode]; 907 908 param->en = 0; 909 910 if (param_ini->pub_cfg) 911 param->pub_cfg = *param_ini->pub_cfg; 912 913 if (param_ini->prec_cfg) 914 param->prec_cfg = *param_ini->prec_cfg; 915 916 if (param_ini->ch_cfg) 917 param->ch_cfg = param_ini->ch_cfg; 918 919 memset(¶m->ch_info, 0, sizeof(param->ch_info)); 920 memset(¶m->pub_info, 0, sizeof(param->pub_info)); 921 param->mode = param_ini->mode; 922 923 return 0; 924 } 925 926 static int hfc_ch_cfg_chk(struct rtw89_dev *rtwdev, u8 ch) 927 { 928 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 929 const struct rtw89_hfc_ch_cfg *ch_cfg = param->ch_cfg; 930 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 931 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 932 933 if (ch >= RTW89_DMA_CH_NUM) 934 return -EINVAL; 935 936 if ((ch_cfg[ch].min && ch_cfg[ch].min < prec_cfg->ch011_prec) || 937 ch_cfg[ch].max > pub_cfg->pub_max) 938 return -EINVAL; 939 if (ch_cfg[ch].grp >= grp_num) 940 return -EINVAL; 941 942 return 0; 943 } 944 945 static int hfc_pub_info_chk(struct rtw89_dev *rtwdev) 946 { 947 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 948 const struct rtw89_hfc_pub_cfg *cfg = ¶m->pub_cfg; 949 struct rtw89_hfc_pub_info *info = ¶m->pub_info; 950 951 if (info->g0_used + info->g1_used + info->pub_aval != cfg->pub_max) { 952 if (rtwdev->chip->chip_id == RTL8852A) 953 return 0; 954 else 955 return -EFAULT; 956 } 957 958 return 0; 959 } 960 961 static int hfc_pub_cfg_chk(struct rtw89_dev *rtwdev) 962 { 963 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 964 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 965 966 if (pub_cfg->grp0 + pub_cfg->grp1 != pub_cfg->pub_max) 967 return -EFAULT; 968 969 return 0; 970 } 971 972 static int hfc_ch_ctrl(struct rtw89_dev *rtwdev, u8 ch) 973 { 974 const struct rtw89_chip_info *chip = rtwdev->chip; 975 const struct rtw89_page_regs *regs = chip->page_regs; 976 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 977 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 978 int ret = 0; 979 u32 val = 0; 980 981 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 982 if (ret) 983 return ret; 984 985 ret = hfc_ch_cfg_chk(rtwdev, ch); 986 if (ret) 987 return ret; 988 989 if (ch > RTW89_DMA_B1HI) 990 return -EINVAL; 991 992 val = u32_encode_bits(cfg[ch].min, B_AX_MIN_PG_MASK) | 993 u32_encode_bits(cfg[ch].max, B_AX_MAX_PG_MASK) | 994 (cfg[ch].grp ? B_AX_GRP : 0); 995 rtw89_write32(rtwdev, regs->ach_page_ctrl + ch * 4, val); 996 997 return 0; 998 } 999 1000 static int hfc_upd_ch_info(struct rtw89_dev *rtwdev, u8 ch) 1001 { 1002 const struct rtw89_chip_info *chip = rtwdev->chip; 1003 const struct rtw89_page_regs *regs = chip->page_regs; 1004 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1005 struct rtw89_hfc_ch_info *info = param->ch_info; 1006 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 1007 u32 val; 1008 int ret; 1009 1010 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1011 if (ret) 1012 return ret; 1013 1014 if (ch > RTW89_DMA_H2C) 1015 return -EINVAL; 1016 1017 val = rtw89_read32(rtwdev, regs->ach_page_info + ch * 4); 1018 info[ch].aval = u32_get_bits(val, B_AX_AVAL_PG_MASK); 1019 if (ch < RTW89_DMA_H2C) 1020 info[ch].used = u32_get_bits(val, B_AX_USE_PG_MASK); 1021 else 1022 info[ch].used = cfg[ch].min - info[ch].aval; 1023 1024 return 0; 1025 } 1026 1027 static int hfc_pub_ctrl(struct rtw89_dev *rtwdev) 1028 { 1029 const struct rtw89_chip_info *chip = rtwdev->chip; 1030 const struct rtw89_page_regs *regs = chip->page_regs; 1031 const struct rtw89_hfc_pub_cfg *cfg = &rtwdev->mac.hfc_param.pub_cfg; 1032 u32 val; 1033 int ret; 1034 1035 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1036 if (ret) 1037 return ret; 1038 1039 ret = hfc_pub_cfg_chk(rtwdev); 1040 if (ret) 1041 return ret; 1042 1043 val = u32_encode_bits(cfg->grp0, B_AX_PUBPG_G0_MASK) | 1044 u32_encode_bits(cfg->grp1, B_AX_PUBPG_G1_MASK); 1045 rtw89_write32(rtwdev, regs->pub_page_ctrl1, val); 1046 1047 val = u32_encode_bits(cfg->wp_thrd, B_AX_WP_THRD_MASK); 1048 rtw89_write32(rtwdev, regs->wp_page_ctrl2, val); 1049 1050 return 0; 1051 } 1052 1053 static void hfc_get_mix_info_ax(struct rtw89_dev *rtwdev) 1054 { 1055 const struct rtw89_chip_info *chip = rtwdev->chip; 1056 const struct rtw89_page_regs *regs = chip->page_regs; 1057 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1058 struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 1059 struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 1060 struct rtw89_hfc_pub_info *info = ¶m->pub_info; 1061 u32 val; 1062 1063 val = rtw89_read32(rtwdev, regs->pub_page_info1); 1064 info->g0_used = u32_get_bits(val, B_AX_G0_USE_PG_MASK); 1065 info->g1_used = u32_get_bits(val, B_AX_G1_USE_PG_MASK); 1066 val = rtw89_read32(rtwdev, regs->pub_page_info3); 1067 info->g0_aval = u32_get_bits(val, B_AX_G0_AVAL_PG_MASK); 1068 info->g1_aval = u32_get_bits(val, B_AX_G1_AVAL_PG_MASK); 1069 info->pub_aval = 1070 u32_get_bits(rtw89_read32(rtwdev, regs->pub_page_info2), 1071 B_AX_PUB_AVAL_PG_MASK); 1072 info->wp_aval = 1073 u32_get_bits(rtw89_read32(rtwdev, regs->wp_page_info1), 1074 B_AX_WP_AVAL_PG_MASK); 1075 1076 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 1077 param->en = val & B_AX_HCI_FC_EN ? 1 : 0; 1078 param->h2c_en = val & B_AX_HCI_FC_CH12_EN ? 1 : 0; 1079 param->mode = u32_get_bits(val, B_AX_HCI_FC_MODE_MASK); 1080 prec_cfg->ch011_full_cond = 1081 u32_get_bits(val, B_AX_HCI_FC_WD_FULL_COND_MASK); 1082 prec_cfg->h2c_full_cond = 1083 u32_get_bits(val, B_AX_HCI_FC_CH12_FULL_COND_MASK); 1084 prec_cfg->wp_ch07_full_cond = 1085 u32_get_bits(val, B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 1086 prec_cfg->wp_ch811_full_cond = 1087 u32_get_bits(val, B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 1088 1089 val = rtw89_read32(rtwdev, regs->ch_page_ctrl); 1090 prec_cfg->ch011_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH011_MASK); 1091 prec_cfg->h2c_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH12_MASK); 1092 1093 val = rtw89_read32(rtwdev, regs->pub_page_ctrl2); 1094 pub_cfg->pub_max = u32_get_bits(val, B_AX_PUBPG_ALL_MASK); 1095 1096 val = rtw89_read32(rtwdev, regs->wp_page_ctrl1); 1097 prec_cfg->wp_ch07_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH07_MASK); 1098 prec_cfg->wp_ch811_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH811_MASK); 1099 1100 val = rtw89_read32(rtwdev, regs->wp_page_ctrl2); 1101 pub_cfg->wp_thrd = u32_get_bits(val, B_AX_WP_THRD_MASK); 1102 1103 val = rtw89_read32(rtwdev, regs->pub_page_ctrl1); 1104 pub_cfg->grp0 = u32_get_bits(val, B_AX_PUBPG_G0_MASK); 1105 pub_cfg->grp1 = u32_get_bits(val, B_AX_PUBPG_G1_MASK); 1106 } 1107 1108 static int hfc_upd_mix_info(struct rtw89_dev *rtwdev) 1109 { 1110 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1111 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1112 int ret; 1113 1114 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1115 if (ret) 1116 return ret; 1117 1118 mac->hfc_get_mix_info(rtwdev); 1119 1120 ret = hfc_pub_info_chk(rtwdev); 1121 if (param->en && ret) 1122 return ret; 1123 1124 return 0; 1125 } 1126 1127 static void hfc_h2c_cfg_ax(struct rtw89_dev *rtwdev) 1128 { 1129 const struct rtw89_chip_info *chip = rtwdev->chip; 1130 const struct rtw89_page_regs *regs = chip->page_regs; 1131 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1132 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 1133 u32 val; 1134 1135 val = u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 1136 rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 1137 1138 rtw89_write32_mask(rtwdev, regs->hci_fc_ctrl, 1139 B_AX_HCI_FC_CH12_FULL_COND_MASK, 1140 prec_cfg->h2c_full_cond); 1141 } 1142 1143 static void hfc_mix_cfg_ax(struct rtw89_dev *rtwdev) 1144 { 1145 const struct rtw89_chip_info *chip = rtwdev->chip; 1146 const struct rtw89_page_regs *regs = chip->page_regs; 1147 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1148 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 1149 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 1150 u32 val; 1151 1152 val = u32_encode_bits(prec_cfg->ch011_prec, B_AX_PREC_PAGE_CH011_MASK) | 1153 u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 1154 rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 1155 1156 val = u32_encode_bits(pub_cfg->pub_max, B_AX_PUBPG_ALL_MASK); 1157 rtw89_write32(rtwdev, regs->pub_page_ctrl2, val); 1158 1159 val = u32_encode_bits(prec_cfg->wp_ch07_prec, 1160 B_AX_PREC_PAGE_WP_CH07_MASK) | 1161 u32_encode_bits(prec_cfg->wp_ch811_prec, 1162 B_AX_PREC_PAGE_WP_CH811_MASK); 1163 rtw89_write32(rtwdev, regs->wp_page_ctrl1, val); 1164 1165 val = u32_replace_bits(rtw89_read32(rtwdev, regs->hci_fc_ctrl), 1166 param->mode, B_AX_HCI_FC_MODE_MASK); 1167 val = u32_replace_bits(val, prec_cfg->ch011_full_cond, 1168 B_AX_HCI_FC_WD_FULL_COND_MASK); 1169 val = u32_replace_bits(val, prec_cfg->h2c_full_cond, 1170 B_AX_HCI_FC_CH12_FULL_COND_MASK); 1171 val = u32_replace_bits(val, prec_cfg->wp_ch07_full_cond, 1172 B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 1173 val = u32_replace_bits(val, prec_cfg->wp_ch811_full_cond, 1174 B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 1175 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 1176 } 1177 1178 static void hfc_func_en_ax(struct rtw89_dev *rtwdev, bool en, bool h2c_en) 1179 { 1180 const struct rtw89_chip_info *chip = rtwdev->chip; 1181 const struct rtw89_page_regs *regs = chip->page_regs; 1182 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1183 u32 val; 1184 1185 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 1186 param->en = en; 1187 param->h2c_en = h2c_en; 1188 val = en ? (val | B_AX_HCI_FC_EN) : (val & ~B_AX_HCI_FC_EN); 1189 val = h2c_en ? (val | B_AX_HCI_FC_CH12_EN) : 1190 (val & ~B_AX_HCI_FC_CH12_EN); 1191 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 1192 } 1193 1194 int rtw89_mac_hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en) 1195 { 1196 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1197 const struct rtw89_chip_info *chip = rtwdev->chip; 1198 u32 dma_ch_mask = chip->dma_ch_mask; 1199 int ret = 0; 1200 u8 ch; 1201 1202 if (reset) 1203 ret = hfc_reset_param(rtwdev); 1204 if (ret) 1205 return ret; 1206 1207 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1208 if (ret) 1209 return ret; 1210 1211 mac->hfc_func_en(rtwdev, false, false); 1212 1213 if (!en && h2c_en) { 1214 mac->hfc_h2c_cfg(rtwdev); 1215 mac->hfc_func_en(rtwdev, en, h2c_en); 1216 return 0; 1217 } 1218 1219 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 1220 if (dma_ch_mask & BIT(ch)) 1221 continue; 1222 ret = hfc_ch_ctrl(rtwdev, ch); 1223 if (ret) 1224 return ret; 1225 } 1226 1227 ret = hfc_pub_ctrl(rtwdev); 1228 if (ret) 1229 return ret; 1230 1231 mac->hfc_mix_cfg(rtwdev); 1232 if (en || h2c_en) { 1233 mac->hfc_func_en(rtwdev, en, h2c_en); 1234 udelay(10); 1235 } 1236 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 1237 if (dma_ch_mask & BIT(ch)) 1238 continue; 1239 ret = hfc_upd_ch_info(rtwdev, ch); 1240 if (ret) 1241 return ret; 1242 } 1243 ret = hfc_upd_mix_info(rtwdev); 1244 1245 return ret; 1246 } 1247 1248 #define PWR_POLL_CNT 2000 1249 static int pwr_cmd_poll(struct rtw89_dev *rtwdev, 1250 const struct rtw89_pwr_cfg *cfg) 1251 { 1252 u8 val = 0; 1253 int ret; 1254 u32 addr = cfg->base == PWR_INTF_MSK_SDIO ? 1255 cfg->addr | SDIO_LOCAL_BASE_ADDR : cfg->addr; 1256 1257 ret = read_poll_timeout(rtw89_read8, val, !((val ^ cfg->val) & cfg->msk), 1258 1000, 1000 * PWR_POLL_CNT, false, rtwdev, addr); 1259 1260 if (!ret) 1261 return 0; 1262 1263 rtw89_warn(rtwdev, "[ERR] Polling timeout\n"); 1264 rtw89_warn(rtwdev, "[ERR] addr: %X, %X\n", addr, cfg->addr); 1265 rtw89_warn(rtwdev, "[ERR] val: %X, %X\n", val, cfg->val); 1266 1267 return -EBUSY; 1268 } 1269 1270 static int rtw89_mac_sub_pwr_seq(struct rtw89_dev *rtwdev, u8 cv_msk, 1271 u8 intf_msk, const struct rtw89_pwr_cfg *cfg) 1272 { 1273 const struct rtw89_pwr_cfg *cur_cfg; 1274 u32 addr; 1275 u8 val; 1276 1277 for (cur_cfg = cfg; cur_cfg->cmd != PWR_CMD_END; cur_cfg++) { 1278 if (!(cur_cfg->intf_msk & intf_msk) || 1279 !(cur_cfg->cv_msk & cv_msk)) 1280 continue; 1281 1282 switch (cur_cfg->cmd) { 1283 case PWR_CMD_WRITE: 1284 addr = cur_cfg->addr; 1285 1286 if (cur_cfg->base == PWR_BASE_SDIO) 1287 addr |= SDIO_LOCAL_BASE_ADDR; 1288 1289 val = rtw89_read8(rtwdev, addr); 1290 val &= ~(cur_cfg->msk); 1291 val |= (cur_cfg->val & cur_cfg->msk); 1292 1293 rtw89_write8(rtwdev, addr, val); 1294 break; 1295 case PWR_CMD_POLL: 1296 if (pwr_cmd_poll(rtwdev, cur_cfg)) 1297 return -EBUSY; 1298 break; 1299 case PWR_CMD_DELAY: 1300 if (cur_cfg->val == PWR_DELAY_US) 1301 udelay(cur_cfg->addr); 1302 else 1303 fsleep(cur_cfg->addr * 1000); 1304 break; 1305 default: 1306 return -EINVAL; 1307 } 1308 } 1309 1310 return 0; 1311 } 1312 1313 static int rtw89_mac_pwr_seq(struct rtw89_dev *rtwdev, 1314 const struct rtw89_pwr_cfg * const *cfg_seq) 1315 { 1316 u8 intf_msk; 1317 int ret; 1318 1319 switch (rtwdev->hci.type) { 1320 case RTW89_HCI_TYPE_PCIE: 1321 intf_msk = PWR_INTF_MSK_PCIE; 1322 break; 1323 case RTW89_HCI_TYPE_USB: 1324 intf_msk = PWR_INTF_MSK_USB; 1325 break; 1326 case RTW89_HCI_TYPE_SDIO: 1327 intf_msk = PWR_INTF_MSK_SDIO; 1328 break; 1329 default: 1330 return -EOPNOTSUPP; 1331 } 1332 1333 for (; *cfg_seq; cfg_seq++) { 1334 ret = rtw89_mac_sub_pwr_seq(rtwdev, BIT(rtwdev->hal.cv), 1335 intf_msk, *cfg_seq); 1336 if (ret) 1337 return -EBUSY; 1338 } 1339 1340 return 0; 1341 } 1342 1343 static enum rtw89_rpwm_req_pwr_state 1344 rtw89_mac_get_req_pwr_state(struct rtw89_dev *rtwdev) 1345 { 1346 enum rtw89_rpwm_req_pwr_state state; 1347 1348 switch (rtwdev->ps_mode) { 1349 case RTW89_PS_MODE_RFOFF: 1350 state = RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF; 1351 break; 1352 case RTW89_PS_MODE_CLK_GATED: 1353 state = RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED; 1354 break; 1355 case RTW89_PS_MODE_PWR_GATED: 1356 state = RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED; 1357 break; 1358 default: 1359 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1360 break; 1361 } 1362 return state; 1363 } 1364 1365 static void rtw89_mac_send_rpwm(struct rtw89_dev *rtwdev, 1366 enum rtw89_rpwm_req_pwr_state req_pwr_state, 1367 bool notify_wake) 1368 { 1369 u16 request; 1370 1371 spin_lock_bh(&rtwdev->rpwm_lock); 1372 1373 request = rtw89_read16(rtwdev, R_AX_RPWM); 1374 request ^= request | PS_RPWM_TOGGLE; 1375 request |= req_pwr_state; 1376 1377 if (notify_wake) { 1378 request |= PS_RPWM_NOTIFY_WAKE; 1379 } else { 1380 rtwdev->mac.rpwm_seq_num = (rtwdev->mac.rpwm_seq_num + 1) & 1381 RPWM_SEQ_NUM_MAX; 1382 request |= FIELD_PREP(PS_RPWM_SEQ_NUM, 1383 rtwdev->mac.rpwm_seq_num); 1384 1385 if (req_pwr_state < RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1386 request |= PS_RPWM_ACK; 1387 } 1388 rtw89_write16(rtwdev, rtwdev->hci.rpwm_addr, request); 1389 1390 spin_unlock_bh(&rtwdev->rpwm_lock); 1391 } 1392 1393 static int rtw89_mac_check_cpwm_state(struct rtw89_dev *rtwdev, 1394 enum rtw89_rpwm_req_pwr_state req_pwr_state) 1395 { 1396 bool request_deep_mode; 1397 bool in_deep_mode; 1398 u8 rpwm_req_num; 1399 u8 cpwm_rsp_seq; 1400 u8 cpwm_seq; 1401 u8 cpwm_status; 1402 1403 if (req_pwr_state >= RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1404 request_deep_mode = true; 1405 else 1406 request_deep_mode = false; 1407 1408 if (rtw89_read32_mask(rtwdev, R_AX_LDM, B_AX_EN_32K)) 1409 in_deep_mode = true; 1410 else 1411 in_deep_mode = false; 1412 1413 if (request_deep_mode != in_deep_mode) 1414 return -EPERM; 1415 1416 if (request_deep_mode) 1417 return 0; 1418 1419 rpwm_req_num = rtwdev->mac.rpwm_seq_num; 1420 cpwm_rsp_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, 1421 PS_CPWM_RSP_SEQ_NUM); 1422 1423 if (rpwm_req_num != cpwm_rsp_seq) 1424 return -EPERM; 1425 1426 rtwdev->mac.cpwm_seq_num = (rtwdev->mac.cpwm_seq_num + 1) & 1427 CPWM_SEQ_NUM_MAX; 1428 1429 cpwm_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_SEQ_NUM); 1430 if (cpwm_seq != rtwdev->mac.cpwm_seq_num) 1431 return -EPERM; 1432 1433 cpwm_status = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_STATE); 1434 if (cpwm_status != req_pwr_state) 1435 return -EPERM; 1436 1437 return 0; 1438 } 1439 1440 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter) 1441 { 1442 enum rtw89_rpwm_req_pwr_state state; 1443 unsigned long delay = enter ? 10 : 150; 1444 int ret; 1445 int i; 1446 1447 if (enter) 1448 state = rtw89_mac_get_req_pwr_state(rtwdev); 1449 else 1450 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1451 1452 for (i = 0; i < RPWM_TRY_CNT; i++) { 1453 rtw89_mac_send_rpwm(rtwdev, state, false); 1454 ret = read_poll_timeout_atomic(rtw89_mac_check_cpwm_state, ret, 1455 !ret, delay, 15000, false, 1456 rtwdev, state); 1457 if (!ret) 1458 break; 1459 1460 if (i == RPWM_TRY_CNT - 1) { 1461 rtw89_err(rtwdev, "firmware failed to ack for %s ps mode\n", 1462 enter ? "entering" : "leaving"); 1463 rtw89_ser_notify(rtwdev, MAC_AX_ERR_ASSERTION); 1464 } else { 1465 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, 1466 "%d time firmware failed to ack for %s ps mode\n", 1467 i + 1, enter ? "entering" : "leaving"); 1468 } 1469 } 1470 } 1471 1472 void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev) 1473 { 1474 enum rtw89_rpwm_req_pwr_state state; 1475 1476 state = rtw89_mac_get_req_pwr_state(rtwdev); 1477 rtw89_mac_send_rpwm(rtwdev, state, true); 1478 } 1479 1480 static void rtw89_mac_power_switch_boot_mode(struct rtw89_dev *rtwdev) 1481 { 1482 u32 boot_mode; 1483 1484 if (rtwdev->hci.type != RTW89_HCI_TYPE_USB) 1485 return; 1486 1487 boot_mode = rtw89_read32_mask(rtwdev, R_AX_GPIO_MUXCFG, B_AX_BOOT_MODE); 1488 if (!boot_mode) 1489 return; 1490 1491 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC); 1492 rtw89_write32_clr(rtwdev, R_AX_SYS_STATUS1, B_AX_AUTO_WLPON); 1493 rtw89_write32_clr(rtwdev, R_AX_GPIO_MUXCFG, B_AX_BOOT_MODE); 1494 rtw89_write32_clr(rtwdev, R_AX_RSV_CTRL, B_AX_R_DIS_PRST); 1495 } 1496 1497 static int rtw89_mac_pwr_off_func_for_unplugged(struct rtw89_dev *rtwdev) 1498 { 1499 /* 1500 * Avoid accessing IO for unplugged power-off to prevent warnings, 1501 * especially XTAL SI. 1502 */ 1503 return 0; 1504 } 1505 1506 static void rtw89_mac_update_scoreboard(struct rtw89_dev *rtwdev, u8 val) 1507 { 1508 const struct rtw89_chip_info *chip = rtwdev->chip; 1509 u32 reg; 1510 int i; 1511 1512 for (i = 0; i < ARRAY_SIZE(chip->btc_sb.n); i++) { 1513 reg = chip->btc_sb.n[i].cfg; 1514 if (!reg) 1515 continue; 1516 1517 rtw89_write8(rtwdev, reg + 3, val); 1518 } 1519 } 1520 1521 static int rtw89_mac_power_switch(struct rtw89_dev *rtwdev, bool on) 1522 { 1523 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1524 const struct rtw89_chip_info *chip = rtwdev->chip; 1525 const struct rtw89_pwr_cfg * const *cfg_seq; 1526 int (*cfg_func)(struct rtw89_dev *rtwdev); 1527 int ret; 1528 1529 rtw89_mac_power_switch_boot_mode(rtwdev); 1530 1531 if (on) { 1532 cfg_seq = chip->pwr_on_seq; 1533 cfg_func = chip->ops->pwr_on_func; 1534 } else { 1535 if (test_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags)) { 1536 cfg_seq = NULL; 1537 cfg_func = rtw89_mac_pwr_off_func_for_unplugged; 1538 } else { 1539 cfg_seq = chip->pwr_off_seq; 1540 cfg_func = chip->ops->pwr_off_func; 1541 } 1542 } 1543 1544 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 1545 __rtw89_leave_ps_mode(rtwdev); 1546 1547 if (on) { 1548 ret = mac->reset_pwr_state(rtwdev); 1549 if (ret) 1550 return ret; 1551 } 1552 1553 ret = cfg_func ? cfg_func(rtwdev) : rtw89_mac_pwr_seq(rtwdev, cfg_seq); 1554 if (ret) 1555 return ret; 1556 1557 if (on) { 1558 if (!test_bit(RTW89_FLAG_PROBE_DONE, rtwdev->flags)) { 1559 rtw89_mac_efuse_read_ecv(rtwdev); 1560 mac->efuse_read_fw_secure(rtwdev); 1561 rtw89_mac_efuse_read_thermal_k(rtwdev); 1562 rtw89_mac_efuse_read_pwr_data(rtwdev); 1563 } 1564 1565 set_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1566 set_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags); 1567 set_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags); 1568 1569 rtw89_mac_update_scoreboard(rtwdev, MAC_AX_NOTIFY_TP_MAJOR); 1570 rtw89_mac_clr_aon_intr(rtwdev); 1571 } else { 1572 clear_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1573 clear_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags); 1574 clear_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags); 1575 clear_bit(RTW89_FLAG_CMAC1_FUNC, rtwdev->flags); 1576 clear_bit(RTW89_FLAG_CMAC0_PWR, rtwdev->flags); 1577 clear_bit(RTW89_FLAG_CMAC1_PWR, rtwdev->flags); 1578 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 1579 1580 rtw89_mac_update_scoreboard(rtwdev, MAC_AX_NOTIFY_PWR_MAJOR); 1581 rtw89_set_entity_state(rtwdev, RTW89_PHY_0, false); 1582 rtw89_set_entity_state(rtwdev, RTW89_PHY_1, false); 1583 } 1584 1585 return 0; 1586 } 1587 1588 int rtw89_mac_pwr_on(struct rtw89_dev *rtwdev) 1589 { 1590 int ret; 1591 1592 ret = rtw89_mac_power_switch(rtwdev, true); 1593 if (ret) { 1594 rtw89_mac_power_switch(rtwdev, false); 1595 ret = rtw89_mac_power_switch(rtwdev, true); 1596 if (ret) 1597 return ret; 1598 } 1599 1600 return 0; 1601 } 1602 1603 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev) 1604 { 1605 rtw89_mac_set_vcore_reset(rtwdev); 1606 1607 rtw89_mac_power_switch(rtwdev, false); 1608 } 1609 1610 static int cmac_func_en_ax(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 1611 { 1612 u32 func_en = 0; 1613 u32 ck_en = 0; 1614 u32 c1pc_en = 0; 1615 u32 addrl_func_en[] = {R_AX_CMAC_FUNC_EN, R_AX_CMAC_FUNC_EN_C1}; 1616 u32 addrl_ck_en[] = {R_AX_CK_EN, R_AX_CK_EN_C1}; 1617 1618 func_en = B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | 1619 B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | 1620 B_AX_SCHEDULER_EN | B_AX_TMAC_EN | B_AX_RMAC_EN | 1621 B_AX_CMAC_CRPRT; 1622 ck_en = B_AX_CMAC_CKEN | B_AX_PHYINTF_CKEN | B_AX_CMAC_DMA_CKEN | 1623 B_AX_PTCLTOP_CKEN | B_AX_SCHEDULER_CKEN | B_AX_TMAC_CKEN | 1624 B_AX_RMAC_CKEN; 1625 c1pc_en = B_AX_R_SYM_WLCMAC1_PC_EN | 1626 B_AX_R_SYM_WLCMAC1_P1_PC_EN | 1627 B_AX_R_SYM_WLCMAC1_P2_PC_EN | 1628 B_AX_R_SYM_WLCMAC1_P3_PC_EN | 1629 B_AX_R_SYM_WLCMAC1_P4_PC_EN; 1630 1631 if (en) { 1632 if (mac_idx == RTW89_MAC_1) { 1633 rtw89_write32_set(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1634 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1635 B_AX_R_SYM_ISO_CMAC12PP); 1636 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1637 B_AX_CMAC1_FEN); 1638 } 1639 rtw89_write32_set(rtwdev, addrl_ck_en[mac_idx], ck_en); 1640 rtw89_write32_set(rtwdev, addrl_func_en[mac_idx], func_en); 1641 } else { 1642 rtw89_write32_clr(rtwdev, addrl_func_en[mac_idx], func_en); 1643 rtw89_write32_clr(rtwdev, addrl_ck_en[mac_idx], ck_en); 1644 if (mac_idx == RTW89_MAC_1) { 1645 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1646 B_AX_CMAC1_FEN); 1647 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1648 B_AX_R_SYM_ISO_CMAC12PP); 1649 rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1650 } 1651 } 1652 1653 return 0; 1654 } 1655 1656 static int dmac_func_en_ax(struct rtw89_dev *rtwdev) 1657 { 1658 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1659 u32 val32; 1660 1661 if (chip_id == RTL8852C) 1662 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1663 B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1664 B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1665 B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1666 B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1667 B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1668 B_AX_DMAC_CRPRT | B_AX_H_AXIDMA_EN); 1669 else 1670 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1671 B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1672 B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1673 B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1674 B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1675 B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1676 B_AX_DMAC_CRPRT); 1677 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val32); 1678 1679 val32 = (B_AX_MAC_SEC_CLK_EN | B_AX_DISPATCHER_CLK_EN | 1680 B_AX_DLE_CPUIO_CLK_EN | B_AX_PKT_IN_CLK_EN | 1681 B_AX_STA_SCH_CLK_EN | B_AX_TXPKT_CTRL_CLK_EN | 1682 B_AX_WD_RLS_CLK_EN | B_AX_BBRPT_CLK_EN); 1683 if (chip_id == RTL8852BT) 1684 val32 |= B_AX_AXIDMA_CLK_EN; 1685 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val32); 1686 1687 return 0; 1688 } 1689 1690 static int chip_func_en_ax(struct rtw89_dev *rtwdev) 1691 { 1692 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1693 1694 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) 1695 rtw89_write32_set(rtwdev, R_AX_SPS_DIG_ON_CTRL0, 1696 B_AX_OCP_L1_MASK); 1697 1698 return 0; 1699 } 1700 1701 static int sys_init_ax(struct rtw89_dev *rtwdev) 1702 { 1703 int ret; 1704 1705 ret = dmac_func_en_ax(rtwdev); 1706 if (ret) 1707 return ret; 1708 1709 ret = cmac_func_en_ax(rtwdev, 0, true); 1710 if (ret) 1711 return ret; 1712 1713 return chip_func_en_ax(rtwdev); 1714 } 1715 1716 const struct rtw89_mac_size_set rtw89_mac_size = { 1717 .hfc_preccfg_pcie = {2, 40, 0, 0, 1, 0, 0, 0}, 1718 .hfc_prec_cfg_c0 = {2, 32, 0, 0, 0, 0, 0, 0, 2, 32, 0, 0}, 1719 .hfc_prec_cfg_c2 = {0, 256, 0, 0, 0, 0, 0, 0, 0, 256, 0, 0}, 1720 .hfc_prec_cfg_c3 = {18, 32, 148, 148, 1, 1, 1, 1}, 1721 .hfc_prec_cfg_c5 = {18, 32, 148, 148, 1, 1, 0, 1}, 1722 .hfc_prec_cfg_c6 = {8, 32, 148, 148, 1, 1, 0, 1}, 1723 /* PCIE 64 */ 1724 .wde_size0 = {RTW89_WDE_PG_64, 4095, 1,}, 1725 .wde_size0_v1 = {RTW89_WDE_PG_64, 3328, 0, 0,}, 1726 /* 8852A USB */ 1727 .wde_size1 = {RTW89_WDE_PG_64, 768, 0,}, 1728 /* DLFW */ 1729 .wde_size3_v1 = {RTW89_WDE_PG_64, 0, 3328, 0,}, 1730 .wde_size4 = {RTW89_WDE_PG_64, 0, 4096,}, 1731 /* 8922A USB3.0 */ 1732 .wde_size4_v1 = {RTW89_WDE_PG_64, 892, 4, 0,}, 1733 .wde_size5_v1 = {RTW89_WDE_PG_64, 864, 32, 0,}, 1734 /* PCIE 64 */ 1735 .wde_size6 = {RTW89_WDE_PG_64, 512, 0,}, 1736 /* 8852B PCIE SCC */ 1737 .wde_size7 = {RTW89_WDE_PG_64, 510, 2,}, 1738 /* 8922A USB2.0 */ 1739 .wde_size7_v1 = {RTW89_WDE_PG_64, 508, 4,}, 1740 .wde_size8_v1 = {RTW89_WDE_PG_64, 634, 6,}, 1741 /* DLFW */ 1742 .wde_size9 = {RTW89_WDE_PG_64, 0, 1024,}, 1743 .wde_size16_v1 = {RTW89_WDE_PG_64, 639, 1, 0,}, 1744 /* 8852C USB3.0 */ 1745 .wde_size17 = {RTW89_WDE_PG_64, 354, 30,}, 1746 /* 8852C DLFW */ 1747 .wde_size18 = {RTW89_WDE_PG_64, 0, 2048,}, 1748 .wde_size18_v1 = {RTW89_WDE_PG_64, 0, 640, 0,}, 1749 /* 8852C PCIE SCC */ 1750 .wde_size19 = {RTW89_WDE_PG_64, 3328, 0,}, 1751 .wde_size22_v1 = {RTW89_WDE_PG_128, 384, 0, 0,}, 1752 .wde_size23 = {RTW89_WDE_PG_64, 1022, 2,}, 1753 /* 8852B USB2.0/USB3.0 SCC turbo */ 1754 .wde_size30 = {RTW89_WDE_PG_64, 220, 36,}, 1755 /* 8852C USB2.0 */ 1756 .wde_size31 = {RTW89_WDE_PG_64, 384, 0,}, 1757 /* PCIE */ 1758 .ple_size0 = {RTW89_PLE_PG_128, 1520, 16,}, 1759 .ple_size0_v1 = {RTW89_PLE_PG_128, 2688, 240, 212992,}, 1760 /* 8852A USB */ 1761 .ple_size1 = {RTW89_PLE_PG_128, 3184, 16,}, 1762 .ple_size3_v1 = {RTW89_PLE_PG_128, 2928, 0, 212992,}, 1763 /* DLFW */ 1764 .ple_size4 = {RTW89_PLE_PG_128, 64, 1472,}, 1765 /* 8922A USB3.0 */ 1766 .ple_size4_v1 = {RTW89_PLE_PG_256, 1963, 109, 57344,}, 1767 /* PCIE 64 */ 1768 .ple_size6 = {RTW89_PLE_PG_128, 496, 16,}, 1769 /* 8922A USB2.0 */ 1770 .ple_size6_v1 = {RTW89_PLE_PG_256, 2059, 109, 32768,}, 1771 .ple_size7_v1 = {RTW89_PLE_PG_256, 2027, 109, 40960,}, 1772 /* DLFW */ 1773 .ple_size8 = {RTW89_PLE_PG_128, 64, 960,}, 1774 .ple_size9 = {RTW89_PLE_PG_128, 2288, 16,}, 1775 /* 8852C USB */ 1776 .ple_size17 = {RTW89_PLE_PG_128, 3368, 24,}, 1777 /* 8852C DLFW */ 1778 .ple_size18 = {RTW89_PLE_PG_128, 2544, 16,}, 1779 /* 8852C PCIE SCC */ 1780 .ple_size19 = {RTW89_PLE_PG_128, 1904, 16,}, 1781 .ple_size20_v1 = {RTW89_PLE_PG_128, 2554, 182, 40960,}, 1782 .ple_size22_v1 = {RTW89_PLE_PG_128, 2736, 0, 40960,}, 1783 /* 8851B USB2.0 SCC turbo */ 1784 .ple_size27 = {RTW89_PLE_PG_128, 1396, 12,}, 1785 .ple_size29_v1 = {RTW89_PLE_PG_128, 1895, 182, 49152,}, 1786 /* 8852B USB3.0 SCC turbo */ 1787 .ple_size31 = {RTW89_PLE_PG_128, 1392, 16,}, 1788 /* 8852C USB2.0 */ 1789 .ple_size34 = {RTW89_PLE_PG_128, 3374, 18,}, 1790 /* PCIE 64 */ 1791 .wde_qt0 = {3792, 196, 0, 107,}, 1792 .wde_qt0_v1 = {3302, 6, 0, 20,}, 1793 /* 8852A USB */ 1794 .wde_qt1 = {512, 196, 0, 60,}, 1795 .wde_qt3 = {0, 0, 0, 0,}, 1796 /* DLFW */ 1797 .wde_qt4 = {0, 0, 0, 0,}, 1798 /* 8922A USB3.0 */ 1799 .wde_qt4_v1 = {876, 6, 0, 10,}, 1800 .wde_qt5_v1 = {838, 6, 0, 20,}, 1801 /* PCIE 64 */ 1802 .wde_qt6 = {448, 48, 0, 16,}, 1803 /* 8852B PCIE SCC */ 1804 .wde_qt7 = {446, 48, 0, 16,}, 1805 /* 8922A USB2.0 */ 1806 .wde_qt7_v1 = {492, 6, 0, 10,}, 1807 .wde_qt8_v1 = {608, 6, 0, 20,}, 1808 /* 8852C USB3.0 */ 1809 .wde_qt16 = {344, 2, 0, 8,}, 1810 /* 8852C DLFW */ 1811 .wde_qt17 = {0, 0, 0, 0,}, 1812 /* 8852C PCIE SCC */ 1813 .wde_qt18 = {3228, 60, 0, 40,}, 1814 .wde_qt19_v1 = {613, 6, 0, 20,}, 1815 .wde_qt23 = {958, 48, 0, 16,}, 1816 .wde_qt23_v1 = {371, 3, 0, 10,}, 1817 /* 8852B USB2.0/USB3.0 SCC turbo */ 1818 .wde_qt30 = {210, 2, 0, 8,}, 1819 /* 8852C USB2.0 */ 1820 .wde_qt31 = {338, 6, 0, 40,}, 1821 .ple_qt0 = {320, 320, 32, 16, 13, 13, 292, 292, 64, 18, 1, 4, 0,}, 1822 .ple_qt1 = {320, 320, 32, 16, 1316, 1316, 1595, 1595, 1367, 1321, 1, 1307, 0,}, 1823 /* PCIE SCC */ 1824 .ple_qt4 = {264, 0, 16, 20, 26, 13, 356, 0, 32, 40, 8,}, 1825 /* PCIE SCC */ 1826 .ple_qt5 = {264, 0, 32, 20, 64, 13, 1101, 0, 64, 128, 120,}, 1827 .ple_qt5_v2 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,}, 1828 /* 8922A USB3.0 */ 1829 .ple_qt6_v1 = {1806, 0, 16, 24, 7, 14, 57, 0, 12, 9, 1, 4, 0,}, 1830 .ple_qt7_v1 = {1806, 0, 16, 24, 20, 27, 70, 0, 25, 9, 1, 17, 0,}, 1831 .ple_qt8_v1 = {1638, 0, 16, 24, 7, 14, 99, 99, 24, 9, 1, 4, 0,}, 1832 /* PCIE SCC */ 1833 .ple_qt9 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 1, 0, 0,}, 1834 /* 8922A USB3.0 */ 1835 .ple_qt9_v1 = {1638, 0, 16, 24, 35, 42, 127, 127, 52, 9, 1, 32, 0,}, 1836 /* 8922A USB2.0 */ 1837 .ple_qt12_v1 = {463, 0, 16, 24, 7, 14, 57, 0, 12, 9, 1, 4, 0,}, 1838 /* DLFW */ 1839 .ple_qt13 = {0, 0, 16, 48, 0, 0, 0, 0, 0, 0, 0,}, 1840 /* 8922A USB2.0 */ 1841 .ple_qt13_v1 = {463, 0, 16, 24, 1459, 1466, 1509, 0, 1464, 9, 1, 1456, 0,}, 1842 .ple_qt14_v1 = {939, 0, 16, 24, 7, 14, 57, 57, 24, 9, 1, 4, 0,}, 1843 .ple_qt15_v1 = {939, 0, 16, 24, 882, 889, 932, 932, 899, 9, 1, 879, 0,}, 1844 /* PCIE 64 */ 1845 .ple_qt18 = {147, 0, 16, 20, 17, 13, 89, 0, 32, 14, 8, 0,}, 1846 /* 8852A USB SCC */ 1847 .ple_qt25 = {1536, 0, 16, 48, 13, 13, 360, 0, 32, 40, 8, 0,}, 1848 .ple_qt26 = {2654, 0, 1134, 48, 64, 13, 1478, 0, 64, 128, 120, 0,}, 1849 /* 8852B USB3.0 SCC turbo */ 1850 .ple_qt27 = {1040, 0, 16, 48, 13, 13, 178, 0, 32, 14, 8, 0,}, 1851 .ple_qt28 = {1040, 0, 32, 48, 43, 13, 208, 0, 62, 14, 24, 0,}, 1852 /* USB 52C USB3.0 */ 1853 .ple_qt42 = {1068, 0, 16, 48, 4, 13, 178, 0, 16, 1, 8, 16, 0,}, 1854 /* USB 52C USB3.0 */ 1855 .ple_qt43 = {3068, 0, 32, 48, 4, 13, 178, 0, 16, 1, 8, 16, 0,}, 1856 /* DLFW 52C */ 1857 .ple_qt44 = {0, 0, 16, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 1858 .ple_qt44_v2 = {91, 91, 32, 16, 19, 13, 91, 91, 44, 18, 1, 4, 0, 0,}, 1859 /* DLFW 52C */ 1860 .ple_qt45 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 1861 .ple_qt45_v2 = {645, 645, 32, 2055, 2058, 2052, 2132, 2132, 2083, 2057, 1, 2043, 0, 0,}, 1862 /* 8852C PCIE SCC */ 1863 .ple_qt46 = {525, 0, 16, 20, 13, 13, 178, 0, 32, 62, 8, 16,}, 1864 /* 8852C PCIE SCC */ 1865 .ple_qt47 = {525, 0, 32, 20, 1034, 13, 1199, 0, 1053, 62, 160, 1037,}, 1866 .ple_qt47_v2 = {0, 0, 32, 2703, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,}, 1867 .ple_qt57 = {147, 0, 16, 20, 13, 13, 178, 0, 32, 14, 8, 0,}, 1868 /* PCIE 64 */ 1869 .ple_qt58 = {147, 0, 16, 20, 157, 13, 229, 0, 172, 14, 24, 0,}, 1870 .ple_qt59 = {147, 0, 32, 20, 1860, 13, 2025, 0, 1879, 14, 24, 0,}, 1871 /* 8851B USB2.0 SCC turbo */ 1872 .ple_qt61 = {858, 0, 16, 48, 4, 13, 370, 0, 32, 14, 8, 0, 0,}, 1873 .ple_qt62 = {858, 0, 32, 48, 37, 13, 403, 0, 65, 14, 24, 0, 0,}, 1874 .ple_qt64_v2 = {91, 91, 32, 16, 19, 13, 93, 93, 44, 34, 1, 4, 0, 0,}, 1875 .ple_qt65_v2 = {645, 645, 32, 1380, 1383, 1377, 1457, 1457, 1408, 1398, 1, 1368,}, 1876 /* USB2.0 52C */ 1877 .ple_qt78 = {1560, 0, 16, 48, 13, 13, 390, 0, 32, 38, 8, 16, 0,}, 1878 /* USB2.0 52C */ 1879 .ple_qt79 = {1560, 0, 32, 48, 1253, 13, 1630, 0, 1272, 38, 120, 1256, 0,}, 1880 /* 8852A PCIE WOW */ 1881 .ple_qt_52a_wow = {264, 0, 32, 20, 64, 13, 1005, 0, 64, 128, 120,}, 1882 /* 8852B PCIE WOW */ 1883 .ple_qt_52b_wow = {147, 0, 16, 20, 157, 13, 133, 0, 172, 14, 24, 0,}, 1884 /* 8852BT PCIE WOW */ 1885 .ple_qt_52bt_wow = {147, 0, 32, 20, 1860, 13, 1929, 0, 1879, 14, 24, 0,}, 1886 /* 8851B PCIE WOW */ 1887 .ple_qt_51b_wow = {147, 0, 16, 20, 157, 13, 133, 0, 172, 14, 24, 0,}, 1888 .ple_rsvd_qt0 = {2, 107, 107, 6, 6, 6, 6, 0, 0, 0,}, 1889 .ple_rsvd_qt1 = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,}, 1890 .ple_rsvd_qt2 = {1, 56, 28, 6, 6, 6, 6, 0, 0, 0,}, 1891 .ple_rsvd_qt9 = {1, 44, 44, 6, 6, 6, 6, 69, 0, 0,}, 1892 .rsvd0_size0 = {212992, 0,}, 1893 .rsvd0_size3 = {57344, 0,}, 1894 .rsvd0_size5 = {32768, 0,}, 1895 .rsvd0_size6 = {40960, 0,}, 1896 .rsvd0_size17 = {49152, 0,}, 1897 .rsvd1_size0 = {587776, 2048,}, 1898 .rsvd1_size2 = {391168, 2048,}, 1899 .rsvd1_size3 = {315008, 78208,}, 1900 .dle_input3 = {0, 0, 0, 16384, 0, 2048, 0, 0, 0,}, 1901 .dle_input20 = {128, 128, 11454, 2048, 0, 2048, 1024, 24, 24,}, 1902 .dle_input28 = {128, 128, 11454, 2048, 0, 2048, 2048, 24, 24,}, 1903 }; 1904 EXPORT_SYMBOL(rtw89_mac_size); 1905 1906 static const struct rtw89_dle_mem *get_dle_mem_cfg(struct rtw89_dev *rtwdev, 1907 enum rtw89_qta_mode mode) 1908 { 1909 const struct rtw89_qta_def *qta_def = rtw89_chip_get_qta_def(rtwdev); 1910 struct rtw89_mac_info *mac = &rtwdev->mac; 1911 const struct rtw89_dle_mem *cfg, *cfgs; 1912 1913 cfgs = qta_def->dle_mem[rtwdev->hci.dle_type]; 1914 if (!cfgs) 1915 return NULL; 1916 1917 cfg = &cfgs[mode]; 1918 if (cfg->mode != mode) { 1919 rtw89_warn(rtwdev, "qta mode unmatch!\n"); 1920 return NULL; 1921 } 1922 1923 mac->dle_info.rsvd_qt = cfg->rsvd_qt; 1924 mac->dle_info.dle_input = cfg->dle_input; 1925 mac->dle_info.ple_pg_size = cfg->ple_size->pge_size; 1926 mac->dle_info.ple_free_pg = cfg->ple_size->lnk_pge_num; 1927 mac->dle_info.qta_mode = mode; 1928 mac->dle_info.c0_rx_qta = cfg->ple_min_qt->cma0_dma; 1929 mac->dle_info.c1_rx_qta = cfg->ple_min_qt->cma1_dma; 1930 1931 return cfg; 1932 } 1933 1934 int rtw89_mac_get_dle_rsvd_qt_cfg(struct rtw89_dev *rtwdev, 1935 enum rtw89_mac_dle_rsvd_qt_type type, 1936 struct rtw89_mac_dle_rsvd_qt_cfg *cfg) 1937 { 1938 struct rtw89_dle_info *dle_info = &rtwdev->mac.dle_info; 1939 const struct rtw89_rsvd_quota *rsvd_qt = dle_info->rsvd_qt; 1940 1941 switch (type) { 1942 case DLE_RSVD_QT_MPDU_INFO: 1943 cfg->pktid = dle_info->ple_free_pg; 1944 cfg->pg_num = rsvd_qt->mpdu_info_tbl; 1945 break; 1946 case DLE_RSVD_QT_B0_CSI: 1947 cfg->pktid = dle_info->ple_free_pg + rsvd_qt->mpdu_info_tbl; 1948 cfg->pg_num = rsvd_qt->b0_csi; 1949 break; 1950 case DLE_RSVD_QT_B1_CSI: 1951 cfg->pktid = dle_info->ple_free_pg + 1952 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi; 1953 cfg->pg_num = rsvd_qt->b1_csi; 1954 break; 1955 case DLE_RSVD_QT_B0_LMR: 1956 cfg->pktid = dle_info->ple_free_pg + 1957 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi; 1958 cfg->pg_num = rsvd_qt->b0_lmr; 1959 break; 1960 case DLE_RSVD_QT_B1_LMR: 1961 cfg->pktid = dle_info->ple_free_pg + 1962 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi + 1963 rsvd_qt->b0_lmr; 1964 cfg->pg_num = rsvd_qt->b1_lmr; 1965 break; 1966 case DLE_RSVD_QT_B0_FTM: 1967 cfg->pktid = dle_info->ple_free_pg + 1968 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi + 1969 rsvd_qt->b0_lmr + rsvd_qt->b1_lmr; 1970 cfg->pg_num = rsvd_qt->b0_ftm; 1971 break; 1972 case DLE_RSVD_QT_B1_FTM: 1973 cfg->pktid = dle_info->ple_free_pg + 1974 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi + 1975 rsvd_qt->b0_lmr + rsvd_qt->b1_lmr + rsvd_qt->b0_ftm; 1976 cfg->pg_num = rsvd_qt->b1_ftm; 1977 break; 1978 default: 1979 return -EINVAL; 1980 } 1981 1982 cfg->size = (u32)cfg->pg_num * dle_info->ple_pg_size; 1983 1984 return 0; 1985 } 1986 1987 static bool mac_is_txq_empty_ax(struct rtw89_dev *rtwdev) 1988 { 1989 struct rtw89_mac_dle_dfi_qempty qempty; 1990 u32 grpnum, qtmp, val32, msk32; 1991 int i, j, ret; 1992 1993 grpnum = rtwdev->chip->wde_qempty_acq_grpnum; 1994 qempty.dle_type = DLE_CTRL_TYPE_WDE; 1995 1996 for (i = 0; i < grpnum; i++) { 1997 qempty.grpsel = i; 1998 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty); 1999 if (ret) { 2000 rtw89_warn(rtwdev, "dle dfi acq empty %d\n", ret); 2001 return false; 2002 } 2003 qtmp = qempty.qempty; 2004 for (j = 0 ; j < QEMP_ACQ_GRP_MACID_NUM; j++) { 2005 val32 = u32_get_bits(qtmp, QEMP_ACQ_GRP_QSEL_MASK); 2006 if (val32 != QEMP_ACQ_GRP_QSEL_MASK) 2007 return false; 2008 qtmp >>= QEMP_ACQ_GRP_QSEL_SH; 2009 } 2010 } 2011 2012 qempty.grpsel = rtwdev->chip->wde_qempty_mgq_grpsel; 2013 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty); 2014 if (ret) { 2015 rtw89_warn(rtwdev, "dle dfi mgq empty %d\n", ret); 2016 return false; 2017 } 2018 msk32 = B_CMAC0_MGQ_NORMAL | B_CMAC0_MGQ_NO_PWRSAV | B_CMAC0_CPUMGQ; 2019 if ((qempty.qempty & msk32) != msk32) 2020 return false; 2021 2022 if (rtwdev->dbcc_en) { 2023 msk32 |= B_CMAC1_MGQ_NORMAL | B_CMAC1_MGQ_NO_PWRSAV | B_CMAC1_CPUMGQ; 2024 if ((qempty.qempty & msk32) != msk32) 2025 return false; 2026 } 2027 2028 msk32 = B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 2029 B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 2030 B_AX_WDE_EMPTY_QUE_OTHERS | B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | 2031 B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 2032 B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_HIF | 2033 B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | 2034 B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 2035 B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX; 2036 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 2037 2038 return (val32 & msk32) == msk32; 2039 } 2040 2041 static inline u32 dle_used_size(const struct rtw89_dle_mem *cfg) 2042 { 2043 const struct rtw89_dle_size *wde = cfg->wde_size; 2044 const struct rtw89_dle_size *ple = cfg->ple_size; 2045 u32 used; 2046 2047 used = wde->pge_size * (wde->lnk_pge_num + wde->unlnk_pge_num) + 2048 ple->pge_size * (ple->lnk_pge_num + ple->unlnk_pge_num); 2049 2050 if (cfg->rsvd0_size && cfg->rsvd1_size) { 2051 used += cfg->rsvd0_size->size; 2052 used += cfg->rsvd1_size->size; 2053 } 2054 2055 return used; 2056 } 2057 2058 static u32 dle_expected_used_size(struct rtw89_dev *rtwdev, 2059 enum rtw89_qta_mode mode) 2060 { 2061 u32 size = rtwdev->chip->fifo_size; 2062 2063 if (mode == RTW89_QTA_SCC && rtwdev->hci.type != RTW89_HCI_TYPE_USB) 2064 size -= rtwdev->chip->dle_scc_rsvd_size; 2065 2066 return size; 2067 } 2068 2069 static void dle_func_en_ax(struct rtw89_dev *rtwdev, bool enable) 2070 { 2071 if (enable) 2072 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, 2073 B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 2074 else 2075 rtw89_write32_clr(rtwdev, R_AX_DMAC_FUNC_EN, 2076 B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 2077 } 2078 2079 static void dle_clk_en_ax(struct rtw89_dev *rtwdev, bool enable) 2080 { 2081 u32 val = B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN; 2082 2083 if (enable) { 2084 if (rtwdev->chip->chip_id == RTL8851B) 2085 val |= B_AX_AXIDMA_CLK_EN; 2086 rtw89_write32_set(rtwdev, R_AX_DMAC_CLK_EN, val); 2087 } else { 2088 rtw89_write32_clr(rtwdev, R_AX_DMAC_CLK_EN, val); 2089 } 2090 } 2091 2092 static int dle_mix_cfg_ax(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg) 2093 { 2094 const struct rtw89_dle_size *size_cfg; 2095 u32 val; 2096 u8 bound = 0; 2097 2098 val = rtw89_read32(rtwdev, R_AX_WDE_PKTBUF_CFG); 2099 size_cfg = cfg->wde_size; 2100 2101 switch (size_cfg->pge_size) { 2102 default: 2103 case RTW89_WDE_PG_64: 2104 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_64, 2105 B_AX_WDE_PAGE_SEL_MASK); 2106 break; 2107 case RTW89_WDE_PG_128: 2108 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_128, 2109 B_AX_WDE_PAGE_SEL_MASK); 2110 break; 2111 case RTW89_WDE_PG_256: 2112 rtw89_err(rtwdev, "[ERR]WDE DLE doesn't support 256 byte!\n"); 2113 return -EINVAL; 2114 } 2115 2116 val = u32_replace_bits(val, bound, B_AX_WDE_START_BOUND_MASK); 2117 val = u32_replace_bits(val, size_cfg->lnk_pge_num, 2118 B_AX_WDE_FREE_PAGE_NUM_MASK); 2119 rtw89_write32(rtwdev, R_AX_WDE_PKTBUF_CFG, val); 2120 2121 val = rtw89_read32(rtwdev, R_AX_PLE_PKTBUF_CFG); 2122 bound = (size_cfg->lnk_pge_num + size_cfg->unlnk_pge_num) 2123 * size_cfg->pge_size / DLE_BOUND_UNIT; 2124 size_cfg = cfg->ple_size; 2125 2126 switch (size_cfg->pge_size) { 2127 default: 2128 case RTW89_PLE_PG_64: 2129 rtw89_err(rtwdev, "[ERR]PLE DLE doesn't support 64 byte!\n"); 2130 return -EINVAL; 2131 case RTW89_PLE_PG_128: 2132 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_128, 2133 B_AX_PLE_PAGE_SEL_MASK); 2134 break; 2135 case RTW89_PLE_PG_256: 2136 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_256, 2137 B_AX_PLE_PAGE_SEL_MASK); 2138 break; 2139 } 2140 2141 val = u32_replace_bits(val, bound, B_AX_PLE_START_BOUND_MASK); 2142 val = u32_replace_bits(val, size_cfg->lnk_pge_num, 2143 B_AX_PLE_FREE_PAGE_NUM_MASK); 2144 rtw89_write32(rtwdev, R_AX_PLE_PKTBUF_CFG, val); 2145 2146 return 0; 2147 } 2148 2149 static int chk_dle_rdy_ax(struct rtw89_dev *rtwdev, bool wde_or_ple) 2150 { 2151 u32 reg, mask; 2152 u32 ini; 2153 2154 if (wde_or_ple) { 2155 reg = R_AX_WDE_INI_STATUS; 2156 mask = WDE_MGN_INI_RDY; 2157 } else { 2158 reg = R_AX_PLE_INI_STATUS; 2159 mask = PLE_MGN_INI_RDY; 2160 } 2161 2162 return read_poll_timeout(rtw89_read32, ini, (ini & mask) == mask, 1, 2163 2000, false, rtwdev, reg); 2164 } 2165 2166 #define INVALID_QT_WCPU U16_MAX 2167 #define SET_QUOTA_VAL(_min_x, _max_x, _module, _idx) \ 2168 do { \ 2169 val = u32_encode_bits(_min_x, B_AX_ ## _module ## _MIN_SIZE_MASK) | \ 2170 u32_encode_bits(_max_x, B_AX_ ## _module ## _MAX_SIZE_MASK); \ 2171 rtw89_write32(rtwdev, \ 2172 R_AX_ ## _module ## _QTA ## _idx ## _CFG, \ 2173 val); \ 2174 } while (0) 2175 #define SET_QUOTA(_x, _module, _idx) \ 2176 SET_QUOTA_VAL(min_cfg->_x, max_cfg->_x, _module, _idx) 2177 2178 static void wde_quota_cfg_ax(struct rtw89_dev *rtwdev, 2179 const struct rtw89_wde_quota *min_cfg, 2180 const struct rtw89_wde_quota *max_cfg, 2181 u16 ext_wde_min_qt_wcpu) 2182 { 2183 u16 min_qt_wcpu = ext_wde_min_qt_wcpu != INVALID_QT_WCPU ? 2184 ext_wde_min_qt_wcpu : min_cfg->wcpu; 2185 u32 val; 2186 2187 SET_QUOTA(hif, WDE, 0); 2188 SET_QUOTA_VAL(min_qt_wcpu, max_cfg->wcpu, WDE, 1); 2189 SET_QUOTA(pkt_in, WDE, 3); 2190 SET_QUOTA(cpu_io, WDE, 4); 2191 } 2192 2193 static void ple_quota_cfg_ax(struct rtw89_dev *rtwdev, 2194 const struct rtw89_ple_quota *min_cfg, 2195 const struct rtw89_ple_quota *max_cfg) 2196 { 2197 u32 val; 2198 2199 SET_QUOTA(cma0_tx, PLE, 0); 2200 SET_QUOTA(cma1_tx, PLE, 1); 2201 SET_QUOTA(c2h, PLE, 2); 2202 SET_QUOTA(h2c, PLE, 3); 2203 SET_QUOTA(wcpu, PLE, 4); 2204 SET_QUOTA(mpdu_proc, PLE, 5); 2205 SET_QUOTA(cma0_dma, PLE, 6); 2206 SET_QUOTA(cma1_dma, PLE, 7); 2207 SET_QUOTA(bb_rpt, PLE, 8); 2208 SET_QUOTA(wd_rel, PLE, 9); 2209 SET_QUOTA(cpu_io, PLE, 10); 2210 if (rtwdev->chip->chip_id == RTL8852C) 2211 SET_QUOTA(tx_rpt, PLE, 11); 2212 } 2213 2214 int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow) 2215 { 2216 const struct rtw89_ple_quota *min_cfg, *max_cfg; 2217 const struct rtw89_dle_mem *cfg; 2218 u32 val; 2219 2220 if (rtwdev->chip->chip_id == RTL8852C) 2221 return 0; 2222 2223 if (rtwdev->mac.qta_mode != RTW89_QTA_SCC) { 2224 rtw89_err(rtwdev, "[ERR]support SCC mode only\n"); 2225 return -EINVAL; 2226 } 2227 2228 if (wow) 2229 cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_WOW); 2230 else 2231 cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_SCC); 2232 if (!cfg) { 2233 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2234 return -EINVAL; 2235 } 2236 2237 min_cfg = cfg->ple_min_qt; 2238 max_cfg = cfg->ple_max_qt; 2239 SET_QUOTA(cma0_dma, PLE, 6); 2240 SET_QUOTA(cma1_dma, PLE, 7); 2241 2242 return 0; 2243 } 2244 #undef SET_QUOTA 2245 2246 void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool enable) 2247 { 2248 const struct rtw89_chip_info *chip = rtwdev->chip; 2249 u32 msk32 = B_AX_UC_MGNT_DEC | B_AX_BMC_MGNT_DEC; 2250 2251 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 2252 return; 2253 2254 /* 8852C enable B_AX_UC_MGNT_DEC by default */ 2255 if (chip->chip_id == RTL8852C) 2256 msk32 = B_AX_BMC_MGNT_DEC; 2257 2258 if (enable) 2259 rtw89_write32_set(rtwdev, R_AX_SEC_ENG_CTRL, msk32); 2260 else 2261 rtw89_write32_clr(rtwdev, R_AX_SEC_ENG_CTRL, msk32); 2262 } 2263 2264 static void dle_quota_cfg(struct rtw89_dev *rtwdev, 2265 const struct rtw89_dle_mem *cfg, 2266 u16 ext_wde_min_qt_wcpu) 2267 { 2268 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2269 2270 mac->wde_quota_cfg(rtwdev, cfg->wde_min_qt, cfg->wde_max_qt, ext_wde_min_qt_wcpu); 2271 mac->ple_quota_cfg(rtwdev, cfg->ple_min_qt, cfg->ple_max_qt); 2272 } 2273 2274 int rtw89_mac_dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 2275 enum rtw89_qta_mode ext_mode) 2276 { 2277 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2278 const struct rtw89_dle_mem *cfg, *ext_cfg; 2279 u16 ext_wde_min_qt_wcpu = INVALID_QT_WCPU; 2280 int ret; 2281 2282 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2283 if (ret) 2284 return ret; 2285 2286 cfg = get_dle_mem_cfg(rtwdev, mode); 2287 if (!cfg) { 2288 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2289 ret = -EINVAL; 2290 goto error; 2291 } 2292 2293 if (mode == RTW89_QTA_DLFW) { 2294 ext_cfg = get_dle_mem_cfg(rtwdev, ext_mode); 2295 if (!ext_cfg) { 2296 rtw89_err(rtwdev, "[ERR]get_dle_ext_mem_cfg %d\n", 2297 ext_mode); 2298 ret = -EINVAL; 2299 goto error; 2300 } 2301 ext_wde_min_qt_wcpu = ext_cfg->wde_min_qt->wcpu; 2302 } 2303 2304 if (dle_used_size(cfg) != dle_expected_used_size(rtwdev, mode)) { 2305 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 2306 ret = -EINVAL; 2307 goto error; 2308 } 2309 2310 mac->dle_func_en(rtwdev, false); 2311 mac->dle_clk_en(rtwdev, true); 2312 2313 ret = mac->dle_mix_cfg(rtwdev, cfg); 2314 if (ret) { 2315 rtw89_err(rtwdev, "[ERR] dle mix cfg\n"); 2316 goto error; 2317 } 2318 dle_quota_cfg(rtwdev, cfg, ext_wde_min_qt_wcpu); 2319 2320 mac->dle_func_en(rtwdev, true); 2321 2322 ret = mac->chk_dle_rdy(rtwdev, true); 2323 if (ret) { 2324 rtw89_err(rtwdev, "[ERR]WDE cfg ready\n"); 2325 return ret; 2326 } 2327 2328 ret = mac->chk_dle_rdy(rtwdev, false); 2329 if (ret) { 2330 rtw89_err(rtwdev, "[ERR]PLE cfg ready\n"); 2331 return ret; 2332 } 2333 2334 return 0; 2335 error: 2336 mac->dle_func_en(rtwdev, false); 2337 rtw89_err(rtwdev, "[ERR]trxcfg wde 0x8900 = %x\n", 2338 rtw89_read32(rtwdev, R_AX_WDE_INI_STATUS)); 2339 rtw89_err(rtwdev, "[ERR]trxcfg ple 0x8D00 = %x\n", 2340 rtw89_read32(rtwdev, R_AX_PLE_INI_STATUS)); 2341 2342 return ret; 2343 } 2344 2345 static int preload_init_set_ax(struct rtw89_dev *rtwdev, u8 mac_idx, 2346 enum rtw89_qta_mode mode) 2347 { 2348 u32 reg, max_preld_size, min_rsvd_size; 2349 2350 rtw89_io_pack(rtwdev); 2351 2352 max_preld_size = (mac_idx == RTW89_MAC_0 ? 2353 PRELD_B0_ENT_NUM : PRELD_B1_ENT_NUM) * PRELD_AMSDU_SIZE; 2354 reg = mac_idx == RTW89_MAC_0 ? 2355 R_AX_TXPKTCTL_B0_PRELD_CFG0 : R_AX_TXPKTCTL_B1_PRELD_CFG0; 2356 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_USEMAXSZ_MASK, max_preld_size); 2357 rtw89_write32_set(rtwdev, reg, B_AX_B0_PRELD_FEN); 2358 2359 min_rsvd_size = PRELD_AMSDU_SIZE; 2360 reg = mac_idx == RTW89_MAC_0 ? 2361 R_AX_TXPKTCTL_B0_PRELD_CFG1 : R_AX_TXPKTCTL_B1_PRELD_CFG1; 2362 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_TXENDWIN_MASK, PRELD_NEXT_WND); 2363 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_RSVMINSZ_MASK, min_rsvd_size); 2364 2365 rtw89_io_unpack(rtwdev); 2366 2367 return 0; 2368 } 2369 2370 static bool is_qta_poh(struct rtw89_dev *rtwdev) 2371 { 2372 return rtwdev->hci.type == RTW89_HCI_TYPE_PCIE; 2373 } 2374 2375 int rtw89_mac_preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 2376 enum rtw89_qta_mode mode) 2377 { 2378 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2379 const struct rtw89_chip_info *chip = rtwdev->chip; 2380 2381 if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev) || 2382 !is_qta_poh(rtwdev)) 2383 return 0; 2384 2385 return mac->preload_init(rtwdev, mac_idx, mode); 2386 } 2387 2388 static bool dle_is_txq_empty(struct rtw89_dev *rtwdev) 2389 { 2390 u32 msk32; 2391 u32 val32; 2392 2393 msk32 = B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC | B_AX_WDE_EMPTY_QUE_CMAC0_MBH | 2394 B_AX_WDE_EMPTY_QUE_CMAC1_MBH | B_AX_WDE_EMPTY_QUE_CMAC0_WMM0 | 2395 B_AX_WDE_EMPTY_QUE_CMAC0_WMM1 | B_AX_WDE_EMPTY_QUE_OTHERS | 2396 B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 2397 B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | 2398 B_AX_WDE_EMPTY_QTA_DMAC_HIF | B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | 2399 B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | 2400 B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | 2401 B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 2402 B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX | 2403 B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 2404 B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 2405 B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU; 2406 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 2407 2408 if ((val32 & msk32) == msk32) 2409 return true; 2410 2411 return false; 2412 } 2413 2414 static void _patch_ss2f_path(struct rtw89_dev *rtwdev) 2415 { 2416 const struct rtw89_chip_info *chip = rtwdev->chip; 2417 2418 if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) 2419 return; 2420 2421 rtw89_write32_mask(rtwdev, R_AX_SS2FINFO_PATH, B_AX_SS_DEST_QUEUE_MASK, 2422 SS2F_PATH_WLCPU); 2423 } 2424 2425 static int sta_sch_init_ax(struct rtw89_dev *rtwdev) 2426 { 2427 u32 p_val; 2428 u8 val; 2429 int ret; 2430 2431 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2432 if (ret) 2433 return ret; 2434 2435 val = rtw89_read8(rtwdev, R_AX_SS_CTRL); 2436 val |= B_AX_SS_EN; 2437 rtw89_write8(rtwdev, R_AX_SS_CTRL, val); 2438 2439 ret = read_poll_timeout(rtw89_read32, p_val, p_val & B_AX_SS_INIT_DONE_1, 2440 1, TRXCFG_WAIT_CNT, false, rtwdev, R_AX_SS_CTRL); 2441 if (ret) { 2442 rtw89_err(rtwdev, "[ERR]STA scheduler init\n"); 2443 return ret; 2444 } 2445 2446 rtw89_io_pack(rtwdev); 2447 2448 rtw89_write32_set(rtwdev, R_AX_SS_CTRL, B_AX_SS_WARM_INIT_FLG); 2449 rtw89_write32_clr(rtwdev, R_AX_SS_CTRL, B_AX_SS_NONEMPTY_SS2FINFO_EN); 2450 2451 _patch_ss2f_path(rtwdev); 2452 2453 rtw89_io_unpack(rtwdev); 2454 2455 return 0; 2456 } 2457 2458 static int mpdu_proc_init_ax(struct rtw89_dev *rtwdev) 2459 { 2460 int ret; 2461 2462 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2463 if (ret) 2464 return ret; 2465 2466 rtw89_io_pack(rtwdev); 2467 2468 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD); 2469 rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD); 2470 rtw89_write32_set(rtwdev, R_AX_MPDU_PROC, 2471 B_AX_APPEND_FCS | B_AX_A_ICV_ERR); 2472 rtw89_write32(rtwdev, R_AX_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL); 2473 2474 rtw89_io_unpack(rtwdev); 2475 2476 return 0; 2477 } 2478 2479 static int sec_eng_init_ax(struct rtw89_dev *rtwdev) 2480 { 2481 const struct rtw89_chip_info *chip = rtwdev->chip; 2482 u32 val = 0; 2483 int ret; 2484 2485 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2486 if (ret) 2487 return ret; 2488 2489 rtw89_io_pack(rtwdev); 2490 2491 val = rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL); 2492 /* init clock */ 2493 val |= (B_AX_CLK_EN_CGCMP | B_AX_CLK_EN_WAPI | B_AX_CLK_EN_WEP_TKIP); 2494 /* init TX encryption */ 2495 val |= (B_AX_SEC_TX_ENC | B_AX_SEC_RX_DEC); 2496 val |= (B_AX_MC_DEC | B_AX_BC_DEC); 2497 if (chip->chip_id == RTL8852C) 2498 val |= B_AX_UC_MGNT_DEC; 2499 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || 2500 chip->chip_id == RTL8851B || 2501 (chip->chip_id == RTL8852C && rtwdev->hci.type == RTW89_HCI_TYPE_USB)) 2502 val &= ~B_AX_TX_PARTIAL_MODE; 2503 rtw89_write32(rtwdev, R_AX_SEC_ENG_CTRL, val); 2504 2505 /* init MIC ICV append */ 2506 val = rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC); 2507 val |= (B_AX_APPEND_ICV | B_AX_APPEND_MIC); 2508 2509 /* option init */ 2510 rtw89_write32(rtwdev, R_AX_SEC_MPDU_PROC, val); 2511 2512 if (chip->chip_id == RTL8852C) 2513 rtw89_write32_mask(rtwdev, R_AX_SEC_DEBUG1, 2514 B_AX_TX_TIMEOUT_SEL_MASK, AX_TX_TO_VAL); 2515 2516 rtw89_io_unpack(rtwdev); 2517 2518 return 0; 2519 } 2520 2521 static int dmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2522 { 2523 int ret; 2524 2525 ret = rtw89_mac_dle_init(rtwdev, rtwdev->mac.qta_mode, RTW89_QTA_INVALID); 2526 if (ret) { 2527 rtw89_err(rtwdev, "[ERR]DLE init %d\n", ret); 2528 return ret; 2529 } 2530 2531 ret = rtw89_mac_preload_init(rtwdev, RTW89_MAC_0, rtwdev->mac.qta_mode); 2532 if (ret) { 2533 rtw89_err(rtwdev, "[ERR]preload init %d\n", ret); 2534 return ret; 2535 } 2536 2537 ret = rtw89_mac_hfc_init(rtwdev, true, true, true); 2538 if (ret) { 2539 rtw89_err(rtwdev, "[ERR]HCI FC init %d\n", ret); 2540 return ret; 2541 } 2542 2543 ret = sta_sch_init_ax(rtwdev); 2544 if (ret) { 2545 rtw89_err(rtwdev, "[ERR]STA SCH init %d\n", ret); 2546 return ret; 2547 } 2548 2549 ret = mpdu_proc_init_ax(rtwdev); 2550 if (ret) { 2551 rtw89_err(rtwdev, "[ERR]MPDU Proc init %d\n", ret); 2552 return ret; 2553 } 2554 2555 ret = sec_eng_init_ax(rtwdev); 2556 if (ret) { 2557 rtw89_err(rtwdev, "[ERR]Security Engine init %d\n", ret); 2558 return ret; 2559 } 2560 2561 return ret; 2562 } 2563 2564 static int addr_cam_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2565 { 2566 u32 val, reg; 2567 u16 p_val; 2568 int ret; 2569 2570 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2571 if (ret) 2572 return ret; 2573 2574 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_ADDR_CAM_CTRL, mac_idx); 2575 2576 val = rtw89_read32(rtwdev, reg); 2577 val |= u32_encode_bits(0x7f, B_AX_ADDR_CAM_RANGE_MASK) | 2578 B_AX_ADDR_CAM_CLR | B_AX_ADDR_CAM_EN; 2579 rtw89_write32(rtwdev, reg, val); 2580 2581 ret = read_poll_timeout(rtw89_read16, p_val, !(p_val & B_AX_ADDR_CAM_CLR), 2582 1, TRXCFG_WAIT_CNT, false, rtwdev, reg); 2583 if (ret) { 2584 rtw89_err(rtwdev, "[ERR]ADDR_CAM reset\n"); 2585 return ret; 2586 } 2587 2588 return 0; 2589 } 2590 2591 static int scheduler_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2592 { 2593 int ret; 2594 u32 reg; 2595 u32 val; 2596 2597 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2598 if (ret) 2599 return ret; 2600 2601 rtw89_io_pack(rtwdev); 2602 2603 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PREBKF_CFG_1, mac_idx); 2604 if (rtwdev->chip->chip_id == RTL8852C) 2605 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, 2606 SIFS_MACTXEN_T1_V1); 2607 else 2608 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, 2609 SIFS_MACTXEN_T1); 2610 2611 if (rtw89_is_rtl885xb(rtwdev)) { 2612 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SCH_EXT_CTRL, mac_idx); 2613 rtw89_write32_set(rtwdev, reg, B_AX_PORT_RST_TSF_ADV); 2614 } 2615 2616 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CCA_CFG_0, mac_idx); 2617 rtw89_write32_clr(rtwdev, reg, B_AX_BTCCA_EN); 2618 2619 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PREBKF_CFG_0, mac_idx); 2620 if (rtwdev->chip->chip_id == RTL8852C) { 2621 val = rtw89_read32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 2622 B_AX_TX_PARTIAL_MODE); 2623 if (!val) 2624 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, 2625 SCH_PREBKF_24US); 2626 } else { 2627 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, 2628 SCH_PREBKF_24US); 2629 } 2630 2631 rtw89_io_unpack(rtwdev); 2632 2633 return 0; 2634 } 2635 2636 static int rtw89_mac_typ_fltr_opt_ax(struct rtw89_dev *rtwdev, 2637 enum rtw89_machdr_frame_type type, 2638 enum rtw89_mac_fwd_target fwd_target, 2639 u8 mac_idx) 2640 { 2641 u32 reg; 2642 u32 val; 2643 2644 switch (fwd_target) { 2645 case RTW89_FWD_DONT_CARE: 2646 val = RX_FLTR_FRAME_DROP; 2647 break; 2648 case RTW89_FWD_TO_HOST: 2649 val = RX_FLTR_FRAME_TO_HOST; 2650 break; 2651 case RTW89_FWD_TO_WLAN_CPU: 2652 val = RX_FLTR_FRAME_TO_WLCPU; 2653 break; 2654 default: 2655 rtw89_err(rtwdev, "[ERR]set rx filter fwd target err\n"); 2656 return -EINVAL; 2657 } 2658 2659 switch (type) { 2660 case RTW89_MGNT: 2661 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MGNT_FLTR, mac_idx); 2662 break; 2663 case RTW89_CTRL: 2664 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTRL_FLTR, mac_idx); 2665 break; 2666 case RTW89_DATA: 2667 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_DATA_FLTR, mac_idx); 2668 break; 2669 default: 2670 rtw89_err(rtwdev, "[ERR]set rx filter type err\n"); 2671 return -EINVAL; 2672 } 2673 rtw89_write32(rtwdev, reg, val); 2674 2675 return 0; 2676 } 2677 2678 void rtw89_mac_set_rx_fltr(struct rtw89_dev *rtwdev, u8 mac_idx, u32 rx_fltr) 2679 { 2680 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2681 u32 reg; 2682 u32 val; 2683 2684 reg = rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, mac_idx); 2685 2686 val = rtw89_read32(rtwdev, reg); 2687 /* B_AX_RX_FLTR_CFG_MASK is not a consecutive bit mask */ 2688 val = (val & ~B_AX_RX_FLTR_CFG_MASK) | (rx_fltr & B_AX_RX_FLTR_CFG_MASK); 2689 rtw89_write32(rtwdev, reg, val); 2690 } 2691 2692 static int rx_fltr_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2693 { 2694 int ret, i; 2695 u32 mac_ftlr, plcp_ftlr; 2696 2697 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2698 if (ret) 2699 return ret; 2700 2701 rtw89_io_pack(rtwdev); 2702 2703 for (i = RTW89_MGNT; i <= RTW89_DATA; i++) { 2704 ret = rtw89_mac_typ_fltr_opt_ax(rtwdev, i, RTW89_FWD_TO_HOST, 2705 mac_idx); 2706 if (ret) 2707 return ret; 2708 } 2709 mac_ftlr = rtwdev->hal.rx_fltr; 2710 plcp_ftlr = B_AX_CCK_CRC_CHK | B_AX_CCK_SIG_CHK | 2711 B_AX_LSIG_PARITY_CHK_EN | B_AX_SIGA_CRC_CHK | 2712 B_AX_VHT_SU_SIGB_CRC_CHK | B_AX_VHT_MU_SIGB_CRC_CHK | 2713 B_AX_HE_SIGB_CRC_CHK; 2714 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, mac_idx), 2715 mac_ftlr); 2716 rtw89_write16(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_PLCP_HDR_FLTR, mac_idx), 2717 plcp_ftlr); 2718 2719 rtw89_io_unpack(rtwdev); 2720 2721 return 0; 2722 } 2723 2724 static void _patch_dis_resp_chk(struct rtw89_dev *rtwdev, u8 mac_idx) 2725 { 2726 u32 reg, val32; 2727 u32 b_rsp_chk_nav, b_rsp_chk_cca; 2728 2729 b_rsp_chk_nav = B_AX_RSP_CHK_TXNAV | B_AX_RSP_CHK_INTRA_NAV | 2730 B_AX_RSP_CHK_BASIC_NAV; 2731 b_rsp_chk_cca = B_AX_RSP_CHK_SEC_CCA_80 | B_AX_RSP_CHK_SEC_CCA_40 | 2732 B_AX_RSP_CHK_SEC_CCA_20 | B_AX_RSP_CHK_BTCCA | 2733 B_AX_RSP_CHK_EDCCA | B_AX_RSP_CHK_CCA; 2734 2735 switch (rtwdev->chip->chip_id) { 2736 case RTL8852A: 2737 case RTL8852B: 2738 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RSP_CHK_SIG, mac_idx); 2739 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_nav; 2740 rtw89_write32(rtwdev, reg, val32); 2741 2742 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2743 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_cca; 2744 rtw89_write32(rtwdev, reg, val32); 2745 break; 2746 default: 2747 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RSP_CHK_SIG, mac_idx); 2748 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_nav; 2749 rtw89_write32(rtwdev, reg, val32); 2750 2751 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2752 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_cca; 2753 rtw89_write32(rtwdev, reg, val32); 2754 break; 2755 } 2756 } 2757 2758 static int cca_ctrl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2759 { 2760 u32 val, reg; 2761 int ret; 2762 2763 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2764 if (ret) 2765 return ret; 2766 2767 rtw89_io_pack(rtwdev); 2768 2769 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CCA_CONTROL, mac_idx); 2770 val = rtw89_read32(rtwdev, reg); 2771 val |= (B_AX_TB_CHK_BASIC_NAV | B_AX_TB_CHK_BTCCA | 2772 B_AX_TB_CHK_EDCCA | B_AX_TB_CHK_CCA_P20 | 2773 B_AX_SIFS_CHK_BTCCA | B_AX_SIFS_CHK_CCA_P20 | 2774 B_AX_CTN_CHK_INTRA_NAV | 2775 B_AX_CTN_CHK_BASIC_NAV | B_AX_CTN_CHK_BTCCA | 2776 B_AX_CTN_CHK_EDCCA | B_AX_CTN_CHK_CCA_S80 | 2777 B_AX_CTN_CHK_CCA_S40 | B_AX_CTN_CHK_CCA_S20 | 2778 B_AX_CTN_CHK_CCA_P20); 2779 val &= ~(B_AX_TB_CHK_TX_NAV | B_AX_TB_CHK_CCA_S80 | 2780 B_AX_TB_CHK_CCA_S40 | B_AX_TB_CHK_CCA_S20 | 2781 B_AX_SIFS_CHK_CCA_S80 | B_AX_SIFS_CHK_CCA_S40 | 2782 B_AX_SIFS_CHK_CCA_S20 | B_AX_CTN_CHK_TXNAV | 2783 B_AX_SIFS_CHK_EDCCA); 2784 2785 rtw89_write32(rtwdev, reg, val); 2786 2787 _patch_dis_resp_chk(rtwdev, mac_idx); 2788 2789 rtw89_io_unpack(rtwdev); 2790 2791 return 0; 2792 } 2793 2794 static int nav_ctrl_init_ax(struct rtw89_dev *rtwdev) 2795 { 2796 rtw89_io_pack(rtwdev); 2797 2798 rtw89_write32_set(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_PLCP_UP_NAV_EN | 2799 B_AX_WMAC_TF_UP_NAV_EN | 2800 B_AX_WMAC_NAV_UPPER_EN); 2801 rtw89_write32_mask(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_NAV_UPPER_MASK, NAV_25MS); 2802 2803 rtw89_io_unpack(rtwdev); 2804 2805 return 0; 2806 } 2807 2808 static int spatial_reuse_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2809 { 2810 u32 reg; 2811 int ret; 2812 2813 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2814 if (ret) 2815 return ret; 2816 2817 rtw89_io_pack(rtwdev); 2818 2819 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_SR_CTRL, mac_idx); 2820 rtw89_write8_clr(rtwdev, reg, B_AX_SR_EN); 2821 2822 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BSSID_SRC_CTRL, mac_idx); 2823 rtw89_write8_set(rtwdev, reg, B_AX_PLCP_SRC_EN); 2824 2825 rtw89_io_unpack(rtwdev); 2826 2827 return 0; 2828 } 2829 2830 static int tmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2831 { 2832 u32 reg; 2833 int ret; 2834 2835 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2836 if (ret) 2837 return ret; 2838 2839 rtw89_io_pack(rtwdev); 2840 2841 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MAC_LOOPBACK, mac_idx); 2842 rtw89_write32_clr(rtwdev, reg, B_AX_MACLBK_EN); 2843 2844 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TCR0, mac_idx); 2845 rtw89_write32_mask(rtwdev, reg, B_AX_TCR_UDF_THSD_MASK, TCR_UDF_THSD); 2846 2847 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXD_FIFO_CTRL, mac_idx); 2848 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_HIGH_MCS_THRE_MASK, TXDFIFO_HIGH_MCS_THRE); 2849 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_LOW_MCS_THRE_MASK, TXDFIFO_LOW_MCS_THRE); 2850 2851 rtw89_io_unpack(rtwdev); 2852 2853 return 0; 2854 } 2855 2856 static int trxptcl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2857 { 2858 const struct rtw89_chip_info *chip = rtwdev->chip; 2859 const struct rtw89_rrsr_cfgs *rrsr = chip->rrsr_cfgs; 2860 u32 reg, val, sifs; 2861 int ret; 2862 2863 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2864 if (ret) 2865 return ret; 2866 2867 rtw89_io_pack(rtwdev); 2868 2869 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2870 val = rtw89_read32(rtwdev, reg); 2871 val &= ~B_AX_WMAC_SPEC_SIFS_CCK_MASK; 2872 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_CCK_MASK, WMAC_SPEC_SIFS_CCK); 2873 2874 switch (rtwdev->chip->chip_id) { 2875 case RTL8852A: 2876 sifs = WMAC_SPEC_SIFS_OFDM_52A; 2877 break; 2878 case RTL8851B: 2879 case RTL8852B: 2880 case RTL8852BT: 2881 sifs = WMAC_SPEC_SIFS_OFDM_52B; 2882 break; 2883 default: 2884 sifs = WMAC_SPEC_SIFS_OFDM_52C; 2885 break; 2886 } 2887 val &= ~B_AX_WMAC_SPEC_SIFS_OFDM_MASK; 2888 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_OFDM_MASK, sifs); 2889 rtw89_write32(rtwdev, reg, val); 2890 2891 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXTRIG_TEST_USER_2, mac_idx); 2892 rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_FCSCHK_EN); 2893 2894 reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->ref_rate.addr, mac_idx); 2895 rtw89_write32_mask(rtwdev, reg, rrsr->ref_rate.mask, rrsr->ref_rate.data); 2896 reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->rsc.addr, mac_idx); 2897 rtw89_write32_mask(rtwdev, reg, rrsr->rsc.mask, rrsr->rsc.data); 2898 2899 rtw89_io_unpack(rtwdev); 2900 2901 return 0; 2902 } 2903 2904 static void rst_bacam(struct rtw89_dev *rtwdev) 2905 { 2906 u32 val32; 2907 int ret; 2908 2909 rtw89_write32_mask(rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK, 2910 S_AX_BACAM_RST_ALL); 2911 2912 ret = read_poll_timeout_atomic(rtw89_read32_mask, val32, val32 == 0, 2913 1, 1000, false, 2914 rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK); 2915 if (ret) 2916 rtw89_warn(rtwdev, "failed to reset BA CAM\n"); 2917 } 2918 2919 static int rmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2920 { 2921 #define TRXCFG_RMAC_CCA_TO 32 2922 #define TRXCFG_RMAC_DATA_TO 15 2923 #define RX_MAX_LEN_UNIT 512 2924 #define PLD_RLS_MAX_PG 127 2925 #define RX_SPEC_MAX_LEN (11454 + RX_MAX_LEN_UNIT) 2926 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2927 int ret; 2928 u32 reg, rx_max_len, rx_qta; 2929 u16 val; 2930 2931 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2932 if (ret) 2933 return ret; 2934 2935 rtw89_io_pack(rtwdev); 2936 2937 if (mac_idx == RTW89_MAC_0) 2938 rst_bacam(rtwdev); 2939 2940 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RESPBA_CAM_CTRL, mac_idx); 2941 rtw89_write8_set(rtwdev, reg, B_AX_SSN_SEL); 2942 2943 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_DLK_PROTECT_CTL, mac_idx); 2944 val = rtw89_read16(rtwdev, reg); 2945 val = u16_replace_bits(val, TRXCFG_RMAC_DATA_TO, 2946 B_AX_RX_DLK_DATA_TIME_MASK); 2947 val = u16_replace_bits(val, TRXCFG_RMAC_CCA_TO, 2948 B_AX_RX_DLK_CCA_TIME_MASK); 2949 if (chip_id == RTL8852BT) 2950 val |= B_AX_RX_DLK_RST_EN; 2951 rtw89_write16(rtwdev, reg, val); 2952 2953 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RCR, mac_idx); 2954 rtw89_write8_mask(rtwdev, reg, B_AX_CH_EN_MASK, 0x1); 2955 2956 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, mac_idx); 2957 if (mac_idx == RTW89_MAC_0) 2958 rx_qta = rtwdev->mac.dle_info.c0_rx_qta; 2959 else 2960 rx_qta = rtwdev->mac.dle_info.c1_rx_qta; 2961 rx_qta = min_t(u32, rx_qta, PLD_RLS_MAX_PG); 2962 rx_max_len = rx_qta * rtwdev->mac.dle_info.ple_pg_size; 2963 rx_max_len = min_t(u32, rx_max_len, RX_SPEC_MAX_LEN); 2964 rx_max_len /= RX_MAX_LEN_UNIT; 2965 rtw89_write32_mask(rtwdev, reg, B_AX_RX_MPDU_MAX_LEN_MASK, rx_max_len); 2966 2967 if (chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV) { 2968 rtw89_write16_mask(rtwdev, 2969 rtw89_mac_reg_by_idx(rtwdev, R_AX_DLK_PROTECT_CTL, mac_idx), 2970 B_AX_RX_DLK_CCA_TIME_MASK, 0); 2971 rtw89_write16_set(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_RCR, mac_idx), 2972 BIT(12)); 2973 } 2974 2975 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PLCP_HDR_FLTR, mac_idx); 2976 rtw89_write8_clr(rtwdev, reg, B_AX_VHT_SU_SIGB_CRC_CHK); 2977 2978 rtw89_io_unpack(rtwdev); 2979 2980 return ret; 2981 } 2982 2983 static int cmac_com_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2984 { 2985 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2986 u32 val, reg; 2987 int ret; 2988 2989 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2990 if (ret) 2991 return ret; 2992 2993 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx); 2994 val = rtw89_read32(rtwdev, reg); 2995 val = u32_replace_bits(val, 0, B_AX_TXSC_20M_MASK); 2996 val = u32_replace_bits(val, 0, B_AX_TXSC_40M_MASK); 2997 val = u32_replace_bits(val, 0, B_AX_TXSC_80M_MASK); 2998 rtw89_write32(rtwdev, reg, val); 2999 3000 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) { 3001 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_RRSR1, mac_idx); 3002 rtw89_write32_mask(rtwdev, reg, B_AX_RRSR_RATE_EN_MASK, RRSR_OFDM_CCK_EN); 3003 } 3004 3005 return 0; 3006 } 3007 3008 bool rtw89_mac_is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) 3009 { 3010 const struct rtw89_dle_mem *cfg; 3011 3012 cfg = get_dle_mem_cfg(rtwdev, mode); 3013 if (!cfg) { 3014 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 3015 return false; 3016 } 3017 3018 return (cfg->ple_min_qt->cma1_dma && cfg->ple_max_qt->cma1_dma); 3019 } 3020 3021 static int ptcl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 3022 { 3023 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3024 u32 val, reg; 3025 int ret; 3026 3027 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3028 if (ret) 3029 return ret; 3030 3031 rtw89_io_pack(rtwdev); 3032 3033 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 3034 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SIFS_SETTING, mac_idx); 3035 val = rtw89_read32(rtwdev, reg); 3036 val = u32_replace_bits(val, S_AX_CTS2S_TH_1K, 3037 B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK); 3038 val = u32_replace_bits(val, S_AX_CTS2S_TH_SEC_256B, 3039 B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK); 3040 val |= B_AX_HW_CTS2SELF_EN; 3041 rtw89_write32(rtwdev, reg, val); 3042 3043 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_FSM_MON, mac_idx); 3044 val = rtw89_read32(rtwdev, reg); 3045 val = u32_replace_bits(val, S_AX_PTCL_TO_2MS, B_AX_PTCL_TX_ARB_TO_THR_MASK); 3046 val &= ~B_AX_PTCL_TX_ARB_TO_MODE; 3047 rtw89_write32(rtwdev, reg, val); 3048 } 3049 3050 if (mac_idx == RTW89_MAC_0) { 3051 rtw89_write8_set(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 3052 B_AX_CMAC_TX_MODE_0 | B_AX_CMAC_TX_MODE_1); 3053 rtw89_write8_clr(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 3054 B_AX_PTCL_TRIGGER_SS_EN_0 | 3055 B_AX_PTCL_TRIGGER_SS_EN_1 | 3056 B_AX_PTCL_TRIGGER_SS_EN_UL); 3057 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL, 3058 B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 3059 } else if (mac_idx == RTW89_MAC_1) { 3060 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL_C1, 3061 B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 3062 } 3063 3064 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) { 3065 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AGG_LEN_VHT_0, mac_idx); 3066 rtw89_write32_mask(rtwdev, reg, 3067 B_AX_AMPDU_MAX_LEN_VHT_MASK, 0x3FF80); 3068 } 3069 3070 rtw89_io_unpack(rtwdev); 3071 3072 return 0; 3073 } 3074 3075 static int cmac_dma_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 3076 { 3077 u32 reg; 3078 int ret; 3079 3080 if (!rtw89_is_rtl885xb(rtwdev)) 3081 return 0; 3082 3083 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3084 if (ret) 3085 return ret; 3086 3087 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXDMA_CTRL_0, mac_idx); 3088 rtw89_write8_clr(rtwdev, reg, RX_FULL_MODE); 3089 3090 return 0; 3091 } 3092 3093 static int cmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 3094 { 3095 int ret; 3096 3097 ret = scheduler_init_ax(rtwdev, mac_idx); 3098 if (ret) { 3099 rtw89_err(rtwdev, "[ERR]CMAC%d SCH init %d\n", mac_idx, ret); 3100 return ret; 3101 } 3102 3103 ret = addr_cam_init_ax(rtwdev, mac_idx); 3104 if (ret) { 3105 rtw89_err(rtwdev, "[ERR]CMAC%d ADDR_CAM reset %d\n", mac_idx, 3106 ret); 3107 return ret; 3108 } 3109 3110 ret = rx_fltr_init_ax(rtwdev, mac_idx); 3111 if (ret) { 3112 rtw89_err(rtwdev, "[ERR]CMAC%d RX filter init %d\n", mac_idx, 3113 ret); 3114 return ret; 3115 } 3116 3117 ret = cca_ctrl_init_ax(rtwdev, mac_idx); 3118 if (ret) { 3119 rtw89_err(rtwdev, "[ERR]CMAC%d CCA CTRL init %d\n", mac_idx, 3120 ret); 3121 return ret; 3122 } 3123 3124 ret = nav_ctrl_init_ax(rtwdev); 3125 if (ret) { 3126 rtw89_err(rtwdev, "[ERR]CMAC%d NAV CTRL init %d\n", mac_idx, 3127 ret); 3128 return ret; 3129 } 3130 3131 ret = spatial_reuse_init_ax(rtwdev, mac_idx); 3132 if (ret) { 3133 rtw89_err(rtwdev, "[ERR]CMAC%d Spatial Reuse init %d\n", 3134 mac_idx, ret); 3135 return ret; 3136 } 3137 3138 ret = tmac_init_ax(rtwdev, mac_idx); 3139 if (ret) { 3140 rtw89_err(rtwdev, "[ERR]CMAC%d TMAC init %d\n", mac_idx, ret); 3141 return ret; 3142 } 3143 3144 ret = trxptcl_init_ax(rtwdev, mac_idx); 3145 if (ret) { 3146 rtw89_err(rtwdev, "[ERR]CMAC%d TRXPTCL init %d\n", mac_idx, ret); 3147 return ret; 3148 } 3149 3150 ret = rmac_init_ax(rtwdev, mac_idx); 3151 if (ret) { 3152 rtw89_err(rtwdev, "[ERR]CMAC%d RMAC init %d\n", mac_idx, ret); 3153 return ret; 3154 } 3155 3156 ret = cmac_com_init_ax(rtwdev, mac_idx); 3157 if (ret) { 3158 rtw89_err(rtwdev, "[ERR]CMAC%d Com init %d\n", mac_idx, ret); 3159 return ret; 3160 } 3161 3162 ret = ptcl_init_ax(rtwdev, mac_idx); 3163 if (ret) { 3164 rtw89_err(rtwdev, "[ERR]CMAC%d PTCL init %d\n", mac_idx, ret); 3165 return ret; 3166 } 3167 3168 ret = cmac_dma_init_ax(rtwdev, mac_idx); 3169 if (ret) { 3170 rtw89_err(rtwdev, "[ERR]CMAC%d DMA init %d\n", mac_idx, ret); 3171 return ret; 3172 } 3173 3174 return ret; 3175 } 3176 3177 static int rtw89_mac_read_phycap(struct rtw89_dev *rtwdev, 3178 struct rtw89_mac_c2h_info *c2h_info, u8 part_num) 3179 { 3180 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3181 const struct rtw89_chip_info *chip = rtwdev->chip; 3182 struct rtw89_mac_h2c_info h2c_info = {}; 3183 enum rtw89_mac_c2h_type c2h_type; 3184 u8 content_len; 3185 int ret; 3186 3187 if (chip->chip_gen == RTW89_CHIP_AX) 3188 content_len = 0; 3189 else 3190 content_len = 2; 3191 3192 switch (part_num) { 3193 case 0: 3194 c2h_type = RTW89_FWCMD_C2HREG_FUNC_PHY_CAP; 3195 break; 3196 case 1: 3197 c2h_type = RTW89_FWCMD_C2HREG_FUNC_PHY_CAP_PART1; 3198 break; 3199 default: 3200 return -EINVAL; 3201 } 3202 3203 mac->cnv_efuse_state(rtwdev, false); 3204 3205 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE; 3206 h2c_info.content_len = content_len; 3207 h2c_info.u.hdr.w0 = u32_encode_bits(part_num, RTW89_H2CREG_GET_FEATURE_PART_NUM); 3208 3209 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, c2h_info); 3210 if (ret) 3211 goto out; 3212 3213 if (c2h_info->id != c2h_type) 3214 ret = -EINVAL; 3215 3216 out: 3217 mac->cnv_efuse_state(rtwdev, true); 3218 3219 return ret; 3220 } 3221 3222 static int rtw89_mac_setup_phycap_part0(struct rtw89_dev *rtwdev) 3223 { 3224 const struct rtw89_chip_info *chip = rtwdev->chip; 3225 const struct rtw89_c2hreg_phycap *phycap; 3226 struct rtw89_efuse *efuse = &rtwdev->efuse; 3227 struct rtw89_mac_c2h_info c2h_info = {}; 3228 struct rtw89_hal *hal = &rtwdev->hal; 3229 u8 protocol; 3230 u8 tx_nss; 3231 u8 rx_nss; 3232 u8 tx_ant; 3233 u8 rx_ant; 3234 int ret; 3235 3236 ret = rtw89_mac_read_phycap(rtwdev, &c2h_info, 0); 3237 if (ret) 3238 return ret; 3239 3240 phycap = &c2h_info.u.phycap; 3241 3242 tx_nss = u32_get_bits(phycap->w1, RTW89_C2HREG_PHYCAP_W1_TX_NSS); 3243 rx_nss = u32_get_bits(phycap->w0, RTW89_C2HREG_PHYCAP_W0_RX_NSS); 3244 tx_ant = u32_get_bits(phycap->w3, RTW89_C2HREG_PHYCAP_W3_ANT_TX_NUM); 3245 rx_ant = u32_get_bits(phycap->w3, RTW89_C2HREG_PHYCAP_W3_ANT_RX_NUM); 3246 3247 if (test_bit(RTW89_QUIRK_1ANT, rtwdev->quirks)) { 3248 tx_ant = 1; 3249 rx_ant = 1; 3250 } 3251 3252 hal->tx_nss = tx_nss ? min_t(u8, tx_nss, chip->tx_nss) : chip->tx_nss; 3253 hal->rx_nss = rx_nss ? min_t(u8, rx_nss, chip->rx_nss) : chip->rx_nss; 3254 3255 if (tx_ant == 1) 3256 hal->antenna_tx = RF_B; 3257 if (rx_ant == 1) 3258 hal->antenna_rx = RF_B; 3259 3260 if (tx_nss == 1 && tx_ant == 2 && rx_ant == 2) { 3261 hal->antenna_tx = RF_B; 3262 hal->tx_path_diversity = true; 3263 } 3264 3265 if (chip->rf_path_num == 1) { 3266 hal->antenna_tx = RF_A; 3267 hal->antenna_rx = RF_A; 3268 if ((efuse->rfe_type % 3) == 2) 3269 hal->ant_diversity = true; 3270 } 3271 3272 rtw89_debug(rtwdev, RTW89_DBG_FW, 3273 "phycap hal/phy/chip: tx_nss=0x%x/0x%x/0x%x rx_nss=0x%x/0x%x/0x%x\n", 3274 hal->tx_nss, tx_nss, chip->tx_nss, 3275 hal->rx_nss, rx_nss, chip->rx_nss); 3276 rtw89_debug(rtwdev, RTW89_DBG_FW, 3277 "ant num/bitmap: tx=%d/0x%x rx=%d/0x%x\n", 3278 tx_ant, hal->antenna_tx, rx_ant, hal->antenna_rx); 3279 rtw89_debug(rtwdev, RTW89_DBG_FW, "TX path diversity=%d\n", hal->tx_path_diversity); 3280 rtw89_debug(rtwdev, RTW89_DBG_FW, "Antenna diversity=%d\n", hal->ant_diversity); 3281 3282 protocol = u32_get_bits(phycap->w1, RTW89_C2HREG_PHYCAP_W1_PROT); 3283 if (protocol < RTW89_C2HREG_PHYCAP_W1_PROT_11BE) 3284 hal->no_eht = true; 3285 3286 return 0; 3287 } 3288 3289 static int rtw89_mac_setup_phycap_part1(struct rtw89_dev *rtwdev) 3290 { 3291 const struct rtw89_chip_variant *variant = rtwdev->variant; 3292 const struct rtw89_c2hreg_phycap *phycap; 3293 struct rtw89_mac_c2h_info c2h_info = {}; 3294 struct rtw89_hal *hal = &rtwdev->hal; 3295 u8 qam_raw, qam; 3296 int ret; 3297 3298 ret = rtw89_mac_read_phycap(rtwdev, &c2h_info, 1); 3299 if (ret) 3300 return ret; 3301 3302 phycap = &c2h_info.u.phycap; 3303 3304 qam_raw = u32_get_bits(phycap->w2, RTW89_C2HREG_PHYCAP_P1_W2_QAM); 3305 3306 switch (qam_raw) { 3307 case RTW89_C2HREG_PHYCAP_P1_W2_QAM_256: 3308 case RTW89_C2HREG_PHYCAP_P1_W2_QAM_1024: 3309 case RTW89_C2HREG_PHYCAP_P1_W2_QAM_4096: 3310 qam = qam_raw; 3311 break; 3312 default: 3313 qam = RTW89_C2HREG_PHYCAP_P1_W2_QAM_4096; 3314 break; 3315 } 3316 3317 if ((variant && variant->no_mcs_12_13) || 3318 qam <= RTW89_C2HREG_PHYCAP_P1_W2_QAM_1024) 3319 hal->no_mcs_12_13 = true; 3320 3321 rtw89_debug(rtwdev, RTW89_DBG_FW, "phycap qam=%d/%d no_mcs_12_13=%d\n", 3322 qam_raw, qam, hal->no_mcs_12_13); 3323 3324 return 0; 3325 } 3326 3327 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev) 3328 { 3329 const struct rtw89_chip_info *chip = rtwdev->chip; 3330 int ret; 3331 3332 ret = rtw89_mac_setup_phycap_part0(rtwdev); 3333 if (ret) 3334 return ret; 3335 3336 if (chip->chip_gen == RTW89_CHIP_AX || 3337 RTW89_CHK_FW_FEATURE(NO_PHYCAP_P1, &rtwdev->fw)) 3338 return 0; 3339 3340 return rtw89_mac_setup_phycap_part1(rtwdev); 3341 } 3342 3343 static int rtw89_hw_sch_tx_en_h2c(struct rtw89_dev *rtwdev, u8 band, 3344 u16 tx_en_u16, u16 mask_u16) 3345 { 3346 struct rtw89_mac_c2h_info c2h_info = {0}; 3347 struct rtw89_mac_h2c_info h2c_info = {0}; 3348 struct rtw89_h2creg_sch_tx_en *sch_tx_en = &h2c_info.u.sch_tx_en; 3349 int ret; 3350 3351 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN; 3352 h2c_info.content_len = sizeof(*sch_tx_en) - RTW89_H2CREG_HDR_LEN; 3353 3354 u32p_replace_bits(&sch_tx_en->w0, tx_en_u16, RTW89_H2CREG_SCH_TX_EN_W0_EN); 3355 u32p_replace_bits(&sch_tx_en->w1, mask_u16, RTW89_H2CREG_SCH_TX_EN_W1_MASK); 3356 u32p_replace_bits(&sch_tx_en->w1, band, RTW89_H2CREG_SCH_TX_EN_W1_BAND); 3357 3358 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info); 3359 if (ret) 3360 return ret; 3361 3362 if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT) 3363 return -EINVAL; 3364 3365 return 0; 3366 } 3367 3368 static int rtw89_set_hw_sch_tx_en(struct rtw89_dev *rtwdev, u8 mac_idx, 3369 u16 tx_en, u16 tx_en_mask) 3370 { 3371 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_TXEN, mac_idx); 3372 u16 val; 3373 int ret; 3374 3375 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3376 if (ret) 3377 return ret; 3378 3379 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 3380 return rtw89_hw_sch_tx_en_h2c(rtwdev, mac_idx, 3381 tx_en, tx_en_mask); 3382 3383 val = rtw89_read16(rtwdev, reg); 3384 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 3385 rtw89_write16(rtwdev, reg, val); 3386 3387 return 0; 3388 } 3389 3390 static int rtw89_set_hw_sch_tx_en_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 3391 u32 tx_en, u32 tx_en_mask) 3392 { 3393 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_DRV_TXEN, mac_idx); 3394 u32 val; 3395 int ret; 3396 3397 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3398 if (ret) 3399 return ret; 3400 3401 val = rtw89_read32(rtwdev, reg); 3402 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 3403 rtw89_write32(rtwdev, reg, val); 3404 3405 return 0; 3406 } 3407 3408 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 3409 u32 *tx_en, enum rtw89_sch_tx_sel sel) 3410 { 3411 int ret; 3412 3413 *tx_en = rtw89_read16(rtwdev, 3414 rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_TXEN, mac_idx)); 3415 3416 switch (sel) { 3417 case RTW89_SCH_TX_SEL_ALL: 3418 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 3419 B_AX_CTN_TXEN_ALL_MASK); 3420 if (ret) 3421 return ret; 3422 break; 3423 case RTW89_SCH_TX_SEL_HIQ: 3424 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 3425 0, B_AX_CTN_TXEN_HGQ); 3426 if (ret) 3427 return ret; 3428 break; 3429 case RTW89_SCH_TX_SEL_MG0: 3430 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 3431 0, B_AX_CTN_TXEN_MGQ); 3432 if (ret) 3433 return ret; 3434 break; 3435 case RTW89_SCH_TX_SEL_MACID: 3436 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 3437 B_AX_CTN_TXEN_ALL_MASK); 3438 if (ret) 3439 return ret; 3440 break; 3441 default: 3442 return 0; 3443 } 3444 3445 return 0; 3446 } 3447 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx); 3448 3449 int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 3450 u32 *tx_en, enum rtw89_sch_tx_sel sel) 3451 { 3452 int ret; 3453 3454 *tx_en = rtw89_read32(rtwdev, 3455 rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_DRV_TXEN, mac_idx)); 3456 3457 switch (sel) { 3458 case RTW89_SCH_TX_SEL_ALL: 3459 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 3460 B_AX_CTN_TXEN_ALL_MASK_V1); 3461 if (ret) 3462 return ret; 3463 break; 3464 case RTW89_SCH_TX_SEL_HIQ: 3465 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 3466 0, B_AX_CTN_TXEN_HGQ); 3467 if (ret) 3468 return ret; 3469 break; 3470 case RTW89_SCH_TX_SEL_MG0: 3471 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 3472 0, B_AX_CTN_TXEN_MGQ); 3473 if (ret) 3474 return ret; 3475 break; 3476 case RTW89_SCH_TX_SEL_MACID: 3477 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 3478 B_AX_CTN_TXEN_ALL_MASK_V1); 3479 if (ret) 3480 return ret; 3481 break; 3482 default: 3483 return 0; 3484 } 3485 3486 return 0; 3487 } 3488 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx_v1); 3489 3490 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 3491 { 3492 int ret; 3493 3494 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, tx_en, B_AX_CTN_TXEN_ALL_MASK); 3495 if (ret) 3496 return ret; 3497 3498 return 0; 3499 } 3500 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx); 3501 3502 int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 3503 { 3504 int ret; 3505 3506 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, tx_en, 3507 B_AX_CTN_TXEN_ALL_MASK_V1); 3508 if (ret) 3509 return ret; 3510 3511 return 0; 3512 } 3513 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx_v1); 3514 3515 static int dle_buf_req_ax(struct rtw89_dev *rtwdev, u16 buf_len, bool wd, u16 *pkt_id) 3516 { 3517 u32 val, reg; 3518 int ret; 3519 3520 reg = wd ? R_AX_WD_BUF_REQ : R_AX_PL_BUF_REQ; 3521 val = buf_len; 3522 val |= B_AX_WD_BUF_REQ_EXEC; 3523 rtw89_write32(rtwdev, reg, val); 3524 3525 reg = wd ? R_AX_WD_BUF_STATUS : R_AX_PL_BUF_STATUS; 3526 3527 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_BUF_STAT_DONE, 3528 1, 2000, false, rtwdev, reg); 3529 if (ret) 3530 return ret; 3531 3532 *pkt_id = FIELD_GET(B_AX_WD_BUF_STAT_PKTID_MASK, val); 3533 if (*pkt_id == S_WD_BUF_STAT_PKTID_INVALID) 3534 return -ENOENT; 3535 3536 return 0; 3537 } 3538 3539 static int set_cpuio_ax(struct rtw89_dev *rtwdev, 3540 struct rtw89_cpuio_ctrl *ctrl_para, bool wd) 3541 { 3542 u32 val, cmd_type, reg; 3543 int ret; 3544 3545 cmd_type = ctrl_para->cmd_type; 3546 3547 reg = wd ? R_AX_WD_CPUQ_OP_2 : R_AX_PL_CPUQ_OP_2; 3548 val = 0; 3549 val = u32_replace_bits(val, ctrl_para->start_pktid, 3550 B_AX_WD_CPUQ_OP_STRT_PKTID_MASK); 3551 val = u32_replace_bits(val, ctrl_para->end_pktid, 3552 B_AX_WD_CPUQ_OP_END_PKTID_MASK); 3553 rtw89_write32(rtwdev, reg, val); 3554 3555 reg = wd ? R_AX_WD_CPUQ_OP_1 : R_AX_PL_CPUQ_OP_1; 3556 val = 0; 3557 val = u32_replace_bits(val, ctrl_para->src_pid, 3558 B_AX_CPUQ_OP_SRC_PID_MASK); 3559 val = u32_replace_bits(val, ctrl_para->src_qid, 3560 B_AX_CPUQ_OP_SRC_QID_MASK); 3561 val = u32_replace_bits(val, ctrl_para->dst_pid, 3562 B_AX_CPUQ_OP_DST_PID_MASK); 3563 val = u32_replace_bits(val, ctrl_para->dst_qid, 3564 B_AX_CPUQ_OP_DST_QID_MASK); 3565 rtw89_write32(rtwdev, reg, val); 3566 3567 reg = wd ? R_AX_WD_CPUQ_OP_0 : R_AX_PL_CPUQ_OP_0; 3568 val = 0; 3569 val = u32_replace_bits(val, cmd_type, 3570 B_AX_CPUQ_OP_CMD_TYPE_MASK); 3571 val = u32_replace_bits(val, ctrl_para->macid, 3572 B_AX_CPUQ_OP_MACID_MASK); 3573 val = u32_replace_bits(val, ctrl_para->pkt_num, 3574 B_AX_CPUQ_OP_PKTNUM_MASK); 3575 val |= B_AX_WD_CPUQ_OP_EXEC; 3576 rtw89_write32(rtwdev, reg, val); 3577 3578 reg = wd ? R_AX_WD_CPUQ_OP_STATUS : R_AX_PL_CPUQ_OP_STATUS; 3579 3580 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_CPUQ_OP_STAT_DONE, 3581 1, 2000, false, rtwdev, reg); 3582 if (ret) 3583 return ret; 3584 3585 if (cmd_type == CPUIO_OP_CMD_GET_1ST_PID || 3586 cmd_type == CPUIO_OP_CMD_GET_NEXT_PID) 3587 ctrl_para->pktid = FIELD_GET(B_AX_WD_CPUQ_OP_PKTID_MASK, val); 3588 3589 return 0; 3590 } 3591 3592 int rtw89_mac_dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 3593 bool band1_en) 3594 { 3595 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3596 const struct rtw89_dle_mem *cfg; 3597 3598 cfg = get_dle_mem_cfg(rtwdev, mode); 3599 if (!cfg) { 3600 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 3601 return -EINVAL; 3602 } 3603 3604 if (dle_used_size(cfg) != dle_expected_used_size(rtwdev, mode)) { 3605 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 3606 return -EINVAL; 3607 } 3608 3609 dle_quota_cfg(rtwdev, cfg, INVALID_QT_WCPU); 3610 3611 return mac->dle_quota_change(rtwdev, band1_en); 3612 } 3613 3614 static int dle_quota_change_ax(struct rtw89_dev *rtwdev, bool band1_en) 3615 { 3616 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3617 struct rtw89_cpuio_ctrl ctrl_para = {0}; 3618 u16 pkt_id; 3619 int ret; 3620 3621 ret = mac->dle_buf_req(rtwdev, 0x20, true, &pkt_id); 3622 if (ret) { 3623 rtw89_err(rtwdev, "[ERR]WDE DLE buf req\n"); 3624 return ret; 3625 } 3626 3627 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 3628 ctrl_para.start_pktid = pkt_id; 3629 ctrl_para.end_pktid = pkt_id; 3630 ctrl_para.pkt_num = 0; 3631 ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS; 3632 ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT; 3633 ret = mac->set_cpuio(rtwdev, &ctrl_para, true); 3634 if (ret) { 3635 rtw89_err(rtwdev, "[ERR]WDE DLE enqueue to head\n"); 3636 return -EFAULT; 3637 } 3638 3639 ret = mac->dle_buf_req(rtwdev, 0x20, false, &pkt_id); 3640 if (ret) { 3641 rtw89_err(rtwdev, "[ERR]PLE DLE buf req\n"); 3642 return ret; 3643 } 3644 3645 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 3646 ctrl_para.start_pktid = pkt_id; 3647 ctrl_para.end_pktid = pkt_id; 3648 ctrl_para.pkt_num = 0; 3649 ctrl_para.dst_pid = PLE_DLE_PORT_ID_PLRLS; 3650 ctrl_para.dst_qid = PLE_DLE_QUEID_NO_REPORT; 3651 ret = mac->set_cpuio(rtwdev, &ctrl_para, false); 3652 if (ret) { 3653 rtw89_err(rtwdev, "[ERR]PLE DLE enqueue to head\n"); 3654 return -EFAULT; 3655 } 3656 3657 return 0; 3658 } 3659 3660 static int band_idle_ck_b(struct rtw89_dev *rtwdev, u8 mac_idx) 3661 { 3662 int ret; 3663 u32 reg; 3664 u8 val; 3665 3666 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3667 if (ret) 3668 return ret; 3669 3670 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_TX_CTN_SEL, mac_idx); 3671 3672 ret = read_poll_timeout(rtw89_read8, val, 3673 (val & B_AX_PTCL_TX_ON_STAT) == 0, 3674 SW_CVR_DUR_US, 3675 SW_CVR_DUR_US * PTCL_IDLE_POLL_CNT, 3676 false, rtwdev, reg); 3677 if (ret) 3678 return ret; 3679 3680 return 0; 3681 } 3682 3683 static int band1_enable_ax(struct rtw89_dev *rtwdev) 3684 { 3685 int ret, i; 3686 u32 sleep_bak[4] = {0}; 3687 u32 pause_bak[4] = {0}; 3688 u32 tx_en; 3689 3690 ret = rtw89_chip_stop_sch_tx(rtwdev, 0, &tx_en, RTW89_SCH_TX_SEL_ALL); 3691 if (ret) { 3692 rtw89_err(rtwdev, "[ERR]stop sch tx %d\n", ret); 3693 return ret; 3694 } 3695 3696 for (i = 0; i < 4; i++) { 3697 sleep_bak[i] = rtw89_read32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4); 3698 pause_bak[i] = rtw89_read32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4); 3699 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, U32_MAX); 3700 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, U32_MAX); 3701 } 3702 3703 ret = band_idle_ck_b(rtwdev, 0); 3704 if (ret) { 3705 rtw89_err(rtwdev, "[ERR]tx idle poll %d\n", ret); 3706 return ret; 3707 } 3708 3709 ret = rtw89_mac_dle_quota_change(rtwdev, rtwdev->mac.qta_mode, true); 3710 if (ret) { 3711 rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret); 3712 return ret; 3713 } 3714 3715 for (i = 0; i < 4; i++) { 3716 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, sleep_bak[i]); 3717 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, pause_bak[i]); 3718 } 3719 3720 ret = rtw89_chip_resume_sch_tx(rtwdev, 0, tx_en); 3721 if (ret) { 3722 rtw89_err(rtwdev, "[ERR]CMAC1 resume sch tx %d\n", ret); 3723 return ret; 3724 } 3725 3726 ret = cmac_func_en_ax(rtwdev, 1, true); 3727 if (ret) { 3728 rtw89_err(rtwdev, "[ERR]CMAC1 func en %d\n", ret); 3729 return ret; 3730 } 3731 3732 ret = cmac_init_ax(rtwdev, 1); 3733 if (ret) { 3734 rtw89_err(rtwdev, "[ERR]CMAC1 init %d\n", ret); 3735 return ret; 3736 } 3737 3738 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 3739 B_AX_R_SYM_FEN_WLBBFUN_1 | B_AX_R_SYM_FEN_WLBBGLB_1); 3740 3741 return 0; 3742 } 3743 3744 static void rtw89_wdrls_imr_enable(struct rtw89_dev *rtwdev) 3745 { 3746 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3747 3748 rtw89_write32_clr(rtwdev, R_AX_WDRLS_ERR_IMR, B_AX_WDRLS_IMR_EN_CLR); 3749 rtw89_write32_set(rtwdev, R_AX_WDRLS_ERR_IMR, imr->wdrls_imr_set); 3750 } 3751 3752 static void rtw89_wsec_imr_enable(struct rtw89_dev *rtwdev) 3753 { 3754 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3755 3756 rtw89_write32_set(rtwdev, imr->wsec_imr_reg, imr->wsec_imr_set); 3757 } 3758 3759 static void rtw89_mpdu_trx_imr_enable(struct rtw89_dev *rtwdev) 3760 { 3761 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3762 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3763 3764 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3765 B_AX_TX_GET_ERRPKTID_INT_EN | 3766 B_AX_TX_NXT_ERRPKTID_INT_EN | 3767 B_AX_TX_MPDU_SIZE_ZERO_INT_EN | 3768 B_AX_TX_OFFSET_ERR_INT_EN | 3769 B_AX_TX_HDR3_SIZE_ERR_INT_EN); 3770 if (chip_id == RTL8852C) 3771 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3772 B_AX_TX_ETH_TYPE_ERR_EN | 3773 B_AX_TX_LLC_PRE_ERR_EN | 3774 B_AX_TX_NW_TYPE_ERR_EN | 3775 B_AX_TX_KSRCH_ERR_EN); 3776 rtw89_write32_set(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3777 imr->mpdu_tx_imr_set); 3778 3779 rtw89_write32_clr(rtwdev, R_AX_MPDU_RX_ERR_IMR, 3780 B_AX_GETPKTID_ERR_INT_EN | 3781 B_AX_MHDRLEN_ERR_INT_EN | 3782 B_AX_RPT_ERR_INT_EN); 3783 rtw89_write32_set(rtwdev, R_AX_MPDU_RX_ERR_IMR, 3784 imr->mpdu_rx_imr_set); 3785 } 3786 3787 static void rtw89_sta_sch_imr_enable(struct rtw89_dev *rtwdev) 3788 { 3789 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3790 3791 rtw89_write32_clr(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 3792 B_AX_SEARCH_HANG_TIMEOUT_INT_EN | 3793 B_AX_RPT_HANG_TIMEOUT_INT_EN | 3794 B_AX_PLE_B_PKTID_ERR_INT_EN); 3795 rtw89_write32_set(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 3796 imr->sta_sch_imr_set); 3797 } 3798 3799 static void rtw89_txpktctl_imr_enable(struct rtw89_dev *rtwdev) 3800 { 3801 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3802 3803 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b0_reg, 3804 imr->txpktctl_imr_b0_clr); 3805 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b0_reg, 3806 imr->txpktctl_imr_b0_set); 3807 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b1_reg, 3808 imr->txpktctl_imr_b1_clr); 3809 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b1_reg, 3810 imr->txpktctl_imr_b1_set); 3811 } 3812 3813 static void rtw89_wde_imr_enable(struct rtw89_dev *rtwdev) 3814 { 3815 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3816 3817 rtw89_write32_clr(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_clr); 3818 rtw89_write32_set(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_set); 3819 } 3820 3821 static void rtw89_ple_imr_enable(struct rtw89_dev *rtwdev) 3822 { 3823 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3824 3825 rtw89_write32_clr(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_clr); 3826 rtw89_write32_set(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_set); 3827 } 3828 3829 static void rtw89_pktin_imr_enable(struct rtw89_dev *rtwdev) 3830 { 3831 rtw89_write32_set(rtwdev, R_AX_PKTIN_ERR_IMR, 3832 B_AX_PKTIN_GETPKTID_ERR_INT_EN); 3833 } 3834 3835 static void rtw89_dispatcher_imr_enable(struct rtw89_dev *rtwdev) 3836 { 3837 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3838 3839 rtw89_write32_clr(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 3840 imr->host_disp_imr_clr); 3841 rtw89_write32_set(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 3842 imr->host_disp_imr_set); 3843 rtw89_write32_clr(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 3844 imr->cpu_disp_imr_clr); 3845 rtw89_write32_set(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 3846 imr->cpu_disp_imr_set); 3847 rtw89_write32_clr(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 3848 imr->other_disp_imr_clr); 3849 rtw89_write32_set(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 3850 imr->other_disp_imr_set); 3851 } 3852 3853 static void rtw89_cpuio_imr_enable(struct rtw89_dev *rtwdev) 3854 { 3855 rtw89_write32_clr(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_CLR); 3856 rtw89_write32_set(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_SET); 3857 } 3858 3859 static void rtw89_bbrpt_imr_enable(struct rtw89_dev *rtwdev) 3860 { 3861 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3862 3863 rtw89_write32_set(rtwdev, imr->bbrpt_com_err_imr_reg, 3864 B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN); 3865 rtw89_write32_clr(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 3866 B_AX_BBRPT_CHINFO_IMR_CLR); 3867 rtw89_write32_set(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 3868 imr->bbrpt_err_imr_set); 3869 rtw89_write32_set(rtwdev, imr->bbrpt_dfs_err_imr_reg, 3870 B_AX_BBRPT_DFS_TO_ERR_INT_EN); 3871 rtw89_write32_set(rtwdev, R_AX_LA_ERRFLAG, B_AX_LA_IMR_DATA_LOSS_ERR); 3872 } 3873 3874 static void rtw89_scheduler_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3875 { 3876 u32 reg; 3877 3878 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SCHEDULE_ERR_IMR, mac_idx); 3879 rtw89_write32_clr(rtwdev, reg, B_AX_SORT_NON_IDLE_ERR_INT_EN | 3880 B_AX_FSM_TIMEOUT_ERR_INT_EN); 3881 rtw89_write32_set(rtwdev, reg, B_AX_FSM_TIMEOUT_ERR_INT_EN); 3882 } 3883 3884 static void rtw89_ptcl_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3885 { 3886 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3887 u32 reg; 3888 3889 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_IMR0, mac_idx); 3890 rtw89_write32_clr(rtwdev, reg, imr->ptcl_imr_clr); 3891 rtw89_write32_set(rtwdev, reg, imr->ptcl_imr_set); 3892 } 3893 3894 static void rtw89_cdma_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3895 { 3896 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3897 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3898 u32 reg; 3899 3900 reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_0_reg, mac_idx); 3901 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_0_clr); 3902 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_0_set); 3903 3904 if (chip_id == RTL8852C) { 3905 reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_1_reg, mac_idx); 3906 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_1_clr); 3907 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_1_set); 3908 } 3909 } 3910 3911 static void rtw89_phy_intf_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3912 { 3913 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3914 u32 reg; 3915 3916 reg = rtw89_mac_reg_by_idx(rtwdev, imr->phy_intf_imr_reg, mac_idx); 3917 rtw89_write32_clr(rtwdev, reg, imr->phy_intf_imr_clr); 3918 rtw89_write32_set(rtwdev, reg, imr->phy_intf_imr_set); 3919 } 3920 3921 static void rtw89_rmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3922 { 3923 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3924 u32 reg; 3925 3926 reg = rtw89_mac_reg_by_idx(rtwdev, imr->rmac_imr_reg, mac_idx); 3927 rtw89_write32_clr(rtwdev, reg, imr->rmac_imr_clr); 3928 rtw89_write32_set(rtwdev, reg, imr->rmac_imr_set); 3929 } 3930 3931 static void rtw89_tmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3932 { 3933 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3934 u32 reg; 3935 3936 reg = rtw89_mac_reg_by_idx(rtwdev, imr->tmac_imr_reg, mac_idx); 3937 rtw89_write32_clr(rtwdev, reg, imr->tmac_imr_clr); 3938 rtw89_write32_set(rtwdev, reg, imr->tmac_imr_set); 3939 } 3940 3941 static int enable_imr_ax(struct rtw89_dev *rtwdev, u8 mac_idx, 3942 enum rtw89_mac_hwmod_sel sel) 3943 { 3944 int ret; 3945 3946 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, sel); 3947 if (ret) { 3948 rtw89_err(rtwdev, "MAC%d mac_idx%d is not ready\n", 3949 sel, mac_idx); 3950 return ret; 3951 } 3952 3953 if (sel == RTW89_DMAC_SEL) { 3954 rtw89_wdrls_imr_enable(rtwdev); 3955 rtw89_wsec_imr_enable(rtwdev); 3956 rtw89_mpdu_trx_imr_enable(rtwdev); 3957 rtw89_sta_sch_imr_enable(rtwdev); 3958 rtw89_txpktctl_imr_enable(rtwdev); 3959 rtw89_wde_imr_enable(rtwdev); 3960 rtw89_ple_imr_enable(rtwdev); 3961 rtw89_pktin_imr_enable(rtwdev); 3962 rtw89_dispatcher_imr_enable(rtwdev); 3963 rtw89_cpuio_imr_enable(rtwdev); 3964 rtw89_bbrpt_imr_enable(rtwdev); 3965 } else if (sel == RTW89_CMAC_SEL) { 3966 rtw89_scheduler_imr_enable(rtwdev, mac_idx); 3967 rtw89_ptcl_imr_enable(rtwdev, mac_idx); 3968 rtw89_cdma_imr_enable(rtwdev, mac_idx); 3969 rtw89_phy_intf_imr_enable(rtwdev, mac_idx); 3970 rtw89_rmac_imr_enable(rtwdev, mac_idx); 3971 rtw89_tmac_imr_enable(rtwdev, mac_idx); 3972 } else { 3973 return -EINVAL; 3974 } 3975 3976 return 0; 3977 } 3978 3979 static void err_imr_ctrl_ax(struct rtw89_dev *rtwdev, bool en) 3980 { 3981 rtw89_write32(rtwdev, R_AX_DMAC_ERR_IMR, 3982 en ? DMAC_ERR_IMR_EN : DMAC_ERR_IMR_DIS); 3983 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR, 3984 en ? CMAC0_ERR_IMR_EN : CMAC0_ERR_IMR_DIS); 3985 if (!rtw89_is_rtl885xb(rtwdev) && rtwdev->mac.dle_info.c1_rx_qta) 3986 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR_C1, 3987 en ? CMAC1_ERR_IMR_EN : CMAC1_ERR_IMR_DIS); 3988 } 3989 3990 static int dbcc_enable_ax(struct rtw89_dev *rtwdev, bool enable) 3991 { 3992 int ret = 0; 3993 3994 if (enable) { 3995 ret = band1_enable_ax(rtwdev); 3996 if (ret) { 3997 rtw89_err(rtwdev, "[ERR] band1_enable %d\n", ret); 3998 return ret; 3999 } 4000 4001 ret = enable_imr_ax(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL); 4002 if (ret) { 4003 rtw89_err(rtwdev, "[ERR] enable CMAC1 IMR %d\n", ret); 4004 return ret; 4005 } 4006 } else { 4007 rtw89_err(rtwdev, "[ERR] disable dbcc is not implemented not\n"); 4008 return -EINVAL; 4009 } 4010 4011 return 0; 4012 } 4013 4014 static int set_host_rpr_ax(struct rtw89_dev *rtwdev) 4015 { 4016 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 4017 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 4018 B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_POH); 4019 rtw89_write32_set(rtwdev, R_AX_RLSRPT0_CFG0, 4020 B_AX_RLSRPT0_FLTR_MAP_MASK); 4021 } else { 4022 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 4023 B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_STF); 4024 rtw89_write32_clr(rtwdev, R_AX_RLSRPT0_CFG0, 4025 B_AX_RLSRPT0_FLTR_MAP_MASK); 4026 } 4027 4028 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_AGGNUM_MASK, 30); 4029 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_TO_MASK, 255); 4030 4031 return 0; 4032 } 4033 4034 static int trx_init_ax(struct rtw89_dev *rtwdev) 4035 { 4036 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 4037 enum rtw89_qta_mode qta_mode = rtwdev->mac.qta_mode; 4038 int ret; 4039 4040 ret = dmac_init_ax(rtwdev, 0); 4041 if (ret) { 4042 rtw89_err(rtwdev, "[ERR]DMAC init %d\n", ret); 4043 return ret; 4044 } 4045 4046 ret = cmac_init_ax(rtwdev, 0); 4047 if (ret) { 4048 rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", 0, ret); 4049 return ret; 4050 } 4051 4052 if (rtw89_mac_is_qta_dbcc(rtwdev, qta_mode)) { 4053 ret = dbcc_enable_ax(rtwdev, true); 4054 if (ret) { 4055 rtw89_err(rtwdev, "[ERR]dbcc_enable init %d\n", ret); 4056 return ret; 4057 } 4058 } 4059 4060 ret = enable_imr_ax(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 4061 if (ret) { 4062 rtw89_err(rtwdev, "[ERR] enable DMAC IMR %d\n", ret); 4063 return ret; 4064 } 4065 4066 ret = enable_imr_ax(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 4067 if (ret) { 4068 rtw89_err(rtwdev, "[ERR] to enable CMAC0 IMR %d\n", ret); 4069 return ret; 4070 } 4071 4072 err_imr_ctrl_ax(rtwdev, true); 4073 4074 ret = set_host_rpr_ax(rtwdev); 4075 if (ret) { 4076 rtw89_err(rtwdev, "[ERR] set host rpr %d\n", ret); 4077 return ret; 4078 } 4079 4080 if (chip_id == RTL8852C) 4081 rtw89_write32_clr(rtwdev, R_AX_RSP_CHK_SIG, 4082 B_AX_RSP_STATIC_RTS_CHK_SERV_BW_EN); 4083 4084 return 0; 4085 } 4086 4087 static int rtw89_mac_feat_init(struct rtw89_dev *rtwdev) 4088 { 4089 #define BACAM_1024BMP_OCC_ENTRY 4 4090 #define BACAM_MAX_RU_SUPPORT_B0_STA 1 4091 #define BACAM_MAX_RU_SUPPORT_B1_STA 1 4092 const struct rtw89_chip_info *chip = rtwdev->chip; 4093 u8 users, offset; 4094 4095 if (!(chip->bacam_ver == RTW89_BACAM_V1 || 4096 chip->bacam_ver == RTW89_BACAM_G7)) 4097 return 0; 4098 4099 offset = 0; 4100 users = BACAM_MAX_RU_SUPPORT_B0_STA; 4101 rtw89_fw_h2c_init_ba_cam_users(rtwdev, users, offset, RTW89_MAC_0); 4102 4103 offset += users * BACAM_1024BMP_OCC_ENTRY; 4104 users = BACAM_MAX_RU_SUPPORT_B1_STA; 4105 rtw89_fw_h2c_init_ba_cam_users(rtwdev, users, offset, RTW89_MAC_1); 4106 4107 return 0; 4108 } 4109 4110 static int rtw89_mac_reset_pwr_state_ax(struct rtw89_dev *rtwdev) 4111 { 4112 u8 val; 4113 4114 val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, B_AX_WLMAC_PWR_STE_MASK); 4115 if (val == MAC_AX_MAC_ON) { 4116 /* 4117 * A USB adapter might play as USB mass storage with driver and 4118 * then switch to WiFi adapter, causing it stays on power-on 4119 * state when doing WiFi USB probe. Return EAGAIN to caller to 4120 * power-off and power-on again to reset the state. 4121 */ 4122 if (rtwdev->hci.type == RTW89_HCI_TYPE_USB && 4123 !test_bit(RTW89_FLAG_PROBE_DONE, rtwdev->flags)) 4124 return -EAGAIN; 4125 4126 rtw89_err(rtwdev, "MAC has already powered on\n"); 4127 return -EBUSY; 4128 } 4129 4130 return 0; 4131 } 4132 4133 static void rtw89_disable_fw_watchdog(struct rtw89_dev *rtwdev) 4134 { 4135 u32 val32; 4136 4137 if (rtw89_is_rtl885xb(rtwdev)) { 4138 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN); 4139 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN); 4140 return; 4141 } 4142 4143 rtw89_mac_mem_write(rtwdev, R_AX_WDT_CTRL, 4144 WDT_CTRL_ALL_DIS, RTW89_MAC_MEM_CPU_LOCAL); 4145 4146 val32 = rtw89_mac_mem_read(rtwdev, R_AX_WDT_STATUS, RTW89_MAC_MEM_CPU_LOCAL); 4147 val32 |= B_AX_FS_WDT_INT; 4148 val32 &= ~B_AX_FS_WDT_INT_MSK; 4149 rtw89_mac_mem_write(rtwdev, R_AX_WDT_STATUS, val32, RTW89_MAC_MEM_CPU_LOCAL); 4150 } 4151 4152 static void rtw89_mac_disable_cpu_ax(struct rtw89_dev *rtwdev) 4153 { 4154 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 4155 4156 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 4157 rtw89_write32_clr(rtwdev, R_AX_WCPU_FW_CTRL, B_AX_WCPU_FWDL_EN | 4158 B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 4159 rtw89_write32_clr(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 4160 4161 rtw89_disable_fw_watchdog(rtwdev); 4162 4163 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 4164 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 4165 } 4166 4167 static int rtw89_mac_enable_cpu_ax(struct rtw89_dev *rtwdev, u8 boot_reason, 4168 bool dlfw, bool include_bb) 4169 { 4170 u32 val; 4171 int ret; 4172 4173 if (rtw89_read32(rtwdev, R_AX_PLATFORM_ENABLE) & B_AX_WCPU_EN) 4174 return -EFAULT; 4175 4176 rtw89_write32(rtwdev, R_AX_UDM1, 0); 4177 rtw89_write32(rtwdev, R_AX_UDM2, 0); 4178 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, 0); 4179 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 4180 rtw89_write32(rtwdev, R_AX_HALT_H2C, 0); 4181 rtw89_write32(rtwdev, R_AX_HALT_C2H, 0); 4182 4183 rtw89_write32_set(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 4184 4185 val = rtw89_read32(rtwdev, R_AX_WCPU_FW_CTRL); 4186 val &= ~(B_AX_WCPU_FWDL_EN | B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 4187 val = u32_replace_bits(val, RTW89_FWDL_INITIAL_STATE, 4188 B_AX_WCPU_FWDL_STS_MASK); 4189 4190 if (dlfw) 4191 val |= B_AX_WCPU_FWDL_EN; 4192 4193 rtw89_write32(rtwdev, R_AX_WCPU_FW_CTRL, val); 4194 4195 if (rtw89_is_rtl885xb(rtwdev)) 4196 rtw89_write32_mask(rtwdev, R_AX_SEC_CTRL, 4197 B_AX_SEC_IDMEM_SIZE_CONFIG_MASK, 0x2); 4198 4199 rtw89_write16_mask(rtwdev, R_AX_BOOT_REASON, B_AX_BOOT_REASON_MASK, 4200 boot_reason); 4201 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 4202 4203 if (!dlfw) { 4204 mdelay(5); 4205 4206 ret = rtw89_fw_check_rdy(rtwdev, RTW89_FWDL_CHECK_FREERTOS_DONE); 4207 if (ret) 4208 return ret; 4209 } 4210 4211 return 0; 4212 } 4213 4214 static void rtw89_mac_hci_func_en_ax(struct rtw89_dev *rtwdev) 4215 { 4216 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 4217 u32 val; 4218 4219 if (chip_id == RTL8852C) 4220 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 4221 B_AX_PKT_BUF_EN | B_AX_H_AXIDMA_EN; 4222 else 4223 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 4224 B_AX_PKT_BUF_EN; 4225 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val); 4226 } 4227 4228 static void rtw89_mac_dmac_func_pre_en_ax(struct rtw89_dev *rtwdev) 4229 { 4230 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 4231 u32 val; 4232 4233 if (chip_id == RTL8851B || chip_id == RTL8852BT) 4234 val = B_AX_DISPATCHER_CLK_EN | B_AX_AXIDMA_CLK_EN; 4235 else 4236 val = B_AX_DISPATCHER_CLK_EN; 4237 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val); 4238 4239 if (chip_id != RTL8852C) 4240 return; 4241 4242 val = rtw89_read32(rtwdev, R_AX_HAXI_INIT_CFG1); 4243 val &= ~(B_AX_DMA_MODE_MASK | B_AX_STOP_AXI_MST); 4244 val |= B_AX_TXHCI_EN_V1 | B_AX_RXHCI_EN_V1; 4245 4246 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) 4247 val |= FIELD_PREP(B_AX_DMA_MODE_MASK, DMA_MOD_PCIE_1B); 4248 else if (rtwdev->hci.type == RTW89_HCI_TYPE_USB) 4249 val |= FIELD_PREP(B_AX_DMA_MODE_MASK, DMA_MOD_USB); 4250 else 4251 val |= FIELD_PREP(B_AX_DMA_MODE_MASK, DMA_MOD_SDIO); 4252 4253 rtw89_write32(rtwdev, R_AX_HAXI_INIT_CFG1, val); 4254 4255 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP1, 4256 B_AX_STOP_ACH0 | B_AX_STOP_ACH1 | B_AX_STOP_ACH3 | 4257 B_AX_STOP_ACH4 | B_AX_STOP_ACH5 | B_AX_STOP_ACH6 | 4258 B_AX_STOP_ACH7 | B_AX_STOP_CH8 | B_AX_STOP_CH9 | 4259 B_AX_STOP_CH12 | B_AX_STOP_ACH2); 4260 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP2, B_AX_STOP_CH10 | B_AX_STOP_CH11); 4261 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_AXIDMA_EN); 4262 } 4263 4264 static int rtw89_mac_dmac_pre_init(struct rtw89_dev *rtwdev) 4265 { 4266 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4267 int ret; 4268 4269 mac->hci_func_en(rtwdev); 4270 mac->dmac_func_pre_en(rtwdev); 4271 4272 ret = rtw89_mac_dle_init(rtwdev, RTW89_QTA_DLFW, rtwdev->mac.qta_mode); 4273 if (ret) { 4274 rtw89_err(rtwdev, "[ERR]DLE pre init %d\n", ret); 4275 return ret; 4276 } 4277 4278 ret = rtw89_mac_hfc_init(rtwdev, true, false, true); 4279 if (ret) { 4280 rtw89_err(rtwdev, "[ERR]HCI FC pre init %d\n", ret); 4281 return ret; 4282 } 4283 4284 return ret; 4285 } 4286 4287 int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev) 4288 { 4289 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, 4290 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 4291 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, 4292 B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 4293 B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 4294 rtw89_write8_set(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 4295 4296 return 0; 4297 } 4298 EXPORT_SYMBOL(rtw89_mac_enable_bb_rf); 4299 4300 int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev) 4301 { 4302 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, 4303 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 4304 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, 4305 B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 4306 B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 4307 rtw89_write8_clr(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 4308 4309 return 0; 4310 } 4311 EXPORT_SYMBOL(rtw89_mac_disable_bb_rf); 4312 4313 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev, bool include_bb, 4314 bool bb_preinit) 4315 { 4316 int ret; 4317 4318 rtw89_mac_ctrl_hci_dma_trx(rtwdev, true); 4319 4320 if (include_bb || bb_preinit) { 4321 /* Only call BB preinit including configuration of BB MCU for 4322 * the chips which need to download BB MCU firmware. Otherwise, 4323 * calling preinit later to prevent touching registers affecting 4324 * download firmware. 4325 */ 4326 rtw89_chip_bb_preinit(rtwdev); 4327 } 4328 4329 ret = rtw89_mac_dmac_pre_init(rtwdev); 4330 if (ret) 4331 return ret; 4332 4333 if (rtwdev->hci.ops->mac_pre_init) { 4334 ret = rtwdev->hci.ops->mac_pre_init(rtwdev); 4335 if (ret) 4336 return ret; 4337 } 4338 4339 rtw89_mac_fwdl_preconfig(rtwdev); 4340 4341 ret = rtw89_fw_download(rtwdev, RTW89_FW_NORMAL, include_bb); 4342 if (ret) 4343 return ret; 4344 4345 return 0; 4346 } 4347 4348 int rtw89_mac_preinit(struct rtw89_dev *rtwdev) 4349 { 4350 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4351 int ret; 4352 4353 ret = rtw89_mac_pwr_on(rtwdev); 4354 if (ret) 4355 return ret; 4356 4357 if (mac->mac_func_en) { 4358 ret = mac->mac_func_en(rtwdev); 4359 if (ret) 4360 return ret; 4361 } 4362 4363 return 0; 4364 } 4365 4366 int rtw89_mac_init(struct rtw89_dev *rtwdev) 4367 { 4368 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4369 const struct rtw89_chip_info *chip = rtwdev->chip; 4370 bool include_bb = !!chip->bbmcu_nr; 4371 int ret; 4372 4373 ret = rtw89_mac_partial_init(rtwdev, include_bb, include_bb); 4374 if (ret) 4375 goto fail; 4376 4377 ret = rtw89_chip_enable_bb_rf(rtwdev); 4378 if (ret) 4379 goto fail; 4380 4381 ret = mac->sys_init(rtwdev); 4382 if (ret) 4383 goto fail; 4384 4385 ret = mac->trx_init(rtwdev); 4386 if (ret) 4387 goto fail; 4388 4389 ret = rtw89_mac_feat_init(rtwdev); 4390 if (ret) 4391 goto fail; 4392 4393 if (rtwdev->hci.ops->mac_post_init) { 4394 ret = rtwdev->hci.ops->mac_post_init(rtwdev); 4395 if (ret) 4396 goto fail; 4397 } 4398 4399 rtw89_fw_send_all_early_h2c(rtwdev); 4400 rtw89_fw_h2c_set_ofld_cfg(rtwdev); 4401 4402 return ret; 4403 fail: 4404 rtw89_mac_pwr_off(rtwdev); 4405 4406 return ret; 4407 } 4408 4409 static void rtw89_mac_dmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 4410 { 4411 struct rtw89_fw_secure *sec = &rtwdev->fw.sec; 4412 u8 i; 4413 4414 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX || sec->secure_boot) 4415 return; 4416 4417 for (i = 0; i < 4; i++) { 4418 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 4419 DMAC_TBL_BASE_ADDR + (macid << 4) + (i << 2)); 4420 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0); 4421 } 4422 } 4423 4424 static void rtw89_mac_cmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 4425 { 4426 struct rtw89_fw_secure *sec = &rtwdev->fw.sec; 4427 4428 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX || sec->secure_boot) 4429 return; 4430 4431 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 4432 CMAC_TBL_BASE_ADDR + macid * CCTL_INFO_SIZE); 4433 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0x4); 4434 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 4, 0x400A0004); 4435 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 8, 0); 4436 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 12, 0); 4437 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 16, 0); 4438 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 20, 0xE43000B); 4439 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 24, 0); 4440 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 28, 0xB8109); 4441 } 4442 4443 int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause) 4444 { 4445 u8 sh = FIELD_GET(GENMASK(4, 0), macid); 4446 u8 grp = macid >> 5; 4447 int ret; 4448 4449 /* If this is called by change_interface() in the case of P2P, it could 4450 * be power-off, so ignore this operation. 4451 */ 4452 if (test_bit(RTW89_FLAG_CHANGING_INTERFACE, rtwdev->flags) && 4453 !test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 4454 return 0; 4455 4456 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 4457 if (ret) 4458 return ret; 4459 4460 rtw89_fw_h2c_macid_pause(rtwdev, sh, grp, pause); 4461 4462 return 0; 4463 } 4464 4465 static const struct rtw89_port_reg rtw89_port_base_ax = { 4466 .port_cfg = R_AX_PORT_CFG_P0, 4467 .tbtt_prohib = R_AX_TBTT_PROHIB_P0, 4468 .bcn_area = R_AX_BCN_AREA_P0, 4469 .bcn_early = R_AX_BCNERLYINT_CFG_P0, 4470 .tbtt_early = R_AX_TBTTERLYINT_CFG_P0, 4471 .tbtt_agg = R_AX_TBTT_AGG_P0, 4472 .bcn_space = R_AX_BCN_SPACE_CFG_P0, 4473 .bcn_forcetx = R_AX_BCN_FORCETX_P0, 4474 .bcn_err_cnt = R_AX_BCN_ERR_CNT_P0, 4475 .bcn_err_flag = R_AX_BCN_ERR_FLAG_P0, 4476 .dtim_ctrl = R_AX_DTIM_CTRL_P0, 4477 .tbtt_shift = R_AX_TBTT_SHIFT_P0, 4478 .bcn_cnt_tmr = R_AX_BCN_CNT_TMR_P0, 4479 .tsftr_l = R_AX_TSFTR_LOW_P0, 4480 .tsftr_h = R_AX_TSFTR_HIGH_P0, 4481 .md_tsft = R_AX_MD_TSFT_STMP_CTL, 4482 .bss_color = R_AX_PTCL_BSS_COLOR_0, 4483 .mbssid = R_AX_MBSSID_CTRL, 4484 .mbssid_drop = R_AX_MBSSID_DROP_0, 4485 .tsf_sync = R_AX_PORT0_TSF_SYNC, 4486 .ptcl_dbg = R_AX_PTCL_DBG, 4487 .ptcl_dbg_info = R_AX_PTCL_DBG_INFO, 4488 .bcn_drop_all = R_AX_BCN_DROP_ALL0, 4489 .bcn_psr_rpt = R_AX_BCN_PSR_RPT_P0, 4490 .hiq_win = {R_AX_P0MB_HGQ_WINDOW_CFG_0, R_AX_PORT_HGQ_WINDOW_CFG, 4491 R_AX_PORT_HGQ_WINDOW_CFG + 1, R_AX_PORT_HGQ_WINDOW_CFG + 2, 4492 R_AX_PORT_HGQ_WINDOW_CFG + 3}, 4493 }; 4494 4495 static const struct rtw89_mac_mu_gid_addr rtw89_mac_mu_gid_addr_ax = { 4496 .position_en = {R_AX_GID_POSITION_EN0, R_AX_GID_POSITION_EN1}, 4497 .position = {R_AX_GID_POSITION0, R_AX_GID_POSITION1, 4498 R_AX_GID_POSITION2, R_AX_GID_POSITION3}, 4499 }; 4500 4501 static void rtw89_mac_check_packet_ctrl(struct rtw89_dev *rtwdev, 4502 struct rtw89_vif_link *rtwvif_link, u8 type) 4503 { 4504 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4505 const struct rtw89_port_reg *p = mac->port_base; 4506 u8 mask = B_AX_PTCL_DBG_INFO_MASK_BY_PORT(rtwvif_link->port); 4507 u32 reg_info, reg_ctrl; 4508 u32 val; 4509 int ret; 4510 4511 reg_info = rtw89_mac_reg_by_idx(rtwdev, p->ptcl_dbg_info, rtwvif_link->mac_idx); 4512 reg_ctrl = rtw89_mac_reg_by_idx(rtwdev, p->ptcl_dbg, rtwvif_link->mac_idx); 4513 4514 rtw89_write32_mask(rtwdev, reg_ctrl, B_AX_PTCL_DBG_SEL_MASK, type); 4515 rtw89_write32_set(rtwdev, reg_ctrl, B_AX_PTCL_DBG_EN); 4516 fsleep(100); 4517 4518 ret = read_poll_timeout(rtw89_read32_mask, val, val == 0, 1000, 100000, 4519 true, rtwdev, reg_info, mask); 4520 if (ret) 4521 rtw89_warn(rtwdev, "Polling beacon packet empty fail\n"); 4522 } 4523 4524 static void rtw89_mac_bcn_drop(struct rtw89_dev *rtwdev, 4525 struct rtw89_vif_link *rtwvif_link) 4526 { 4527 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4528 const struct rtw89_port_reg *p = mac->port_base; 4529 4530 rtw89_write32_set(rtwdev, p->bcn_drop_all, BIT(rtwvif_link->port)); 4531 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib, B_AX_TBTT_SETUP_MASK, 4532 1); 4533 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_area, B_AX_BCN_MSK_AREA_MASK, 4534 0); 4535 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib, B_AX_TBTT_HOLD_MASK, 4536 0); 4537 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_early, B_AX_BCNERLY_MASK, 2); 4538 rtw89_write16_port_mask(rtwdev, rtwvif_link, p->tbtt_early, 4539 B_AX_TBTTERLY_MASK, 1); 4540 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_space, 4541 B_AX_BCN_SPACE_MASK, 1); 4542 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, B_AX_BCNTX_EN); 4543 4544 rtw89_mac_check_packet_ctrl(rtwdev, rtwvif_link, AX_PTCL_DBG_BCNQ_NUM0); 4545 if (rtwvif_link->port == RTW89_PORT_0) 4546 rtw89_mac_check_packet_ctrl(rtwdev, rtwvif_link, AX_PTCL_DBG_BCNQ_NUM1); 4547 4548 rtw89_write32_clr(rtwdev, p->bcn_drop_all, BIT(rtwvif_link->port)); 4549 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, B_AX_TBTT_PROHIB_EN); 4550 fsleep(2000); 4551 } 4552 4553 #define BCN_INTERVAL 100 4554 #define BCN_ERLY_DEF 160 4555 #define BCN_SETUP_DEF 2 4556 #define BCN_HOLD_DEF 200 4557 #define BCN_MASK_DEF 0 4558 #define TBTT_ERLY_DEF 5 4559 #define TBTT_AGG_DEF 1 4560 #define BCN_SET_UNIT 32 4561 #define BCN_ERLY_SET_DLY (10 * 2) 4562 4563 static void rtw89_mac_port_cfg_func_sw(struct rtw89_dev *rtwdev, 4564 struct rtw89_vif_link *rtwvif_link) 4565 { 4566 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4567 const struct rtw89_port_reg *p = mac->port_base; 4568 const struct rtw89_chip_info *chip = rtwdev->chip; 4569 struct ieee80211_bss_conf *bss_conf; 4570 bool need_backup = false; 4571 u32 backup_val; 4572 u16 beacon_int; 4573 4574 if (!rtw89_read32_port_mask(rtwdev, rtwvif_link, p->port_cfg, B_AX_PORT_FUNC_EN)) 4575 return; 4576 4577 if (chip->chip_id == RTL8852A && rtwvif_link->port != RTW89_PORT_0) { 4578 need_backup = true; 4579 backup_val = rtw89_read32_port(rtwdev, rtwvif_link, p->tbtt_prohib); 4580 } 4581 4582 if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE) 4583 rtw89_mac_bcn_drop(rtwdev, rtwvif_link); 4584 4585 if (chip->chip_id == RTL8852A) { 4586 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->tbtt_prohib, 4587 B_AX_TBTT_SETUP_MASK); 4588 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib, 4589 B_AX_TBTT_HOLD_MASK, 1); 4590 rtw89_write16_port_clr(rtwdev, rtwvif_link, p->tbtt_early, 4591 B_AX_TBTTERLY_MASK); 4592 rtw89_write16_port_clr(rtwdev, rtwvif_link, p->bcn_early, 4593 B_AX_BCNERLY_MASK); 4594 } 4595 4596 rcu_read_lock(); 4597 4598 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4599 beacon_int = bss_conf->beacon_int; 4600 4601 rcu_read_unlock(); 4602 4603 msleep(beacon_int + 1); 4604 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, B_AX_PORT_FUNC_EN | 4605 B_AX_BRK_SETUP); 4606 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, B_AX_TSFTR_RST); 4607 rtw89_write32_port(rtwdev, rtwvif_link, p->bcn_cnt_tmr, 0); 4608 4609 if (need_backup) 4610 rtw89_write32_port(rtwdev, rtwvif_link, p->tbtt_prohib, backup_val); 4611 } 4612 4613 static void rtw89_mac_port_cfg_tx_rpt(struct rtw89_dev *rtwdev, 4614 struct rtw89_vif_link *rtwvif_link, bool en) 4615 { 4616 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4617 const struct rtw89_port_reg *p = mac->port_base; 4618 4619 if (en) 4620 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, 4621 B_AX_TXBCN_RPT_EN); 4622 else 4623 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, 4624 B_AX_TXBCN_RPT_EN); 4625 } 4626 4627 static void rtw89_mac_port_cfg_rx_rpt(struct rtw89_dev *rtwdev, 4628 struct rtw89_vif_link *rtwvif_link, bool en) 4629 { 4630 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4631 const struct rtw89_port_reg *p = mac->port_base; 4632 4633 if (en) 4634 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, 4635 B_AX_RXBCN_RPT_EN); 4636 else 4637 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, 4638 B_AX_RXBCN_RPT_EN); 4639 } 4640 4641 static void rtw89_mac_port_cfg_net_type(struct rtw89_dev *rtwdev, 4642 struct rtw89_vif_link *rtwvif_link) 4643 { 4644 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4645 const struct rtw89_port_reg *p = mac->port_base; 4646 4647 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->port_cfg, B_AX_NET_TYPE_MASK, 4648 rtwvif_link->net_type); 4649 } 4650 4651 static void rtw89_mac_port_cfg_bcn_prct(struct rtw89_dev *rtwdev, 4652 struct rtw89_vif_link *rtwvif_link) 4653 { 4654 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4655 const struct rtw89_port_reg *p = mac->port_base; 4656 bool en = rtwvif_link->net_type != RTW89_NET_TYPE_NO_LINK; 4657 u32 bits = B_AX_TBTT_PROHIB_EN | B_AX_BRK_SETUP; 4658 4659 if (en) 4660 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, bits); 4661 else 4662 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, bits); 4663 } 4664 4665 static void rtw89_mac_port_cfg_rx_sw(struct rtw89_dev *rtwdev, 4666 struct rtw89_vif_link *rtwvif_link) 4667 { 4668 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4669 const struct rtw89_port_reg *p = mac->port_base; 4670 bool en = rtwvif_link->net_type == RTW89_NET_TYPE_INFRA || 4671 rtwvif_link->net_type == RTW89_NET_TYPE_AD_HOC; 4672 u32 bit = B_AX_RX_BSSID_FIT_EN; 4673 4674 if (en) 4675 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, bit); 4676 else 4677 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, bit); 4678 } 4679 4680 void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev, 4681 struct rtw89_vif_link *rtwvif_link, bool en) 4682 { 4683 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4684 const struct rtw89_port_reg *p = mac->port_base; 4685 4686 if (en) 4687 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, B_AX_TSF_UDT_EN); 4688 else 4689 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, B_AX_TSF_UDT_EN); 4690 } 4691 4692 static void rtw89_mac_port_cfg_rx_sync_by_nettype(struct rtw89_dev *rtwdev, 4693 struct rtw89_vif_link *rtwvif_link) 4694 { 4695 bool en = rtwvif_link->net_type == RTW89_NET_TYPE_INFRA || 4696 rtwvif_link->net_type == RTW89_NET_TYPE_AD_HOC; 4697 4698 rtw89_mac_port_cfg_rx_sync(rtwdev, rtwvif_link, en); 4699 } 4700 4701 static void rtw89_mac_port_cfg_tx_sw(struct rtw89_dev *rtwdev, 4702 struct rtw89_vif_link *rtwvif_link, bool en) 4703 { 4704 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4705 const struct rtw89_port_reg *p = mac->port_base; 4706 4707 if (en) 4708 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, B_AX_BCNTX_EN); 4709 else 4710 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, B_AX_BCNTX_EN); 4711 } 4712 4713 static void rtw89_mac_port_cfg_tx_sw_by_nettype(struct rtw89_dev *rtwdev, 4714 struct rtw89_vif_link *rtwvif_link) 4715 { 4716 bool en = rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE || 4717 rtwvif_link->net_type == RTW89_NET_TYPE_AD_HOC; 4718 4719 rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif_link, en); 4720 } 4721 4722 static void rtw89_mac_enable_ap_bcn_by_chan(struct rtw89_dev *rtwdev, 4723 struct rtw89_vif_link *rtwvif_link, 4724 const struct rtw89_chan *to_match, 4725 bool en) 4726 { 4727 const struct rtw89_chan *chan; 4728 4729 if (rtwvif_link->net_type != RTW89_NET_TYPE_AP_MODE) 4730 return; 4731 4732 if (!to_match) 4733 goto doit; 4734 4735 /* @to_match may not be in the same domain as return of calling 4736 * rtw89_chan_get(). So, cannot compare their addresses directly. 4737 */ 4738 chan = rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx); 4739 if (chan->channel != to_match->channel) 4740 return; 4741 4742 doit: 4743 rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif_link, en); 4744 } 4745 4746 static void rtw89_mac_enable_aps_bcn_by_chan(struct rtw89_dev *rtwdev, 4747 const struct rtw89_chan *to_match, 4748 bool en) 4749 { 4750 struct rtw89_vif_link *rtwvif_link; 4751 struct rtw89_vif *rtwvif; 4752 unsigned int link_id; 4753 4754 rtw89_for_each_rtwvif(rtwdev, rtwvif) 4755 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 4756 rtw89_mac_enable_ap_bcn_by_chan(rtwdev, rtwvif_link, 4757 to_match, en); 4758 } 4759 4760 void rtw89_mac_enable_beacon_for_ap_vifs(struct rtw89_dev *rtwdev, bool en) 4761 { 4762 rtw89_mac_enable_aps_bcn_by_chan(rtwdev, NULL, en); 4763 } 4764 4765 static void rtw89_mac_port_cfg_bcn_intv(struct rtw89_dev *rtwdev, 4766 struct rtw89_vif_link *rtwvif_link) 4767 { 4768 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4769 const struct rtw89_port_reg *p = mac->port_base; 4770 struct ieee80211_bss_conf *bss_conf; 4771 u16 bcn_int; 4772 4773 rcu_read_lock(); 4774 4775 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4776 if (bss_conf->beacon_int) 4777 bcn_int = bss_conf->beacon_int; 4778 else 4779 bcn_int = BCN_INTERVAL; 4780 4781 rcu_read_unlock(); 4782 4783 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_space, B_AX_BCN_SPACE_MASK, 4784 bcn_int); 4785 } 4786 4787 static void rtw89_mac_port_cfg_hiq_win(struct rtw89_dev *rtwdev, 4788 struct rtw89_vif_link *rtwvif_link) 4789 { 4790 u8 win = rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE ? 16 : 0; 4791 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4792 const struct rtw89_port_reg *p = mac->port_base; 4793 u8 port = rtwvif_link->port; 4794 u32 reg; 4795 4796 reg = rtw89_mac_reg_by_idx(rtwdev, p->hiq_win[port], rtwvif_link->mac_idx); 4797 rtw89_write8(rtwdev, reg, win); 4798 } 4799 4800 static void rtw89_mac_port_cfg_hiq_dtim(struct rtw89_dev *rtwdev, 4801 struct rtw89_vif_link *rtwvif_link) 4802 { 4803 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4804 const struct rtw89_port_reg *p = mac->port_base; 4805 struct ieee80211_bss_conf *bss_conf; 4806 u8 dtim_period; 4807 u32 addr; 4808 4809 rcu_read_lock(); 4810 4811 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4812 dtim_period = bss_conf->dtim_period; 4813 4814 rcu_read_unlock(); 4815 4816 addr = rtw89_mac_reg_by_idx(rtwdev, p->md_tsft, rtwvif_link->mac_idx); 4817 rtw89_write8_set(rtwdev, addr, B_AX_UPD_HGQMD | B_AX_UPD_TIMIE); 4818 4819 rtw89_write16_port_mask(rtwdev, rtwvif_link, p->dtim_ctrl, B_AX_DTIM_NUM_MASK, 4820 dtim_period); 4821 } 4822 4823 static void rtw89_mac_port_cfg_bcn_setup_time(struct rtw89_dev *rtwdev, 4824 struct rtw89_vif_link *rtwvif_link) 4825 { 4826 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4827 const struct rtw89_port_reg *p = mac->port_base; 4828 4829 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib, 4830 B_AX_TBTT_SETUP_MASK, BCN_SETUP_DEF); 4831 } 4832 4833 static void rtw89_mac_port_cfg_bcn_hold_time(struct rtw89_dev *rtwdev, 4834 struct rtw89_vif_link *rtwvif_link) 4835 { 4836 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4837 const struct rtw89_port_reg *p = mac->port_base; 4838 4839 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->tbtt_prohib, 4840 B_AX_TBTT_HOLD_MASK, BCN_HOLD_DEF); 4841 } 4842 4843 static void rtw89_mac_port_cfg_bcn_mask_area(struct rtw89_dev *rtwdev, 4844 struct rtw89_vif_link *rtwvif_link) 4845 { 4846 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4847 const struct rtw89_port_reg *p = mac->port_base; 4848 4849 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_area, 4850 B_AX_BCN_MSK_AREA_MASK, BCN_MASK_DEF); 4851 } 4852 4853 static void rtw89_mac_port_cfg_tbtt_early(struct rtw89_dev *rtwdev, 4854 struct rtw89_vif_link *rtwvif_link) 4855 { 4856 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4857 const struct rtw89_port_reg *p = mac->port_base; 4858 4859 rtw89_write16_port_mask(rtwdev, rtwvif_link, p->tbtt_early, 4860 B_AX_TBTTERLY_MASK, TBTT_ERLY_DEF); 4861 } 4862 4863 static void rtw89_mac_port_cfg_tbtt_agg(struct rtw89_dev *rtwdev, 4864 struct rtw89_vif_link *rtwvif_link) 4865 { 4866 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4867 const struct rtw89_port_reg *p = mac->port_base; 4868 4869 rtw89_write16_port_mask(rtwdev, rtwvif_link, p->tbtt_agg, 4870 B_AX_TBTT_AGG_NUM_MASK, TBTT_AGG_DEF); 4871 } 4872 4873 static void rtw89_mac_port_cfg_bss_color(struct rtw89_dev *rtwdev, 4874 struct rtw89_vif_link *rtwvif_link) 4875 { 4876 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4877 const struct rtw89_port_reg *p = mac->port_base; 4878 static const u32 masks[RTW89_PORT_NUM] = { 4879 B_AX_BSS_COLOB_AX_PORT_0_MASK, B_AX_BSS_COLOB_AX_PORT_1_MASK, 4880 B_AX_BSS_COLOB_AX_PORT_2_MASK, B_AX_BSS_COLOB_AX_PORT_3_MASK, 4881 B_AX_BSS_COLOB_AX_PORT_4_MASK, 4882 }; 4883 struct ieee80211_bss_conf *bss_conf; 4884 u8 port = rtwvif_link->port; 4885 u32 reg_base; 4886 u32 reg; 4887 u8 bss_color; 4888 4889 rcu_read_lock(); 4890 4891 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4892 bss_color = bss_conf->he_bss_color.color; 4893 4894 rcu_read_unlock(); 4895 4896 reg_base = port >= 4 ? p->bss_color + 4 : p->bss_color; 4897 reg = rtw89_mac_reg_by_idx(rtwdev, reg_base, rtwvif_link->mac_idx); 4898 rtw89_write32_mask(rtwdev, reg, masks[port], bss_color); 4899 } 4900 4901 static void rtw89_mac_port_cfg_mbssid(struct rtw89_dev *rtwdev, 4902 struct rtw89_vif_link *rtwvif_link) 4903 { 4904 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4905 const struct rtw89_port_reg *p = mac->port_base; 4906 u8 port = rtwvif_link->port; 4907 u32 reg; 4908 4909 if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE) 4910 return; 4911 4912 if (port == 0) { 4913 reg = rtw89_mac_reg_by_idx(rtwdev, p->mbssid, rtwvif_link->mac_idx); 4914 rtw89_write32_clr(rtwdev, reg, B_AX_P0MB_ALL_MASK); 4915 } 4916 } 4917 4918 static void rtw89_mac_port_cfg_hiq_drop(struct rtw89_dev *rtwdev, 4919 struct rtw89_vif_link *rtwvif_link) 4920 { 4921 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4922 const struct rtw89_port_reg *p = mac->port_base; 4923 u8 port = rtwvif_link->port; 4924 u32 reg; 4925 u32 val; 4926 4927 reg = rtw89_mac_reg_by_idx(rtwdev, p->mbssid_drop, rtwvif_link->mac_idx); 4928 val = rtw89_read32(rtwdev, reg); 4929 val &= ~FIELD_PREP(B_AX_PORT_DROP_4_0_MASK, BIT(port)); 4930 if (port == 0) 4931 val &= ~BIT(0); 4932 rtw89_write32(rtwdev, reg, val); 4933 } 4934 4935 static void rtw89_mac_port_cfg_func_en(struct rtw89_dev *rtwdev, 4936 struct rtw89_vif_link *rtwvif_link, bool enable) 4937 { 4938 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4939 const struct rtw89_port_reg *p = mac->port_base; 4940 4941 if (enable) 4942 rtw89_write32_port_set(rtwdev, rtwvif_link, p->port_cfg, 4943 B_AX_PORT_FUNC_EN); 4944 else 4945 rtw89_write32_port_clr(rtwdev, rtwvif_link, p->port_cfg, 4946 B_AX_PORT_FUNC_EN); 4947 } 4948 4949 static void rtw89_mac_port_cfg_bcn_early(struct rtw89_dev *rtwdev, 4950 struct rtw89_vif_link *rtwvif_link) 4951 { 4952 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4953 const struct rtw89_port_reg *p = mac->port_base; 4954 4955 rtw89_write32_port_mask(rtwdev, rtwvif_link, p->bcn_early, B_AX_BCNERLY_MASK, 4956 BCN_ERLY_DEF); 4957 } 4958 4959 static void rtw89_mac_port_cfg_bcn_psr_rpt(struct rtw89_dev *rtwdev, 4960 struct rtw89_vif_link *rtwvif_link) 4961 { 4962 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4963 const struct rtw89_port_reg *p = mac->port_base; 4964 struct ieee80211_bss_conf *bss_conf; 4965 u8 bssid_index; 4966 u32 reg; 4967 4968 rcu_read_lock(); 4969 4970 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4971 if (bss_conf->nontransmitted) 4972 bssid_index = bss_conf->bssid_index; 4973 else 4974 bssid_index = 0; 4975 4976 rcu_read_unlock(); 4977 4978 reg = rtw89_mac_reg_by_idx(rtwdev, p->bcn_psr_rpt + rtwvif_link->port * 4, 4979 rtwvif_link->mac_idx); 4980 rtw89_write32_mask(rtwdev, reg, B_AX_BCAID_P0_MASK, bssid_index); 4981 } 4982 4983 void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev, 4984 struct rtw89_vif_link *rtwvif_link, 4985 struct rtw89_vif_link *rtwvif_src, 4986 u16 offset_tu) 4987 { 4988 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4989 const struct rtw89_port_reg *p = mac->port_base; 4990 u32 val, reg; 4991 4992 val = RTW89_PORT_OFFSET_TU_TO_32US(offset_tu); 4993 reg = rtw89_mac_reg_by_idx(rtwdev, p->tsf_sync + rtwvif_link->port * 4, 4994 rtwvif_link->mac_idx); 4995 4996 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_SRC, rtwvif_src->port); 4997 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_OFFSET_VAL, val); 4998 rtw89_write32_set(rtwdev, reg, B_AX_SYNC_NOW); 4999 } 5000 5001 static void rtw89_mac_port_tsf_sync_rand(struct rtw89_dev *rtwdev, 5002 struct rtw89_vif_link *rtwvif_link, 5003 struct rtw89_vif_link *rtwvif_src, 5004 u8 offset, int *n_offset) 5005 { 5006 if (rtwvif_link->net_type != RTW89_NET_TYPE_AP_MODE || rtwvif_link == rtwvif_src) 5007 return; 5008 5009 if (rtwvif_link->rand_tsf_done) 5010 goto out; 5011 5012 /* adjust offset randomly to avoid beacon conflict */ 5013 offset = offset - offset / 4 + get_random_u32() % (offset / 2); 5014 rtw89_mac_port_tsf_sync(rtwdev, rtwvif_link, rtwvif_src, 5015 (*n_offset) * offset); 5016 5017 rtwvif_link->rand_tsf_done = true; 5018 5019 out: 5020 (*n_offset)++; 5021 } 5022 5023 static void rtw89_mac_port_tsf_resync_all(struct rtw89_dev *rtwdev) 5024 { 5025 struct rtw89_vif_link *src = NULL, *tmp; 5026 u8 offset = 100, vif_aps = 0; 5027 struct rtw89_vif *rtwvif; 5028 unsigned int link_id; 5029 int n_offset = 1; 5030 5031 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 5032 rtw89_vif_for_each_link(rtwvif, tmp, link_id) { 5033 if (!src || tmp->net_type == RTW89_NET_TYPE_INFRA) 5034 src = tmp; 5035 if (tmp->net_type == RTW89_NET_TYPE_AP_MODE) 5036 vif_aps++; 5037 } 5038 } 5039 5040 if (vif_aps == 0) 5041 return; 5042 5043 offset /= (vif_aps + 1); 5044 5045 rtw89_for_each_rtwvif(rtwdev, rtwvif) 5046 rtw89_vif_for_each_link(rtwvif, tmp, link_id) 5047 rtw89_mac_port_tsf_sync_rand(rtwdev, tmp, src, offset, 5048 &n_offset); 5049 } 5050 5051 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 5052 { 5053 int ret; 5054 5055 ret = rtw89_mac_port_update(rtwdev, rtwvif_link); 5056 if (ret) 5057 return ret; 5058 5059 rtw89_mac_dmac_tbl_init(rtwdev, rtwvif_link->mac_id); 5060 rtw89_mac_cmac_tbl_init(rtwdev, rtwvif_link->mac_id); 5061 5062 ret = rtw89_mac_set_macid_pause(rtwdev, rtwvif_link->mac_id, false); 5063 if (ret) 5064 return ret; 5065 5066 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif_link, NULL, RTW89_ROLE_CREATE); 5067 if (ret) 5068 return ret; 5069 5070 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif_link, NULL, true); 5071 if (ret) 5072 return ret; 5073 5074 ret = rtw89_cam_init(rtwdev, rtwvif_link); 5075 if (ret) 5076 return ret; 5077 5078 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, NULL, RTW89_ROLE_CREATE); 5079 if (ret) 5080 return ret; 5081 5082 ret = rtw89_chip_h2c_default_cmac_tbl(rtwdev, rtwvif_link, NULL); 5083 if (ret) 5084 return ret; 5085 5086 ret = rtw89_chip_h2c_default_dmac_tbl(rtwdev, rtwvif_link, NULL); 5087 if (ret) 5088 return ret; 5089 5090 return 0; 5091 } 5092 5093 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 5094 { 5095 int ret; 5096 5097 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif_link, NULL, RTW89_ROLE_REMOVE); 5098 if (ret) 5099 return ret; 5100 5101 rtw89_cam_deinit(rtwdev, rtwvif_link); 5102 5103 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, NULL, RTW89_ROLE_REMOVE); 5104 if (ret) 5105 return ret; 5106 5107 return 0; 5108 } 5109 5110 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 5111 { 5112 u8 port = rtwvif_link->port; 5113 5114 if (port >= RTW89_PORT_NUM) 5115 return -EINVAL; 5116 5117 rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif_link); 5118 rtw89_mac_port_cfg_tx_rpt(rtwdev, rtwvif_link, false); 5119 rtw89_mac_port_cfg_rx_rpt(rtwdev, rtwvif_link, false); 5120 rtw89_mac_port_cfg_net_type(rtwdev, rtwvif_link); 5121 rtw89_mac_port_cfg_bcn_prct(rtwdev, rtwvif_link); 5122 rtw89_mac_port_cfg_rx_sw(rtwdev, rtwvif_link); 5123 rtw89_mac_port_cfg_rx_sync_by_nettype(rtwdev, rtwvif_link); 5124 rtw89_mac_port_cfg_tx_sw_by_nettype(rtwdev, rtwvif_link); 5125 rtw89_mac_port_cfg_bcn_intv(rtwdev, rtwvif_link); 5126 rtw89_mac_port_cfg_hiq_win(rtwdev, rtwvif_link); 5127 rtw89_mac_port_cfg_hiq_dtim(rtwdev, rtwvif_link); 5128 rtw89_mac_port_cfg_hiq_drop(rtwdev, rtwvif_link); 5129 rtw89_mac_port_cfg_bcn_setup_time(rtwdev, rtwvif_link); 5130 rtw89_mac_port_cfg_bcn_hold_time(rtwdev, rtwvif_link); 5131 rtw89_mac_port_cfg_bcn_mask_area(rtwdev, rtwvif_link); 5132 rtw89_mac_port_cfg_tbtt_early(rtwdev, rtwvif_link); 5133 rtw89_mac_port_cfg_tbtt_agg(rtwdev, rtwvif_link); 5134 rtw89_mac_port_cfg_bss_color(rtwdev, rtwvif_link); 5135 rtw89_mac_port_cfg_mbssid(rtwdev, rtwvif_link); 5136 rtw89_mac_port_cfg_func_en(rtwdev, rtwvif_link, true); 5137 rtw89_mac_port_tsf_resync_all(rtwdev); 5138 fsleep(BCN_ERLY_SET_DLY); 5139 rtw89_mac_port_cfg_bcn_early(rtwdev, rtwvif_link); 5140 rtw89_mac_port_cfg_bcn_psr_rpt(rtwdev, rtwvif_link); 5141 5142 return 0; 5143 } 5144 5145 int rtw89_mac_port_get_tsf(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 5146 u64 *tsf) 5147 { 5148 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 5149 const struct rtw89_port_reg *p = mac->port_base; 5150 u32 tsf_low, tsf_high; 5151 int ret; 5152 5153 ret = rtw89_mac_check_mac_en(rtwdev, rtwvif_link->mac_idx, RTW89_CMAC_SEL); 5154 if (ret) 5155 return ret; 5156 5157 tsf_low = rtw89_read32_port(rtwdev, rtwvif_link, p->tsftr_l); 5158 tsf_high = rtw89_read32_port(rtwdev, rtwvif_link, p->tsftr_h); 5159 *tsf = (u64)tsf_high << 32 | tsf_low; 5160 5161 return 0; 5162 } 5163 5164 static void rtw89_mac_check_he_obss_narrow_bw_ru_iter(struct wiphy *wiphy, 5165 struct cfg80211_bss *bss, 5166 void *data) 5167 { 5168 const struct cfg80211_bss_ies *ies; 5169 const struct element *elem; 5170 bool *tolerated = data; 5171 5172 rcu_read_lock(); 5173 ies = rcu_dereference(bss->ies); 5174 elem = cfg80211_find_elem(WLAN_EID_EXT_CAPABILITY, ies->data, 5175 ies->len); 5176 5177 if (!elem || elem->datalen < 11 || 5178 !(elem->data[10] & WLAN_EXT_CAPA10_OBSS_NARROW_BW_RU_TOLERANCE_SUPPORT)) 5179 *tolerated = false; 5180 rcu_read_unlock(); 5181 } 5182 5183 void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev, 5184 struct rtw89_vif_link *rtwvif_link) 5185 { 5186 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 5187 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 5188 struct ieee80211_hw *hw = rtwdev->hw; 5189 struct ieee80211_bss_conf *bss_conf; 5190 struct cfg80211_chan_def oper; 5191 bool tolerated = true; 5192 u32 reg; 5193 5194 rcu_read_lock(); 5195 5196 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 5197 if (!bss_conf->he_support || vif->type != NL80211_IFTYPE_STATION) { 5198 rcu_read_unlock(); 5199 return; 5200 } 5201 5202 oper = bss_conf->chanreq.oper; 5203 if (!(oper.chan->flags & IEEE80211_CHAN_RADAR)) { 5204 rcu_read_unlock(); 5205 return; 5206 } 5207 5208 rcu_read_unlock(); 5209 5210 cfg80211_bss_iter(hw->wiphy, &oper, 5211 rtw89_mac_check_he_obss_narrow_bw_ru_iter, 5212 &tolerated); 5213 5214 reg = rtw89_mac_reg_by_idx(rtwdev, mac->narrow_bw_ru_dis.addr, 5215 rtwvif_link->mac_idx); 5216 if (tolerated) 5217 rtw89_write32_clr(rtwdev, reg, mac->narrow_bw_ru_dis.mask); 5218 else 5219 rtw89_write32_set(rtwdev, reg, mac->narrow_bw_ru_dis.mask); 5220 } 5221 5222 void rtw89_mac_set_he_tb(struct rtw89_dev *rtwdev, 5223 struct rtw89_vif_link *rtwvif_link) 5224 { 5225 struct ieee80211_bss_conf *bss_conf; 5226 bool set; 5227 u32 reg; 5228 5229 if (rtwdev->chip->chip_gen != RTW89_CHIP_BE) 5230 return; 5231 5232 rcu_read_lock(); 5233 5234 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 5235 set = bss_conf->he_support && !bss_conf->eht_support; 5236 5237 rcu_read_unlock(); 5238 5239 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CLIENT_OM_CTRL, 5240 rtwvif_link->mac_idx); 5241 5242 if (set) 5243 rtw89_write32_set(rtwdev, reg, B_BE_TRIG_DIS_EHTTB); 5244 else 5245 rtw89_write32_clr(rtwdev, reg, B_BE_TRIG_DIS_EHTTB); 5246 } 5247 5248 void rtw89_mac_stop_ap(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 5249 { 5250 rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif_link); 5251 5252 rtwvif_link->rand_tsf_done = false; 5253 } 5254 5255 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 5256 { 5257 return rtw89_mac_vif_init(rtwdev, rtwvif_link); 5258 } 5259 5260 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link) 5261 { 5262 return rtw89_mac_vif_deinit(rtwdev, rtwvif_link); 5263 } 5264 5265 static void 5266 rtw89_mac_c2h_macid_pause(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5267 { 5268 } 5269 5270 static const struct rtw89_chan * 5271 rtw89_hw_scan_search_op_chan(struct rtw89_dev *rtwdev, u8 band, u8 channel) 5272 { 5273 struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info; 5274 const struct rtw89_chan *op = &rtwdev->scan_info.op_chan; 5275 5276 if (band == op->band_type && channel == op->primary_channel) 5277 return op; 5278 5279 if (scan_info->extra_op.set) { 5280 op = &scan_info->extra_op.chan; 5281 if (band == op->band_type && channel == op->primary_channel) 5282 return op; 5283 } 5284 5285 return NULL; 5286 } 5287 5288 static void 5289 rtw89_mac_c2h_scanofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *skb, 5290 u32 len) 5291 { 5292 const struct rtw89_c2h_scanofld *c2h = 5293 (const struct rtw89_c2h_scanofld *)skb->data; 5294 struct rtw89_vif_link *rtwvif_link = rtwdev->scan_info.scanning_vif; 5295 const struct rtw89_chan *op_chan; 5296 struct rtw89_vif *rtwvif; 5297 struct rtw89_chan new; 5298 u16 actual_period, expect_period; 5299 u8 reason, status, tx_fail, band; 5300 u8 mac_idx, sw_def, fw_def; 5301 u8 ver = U8_MAX; 5302 u32 report_tsf; 5303 u16 chan; 5304 int ret; 5305 5306 if (!rtwvif_link) 5307 return; 5308 5309 rtwvif = rtwvif_link->rtwvif; 5310 5311 if (RTW89_CHK_FW_FEATURE(CH_INFO_BE_V0, &rtwdev->fw)) 5312 ver = 0; 5313 5314 tx_fail = le32_get_bits(c2h->w5, RTW89_C2H_SCANOFLD_W5_TX_FAIL); 5315 status = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_STATUS); 5316 chan = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_PRI_CH); 5317 reason = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_RSN); 5318 band = le32_get_bits(c2h->w5, RTW89_C2H_SCANOFLD_W5_BAND); 5319 actual_period = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_PERIOD); 5320 mac_idx = le32_get_bits(c2h->w5, RTW89_C2H_SCANOFLD_W5_MAC_IDX); 5321 5322 5323 if (!(rtwdev->chip->support_bands & BIT(NL80211_BAND_6GHZ))) 5324 band = chan > 14 ? RTW89_BAND_5G : RTW89_BAND_2G; 5325 5326 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) { 5327 sw_def = le32_get_bits(c2h->w6, RTW89_C2H_SCANOFLD_W6_SW_DEF); 5328 fw_def = le32_get_bits(c2h->w6, RTW89_C2H_SCANOFLD_W6_FW_DEF); 5329 report_tsf = le32_get_bits(c2h->w7, RTW89_C2H_SCANOFLD_W7_REPORT_TSF); 5330 if (ver == 0) { 5331 expect_period = 5332 le32_get_bits(c2h->w6, RTW89_C2H_SCANOFLD_W6_EXPECT_PERIOD); 5333 } else { 5334 actual_period = le32_get_bits(c2h->w8, RTW89_C2H_SCANOFLD_W8_PERIOD_V1); 5335 expect_period = 5336 le32_get_bits(c2h->w8, RTW89_C2H_SCANOFLD_W8_EXPECT_PERIOD_V1); 5337 } 5338 5339 rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN, 5340 "sw_def: %d, fw_def: %d, tsf: %x, expect: %d\n", 5341 sw_def, fw_def, report_tsf, expect_period); 5342 } 5343 5344 rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN, 5345 "mac_idx[%d] band: %d, chan: %d, reason: %d, status: %d, tx_fail: %d, actual: %d\n", 5346 mac_idx, band, chan, reason, status, tx_fail, actual_period); 5347 5348 switch (reason) { 5349 case RTW89_SCAN_LEAVE_OP_NOTIFY: 5350 case RTW89_SCAN_LEAVE_CH_NOTIFY: 5351 op_chan = rtw89_hw_scan_search_op_chan(rtwdev, band, chan); 5352 if (op_chan) { 5353 rtw89_mac_enable_aps_bcn_by_chan(rtwdev, op_chan, false); 5354 ieee80211_stop_queues(rtwdev->hw); 5355 } else { 5356 rtw89_phy_nhm_get_result(rtwdev, band, chan); 5357 } 5358 return; 5359 case RTW89_SCAN_END_SCAN_NOTIFY: 5360 if (rtwdev->scan_info.abort) 5361 return; 5362 5363 if (rtwvif_link && rtwvif->scan_req && 5364 !list_empty(&rtwdev->scan_info.chan_list)) { 5365 rtwdev->scan_info.delay = 0; 5366 ret = rtw89_hw_scan_offload(rtwdev, rtwvif_link, true); 5367 if (ret) { 5368 rtw89_hw_scan_abort(rtwdev, rtwvif_link); 5369 rtw89_warn(rtwdev, "HW scan failed: %d\n", ret); 5370 } 5371 } else { 5372 rtw89_hw_scan_complete(rtwdev, rtwvif_link, false); 5373 } 5374 break; 5375 case RTW89_SCAN_ENTER_OP_NOTIFY: 5376 case RTW89_SCAN_ENTER_CH_NOTIFY: 5377 op_chan = rtw89_hw_scan_search_op_chan(rtwdev, band, chan); 5378 if (op_chan) { 5379 rtw89_assign_entity_chan(rtwdev, rtwvif_link->chanctx_idx, op_chan); 5380 rtw89_mac_enable_aps_bcn_by_chan(rtwdev, op_chan, true); 5381 ieee80211_wake_queues(rtwdev->hw); 5382 } else { 5383 rtw89_chan_create(&new, chan, chan, band, 5384 RTW89_CHANNEL_WIDTH_20); 5385 rtw89_assign_entity_chan(rtwdev, rtwvif_link->chanctx_idx, 5386 &new); 5387 rtw89_phy_nhm_trigger(rtwdev); 5388 } 5389 break; 5390 default: 5391 return; 5392 } 5393 } 5394 5395 static void 5396 rtw89_mac_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 5397 struct sk_buff *skb) 5398 { 5399 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 5400 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 5401 enum nl80211_cqm_rssi_threshold_event nl_event; 5402 const struct rtw89_c2h_mac_bcnfltr_rpt *c2h = 5403 (const struct rtw89_c2h_mac_bcnfltr_rpt *)skb->data; 5404 u8 type, event, mac_id; 5405 bool start_detect; 5406 s8 sig; 5407 5408 type = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_TYPE); 5409 sig = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_MA) - MAX_RSSI; 5410 event = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_EVENT); 5411 mac_id = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_MACID); 5412 5413 if (mac_id != rtwvif_link->mac_id) 5414 return; 5415 5416 rtw89_debug(rtwdev, RTW89_DBG_FW, 5417 "C2H bcnfltr rpt macid: %d, type: %d, ma: %d, event: %d\n", 5418 mac_id, type, sig, event); 5419 5420 switch (type) { 5421 case RTW89_BCN_FLTR_BEACON_LOSS: 5422 if (!rtwdev->scanning && !rtwvif->offchan && 5423 !rtwvif_link->noa_once.in_duration) { 5424 start_detect = rtw89_mcc_detect_go_bcn(rtwdev, rtwvif_link); 5425 if (start_detect) 5426 return; 5427 5428 ieee80211_beacon_loss(vif); 5429 } 5430 5431 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, rtwvif_link, true); 5432 return; 5433 case RTW89_BCN_FLTR_NOTIFY: 5434 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH; 5435 break; 5436 case RTW89_BCN_FLTR_RSSI: 5437 if (event == RTW89_BCN_FLTR_RSSI_LOW) 5438 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_LOW; 5439 else if (event == RTW89_BCN_FLTR_RSSI_HIGH) 5440 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH; 5441 else 5442 return; 5443 break; 5444 default: 5445 return; 5446 } 5447 5448 ieee80211_cqm_rssi_notify(vif, nl_event, sig, GFP_KERNEL); 5449 } 5450 5451 static void 5452 rtw89_mac_c2h_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 5453 u32 len) 5454 { 5455 struct rtw89_vif_link *rtwvif_link; 5456 struct rtw89_vif *rtwvif; 5457 unsigned int link_id; 5458 5459 rtw89_for_each_rtwvif(rtwdev, rtwvif) 5460 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 5461 rtw89_mac_bcn_fltr_rpt(rtwdev, rtwvif_link, c2h); 5462 } 5463 5464 static void 5465 rtw89_mac_c2h_rec_ack(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, u32 len) 5466 { 5467 /* N.B. This will run in interrupt context. */ 5468 const struct rtw89_c2h_rev_ack *c2h = (const void *)skb_c2h->data; 5469 5470 u8 h2c_cat = le32_get_bits(c2h->w2, RTW89_C2H_REV_ACK_W2_CAT); 5471 u8 h2c_class = le32_get_bits(c2h->w2, RTW89_C2H_REV_ACK_W2_CLASS); 5472 u8 h2c_func = le32_get_bits(c2h->w2, RTW89_C2H_REV_ACK_W2_FUNC); 5473 u8 h2c_seq = le32_get_bits(c2h->w2, RTW89_C2H_REV_ACK_W2_H2C_SEQ); 5474 struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info; 5475 5476 rtw89_debug(rtwdev, RTW89_DBG_FW, 5477 "C2H rev ack recv, cat: %d, class: %d, func: %d, seq : %d\n", 5478 h2c_cat, h2c_class, h2c_func, h2c_seq); 5479 5480 if (h2c_cat != H2C_CAT_MAC) 5481 return; 5482 5483 switch (h2c_class) { 5484 default: 5485 return; 5486 case H2C_CL_MAC_FW_OFLD: 5487 switch (h2c_func) { 5488 default: 5489 return; 5490 case H2C_FUNC_SCANOFLD: 5491 case H2C_FUNC_SCANOFLD_BE: 5492 scan_info->seq++; 5493 break; 5494 } 5495 5496 return; 5497 } 5498 } 5499 5500 static void 5501 rtw89_mac_c2h_done_ack(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, u32 len) 5502 { 5503 /* N.B. This will run in interrupt context. */ 5504 struct rtw89_wait_info *fw_ofld_wait = &rtwdev->mac.fw_ofld_wait; 5505 struct rtw89_wait_info *ps_wait = &rtwdev->mac.ps_wait; 5506 const struct rtw89_c2h_done_ack *c2h = 5507 (const struct rtw89_c2h_done_ack *)skb_c2h->data; 5508 u8 h2c_cat = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_CAT); 5509 u8 h2c_class = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_CLASS); 5510 u8 h2c_func = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_FUNC); 5511 u8 h2c_return = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_H2C_RETURN); 5512 u8 h2c_seq = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_H2C_SEQ); 5513 struct rtw89_completion_data data = {}; 5514 unsigned int cond; 5515 5516 rtw89_debug(rtwdev, RTW89_DBG_FW, 5517 "C2H done ack recv, cat: %d, class: %d, func: %d, ret: %d, seq : %d\n", 5518 h2c_cat, h2c_class, h2c_func, h2c_return, h2c_seq); 5519 5520 if (h2c_cat != H2C_CAT_MAC) 5521 return; 5522 5523 switch (h2c_class) { 5524 default: 5525 return; 5526 case H2C_CL_MAC_PS: 5527 switch (h2c_func) { 5528 default: 5529 return; 5530 case H2C_FUNC_IPS_CFG: 5531 cond = RTW89_PS_WAIT_COND_IPS_CFG; 5532 break; 5533 } 5534 5535 data.err = !!h2c_return; 5536 rtw89_complete_cond(ps_wait, cond, &data); 5537 return; 5538 case H2C_CL_MAC_FW_OFLD: 5539 switch (h2c_func) { 5540 default: 5541 return; 5542 case H2C_FUNC_ADD_SCANOFLD_CH: 5543 cond = RTW89_SCANOFLD_WAIT_COND_ADD_CH; 5544 h2c_return &= RTW89_C2H_SCAN_DONE_ACK_RETURN; 5545 break; 5546 case H2C_FUNC_SCANOFLD: 5547 cond = RTW89_SCANOFLD_WAIT_COND_START; 5548 break; 5549 case H2C_FUNC_SCANOFLD_BE: 5550 cond = RTW89_SCANOFLD_BE_WAIT_COND_START; 5551 h2c_return &= RTW89_C2H_SCAN_DONE_ACK_RETURN; 5552 break; 5553 case H2C_FUNC_TRX_PROTECT: 5554 cond = RTW89_FW_OFLD_WAIT_COND_TRX_PROTECT; 5555 break; 5556 } 5557 5558 data.err = !!h2c_return; 5559 rtw89_complete_cond(fw_ofld_wait, cond, &data); 5560 return; 5561 } 5562 } 5563 5564 static void 5565 rtw89_mac_c2h_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5566 { 5567 rtw89_fw_log_dump(rtwdev, c2h->data, len); 5568 } 5569 5570 static void 5571 rtw89_mac_c2h_bcn_cnt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5572 { 5573 } 5574 5575 static void 5576 rtw89_mac_c2h_bcn_upd_done(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, u32 len) 5577 { 5578 const struct rtw89_c2h_bcn_upd_done *c2h = 5579 (const struct rtw89_c2h_bcn_upd_done *)skb_c2h->data; 5580 u8 band, port, mbssid; 5581 5582 port = le32_get_bits(c2h->w2, RTW89_C2H_BCN_UPD_DONE_W2_PORT); 5583 mbssid = le32_get_bits(c2h->w2, RTW89_C2H_BCN_UPD_DONE_W2_MBSSID); 5584 band = le32_get_bits(c2h->w2, RTW89_C2H_BCN_UPD_DONE_W2_BAND_IDX); 5585 5586 rtw89_debug(rtwdev, RTW89_DBG_FW, 5587 "BCN update done on port:%d mbssid:%d band:%d\n", 5588 port, mbssid, band); 5589 } 5590 5591 static void 5592 rtw89_mac_c2h_pkt_ofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, 5593 u32 len) 5594 { 5595 struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait; 5596 const struct rtw89_c2h_pkt_ofld_rsp *c2h = 5597 (const struct rtw89_c2h_pkt_ofld_rsp *)skb_c2h->data; 5598 u16 pkt_len = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_LEN); 5599 u8 pkt_id = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_ID); 5600 u8 pkt_op = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_OP); 5601 struct rtw89_completion_data data = {}; 5602 unsigned int cond; 5603 5604 rtw89_debug(rtwdev, RTW89_DBG_FW, "pkt ofld rsp: id %d op %d len %d\n", 5605 pkt_id, pkt_op, pkt_len); 5606 5607 data.err = !pkt_len; 5608 cond = RTW89_FW_OFLD_WAIT_COND_PKT_OFLD(pkt_id, pkt_op); 5609 5610 rtw89_complete_cond(wait, cond, &data); 5611 } 5612 5613 static void 5614 rtw89_mac_c2h_bcn_resend(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5615 { 5616 } 5617 5618 static void 5619 rtw89_mac_c2h_tx_duty_rpt(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, u32 len) 5620 { 5621 struct rtw89_c2h_tx_duty_rpt *c2h = 5622 (struct rtw89_c2h_tx_duty_rpt *)skb_c2h->data; 5623 u8 err; 5624 5625 err = le32_get_bits(c2h->w2, RTW89_C2H_TX_DUTY_RPT_W2_TIMER_ERR); 5626 5627 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, "C2H TX duty rpt with err=%d\n", err); 5628 } 5629 5630 static void 5631 rtw89_mac_c2h_tsf32_toggle_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 5632 u32 len) 5633 { 5634 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_TSF32_TOGGLE_CHANGE); 5635 } 5636 5637 static void 5638 rtw89_mac_c2h_mcc_rcv_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5639 { 5640 u8 group = RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h->data); 5641 u8 func = RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h->data); 5642 5643 switch (func) { 5644 case H2C_FUNC_ADD_MCC: 5645 case H2C_FUNC_START_MCC: 5646 case H2C_FUNC_STOP_MCC: 5647 case H2C_FUNC_DEL_MCC_GROUP: 5648 case H2C_FUNC_RESET_MCC_GROUP: 5649 case H2C_FUNC_MCC_REQ_TSF: 5650 case H2C_FUNC_MCC_MACID_BITMAP: 5651 case H2C_FUNC_MCC_SYNC: 5652 case H2C_FUNC_MCC_SET_DURATION: 5653 break; 5654 default: 5655 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5656 "invalid MCC C2H RCV ACK: func %d\n", func); 5657 return; 5658 } 5659 5660 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5661 "MCC C2H RCV ACK: group %d, func %d\n", group, func); 5662 } 5663 5664 static void 5665 rtw89_mac_c2h_mcc_req_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5666 { 5667 u8 group = RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h->data); 5668 u8 func = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h->data); 5669 u8 retcode = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h->data); 5670 struct rtw89_completion_data data = {}; 5671 unsigned int cond; 5672 bool next = false; 5673 5674 switch (func) { 5675 case H2C_FUNC_MCC_REQ_TSF: 5676 next = true; 5677 break; 5678 case H2C_FUNC_MCC_MACID_BITMAP: 5679 case H2C_FUNC_MCC_SYNC: 5680 case H2C_FUNC_MCC_SET_DURATION: 5681 break; 5682 case H2C_FUNC_ADD_MCC: 5683 case H2C_FUNC_START_MCC: 5684 case H2C_FUNC_STOP_MCC: 5685 case H2C_FUNC_DEL_MCC_GROUP: 5686 case H2C_FUNC_RESET_MCC_GROUP: 5687 default: 5688 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5689 "invalid MCC C2H REQ ACK: func %d\n", func); 5690 return; 5691 } 5692 5693 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5694 "MCC C2H REQ ACK: group %d, func %d, return code %d\n", 5695 group, func, retcode); 5696 5697 if (!retcode && next) 5698 return; 5699 5700 data.err = !!retcode; 5701 cond = RTW89_MCC_WAIT_COND(group, func); 5702 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 5703 } 5704 5705 static void 5706 rtw89_mac_c2h_mcc_tsf_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5707 { 5708 u8 group = RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h->data); 5709 struct rtw89_completion_data data = {}; 5710 struct rtw89_mac_mcc_tsf_rpt *rpt; 5711 unsigned int cond; 5712 5713 rpt = (struct rtw89_mac_mcc_tsf_rpt *)data.buf; 5714 rpt->macid_x = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h->data); 5715 rpt->macid_y = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h->data); 5716 rpt->tsf_x_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h->data); 5717 rpt->tsf_x_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h->data); 5718 rpt->tsf_y_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h->data); 5719 rpt->tsf_y_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h->data); 5720 5721 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5722 "MCC C2H TSF RPT: macid %d> %llu, macid %d> %llu\n", 5723 rpt->macid_x, (u64)rpt->tsf_x_high << 32 | rpt->tsf_x_low, 5724 rpt->macid_y, (u64)rpt->tsf_y_high << 32 | rpt->tsf_y_low); 5725 5726 cond = RTW89_MCC_WAIT_COND(group, H2C_FUNC_MCC_REQ_TSF); 5727 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 5728 } 5729 5730 static void 5731 rtw89_mac_c2h_mcc_status_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5732 { 5733 u8 group = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h->data); 5734 u8 macid = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h->data); 5735 u8 status = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h->data); 5736 u32 tsf_low = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h->data); 5737 u32 tsf_high = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h->data); 5738 struct rtw89_completion_data data = {}; 5739 unsigned int cond; 5740 bool rsp = true; 5741 bool err; 5742 u8 func; 5743 5744 switch (status) { 5745 case RTW89_MAC_MCC_ADD_ROLE_OK: 5746 case RTW89_MAC_MCC_ADD_ROLE_FAIL: 5747 func = H2C_FUNC_ADD_MCC; 5748 err = status == RTW89_MAC_MCC_ADD_ROLE_FAIL; 5749 break; 5750 case RTW89_MAC_MCC_START_GROUP_OK: 5751 case RTW89_MAC_MCC_START_GROUP_FAIL: 5752 func = H2C_FUNC_START_MCC; 5753 err = status == RTW89_MAC_MCC_START_GROUP_FAIL; 5754 break; 5755 case RTW89_MAC_MCC_STOP_GROUP_OK: 5756 case RTW89_MAC_MCC_STOP_GROUP_FAIL: 5757 func = H2C_FUNC_STOP_MCC; 5758 err = status == RTW89_MAC_MCC_STOP_GROUP_FAIL; 5759 break; 5760 case RTW89_MAC_MCC_DEL_GROUP_OK: 5761 case RTW89_MAC_MCC_DEL_GROUP_FAIL: 5762 func = H2C_FUNC_DEL_MCC_GROUP; 5763 err = status == RTW89_MAC_MCC_DEL_GROUP_FAIL; 5764 break; 5765 case RTW89_MAC_MCC_RESET_GROUP_OK: 5766 case RTW89_MAC_MCC_RESET_GROUP_FAIL: 5767 func = H2C_FUNC_RESET_MCC_GROUP; 5768 err = status == RTW89_MAC_MCC_RESET_GROUP_FAIL; 5769 break; 5770 case RTW89_MAC_MCC_SWITCH_CH_OK: 5771 case RTW89_MAC_MCC_SWITCH_CH_FAIL: 5772 case RTW89_MAC_MCC_TXNULL0_OK: 5773 case RTW89_MAC_MCC_TXNULL0_FAIL: 5774 case RTW89_MAC_MCC_TXNULL1_OK: 5775 case RTW89_MAC_MCC_TXNULL1_FAIL: 5776 case RTW89_MAC_MCC_SWITCH_EARLY: 5777 case RTW89_MAC_MCC_TBTT: 5778 case RTW89_MAC_MCC_DURATION_START: 5779 case RTW89_MAC_MCC_DURATION_END: 5780 rsp = false; 5781 break; 5782 default: 5783 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5784 "invalid MCC C2H STS RPT: status %d\n", status); 5785 return; 5786 } 5787 5788 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5789 "MCC C2H STS RPT: group %d, macid %d, status %d, tsf %llu\n", 5790 group, macid, status, (u64)tsf_high << 32 | tsf_low); 5791 5792 if (!rsp) 5793 return; 5794 5795 data.err = err; 5796 cond = RTW89_MCC_WAIT_COND(group, func); 5797 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 5798 } 5799 5800 static void 5801 rtw89_mac_c2h_tx_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5802 { 5803 struct rtw89_tx_rpt *tx_rpt = &rtwdev->tx_rpt; 5804 struct rtw89_tx_skb_data *skb_data; 5805 u8 sw_define, tx_status, txcnt; 5806 struct sk_buff *skb; 5807 5808 if (rtwdev->chip->chip_id == RTL8922A) { 5809 const struct rtw89_c2h_mac_tx_rpt_v2 *rpt_v2; 5810 5811 rpt_v2 = (const struct rtw89_c2h_mac_tx_rpt_v2 *)c2h->data; 5812 sw_define = le32_get_bits(rpt_v2->w12, 5813 RTW89_C2H_MAC_TX_RPT_W12_SW_DEFINE_V2); 5814 tx_status = le32_get_bits(rpt_v2->w12, 5815 RTW89_C2H_MAC_TX_RPT_W12_TX_STATE_V2); 5816 txcnt = le32_get_bits(rpt_v2->w14, 5817 RTW89_C2H_MAC_TX_RPT_W14_DATA_TX_CNT_V2); 5818 } else { 5819 const struct rtw89_c2h_mac_tx_rpt *rpt; 5820 5821 rpt = (const struct rtw89_c2h_mac_tx_rpt *)c2h->data; 5822 sw_define = le32_get_bits(rpt->w2, RTW89_C2H_MAC_TX_RPT_W2_SW_DEFINE); 5823 tx_status = le32_get_bits(rpt->w2, RTW89_C2H_MAC_TX_RPT_W2_TX_STATE); 5824 if (rtwdev->chip->chip_id == RTL8852C) 5825 txcnt = le32_get_bits(rpt->w5, 5826 RTW89_C2H_MAC_TX_RPT_W5_DATA_TX_CNT_V1); 5827 else 5828 txcnt = le32_get_bits(rpt->w5, 5829 RTW89_C2H_MAC_TX_RPT_W5_DATA_TX_CNT); 5830 } 5831 5832 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 5833 "C2H TX RPT: sn %d, tx_status %d, txcnt %d\n", 5834 sw_define, tx_status, txcnt); 5835 5836 /* claim sw_define is not over size of tx_rpt->skbs[] */ 5837 static_assert(hweight32(RTW89_MAX_TX_RPTS_MASK) == 5838 hweight32(RTW89_C2H_MAC_TX_RPT_W12_SW_DEFINE_V2) && 5839 hweight32(RTW89_MAX_TX_RPTS_MASK) == 5840 hweight32(RTW89_C2H_MAC_TX_RPT_W2_SW_DEFINE)); 5841 5842 scoped_guard(spinlock_irqsave, &tx_rpt->skb_lock) { 5843 skb = tx_rpt->skbs[sw_define]; 5844 5845 /* skip if no skb (normally shouldn't happen) */ 5846 if (!skb) { 5847 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 5848 "C2H TX RPT: no skb found in queue\n"); 5849 return; 5850 } 5851 5852 skb_data = RTW89_TX_SKB_CB(skb); 5853 5854 /* skip if TX attempt has failed and retry limit has not been 5855 * reached yet 5856 */ 5857 if (tx_status != RTW89_TX_DONE && 5858 txcnt != skb_data->tx_pkt_cnt_lmt) 5859 return; 5860 5861 tx_rpt->skbs[sw_define] = NULL; 5862 rtw89_tx_rpt_tx_status(rtwdev, skb, tx_status); 5863 } 5864 } 5865 5866 static void 5867 rtw89_mac_c2h_mrc_tsf_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5868 { 5869 struct rtw89_wait_info *wait = &rtwdev->mcc.wait; 5870 const struct rtw89_c2h_mrc_tsf_rpt *c2h_rpt; 5871 struct rtw89_completion_data data = {}; 5872 struct rtw89_mac_mrc_tsf_rpt *rpt; 5873 unsigned int i; 5874 5875 c2h_rpt = (const struct rtw89_c2h_mrc_tsf_rpt *)c2h->data; 5876 rpt = (struct rtw89_mac_mrc_tsf_rpt *)data.buf; 5877 rpt->num = min_t(u8, RTW89_MAC_MRC_MAX_REQ_TSF_NUM, 5878 le32_get_bits(c2h_rpt->w2, 5879 RTW89_C2H_MRC_TSF_RPT_W2_REQ_TSF_NUM)); 5880 5881 for (i = 0; i < rpt->num; i++) { 5882 u32 tsf_high = le32_to_cpu(c2h_rpt->infos[i].tsf_high); 5883 u32 tsf_low = le32_to_cpu(c2h_rpt->infos[i].tsf_low); 5884 5885 rpt->tsfs[i] = (u64)tsf_high << 32 | tsf_low; 5886 5887 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5888 "MRC C2H TSF RPT: index %u> %llu\n", 5889 i, rpt->tsfs[i]); 5890 } 5891 5892 rtw89_complete_cond(wait, RTW89_MRC_WAIT_COND_REQ_TSF, &data); 5893 } 5894 5895 static void 5896 rtw89_mac_c2h_wow_aoac_rpt(struct rtw89_dev *rtwdev, struct sk_buff *skb, u32 len) 5897 { 5898 struct rtw89_wow_param *rtw_wow = &rtwdev->wow; 5899 struct rtw89_wow_aoac_report *aoac_rpt = &rtw_wow->aoac_rpt; 5900 struct rtw89_wait_info *wait = &rtw_wow->wait; 5901 const struct rtw89_c2h_wow_aoac_report *c2h = 5902 (const struct rtw89_c2h_wow_aoac_report *)skb->data; 5903 struct rtw89_completion_data data = {}; 5904 5905 if (skb->len < sizeof(*c2h)) { 5906 rtw89_warn(rtwdev, "wow: aoac rpt skb len %u is too short\n", 5907 skb->len); 5908 data.err = true; 5909 goto out; 5910 } 5911 5912 aoac_rpt->rpt_ver = c2h->rpt_ver; 5913 aoac_rpt->sec_type = c2h->sec_type; 5914 aoac_rpt->key_idx = c2h->key_idx; 5915 aoac_rpt->pattern_idx = c2h->pattern_idx; 5916 aoac_rpt->rekey_ok = u8_get_bits(c2h->rekey_ok, 5917 RTW89_C2H_WOW_AOAC_RPT_REKEY_IDX); 5918 memcpy(aoac_rpt->ptk_tx_iv, c2h->ptk_tx_iv, sizeof(aoac_rpt->ptk_tx_iv)); 5919 memcpy(aoac_rpt->eapol_key_replay_count, c2h->eapol_key_replay_count, 5920 sizeof(aoac_rpt->eapol_key_replay_count)); 5921 memcpy(aoac_rpt->gtk, c2h->gtk, sizeof(aoac_rpt->gtk)); 5922 memcpy(aoac_rpt->ptk_rx_iv, c2h->ptk_rx_iv, sizeof(aoac_rpt->ptk_rx_iv)); 5923 memcpy(aoac_rpt->gtk_rx_iv, c2h->gtk_rx_iv, sizeof(aoac_rpt->gtk_rx_iv)); 5924 aoac_rpt->igtk_key_id = le64_to_cpu(c2h->igtk_key_id); 5925 aoac_rpt->igtk_ipn = le64_to_cpu(c2h->igtk_ipn); 5926 memcpy(aoac_rpt->igtk, c2h->igtk, sizeof(aoac_rpt->igtk)); 5927 5928 out: 5929 rtw89_complete_cond(wait, RTW89_WOW_WAIT_COND_AOAC, &data); 5930 } 5931 5932 static void 5933 rtw89_mac_c2h_mlo_link_cfg_stat(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5934 { 5935 const struct rtw89_c2h_mlo_link_cfg_rpt *c2h_rpt; 5936 struct rtw89_wait_info *wait = &rtwdev->mlo.wait; 5937 struct rtw89_completion_data data = {}; 5938 unsigned int cond; 5939 u16 mac_id; 5940 u8 status; 5941 5942 c2h_rpt = (const struct rtw89_c2h_mlo_link_cfg_rpt *)c2h->data; 5943 5944 mac_id = le32_get_bits(c2h_rpt->w2, RTW89_C2H_MLO_LINK_CFG_RPT_W2_MACID); 5945 status = le32_get_bits(c2h_rpt->w2, RTW89_C2H_MLO_LINK_CFG_RPT_W2_STATUS); 5946 5947 data.err = status == RTW89_C2H_MLO_LINK_CFG_ROLE_NOT_EXIST || 5948 status == RTW89_C2H_MLO_LINK_CFG_RUNNING; 5949 cond = RTW89_MLO_WAIT_COND(mac_id, H2C_FUNC_MLO_LINK_CFG); 5950 rtw89_complete_cond(wait, cond, &data); 5951 } 5952 5953 static void 5954 rtw89_mac_c2h_mrc_status_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5955 { 5956 struct rtw89_wait_info *wait = &rtwdev->mcc.wait; 5957 const struct rtw89_c2h_mrc_status_rpt *c2h_rpt; 5958 struct rtw89_completion_data data = {}; 5959 enum rtw89_mac_mrc_status status; 5960 unsigned int cond; 5961 bool next = false; 5962 u32 tsf_high; 5963 u32 tsf_low; 5964 u8 sch_idx; 5965 u8 func; 5966 5967 c2h_rpt = (const struct rtw89_c2h_mrc_status_rpt *)c2h->data; 5968 sch_idx = le32_get_bits(c2h_rpt->w2, RTW89_C2H_MRC_STATUS_RPT_W2_SCH_IDX); 5969 status = le32_get_bits(c2h_rpt->w2, RTW89_C2H_MRC_STATUS_RPT_W2_STATUS); 5970 tsf_high = le32_to_cpu(c2h_rpt->tsf_high); 5971 tsf_low = le32_to_cpu(c2h_rpt->tsf_low); 5972 5973 switch (status) { 5974 case RTW89_MAC_MRC_START_SCH_OK: 5975 func = H2C_FUNC_START_MRC; 5976 break; 5977 case RTW89_MAC_MRC_STOP_SCH_OK: 5978 /* H2C_FUNC_DEL_MRC without STOP_ONLY, so wait for DEL_SCH_OK */ 5979 func = H2C_FUNC_DEL_MRC; 5980 next = true; 5981 break; 5982 case RTW89_MAC_MRC_DEL_SCH_OK: 5983 func = H2C_FUNC_DEL_MRC; 5984 break; 5985 case RTW89_MAC_MRC_EMPTY_SCH_FAIL: 5986 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5987 "MRC C2H STS RPT: empty sch fail\n"); 5988 return; 5989 case RTW89_MAC_MRC_ROLE_NOT_EXIST_FAIL: 5990 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5991 "MRC C2H STS RPT: role not exist fail\n"); 5992 return; 5993 case RTW89_MAC_MRC_DATA_NOT_FOUND_FAIL: 5994 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5995 "MRC C2H STS RPT: data not found fail\n"); 5996 return; 5997 case RTW89_MAC_MRC_GET_NEXT_SLOT_FAIL: 5998 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5999 "MRC C2H STS RPT: get next slot fail\n"); 6000 return; 6001 case RTW89_MAC_MRC_ALT_ROLE_FAIL: 6002 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 6003 "MRC C2H STS RPT: alt role fail\n"); 6004 return; 6005 case RTW89_MAC_MRC_ADD_PSTIMER_FAIL: 6006 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 6007 "MRC C2H STS RPT: add ps timer fail\n"); 6008 return; 6009 case RTW89_MAC_MRC_MALLOC_FAIL: 6010 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 6011 "MRC C2H STS RPT: malloc fail\n"); 6012 return; 6013 case RTW89_MAC_MRC_SWITCH_CH_FAIL: 6014 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 6015 "MRC C2H STS RPT: switch ch fail\n"); 6016 return; 6017 case RTW89_MAC_MRC_TXNULL0_FAIL: 6018 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 6019 "MRC C2H STS RPT: tx null-0 fail\n"); 6020 return; 6021 case RTW89_MAC_MRC_PORT_FUNC_EN_FAIL: 6022 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 6023 "MRC C2H STS RPT: port func en fail\n"); 6024 return; 6025 default: 6026 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 6027 "invalid MRC C2H STS RPT: status %d\n", status); 6028 return; 6029 } 6030 6031 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 6032 "MRC C2H STS RPT: sch_idx %d, status %d, tsf %llu\n", 6033 sch_idx, status, (u64)tsf_high << 32 | tsf_low); 6034 6035 if (next) 6036 return; 6037 6038 cond = RTW89_MRC_WAIT_COND(sch_idx, func); 6039 rtw89_complete_cond(wait, cond, &data); 6040 } 6041 6042 static void 6043 rtw89_mac_c2h_pwr_int_notify(struct rtw89_dev *rtwdev, struct sk_buff *skb, u32 len) 6044 { 6045 const struct rtw89_c2h_pwr_int_notify *c2h; 6046 struct rtw89_sta_link *rtwsta_link; 6047 struct ieee80211_sta *sta; 6048 struct rtw89_sta *rtwsta; 6049 u16 macid; 6050 bool ps; 6051 6052 c2h = (const struct rtw89_c2h_pwr_int_notify *)skb->data; 6053 macid = le32_get_bits(c2h->w2, RTW89_C2H_PWR_INT_NOTIFY_W2_MACID); 6054 ps = le32_get_bits(c2h->w2, RTW89_C2H_PWR_INT_NOTIFY_W2_PWR_STATUS); 6055 6056 rcu_read_lock(); 6057 6058 rtwsta_link = rtw89_assoc_link_rcu_dereference(rtwdev, macid); 6059 if (unlikely(!rtwsta_link)) 6060 goto out; 6061 6062 rtwsta = rtwsta_link->rtwsta; 6063 assign_bit(RTW89_REMOTE_STA_IN_PS, rtwsta->flags, ps); 6064 6065 sta = rtwsta_to_sta(rtwsta); 6066 ieee80211_sta_ps_transition(sta, ps); 6067 6068 out: 6069 rcu_read_unlock(); 6070 } 6071 6072 static 6073 void (* const rtw89_mac_c2h_ofld_handler[])(struct rtw89_dev *rtwdev, 6074 struct sk_buff *c2h, u32 len) = { 6075 [RTW89_MAC_C2H_FUNC_EFUSE_DUMP] = NULL, 6076 [RTW89_MAC_C2H_FUNC_READ_RSP] = NULL, 6077 [RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP] = rtw89_mac_c2h_pkt_ofld_rsp, 6078 [RTW89_MAC_C2H_FUNC_BCN_RESEND] = rtw89_mac_c2h_bcn_resend, 6079 [RTW89_MAC_C2H_FUNC_MACID_PAUSE] = rtw89_mac_c2h_macid_pause, 6080 [RTW89_MAC_C2H_FUNC_SCANOFLD_RSP] = rtw89_mac_c2h_scanofld_rsp, 6081 [RTW89_MAC_C2H_FUNC_TX_DUTY_RPT] = rtw89_mac_c2h_tx_duty_rpt, 6082 [RTW89_MAC_C2H_FUNC_TSF32_TOGL_RPT] = rtw89_mac_c2h_tsf32_toggle_rpt, 6083 [RTW89_MAC_C2H_FUNC_BCNFLTR_RPT] = rtw89_mac_c2h_bcn_fltr_rpt, 6084 }; 6085 6086 static 6087 void (* const rtw89_mac_c2h_info_handler[])(struct rtw89_dev *rtwdev, 6088 struct sk_buff *c2h, u32 len) = { 6089 [RTW89_MAC_C2H_FUNC_REC_ACK] = rtw89_mac_c2h_rec_ack, 6090 [RTW89_MAC_C2H_FUNC_DONE_ACK] = rtw89_mac_c2h_done_ack, 6091 [RTW89_MAC_C2H_FUNC_C2H_LOG] = rtw89_mac_c2h_log, 6092 [RTW89_MAC_C2H_FUNC_BCN_CNT] = rtw89_mac_c2h_bcn_cnt, 6093 [RTW89_MAC_C2H_FUNC_BCN_UPD_DONE] = rtw89_mac_c2h_bcn_upd_done, 6094 }; 6095 6096 static 6097 void (* const rtw89_mac_c2h_mcc_handler[])(struct rtw89_dev *rtwdev, 6098 struct sk_buff *c2h, u32 len) = { 6099 [RTW89_MAC_C2H_FUNC_MCC_RCV_ACK] = rtw89_mac_c2h_mcc_rcv_ack, 6100 [RTW89_MAC_C2H_FUNC_MCC_REQ_ACK] = rtw89_mac_c2h_mcc_req_ack, 6101 [RTW89_MAC_C2H_FUNC_MCC_TSF_RPT] = rtw89_mac_c2h_mcc_tsf_rpt, 6102 [RTW89_MAC_C2H_FUNC_MCC_STATUS_RPT] = rtw89_mac_c2h_mcc_status_rpt, 6103 }; 6104 6105 static 6106 void (* const rtw89_mac_c2h_misc_handler[])(struct rtw89_dev *rtwdev, 6107 struct sk_buff *c2h, u32 len) = { 6108 [RTW89_MAC_C2H_FUNC_TX_REPORT] = rtw89_mac_c2h_tx_rpt, 6109 }; 6110 6111 static 6112 void (* const rtw89_mac_c2h_mlo_handler[])(struct rtw89_dev *rtwdev, 6113 struct sk_buff *c2h, u32 len) = { 6114 [RTW89_MAC_C2H_FUNC_MLO_GET_TBL] = NULL, 6115 [RTW89_MAC_C2H_FUNC_MLO_EMLSR_TRANS_DONE] = NULL, 6116 [RTW89_MAC_C2H_FUNC_MLO_EMLSR_STA_CFG_DONE] = NULL, 6117 [RTW89_MAC_C2H_FUNC_MCMLO_RELINK_RPT] = NULL, 6118 [RTW89_MAC_C2H_FUNC_MCMLO_SN_SYNC_RPT] = NULL, 6119 [RTW89_MAC_C2H_FUNC_MLO_LINK_CFG_STAT] = rtw89_mac_c2h_mlo_link_cfg_stat, 6120 [RTW89_MAC_C2H_FUNC_MLO_DM_DBG_DUMP] = NULL, 6121 }; 6122 6123 static 6124 void (* const rtw89_mac_c2h_mrc_handler[])(struct rtw89_dev *rtwdev, 6125 struct sk_buff *c2h, u32 len) = { 6126 [RTW89_MAC_C2H_FUNC_MRC_TSF_RPT] = rtw89_mac_c2h_mrc_tsf_rpt, 6127 [RTW89_MAC_C2H_FUNC_MRC_STATUS_RPT] = rtw89_mac_c2h_mrc_status_rpt, 6128 }; 6129 6130 static 6131 void (* const rtw89_mac_c2h_wow_handler[])(struct rtw89_dev *rtwdev, 6132 struct sk_buff *c2h, u32 len) = { 6133 [RTW89_MAC_C2H_FUNC_AOAC_REPORT] = rtw89_mac_c2h_wow_aoac_rpt, 6134 }; 6135 6136 static 6137 void (* const rtw89_mac_c2h_ap_handler[])(struct rtw89_dev *rtwdev, 6138 struct sk_buff *c2h, u32 len) = { 6139 [RTW89_MAC_C2H_FUNC_PWR_INT_NOTIFY] = rtw89_mac_c2h_pwr_int_notify, 6140 }; 6141 6142 static void rtw89_mac_c2h_scanofld_rsp_atomic(struct rtw89_dev *rtwdev, 6143 struct sk_buff *skb) 6144 { 6145 const struct rtw89_c2h_scanofld *c2h = 6146 (const struct rtw89_c2h_scanofld *)skb->data; 6147 struct rtw89_wait_info *fw_ofld_wait = &rtwdev->mac.fw_ofld_wait; 6148 struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info; 6149 struct rtw89_fw_c2h_attr *attr = RTW89_SKB_C2H_CB(skb); 6150 struct rtw89_completion_data data = {}; 6151 unsigned int cond; 6152 u8 status, reason; 6153 6154 attr->is_scan_event = 1; 6155 attr->scan_seq = scan_info->seq; 6156 6157 status = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_STATUS); 6158 reason = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_RSN); 6159 data.err = status != RTW89_SCAN_STATUS_SUCCESS; 6160 6161 if (reason == RTW89_SCAN_END_SCAN_NOTIFY) { 6162 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 6163 cond = RTW89_SCANOFLD_BE_WAIT_COND_STOP; 6164 else 6165 cond = RTW89_SCANOFLD_WAIT_COND_STOP; 6166 6167 rtw89_complete_cond(fw_ofld_wait, cond, &data); 6168 } 6169 } 6170 6171 bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 6172 u8 class, u8 func) 6173 { 6174 switch (class) { 6175 default: 6176 return false; 6177 case RTW89_MAC_C2H_CLASS_INFO: 6178 switch (func) { 6179 default: 6180 return false; 6181 case RTW89_MAC_C2H_FUNC_REC_ACK: 6182 case RTW89_MAC_C2H_FUNC_DONE_ACK: 6183 return true; 6184 } 6185 case RTW89_MAC_C2H_CLASS_OFLD: 6186 switch (func) { 6187 default: 6188 return false; 6189 case RTW89_MAC_C2H_FUNC_SCANOFLD_RSP: 6190 rtw89_mac_c2h_scanofld_rsp_atomic(rtwdev, c2h); 6191 return false; 6192 case RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP: 6193 return true; 6194 } 6195 case RTW89_MAC_C2H_CLASS_MCC: 6196 return true; 6197 case RTW89_MAC_C2H_CLASS_MISC: 6198 return true; 6199 case RTW89_MAC_C2H_CLASS_MLO: 6200 return true; 6201 case RTW89_MAC_C2H_CLASS_MRC: 6202 return true; 6203 case RTW89_MAC_C2H_CLASS_WOW: 6204 return true; 6205 case RTW89_MAC_C2H_CLASS_AP: 6206 switch (func) { 6207 default: 6208 return false; 6209 case RTW89_MAC_C2H_FUNC_PWR_INT_NOTIFY: 6210 return true; 6211 } 6212 } 6213 } 6214 6215 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 6216 u32 len, u8 class, u8 func) 6217 { 6218 void (*handler)(struct rtw89_dev *rtwdev, 6219 struct sk_buff *c2h, u32 len) = NULL; 6220 6221 switch (class) { 6222 case RTW89_MAC_C2H_CLASS_INFO: 6223 if (func < RTW89_MAC_C2H_FUNC_INFO_MAX) 6224 handler = rtw89_mac_c2h_info_handler[func]; 6225 break; 6226 case RTW89_MAC_C2H_CLASS_OFLD: 6227 if (func < RTW89_MAC_C2H_FUNC_OFLD_MAX) 6228 handler = rtw89_mac_c2h_ofld_handler[func]; 6229 break; 6230 case RTW89_MAC_C2H_CLASS_MCC: 6231 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MCC) 6232 handler = rtw89_mac_c2h_mcc_handler[func]; 6233 break; 6234 case RTW89_MAC_C2H_CLASS_MISC: 6235 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MISC) 6236 handler = rtw89_mac_c2h_misc_handler[func]; 6237 break; 6238 case RTW89_MAC_C2H_CLASS_MLO: 6239 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MLO) 6240 handler = rtw89_mac_c2h_mlo_handler[func]; 6241 break; 6242 case RTW89_MAC_C2H_CLASS_MRC: 6243 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MRC) 6244 handler = rtw89_mac_c2h_mrc_handler[func]; 6245 break; 6246 case RTW89_MAC_C2H_CLASS_WOW: 6247 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_WOW) 6248 handler = rtw89_mac_c2h_wow_handler[func]; 6249 break; 6250 case RTW89_MAC_C2H_CLASS_AP: 6251 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_AP) 6252 handler = rtw89_mac_c2h_ap_handler[func]; 6253 break; 6254 case RTW89_MAC_C2H_CLASS_FWDBG: 6255 case RTW89_MAC_C2H_CLASS_ROLE: 6256 return; 6257 default: 6258 break; 6259 } 6260 if (!handler) { 6261 rtw89_info_once(rtwdev, "MAC c2h class %d func %d not support\n", 6262 class, func); 6263 return; 6264 } 6265 handler(rtwdev, skb, len); 6266 } 6267 6268 static 6269 bool rtw89_mac_get_txpwr_cr_ax(struct rtw89_dev *rtwdev, 6270 enum rtw89_phy_idx phy_idx, 6271 u32 reg_base, u32 *cr) 6272 { 6273 enum rtw89_qta_mode mode = rtwdev->mac.qta_mode; 6274 u32 addr = rtw89_mac_reg_by_idx(rtwdev, reg_base, phy_idx); 6275 6276 if (addr < R_AX_PWR_RATE_CTRL || addr > CMAC1_END_ADDR_AX) { 6277 rtw89_err(rtwdev, "[TXPWR] addr=0x%x exceed txpwr cr\n", 6278 addr); 6279 goto error; 6280 } 6281 6282 if (addr >= CMAC1_START_ADDR_AX && addr <= CMAC1_END_ADDR_AX) 6283 if (mode == RTW89_QTA_SCC) { 6284 rtw89_err(rtwdev, 6285 "[TXPWR] addr=0x%x but hw not enable\n", 6286 addr); 6287 goto error; 6288 } 6289 6290 *cr = addr; 6291 return true; 6292 6293 error: 6294 rtw89_err(rtwdev, "[TXPWR] check txpwr cr 0x%x(phy%d) fail\n", 6295 addr, phy_idx); 6296 6297 return false; 6298 } 6299 6300 static 6301 int rtw89_mac_cfg_ppdu_status_ax(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable) 6302 { 6303 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PPDU_STAT, mac_idx); 6304 int ret; 6305 6306 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6307 if (ret) 6308 return ret; 6309 6310 if (!enable) { 6311 rtw89_write32_clr(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN); 6312 return 0; 6313 } 6314 6315 rtw89_write32(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN | 6316 B_AX_APP_MAC_INFO_RPT | 6317 B_AX_APP_PLCP_HDR_RPT | 6318 B_AX_PPDU_STAT_RPT_CRC32); 6319 rtw89_write32_mask(rtwdev, R_AX_HW_RPT_FWD, B_AX_FWD_PPDU_STAT_MASK, 6320 RTW89_PRPT_DEST_HOST); 6321 6322 return 0; 6323 } 6324 6325 static 6326 void __rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx) 6327 { 6328 #define MAC_AX_TIME_TH_SH 5 6329 #define MAC_AX_LEN_TH_SH 4 6330 #define MAC_AX_TIME_TH_MAX 255 6331 #define MAC_AX_LEN_TH_MAX 255 6332 #define MAC_AX_TIME_TH_DEF 88 6333 #define MAC_AX_LEN_TH_DEF 4080 6334 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6335 struct ieee80211_hw *hw = rtwdev->hw; 6336 u32 rts_threshold = hw->wiphy->rts_threshold; 6337 u32 time_th, len_th; 6338 u32 reg; 6339 6340 if (rts_threshold == (u32)-1) { 6341 time_th = MAC_AX_TIME_TH_DEF; 6342 len_th = MAC_AX_LEN_TH_DEF; 6343 } else { 6344 time_th = MAC_AX_TIME_TH_MAX << MAC_AX_TIME_TH_SH; 6345 len_th = rts_threshold; 6346 } 6347 6348 time_th = min_t(u32, time_th >> MAC_AX_TIME_TH_SH, MAC_AX_TIME_TH_MAX); 6349 len_th = min_t(u32, len_th >> MAC_AX_LEN_TH_SH, MAC_AX_LEN_TH_MAX); 6350 6351 reg = rtw89_mac_reg_by_idx(rtwdev, mac->agg_len_ht, mac_idx); 6352 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_TXTIME_TH_MASK, time_th); 6353 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_LEN_TH_MASK, len_th); 6354 } 6355 6356 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev) 6357 { 6358 __rtw89_mac_update_rts_threshold(rtwdev, RTW89_MAC_0); 6359 if (rtwdev->dbcc_en) 6360 __rtw89_mac_update_rts_threshold(rtwdev, RTW89_MAC_1); 6361 } 6362 6363 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop) 6364 { 6365 bool empty; 6366 int ret; 6367 6368 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 6369 return; 6370 6371 ret = read_poll_timeout(dle_is_txq_empty, empty, empty, 6372 10000, 200000, false, rtwdev); 6373 if (ret && !drop && (rtwdev->total_sta_assoc || rtwdev->scanning)) 6374 rtw89_info(rtwdev, "timed out to flush queues\n"); 6375 } 6376 6377 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex) 6378 { 6379 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 6380 u8 val; 6381 u16 val16; 6382 u32 val32; 6383 int ret; 6384 6385 rtw89_write8_set(rtwdev, R_AX_GPIO_MUXCFG, B_AX_ENBT); 6386 if (chip_id != RTL8851B && chip_id != RTL8852BT) 6387 rtw89_write8_set(rtwdev, R_AX_BTC_FUNC_EN, B_AX_PTA_WL_TX_EN); 6388 rtw89_write8_set(rtwdev, R_AX_BT_COEX_CFG_2 + 1, B_AX_GNT_BT_POLARITY >> 8); 6389 rtw89_write8_set(rtwdev, R_AX_CSR_MODE, B_AX_STATIS_BT_EN | B_AX_WL_ACT_MSK); 6390 rtw89_write8_set(rtwdev, R_AX_CSR_MODE + 2, B_AX_BT_CNT_RST >> 16); 6391 if (chip_id != RTL8851B && chip_id != RTL8852BT) 6392 rtw89_write8_clr(rtwdev, R_AX_TRXPTCL_RESP_0 + 3, B_AX_RSP_CHK_BTCCA >> 24); 6393 6394 val16 = rtw89_read16(rtwdev, R_AX_CCA_CFG_0); 6395 val16 = (val16 | B_AX_BTCCA_EN) & ~B_AX_BTCCA_BRK_TXOP_EN; 6396 rtw89_write16(rtwdev, R_AX_CCA_CFG_0, val16); 6397 6398 ret = rtw89_mac_read_lte(rtwdev, R_AX_LTE_SW_CFG_2, &val32); 6399 if (ret) { 6400 if (!test_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags)) 6401 rtw89_err(rtwdev, "Read R_AX_LTE_SW_CFG_2 fail!\n"); 6402 return ret; 6403 } 6404 val32 = val32 & B_AX_WL_RX_CTRL; 6405 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_2, val32); 6406 if (ret) { 6407 if (!test_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags)) 6408 rtw89_err(rtwdev, "Write R_AX_LTE_SW_CFG_2 fail!\n"); 6409 return ret; 6410 } 6411 6412 switch (coex->pta_mode) { 6413 case RTW89_MAC_AX_COEX_RTK_MODE: 6414 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 6415 val &= ~B_AX_BTMODE_MASK; 6416 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_0_3); 6417 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 6418 6419 val = rtw89_read8(rtwdev, R_AX_TDMA_MODE); 6420 rtw89_write8(rtwdev, R_AX_TDMA_MODE, val | B_AX_RTK_BT_ENABLE); 6421 6422 val = rtw89_read8(rtwdev, R_AX_BT_COEX_CFG_5); 6423 val &= ~B_AX_BT_RPT_SAMPLE_RATE_MASK; 6424 val |= FIELD_PREP(B_AX_BT_RPT_SAMPLE_RATE_MASK, MAC_AX_RTK_RATE); 6425 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_5, val); 6426 break; 6427 case RTW89_MAC_AX_COEX_CSR_MODE: 6428 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 6429 val &= ~B_AX_BTMODE_MASK; 6430 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_2); 6431 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 6432 6433 val16 = rtw89_read16(rtwdev, R_AX_CSR_MODE); 6434 val16 &= ~B_AX_BT_PRI_DETECT_TO_MASK; 6435 val16 |= FIELD_PREP(B_AX_BT_PRI_DETECT_TO_MASK, MAC_AX_CSR_PRI_TO); 6436 val16 &= ~B_AX_BT_TRX_INIT_DETECT_MASK; 6437 val16 |= FIELD_PREP(B_AX_BT_TRX_INIT_DETECT_MASK, MAC_AX_CSR_TRX_TO); 6438 val16 &= ~B_AX_BT_STAT_DELAY_MASK; 6439 val16 |= FIELD_PREP(B_AX_BT_STAT_DELAY_MASK, MAC_AX_CSR_DELAY); 6440 val16 |= B_AX_ENHANCED_BT; 6441 rtw89_write16(rtwdev, R_AX_CSR_MODE, val16); 6442 6443 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_2, MAC_AX_CSR_RATE); 6444 break; 6445 default: 6446 return -EINVAL; 6447 } 6448 6449 switch (coex->direction) { 6450 case RTW89_MAC_AX_COEX_INNER: 6451 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 6452 val = (val & ~BIT(2)) | BIT(1); 6453 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 6454 break; 6455 case RTW89_MAC_AX_COEX_OUTPUT: 6456 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 6457 val = val | BIT(1) | BIT(0); 6458 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 6459 break; 6460 case RTW89_MAC_AX_COEX_INPUT: 6461 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 6462 val = val & ~(BIT(2) | BIT(1)); 6463 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 6464 break; 6465 default: 6466 return -EINVAL; 6467 } 6468 6469 return 0; 6470 } 6471 EXPORT_SYMBOL(rtw89_mac_coex_init); 6472 6473 int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev, 6474 const struct rtw89_mac_ax_coex *coex) 6475 { 6476 rtw89_write32_set(rtwdev, R_AX_BTC_CFG, 6477 B_AX_BTC_EN | B_AX_BTG_LNA1_GAIN_SEL); 6478 rtw89_write32_set(rtwdev, R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN); 6479 rtw89_write16_set(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_EN); 6480 rtw89_write16_clr(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_BRK_TXOP_EN); 6481 6482 switch (coex->pta_mode) { 6483 case RTW89_MAC_AX_COEX_RTK_MODE: 6484 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 6485 MAC_AX_RTK_MODE); 6486 rtw89_write32_mask(rtwdev, R_AX_RTK_MODE_CFG_V1, 6487 B_AX_SAMPLE_CLK_MASK, MAC_AX_RTK_RATE); 6488 break; 6489 case RTW89_MAC_AX_COEX_CSR_MODE: 6490 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 6491 MAC_AX_CSR_MODE); 6492 break; 6493 default: 6494 return -EINVAL; 6495 } 6496 6497 return 0; 6498 } 6499 EXPORT_SYMBOL(rtw89_mac_coex_init_v1); 6500 6501 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev, 6502 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 6503 { 6504 u32 val = 0, ret; 6505 6506 if (gnt_cfg->band[0].gnt_bt) 6507 val |= B_AX_GNT_BT_RFC_S0_SW_VAL | B_AX_GNT_BT_BB_S0_SW_VAL; 6508 6509 if (gnt_cfg->band[0].gnt_bt_sw_en) 6510 val |= B_AX_GNT_BT_RFC_S0_SW_CTRL | B_AX_GNT_BT_BB_S0_SW_CTRL; 6511 6512 if (gnt_cfg->band[0].gnt_wl) 6513 val |= B_AX_GNT_WL_RFC_S0_SW_VAL | B_AX_GNT_WL_BB_S0_SW_VAL; 6514 6515 if (gnt_cfg->band[0].gnt_wl_sw_en) 6516 val |= B_AX_GNT_WL_RFC_S0_SW_CTRL | B_AX_GNT_WL_BB_S0_SW_CTRL; 6517 6518 if (gnt_cfg->band[1].gnt_bt) 6519 val |= B_AX_GNT_BT_RFC_S1_SW_VAL | B_AX_GNT_BT_BB_S1_SW_VAL; 6520 6521 if (gnt_cfg->band[1].gnt_bt_sw_en) 6522 val |= B_AX_GNT_BT_RFC_S1_SW_CTRL | B_AX_GNT_BT_BB_S1_SW_CTRL; 6523 6524 if (gnt_cfg->band[1].gnt_wl) 6525 val |= B_AX_GNT_WL_RFC_S1_SW_VAL | B_AX_GNT_WL_BB_S1_SW_VAL; 6526 6527 if (gnt_cfg->band[1].gnt_wl_sw_en) 6528 val |= B_AX_GNT_WL_RFC_S1_SW_CTRL | B_AX_GNT_WL_BB_S1_SW_CTRL; 6529 6530 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_1, val); 6531 if (ret) { 6532 if (!test_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags)) 6533 rtw89_err(rtwdev, "Write LTE fail!\n"); 6534 return ret; 6535 } 6536 6537 return 0; 6538 } 6539 EXPORT_SYMBOL(rtw89_mac_cfg_gnt); 6540 6541 int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev, 6542 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 6543 { 6544 u32 val = 0; 6545 6546 if (gnt_cfg->band[0].gnt_bt) 6547 val |= B_AX_GNT_BT_RFC_S0_VAL | B_AX_GNT_BT_RX_VAL | 6548 B_AX_GNT_BT_TX_VAL; 6549 6550 if (gnt_cfg->band[0].gnt_bt_sw_en) 6551 val |= B_AX_GNT_BT_RFC_S0_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 6552 B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 6553 6554 if (gnt_cfg->band[0].gnt_wl) 6555 val |= B_AX_GNT_WL_RFC_S0_VAL | B_AX_GNT_WL_RX_VAL | 6556 B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 6557 6558 if (gnt_cfg->band[0].gnt_wl_sw_en) 6559 val |= B_AX_GNT_WL_RFC_S0_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 6560 B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 6561 6562 if (gnt_cfg->band[1].gnt_bt) 6563 val |= B_AX_GNT_BT_RFC_S1_VAL | B_AX_GNT_BT_RX_VAL | 6564 B_AX_GNT_BT_TX_VAL; 6565 6566 if (gnt_cfg->band[1].gnt_bt_sw_en) 6567 val |= B_AX_GNT_BT_RFC_S1_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 6568 B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 6569 6570 if (gnt_cfg->band[1].gnt_wl) 6571 val |= B_AX_GNT_WL_RFC_S1_VAL | B_AX_GNT_WL_RX_VAL | 6572 B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 6573 6574 if (gnt_cfg->band[1].gnt_wl_sw_en) 6575 val |= B_AX_GNT_WL_RFC_S1_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 6576 B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 6577 6578 if (gnt_cfg->bt[0].wlan_act_en) 6579 val |= B_AX_WL_ACT_SWCTRL; 6580 if (gnt_cfg->bt[0].wlan_act) 6581 val |= B_AX_WL_ACT_VAL; 6582 if (gnt_cfg->bt[1].wlan_act_en) 6583 val |= B_AX_WL_ACT2_SWCTRL; 6584 if (gnt_cfg->bt[1].wlan_act) 6585 val |= B_AX_WL_ACT2_VAL; 6586 6587 rtw89_write32(rtwdev, R_AX_GNT_SW_CTRL, val); 6588 6589 return 0; 6590 } 6591 EXPORT_SYMBOL(rtw89_mac_cfg_gnt_v1); 6592 6593 static 6594 int rtw89_mac_cfg_plt_ax(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt) 6595 { 6596 u32 reg; 6597 u16 val; 6598 int ret; 6599 6600 ret = rtw89_mac_check_mac_en(rtwdev, plt->band, RTW89_CMAC_SEL); 6601 if (ret) 6602 return ret; 6603 6604 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BT_PLT, plt->band); 6605 val = (plt->tx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_TX_PLT_GNT_LTE_RX : 0) | 6606 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_TX_PLT_GNT_BT_TX : 0) | 6607 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_TX_PLT_GNT_BT_RX : 0) | 6608 (plt->tx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_TX_PLT_GNT_WL : 0) | 6609 (plt->rx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_RX_PLT_GNT_LTE_RX : 0) | 6610 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_RX_PLT_GNT_BT_TX : 0) | 6611 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_RX_PLT_GNT_BT_RX : 0) | 6612 (plt->rx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_RX_PLT_GNT_WL : 0) | 6613 B_AX_PLT_EN; 6614 rtw89_write16(rtwdev, reg, val); 6615 6616 return 0; 6617 } 6618 6619 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val) 6620 { 6621 const struct rtw89_chip_info *chip = rtwdev->chip; 6622 u32 reg = chip->btc_sb.n[0].cfg; 6623 u32 fw_sb; 6624 6625 fw_sb = rtw89_read32(rtwdev, reg); 6626 fw_sb = FIELD_GET(B_MAC_AX_SB_FW_MASK, fw_sb); 6627 fw_sb = fw_sb & ~B_MAC_AX_BTGS1_NOTIFY; 6628 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 6629 fw_sb = fw_sb | MAC_AX_NOTIFY_PWR_MAJOR; 6630 else 6631 fw_sb = fw_sb | MAC_AX_NOTIFY_TP_MAJOR; 6632 val = FIELD_GET(B_MAC_AX_SB_DRV_MASK, val); 6633 val = B_AX_TOGGLE | 6634 FIELD_PREP(B_MAC_AX_SB_DRV_MASK, val) | 6635 FIELD_PREP(B_MAC_AX_SB_FW_MASK, fw_sb); 6636 rtw89_write32(rtwdev, reg, val); 6637 fsleep(1000); /* avoid BT FW loss information */ 6638 } 6639 6640 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev) 6641 { 6642 const struct rtw89_chip_info *chip = rtwdev->chip; 6643 u32 reg = chip->btc_sb.n[0].get; 6644 6645 return rtw89_read32(rtwdev, reg); 6646 } 6647 6648 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 6649 { 6650 u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3); 6651 6652 val = wl ? val | BIT(2) : val & ~BIT(2); 6653 rtw89_write8(rtwdev, R_AX_SYS_SDIO_CTRL + 3, val); 6654 6655 return 0; 6656 } 6657 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path); 6658 6659 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl) 6660 { 6661 struct rtw89_mac_ax_coex_gnt gnt = {}; 6662 int i; 6663 6664 if (wl) 6665 return 0; 6666 6667 for (i = 0; i < RTW89_PHY_NUM; i++) { 6668 gnt.band[i].gnt_bt_sw_en = 1; 6669 gnt.band[i].gnt_bt = 1; 6670 gnt.band[i].gnt_wl_sw_en = 1; 6671 gnt.band[i].gnt_wl = 0; 6672 } 6673 6674 return rtw89_mac_cfg_gnt_v1(rtwdev, &gnt); 6675 } 6676 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path_v1); 6677 6678 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev) 6679 { 6680 const struct rtw89_chip_info *chip = rtwdev->chip; 6681 u8 val = 0; 6682 6683 if (chip->chip_id == RTL8852C || chip->chip_id == RTL8922A) 6684 return false; 6685 else if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) 6686 val = rtw89_read8_mask(rtwdev, R_AX_SYS_SDIO_CTRL + 3, 6687 B_AX_LTE_MUX_CTRL_PATH >> 24); 6688 6689 return !!val; 6690 } 6691 6692 static u16 rtw89_mac_get_plt_cnt_ax(struct rtw89_dev *rtwdev, u8 band) 6693 { 6694 u32 reg; 6695 u16 cnt; 6696 6697 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BT_PLT, band); 6698 cnt = rtw89_read32_mask(rtwdev, reg, B_AX_BT_PLT_PKT_CNT_MASK); 6699 rtw89_write16_set(rtwdev, reg, B_AX_BT_PLT_RST); 6700 6701 return cnt; 6702 } 6703 6704 static void rtw89_mac_bfee_standby_timer(struct rtw89_dev *rtwdev, u8 mac_idx, 6705 bool keep) 6706 { 6707 u32 reg; 6708 6709 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 6710 return; 6711 6712 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee standby_timer to %d\n", keep); 6713 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx); 6714 if (keep) { 6715 set_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 6716 rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, 6717 BFRP_RX_STANDBY_TIMER_KEEP); 6718 } else { 6719 clear_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 6720 rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, 6721 BFRP_RX_STANDBY_TIMER_RELEASE); 6722 } 6723 } 6724 6725 void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 6726 { 6727 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6728 u32 reg; 6729 u32 mask = mac->bfee_ctrl.mask; 6730 6731 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee ndpa_en to %d\n", en); 6732 reg = rtw89_mac_reg_by_idx(rtwdev, mac->bfee_ctrl.addr, mac_idx); 6733 if (en) { 6734 set_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 6735 rtw89_write32_set(rtwdev, reg, mask); 6736 } else { 6737 clear_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 6738 rtw89_write32_clr(rtwdev, reg, mask); 6739 } 6740 } 6741 6742 static int rtw89_mac_init_bfee_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 6743 { 6744 u32 reg; 6745 u32 val32; 6746 int ret; 6747 6748 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6749 if (ret) 6750 return ret; 6751 6752 /* AP mode set tx gid to 63 */ 6753 /* STA mode set tx gid to 0(default) */ 6754 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMER_CTRL_0, mac_idx); 6755 rtw89_write32_set(rtwdev, reg, B_AX_BFMER_NDP_BFEN); 6756 6757 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx); 6758 rtw89_write32(rtwdev, reg, CSI_RRSC_BMAP); 6759 6760 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx); 6761 val32 = FIELD_PREP(B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK, NDP_RX_STANDBY_TIMER); 6762 rtw89_write32(rtwdev, reg, val32); 6763 rtw89_mac_bfee_standby_timer(rtwdev, mac_idx, true); 6764 rtw89_mac_bfee_ctrl(rtwdev, mac_idx, true); 6765 6766 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 6767 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL | 6768 B_AX_BFMEE_USE_NSTS | 6769 B_AX_BFMEE_CSI_GID_SEL | 6770 B_AX_BFMEE_CSI_FORCE_RETE_EN); 6771 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RATE, mac_idx); 6772 rtw89_write32(rtwdev, reg, 6773 u32_encode_bits(CSI_INIT_RATE_HT, B_AX_BFMEE_HT_CSI_RATE_MASK) | 6774 u32_encode_bits(CSI_INIT_RATE_VHT, B_AX_BFMEE_VHT_CSI_RATE_MASK) | 6775 u32_encode_bits(CSI_INIT_RATE_HE, B_AX_BFMEE_HE_CSI_RATE_MASK)); 6776 6777 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CSIRPT_OPTION, mac_idx); 6778 rtw89_write32_set(rtwdev, reg, 6779 B_AX_CSIPRT_VHTSU_AID_EN | B_AX_CSIPRT_HESU_AID_EN); 6780 6781 return 0; 6782 } 6783 6784 static int rtw89_mac_set_csi_para_reg_ax(struct rtw89_dev *rtwdev, 6785 struct rtw89_vif_link *rtwvif_link, 6786 struct rtw89_sta_link *rtwsta_link) 6787 { 6788 u8 nc = 1, nr = 3, ng = 0, cb = 1, cs = 1, ldpc_en = 1, stbc_en = 1; 6789 struct ieee80211_link_sta *link_sta; 6790 u8 mac_idx = rtwvif_link->mac_idx; 6791 u8 port_sel = rtwvif_link->port; 6792 u8 sound_dim = 3, t; 6793 u8 *phy_cap; 6794 u32 reg; 6795 u16 val; 6796 int ret; 6797 6798 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6799 if (ret) 6800 return ret; 6801 6802 rcu_read_lock(); 6803 6804 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 6805 phy_cap = link_sta->he_cap.he_cap_elem.phy_cap_info; 6806 6807 if ((phy_cap[3] & IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 6808 (phy_cap[4] & IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) { 6809 ldpc_en &= !!(phy_cap[1] & IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD); 6810 stbc_en &= !!(phy_cap[2] & IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ); 6811 t = FIELD_GET(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 6812 phy_cap[5]); 6813 sound_dim = min(sound_dim, t); 6814 } 6815 if ((link_sta->vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 6816 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) { 6817 ldpc_en &= !!(link_sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC); 6818 stbc_en &= !!(link_sta->vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK); 6819 t = FIELD_GET(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, 6820 link_sta->vht_cap.cap); 6821 sound_dim = min(sound_dim, t); 6822 } 6823 nc = min(nc, sound_dim); 6824 nr = min(nr, sound_dim); 6825 6826 rcu_read_unlock(); 6827 6828 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 6829 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 6830 6831 val = FIELD_PREP(B_AX_BFMEE_CSIINFO0_NC_MASK, nc) | 6832 FIELD_PREP(B_AX_BFMEE_CSIINFO0_NR_MASK, nr) | 6833 FIELD_PREP(B_AX_BFMEE_CSIINFO0_NG_MASK, ng) | 6834 FIELD_PREP(B_AX_BFMEE_CSIINFO0_CB_MASK, cb) | 6835 FIELD_PREP(B_AX_BFMEE_CSIINFO0_CS_MASK, cs) | 6836 FIELD_PREP(B_AX_BFMEE_CSIINFO0_LDPC_EN, ldpc_en) | 6837 FIELD_PREP(B_AX_BFMEE_CSIINFO0_STBC_EN, stbc_en); 6838 6839 if (port_sel == 0) 6840 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 6841 else 6842 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_1, mac_idx); 6843 6844 rtw89_write16(rtwdev, reg, val); 6845 6846 return 0; 6847 } 6848 6849 static int rtw89_mac_csi_rrsc_ax(struct rtw89_dev *rtwdev, 6850 struct rtw89_vif_link *rtwvif_link, 6851 struct rtw89_sta_link *rtwsta_link) 6852 { 6853 u32 rrsc = BIT(RTW89_MAC_BF_RRSC_6M) | BIT(RTW89_MAC_BF_RRSC_24M); 6854 struct ieee80211_link_sta *link_sta; 6855 u8 mac_idx = rtwvif_link->mac_idx; 6856 u32 reg; 6857 int ret; 6858 6859 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6860 if (ret) 6861 return ret; 6862 6863 rcu_read_lock(); 6864 6865 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 6866 6867 if (link_sta->he_cap.has_he) { 6868 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HE_MSC0) | 6869 BIT(RTW89_MAC_BF_RRSC_HE_MSC3) | 6870 BIT(RTW89_MAC_BF_RRSC_HE_MSC5)); 6871 } 6872 if (link_sta->vht_cap.vht_supported) { 6873 rrsc |= (BIT(RTW89_MAC_BF_RRSC_VHT_MSC0) | 6874 BIT(RTW89_MAC_BF_RRSC_VHT_MSC3) | 6875 BIT(RTW89_MAC_BF_RRSC_VHT_MSC5)); 6876 } 6877 if (link_sta->ht_cap.ht_supported) { 6878 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HT_MSC0) | 6879 BIT(RTW89_MAC_BF_RRSC_HT_MSC3) | 6880 BIT(RTW89_MAC_BF_RRSC_HT_MSC5)); 6881 } 6882 6883 rcu_read_unlock(); 6884 6885 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 6886 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 6887 rtw89_write32_clr(rtwdev, reg, B_AX_BFMEE_CSI_FORCE_RETE_EN); 6888 rtw89_write32(rtwdev, 6889 rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx), 6890 rrsc); 6891 6892 return 0; 6893 } 6894 6895 static void rtw89_mac_bf_assoc_ax(struct rtw89_dev *rtwdev, 6896 struct rtw89_vif_link *rtwvif_link, 6897 struct rtw89_sta_link *rtwsta_link) 6898 { 6899 struct ieee80211_link_sta *link_sta; 6900 bool has_beamformer_cap; 6901 6902 rcu_read_lock(); 6903 6904 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 6905 has_beamformer_cap = rtw89_sta_has_beamformer_cap(link_sta); 6906 6907 rcu_read_unlock(); 6908 6909 if (has_beamformer_cap) { 6910 rtw89_debug(rtwdev, RTW89_DBG_BF, 6911 "initialize bfee for new association\n"); 6912 rtw89_mac_init_bfee_ax(rtwdev, rtwvif_link->mac_idx); 6913 rtw89_mac_set_csi_para_reg_ax(rtwdev, rtwvif_link, rtwsta_link); 6914 rtw89_mac_csi_rrsc_ax(rtwdev, rtwvif_link, rtwsta_link); 6915 } 6916 } 6917 6918 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, 6919 struct rtw89_vif_link *rtwvif_link, 6920 struct rtw89_sta_link *rtwsta_link) 6921 { 6922 rtw89_mac_bfee_ctrl(rtwdev, rtwvif_link->mac_idx, false); 6923 } 6924 6925 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 6926 struct ieee80211_bss_conf *conf) 6927 { 6928 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6929 const struct rtw89_mac_mu_gid_addr *addr = mac->mu_gid; 6930 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif); 6931 struct rtw89_vif_link *rtwvif_link; 6932 u8 mac_idx; 6933 __le32 *p; 6934 6935 rtwvif_link = rtwvif->links[conf->link_id]; 6936 if (unlikely(!rtwvif_link)) { 6937 rtw89_err(rtwdev, 6938 "%s: rtwvif link (link_id %u) is not active\n", 6939 __func__, conf->link_id); 6940 return; 6941 } 6942 6943 mac_idx = rtwvif_link->mac_idx; 6944 6945 rtw89_debug(rtwdev, RTW89_DBG_BF, "update bf GID table\n"); 6946 6947 p = (__le32 *)conf->mu_group.membership; 6948 rtw89_write32(rtwdev, 6949 rtw89_mac_reg_by_idx(rtwdev, addr->position_en[0], mac_idx), 6950 le32_to_cpu(p[0])); 6951 rtw89_write32(rtwdev, 6952 rtw89_mac_reg_by_idx(rtwdev, addr->position_en[1], mac_idx), 6953 le32_to_cpu(p[1])); 6954 6955 p = (__le32 *)conf->mu_group.position; 6956 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, addr->position[0], mac_idx), 6957 le32_to_cpu(p[0])); 6958 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, addr->position[1], mac_idx), 6959 le32_to_cpu(p[1])); 6960 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, addr->position[2], mac_idx), 6961 le32_to_cpu(p[2])); 6962 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, addr->position[3], mac_idx), 6963 le32_to_cpu(p[3])); 6964 } 6965 6966 struct rtw89_mac_bf_monitor_iter_data { 6967 struct rtw89_dev *rtwdev; 6968 struct rtw89_sta_link *down_rtwsta_link; 6969 int count; 6970 }; 6971 6972 static 6973 void rtw89_mac_bf_monitor_calc_iter(void *data, struct ieee80211_sta *sta) 6974 { 6975 struct rtw89_mac_bf_monitor_iter_data *iter_data = 6976 (struct rtw89_mac_bf_monitor_iter_data *)data; 6977 struct rtw89_sta_link *down_rtwsta_link = iter_data->down_rtwsta_link; 6978 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 6979 struct ieee80211_link_sta *link_sta; 6980 struct rtw89_sta_link *rtwsta_link; 6981 bool has_beamformer_cap = false; 6982 int *count = &iter_data->count; 6983 unsigned int link_id; 6984 6985 rcu_read_lock(); 6986 6987 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) { 6988 if (rtwsta_link == down_rtwsta_link) 6989 continue; 6990 6991 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false); 6992 if (rtw89_sta_has_beamformer_cap(link_sta)) { 6993 has_beamformer_cap = true; 6994 break; 6995 } 6996 } 6997 6998 if (has_beamformer_cap) 6999 (*count)++; 7000 7001 rcu_read_unlock(); 7002 } 7003 7004 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev, 7005 struct rtw89_sta_link *rtwsta_link, 7006 bool disconnect) 7007 { 7008 struct rtw89_mac_bf_monitor_iter_data data; 7009 7010 data.rtwdev = rtwdev; 7011 data.down_rtwsta_link = disconnect ? rtwsta_link : NULL; 7012 data.count = 0; 7013 ieee80211_iterate_stations_atomic(rtwdev->hw, 7014 rtw89_mac_bf_monitor_calc_iter, 7015 &data); 7016 7017 rtw89_debug(rtwdev, RTW89_DBG_BF, "bfee STA count=%d\n", data.count); 7018 assign_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags, data.count); 7019 } 7020 7021 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev) 7022 { 7023 struct rtw89_traffic_stats *stats = &rtwdev->stats; 7024 struct rtw89_vif_link *rtwvif_link; 7025 bool en = stats->tx_tfc_lv <= stats->rx_tfc_lv; 7026 bool old = test_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 7027 struct rtw89_vif *rtwvif; 7028 bool keep_timer = true; 7029 unsigned int link_id; 7030 bool old_keep_timer; 7031 7032 old_keep_timer = test_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 7033 7034 if (stats->tx_tfc_lv <= RTW89_TFC_LOW && stats->rx_tfc_lv <= RTW89_TFC_LOW) 7035 keep_timer = false; 7036 7037 if (keep_timer != old_keep_timer) { 7038 rtw89_for_each_rtwvif(rtwdev, rtwvif) 7039 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 7040 rtw89_mac_bfee_standby_timer(rtwdev, rtwvif_link->mac_idx, 7041 keep_timer); 7042 } 7043 7044 if (en == old) 7045 return; 7046 7047 rtw89_for_each_rtwvif(rtwdev, rtwvif) 7048 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 7049 rtw89_mac_bfee_ctrl(rtwdev, rtwvif_link->mac_idx, en); 7050 } 7051 7052 static int 7053 __rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link, 7054 u32 tx_time) 7055 { 7056 #define MAC_AX_DFLT_TX_TIME 5280 7057 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 7058 const struct rtw89_chip_info *chip = rtwdev->chip; 7059 u8 mac_idx = rtwsta_link->rtwvif_link->mac_idx; 7060 u32 max_tx_time = tx_time == 0 ? MAC_AX_DFLT_TX_TIME : tx_time; 7061 struct rtw89_entity_conf conf; 7062 const struct rtw89_chan *chan; 7063 u32 reg; 7064 int ret = 0; 7065 7066 if (chip->txtime_limit_2ghz) { 7067 rtw89_entity_get_conf(rtwdev, &conf); 7068 chan = conf.chans[mac_idx]; 7069 7070 if (chan->band_type == RTW89_BAND_2G) 7071 max_tx_time = min_t(u32, max_tx_time, 7072 chip->txtime_limit_2ghz); 7073 } 7074 7075 if (rtwsta_link->cctl_tx_time) { 7076 rtwsta_link->ampdu_max_time = (max_tx_time - 512) >> 9; 7077 ret = rtw89_chip_h2c_txtime_cmac_tbl(rtwdev, rtwsta_link); 7078 } else { 7079 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 7080 if (ret) { 7081 rtw89_warn(rtwdev, "failed to check cmac in set txtime\n"); 7082 return ret; 7083 } 7084 7085 if (chip->chip_gen == RTW89_CHIP_AX) 7086 max_tx_time >>= 5; 7087 else 7088 max_tx_time = max_tx_time * 1000 >> 15; 7089 7090 reg = rtw89_mac_reg_by_idx(rtwdev, mac->agg_limit.addr, mac_idx); 7091 rtw89_write32_mask(rtwdev, reg, mac->agg_limit.mask, max_tx_time); 7092 } 7093 7094 return ret; 7095 } 7096 7097 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link, 7098 bool resume, u32 tx_time) 7099 { 7100 int ret = 0; 7101 7102 if (!resume) { 7103 rtwsta_link->cctl_tx_time = true; 7104 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta_link, tx_time); 7105 } else { 7106 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta_link, tx_time); 7107 rtwsta_link->cctl_tx_time = false; 7108 } 7109 7110 return ret; 7111 } 7112 7113 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link, 7114 u32 *tx_time) 7115 { 7116 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 7117 u8 mac_idx = rtwsta_link->rtwvif_link->mac_idx; 7118 u32 reg; 7119 int ret = 0; 7120 7121 if (rtwsta_link->cctl_tx_time) { 7122 *tx_time = (rtwsta_link->ampdu_max_time + 1) << 9; 7123 } else { 7124 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 7125 if (ret) { 7126 rtw89_warn(rtwdev, "failed to check cmac in tx_time\n"); 7127 return ret; 7128 } 7129 7130 reg = rtw89_mac_reg_by_idx(rtwdev, mac->agg_limit.addr, mac_idx); 7131 *tx_time = rtw89_read32_mask(rtwdev, reg, mac->agg_limit.mask) << 5; 7132 } 7133 7134 return ret; 7135 } 7136 7137 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev, 7138 struct rtw89_sta_link *rtwsta_link, 7139 bool resume, u8 tx_retry) 7140 { 7141 int ret = 0; 7142 7143 rtwsta_link->data_tx_cnt_lmt = tx_retry; 7144 7145 if (!resume) { 7146 rtwsta_link->cctl_tx_retry_limit = true; 7147 ret = rtw89_chip_h2c_txtime_cmac_tbl(rtwdev, rtwsta_link); 7148 } else { 7149 ret = rtw89_chip_h2c_txtime_cmac_tbl(rtwdev, rtwsta_link); 7150 rtwsta_link->cctl_tx_retry_limit = false; 7151 } 7152 7153 return ret; 7154 } 7155 7156 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev, 7157 struct rtw89_sta_link *rtwsta_link, u8 *tx_retry) 7158 { 7159 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 7160 u8 mac_idx = rtwsta_link->rtwvif_link->mac_idx; 7161 u32 reg; 7162 int ret = 0; 7163 7164 if (rtwsta_link->cctl_tx_retry_limit) { 7165 *tx_retry = rtwsta_link->data_tx_cnt_lmt; 7166 } else { 7167 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 7168 if (ret) { 7169 rtw89_warn(rtwdev, "failed to check cmac in rty_lmt\n"); 7170 return ret; 7171 } 7172 7173 reg = rtw89_mac_reg_by_idx(rtwdev, mac->txcnt_limit.addr, mac_idx); 7174 *tx_retry = rtw89_read32_mask(rtwdev, reg, mac->txcnt_limit.mask); 7175 } 7176 7177 return ret; 7178 } 7179 7180 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev, 7181 struct rtw89_vif_link *rtwvif_link, bool en) 7182 { 7183 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 7184 u8 mac_idx = rtwvif_link->mac_idx; 7185 u16 set = mac->muedca_ctrl.mask; 7186 u32 reg; 7187 int ret; 7188 7189 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 7190 if (ret) 7191 return ret; 7192 7193 reg = rtw89_mac_reg_by_idx(rtwdev, mac->muedca_ctrl.addr, mac_idx); 7194 if (en) 7195 rtw89_write16_set(rtwdev, reg, set); 7196 else 7197 rtw89_write16_clr(rtwdev, reg, set); 7198 7199 return 0; 7200 } 7201 7202 static 7203 int rtw89_mac_write_xtal_si_ax(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask) 7204 { 7205 u32 val32; 7206 int ret; 7207 7208 val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 7209 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, val) | 7210 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, mask) | 7211 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_WRITE) | 7212 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 7213 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 7214 7215 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 7216 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 7217 if (ret) { 7218 rtw89_warn(rtwdev, "xtal si not ready(W): offset=%x val=%x mask=%x\n", 7219 offset, val, mask); 7220 return ret; 7221 } 7222 7223 if (!test_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags) && 7224 (u32_get_bits(val32, B_AX_WL_XTAL_SI_ADDR_MASK) != offset || 7225 u32_get_bits(val32, B_AX_WL_XTAL_SI_DATA_MASK) != val)) 7226 rtw89_warn(rtwdev, "xtal si write: offset=%x val=%x poll=%x\n", 7227 offset, val, val32); 7228 7229 return 0; 7230 } 7231 7232 static 7233 int rtw89_mac_read_xtal_si_ax(struct rtw89_dev *rtwdev, u8 offset, u8 *val) 7234 { 7235 u32 val32; 7236 int ret; 7237 7238 val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 7239 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, 0x00) | 7240 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, 0x00) | 7241 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_READ) | 7242 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 7243 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 7244 7245 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 7246 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 7247 if (ret) { 7248 rtw89_warn(rtwdev, "xtal si not ready(R): offset=%x\n", offset); 7249 return ret; 7250 } 7251 7252 if (!test_bit(RTW89_FLAG_UNPLUGGED, rtwdev->flags) && 7253 u32_get_bits(val32, B_AX_WL_XTAL_SI_ADDR_MASK) != offset) 7254 rtw89_warn(rtwdev, "xtal si read: offset=%x poll=%x\n", 7255 offset, val32); 7256 7257 *val = u32_get_bits(val32, B_AX_WL_XTAL_SI_DATA_MASK); 7258 7259 return 0; 7260 } 7261 7262 static 7263 void rtw89_mac_pkt_drop_sta(struct rtw89_dev *rtwdev, 7264 struct rtw89_vif_link *rtwvif_link, 7265 struct rtw89_sta_link *rtwsta_link) 7266 { 7267 static const enum rtw89_pkt_drop_sel sels[] = { 7268 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 7269 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 7270 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 7271 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 7272 }; 7273 struct rtw89_pkt_drop_params params = {0}; 7274 int i; 7275 7276 params.mac_band = rtwvif_link->mac_idx; 7277 params.macid = rtwsta_link->mac_id; 7278 params.port = rtwvif_link->port; 7279 params.mbssid = 0; 7280 params.tf_trs = rtwvif_link->trigger; 7281 7282 for (i = 0; i < ARRAY_SIZE(sels); i++) { 7283 params.sel = sels[i]; 7284 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); 7285 } 7286 } 7287 7288 static void rtw89_mac_pkt_drop_vif_iter(void *data, struct ieee80211_sta *sta) 7289 { 7290 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 7291 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 7292 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 7293 struct rtw89_vif_link *rtwvif_link; 7294 struct rtw89_sta_link *rtwsta_link; 7295 struct rtw89_vif *target = data; 7296 unsigned int link_id; 7297 7298 if (rtwvif != target) 7299 return; 7300 7301 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) { 7302 rtwvif_link = rtwsta_link->rtwvif_link; 7303 rtw89_mac_pkt_drop_sta(rtwdev, rtwvif_link, rtwsta_link); 7304 } 7305 } 7306 7307 void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 7308 { 7309 ieee80211_iterate_stations_atomic(rtwdev->hw, 7310 rtw89_mac_pkt_drop_vif_iter, 7311 rtwvif); 7312 } 7313 7314 int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev, 7315 enum rtw89_mac_idx band) 7316 { 7317 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 7318 struct rtw89_pkt_drop_params params = {0}; 7319 bool empty; 7320 int i, ret = 0, try_cnt = 3; 7321 7322 params.mac_band = band; 7323 params.sel = RTW89_PKT_DROP_SEL_BAND_ONCE; 7324 7325 for (i = 0; i < try_cnt; i++) { 7326 ret = read_poll_timeout(mac->is_txq_empty, empty, empty, 50, 7327 50000, false, rtwdev); 7328 if (ret && !RTW89_CHK_FW_FEATURE(NO_PACKET_DROP, &rtwdev->fw)) 7329 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); 7330 else 7331 return 0; 7332 } 7333 return ret; 7334 } 7335 7336 static int _rtw89_mac_cpu_io_rx(struct rtw89_dev *rtwdev, bool wow_enable) 7337 { 7338 struct rtw89_mac_h2c_info h2c_info = {}; 7339 struct rtw89_mac_c2h_info c2h_info = {}; 7340 int ret; 7341 7342 if (RTW89_CHK_FW_FEATURE(NO_WOW_CPU_IO_RX, &rtwdev->fw)) 7343 return 0; 7344 7345 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_WOW_CPUIO_RX_CTRL; 7346 h2c_info.content_len = sizeof(h2c_info.u.hdr); 7347 h2c_info.u.hdr.w0 = u32_encode_bits(wow_enable, RTW89_H2CREG_WOW_CPUIO_RX_CTRL_EN); 7348 7349 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info); 7350 if (ret) 7351 return ret; 7352 7353 if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_WOW_CPUIO_RX_ACK) 7354 ret = -EINVAL; 7355 7356 return ret; 7357 } 7358 7359 int rtw89_mac_cpu_io_rx(struct rtw89_dev *rtwdev, bool wow_enable) 7360 { 7361 int i, ret; 7362 7363 for (i = 0; i < CPU_IO_RX_RETRY_CNT; i++) { 7364 ret = _rtw89_mac_cpu_io_rx(rtwdev, wow_enable); 7365 if (!ret) 7366 return 0; 7367 } 7368 7369 return ret; 7370 } 7371 7372 static int rtw89_wow_config_mac_ax(struct rtw89_dev *rtwdev, bool enable_wow) 7373 { 7374 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 7375 const struct rtw89_chip_info *chip = rtwdev->chip; 7376 int ret; 7377 7378 if (enable_wow) { 7379 ret = rtw89_mac_resize_ple_rx_quota(rtwdev, true); 7380 if (ret) { 7381 rtw89_err(rtwdev, "[ERR]patch rx qta %d\n", ret); 7382 return ret; 7383 } 7384 7385 rtw89_write32_set(rtwdev, R_AX_RX_FUNCTION_STOP, B_AX_HDR_RX_STOP); 7386 rtw89_mac_cpu_io_rx(rtwdev, enable_wow); 7387 rtw89_write32_clr(rtwdev, mac->rx_fltr, B_AX_SNIFFER_MODE); 7388 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false); 7389 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, 0); 7390 rtw89_write32(rtwdev, R_AX_ACTION_FWD1, 0); 7391 rtw89_write32(rtwdev, R_AX_TF_FWD, 0); 7392 rtw89_write32(rtwdev, R_AX_HW_RPT_FWD, 0); 7393 7394 if (RTW89_CHK_FW_FEATURE(NO_WOW_CPU_IO_RX, &rtwdev->fw)) 7395 return 0; 7396 7397 if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) 7398 rtw89_write8(rtwdev, R_BE_DBG_WOW_READY, WOWLAN_NOT_READY); 7399 else 7400 rtw89_write32_set(rtwdev, R_AX_DBG_WOW, 7401 B_AX_DBG_WOW_CPU_IO_RX_EN); 7402 } else { 7403 ret = rtw89_mac_resize_ple_rx_quota(rtwdev, false); 7404 if (ret) { 7405 rtw89_err(rtwdev, "[ERR]patch rx qta %d\n", ret); 7406 return ret; 7407 } 7408 7409 rtw89_mac_cpu_io_rx(rtwdev, enable_wow); 7410 rtw89_write32_clr(rtwdev, R_AX_RX_FUNCTION_STOP, B_AX_HDR_RX_STOP); 7411 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true); 7412 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD); 7413 rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD); 7414 } 7415 7416 return 0; 7417 } 7418 7419 static u8 rtw89_fw_get_rdy_ax(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type) 7420 { 7421 u8 val = rtw89_read8(rtwdev, R_AX_WCPU_FW_CTRL); 7422 7423 return FIELD_GET(B_AX_WCPU_FWDL_STS_MASK, val); 7424 } 7425 7426 static 7427 int rtw89_fwdl_check_path_ready_ax(struct rtw89_dev *rtwdev, 7428 bool h2c_or_fwdl) 7429 { 7430 u8 check = h2c_or_fwdl ? B_AX_H2C_PATH_RDY : B_AX_FWDL_PATH_RDY; 7431 u32 timeout; 7432 u8 val; 7433 7434 if (rtwdev->hci.type == RTW89_HCI_TYPE_USB) 7435 timeout = FWDL_WAIT_CNT_USB; 7436 else 7437 timeout = FWDL_WAIT_CNT; 7438 7439 return read_poll_timeout_atomic(rtw89_read8, val, val & check, 7440 1, timeout, false, 7441 rtwdev, R_AX_WCPU_FW_CTRL); 7442 } 7443 7444 static 7445 void rtw89_fwdl_secure_idmem_share_mode_ax(struct rtw89_dev *rtwdev, u8 mode) 7446 { 7447 struct rtw89_fw_secure *sec = &rtwdev->fw.sec; 7448 7449 if (!sec->secure_boot) 7450 return; 7451 7452 rtw89_write32_mask(rtwdev, R_AX_WCPU_FW_CTRL, 7453 B_AX_IDMEM_SHARE_MODE_RECORD_MASK, mode); 7454 rtw89_write32_set(rtwdev, R_AX_WCPU_FW_CTRL, 7455 B_AX_IDMEM_SHARE_MODE_RECORD_VALID); 7456 } 7457 7458 const struct rtw89_mac_gen_def rtw89_mac_gen_ax = { 7459 .band1_offset = RTW89_MAC_AX_BAND_REG_OFFSET, 7460 .filter_model_addr = R_AX_FILTER_MODEL_ADDR, 7461 .indir_access_addr = R_AX_INDIR_ACCESS_ENTRY, 7462 .mem_base_addrs = rtw89_mac_mem_base_addrs_ax, 7463 .mem_page_size = MAC_MEM_DUMP_PAGE_SIZE_AX, 7464 .rx_fltr = R_AX_RX_FLTR_OPT, 7465 .default_rx_fltr = DEFAULT_AX_RX_FLTR, 7466 .port_base = &rtw89_port_base_ax, 7467 .agg_len_ht = R_AX_AGG_LEN_HT_0, 7468 .ps_status = R_AX_PPWRBIT_SETTING, 7469 .mu_gid = &rtw89_mac_mu_gid_addr_ax, 7470 .boot_dbg = R_AX_BOOT_DBG, 7471 7472 .muedca_ctrl = { 7473 .addr = R_AX_MUEDCA_EN, 7474 .mask = B_AX_MUEDCA_EN_0 | B_AX_SET_MUEDCATIMER_TF_0, 7475 }, 7476 .bfee_ctrl = { 7477 .addr = R_AX_BFMEE_RESP_OPTION, 7478 .mask = B_AX_BFMEE_HT_NDPA_EN | B_AX_BFMEE_VHT_NDPA_EN | 7479 B_AX_BFMEE_HE_NDPA_EN, 7480 }, 7481 .narrow_bw_ru_dis = { 7482 .addr = R_AX_RXTRIG_TEST_USER_2, 7483 .mask = B_AX_RXTRIG_RU26_DIS, 7484 }, 7485 .wow_ctrl = {.addr = R_AX_WOW_CTRL, .mask = B_AX_WOW_WOWEN,}, 7486 .agg_limit = {.addr = R_AX_AMPDU_AGG_LIMIT, .mask = B_AX_AMPDU_MAX_TIME_MASK,}, 7487 .ra_agg_limit = {.addr = R_AX_AMPDU_AGG_LIMIT, 7488 .mask = B_AX_RA_TRY_RATE_AGG_LMT_MASK,}, 7489 .txcnt_limit = {.addr = R_AX_TXCNT, .mask = B_AX_L_TXCNT_LMT_MASK,}, 7490 7491 .check_mac_en = rtw89_mac_check_mac_en_ax, 7492 .sys_init = sys_init_ax, 7493 .trx_init = trx_init_ax, 7494 .preload_init = preload_init_set_ax, 7495 .clr_aon_intr = NULL, 7496 .err_imr_ctrl = err_imr_ctrl_ax, 7497 .mac_func_en = NULL, 7498 .hci_func_en = rtw89_mac_hci_func_en_ax, 7499 .dmac_func_pre_en = rtw89_mac_dmac_func_pre_en_ax, 7500 .dle_func_en = dle_func_en_ax, 7501 .dle_clk_en = dle_clk_en_ax, 7502 .bf_assoc = rtw89_mac_bf_assoc_ax, 7503 7504 .typ_fltr_opt = rtw89_mac_typ_fltr_opt_ax, 7505 .cfg_ppdu_status = rtw89_mac_cfg_ppdu_status_ax, 7506 .cfg_phy_rpt = NULL, 7507 .set_edcca_mode = NULL, 7508 .set_vcore_cfg = NULL, 7509 7510 .dle_mix_cfg = dle_mix_cfg_ax, 7511 .chk_dle_rdy = chk_dle_rdy_ax, 7512 .dle_buf_req = dle_buf_req_ax, 7513 .hfc_func_en = hfc_func_en_ax, 7514 .hfc_h2c_cfg = hfc_h2c_cfg_ax, 7515 .hfc_mix_cfg = hfc_mix_cfg_ax, 7516 .hfc_get_mix_info = hfc_get_mix_info_ax, 7517 .wde_quota_cfg = wde_quota_cfg_ax, 7518 .ple_quota_cfg = ple_quota_cfg_ax, 7519 .set_cpuio = set_cpuio_ax, 7520 .dle_quota_change = dle_quota_change_ax, 7521 7522 .reset_pwr_state = rtw89_mac_reset_pwr_state_ax, 7523 .disable_cpu = rtw89_mac_disable_cpu_ax, 7524 .fwdl_preconfig = NULL, 7525 .fwdl_enable_wcpu = rtw89_mac_enable_cpu_ax, 7526 .fwdl_get_status = rtw89_fw_get_rdy_ax, 7527 .fwdl_check_path_ready = rtw89_fwdl_check_path_ready_ax, 7528 .fwdl_secure_idmem_share_mode = rtw89_fwdl_secure_idmem_share_mode_ax, 7529 .parse_efuse_map = rtw89_parse_efuse_map_ax, 7530 .parse_phycap_map = rtw89_parse_phycap_map_ax, 7531 .cnv_efuse_state = rtw89_cnv_efuse_state_ax, 7532 .efuse_read_fw_secure = rtw89_efuse_read_fw_secure_ax, 7533 .efuse_read_ecv = NULL, 7534 .efuse_read_thermal_k = NULL, 7535 .efuse_read_pwr_data = NULL, 7536 7537 .cfg_plt = rtw89_mac_cfg_plt_ax, 7538 .get_plt_cnt = rtw89_mac_get_plt_cnt_ax, 7539 7540 .get_txpwr_cr = rtw89_mac_get_txpwr_cr_ax, 7541 7542 .write_xtal_si = rtw89_mac_write_xtal_si_ax, 7543 .read_xtal_si = rtw89_mac_read_xtal_si_ax, 7544 7545 .dump_qta_lost = rtw89_mac_dump_qta_lost_ax, 7546 .dump_err_status = rtw89_mac_dump_err_status_ax, 7547 7548 .is_txq_empty = mac_is_txq_empty_ax, 7549 7550 .prep_chan_list = rtw89_hw_scan_prep_chan_list_ax, 7551 .free_chan_list = rtw89_hw_scan_free_chan_list_ax, 7552 .add_chan_list = rtw89_hw_scan_add_chan_list_ax, 7553 .add_chan_list_pno = rtw89_pno_scan_add_chan_list_ax, 7554 .scan_offload = rtw89_fw_h2c_scan_offload_ax, 7555 7556 .wow_config_mac = rtw89_wow_config_mac_ax, 7557 }; 7558 EXPORT_SYMBOL(rtw89_mac_gen_ax); 7559