1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 #include <linux/ip.h> 5 #include <linux/sort.h> 6 #include <linux/udp.h> 7 8 #include "cam.h" 9 #include "chan.h" 10 #include "coex.h" 11 #include "core.h" 12 #include "efuse.h" 13 #include "fw.h" 14 #include "led.h" 15 #include "mac.h" 16 #include "phy.h" 17 #include "ps.h" 18 #include "reg.h" 19 #include "sar.h" 20 #include "ser.h" 21 #include "txrx.h" 22 #include "util.h" 23 #include "wow.h" 24 25 static bool rtw89_disable_ps_mode; 26 module_param_named(disable_ps_mode, rtw89_disable_ps_mode, bool, 0644); 27 MODULE_PARM_DESC(disable_ps_mode, "Set Y to disable low power mode"); 28 29 #define RTW89_DEF_CHAN(_freq, _hw_val, _flags, _band) \ 30 { .center_freq = _freq, .hw_value = _hw_val, .flags = _flags, .band = _band, } 31 #define RTW89_DEF_CHAN_2G(_freq, _hw_val) \ 32 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_2GHZ) 33 #define RTW89_DEF_CHAN_5G(_freq, _hw_val) \ 34 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_5GHZ) 35 #define RTW89_DEF_CHAN_5G_NO_HT40MINUS(_freq, _hw_val) \ 36 RTW89_DEF_CHAN(_freq, _hw_val, IEEE80211_CHAN_NO_HT40MINUS, NL80211_BAND_5GHZ) 37 #define RTW89_DEF_CHAN_6G(_freq, _hw_val) \ 38 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_6GHZ) 39 40 static struct ieee80211_channel rtw89_channels_2ghz[] = { 41 RTW89_DEF_CHAN_2G(2412, 1), 42 RTW89_DEF_CHAN_2G(2417, 2), 43 RTW89_DEF_CHAN_2G(2422, 3), 44 RTW89_DEF_CHAN_2G(2427, 4), 45 RTW89_DEF_CHAN_2G(2432, 5), 46 RTW89_DEF_CHAN_2G(2437, 6), 47 RTW89_DEF_CHAN_2G(2442, 7), 48 RTW89_DEF_CHAN_2G(2447, 8), 49 RTW89_DEF_CHAN_2G(2452, 9), 50 RTW89_DEF_CHAN_2G(2457, 10), 51 RTW89_DEF_CHAN_2G(2462, 11), 52 RTW89_DEF_CHAN_2G(2467, 12), 53 RTW89_DEF_CHAN_2G(2472, 13), 54 RTW89_DEF_CHAN_2G(2484, 14), 55 }; 56 57 static struct ieee80211_channel rtw89_channels_5ghz[] = { 58 RTW89_DEF_CHAN_5G(5180, 36), 59 RTW89_DEF_CHAN_5G(5200, 40), 60 RTW89_DEF_CHAN_5G(5220, 44), 61 RTW89_DEF_CHAN_5G(5240, 48), 62 RTW89_DEF_CHAN_5G(5260, 52), 63 RTW89_DEF_CHAN_5G(5280, 56), 64 RTW89_DEF_CHAN_5G(5300, 60), 65 RTW89_DEF_CHAN_5G(5320, 64), 66 RTW89_DEF_CHAN_5G(5500, 100), 67 RTW89_DEF_CHAN_5G(5520, 104), 68 RTW89_DEF_CHAN_5G(5540, 108), 69 RTW89_DEF_CHAN_5G(5560, 112), 70 RTW89_DEF_CHAN_5G(5580, 116), 71 RTW89_DEF_CHAN_5G(5600, 120), 72 RTW89_DEF_CHAN_5G(5620, 124), 73 RTW89_DEF_CHAN_5G(5640, 128), 74 RTW89_DEF_CHAN_5G(5660, 132), 75 RTW89_DEF_CHAN_5G(5680, 136), 76 RTW89_DEF_CHAN_5G(5700, 140), 77 RTW89_DEF_CHAN_5G(5720, 144), 78 RTW89_DEF_CHAN_5G(5745, 149), 79 RTW89_DEF_CHAN_5G(5765, 153), 80 RTW89_DEF_CHAN_5G(5785, 157), 81 RTW89_DEF_CHAN_5G(5805, 161), 82 RTW89_DEF_CHAN_5G_NO_HT40MINUS(5825, 165), 83 RTW89_DEF_CHAN_5G(5845, 169), 84 RTW89_DEF_CHAN_5G(5865, 173), 85 RTW89_DEF_CHAN_5G(5885, 177), 86 }; 87 88 static_assert(RTW89_5GHZ_UNII4_START_INDEX + RTW89_5GHZ_UNII4_CHANNEL_NUM == 89 ARRAY_SIZE(rtw89_channels_5ghz)); 90 91 static struct ieee80211_channel rtw89_channels_6ghz[] = { 92 RTW89_DEF_CHAN_6G(5955, 1), 93 RTW89_DEF_CHAN_6G(5975, 5), 94 RTW89_DEF_CHAN_6G(5995, 9), 95 RTW89_DEF_CHAN_6G(6015, 13), 96 RTW89_DEF_CHAN_6G(6035, 17), 97 RTW89_DEF_CHAN_6G(6055, 21), 98 RTW89_DEF_CHAN_6G(6075, 25), 99 RTW89_DEF_CHAN_6G(6095, 29), 100 RTW89_DEF_CHAN_6G(6115, 33), 101 RTW89_DEF_CHAN_6G(6135, 37), 102 RTW89_DEF_CHAN_6G(6155, 41), 103 RTW89_DEF_CHAN_6G(6175, 45), 104 RTW89_DEF_CHAN_6G(6195, 49), 105 RTW89_DEF_CHAN_6G(6215, 53), 106 RTW89_DEF_CHAN_6G(6235, 57), 107 RTW89_DEF_CHAN_6G(6255, 61), 108 RTW89_DEF_CHAN_6G(6275, 65), 109 RTW89_DEF_CHAN_6G(6295, 69), 110 RTW89_DEF_CHAN_6G(6315, 73), 111 RTW89_DEF_CHAN_6G(6335, 77), 112 RTW89_DEF_CHAN_6G(6355, 81), 113 RTW89_DEF_CHAN_6G(6375, 85), 114 RTW89_DEF_CHAN_6G(6395, 89), 115 RTW89_DEF_CHAN_6G(6415, 93), 116 RTW89_DEF_CHAN_6G(6435, 97), 117 RTW89_DEF_CHAN_6G(6455, 101), 118 RTW89_DEF_CHAN_6G(6475, 105), 119 RTW89_DEF_CHAN_6G(6495, 109), 120 RTW89_DEF_CHAN_6G(6515, 113), 121 RTW89_DEF_CHAN_6G(6535, 117), 122 RTW89_DEF_CHAN_6G(6555, 121), 123 RTW89_DEF_CHAN_6G(6575, 125), 124 RTW89_DEF_CHAN_6G(6595, 129), 125 RTW89_DEF_CHAN_6G(6615, 133), 126 RTW89_DEF_CHAN_6G(6635, 137), 127 RTW89_DEF_CHAN_6G(6655, 141), 128 RTW89_DEF_CHAN_6G(6675, 145), 129 RTW89_DEF_CHAN_6G(6695, 149), 130 RTW89_DEF_CHAN_6G(6715, 153), 131 RTW89_DEF_CHAN_6G(6735, 157), 132 RTW89_DEF_CHAN_6G(6755, 161), 133 RTW89_DEF_CHAN_6G(6775, 165), 134 RTW89_DEF_CHAN_6G(6795, 169), 135 RTW89_DEF_CHAN_6G(6815, 173), 136 RTW89_DEF_CHAN_6G(6835, 177), 137 RTW89_DEF_CHAN_6G(6855, 181), 138 RTW89_DEF_CHAN_6G(6875, 185), 139 RTW89_DEF_CHAN_6G(6895, 189), 140 RTW89_DEF_CHAN_6G(6915, 193), 141 RTW89_DEF_CHAN_6G(6935, 197), 142 RTW89_DEF_CHAN_6G(6955, 201), 143 RTW89_DEF_CHAN_6G(6975, 205), 144 RTW89_DEF_CHAN_6G(6995, 209), 145 RTW89_DEF_CHAN_6G(7015, 213), 146 RTW89_DEF_CHAN_6G(7035, 217), 147 RTW89_DEF_CHAN_6G(7055, 221), 148 RTW89_DEF_CHAN_6G(7075, 225), 149 RTW89_DEF_CHAN_6G(7095, 229), 150 RTW89_DEF_CHAN_6G(7115, 233), 151 }; 152 153 static struct ieee80211_rate rtw89_bitrates[] = { 154 { .bitrate = 10, .hw_value = 0x00, }, 155 { .bitrate = 20, .hw_value = 0x01, }, 156 { .bitrate = 55, .hw_value = 0x02, }, 157 { .bitrate = 110, .hw_value = 0x03, }, 158 { .bitrate = 60, .hw_value = 0x04, }, 159 { .bitrate = 90, .hw_value = 0x05, }, 160 { .bitrate = 120, .hw_value = 0x06, }, 161 { .bitrate = 180, .hw_value = 0x07, }, 162 { .bitrate = 240, .hw_value = 0x08, }, 163 { .bitrate = 360, .hw_value = 0x09, }, 164 { .bitrate = 480, .hw_value = 0x0a, }, 165 { .bitrate = 540, .hw_value = 0x0b, }, 166 }; 167 168 static const struct ieee80211_iface_limit rtw89_iface_limits[] = { 169 { 170 .max = 2, 171 .types = BIT(NL80211_IFTYPE_STATION), 172 }, 173 { 174 .max = 1, 175 .types = BIT(NL80211_IFTYPE_P2P_CLIENT) | 176 BIT(NL80211_IFTYPE_P2P_GO) | 177 BIT(NL80211_IFTYPE_AP), 178 }, 179 { 180 .max = 1, 181 .types = BIT(NL80211_IFTYPE_P2P_DEVICE), 182 }, 183 }; 184 185 static const struct ieee80211_iface_limit rtw89_iface_limits_mcc[] = { 186 { 187 .max = 1, 188 .types = BIT(NL80211_IFTYPE_STATION), 189 }, 190 { 191 .max = 1, 192 .types = BIT(NL80211_IFTYPE_P2P_CLIENT) | 193 BIT(NL80211_IFTYPE_P2P_GO), 194 }, 195 { 196 .max = 1, 197 .types = BIT(NL80211_IFTYPE_P2P_DEVICE), 198 }, 199 }; 200 201 static const struct ieee80211_iface_combination rtw89_iface_combs[] = { 202 { 203 .limits = rtw89_iface_limits, 204 .n_limits = ARRAY_SIZE(rtw89_iface_limits), 205 .max_interfaces = RTW89_MAX_INTERFACE_NUM, 206 .num_different_channels = 1, 207 }, 208 { 209 .limits = rtw89_iface_limits_mcc, 210 .n_limits = ARRAY_SIZE(rtw89_iface_limits_mcc), 211 .max_interfaces = RTW89_MAX_INTERFACE_NUM, 212 .num_different_channels = 2, 213 }, 214 }; 215 216 static const u8 rtw89_ext_capa_sta[] = { 217 [0] = WLAN_EXT_CAPA1_EXT_CHANNEL_SWITCHING, 218 [2] = WLAN_EXT_CAPA3_MULTI_BSSID_SUPPORT, 219 [7] = WLAN_EXT_CAPA8_OPMODE_NOTIF, 220 }; 221 222 static const struct wiphy_iftype_ext_capab rtw89_iftypes_ext_capa[] = { 223 { 224 .iftype = NL80211_IFTYPE_STATION, 225 .extended_capabilities = rtw89_ext_capa_sta, 226 .extended_capabilities_mask = rtw89_ext_capa_sta, 227 .extended_capabilities_len = sizeof(rtw89_ext_capa_sta), 228 /* relevant only if EHT is supported */ 229 .eml_capabilities = 0, 230 .mld_capa_and_ops = 0, 231 }, 232 }; 233 234 #define RTW89_6GHZ_SPAN_HEAD 6145 235 #define RTW89_6GHZ_SPAN_IDX(center_freq) \ 236 ((((int)(center_freq) - RTW89_6GHZ_SPAN_HEAD) / 5) / 2) 237 238 #define RTW89_DECL_6GHZ_SPAN(center_freq, subband_l, subband_h) \ 239 [RTW89_6GHZ_SPAN_IDX(center_freq)] = { \ 240 .sar_subband_low = RTW89_SAR_6GHZ_ ## subband_l, \ 241 .sar_subband_high = RTW89_SAR_6GHZ_ ## subband_h, \ 242 .acpi_sar_subband_low = RTW89_ACPI_SAR_6GHZ_ ## subband_l, \ 243 .acpi_sar_subband_high = RTW89_ACPI_SAR_6GHZ_ ## subband_h, \ 244 .ant_gain_subband_low = RTW89_ANT_GAIN_6GHZ_ ## subband_l, \ 245 .ant_gain_subband_high = RTW89_ANT_GAIN_6GHZ_ ## subband_h, \ 246 } 247 248 /* Since 6GHz subbands are not edge aligned, some cases span two subbands. 249 * In the following, we describe each of them with rtw89_6ghz_span. 250 */ 251 static const struct rtw89_6ghz_span rtw89_overlapping_6ghz[] = { 252 RTW89_DECL_6GHZ_SPAN(6145, SUBBAND_5_L, SUBBAND_5_H), 253 RTW89_DECL_6GHZ_SPAN(6165, SUBBAND_5_L, SUBBAND_5_H), 254 RTW89_DECL_6GHZ_SPAN(6185, SUBBAND_5_L, SUBBAND_5_H), 255 RTW89_DECL_6GHZ_SPAN(6505, SUBBAND_6, SUBBAND_7_L), 256 RTW89_DECL_6GHZ_SPAN(6525, SUBBAND_6, SUBBAND_7_L), 257 RTW89_DECL_6GHZ_SPAN(6545, SUBBAND_6, SUBBAND_7_L), 258 RTW89_DECL_6GHZ_SPAN(6665, SUBBAND_7_L, SUBBAND_7_H), 259 RTW89_DECL_6GHZ_SPAN(6705, SUBBAND_7_L, SUBBAND_7_H), 260 RTW89_DECL_6GHZ_SPAN(6825, SUBBAND_7_H, SUBBAND_8), 261 RTW89_DECL_6GHZ_SPAN(6865, SUBBAND_7_H, SUBBAND_8), 262 RTW89_DECL_6GHZ_SPAN(6875, SUBBAND_7_H, SUBBAND_8), 263 RTW89_DECL_6GHZ_SPAN(6885, SUBBAND_7_H, SUBBAND_8), 264 }; 265 266 const struct rtw89_6ghz_span * 267 rtw89_get_6ghz_span(struct rtw89_dev *rtwdev, u32 center_freq) 268 { 269 int idx; 270 271 if (center_freq >= RTW89_6GHZ_SPAN_HEAD) { 272 idx = RTW89_6GHZ_SPAN_IDX(center_freq); 273 /* To decrease size of rtw89_overlapping_6ghz[], 274 * RTW89_6GHZ_SPAN_IDX() truncates the leading NULLs 275 * to make first span as index 0 of the table. So, if center 276 * frequency is less than the first one, it will get netative. 277 */ 278 if (idx >= 0 && idx < ARRAY_SIZE(rtw89_overlapping_6ghz)) 279 return &rtw89_overlapping_6ghz[idx]; 280 } 281 282 return NULL; 283 } 284 285 bool rtw89_legacy_rate_to_bitrate(struct rtw89_dev *rtwdev, u8 legacy_rate, u16 *bitrate) 286 { 287 const struct ieee80211_rate *rate; 288 289 if (unlikely(legacy_rate >= ARRAY_SIZE(rtw89_bitrates))) { 290 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, 291 "invalid legacy rate %d\n", legacy_rate); 292 return false; 293 } 294 295 rate = &rtw89_bitrates[legacy_rate]; 296 *bitrate = rate->bitrate; 297 298 return true; 299 } 300 301 static const struct ieee80211_supported_band rtw89_sband_2ghz = { 302 .band = NL80211_BAND_2GHZ, 303 .channels = rtw89_channels_2ghz, 304 .n_channels = ARRAY_SIZE(rtw89_channels_2ghz), 305 .bitrates = rtw89_bitrates, 306 .n_bitrates = ARRAY_SIZE(rtw89_bitrates), 307 .ht_cap = {0}, 308 .vht_cap = {0}, 309 }; 310 311 static const struct ieee80211_supported_band rtw89_sband_5ghz = { 312 .band = NL80211_BAND_5GHZ, 313 .channels = rtw89_channels_5ghz, 314 .n_channels = ARRAY_SIZE(rtw89_channels_5ghz), 315 316 /* 5G has no CCK rates, 1M/2M/5.5M/11M */ 317 .bitrates = rtw89_bitrates + 4, 318 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4, 319 .ht_cap = {0}, 320 .vht_cap = {0}, 321 }; 322 323 static const struct ieee80211_supported_band rtw89_sband_6ghz = { 324 .band = NL80211_BAND_6GHZ, 325 .channels = rtw89_channels_6ghz, 326 .n_channels = ARRAY_SIZE(rtw89_channels_6ghz), 327 328 /* 6G has no CCK rates, 1M/2M/5.5M/11M */ 329 .bitrates = rtw89_bitrates + 4, 330 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4, 331 }; 332 333 static const struct rtw89_hw_rate_def { 334 enum rtw89_hw_rate ht; 335 enum rtw89_hw_rate vht[RTW89_NSS_NUM]; 336 } rtw89_hw_rate[RTW89_CHIP_GEN_NUM] = { 337 [RTW89_CHIP_AX] = { 338 .ht = RTW89_HW_RATE_MCS0, 339 .vht = {RTW89_HW_RATE_VHT_NSS1_MCS0, 340 RTW89_HW_RATE_VHT_NSS2_MCS0, 341 RTW89_HW_RATE_VHT_NSS3_MCS0, 342 RTW89_HW_RATE_VHT_NSS4_MCS0}, 343 }, 344 [RTW89_CHIP_BE] = { 345 .ht = RTW89_HW_RATE_V1_MCS0, 346 .vht = {RTW89_HW_RATE_V1_VHT_NSS1_MCS0, 347 RTW89_HW_RATE_V1_VHT_NSS2_MCS0, 348 RTW89_HW_RATE_V1_VHT_NSS3_MCS0, 349 RTW89_HW_RATE_V1_VHT_NSS4_MCS0}, 350 }, 351 }; 352 353 static void rtw89_core_tx_skb_proto_stats(struct rtw89_traffic_stats *stats, 354 struct sk_buff *skb) 355 { 356 switch (ip_hdr(skb)->protocol) { 357 case IPPROTO_TCP: 358 stats->tcp++; 359 break; 360 case IPPROTO_UDP: 361 stats->udp++; 362 break; 363 default: 364 break; 365 } 366 } 367 368 static void __rtw89_traffic_stats_accu(struct rtw89_traffic_stats *stats, 369 struct sk_buff *skb, bool tx) 370 { 371 if (tx) { 372 rtw89_core_tx_skb_proto_stats(stats, skb); 373 stats->tx_cnt++; 374 stats->tx_unicast += skb->len; 375 } else { 376 stats->rx_cnt++; 377 stats->rx_unicast += skb->len; 378 } 379 } 380 381 static void rtw89_traffic_stats_accu(struct rtw89_dev *rtwdev, 382 struct rtw89_vif *rtwvif, 383 struct sk_buff *skb, 384 bool accu_dev, bool tx) 385 { 386 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 387 388 if (!ieee80211_is_data(hdr->frame_control)) 389 return; 390 391 if (is_broadcast_ether_addr(hdr->addr1) || 392 is_multicast_ether_addr(hdr->addr1)) 393 return; 394 395 if (accu_dev) 396 __rtw89_traffic_stats_accu(&rtwdev->stats, skb, tx); 397 398 if (rtwvif) { 399 __rtw89_traffic_stats_accu(&rtwvif->stats, skb, tx); 400 __rtw89_traffic_stats_accu(&rtwvif->stats_ps, skb, tx); 401 } 402 } 403 404 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef) 405 { 406 cfg80211_chandef_create(chandef, &rtw89_channels_2ghz[0], 407 NL80211_CHAN_NO_HT); 408 } 409 410 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef, 411 struct rtw89_chan *chan) 412 { 413 struct ieee80211_channel *channel = chandef->chan; 414 enum nl80211_chan_width width = chandef->width; 415 u32 primary_freq, center_freq; 416 u8 center_chan; 417 u8 bandwidth = RTW89_CHANNEL_WIDTH_20; 418 u32 offset; 419 u8 band; 420 421 center_chan = channel->hw_value; 422 primary_freq = channel->center_freq; 423 center_freq = chandef->center_freq1; 424 425 switch (width) { 426 case NL80211_CHAN_WIDTH_20_NOHT: 427 case NL80211_CHAN_WIDTH_20: 428 bandwidth = RTW89_CHANNEL_WIDTH_20; 429 break; 430 case NL80211_CHAN_WIDTH_40: 431 bandwidth = RTW89_CHANNEL_WIDTH_40; 432 if (primary_freq > center_freq) { 433 center_chan -= 2; 434 } else { 435 center_chan += 2; 436 } 437 break; 438 case NL80211_CHAN_WIDTH_80: 439 case NL80211_CHAN_WIDTH_160: 440 bandwidth = nl_to_rtw89_bandwidth(width); 441 if (primary_freq > center_freq) { 442 offset = (primary_freq - center_freq - 10) / 20; 443 center_chan -= 2 + offset * 4; 444 } else { 445 offset = (center_freq - primary_freq - 10) / 20; 446 center_chan += 2 + offset * 4; 447 } 448 break; 449 default: 450 center_chan = 0; 451 break; 452 } 453 454 switch (channel->band) { 455 default: 456 case NL80211_BAND_2GHZ: 457 band = RTW89_BAND_2G; 458 break; 459 case NL80211_BAND_5GHZ: 460 band = RTW89_BAND_5G; 461 break; 462 case NL80211_BAND_6GHZ: 463 band = RTW89_BAND_6G; 464 break; 465 } 466 467 rtw89_chan_create(chan, center_chan, channel->hw_value, band, bandwidth); 468 } 469 470 static void __rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev, 471 const struct rtw89_chan *chan, 472 enum rtw89_phy_idx phy_idx) 473 { 474 const struct rtw89_chip_info *chip = rtwdev->chip; 475 bool entity_active; 476 477 entity_active = rtw89_get_entity_state(rtwdev, phy_idx); 478 if (!entity_active) 479 return; 480 481 chip->ops->set_txpwr(rtwdev, chan, phy_idx); 482 } 483 484 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev) 485 { 486 struct rtw89_entity_conf conf; 487 488 rtw89_entity_get_conf(rtwdev, &conf); 489 490 __rtw89_core_set_chip_txpwr(rtwdev, conf.chans[0], RTW89_PHY_0); 491 492 if (rtwdev->chip->chip_gen == RTW89_CHIP_AX) 493 return; 494 495 __rtw89_core_set_chip_txpwr(rtwdev, conf.chans[1], RTW89_PHY_1); 496 } 497 498 static void rtw89_core_rfk_record(struct rtw89_dev *rtwdev, 499 struct rtw89_vif_link *rtwvif_link, 500 bool start) 501 { 502 struct rtw89_rfk_wait_info *info = &rtwdev->rfk_wait; 503 struct rtw89_rfk_record *record = &info->records[info->record_idx]; 504 const struct rtw89_chip_info *chip = rtwdev->chip; 505 u8 path_num = min(chip->rf_path_num, RTW89_RFK_RECORD_PATH_NR); 506 int path; 507 508 if (!start) 509 goto end; 510 511 info->record_ptr = record; 512 record->phy_idx = rtwvif_link->phy_idx; 513 514 for (path = 0; path < path_num; path++) { 515 record->ch[path] = rtw89_read_rf(rtwdev, path, RR_CFGCH, 516 RR_CFGCH_BAND0 | RR_CFGCH_CH); 517 record->cv[path] = rtw89_read_rf(rtwdev, path, RR_VCO, 518 RR_VCO_SEL | RR_VCO_STS); 519 record->c5[path] = rtw89_read_rf(rtwdev, path, RR_SYNFB, RFREG_MASK); 520 } 521 522 return; 523 524 end: 525 info->record_idx = (info->record_idx + 1) % RTW89_RFK_RECORD_HISTORY_NR; 526 info->record_ptr = NULL; 527 } 528 529 void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev, 530 struct rtw89_vif_link *rtwvif_link) 531 { 532 const struct rtw89_chip_info *chip = rtwdev->chip; 533 bool mon = !!rtwdev->pure_monitor_mode_vif; 534 bool prehdl_link = false; 535 536 if (chip->chip_gen != RTW89_CHIP_AX && 537 !RTW89_CHK_FW_FEATURE_GROUP(WITH_RFK_PRE_NOTIFY, &rtwdev->fw) && 538 !mon && !rtw89_entity_check_hw(rtwdev, rtwvif_link->phy_idx)) 539 prehdl_link = true; 540 541 if (prehdl_link) { 542 rtw89_entity_force_hw(rtwdev, rtwvif_link->phy_idx); 543 rtw89_set_channel(rtwdev); 544 } 545 546 if (chip->ops->rfk_channel) { 547 rtw89_core_rfk_record(rtwdev, rtwvif_link, true); 548 549 chip->ops->rfk_channel(rtwdev, rtwvif_link); 550 551 rtw89_core_rfk_record(rtwdev, rtwvif_link, false); 552 } 553 554 if (prehdl_link) { 555 rtw89_entity_force_hw(rtwdev, RTW89_PHY_NUM); 556 rtw89_set_channel(rtwdev); 557 } 558 } 559 560 static void rtw89_chip_rfk_channel_for_pure_mon_vif(struct rtw89_dev *rtwdev, 561 enum rtw89_phy_idx phy_idx) 562 { 563 struct rtw89_vif *rtwvif = rtwdev->pure_monitor_mode_vif; 564 struct rtw89_vif_link *rtwvif_link; 565 566 if (!rtwvif) 567 return; 568 569 rtwvif_link = rtw89_vif_get_link_inst(rtwvif, phy_idx); 570 if (!rtwvif_link) 571 return; 572 573 rtw89_chip_rfk_channel(rtwdev, rtwvif_link); 574 } 575 576 static void __rtw89_set_channel(struct rtw89_dev *rtwdev, 577 const struct rtw89_chan *chan, 578 enum rtw89_mac_idx mac_idx, 579 enum rtw89_phy_idx phy_idx) 580 { 581 const struct rtw89_chip_info *chip = rtwdev->chip; 582 const struct rtw89_chan_rcd *chan_rcd; 583 struct rtw89_channel_help_params bak; 584 bool entity_active; 585 586 entity_active = rtw89_get_entity_state(rtwdev, phy_idx); 587 588 chan_rcd = rtw89_chan_rcd_get_by_chan(chan); 589 590 rtw89_chip_set_channel_prepare(rtwdev, &bak, chan, mac_idx, phy_idx); 591 592 chip->ops->set_channel(rtwdev, chan, mac_idx, phy_idx); 593 594 chip->ops->set_txpwr(rtwdev, chan, phy_idx); 595 596 rtw89_chip_set_channel_done(rtwdev, &bak, chan, mac_idx, phy_idx); 597 598 if (!entity_active || chan_rcd->band_changed) { 599 rtw89_btc_ntfy_switch_band(rtwdev, phy_idx, chan->band_type); 600 rtw89_chip_rfk_band_changed(rtwdev, phy_idx, chan); 601 } 602 603 rtw89_set_entity_state(rtwdev, phy_idx, true); 604 605 rtw89_chip_rfk_channel_for_pure_mon_vif(rtwdev, phy_idx); 606 } 607 608 int rtw89_set_channel(struct rtw89_dev *rtwdev) 609 { 610 struct rtw89_entity_conf conf; 611 enum rtw89_entity_mode mode; 612 613 mode = rtw89_entity_recalc(rtwdev); 614 if (mode < 0 || mode >= NUM_OF_RTW89_ENTITY_MODE) { 615 WARN(1, "Invalid ent mode: %d\n", mode); 616 return -EINVAL; 617 } 618 619 rtw89_entity_get_conf(rtwdev, &conf); 620 621 __rtw89_set_channel(rtwdev, conf.chans[0], RTW89_MAC_0, RTW89_PHY_0); 622 623 if (rtwdev->chip->chip_gen == RTW89_CHIP_AX) 624 return 0; 625 626 __rtw89_set_channel(rtwdev, conf.chans[1], RTW89_MAC_1, RTW89_PHY_1); 627 628 return 0; 629 } 630 631 static enum rtw89_core_tx_type 632 rtw89_core_get_tx_type(struct rtw89_dev *rtwdev, 633 struct sk_buff *skb) 634 { 635 struct ieee80211_hdr *hdr = (void *)skb->data; 636 __le16 fc = hdr->frame_control; 637 638 if (ieee80211_is_mgmt(fc) || ieee80211_is_any_nullfunc(fc)) 639 return RTW89_CORE_TX_TYPE_MGMT; 640 641 return RTW89_CORE_TX_TYPE_DATA; 642 } 643 644 static void 645 rtw89_core_tx_update_ampdu_info(struct rtw89_dev *rtwdev, 646 struct rtw89_core_tx_request *tx_req, 647 enum btc_pkt_type pkt_type) 648 { 649 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 650 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 651 struct ieee80211_link_sta *link_sta; 652 struct sk_buff *skb = tx_req->skb; 653 struct rtw89_sta *rtwsta; 654 u8 ampdu_num; 655 u8 tid; 656 657 if (pkt_type == PACKET_EAPOL) { 658 desc_info->bk = true; 659 return; 660 } 661 662 if (!(IEEE80211_SKB_CB(skb)->flags & IEEE80211_TX_CTL_AMPDU)) 663 return; 664 665 if (!rtwsta_link) { 666 rtw89_warn(rtwdev, "cannot set ampdu info without sta\n"); 667 return; 668 } 669 670 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; 671 rtwsta = rtwsta_link->rtwsta; 672 673 rcu_read_lock(); 674 675 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false); 676 ampdu_num = (u8)((rtwsta->ampdu_params[tid].agg_num ? 677 rtwsta->ampdu_params[tid].agg_num : 678 4 << link_sta->ht_cap.ampdu_factor) - 1); 679 680 desc_info->agg_en = true; 681 desc_info->ampdu_density = link_sta->ht_cap.ampdu_density; 682 desc_info->ampdu_num = ampdu_num; 683 684 rcu_read_unlock(); 685 } 686 687 static void 688 rtw89_core_tx_update_sec_key(struct rtw89_dev *rtwdev, 689 struct rtw89_core_tx_request *tx_req) 690 { 691 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 692 const struct rtw89_chip_info *chip = rtwdev->chip; 693 const struct rtw89_sec_cam_entry *sec_cam; 694 struct ieee80211_tx_info *info; 695 struct ieee80211_key_conf *key; 696 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 697 struct sk_buff *skb = tx_req->skb; 698 u8 sec_type = RTW89_SEC_KEY_TYPE_NONE; 699 u8 sec_cam_idx; 700 u64 pn64; 701 702 info = IEEE80211_SKB_CB(skb); 703 key = info->control.hw_key; 704 sec_cam_idx = key->hw_key_idx; 705 sec_cam = cam_info->sec_entries[sec_cam_idx]; 706 if (!sec_cam) { 707 rtw89_warn(rtwdev, "sec cam entry is empty\n"); 708 return; 709 } 710 711 switch (key->cipher) { 712 case WLAN_CIPHER_SUITE_WEP40: 713 sec_type = RTW89_SEC_KEY_TYPE_WEP40; 714 break; 715 case WLAN_CIPHER_SUITE_WEP104: 716 sec_type = RTW89_SEC_KEY_TYPE_WEP104; 717 break; 718 case WLAN_CIPHER_SUITE_TKIP: 719 sec_type = RTW89_SEC_KEY_TYPE_TKIP; 720 break; 721 case WLAN_CIPHER_SUITE_CCMP: 722 sec_type = RTW89_SEC_KEY_TYPE_CCMP128; 723 break; 724 case WLAN_CIPHER_SUITE_CCMP_256: 725 sec_type = RTW89_SEC_KEY_TYPE_CCMP256; 726 break; 727 case WLAN_CIPHER_SUITE_GCMP: 728 sec_type = RTW89_SEC_KEY_TYPE_GCMP128; 729 break; 730 case WLAN_CIPHER_SUITE_GCMP_256: 731 sec_type = RTW89_SEC_KEY_TYPE_GCMP256; 732 break; 733 default: 734 rtw89_warn(rtwdev, "key cipher not supported %d\n", key->cipher); 735 return; 736 } 737 738 desc_info->sec_en = true; 739 desc_info->sec_keyid = key->keyidx; 740 desc_info->sec_type = sec_type; 741 desc_info->sec_cam_idx = sec_cam->sec_cam_idx; 742 743 if (!chip->hw_sec_hdr) 744 return; 745 746 pn64 = atomic64_inc_return(&key->tx_pn); 747 desc_info->sec_seq[0] = pn64; 748 desc_info->sec_seq[1] = pn64 >> 8; 749 desc_info->sec_seq[2] = pn64 >> 16; 750 desc_info->sec_seq[3] = pn64 >> 24; 751 desc_info->sec_seq[4] = pn64 >> 32; 752 desc_info->sec_seq[5] = pn64 >> 40; 753 desc_info->wp_offset = 1; /* in unit of 8 bytes for security header */ 754 } 755 756 static u16 rtw89_core_get_mgmt_rate(struct rtw89_dev *rtwdev, 757 struct rtw89_core_tx_request *tx_req, 758 const struct rtw89_chan *chan) 759 { 760 struct sk_buff *skb = tx_req->skb; 761 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link; 762 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 763 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 764 struct ieee80211_vif *vif = tx_info->control.vif; 765 struct ieee80211_bss_conf *bss_conf; 766 u16 lowest_rate; 767 u16 rate; 768 769 if (tx_info->flags & IEEE80211_TX_CTL_NO_CCK_RATE || 770 (vif && vif->p2p)) 771 lowest_rate = RTW89_HW_RATE_OFDM6; 772 else if (chan->band_type == RTW89_BAND_2G) 773 lowest_rate = RTW89_HW_RATE_CCK1; 774 else 775 lowest_rate = RTW89_HW_RATE_OFDM6; 776 777 if (!rtwvif_link) 778 return lowest_rate; 779 780 rcu_read_lock(); 781 782 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false); 783 if (!bss_conf->basic_rates || !rtwsta_link) { 784 rate = lowest_rate; 785 goto out; 786 } 787 788 rate = __ffs(bss_conf->basic_rates) + lowest_rate; 789 790 out: 791 rcu_read_unlock(); 792 793 return rate; 794 } 795 796 static u8 rtw89_core_tx_get_mac_id(struct rtw89_dev *rtwdev, 797 struct rtw89_core_tx_request *tx_req) 798 { 799 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 800 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link; 801 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 802 803 if (desc_info->mlo && !desc_info->sw_mld) { 804 if (rtwsta_link) 805 return rtw89_sta_get_main_macid(rtwsta_link->rtwsta); 806 else 807 return rtw89_vif_get_main_macid(rtwvif_link->rtwvif); 808 } 809 810 if (!rtwsta_link) 811 return rtwvif_link->mac_id; 812 813 return rtwsta_link->mac_id; 814 } 815 816 static void rtw89_core_tx_update_llc_hdr(struct rtw89_dev *rtwdev, 817 struct rtw89_tx_desc_info *desc_info, 818 struct sk_buff *skb) 819 { 820 struct ieee80211_hdr *hdr = (void *)skb->data; 821 __le16 fc = hdr->frame_control; 822 823 desc_info->hdr_llc_len = ieee80211_hdrlen(fc); 824 desc_info->hdr_llc_len >>= 1; /* in unit of 2 bytes */ 825 } 826 827 u8 rtw89_core_get_ch_dma(struct rtw89_dev *rtwdev, u8 qsel) 828 { 829 switch (qsel) { 830 default: 831 rtw89_warn(rtwdev, "Cannot map qsel to dma: %d\n", qsel); 832 fallthrough; 833 case RTW89_TX_QSEL_BE_0: 834 case RTW89_TX_QSEL_BE_1: 835 case RTW89_TX_QSEL_BE_2: 836 case RTW89_TX_QSEL_BE_3: 837 return RTW89_TXCH_ACH0; 838 case RTW89_TX_QSEL_BK_0: 839 case RTW89_TX_QSEL_BK_1: 840 case RTW89_TX_QSEL_BK_2: 841 case RTW89_TX_QSEL_BK_3: 842 return RTW89_TXCH_ACH1; 843 case RTW89_TX_QSEL_VI_0: 844 case RTW89_TX_QSEL_VI_1: 845 case RTW89_TX_QSEL_VI_2: 846 case RTW89_TX_QSEL_VI_3: 847 return RTW89_TXCH_ACH2; 848 case RTW89_TX_QSEL_VO_0: 849 case RTW89_TX_QSEL_VO_1: 850 case RTW89_TX_QSEL_VO_2: 851 case RTW89_TX_QSEL_VO_3: 852 return RTW89_TXCH_ACH3; 853 case RTW89_TX_QSEL_B0_MGMT: 854 return RTW89_TXCH_CH8; 855 case RTW89_TX_QSEL_B0_HI: 856 return RTW89_TXCH_CH9; 857 case RTW89_TX_QSEL_B1_MGMT: 858 return RTW89_TXCH_CH10; 859 case RTW89_TX_QSEL_B1_HI: 860 return RTW89_TXCH_CH11; 861 } 862 } 863 EXPORT_SYMBOL(rtw89_core_get_ch_dma); 864 865 u8 rtw89_core_get_ch_dma_v1(struct rtw89_dev *rtwdev, u8 qsel) 866 { 867 switch (qsel) { 868 default: 869 rtw89_warn(rtwdev, "Cannot map qsel to dma v1: %d\n", qsel); 870 fallthrough; 871 case RTW89_TX_QSEL_BE_0: 872 case RTW89_TX_QSEL_BK_0: 873 return RTW89_TXCH_ACH0; 874 case RTW89_TX_QSEL_VI_0: 875 case RTW89_TX_QSEL_VO_0: 876 return RTW89_TXCH_ACH2; 877 case RTW89_TX_QSEL_B0_MGMT: 878 case RTW89_TX_QSEL_B0_HI: 879 return RTW89_TXCH_CH8; 880 case RTW89_TX_QSEL_B1_MGMT: 881 case RTW89_TX_QSEL_B1_HI: 882 return RTW89_TXCH_CH10; 883 } 884 } 885 EXPORT_SYMBOL(rtw89_core_get_ch_dma_v1); 886 887 u8 rtw89_core_get_ch_dma_v2(struct rtw89_dev *rtwdev, u8 qsel) 888 { 889 switch (qsel) { 890 default: 891 rtw89_warn(rtwdev, "Cannot map qsel to dma v2: %d\n", qsel); 892 fallthrough; 893 case RTW89_TX_QSEL_BE_0: 894 case RTW89_TX_QSEL_VO_0: 895 return RTW89_TXCH_ACH0; 896 case RTW89_TX_QSEL_BK_0: 897 case RTW89_TX_QSEL_VI_0: 898 return RTW89_TXCH_ACH2; 899 case RTW89_TX_QSEL_B0_MGMT: 900 case RTW89_TX_QSEL_B0_HI: 901 return RTW89_TXCH_CH8; 902 case RTW89_TX_QSEL_B1_MGMT: 903 case RTW89_TX_QSEL_B1_HI: 904 return RTW89_TXCH_CH10; 905 } 906 } 907 EXPORT_SYMBOL(rtw89_core_get_ch_dma_v2); 908 909 static void 910 rtw89_core_tx_update_mgmt_info(struct rtw89_dev *rtwdev, 911 struct rtw89_core_tx_request *tx_req) 912 { 913 const struct rtw89_chip_info *chip = rtwdev->chip; 914 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link; 915 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 916 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 917 rtwvif_link->chanctx_idx); 918 struct sk_buff *skb = tx_req->skb; 919 u8 qsel, ch_dma; 920 921 qsel = rtw89_core_get_qsel_mgmt(rtwdev, tx_req); 922 ch_dma = rtw89_chip_get_ch_dma(rtwdev, qsel); 923 924 desc_info->qsel = qsel; 925 desc_info->ch_dma = ch_dma; 926 desc_info->sw_mld = true; 927 desc_info->port = desc_info->hiq ? rtwvif_link->port : 0; 928 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req); 929 desc_info->hw_ssn_sel = RTW89_MGMT_HW_SSN_SEL; 930 desc_info->hw_seq_mode = RTW89_MGMT_HW_SEQ_MODE; 931 932 /* fixed data rate for mgmt frames */ 933 desc_info->en_wd_info = true; 934 desc_info->use_rate = true; 935 desc_info->dis_data_fb = true; 936 desc_info->data_rate = rtw89_core_get_mgmt_rate(rtwdev, tx_req, chan); 937 938 if (chip->hw_mgmt_tx_encrypt && IEEE80211_SKB_CB(skb)->control.hw_key) { 939 rtw89_core_tx_update_sec_key(rtwdev, tx_req); 940 rtw89_core_tx_update_llc_hdr(rtwdev, desc_info, skb); 941 } 942 943 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 944 "tx mgmt frame with rate 0x%x on channel %d (band %d, bw %d)\n", 945 desc_info->data_rate, chan->channel, chan->band_type, 946 chan->band_width); 947 } 948 949 static void 950 rtw89_core_tx_update_h2c_info(struct rtw89_dev *rtwdev, 951 struct rtw89_core_tx_request *tx_req) 952 { 953 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 954 955 desc_info->is_bmc = false; 956 desc_info->wd_page = false; 957 desc_info->ch_dma = RTW89_DMA_H2C; 958 } 959 960 static void rtw89_core_get_no_ul_ofdma_htc(struct rtw89_dev *rtwdev, __le32 *htc, 961 const struct rtw89_chan *chan) 962 { 963 static const u8 rtw89_bandwidth_to_om[] = { 964 [RTW89_CHANNEL_WIDTH_20] = HTC_OM_CHANNEL_WIDTH_20, 965 [RTW89_CHANNEL_WIDTH_40] = HTC_OM_CHANNEL_WIDTH_40, 966 [RTW89_CHANNEL_WIDTH_80] = HTC_OM_CHANNEL_WIDTH_80, 967 [RTW89_CHANNEL_WIDTH_160] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80, 968 [RTW89_CHANNEL_WIDTH_80_80] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80, 969 }; 970 const struct rtw89_chip_info *chip = rtwdev->chip; 971 struct rtw89_hal *hal = &rtwdev->hal; 972 u8 om_bandwidth; 973 974 if (!chip->dis_2g_40m_ul_ofdma || 975 chan->band_type != RTW89_BAND_2G || 976 chan->band_width != RTW89_CHANNEL_WIDTH_40) 977 return; 978 979 om_bandwidth = chan->band_width < ARRAY_SIZE(rtw89_bandwidth_to_om) ? 980 rtw89_bandwidth_to_om[chan->band_width] : 0; 981 *htc = le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) | 982 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_OM, RTW89_HTC_MASK_CTL_ID) | 983 le32_encode_bits(hal->rx_nss - 1, RTW89_HTC_MASK_HTC_OM_RX_NSS) | 984 le32_encode_bits(om_bandwidth, RTW89_HTC_MASK_HTC_OM_CH_WIDTH) | 985 le32_encode_bits(1, RTW89_HTC_MASK_HTC_OM_UL_MU_DIS) | 986 le32_encode_bits(hal->tx_nss - 1, RTW89_HTC_MASK_HTC_OM_TX_NSTS) | 987 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_ER_SU_DIS) | 988 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR) | 989 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS); 990 } 991 992 static bool 993 __rtw89_core_tx_check_he_qos_htc(struct rtw89_dev *rtwdev, 994 struct rtw89_core_tx_request *tx_req, 995 enum btc_pkt_type pkt_type) 996 { 997 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 998 struct ieee80211_vif *vif = tx_req->vif; 999 struct sk_buff *skb = tx_req->skb; 1000 struct ieee80211_hdr *hdr = (void *)skb->data; 1001 struct ieee80211_link_sta *link_sta; 1002 __le16 fc = hdr->frame_control; 1003 1004 /* AP IOT issue with EAPoL, ARP and DHCP */ 1005 if (pkt_type < PACKET_MAX) 1006 return false; 1007 1008 if (!rtwsta_link) 1009 return false; 1010 1011 rcu_read_lock(); 1012 1013 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false); 1014 if (!link_sta->he_cap.has_he) { 1015 rcu_read_unlock(); 1016 return false; 1017 } 1018 1019 rcu_read_unlock(); 1020 1021 if (!ieee80211_is_data_qos(fc)) 1022 return false; 1023 1024 if (skb_headroom(skb) < IEEE80211_HT_CTL_LEN) 1025 return false; 1026 1027 if (rtwsta_link && rtwsta_link->ra_report.might_fallback_legacy) 1028 return false; 1029 1030 if (vif->type == NL80211_IFTYPE_AP) 1031 return false; 1032 1033 return true; 1034 } 1035 1036 static void 1037 __rtw89_core_tx_adjust_he_qos_htc(struct rtw89_dev *rtwdev, 1038 struct rtw89_core_tx_request *tx_req) 1039 { 1040 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 1041 struct sk_buff *skb = tx_req->skb; 1042 struct ieee80211_hdr *hdr = (void *)skb->data; 1043 __le16 fc = hdr->frame_control; 1044 void *data; 1045 __le32 *htc; 1046 u8 *qc; 1047 int hdr_len; 1048 1049 hdr_len = ieee80211_has_a4(fc) ? 32 : 26; 1050 data = skb_push(skb, IEEE80211_HT_CTL_LEN); 1051 memmove(data, data + IEEE80211_HT_CTL_LEN, hdr_len); 1052 1053 hdr = data; 1054 htc = data + hdr_len; 1055 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_ORDER); 1056 *htc = rtwsta_link->htc_template ? rtwsta_link->htc_template : 1057 le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) | 1058 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_CAS, RTW89_HTC_MASK_CTL_ID); 1059 1060 qc = data + hdr_len - IEEE80211_QOS_CTL_LEN; 1061 qc[0] |= IEEE80211_QOS_CTL_EOSP; 1062 } 1063 1064 static void 1065 rtw89_core_tx_update_he_qos_htc(struct rtw89_dev *rtwdev, 1066 struct rtw89_core_tx_request *tx_req, 1067 enum btc_pkt_type pkt_type) 1068 { 1069 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 1070 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link; 1071 1072 if (!__rtw89_core_tx_check_he_qos_htc(rtwdev, tx_req, pkt_type)) 1073 goto desc_bk; 1074 1075 __rtw89_core_tx_adjust_he_qos_htc(rtwdev, tx_req); 1076 1077 desc_info->pkt_size += IEEE80211_HT_CTL_LEN; 1078 desc_info->a_ctrl_bsr = true; 1079 1080 desc_bk: 1081 if (!rtwvif_link || rtwvif_link->last_a_ctrl == desc_info->a_ctrl_bsr) 1082 return; 1083 1084 rtwvif_link->last_a_ctrl = desc_info->a_ctrl_bsr; 1085 desc_info->bk = true; 1086 } 1087 1088 static u16 rtw89_core_get_data_rate(struct rtw89_dev *rtwdev, 1089 struct rtw89_core_tx_request *tx_req) 1090 { 1091 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link; 1092 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 1093 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 1094 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif_link->rate_pattern; 1095 enum rtw89_chanctx_idx idx = rtwvif_link->chanctx_idx; 1096 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, idx); 1097 struct ieee80211_link_sta *link_sta; 1098 u16 lowest_rate; 1099 u16 rate; 1100 1101 if (rate_pattern->enable) 1102 return rate_pattern->rate; 1103 1104 if (vif->p2p) 1105 lowest_rate = RTW89_HW_RATE_OFDM6; 1106 else if (chan->band_type == RTW89_BAND_2G) 1107 lowest_rate = RTW89_HW_RATE_CCK1; 1108 else 1109 lowest_rate = RTW89_HW_RATE_OFDM6; 1110 1111 if (!rtwsta_link) 1112 return lowest_rate; 1113 1114 rcu_read_lock(); 1115 1116 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false); 1117 if (!link_sta->supp_rates[chan->band_type]) { 1118 rate = lowest_rate; 1119 goto out; 1120 } 1121 1122 rate = __ffs(link_sta->supp_rates[chan->band_type]) + lowest_rate; 1123 1124 out: 1125 rcu_read_unlock(); 1126 1127 return rate; 1128 } 1129 1130 static void 1131 rtw89_core_tx_update_data_info(struct rtw89_dev *rtwdev, 1132 struct rtw89_core_tx_request *tx_req) 1133 { 1134 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link; 1135 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 1136 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 1137 struct sk_buff *skb = tx_req->skb; 1138 u8 tid, tid_indicate; 1139 u8 qsel, ch_dma; 1140 1141 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; 1142 tid_indicate = rtw89_core_get_tid_indicate(rtwdev, tid); 1143 qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : rtw89_core_get_qsel(rtwdev, tid); 1144 ch_dma = rtw89_chip_get_ch_dma(rtwdev, qsel); 1145 1146 desc_info->ch_dma = ch_dma; 1147 desc_info->tid_indicate = tid_indicate; 1148 desc_info->qsel = qsel; 1149 desc_info->sw_mld = false; 1150 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req); 1151 desc_info->port = desc_info->hiq ? rtwvif_link->port : 0; 1152 desc_info->er_cap = rtwsta_link ? rtwsta_link->er_cap : false; 1153 desc_info->stbc = rtwsta_link ? rtwsta_link->ra.stbc_cap : false; 1154 desc_info->ldpc = rtwsta_link ? rtwsta_link->ra.ldpc_cap : false; 1155 1156 /* enable wd_info for AMPDU */ 1157 desc_info->en_wd_info = true; 1158 1159 if (IEEE80211_SKB_CB(skb)->control.hw_key) 1160 rtw89_core_tx_update_sec_key(rtwdev, tx_req); 1161 1162 desc_info->data_retry_lowest_rate = rtw89_core_get_data_rate(rtwdev, tx_req); 1163 } 1164 1165 static enum btc_pkt_type 1166 rtw89_core_tx_btc_spec_pkt_notify(struct rtw89_dev *rtwdev, 1167 struct rtw89_core_tx_request *tx_req) 1168 { 1169 struct wiphy *wiphy = rtwdev->hw->wiphy; 1170 struct sk_buff *skb = tx_req->skb; 1171 struct udphdr *udphdr; 1172 1173 if (IEEE80211_SKB_CB(skb)->control.flags & IEEE80211_TX_CTRL_PORT_CTRL_PROTO) { 1174 wiphy_work_queue(wiphy, &rtwdev->btc.eapol_notify_work); 1175 return PACKET_EAPOL; 1176 } 1177 1178 if (skb->protocol == htons(ETH_P_ARP)) { 1179 wiphy_work_queue(wiphy, &rtwdev->btc.arp_notify_work); 1180 return PACKET_ARP; 1181 } 1182 1183 if (skb->protocol == htons(ETH_P_IP) && 1184 ip_hdr(skb)->protocol == IPPROTO_UDP) { 1185 udphdr = udp_hdr(skb); 1186 if (((udphdr->source == htons(67) && udphdr->dest == htons(68)) || 1187 (udphdr->source == htons(68) && udphdr->dest == htons(67))) && 1188 skb->len > 282) { 1189 wiphy_work_queue(wiphy, &rtwdev->btc.dhcp_notify_work); 1190 return PACKET_DHCP; 1191 } 1192 } 1193 1194 if (skb->protocol == htons(ETH_P_IP) && 1195 ip_hdr(skb)->protocol == IPPROTO_ICMP) { 1196 wiphy_work_queue(wiphy, &rtwdev->btc.icmp_notify_work); 1197 return PACKET_ICMP; 1198 } 1199 1200 return PACKET_MAX; 1201 } 1202 1203 static void 1204 rtw89_core_tx_wake(struct rtw89_dev *rtwdev, 1205 struct rtw89_core_tx_request *tx_req) 1206 { 1207 const struct rtw89_chip_info *chip = rtwdev->chip; 1208 1209 if (!RTW89_CHK_FW_FEATURE(TX_WAKE, &rtwdev->fw)) 1210 return; 1211 1212 switch (chip->chip_id) { 1213 case RTL8852BT: 1214 if (test_bit(RTW89_FLAG_LEISURE_PS, rtwdev->flags)) 1215 goto notify; 1216 break; 1217 case RTL8852C: 1218 if (test_bit(RTW89_FLAG_LOW_POWER_MODE, rtwdev->flags)) 1219 goto notify; 1220 break; 1221 default: 1222 if (test_bit(RTW89_FLAG_LOW_POWER_MODE, rtwdev->flags) && 1223 tx_req->tx_type == RTW89_CORE_TX_TYPE_MGMT) 1224 goto notify; 1225 break; 1226 } 1227 1228 return; 1229 1230 notify: 1231 rtw89_mac_notify_wake(rtwdev); 1232 } 1233 1234 static void rtw89_core_tx_update_injection(struct rtw89_dev *rtwdev, 1235 struct rtw89_core_tx_request *tx_req, 1236 struct ieee80211_tx_info *info) 1237 { 1238 const struct rtw89_hw_rate_def *hw_rate = &rtw89_hw_rate[rtwdev->chip->chip_gen]; 1239 enum mac80211_rate_control_flags flags = info->control.rates[0].flags; 1240 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 1241 const struct rtw89_chan *chan; 1242 u8 idx = info->control.rates[0].idx; 1243 u8 nss, mcs; 1244 1245 desc_info->use_rate = true; 1246 desc_info->dis_data_fb = true; 1247 1248 if (flags & IEEE80211_TX_RC_160_MHZ_WIDTH) 1249 desc_info->data_bw = 3; 1250 else if (flags & IEEE80211_TX_RC_80_MHZ_WIDTH) 1251 desc_info->data_bw = 2; 1252 else if (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 1253 desc_info->data_bw = 1; 1254 1255 if (flags & IEEE80211_TX_RC_SHORT_GI) 1256 desc_info->gi_ltf = 1; 1257 1258 if (flags & IEEE80211_TX_RC_VHT_MCS) { 1259 nss = umin(idx >> 4, ARRAY_SIZE(hw_rate->vht) - 1); 1260 mcs = idx & 0xf; 1261 desc_info->data_rate = hw_rate->vht[nss] + mcs; 1262 } else if (flags & IEEE80211_TX_RC_MCS) { 1263 desc_info->data_rate = hw_rate->ht + idx; 1264 } else { 1265 chan = rtw89_chan_get(rtwdev, tx_req->rtwvif_link->chanctx_idx); 1266 1267 desc_info->data_rate = idx + (chan->band_type == RTW89_BAND_2G ? 1268 RTW89_HW_RATE_CCK1 : RTW89_HW_RATE_OFDM6); 1269 } 1270 } 1271 1272 static void 1273 rtw89_core_tx_update_desc_info(struct rtw89_dev *rtwdev, 1274 struct rtw89_core_tx_request *tx_req) 1275 { 1276 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 1277 struct sk_buff *skb = tx_req->skb; 1278 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1279 struct ieee80211_hdr *hdr = (void *)skb->data; 1280 struct rtw89_addr_cam_entry *addr_cam; 1281 enum btc_pkt_type pkt_type; 1282 bool upd_wlan_hdr = false; 1283 bool is_bmc; 1284 u16 seq; 1285 1286 desc_info->pkt_size = skb->len; 1287 1288 if (unlikely(tx_req->tx_type == RTW89_CORE_TX_TYPE_FWCMD)) { 1289 rtw89_core_tx_update_h2c_info(rtwdev, tx_req); 1290 return; 1291 } 1292 1293 tx_req->tx_type = rtw89_core_get_tx_type(rtwdev, skb); 1294 1295 if (tx_req->sta) 1296 desc_info->mlo = tx_req->sta->mlo; 1297 else if (tx_req->vif) 1298 desc_info->mlo = ieee80211_vif_is_mld(tx_req->vif); 1299 1300 seq = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4; 1301 addr_cam = rtw89_get_addr_cam_of(tx_req->rtwvif_link, 1302 tx_req->rtwsta_link); 1303 if (addr_cam->valid && desc_info->mlo) 1304 upd_wlan_hdr = true; 1305 1306 if (info->flags & IEEE80211_TX_CTL_REQ_TX_STATUS || tx_req->with_wait) 1307 rtw89_tx_rpt_init(rtwdev, tx_req); 1308 1309 is_bmc = (is_broadcast_ether_addr(hdr->addr1) || 1310 is_multicast_ether_addr(hdr->addr1)); 1311 1312 desc_info->seq = seq; 1313 desc_info->is_bmc = is_bmc; 1314 desc_info->wd_page = true; 1315 desc_info->hiq = info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM; 1316 desc_info->upd_wlan_hdr = upd_wlan_hdr; 1317 1318 switch (tx_req->tx_type) { 1319 case RTW89_CORE_TX_TYPE_MGMT: 1320 rtw89_core_tx_update_mgmt_info(rtwdev, tx_req); 1321 break; 1322 case RTW89_CORE_TX_TYPE_DATA: 1323 rtw89_core_tx_update_data_info(rtwdev, tx_req); 1324 pkt_type = rtw89_core_tx_btc_spec_pkt_notify(rtwdev, tx_req); 1325 rtw89_core_tx_update_he_qos_htc(rtwdev, tx_req, pkt_type); 1326 rtw89_core_tx_update_ampdu_info(rtwdev, tx_req, pkt_type); 1327 rtw89_core_tx_update_llc_hdr(rtwdev, desc_info, skb); 1328 break; 1329 default: 1330 break; 1331 } 1332 1333 if (unlikely(info->flags & IEEE80211_TX_CTL_INJECTED)) 1334 rtw89_core_tx_update_injection(rtwdev, tx_req, info); 1335 } 1336 1337 static void rtw89_tx_wait_work(struct wiphy *wiphy, struct wiphy_work *work) 1338 { 1339 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 1340 tx_wait_work.work); 1341 1342 rtw89_tx_wait_list_clear(rtwdev); 1343 } 1344 1345 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel) 1346 { 1347 u8 ch_dma; 1348 1349 ch_dma = rtw89_chip_get_ch_dma(rtwdev, qsel); 1350 1351 rtw89_hci_tx_kick_off(rtwdev, ch_dma); 1352 } 1353 1354 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb, 1355 struct rtw89_tx_wait_info *wait, int qsel, 1356 unsigned int timeout) 1357 { 1358 unsigned long time_left; 1359 int ret = 0; 1360 1361 lockdep_assert_wiphy(rtwdev->hw->wiphy); 1362 1363 rtw89_core_tx_kick_off(rtwdev, qsel); 1364 time_left = wait_for_completion_timeout(&wait->completion, 1365 msecs_to_jiffies(timeout)); 1366 1367 if (time_left == 0) { 1368 ret = -ETIMEDOUT; 1369 list_add_tail(&wait->list, &rtwdev->tx_waits); 1370 wiphy_delayed_work_queue(rtwdev->hw->wiphy, &rtwdev->tx_wait_work, 1371 RTW89_TX_WAIT_WORK_TIMEOUT); 1372 } else { 1373 if (!wait->tx_done) 1374 ret = -EAGAIN; 1375 rtw89_tx_wait_release(wait); 1376 } 1377 1378 return ret; 1379 } 1380 1381 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 1382 struct sk_buff *skb, bool fwdl) 1383 { 1384 struct rtw89_core_tx_request tx_req = {0}; 1385 u32 cnt; 1386 int ret; 1387 1388 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) { 1389 rtw89_debug(rtwdev, RTW89_DBG_FW, 1390 "ignore h2c due to power is off with firmware state=%d\n", 1391 test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)); 1392 dev_kfree_skb(skb); 1393 return 0; 1394 } 1395 1396 tx_req.skb = skb; 1397 tx_req.tx_type = RTW89_CORE_TX_TYPE_FWCMD; 1398 if (fwdl) 1399 tx_req.desc_info.fw_dl = true; 1400 1401 rtw89_core_tx_update_desc_info(rtwdev, &tx_req); 1402 1403 if (!fwdl) 1404 rtw89_hex_dump(rtwdev, RTW89_DBG_FW, "H2C: ", skb->data, skb->len); 1405 1406 cnt = rtw89_hci_check_and_reclaim_tx_resource(rtwdev, RTW89_TXCH_CH12); 1407 if (cnt == 0) { 1408 rtw89_err(rtwdev, "no tx fwcmd resource\n"); 1409 return -ENOSPC; 1410 } 1411 1412 ret = rtw89_hci_tx_write(rtwdev, &tx_req); 1413 if (ret) { 1414 rtw89_err(rtwdev, "failed to transmit skb to HCI\n"); 1415 return ret; 1416 } 1417 rtw89_hci_tx_kick_off(rtwdev, RTW89_TXCH_CH12); 1418 1419 return 0; 1420 } 1421 1422 static int rtw89_core_tx_write_link(struct rtw89_dev *rtwdev, 1423 struct rtw89_vif_link *rtwvif_link, 1424 struct rtw89_sta_link *rtwsta_link, 1425 struct sk_buff *skb, int *qsel, 1426 struct rtw89_tx_wait_info *wait) 1427 { 1428 struct ieee80211_sta *sta = rtwsta_link_to_sta_safe(rtwsta_link); 1429 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 1430 struct rtw89_tx_skb_data *skb_data = RTW89_TX_SKB_CB(skb); 1431 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 1432 struct rtw89_core_tx_request tx_req = {}; 1433 int ret; 1434 1435 tx_req.skb = skb; 1436 tx_req.vif = vif; 1437 tx_req.sta = sta; 1438 tx_req.rtwvif_link = rtwvif_link; 1439 tx_req.rtwsta_link = rtwsta_link; 1440 tx_req.with_wait = !!wait; 1441 1442 rtw89_traffic_stats_accu(rtwdev, rtwvif, skb, true, true); 1443 rtw89_wow_parse_akm(rtwdev, skb); 1444 rtw89_core_tx_update_desc_info(rtwdev, &tx_req); 1445 rtw89_core_tx_wake(rtwdev, &tx_req); 1446 1447 rcu_assign_pointer(skb_data->wait, wait); 1448 1449 ret = rtw89_hci_tx_write(rtwdev, &tx_req); 1450 if (ret) { 1451 rtw89_err(rtwdev, "failed to transmit skb to HCI\n"); 1452 return ret; 1453 } 1454 1455 if (qsel) 1456 *qsel = tx_req.desc_info.qsel; 1457 1458 return 0; 1459 } 1460 1461 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 1462 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel) 1463 { 1464 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 1465 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif); 1466 struct rtw89_sta_link *rtwsta_link = NULL; 1467 struct rtw89_vif_link *rtwvif_link; 1468 1469 if (rtwsta) { 1470 rtwsta_link = rtw89_get_designated_link(rtwsta); 1471 if (unlikely(!rtwsta_link)) { 1472 rtw89_err(rtwdev, "tx: find no sta designated link\n"); 1473 return -ENOLINK; 1474 } 1475 1476 rtwvif_link = rtwsta_link->rtwvif_link; 1477 } else { 1478 rtwvif_link = rtw89_get_designated_link(rtwvif); 1479 if (unlikely(!rtwvif_link)) { 1480 rtw89_err(rtwdev, "tx: find no vif designated link\n"); 1481 return -ENOLINK; 1482 } 1483 } 1484 1485 return rtw89_core_tx_write_link(rtwdev, rtwvif_link, rtwsta_link, skb, qsel, NULL); 1486 } 1487 1488 static __le32 rtw89_build_txwd_body0(struct rtw89_tx_desc_info *desc_info) 1489 { 1490 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET, desc_info->wp_offset) | 1491 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) | 1492 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) | 1493 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 1494 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) | 1495 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl) | 1496 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_SEL, desc_info->hw_ssn_sel) | 1497 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_MODE, desc_info->hw_seq_mode); 1498 1499 return cpu_to_le32(dword); 1500 } 1501 1502 static __le32 rtw89_build_txwd_body0_v1(struct rtw89_tx_desc_info *desc_info) 1503 { 1504 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) | 1505 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) | 1506 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) | 1507 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 1508 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) | 1509 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl); 1510 1511 return cpu_to_le32(dword); 1512 } 1513 1514 static __le32 rtw89_build_txwd_body1_v1(struct rtw89_tx_desc_info *desc_info) 1515 { 1516 u32 dword = FIELD_PREP(RTW89_TXWD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) | 1517 FIELD_PREP(RTW89_TXWD_BODY1_SEC_KEYID, desc_info->sec_keyid) | 1518 FIELD_PREP(RTW89_TXWD_BODY1_SEC_TYPE, desc_info->sec_type); 1519 1520 return cpu_to_le32(dword); 1521 } 1522 1523 static __le32 rtw89_build_txwd_body2(struct rtw89_tx_desc_info *desc_info) 1524 { 1525 u32 dword = FIELD_PREP(RTW89_TXWD_BODY2_TID_INDICATE, desc_info->tid_indicate) | 1526 FIELD_PREP(RTW89_TXWD_BODY2_QSEL, desc_info->qsel) | 1527 FIELD_PREP(RTW89_TXWD_BODY2_TXPKT_SIZE, desc_info->pkt_size) | 1528 FIELD_PREP(RTW89_TXWD_BODY2_MACID, desc_info->mac_id); 1529 1530 return cpu_to_le32(dword); 1531 } 1532 1533 static __le32 rtw89_build_txwd_body3(struct rtw89_tx_desc_info *desc_info) 1534 { 1535 u32 dword = FIELD_PREP(RTW89_TXWD_BODY3_SW_SEQ, desc_info->seq) | 1536 FIELD_PREP(RTW89_TXWD_BODY3_AGG_EN, desc_info->agg_en) | 1537 FIELD_PREP(RTW89_TXWD_BODY3_BK, desc_info->bk); 1538 1539 return cpu_to_le32(dword); 1540 } 1541 1542 static __le32 rtw89_build_txwd_body4(struct rtw89_tx_desc_info *desc_info) 1543 { 1544 u32 dword = FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) | 1545 FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]); 1546 1547 return cpu_to_le32(dword); 1548 } 1549 1550 static __le32 rtw89_build_txwd_body5(struct rtw89_tx_desc_info *desc_info) 1551 { 1552 u32 dword = FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) | 1553 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) | 1554 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) | 1555 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]); 1556 1557 return cpu_to_le32(dword); 1558 } 1559 1560 static __le32 rtw89_build_txwd_body7_v1(struct rtw89_tx_desc_info *desc_info) 1561 { 1562 u32 dword = FIELD_PREP(RTW89_TXWD_BODY7_USE_RATE_V1, desc_info->use_rate) | 1563 FIELD_PREP(RTW89_TXWD_BODY7_DATA_BW, desc_info->data_bw) | 1564 FIELD_PREP(RTW89_TXWD_BODY7_GI_LTF, desc_info->gi_ltf) | 1565 FIELD_PREP(RTW89_TXWD_BODY7_DATA_RATE, desc_info->data_rate); 1566 1567 return cpu_to_le32(dword); 1568 } 1569 1570 static __le32 rtw89_build_txwd_info0(struct rtw89_tx_desc_info *desc_info) 1571 { 1572 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_USE_RATE, desc_info->use_rate) | 1573 FIELD_PREP(RTW89_TXWD_INFO0_DATA_BW, desc_info->data_bw) | 1574 FIELD_PREP(RTW89_TXWD_INFO0_GI_LTF, desc_info->gi_ltf) | 1575 FIELD_PREP(RTW89_TXWD_INFO0_DATA_RATE, desc_info->data_rate) | 1576 FIELD_PREP(RTW89_TXWD_INFO0_DATA_STBC, desc_info->stbc) | 1577 FIELD_PREP(RTW89_TXWD_INFO0_DATA_LDPC, desc_info->ldpc) | 1578 FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1579 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port); 1580 1581 return cpu_to_le32(dword); 1582 } 1583 1584 static __le32 rtw89_build_txwd_info0_v1(struct rtw89_tx_desc_info *desc_info) 1585 { 1586 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_DATA_STBC, desc_info->stbc) | 1587 FIELD_PREP(RTW89_TXWD_INFO0_DATA_LDPC, desc_info->ldpc) | 1588 FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1589 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port) | 1590 FIELD_PREP(RTW89_TXWD_INFO0_DATA_ER, desc_info->er_cap) | 1591 FIELD_PREP(RTW89_TXWD_INFO0_DATA_BW_ER, 0); 1592 1593 return cpu_to_le32(dword); 1594 } 1595 1596 static __le32 rtw89_build_txwd_info1(struct rtw89_tx_desc_info *desc_info) 1597 { 1598 u32 dword = FIELD_PREP(RTW89_TXWD_INFO1_MAX_AGGNUM, desc_info->ampdu_num) | 1599 FIELD_PREP(RTW89_TXWD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) | 1600 FIELD_PREP(RTW89_TXWD_INFO1_DATA_RTY_LOWEST_RATE, 1601 desc_info->data_retry_lowest_rate) | 1602 FIELD_PREP(RTW89_TXWD_INFO1_DATA_TXCNT_LMT_SEL, 1603 desc_info->tx_cnt_lmt_en) | 1604 FIELD_PREP(RTW89_TXWD_INFO1_DATA_TXCNT_LMT, desc_info->tx_cnt_lmt); 1605 1606 return cpu_to_le32(dword); 1607 } 1608 1609 static __le32 rtw89_build_txwd_info2(struct rtw89_tx_desc_info *desc_info) 1610 { 1611 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1612 FIELD_PREP(RTW89_TXWD_INFO2_SEC_TYPE, desc_info->sec_type) | 1613 FIELD_PREP(RTW89_TXWD_INFO2_SEC_HW_ENC, desc_info->sec_en) | 1614 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1615 1616 return cpu_to_le32(dword); 1617 } 1618 1619 static __le32 rtw89_build_txwd_info2_v1(struct rtw89_tx_desc_info *desc_info) 1620 { 1621 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1622 FIELD_PREP(RTW89_TXWD_INFO2_FORCE_KEY_EN, desc_info->sec_en) | 1623 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1624 1625 return cpu_to_le32(dword); 1626 } 1627 1628 static __le32 rtw89_build_txwd_info3(struct rtw89_tx_desc_info *desc_info) 1629 { 1630 u32 dword = FIELD_PREP(RTW89_TXWD_INFO3_SPE_RPT, desc_info->report); 1631 1632 return cpu_to_le32(dword); 1633 } 1634 1635 static __le32 rtw89_build_txwd_info4(struct rtw89_tx_desc_info *desc_info) 1636 { 1637 bool rts_en = !desc_info->is_bmc; 1638 u32 dword = FIELD_PREP(RTW89_TXWD_INFO4_RTS_EN, rts_en) | 1639 FIELD_PREP(RTW89_TXWD_INFO4_HW_RTS_EN, 1) | 1640 FIELD_PREP(RTW89_TXWD_INFO4_SW_DEFINE, desc_info->sn); 1641 1642 return cpu_to_le32(dword); 1643 } 1644 1645 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 1646 struct rtw89_tx_desc_info *desc_info, 1647 void *txdesc) 1648 { 1649 struct rtw89_txwd_body *txwd_body = (struct rtw89_txwd_body *)txdesc; 1650 struct rtw89_txwd_info *txwd_info; 1651 1652 txwd_body->dword0 = rtw89_build_txwd_body0(desc_info); 1653 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info); 1654 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info); 1655 1656 if (!desc_info->en_wd_info) 1657 return; 1658 1659 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1); 1660 txwd_info->dword0 = rtw89_build_txwd_info0(desc_info); 1661 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info); 1662 txwd_info->dword2 = rtw89_build_txwd_info2(desc_info); 1663 txwd_info->dword3 = rtw89_build_txwd_info3(desc_info); 1664 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info); 1665 1666 } 1667 EXPORT_SYMBOL(rtw89_core_fill_txdesc); 1668 1669 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 1670 struct rtw89_tx_desc_info *desc_info, 1671 void *txdesc) 1672 { 1673 struct rtw89_txwd_body_v1 *txwd_body = (struct rtw89_txwd_body_v1 *)txdesc; 1674 struct rtw89_txwd_info *txwd_info; 1675 1676 txwd_body->dword0 = rtw89_build_txwd_body0_v1(desc_info); 1677 txwd_body->dword1 = rtw89_build_txwd_body1_v1(desc_info); 1678 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info); 1679 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info); 1680 if (desc_info->sec_en) { 1681 txwd_body->dword4 = rtw89_build_txwd_body4(desc_info); 1682 txwd_body->dword5 = rtw89_build_txwd_body5(desc_info); 1683 } 1684 txwd_body->dword7 = rtw89_build_txwd_body7_v1(desc_info); 1685 1686 if (!desc_info->en_wd_info) 1687 return; 1688 1689 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1); 1690 txwd_info->dword0 = rtw89_build_txwd_info0_v1(desc_info); 1691 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info); 1692 txwd_info->dword2 = rtw89_build_txwd_info2_v1(desc_info); 1693 txwd_info->dword3 = rtw89_build_txwd_info3(desc_info); 1694 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info); 1695 } 1696 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v1); 1697 1698 static __le32 rtw89_build_txwd_body0_v2(struct rtw89_tx_desc_info *desc_info) 1699 { 1700 u32 dword = FIELD_PREP(BE_TXD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) | 1701 FIELD_PREP(BE_TXD_BODY0_WDINFO_EN, desc_info->en_wd_info) | 1702 FIELD_PREP(BE_TXD_BODY0_CH_DMA, desc_info->ch_dma) | 1703 FIELD_PREP(BE_TXD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 1704 FIELD_PREP(BE_TXD_BODY0_WD_PAGE, desc_info->wd_page); 1705 1706 return cpu_to_le32(dword); 1707 } 1708 1709 static __le32 rtw89_build_txwd_body1_v2(struct rtw89_tx_desc_info *desc_info) 1710 { 1711 u32 dword = FIELD_PREP(BE_TXD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) | 1712 FIELD_PREP(BE_TXD_BODY1_SEC_KEYID, desc_info->sec_keyid) | 1713 FIELD_PREP(BE_TXD_BODY1_SEC_TYPE, desc_info->sec_type); 1714 1715 return cpu_to_le32(dword); 1716 } 1717 1718 static __le32 rtw89_build_txwd_body2_v2(struct rtw89_tx_desc_info *desc_info) 1719 { 1720 u32 dword = FIELD_PREP(BE_TXD_BODY2_TID_IND, desc_info->tid_indicate) | 1721 FIELD_PREP(BE_TXD_BODY2_QSEL, desc_info->qsel) | 1722 FIELD_PREP(BE_TXD_BODY2_TXPKTSIZE, desc_info->pkt_size) | 1723 FIELD_PREP(BE_TXD_BODY2_AGG_EN, desc_info->agg_en) | 1724 FIELD_PREP(BE_TXD_BODY2_BK, desc_info->bk) | 1725 FIELD_PREP(BE_TXD_BODY2_MACID, desc_info->mac_id); 1726 1727 return cpu_to_le32(dword); 1728 } 1729 1730 static __le32 rtw89_build_txwd_body2_v3(struct rtw89_tx_desc_info *desc_info) 1731 { 1732 u32 dword = FIELD_PREP(BE_TXD_BODY2_TID_IND_V1, desc_info->tid_indicate) | 1733 FIELD_PREP(BE_TXD_BODY2_QSEL_V1, desc_info->qsel) | 1734 FIELD_PREP(BE_TXD_BODY2_TXPKTSIZE, desc_info->pkt_size) | 1735 FIELD_PREP(BE_TXD_BODY2_AGG_EN, desc_info->agg_en) | 1736 FIELD_PREP(BE_TXD_BODY2_MACID_V1, desc_info->mac_id); 1737 1738 return cpu_to_le32(dword); 1739 } 1740 1741 static __le32 rtw89_build_txwd_body3_v2(struct rtw89_tx_desc_info *desc_info) 1742 { 1743 u32 dword = FIELD_PREP(BE_TXD_BODY3_WIFI_SEQ, desc_info->seq) | 1744 FIELD_PREP(BE_TXD_BODY3_MLO_FLAG, desc_info->mlo) | 1745 FIELD_PREP(BE_TXD_BODY3_IS_MLD_SW_EN, desc_info->sw_mld); 1746 1747 return cpu_to_le32(dword); 1748 } 1749 1750 static __le32 rtw89_build_txwd_body3_v3(struct rtw89_tx_desc_info *desc_info) 1751 { 1752 u32 dword = FIELD_PREP(BE_TXD_BODY3_WIFI_SEQ, desc_info->seq) | 1753 FIELD_PREP(BE_TXD_BODY3_MLO_FLAG, desc_info->mlo) | 1754 FIELD_PREP(BE_TXD_BODY3_IS_MLD_SW_EN, desc_info->sw_mld) | 1755 FIELD_PREP(BE_TXD_BODY3_BK_V1, desc_info->bk); 1756 1757 return cpu_to_le32(dword); 1758 } 1759 1760 static __le32 rtw89_build_txwd_body4_v2(struct rtw89_tx_desc_info *desc_info) 1761 { 1762 u32 dword = FIELD_PREP(BE_TXD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) | 1763 FIELD_PREP(BE_TXD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]); 1764 1765 return cpu_to_le32(dword); 1766 } 1767 1768 static __le32 rtw89_build_txwd_body5_v2(struct rtw89_tx_desc_info *desc_info) 1769 { 1770 u32 dword = FIELD_PREP(BE_TXD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) | 1771 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) | 1772 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) | 1773 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]); 1774 1775 return cpu_to_le32(dword); 1776 } 1777 1778 static __le32 rtw89_build_txwd_body6_v2(struct rtw89_tx_desc_info *desc_info) 1779 { 1780 u32 dword = FIELD_PREP(BE_TXD_BODY6_UPD_WLAN_HDR, desc_info->upd_wlan_hdr); 1781 1782 return cpu_to_le32(dword); 1783 } 1784 1785 static __le32 rtw89_build_txwd_body7_v2(struct rtw89_tx_desc_info *desc_info) 1786 { 1787 u32 dword = FIELD_PREP(BE_TXD_BODY7_USERATE_SEL, desc_info->use_rate) | 1788 FIELD_PREP(BE_TXD_BODY7_DATA_BW, desc_info->data_bw) | 1789 FIELD_PREP(BE_TXD_BODY7_GI_LTF, desc_info->gi_ltf) | 1790 FIELD_PREP(BE_TXD_BODY7_DATA_ER, desc_info->er_cap) | 1791 FIELD_PREP(BE_TXD_BODY7_DATA_BW_ER, 0) | 1792 FIELD_PREP(BE_TXD_BODY7_DATARATE, desc_info->data_rate); 1793 1794 return cpu_to_le32(dword); 1795 } 1796 1797 static __le32 rtw89_build_txwd_info0_v2(struct rtw89_tx_desc_info *desc_info) 1798 { 1799 u32 dword = FIELD_PREP(BE_TXD_INFO0_DATA_STBC, desc_info->stbc) | 1800 FIELD_PREP(BE_TXD_INFO0_DATA_LDPC, desc_info->ldpc) | 1801 FIELD_PREP(BE_TXD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1802 FIELD_PREP(BE_TXD_INFO0_MULTIPORT_ID, desc_info->port) | 1803 FIELD_PREP(BE_TXD_INFO0_DATA_TXCNT_LMT_SEL, 1804 desc_info->tx_cnt_lmt_en) | 1805 FIELD_PREP(BE_TXD_INFO0_DATA_TXCNT_LMT, desc_info->tx_cnt_lmt); 1806 1807 return cpu_to_le32(dword); 1808 } 1809 1810 static __le32 rtw89_build_txwd_info1_v2(struct rtw89_tx_desc_info *desc_info) 1811 { 1812 u32 dword = FIELD_PREP(BE_TXD_INFO1_MAX_AGG_NUM, desc_info->ampdu_num) | 1813 FIELD_PREP(BE_TXD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) | 1814 FIELD_PREP(BE_TXD_INFO1_DATA_RTY_LOWEST_RATE, 1815 desc_info->data_retry_lowest_rate) | 1816 FIELD_PREP(BE_TXD_INFO1_SW_DEFINE, desc_info->sn); 1817 1818 return cpu_to_le32(dword); 1819 } 1820 1821 static __le32 rtw89_build_txwd_info2_v2(struct rtw89_tx_desc_info *desc_info) 1822 { 1823 u32 dword = FIELD_PREP(BE_TXD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1824 FIELD_PREP(BE_TXD_INFO2_FORCE_KEY_EN, desc_info->sec_en) | 1825 FIELD_PREP(BE_TXD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx) | 1826 FIELD_PREP(BE_TXD_INFO2_SPE_RPT_V1, desc_info->report); 1827 1828 return cpu_to_le32(dword); 1829 } 1830 1831 static __le32 rtw89_build_txwd_info2_v3(struct rtw89_tx_desc_info *desc_info) 1832 { 1833 u32 dword = FIELD_PREP(BE_TXD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1834 FIELD_PREP(BE_TXD_INFO2_FORCE_KEY_EN_V1, desc_info->sec_en) | 1835 FIELD_PREP(BE_TXD_INFO2_SEC_CAM_IDX_V1, desc_info->sec_cam_idx); 1836 1837 return cpu_to_le32(dword); 1838 } 1839 1840 static __le32 rtw89_build_txwd_info4_v2(struct rtw89_tx_desc_info *desc_info) 1841 { 1842 bool rts_en = !desc_info->is_bmc; 1843 u32 dword = FIELD_PREP(BE_TXD_INFO4_RTS_EN, rts_en) | 1844 FIELD_PREP(BE_TXD_INFO4_HW_RTS_EN, 1); 1845 1846 return cpu_to_le32(dword); 1847 } 1848 1849 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev, 1850 struct rtw89_tx_desc_info *desc_info, 1851 void *txdesc) 1852 { 1853 struct rtw89_txwd_body_v2 *txwd_body = txdesc; 1854 struct rtw89_txwd_info_v2 *txwd_info; 1855 1856 txwd_body->dword0 = rtw89_build_txwd_body0_v2(desc_info); 1857 txwd_body->dword1 = rtw89_build_txwd_body1_v2(desc_info); 1858 txwd_body->dword2 = rtw89_build_txwd_body2_v2(desc_info); 1859 txwd_body->dword3 = rtw89_build_txwd_body3_v2(desc_info); 1860 if (desc_info->sec_en) { 1861 txwd_body->dword4 = rtw89_build_txwd_body4_v2(desc_info); 1862 txwd_body->dword5 = rtw89_build_txwd_body5_v2(desc_info); 1863 } 1864 txwd_body->dword6 = rtw89_build_txwd_body6_v2(desc_info); 1865 txwd_body->dword7 = rtw89_build_txwd_body7_v2(desc_info); 1866 1867 if (!desc_info->en_wd_info) 1868 return; 1869 1870 txwd_info = (struct rtw89_txwd_info_v2 *)(txwd_body + 1); 1871 txwd_info->dword0 = rtw89_build_txwd_info0_v2(desc_info); 1872 txwd_info->dword1 = rtw89_build_txwd_info1_v2(desc_info); 1873 txwd_info->dword2 = rtw89_build_txwd_info2_v2(desc_info); 1874 txwd_info->dword4 = rtw89_build_txwd_info4_v2(desc_info); 1875 } 1876 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v2); 1877 1878 void rtw89_core_fill_txdesc_v3(struct rtw89_dev *rtwdev, 1879 struct rtw89_tx_desc_info *desc_info, 1880 void *txdesc) 1881 { 1882 struct rtw89_txwd_body_v2 *txwd_body = txdesc; 1883 struct rtw89_txwd_info_v2 *txwd_info; 1884 1885 txwd_body->dword0 = rtw89_build_txwd_body0_v2(desc_info); 1886 txwd_body->dword1 = rtw89_build_txwd_body1_v2(desc_info); 1887 txwd_body->dword2 = rtw89_build_txwd_body2_v3(desc_info); 1888 txwd_body->dword3 = rtw89_build_txwd_body3_v3(desc_info); 1889 if (desc_info->sec_en) { 1890 txwd_body->dword4 = rtw89_build_txwd_body4_v2(desc_info); 1891 txwd_body->dword5 = rtw89_build_txwd_body5_v2(desc_info); 1892 } 1893 txwd_body->dword6 = rtw89_build_txwd_body6_v2(desc_info); 1894 txwd_body->dword7 = rtw89_build_txwd_body7_v2(desc_info); 1895 1896 if (!desc_info->en_wd_info) 1897 return; 1898 1899 txwd_info = (struct rtw89_txwd_info_v2 *)(txwd_body + 1); 1900 txwd_info->dword0 = rtw89_build_txwd_info0_v2(desc_info); 1901 txwd_info->dword1 = rtw89_build_txwd_info1_v2(desc_info); 1902 txwd_info->dword2 = rtw89_build_txwd_info2_v3(desc_info); 1903 txwd_info->dword4 = rtw89_build_txwd_info4_v2(desc_info); 1904 } 1905 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v3); 1906 1907 static __le32 rtw89_build_txwd_fwcmd0_v1(struct rtw89_tx_desc_info *desc_info) 1908 { 1909 u32 dword = FIELD_PREP(AX_RXD_RPKT_LEN_MASK, desc_info->pkt_size) | 1910 FIELD_PREP(AX_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ? 1911 RTW89_CORE_RX_TYPE_FWDL : 1912 RTW89_CORE_RX_TYPE_H2C); 1913 1914 return cpu_to_le32(dword); 1915 } 1916 1917 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 1918 struct rtw89_tx_desc_info *desc_info, 1919 void *txdesc) 1920 { 1921 struct rtw89_rxdesc_short *txwd_v1 = (struct rtw89_rxdesc_short *)txdesc; 1922 1923 txwd_v1->dword0 = rtw89_build_txwd_fwcmd0_v1(desc_info); 1924 } 1925 EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v1); 1926 1927 static __le32 rtw89_build_txwd_fwcmd0_v2(struct rtw89_tx_desc_info *desc_info) 1928 { 1929 u32 dword = FIELD_PREP(BE_RXD_RPKT_LEN_MASK, desc_info->pkt_size) | 1930 FIELD_PREP(BE_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ? 1931 RTW89_CORE_RX_TYPE_FWDL : 1932 RTW89_CORE_RX_TYPE_H2C); 1933 1934 return cpu_to_le32(dword); 1935 } 1936 1937 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev, 1938 struct rtw89_tx_desc_info *desc_info, 1939 void *txdesc) 1940 { 1941 struct rtw89_rxdesc_short_v2 *txwd_v2 = (struct rtw89_rxdesc_short_v2 *)txdesc; 1942 1943 txwd_v2->dword0 = rtw89_build_txwd_fwcmd0_v2(desc_info); 1944 } 1945 EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v2); 1946 1947 static int rtw89_core_rx_process_mac_ppdu(struct rtw89_dev *rtwdev, 1948 struct sk_buff *skb_ppdu, 1949 struct rtw89_rx_phy_ppdu *phy_ppdu) 1950 { 1951 const struct rtw89_chip_info *chip = rtwdev->chip; 1952 const struct rtw89_rxinfo *rxinfo = (const struct rtw89_rxinfo *)skb_ppdu->data; 1953 const struct rtw89_rxinfo_user *user; 1954 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen; 1955 int rx_cnt_size = RTW89_PPDU_MAC_RX_CNT_SIZE; 1956 bool rx_cnt_valid = false; 1957 bool invalid = false; 1958 u8 plcp_size = 0; 1959 u8 *phy_sts; 1960 u8 usr_num; 1961 int i; 1962 1963 if (chip_gen == RTW89_CHIP_BE) { 1964 invalid = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_INVALID_V1); 1965 rx_cnt_size = RTW89_PPDU_MAC_RX_CNT_SIZE_V1; 1966 } 1967 1968 if (invalid) 1969 return -EINVAL; 1970 1971 rx_cnt_valid = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_RX_CNT_VLD); 1972 if (chip_gen == RTW89_CHIP_BE) { 1973 plcp_size = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_PLCP_LEN_V1) << 3; 1974 usr_num = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_USR_NUM_V1); 1975 } else { 1976 plcp_size = le32_get_bits(rxinfo->w1, RTW89_RXINFO_W1_PLCP_LEN) << 3; 1977 usr_num = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_USR_NUM); 1978 } 1979 if (usr_num > chip->ppdu_max_usr) { 1980 rtw89_warn(rtwdev, "Invalid user number (%d) in mac info\n", 1981 usr_num); 1982 return -EINVAL; 1983 } 1984 1985 for (i = 0; i < usr_num; i++) { 1986 user = &rxinfo->user[i]; 1987 if (!le32_get_bits(user->w0, RTW89_RXINFO_USER_MAC_ID_VALID)) 1988 continue; 1989 /* For WiFi 7 chips, RXWD.mac_id of PPDU status is not set 1990 * by hardware, so update mac_id by rxinfo_user[].mac_id. 1991 */ 1992 if (chip->chip_id == RTL8922A) 1993 phy_ppdu->mac_id = 1994 le32_get_bits(user->w0, RTW89_RXINFO_USER_MACID); 1995 else if (chip->chip_id == RTL8922D) 1996 phy_ppdu->mac_id = 1997 le32_get_bits(user->w0, RTW89_RXINFO_USER_MACID_V1); 1998 1999 phy_ppdu->has_data = 2000 le32_get_bits(user->w0, RTW89_RXINFO_USER_DATA); 2001 phy_ppdu->has_bcn = 2002 le32_get_bits(user->w0, RTW89_RXINFO_USER_BCN); 2003 break; 2004 } 2005 2006 phy_sts = skb_ppdu->data + RTW89_PPDU_MAC_INFO_SIZE; 2007 phy_sts += usr_num * RTW89_PPDU_MAC_INFO_USR_SIZE; 2008 /* 8-byte alignment */ 2009 if (usr_num & BIT(0)) 2010 phy_sts += RTW89_PPDU_MAC_INFO_USR_SIZE; 2011 if (rx_cnt_valid) 2012 phy_sts += rx_cnt_size; 2013 phy_sts += plcp_size; 2014 2015 if (phy_sts > skb_ppdu->data + skb_ppdu->len) 2016 return -EINVAL; 2017 2018 phy_ppdu->buf = phy_sts; 2019 phy_ppdu->len = skb_ppdu->data + skb_ppdu->len - phy_sts; 2020 2021 return 0; 2022 } 2023 2024 static u8 rtw89_get_data_rate_nss(struct rtw89_dev *rtwdev, u16 data_rate) 2025 { 2026 u8 data_rate_mode; 2027 2028 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate); 2029 switch (data_rate_mode) { 2030 case DATA_RATE_MODE_NON_HT: 2031 return 1; 2032 case DATA_RATE_MODE_HT: 2033 return rtw89_get_data_ht_nss(rtwdev, data_rate) + 1; 2034 case DATA_RATE_MODE_VHT: 2035 case DATA_RATE_MODE_HE: 2036 case DATA_RATE_MODE_EHT: 2037 return rtw89_get_data_nss(rtwdev, data_rate) + 1; 2038 default: 2039 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); 2040 return 0; 2041 } 2042 } 2043 2044 static void rtw89_core_rx_process_phy_ppdu_iter(void *data, 2045 struct ieee80211_sta *sta) 2046 { 2047 struct rtw89_rx_phy_ppdu *phy_ppdu = (struct rtw89_rx_phy_ppdu *)data; 2048 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 2049 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 2050 struct rtw89_hal *hal = &rtwdev->hal; 2051 struct rtw89_sta_link *rtwsta_link; 2052 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num; 2053 u8 ant_pos = U8_MAX; 2054 u8 evm_pos = 0; 2055 int i; 2056 2057 rtwsta_link = rtw89_sta_get_link_inst(rtwsta, phy_ppdu->phy_idx); 2058 if (unlikely(!rtwsta_link)) 2059 return; 2060 2061 if (rtwsta_link->mac_id != phy_ppdu->mac_id || !phy_ppdu->to_self) 2062 return; 2063 2064 if (hal->ant_diversity && hal->antenna_rx) { 2065 ant_pos = __ffs(hal->antenna_rx); 2066 evm_pos = ant_pos; 2067 } 2068 2069 ewma_rssi_add(&rtwsta_link->avg_rssi, phy_ppdu->rssi_avg); 2070 2071 if (ant_pos < ant_num) { 2072 ewma_rssi_add(&rtwsta_link->rssi[ant_pos], phy_ppdu->rssi[0]); 2073 } else { 2074 for (i = 0; i < rtwdev->chip->rf_path_num; i++) 2075 ewma_rssi_add(&rtwsta_link->rssi[i], phy_ppdu->rssi[i]); 2076 } 2077 2078 if (phy_ppdu->ofdm.has && (phy_ppdu->has_data || phy_ppdu->has_bcn)) { 2079 ewma_snr_add(&rtwsta_link->avg_snr, phy_ppdu->ofdm.avg_snr); 2080 if (rtw89_get_data_rate_nss(rtwdev, phy_ppdu->rate) == 1) { 2081 ewma_evm_add(&rtwsta_link->evm_1ss, phy_ppdu->ofdm.evm_min); 2082 } else { 2083 ewma_evm_add(&rtwsta_link->evm_min[evm_pos], 2084 phy_ppdu->ofdm.evm_min); 2085 ewma_evm_add(&rtwsta_link->evm_max[evm_pos], 2086 phy_ppdu->ofdm.evm_max); 2087 } 2088 } 2089 } 2090 2091 static u16 rtw89_core_get_phy_status_ie_len(struct rtw89_dev *rtwdev, 2092 const struct rtw89_phy_sts_iehdr *iehdr) 2093 { 2094 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 2095 const u8 *physts_ie_len_tab = phy->physt_ie_len; 2096 u16 ie_len; 2097 u8 ie; 2098 2099 ie = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_TYPE); 2100 if (physts_ie_len_tab[ie] != VAR_LEN) 2101 ie_len = physts_ie_len_tab[ie]; 2102 else 2103 ie_len = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_LEN) * VAR_LEN_UNIT; 2104 2105 return ie_len; 2106 } 2107 2108 static void rtw89_core_parse_phy_status_ie01_v2(struct rtw89_dev *rtwdev, 2109 const struct rtw89_phy_sts_iehdr *iehdr, 2110 struct rtw89_rx_phy_ppdu *phy_ppdu) 2111 { 2112 const struct rtw89_phy_sts_ie01_v2 *ie; 2113 u8 *rpl_fd = phy_ppdu->rpl_fd; 2114 2115 ie = (const struct rtw89_phy_sts_ie01_v2 *)iehdr; 2116 rpl_fd[RF_PATH_A] = le32_get_bits(ie->w8, RTW89_PHY_STS_IE01_V2_W8_RPL_FD_A); 2117 rpl_fd[RF_PATH_B] = le32_get_bits(ie->w8, RTW89_PHY_STS_IE01_V2_W8_RPL_FD_B); 2118 rpl_fd[RF_PATH_C] = le32_get_bits(ie->w9, RTW89_PHY_STS_IE01_V2_W9_RPL_FD_C); 2119 rpl_fd[RF_PATH_D] = le32_get_bits(ie->w9, RTW89_PHY_STS_IE01_V2_W9_RPL_FD_D); 2120 2121 phy_ppdu->bw_idx = le32_get_bits(ie->w5, RTW89_PHY_STS_IE01_V2_W5_BW_IDX); 2122 } 2123 2124 static void rtw89_core_parse_phy_status_ie01(struct rtw89_dev *rtwdev, 2125 const struct rtw89_phy_sts_iehdr *iehdr, 2126 struct rtw89_rx_phy_ppdu *phy_ppdu) 2127 { 2128 const struct rtw89_phy_sts_ie01 *ie = (const struct rtw89_phy_sts_ie01 *)iehdr; 2129 s16 cfo; 2130 u32 t; 2131 2132 phy_ppdu->chan_idx = le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_CH_IDX); 2133 phy_ppdu->ldpc = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_LDPC); 2134 phy_ppdu->stbc = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_STBC); 2135 phy_ppdu->bf = le32_get_bits(ie->w3, RTW89_PHY_STS_IE01_W3_BF); 2136 2137 if (!phy_ppdu->hdr_2_en) 2138 phy_ppdu->rx_path_en = 2139 le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_RX_PATH_EN); 2140 2141 if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6) 2142 return; 2143 2144 if (!phy_ppdu->to_self) 2145 return; 2146 2147 phy_ppdu->rpl_avg = le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_RSSI_AVG_FD); 2148 phy_ppdu->su = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_SU); 2149 phy_ppdu->ofdm.avg_snr = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_AVG_SNR); 2150 phy_ppdu->ofdm.evm_max = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_EVM_MAX); 2151 phy_ppdu->ofdm.evm_min = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_EVM_MIN); 2152 phy_ppdu->ofdm.has = true; 2153 2154 /* sign conversion for S(12,2) */ 2155 if (rtwdev->chip->cfo_src_fd) { 2156 t = le32_get_bits(ie->w1, RTW89_PHY_STS_IE01_W1_FD_CFO); 2157 cfo = sign_extend32(t, 11); 2158 } else { 2159 t = le32_get_bits(ie->w1, RTW89_PHY_STS_IE01_W1_PREMB_CFO); 2160 cfo = sign_extend32(t, 11); 2161 } 2162 2163 rtw89_phy_cfo_parse(rtwdev, cfo, phy_ppdu); 2164 2165 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 2166 rtw89_core_parse_phy_status_ie01_v2(rtwdev, iehdr, phy_ppdu); 2167 } 2168 2169 static void rtw89_core_parse_phy_status_ie00(struct rtw89_dev *rtwdev, 2170 const struct rtw89_phy_sts_iehdr *iehdr, 2171 struct rtw89_rx_phy_ppdu *phy_ppdu) 2172 { 2173 const struct rtw89_phy_sts_ie00 *ie = (const struct rtw89_phy_sts_ie00 *)iehdr; 2174 u16 tmp_rpl; 2175 2176 tmp_rpl = le32_get_bits(ie->w0, RTW89_PHY_STS_IE00_W0_RPL); 2177 phy_ppdu->rpl_avg = tmp_rpl >> 1; 2178 2179 if (!phy_ppdu->hdr_2_en) 2180 phy_ppdu->rx_path_en = 2181 le32_get_bits(ie->w3, RTW89_PHY_STS_IE00_W3_RX_PATH_EN); 2182 } 2183 2184 static void rtw89_core_parse_phy_status_ie00_v2(struct rtw89_dev *rtwdev, 2185 const struct rtw89_phy_sts_iehdr *iehdr, 2186 struct rtw89_rx_phy_ppdu *phy_ppdu) 2187 { 2188 const struct rtw89_phy_sts_ie00_v2 *ie; 2189 u8 *rpl_path = phy_ppdu->rpl_path; 2190 u16 tmp_rpl[RF_PATH_MAX]; 2191 u8 i; 2192 2193 ie = (const struct rtw89_phy_sts_ie00_v2 *)iehdr; 2194 tmp_rpl[RF_PATH_A] = le32_get_bits(ie->w4, RTW89_PHY_STS_IE00_V2_W4_RPL_TD_A); 2195 tmp_rpl[RF_PATH_B] = le32_get_bits(ie->w4, RTW89_PHY_STS_IE00_V2_W4_RPL_TD_B); 2196 tmp_rpl[RF_PATH_C] = le32_get_bits(ie->w4, RTW89_PHY_STS_IE00_V2_W4_RPL_TD_C); 2197 tmp_rpl[RF_PATH_D] = le32_get_bits(ie->w5, RTW89_PHY_STS_IE00_V2_W5_RPL_TD_D); 2198 2199 for (i = 0; i < RF_PATH_MAX; i++) 2200 rpl_path[i] = tmp_rpl[i] >> 1; 2201 } 2202 2203 static void rtw89_core_parse_phy_status_ie09(struct rtw89_dev *rtwdev, 2204 const struct rtw89_phy_sts_iehdr *iehdr, 2205 struct rtw89_rx_phy_ppdu *phy_ppdu) 2206 { 2207 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 2208 const union rtw89_phy_sts_ie09 *ie09; 2209 u16 ie_len; 2210 2211 ie09 = (const void *)iehdr; 2212 2213 if (phy->physt_gen >= 2) { 2214 ie_len = rtw89_core_get_phy_status_ie_len(rtwdev, (const void *)iehdr); 2215 if (ie_len < sizeof(ie09->gen2)) 2216 return; 2217 } 2218 2219 phy_ppdu->ie09 = ie09; 2220 } 2221 2222 static void rtw89_core_parse_phy_status_ie10(struct rtw89_dev *rtwdev, 2223 const struct rtw89_phy_sts_iehdr *iehdr, 2224 struct rtw89_rx_phy_ppdu *phy_ppdu) 2225 { 2226 phy_ppdu->ie10 = (const void *)iehdr; 2227 } 2228 2229 static int rtw89_core_process_phy_status_ie(struct rtw89_dev *rtwdev, 2230 const struct rtw89_phy_sts_iehdr *iehdr, 2231 struct rtw89_rx_phy_ppdu *phy_ppdu) 2232 { 2233 bool accept; 2234 u8 ie; 2235 2236 ie = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_TYPE); 2237 2238 /* 2239 * For normal mode, only parse ppdu_sts that are A1-matched, except for 2240 * scanning that needs to get chan_idx in IE01. 2241 */ 2242 accept = phy_ppdu->to_self || ie == RTW89_PHYSTS_IE01_CMN_OFDM || 2243 rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR; 2244 if (!accept) 2245 return 0; 2246 2247 switch (ie) { 2248 case RTW89_PHYSTS_IE00_CMN_CCK: 2249 rtw89_core_parse_phy_status_ie00(rtwdev, iehdr, phy_ppdu); 2250 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 2251 rtw89_core_parse_phy_status_ie00_v2(rtwdev, iehdr, phy_ppdu); 2252 break; 2253 case RTW89_PHYSTS_IE01_CMN_OFDM: 2254 rtw89_core_parse_phy_status_ie01(rtwdev, iehdr, phy_ppdu); 2255 break; 2256 case RTW89_PHYSTS_IE09_FTR_0: 2257 rtw89_core_parse_phy_status_ie09(rtwdev, iehdr, phy_ppdu); 2258 break; 2259 case RTW89_PHYSTS_IE10_FTR_PLCP_EXT: 2260 rtw89_core_parse_phy_status_ie10(rtwdev, iehdr, phy_ppdu); 2261 break; 2262 default: 2263 break; 2264 } 2265 2266 return 0; 2267 } 2268 2269 static void rtw89_core_update_phy_ppdu_hdr_v2(struct rtw89_rx_phy_ppdu *phy_ppdu) 2270 { 2271 const struct rtw89_phy_sts_hdr_v2 *hdr = phy_ppdu->buf + PHY_STS_HDR_LEN; 2272 2273 phy_ppdu->rx_path_en = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_V2_W0_PATH_EN); 2274 } 2275 2276 static void rtw89_core_update_phy_ppdu(struct rtw89_rx_phy_ppdu *phy_ppdu) 2277 { 2278 const struct rtw89_phy_sts_hdr *hdr = phy_ppdu->buf; 2279 u8 *rssi = phy_ppdu->rssi; 2280 2281 phy_ppdu->ie = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_IE_MAP); 2282 phy_ppdu->rssi_avg = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_RSSI_AVG); 2283 rssi[RF_PATH_A] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_A); 2284 rssi[RF_PATH_B] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_B); 2285 rssi[RF_PATH_C] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_C); 2286 rssi[RF_PATH_D] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_D); 2287 2288 phy_ppdu->hdr_2_en = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_HDR_2_EN); 2289 if (phy_ppdu->hdr_2_en) 2290 rtw89_core_update_phy_ppdu_hdr_v2(phy_ppdu); 2291 } 2292 2293 static int rtw89_core_rx_process_phy_ppdu(struct rtw89_dev *rtwdev, 2294 struct rtw89_rx_phy_ppdu *phy_ppdu) 2295 { 2296 const struct rtw89_phy_sts_hdr *hdr = phy_ppdu->buf; 2297 u32 len_from_header; 2298 bool physts_valid; 2299 2300 physts_valid = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_VALID); 2301 if (!physts_valid) 2302 return -EINVAL; 2303 2304 len_from_header = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_LEN) << 3; 2305 2306 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 2307 len_from_header += PHY_STS_HDR_LEN; 2308 2309 if (len_from_header != phy_ppdu->len) { 2310 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "phy ppdu len mismatch\n"); 2311 return -EINVAL; 2312 } 2313 rtw89_core_update_phy_ppdu(phy_ppdu); 2314 2315 return 0; 2316 } 2317 2318 static int rtw89_core_rx_parse_phy_sts(struct rtw89_dev *rtwdev, 2319 struct rtw89_rx_phy_ppdu *phy_ppdu) 2320 { 2321 void *pos, *end; 2322 bool accept; 2323 u16 ie_len; 2324 2325 /* for normal mode, mark invalid reports and bypass them */ 2326 accept = phy_ppdu->ie >= RTW89_CCK_PKT || 2327 rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR; 2328 if (!accept) 2329 return -EINVAL; 2330 2331 pos = phy_ppdu->buf + PHY_STS_HDR_LEN; 2332 if (phy_ppdu->hdr_2_en) 2333 pos += PHY_STS_HDR_LEN; 2334 end = phy_ppdu->buf + phy_ppdu->len; 2335 while (pos < end) { 2336 const struct rtw89_phy_sts_iehdr *iehdr = pos; 2337 2338 /* 2339 * RTL8922D might reports 8 bytes zeros at end if IE09 presents. 2340 * Check and ignore the zeros. 2341 */ 2342 if (unlikely(phy_ppdu->ie09 && end - pos == 8 && iehdr->w0 == 0)) 2343 break; 2344 2345 ie_len = rtw89_core_get_phy_status_ie_len(rtwdev, iehdr); 2346 pos += ie_len; 2347 if (pos > end || ie_len == 0) { 2348 /* clear pointers to prevent accessing out of IE */ 2349 phy_ppdu->ie09 = NULL; 2350 phy_ppdu->ie10 = NULL; 2351 2352 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 2353 "phy status parse failed\n"); 2354 2355 return -EINVAL; 2356 } 2357 2358 rtw89_core_process_phy_status_ie(rtwdev, iehdr, phy_ppdu); 2359 } 2360 2361 rtw89_chip_convert_rpl_to_rssi(rtwdev, phy_ppdu); 2362 rtw89_phy_antdiv_parse(rtwdev, phy_ppdu); 2363 2364 return 0; 2365 } 2366 2367 static void rtw89_core_rx_process_phy_sts(struct rtw89_dev *rtwdev, 2368 struct rtw89_rx_phy_ppdu *phy_ppdu) 2369 { 2370 int ret; 2371 2372 ret = rtw89_core_rx_parse_phy_sts(rtwdev, phy_ppdu); 2373 if (ret) 2374 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "parse phy sts failed\n"); 2375 else 2376 phy_ppdu->valid = true; 2377 2378 ieee80211_iterate_stations_atomic(rtwdev->hw, 2379 rtw89_core_rx_process_phy_ppdu_iter, 2380 phy_ppdu); 2381 } 2382 2383 static u8 rtw89_rxdesc_to_nl_he_gi(struct rtw89_dev *rtwdev, 2384 u8 desc_info_gi, 2385 bool rx_status) 2386 { 2387 switch (desc_info_gi) { 2388 case RTW89_GILTF_SGI_4XHE08: 2389 case RTW89_GILTF_2XHE08: 2390 case RTW89_GILTF_1XHE08: 2391 return NL80211_RATE_INFO_HE_GI_0_8; 2392 case RTW89_GILTF_2XHE16: 2393 case RTW89_GILTF_1XHE16: 2394 return NL80211_RATE_INFO_HE_GI_1_6; 2395 case RTW89_GILTF_LGI_4XHE32: 2396 return NL80211_RATE_INFO_HE_GI_3_2; 2397 default: 2398 rtw89_warn(rtwdev, "invalid gi_ltf=%d", desc_info_gi); 2399 if (rx_status) 2400 return NL80211_RATE_INFO_HE_GI_3_2; 2401 return U8_MAX; 2402 } 2403 } 2404 2405 static u8 rtw89_rxdesc_to_nl_eht_gi(struct rtw89_dev *rtwdev, 2406 u8 desc_info_gi, 2407 bool rx_status) 2408 { 2409 switch (desc_info_gi) { 2410 case RTW89_GILTF_SGI_4XHE08: 2411 case RTW89_GILTF_2XHE08: 2412 case RTW89_GILTF_1XHE08: 2413 return NL80211_RATE_INFO_EHT_GI_0_8; 2414 case RTW89_GILTF_2XHE16: 2415 case RTW89_GILTF_1XHE16: 2416 return NL80211_RATE_INFO_EHT_GI_1_6; 2417 case RTW89_GILTF_LGI_4XHE32: 2418 return NL80211_RATE_INFO_EHT_GI_3_2; 2419 default: 2420 rtw89_warn(rtwdev, "invalid gi_ltf=%d", desc_info_gi); 2421 if (rx_status) 2422 return NL80211_RATE_INFO_EHT_GI_3_2; 2423 return U8_MAX; 2424 } 2425 } 2426 2427 static u8 rtw89_rxdesc_to_nl_he_eht_gi(struct rtw89_dev *rtwdev, 2428 u8 desc_info_gi, 2429 bool rx_status, bool eht) 2430 { 2431 return eht ? rtw89_rxdesc_to_nl_eht_gi(rtwdev, desc_info_gi, rx_status) : 2432 rtw89_rxdesc_to_nl_he_gi(rtwdev, desc_info_gi, rx_status); 2433 } 2434 2435 static 2436 bool rtw89_check_rx_statu_gi_match(struct ieee80211_rx_status *status, u8 gi_ltf, 2437 bool eht) 2438 { 2439 if (eht) 2440 return status->eht.gi == gi_ltf; 2441 2442 return status->he_gi == gi_ltf; 2443 } 2444 2445 static bool rtw89_core_rx_ppdu_match(struct rtw89_dev *rtwdev, 2446 struct rtw89_rx_desc_info *desc_ppdu, 2447 struct ieee80211_rx_status *status) 2448 { 2449 u8 band = desc_ppdu->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 2450 u8 data_rate_mode, bw, rate_idx = MASKBYTE0, gi_ltf; 2451 bool eht = false; 2452 u16 data_rate; 2453 bool ret; 2454 2455 data_rate = desc_ppdu->data_rate; 2456 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate); 2457 if (data_rate_mode == DATA_RATE_MODE_NON_HT) { 2458 rate_idx = rtw89_get_data_not_ht_idx(rtwdev, data_rate); 2459 /* rate_idx is still hardware value here */ 2460 } else if (data_rate_mode == DATA_RATE_MODE_HT) { 2461 rate_idx = rtw89_get_data_ht_mcs(rtwdev, data_rate); 2462 } else if (data_rate_mode == DATA_RATE_MODE_VHT || 2463 data_rate_mode == DATA_RATE_MODE_HE || 2464 data_rate_mode == DATA_RATE_MODE_EHT) { 2465 rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 2466 } else { 2467 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); 2468 } 2469 2470 eht = data_rate_mode == DATA_RATE_MODE_EHT; 2471 bw = rtw89_hw_to_rate_info_bw(desc_ppdu->bw); 2472 gi_ltf = rtw89_rxdesc_to_nl_he_eht_gi(rtwdev, desc_ppdu->gi_ltf, false, eht); 2473 ret = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band] == desc_ppdu->ppdu_cnt && 2474 status->rate_idx == rate_idx && 2475 rtw89_check_rx_statu_gi_match(status, gi_ltf, eht) && 2476 status->bw == bw; 2477 2478 return ret; 2479 } 2480 2481 struct rtw89_vif_rx_stats_iter_data { 2482 struct rtw89_dev *rtwdev; 2483 struct rtw89_rx_phy_ppdu *phy_ppdu; 2484 struct rtw89_rx_desc_info *desc_info; 2485 struct sk_buff *skb; 2486 const u8 *bssid; 2487 }; 2488 2489 static void rtw89_stats_trigger_frame(struct rtw89_dev *rtwdev, 2490 struct rtw89_vif_link *rtwvif_link, 2491 struct ieee80211_bss_conf *bss_conf, 2492 struct sk_buff *skb) 2493 { 2494 struct ieee80211_trigger *tf = (struct ieee80211_trigger *)skb->data; 2495 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 2496 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 2497 u8 *pos, *end, type, tf_bw; 2498 u16 aid, tf_rua; 2499 2500 if (!ether_addr_equal(bss_conf->bssid, tf->ta) || 2501 rtwvif_link->wifi_role != RTW89_WIFI_ROLE_STATION || 2502 rtwvif_link->net_type == RTW89_NET_TYPE_NO_LINK) 2503 return; 2504 2505 type = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_TYPE_MASK); 2506 if (type != IEEE80211_TRIGGER_TYPE_BASIC && type != IEEE80211_TRIGGER_TYPE_MU_BAR) 2507 return; 2508 2509 end = (u8 *)tf + skb->len; 2510 pos = tf->variable; 2511 2512 while (end - pos >= RTW89_TF_BASIC_USER_INFO_SZ) { 2513 aid = RTW89_GET_TF_USER_INFO_AID12(pos); 2514 tf_rua = RTW89_GET_TF_USER_INFO_RUA(pos); 2515 tf_bw = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_ULBW_MASK); 2516 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 2517 "[TF] aid: %d, ul_mcs: %d, rua: %d, bw: %d\n", 2518 aid, RTW89_GET_TF_USER_INFO_UL_MCS(pos), 2519 tf_rua, tf_bw); 2520 2521 if (aid == RTW89_TF_PAD) 2522 break; 2523 2524 if (aid == vif->cfg.aid) { 2525 enum nl80211_he_ru_alloc rua; 2526 2527 rtwvif->stats.rx_tf_acc++; 2528 rtwdev->stats.rx_tf_acc++; 2529 2530 /* The following only required for HE trigger frame, but we 2531 * cannot use UL HE-SIG-A2 reserved subfield to identify it 2532 * since some 11ax APs will fill it with all 0s, which will 2533 * be misunderstood as EHT trigger frame. 2534 */ 2535 if (bss_conf->eht_support) 2536 break; 2537 2538 rua = rtw89_he_rua_to_ru_alloc(tf_rua >> 1); 2539 2540 if (tf_bw == IEEE80211_TRIGGER_ULBW_160_80P80MHZ && 2541 rua <= NL80211_RATE_INFO_HE_RU_ALLOC_106) 2542 rtwvif_link->pwr_diff_en = true; 2543 break; 2544 } 2545 2546 pos += RTW89_TF_BASIC_USER_INFO_SZ; 2547 } 2548 } 2549 2550 static void rtw89_cancel_6ghz_probe_work(struct wiphy *wiphy, struct wiphy_work *work) 2551 { 2552 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 2553 cancel_6ghz_probe_work); 2554 struct list_head *pkt_list = rtwdev->scan_info.pkt_list; 2555 struct rtw89_pktofld_info *info; 2556 2557 lockdep_assert_wiphy(wiphy); 2558 2559 if (!rtwdev->scanning) 2560 return; 2561 2562 list_for_each_entry(info, &pkt_list[NL80211_BAND_6GHZ], list) { 2563 if (!info->cancel || !test_bit(info->id, rtwdev->pkt_offload)) 2564 continue; 2565 2566 rtw89_fw_h2c_del_pkt_offload(rtwdev, info->id); 2567 2568 /* Don't delete/free info from pkt_list at this moment. Let it 2569 * be deleted/freed in rtw89_release_pkt_list() after scanning, 2570 * since if during scanning, pkt_list is accessed in bottom half. 2571 */ 2572 } 2573 } 2574 2575 static void rtw89_core_cancel_6ghz_probe_tx(struct rtw89_dev *rtwdev, 2576 struct sk_buff *skb) 2577 { 2578 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb); 2579 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 2580 struct list_head *pkt_list = rtwdev->scan_info.pkt_list; 2581 struct rtw89_pktofld_info *info; 2582 bool queue_work = false; 2583 2584 if (rx_status->band != NL80211_BAND_6GHZ) 2585 return; 2586 2587 if (unlikely(!(rtwdev->chip->support_bands & BIT(NL80211_BAND_6GHZ)))) { 2588 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "invalid rx on unsupported 6 GHz\n"); 2589 return; 2590 } 2591 2592 list_for_each_entry(info, &pkt_list[NL80211_BAND_6GHZ], list) { 2593 if (ether_addr_equal(info->bssid, mgmt->bssid)) { 2594 info->cancel = true; 2595 queue_work = true; 2596 } 2597 } 2598 2599 if (queue_work) 2600 wiphy_work_queue(rtwdev->hw->wiphy, &rtwdev->cancel_6ghz_probe_work); 2601 } 2602 2603 static void rtw89_vif_sync_bcn_tsf(struct rtw89_vif_link *rtwvif_link, 2604 struct ieee80211_hdr *hdr, size_t len) 2605 { 2606 struct ieee80211_mgmt *mgmt = (typeof(mgmt))hdr; 2607 2608 if (len < offsetof(typeof(*mgmt), u.beacon.variable)) 2609 return; 2610 2611 WRITE_ONCE(rtwvif_link->sync_bcn_tsf, le64_to_cpu(mgmt->u.beacon.timestamp)); 2612 } 2613 2614 static u32 rtw89_bcn_calc_min_tbtt(struct rtw89_dev *rtwdev, u32 tbtt1, u32 tbtt2) 2615 { 2616 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track; 2617 u32 close_bcn_intvl_th = bcn_track->close_bcn_intvl_th; 2618 u32 tbtt_diff_th = bcn_track->tbtt_diff_th; 2619 2620 if (tbtt2 > tbtt1) 2621 swap(tbtt1, tbtt2); 2622 2623 if (tbtt1 - tbtt2 > tbtt_diff_th) 2624 return tbtt1; 2625 else if (tbtt2 > close_bcn_intvl_th) 2626 return tbtt2; 2627 else if (tbtt1 > close_bcn_intvl_th) 2628 return tbtt1; 2629 else 2630 return tbtt2; 2631 } 2632 2633 static void rtw89_bcn_cfg_tbtt_offset(struct rtw89_dev *rtwdev, 2634 struct rtw89_vif_link *rtwvif_link) 2635 { 2636 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track; 2637 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2638 u32 offset = bcn_track->tbtt_offset; 2639 2640 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) { 2641 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2642 const struct rtw89_port_reg *p = mac->port_base; 2643 u32 bcnspc, val; 2644 2645 bcnspc = rtw89_read32_port_mask(rtwdev, rtwvif_link, 2646 p->bcn_space, B_AX_BCN_SPACE_MASK); 2647 val = bcnspc - (offset / 1024); 2648 val = u32_encode_bits(val, B_AX_TBTT_SHIFT_OFST_MAG) | 2649 B_AX_TBTT_SHIFT_OFST_SIGN; 2650 2651 rtw89_write16_port_mask(rtwdev, rtwvif_link, p->tbtt_shift, 2652 B_AX_TBTT_SHIFT_OFST_MASK, val); 2653 2654 return; 2655 } 2656 2657 rtw89_fw_h2c_tbtt_tuning(rtwdev, rtwvif_link, offset); 2658 } 2659 2660 static void rtw89_bcn_update_tbtt_offset(struct rtw89_dev *rtwdev, 2661 struct rtw89_vif_link *rtwvif_link) 2662 { 2663 struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat; 2664 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track; 2665 u32 *tbtt_us = bcn_stat->tbtt_us; 2666 u32 offset = tbtt_us[0]; 2667 u8 i; 2668 2669 for (i = 1; i < RTW89_BCN_TRACK_STAT_NR; i++) 2670 offset = rtw89_bcn_calc_min_tbtt(rtwdev, tbtt_us[i], offset); 2671 2672 if (bcn_track->tbtt_offset == offset) 2673 return; 2674 2675 bcn_track->tbtt_offset = offset; 2676 rtw89_bcn_cfg_tbtt_offset(rtwdev, rtwvif_link); 2677 } 2678 2679 static int cmp_u16(const void *a, const void *b) 2680 { 2681 return *(const u16 *)a - *(const u16 *)b; 2682 } 2683 2684 static u16 _rtw89_bcn_calc_drift(u16 tbtt, u16 offset, u16 beacon_int) 2685 { 2686 if (tbtt < offset) 2687 return beacon_int - offset + tbtt; 2688 2689 return tbtt - offset; 2690 } 2691 2692 static void rtw89_bcn_calc_drift(struct rtw89_dev *rtwdev) 2693 { 2694 struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat; 2695 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track; 2696 u16 offset_tu = bcn_track->tbtt_offset / 1024; 2697 u16 *tbtt_tu = bcn_stat->tbtt_tu; 2698 u16 *drift = bcn_stat->drift; 2699 u8 i; 2700 2701 bcn_stat->tbtt_tu_min = U16_MAX; 2702 bcn_stat->tbtt_tu_max = 0; 2703 for (i = 0; i < RTW89_BCN_TRACK_STAT_NR; i++) { 2704 drift[i] = _rtw89_bcn_calc_drift(tbtt_tu[i], offset_tu, 2705 bcn_track->beacon_int); 2706 2707 bcn_stat->tbtt_tu_min = min(bcn_stat->tbtt_tu_min, tbtt_tu[i]); 2708 bcn_stat->tbtt_tu_max = max(bcn_stat->tbtt_tu_max, tbtt_tu[i]); 2709 } 2710 2711 sort(drift, RTW89_BCN_TRACK_STAT_NR, sizeof(*drift), cmp_u16, NULL); 2712 } 2713 2714 static void rtw89_bcn_calc_distribution(struct rtw89_dev *rtwdev) 2715 { 2716 struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat; 2717 struct rtw89_beacon_dist *bcn_dist = &bcn_stat->bcn_dist; 2718 u16 lower_bound, upper_bound, outlier_count = 0; 2719 u16 *drift = bcn_stat->drift; 2720 u16 *bins = bcn_dist->bins; 2721 u16 q1, q3, iqr, tmp; 2722 u8 i; 2723 2724 BUILD_BUG_ON(RTW89_BCN_TRACK_STAT_NR % 4 != 0); 2725 2726 memset(bcn_dist, 0, sizeof(*bcn_dist)); 2727 2728 bcn_dist->min = drift[0]; 2729 bcn_dist->max = drift[RTW89_BCN_TRACK_STAT_NR - 1]; 2730 2731 tmp = RTW89_BCN_TRACK_STAT_NR / 4; 2732 q1 = ((drift[tmp] + drift[tmp - 1]) * RTW89_BCN_TRACK_SCALE_FACTOR) / 2; 2733 2734 tmp = (RTW89_BCN_TRACK_STAT_NR * 3) / 4; 2735 q3 = ((drift[tmp] + drift[tmp - 1]) * RTW89_BCN_TRACK_SCALE_FACTOR) / 2; 2736 2737 iqr = q3 - q1; 2738 tmp = (3 * iqr) / 2; 2739 2740 if (bcn_dist->min <= 5) 2741 lower_bound = bcn_dist->min; 2742 else if (q1 > tmp) 2743 lower_bound = (q1 - tmp) / RTW89_BCN_TRACK_SCALE_FACTOR; 2744 else 2745 lower_bound = 0; 2746 2747 upper_bound = (q3 + tmp) / RTW89_BCN_TRACK_SCALE_FACTOR; 2748 2749 for (i = 0; i < RTW89_BCN_TRACK_STAT_NR; i++) { 2750 u16 tbtt = bcn_stat->tbtt_tu[i]; 2751 u16 min = bcn_stat->tbtt_tu_min; 2752 u8 bin_idx; 2753 2754 /* histogram */ 2755 bin_idx = min((tbtt - min) / RTW89_BCN_TRACK_BIN_WIDTH, 2756 RTW89_BCN_TRACK_MAX_BIN_NUM - 1); 2757 bins[bin_idx]++; 2758 2759 /* boxplot outlier */ 2760 if (drift[i] < lower_bound || drift[i] > upper_bound) 2761 outlier_count++; 2762 } 2763 2764 bcn_dist->outlier_count = outlier_count; 2765 bcn_dist->lower_bound = lower_bound; 2766 bcn_dist->upper_bound = upper_bound; 2767 } 2768 2769 static u8 rtw89_bcn_get_coverage(struct rtw89_dev *rtwdev, u16 threshold) 2770 { 2771 struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat; 2772 int l = 0, r = RTW89_BCN_TRACK_STAT_NR - 1, m; 2773 u16 *drift = bcn_stat->drift; 2774 int index = -1; 2775 u8 count = 0; 2776 2777 while (l <= r) { 2778 m = l + (r - l) / 2; 2779 2780 if (drift[m] <= threshold) { 2781 index = m; 2782 l = m + 1; 2783 } else { 2784 r = m - 1; 2785 } 2786 } 2787 2788 count = (index == -1) ? 0 : (index + 1); 2789 2790 return (count * PERCENT) / RTW89_BCN_TRACK_STAT_NR; 2791 } 2792 2793 static u16 rtw89_bcn_get_histogram_bound(struct rtw89_dev *rtwdev, u8 target) 2794 { 2795 struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat; 2796 struct rtw89_beacon_dist *bcn_dist = &bcn_stat->bcn_dist; 2797 u16 tbtt_tu_max = bcn_stat->tbtt_tu_max; 2798 u16 upper, lower = bcn_stat->tbtt_tu_min; 2799 u8 i, count = 0; 2800 2801 for (i = 0; i < RTW89_BCN_TRACK_MAX_BIN_NUM; i++) { 2802 upper = lower + RTW89_BCN_TRACK_BIN_WIDTH - 1; 2803 if (i == RTW89_BCN_TRACK_MAX_BIN_NUM - 1) 2804 upper = max(upper, tbtt_tu_max); 2805 2806 count += bcn_dist->bins[i]; 2807 if (count > target) 2808 break; 2809 2810 lower = upper + 1; 2811 } 2812 2813 return upper; 2814 } 2815 2816 static u16 rtw89_bcn_get_rx_time(struct rtw89_dev *rtwdev, 2817 struct rtw89_vif_link *rtwvif_link) 2818 { 2819 #define RTW89_SYMBOL_TIME_2GHZ 192 2820 #define RTW89_SYMBOL_TIME_5GHZ 20 2821 #define RTW89_SYMBOL_TIME_6GHZ 20 2822 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx); 2823 struct rtw89_bb_ctx *bb = rtw89_get_bb_ctx(rtwdev, rtwvif_link->phy_idx); 2824 struct rtw89_pkt_stat *pkt_stat = &bb->cur_pkt_stat; 2825 u16 bitrate, val; 2826 2827 if (!rtw89_legacy_rate_to_bitrate(rtwdev, pkt_stat->beacon_rate, &bitrate)) 2828 return 0; 2829 2830 val = (pkt_stat->beacon_len * 8 * RTW89_BCN_TRACK_SCALE_FACTOR) / bitrate; 2831 2832 switch (chan->band_type) { 2833 default: 2834 case RTW89_BAND_2G: 2835 val += RTW89_SYMBOL_TIME_2GHZ; 2836 break; 2837 case RTW89_BAND_5G: 2838 val += RTW89_SYMBOL_TIME_5GHZ; 2839 break; 2840 case RTW89_BAND_6G: 2841 val += RTW89_SYMBOL_TIME_6GHZ; 2842 break; 2843 } 2844 2845 /* convert to millisecond */ 2846 return DIV_ROUND_UP(val, 1000); 2847 } 2848 2849 static void rtw89_bcn_calc_timeout(struct rtw89_dev *rtwdev, 2850 struct rtw89_vif_link *rtwvif_link) 2851 { 2852 #define RTW89_BCN_TRACK_EXTEND_TIMEOUT 5 2853 #define RTW89_BCN_TRACK_COVERAGE_TH 0 /* unit: TU */ 2854 #define RTW89_BCN_TRACK_STRONG_RSSI 80 2855 struct rtw89_bb_ctx *bb = rtw89_get_bb_ctx(rtwdev, rtwvif_link->phy_idx); 2856 struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat; 2857 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track; 2858 struct rtw89_pkt_stat *pkt_stat = &bb->cur_pkt_stat; 2859 struct rtw89_beacon_dist *bcn_dist = &bcn_stat->bcn_dist; 2860 u16 outlier_high_bcn_th = bcn_track->outlier_high_bcn_th; 2861 u16 outlier_low_bcn_th = bcn_track->outlier_low_bcn_th; 2862 u16 target_bcn_th = bcn_track->target_bcn_th; 2863 u8 rssi = ewma_rssi_read(&bb->bcn_rssi); 2864 u16 low_bcn_th = bcn_track->low_bcn_th; 2865 u16 med_bcn_th = bcn_track->med_bcn_th; 2866 u16 beacon_int = bcn_track->beacon_int; 2867 u16 bcn_timeout; 2868 2869 if (pkt_stat->beacon_nr < low_bcn_th) { 2870 bcn_timeout = (RTW89_BCN_TRACK_TARGET_BCN * beacon_int) / PERCENT; 2871 goto out; 2872 } 2873 2874 if (bcn_dist->outlier_count >= outlier_high_bcn_th) { 2875 bcn_timeout = bcn_dist->max; 2876 goto out; 2877 } 2878 2879 if (pkt_stat->beacon_nr < med_bcn_th) { 2880 if (bcn_dist->outlier_count > outlier_low_bcn_th) 2881 bcn_timeout = (bcn_dist->max + bcn_dist->upper_bound) / 2; 2882 else 2883 bcn_timeout = bcn_dist->upper_bound + 2884 RTW89_BCN_TRACK_EXTEND_TIMEOUT; 2885 2886 goto out; 2887 } 2888 2889 if (rssi >= RTW89_BCN_TRACK_STRONG_RSSI) { 2890 if (rtw89_bcn_get_coverage(rtwdev, RTW89_BCN_TRACK_COVERAGE_TH) >= 90) { 2891 /* ideal case */ 2892 bcn_timeout = 0; 2893 } else { 2894 u16 offset_tu = bcn_track->tbtt_offset / 1024; 2895 u16 upper_bound; 2896 2897 upper_bound = 2898 rtw89_bcn_get_histogram_bound(rtwdev, target_bcn_th); 2899 bcn_timeout = 2900 _rtw89_bcn_calc_drift(upper_bound, offset_tu, beacon_int); 2901 } 2902 2903 goto out; 2904 } 2905 2906 bcn_timeout = bcn_stat->drift[target_bcn_th]; 2907 2908 out: 2909 bcn_track->bcn_timeout = bcn_timeout + rtw89_bcn_get_rx_time(rtwdev, rtwvif_link); 2910 } 2911 2912 static void rtw89_bcn_update_timeout(struct rtw89_dev *rtwdev, 2913 struct rtw89_vif_link *rtwvif_link) 2914 { 2915 rtw89_bcn_calc_drift(rtwdev); 2916 rtw89_bcn_calc_distribution(rtwdev); 2917 rtw89_bcn_calc_timeout(rtwdev, rtwvif_link); 2918 } 2919 2920 static void rtw89_core_bcn_track(struct rtw89_dev *rtwdev) 2921 { 2922 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track; 2923 struct rtw89_vif_link *rtwvif_link; 2924 struct rtw89_vif *rtwvif; 2925 unsigned int link_id; 2926 2927 if (!RTW89_CHK_FW_FEATURE(BEACON_TRACKING, &rtwdev->fw)) 2928 return; 2929 2930 if (!rtwdev->lps_enabled) 2931 return; 2932 2933 if (!bcn_track->is_data_ready) 2934 return; 2935 2936 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 2937 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) { 2938 if (!(rtwvif_link->wifi_role == RTW89_WIFI_ROLE_STATION || 2939 rtwvif_link->wifi_role == RTW89_WIFI_ROLE_P2P_CLIENT)) 2940 continue; 2941 2942 rtw89_bcn_update_tbtt_offset(rtwdev, rtwvif_link); 2943 rtw89_bcn_update_timeout(rtwdev, rtwvif_link); 2944 } 2945 } 2946 } 2947 2948 static bool rtw89_core_bcn_track_can_lps(struct rtw89_dev *rtwdev) 2949 { 2950 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track; 2951 2952 if (!RTW89_CHK_FW_FEATURE(BEACON_TRACKING, &rtwdev->fw)) 2953 return true; 2954 2955 return bcn_track->is_data_ready; 2956 } 2957 2958 static void rtw89_core_bcn_track_assoc(struct rtw89_dev *rtwdev, 2959 struct rtw89_vif_link *rtwvif_link) 2960 { 2961 #define RTW89_BCN_TRACK_MED_BCN 70 2962 #define RTW89_BCN_TRACK_LOW_BCN 30 2963 #define RTW89_BCN_TRACK_OUTLIER_HIGH_BCN 30 2964 #define RTW89_BCN_TRACK_OUTLIER_LOW_BCN 20 2965 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track; 2966 u32 period = jiffies_to_msecs(RTW89_TRACK_WORK_PERIOD); 2967 struct ieee80211_bss_conf *bss_conf; 2968 u32 beacons_in_period; 2969 u32 bcn_intvl_us; 2970 u16 beacon_int; 2971 u8 dtim; 2972 2973 rcu_read_lock(); 2974 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 2975 beacon_int = bss_conf->beacon_int ?: 100; 2976 dtim = bss_conf->dtim_period; 2977 rcu_read_unlock(); 2978 2979 beacons_in_period = period / beacon_int / dtim; 2980 bcn_intvl_us = ieee80211_tu_to_usec(beacon_int); 2981 2982 bcn_track->low_bcn_th = 2983 (beacons_in_period * RTW89_BCN_TRACK_LOW_BCN) / PERCENT; 2984 bcn_track->med_bcn_th = 2985 (beacons_in_period * RTW89_BCN_TRACK_MED_BCN) / PERCENT; 2986 bcn_track->outlier_low_bcn_th = 2987 (RTW89_BCN_TRACK_STAT_NR * RTW89_BCN_TRACK_OUTLIER_LOW_BCN) / PERCENT; 2988 bcn_track->outlier_high_bcn_th = 2989 (RTW89_BCN_TRACK_STAT_NR * RTW89_BCN_TRACK_OUTLIER_HIGH_BCN) / PERCENT; 2990 bcn_track->target_bcn_th = 2991 (RTW89_BCN_TRACK_STAT_NR * RTW89_BCN_TRACK_TARGET_BCN) / PERCENT; 2992 2993 bcn_track->close_bcn_intvl_th = ieee80211_tu_to_usec(beacon_int - 3); 2994 bcn_track->tbtt_diff_th = (bcn_intvl_us * 85) / PERCENT; 2995 bcn_track->beacon_int = beacon_int; 2996 bcn_track->dtim = dtim; 2997 } 2998 2999 static void rtw89_core_bcn_track_reset(struct rtw89_dev *rtwdev) 3000 { 3001 memset(&rtwdev->phystat.bcn_stat, 0, sizeof(rtwdev->phystat.bcn_stat)); 3002 memset(&rtwdev->bcn_track, 0, sizeof(rtwdev->bcn_track)); 3003 } 3004 3005 static bool rtw89_core_proto_stats_can_lps(struct rtw89_dev *rtwdev, 3006 struct rtw89_vif *rtwvif, 3007 enum rtw89_tfc_interval interval) 3008 { 3009 if (rtwdev->chip->chip_id != RTL8852A) 3010 return true; 3011 3012 if (rtwvif->burst_active) 3013 return false; 3014 3015 if (interval == RTW89_TFC_INTERVAL_100MS && 3016 hweight8(rtwvif->stats_ps.active_histogram) < 3) 3017 return false; 3018 3019 return true; 3020 } 3021 3022 static void rtw89_vif_rx_bcn_stat(struct rtw89_dev *rtwdev, struct sk_buff *skb) 3023 { 3024 #define RTW89_APPEND_TSF_2GHZ 384 3025 #define RTW89_APPEND_TSF_5GHZ 52 3026 #define RTW89_APPEND_TSF_6GHZ 52 3027 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 3028 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb); 3029 struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat; 3030 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track; 3031 u32 bcn_intvl_us = ieee80211_tu_to_usec(bcn_track->beacon_int); 3032 u64 tsf = le64_to_cpu(mgmt->u.beacon.timestamp); 3033 u8 wp, num = bcn_stat->num; 3034 u16 append; 3035 3036 if (!RTW89_CHK_FW_FEATURE(BEACON_TRACKING, &rtwdev->fw)) 3037 return; 3038 3039 /* Skip if not yet associated */ 3040 if (!bcn_intvl_us) 3041 return; 3042 3043 switch (rx_status->band) { 3044 default: 3045 case NL80211_BAND_2GHZ: 3046 append = RTW89_APPEND_TSF_2GHZ; 3047 break; 3048 case NL80211_BAND_5GHZ: 3049 append = RTW89_APPEND_TSF_5GHZ; 3050 break; 3051 case NL80211_BAND_6GHZ: 3052 append = RTW89_APPEND_TSF_6GHZ; 3053 break; 3054 } 3055 3056 wp = bcn_stat->wp; 3057 div_u64_rem(tsf - append, bcn_intvl_us, &bcn_stat->tbtt_us[wp]); 3058 bcn_stat->tbtt_tu[wp] = bcn_stat->tbtt_us[wp] / 1024; 3059 bcn_stat->wp = (wp + 1) % RTW89_BCN_TRACK_STAT_NR; 3060 bcn_stat->num = umin(num + 1, RTW89_BCN_TRACK_STAT_NR); 3061 bcn_track->is_data_ready = bcn_stat->num == RTW89_BCN_TRACK_STAT_NR; 3062 } 3063 3064 static void rtw89_vif_rx_stats_iter(void *data, u8 *mac, 3065 struct ieee80211_vif *vif) 3066 { 3067 struct rtw89_vif_rx_stats_iter_data *iter_data = data; 3068 struct rtw89_dev *rtwdev = iter_data->rtwdev; 3069 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif); 3070 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info; 3071 struct sk_buff *skb = iter_data->skb; 3072 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 3073 struct rtw89_rx_phy_ppdu *phy_ppdu = iter_data->phy_ppdu; 3074 struct ieee80211_bss_conf *bss_conf; 3075 struct rtw89_vif_link *rtwvif_link; 3076 const u8 *bssid = iter_data->bssid; 3077 struct rtw89_pkt_stat *pkt_stat; 3078 struct rtw89_bb_ctx *bb; 3079 const u8 *target_bssid; 3080 3081 rcu_read_lock(); 3082 3083 rtwvif_link = rtw89_vif_get_link_inst(rtwvif, desc_info->bb_sel); 3084 if (unlikely(!rtwvif_link)) 3085 goto out; 3086 3087 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false); 3088 if (!bss_conf->bssid) 3089 goto out; 3090 3091 if (ieee80211_is_trigger(hdr->frame_control)) { 3092 rtw89_stats_trigger_frame(rtwdev, rtwvif_link, bss_conf, skb); 3093 goto out; 3094 } 3095 3096 target_bssid = ieee80211_is_beacon(hdr->frame_control) && 3097 bss_conf->nontransmitted ? 3098 bss_conf->transmitter_bssid : bss_conf->bssid; 3099 if (!ether_addr_equal(target_bssid, bssid)) 3100 goto out; 3101 3102 bb = rtw89_get_bb_ctx(rtwdev, rtwvif_link->phy_idx); 3103 pkt_stat = &bb->cur_pkt_stat; 3104 3105 if (ieee80211_is_beacon(hdr->frame_control)) { 3106 if (vif->type == NL80211_IFTYPE_STATION && 3107 !test_bit(RTW89_FLAG_WOWLAN, rtwdev->flags)) { 3108 rtw89_vif_sync_bcn_tsf(rtwvif_link, hdr, skb->len); 3109 rtw89_fw_h2c_rssi_offload(rtwdev, phy_ppdu); 3110 } 3111 3112 if (phy_ppdu) { 3113 ewma_rssi_add(&bb->bcn_rssi, phy_ppdu->rssi_avg); 3114 if (!test_bit(RTW89_FLAG_LOW_POWER_MODE, rtwdev->flags)) 3115 rtwvif_link->bcn_bw_idx = phy_ppdu->bw_idx; 3116 } 3117 3118 pkt_stat->beacon_nr++; 3119 pkt_stat->beacon_rate = desc_info->data_rate; 3120 pkt_stat->beacon_len = skb->len; 3121 3122 rtw89_vif_rx_bcn_stat(rtwdev, skb); 3123 } 3124 3125 if (!ether_addr_equal(bss_conf->addr, hdr->addr1)) 3126 goto out; 3127 3128 if (desc_info->data_rate < RTW89_HW_RATE_NR) 3129 pkt_stat->rx_rate_cnt[desc_info->data_rate]++; 3130 3131 if (phy_ppdu && phy_ppdu->ofdm.has) { 3132 if (phy_ppdu->ldpc) 3133 pkt_stat->rx.ldpc++; 3134 else 3135 pkt_stat->rx.bcc++; 3136 3137 if (phy_ppdu->stbc) 3138 pkt_stat->rx.stbc++; 3139 3140 if (!phy_ppdu->su) 3141 pkt_stat->rx.mu++; 3142 else if (phy_ppdu->bf) 3143 pkt_stat->rx.su_bf++; 3144 else 3145 pkt_stat->rx.su_non_bf++; 3146 } 3147 3148 rtw89_traffic_stats_accu(rtwdev, rtwvif, skb, false, false); 3149 3150 out: 3151 rcu_read_unlock(); 3152 } 3153 3154 static void rtw89_core_rx_stats(struct rtw89_dev *rtwdev, 3155 struct rtw89_rx_phy_ppdu *phy_ppdu, 3156 struct rtw89_rx_desc_info *desc_info, 3157 struct sk_buff *skb) 3158 { 3159 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 3160 struct rtw89_vif_rx_stats_iter_data iter_data; 3161 3162 if (rtwdev->scanning && 3163 (ieee80211_is_beacon(hdr->frame_control) || 3164 ieee80211_is_probe_resp(hdr->frame_control))) 3165 rtw89_core_cancel_6ghz_probe_tx(rtwdev, skb); 3166 3167 rtw89_traffic_stats_accu(rtwdev, NULL, skb, true, false); 3168 3169 iter_data.rtwdev = rtwdev; 3170 iter_data.phy_ppdu = phy_ppdu; 3171 iter_data.desc_info = desc_info; 3172 iter_data.skb = skb; 3173 iter_data.bssid = get_hdr_bssid((struct ieee80211_hdr *)skb->data); 3174 rtw89_iterate_vifs_bh(rtwdev, rtw89_vif_rx_stats_iter, &iter_data); 3175 } 3176 3177 static void rtw89_correct_cck_chan(struct rtw89_dev *rtwdev, 3178 struct ieee80211_rx_status *status) 3179 { 3180 const struct rtw89_chan_rcd *rcd = 3181 rtw89_chan_rcd_get(rtwdev, RTW89_CHANCTX_0); 3182 u16 chan = rcd->prev_primary_channel; 3183 u8 band = rtw89_hw_to_nl80211_band(rcd->prev_band_type); 3184 3185 if (status->band != NL80211_BAND_2GHZ && 3186 status->encoding == RX_ENC_LEGACY && 3187 status->rate_idx < RTW89_HW_RATE_OFDM6) { 3188 status->freq = ieee80211_channel_to_frequency(chan, band); 3189 status->band = band; 3190 } 3191 } 3192 3193 static void rtw89_core_hw_to_sband_rate(struct ieee80211_rx_status *rx_status) 3194 { 3195 if (rx_status->band == NL80211_BAND_2GHZ || 3196 rx_status->encoding != RX_ENC_LEGACY) 3197 return; 3198 3199 /* Some control frames' freq(ACKs in this case) are reported wrong due 3200 * to FW notify timing, set to lowest rate to prevent overflow. 3201 */ 3202 if (rx_status->rate_idx < RTW89_HW_RATE_OFDM6) { 3203 rx_status->rate_idx = 0; 3204 return; 3205 } 3206 3207 /* No 4 CCK rates for non-2G */ 3208 rx_status->rate_idx -= 4; 3209 } 3210 3211 static 3212 void rtw89_core_update_rx_status_by_ppdu(struct rtw89_dev *rtwdev, 3213 struct ieee80211_rx_status *rx_status, 3214 struct rtw89_rx_phy_ppdu *phy_ppdu) 3215 { 3216 if (!(rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR)) 3217 return; 3218 3219 if (!phy_ppdu) 3220 return; 3221 3222 if (phy_ppdu->bf) 3223 rx_status->enc_flags |= RX_ENC_FLAG_BF; 3224 if (phy_ppdu->ldpc) 3225 rx_status->enc_flags |= RX_ENC_FLAG_LDPC; 3226 if (phy_ppdu->stbc) 3227 rx_status->enc_flags |= u8_encode_bits(1, RX_ENC_FLAG_STBC_MASK); 3228 } 3229 3230 static void rtw89_core_update_radiotap_vht(struct rtw89_dev *rtwdev, 3231 struct sk_buff *skb, 3232 struct ieee80211_rx_status *rx_status, 3233 struct rtw89_rx_phy_ppdu *phy_ppdu) 3234 { 3235 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 3236 const union rtw89_phy_sts_ie09 *ie09; 3237 struct ieee80211_radiotap_vht *vht; 3238 u8 group_id; 3239 u32 sig_a1; 3240 u16 paid; 3241 u8 nss; 3242 3243 if (!phy_ppdu) 3244 return; 3245 3246 ie09 = phy_ppdu->ie09; 3247 if (!ie09) 3248 return; 3249 3250 vht = skb_push(skb, sizeof(*vht)); 3251 memset(vht, 0, sizeof(*vht)); 3252 rx_status->flag |= RX_FLAG_RADIOTAP_VHT; 3253 3254 if (phy->physt_gen >= 2) 3255 sig_a1 = le64_get_bits(ie09->gen2.qw0, RTW89_PHY_STS_IE09_VHT_SIG_A1_MASK_GEN2); 3256 else 3257 sig_a1 = le64_get_bits(ie09->gen0.qw0, RTW89_PHY_STS_IE09_VHT_SIG_A1_MASK); 3258 3259 group_id = u32_get_bits(sig_a1, RTW89_PHY_STS_IE09_VHT_SIG_A1_GRP_ID); 3260 vht->group_id = group_id; 3261 3262 if (group_id == 0 || group_id == 63) { 3263 paid = u32_get_bits(sig_a1, RTW89_PHY_STS_IE09_VHT_SIG_A1_SU_PAID); 3264 vht->partial_aid = cpu_to_le16(paid); 3265 } else { 3266 /* let mac80211 fill vht->mcs_nss[0] */ 3267 #define WITH_MCS_IS_NOT_KNOWN(nss) ((nss) ? (15 << 4) | (nss) : 0) 3268 nss = u32_get_bits(sig_a1, RTW89_PHY_STS_IE09_VHT_SIG_A1_MU_NSTS1); 3269 vht->mcs_nss[1] = WITH_MCS_IS_NOT_KNOWN(nss); 3270 nss = u32_get_bits(sig_a1, RTW89_PHY_STS_IE09_VHT_SIG_A1_MU_NSTS2); 3271 vht->mcs_nss[2] = WITH_MCS_IS_NOT_KNOWN(nss); 3272 nss = u32_get_bits(sig_a1, RTW89_PHY_STS_IE09_VHT_SIG_A1_MU_NSTS3); 3273 vht->mcs_nss[3] = WITH_MCS_IS_NOT_KNOWN(nss); 3274 #undef WITH_MCS_IS_NOT_KNOWN 3275 } 3276 } 3277 3278 static void rtw89_core_update_radiotap_he_su(struct rtw89_dev *rtwdev, 3279 struct sk_buff *skb, 3280 struct ieee80211_rx_status *rx_status, 3281 struct ieee80211_radiotap_he *he, 3282 const union rtw89_phy_sts_ie09 *ie09) 3283 { 3284 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 3285 u32 sig_a1, sig_a2; 3286 u16 t; 3287 3288 if (!ie09) 3289 return; 3290 3291 if (phy->physt_gen >= 2) { 3292 sig_a1 = le64_get_bits(ie09->gen2.qw0, 3293 RTW89_PHY_STS_IE09_HE_SU_SIG_A1_MASK_GEN2); 3294 sig_a2 = le64_get_bits(ie09->gen2.qw0, 3295 RTW89_PHY_STS_IE09_HE_SU_SIG_A2_MASK_GEN2_L0); 3296 sig_a2 |= le64_get_bits(ie09->gen2.qw1, 3297 RTW89_PHY_STS_IE09_HE_SU_SIG_A2_MASK_GEN2_H6) << 6; 3298 } else { 3299 sig_a1 = le64_get_bits(ie09->gen0.qw0, RTW89_PHY_STS_IE09_HE_SU_SIG_A1_MASK); 3300 sig_a2 = le64_get_bits(ie09->gen0.qw0, RTW89_PHY_STS_IE09_HE_SU_SIG_A2_MASK); 3301 } 3302 3303 he->data1 |= cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_BEAM_CHANGE_KNOWN | 3304 IEEE80211_RADIOTAP_HE_DATA1_UL_DL_KNOWN | 3305 IEEE80211_RADIOTAP_HE_DATA1_BSS_COLOR_KNOWN | 3306 IEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE_KNOWN | 3307 IEEE80211_RADIOTAP_HE_DATA1_LDPC_XSYMSEG_KNOWN | 3308 IEEE80211_RADIOTAP_HE_DATA1_DOPPLER_KNOWN | 3309 0); 3310 3311 he->data2 |= cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_TXOP_KNOWN | 3312 IEEE80211_RADIOTAP_HE_DATA2_TXBF_KNOWN | 3313 IEEE80211_RADIOTAP_HE_DATA2_PRE_FEC_PAD_KNOWN | 3314 IEEE80211_RADIOTAP_HE_DATA2_PE_DISAMBIG_KNOWN | 3315 0); 3316 3317 t = u32_get_bits(sig_a1, RTW89_PHY_STS_IE09_HE_SU_SIG_A1_BEAM_CHANGE); 3318 he->data3 |= le16_encode_bits(t, IEEE80211_RADIOTAP_HE_DATA3_BEAM_CHANGE); 3319 3320 t = u32_get_bits(sig_a1, RTW89_PHY_STS_IE09_HE_SU_SIG_A1_ULDL); 3321 he->data3 |= le16_encode_bits(t, IEEE80211_RADIOTAP_HE_DATA3_UL_DL); 3322 3323 rx_status->he_dcm = u32_get_bits(sig_a1, RTW89_PHY_STS_IE09_HE_SU_SIG_A1_DCM); 3324 3325 t = u32_get_bits(sig_a1, RTW89_PHY_STS_IE09_HE_SU_SIG_A1_BSS_COLOR); 3326 he->data3 |= le16_encode_bits(t, IEEE80211_RADIOTAP_HE_DATA3_BSS_COLOR); 3327 3328 t = u32_get_bits(sig_a1, RTW89_PHY_STS_IE09_HE_SU_SIG_A1_SR); 3329 he->data4 |= le16_encode_bits(t, IEEE80211_RADIOTAP_HE_DATA4_SU_MU_SPTL_REUSE); 3330 3331 t = u32_get_bits(sig_a2, RTW89_PHY_STS_IE09_HE_SU_SIG_A2_TXOP); 3332 he->data6 |= le16_encode_bits(t, IEEE80211_RADIOTAP_HE_DATA6_TXOP); 3333 3334 t = u32_get_bits(sig_a2, RTW89_PHY_STS_IE09_HE_SU_SIG_A2_LDPC_XSYMSEG); 3335 he->data3 |= le16_encode_bits(t, IEEE80211_RADIOTAP_HE_DATA3_LDPC_XSYMSEG); 3336 3337 t = u32_get_bits(sig_a2, RTW89_PHY_STS_IE09_HE_SU_SIG_A2_BEAMFORMED); 3338 he->data5 |= le16_encode_bits(t, IEEE80211_RADIOTAP_HE_DATA5_TXBF); 3339 3340 t = u32_get_bits(sig_a2, RTW89_PHY_STS_IE09_HE_SU_SIG_A2_PREFEC); 3341 he->data5 |= le16_encode_bits(t, IEEE80211_RADIOTAP_HE_DATA5_PRE_FEC_PAD); 3342 3343 t = u32_get_bits(sig_a2, RTW89_PHY_STS_IE09_HE_SU_SIG_A2_PE); 3344 he->data5 |= le16_encode_bits(t, IEEE80211_RADIOTAP_HE_DATA5_PE_DISAMBIG); 3345 3346 t = u32_get_bits(sig_a2, RTW89_PHY_STS_IE09_HE_SU_SIG_A2_DOPPLER); 3347 he->data6 |= le16_encode_bits(t, IEEE80211_RADIOTAP_HE_DATA6_DOPPLER); 3348 } 3349 3350 static void rtw89_core_update_radiotap_he_tb(struct rtw89_dev *rtwdev, 3351 struct sk_buff *skb, 3352 struct ieee80211_rx_status *rx_status, 3353 struct ieee80211_radiotap_he *he, 3354 const union rtw89_phy_sts_ie09 *sig) 3355 { 3356 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 3357 u32 sig_a1, sig_a2; 3358 u16 t; 3359 3360 if (!sig) 3361 return; 3362 3363 if (phy->physt_gen >= 2) { 3364 sig_a1 = le64_get_bits(sig->gen2.qw0, 3365 RTW89_PHY_STS_IE09_HE_TB_SIG_A1_MASK_GEN2); 3366 sig_a2 = le64_get_bits(sig->gen2.qw0, 3367 RTW89_PHY_STS_IE09_HE_TB_SIG_A2_MASK_GEN2_L0); 3368 sig_a2 |= le64_get_bits(sig->gen2.qw1, 3369 RTW89_PHY_STS_IE09_HE_TB_SIG_A2_MASK_GEN2_H6); 3370 } else { 3371 sig_a1 = le64_get_bits(sig->gen0.qw0, RTW89_PHY_STS_IE09_HE_TB_SIG_A1_MASK); 3372 sig_a2 = le64_get_bits(sig->gen0.qw0, RTW89_PHY_STS_IE09_HE_TB_SIG_A2_MASK); 3373 } 3374 3375 he->data1 |= cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_BSS_COLOR_KNOWN | 3376 IEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE_KNOWN | 3377 IEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE2_KNOWN | 3378 IEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE3_KNOWN | 3379 IEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE4_KNOWN); 3380 3381 he->data2 |= cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_TXOP_KNOWN); 3382 3383 t = u32_get_bits(sig_a1, RTW89_PHY_STS_IE09_HE_TB_SIG_A1_BSS_COLOR); 3384 he->data3 |= le16_encode_bits(t, IEEE80211_RADIOTAP_HE_DATA3_BSS_COLOR); 3385 3386 t = u32_get_bits(sig_a1, RTW89_PHY_STS_IE09_HE_TB_SIG_A1_SB1); 3387 he->data4 |= le16_encode_bits(t, IEEE80211_RADIOTAP_HE_DATA4_TB_SPTL_REUSE1); 3388 t = u32_get_bits(sig_a1, RTW89_PHY_STS_IE09_HE_TB_SIG_A1_SB2); 3389 he->data4 |= le16_encode_bits(t, IEEE80211_RADIOTAP_HE_DATA4_TB_SPTL_REUSE2); 3390 t = u32_get_bits(sig_a1, RTW89_PHY_STS_IE09_HE_TB_SIG_A1_SB3); 3391 he->data4 |= le16_encode_bits(t, IEEE80211_RADIOTAP_HE_DATA4_TB_SPTL_REUSE3); 3392 t = u32_get_bits(sig_a1, RTW89_PHY_STS_IE09_HE_TB_SIG_A1_SB4); 3393 he->data4 |= le16_encode_bits(t, IEEE80211_RADIOTAP_HE_DATA4_TB_SPTL_REUSE4); 3394 3395 t = u32_get_bits(sig_a2, RTW89_PHY_STS_IE09_HE_TB_SIG_A2_TXOP); 3396 he->data6 |= le16_encode_bits(t, IEEE80211_RADIOTAP_HE_DATA6_TXOP); 3397 } 3398 3399 static u8 rtw89_core_he_mu_get_n_user_fields_by_ru_alloc(struct rtw89_dev *rtwdev, 3400 u8 ru_alloc) 3401 { 3402 u8 mu_users; 3403 3404 if (ru_alloc <= 15) { 3405 static const u8 entries_0_15[16] = { 3406 9, 8, 8, 7, 8, 7, 7, 6, 8, 7, 7, 6, 7, 6, 6, 5, 3407 }; 3408 3409 return entries_0_15[ru_alloc]; 3410 } 3411 3412 if (ru_alloc >= 16 && ru_alloc <= 95) { 3413 mu_users = ru_alloc & 0x07; 3414 3415 switch (ru_alloc & 0xF8) { 3416 case 16: case 24: return mu_users + 3; 3417 case 32: case 64: return mu_users + 6; 3418 case 40: case 48: case 72: case 80: return mu_users + 5; 3419 case 56: case 88: return mu_users + 4; 3420 } 3421 } 3422 3423 if (ru_alloc >= 96 && ru_alloc <= 111) { 3424 mu_users = ru_alloc & 0x03; 3425 mu_users += ru_alloc >> 2 & 0x03; 3426 3427 return mu_users + 2; 3428 } 3429 3430 if (ru_alloc == 112) 3431 return 4; 3432 3433 if (ru_alloc >= 113 && ru_alloc <= 115) 3434 return 0; 3435 3436 if (ru_alloc >= 128 && ru_alloc <= 191) { 3437 mu_users = ru_alloc & 0x07; 3438 mu_users += ru_alloc >> 3 & 0x07; 3439 3440 return mu_users + 3; 3441 } 3442 3443 if (ru_alloc >= 192 && ru_alloc <= 215) 3444 return (ru_alloc & 0x07) + 1; 3445 3446 return 0; 3447 } 3448 3449 static int rtw89_core_he_mu_get_n_ru_alloc(struct rtw89_dev *rtwdev, u8 bw) 3450 { 3451 switch (bw) { 3452 case 0: 3453 case 1: 3454 return 1; 3455 case 2: 3456 case 4: 3457 case 5: 3458 return 2; 3459 case 3: 3460 case 6: 3461 case 7: 3462 return 3; 3463 } 3464 3465 return 0; 3466 } 3467 3468 static void rtw89_core_he_mu_get_cc_ptr(struct rtw89_dev *rtwdev, 3469 const struct rtw89_phy_sts_ie10 *ie10, 3470 u8 bw, int n_ru, int n_center_26tone, 3471 const u8 **c1, const u8 **c2) 3472 { 3473 const u8 *sigb, *end_sigb; 3474 int total_bits, c2_offset; 3475 int n_user_fields = 0; 3476 const u8 *ptr; 3477 int i; 3478 3479 sigb = &ie10->sigb[0]; 3480 end_sigb = (const void *)ie10 + 3481 rtw89_core_get_phy_status_ie_len(rtwdev, (const void *)ie10); 3482 3483 ptr = sigb; 3484 if (ptr + n_ru + n_center_26tone >= end_sigb) 3485 return; 3486 *c1 = ptr; 3487 3488 if (bw == 0) /* 20MHz doesn't have content channel 2 */ 3489 return; 3490 3491 for (i = 0; i < n_ru; i++) 3492 n_user_fields += 3493 rtw89_core_he_mu_get_n_user_fields_by_ru_alloc(rtwdev, (*c1)[i]); 3494 3495 /* hardware report max 15 recordes, align 8 */ 3496 n_user_fields = min(n_user_fields, 15); 3497 3498 total_bits = n_ru * 8 + n_center_26tone + 10 + 3499 n_user_fields * 21 + DIV_ROUND_UP(n_user_fields, 2) * 10; 3500 c2_offset = ALIGN(DIV_ROUND_UP(total_bits, 8), 8); 3501 3502 ptr = &sigb[c2_offset]; 3503 if (ptr + n_ru + n_center_26tone >= end_sigb) 3504 return; 3505 3506 *c2 = ptr; 3507 } 3508 3509 static void rtw89_core_update_radiotap_he_mu(struct rtw89_dev *rtwdev, 3510 struct sk_buff *skb, 3511 struct ieee80211_rx_status *rx_status, 3512 struct ieee80211_radiotap_he *he, 3513 struct ieee80211_radiotap_he_mu *he_mu, 3514 const union rtw89_phy_sts_ie09 *ie09, 3515 const struct rtw89_phy_sts_ie10 *ie10) 3516 { 3517 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 3518 const u8 *c1 = NULL, *c2 = NULL; 3519 int n_center_26tone, n_ru, i; 3520 bool doppler, comp; 3521 u32 sig_a1, sig_a2; 3522 u16 t; 3523 u8 bw; 3524 3525 if (!ie09) 3526 return; 3527 3528 he->data1 |= cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_UL_DL_KNOWN | 3529 IEEE80211_RADIOTAP_HE_DATA1_BSS_COLOR_KNOWN | 3530 IEEE80211_RADIOTAP_HE_DATA1_SPTL_REUSE_KNOWN | 3531 IEEE80211_RADIOTAP_HE_DATA1_DOPPLER_KNOWN | 3532 IEEE80211_RADIOTAP_HE_DATA1_LDPC_XSYMSEG_KNOWN); 3533 he->data2 |= cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_TXOP_KNOWN | 3534 IEEE80211_RADIOTAP_HE_DATA2_MIDAMBLE_KNOWN | 3535 IEEE80211_RADIOTAP_HE_DATA2_PRE_FEC_PAD_KNOWN | 3536 IEEE80211_RADIOTAP_HE_DATA2_PE_DISAMBIG_KNOWN); 3537 3538 if (phy->physt_gen >= 2) { 3539 sig_a1 = le64_get_bits(ie09->gen2.qw0, 3540 RTW89_PHY_STS_IE09_HE_MU_SIG_A1_MASK_GEN2); 3541 sig_a2 = le64_get_bits(ie09->gen2.qw0, 3542 RTW89_PHY_STS_IE09_HE_MU_SIG_A2_MASK_GEN2_L0); 3543 sig_a2 |= le64_get_bits(ie09->gen2.qw1, 3544 RTW89_PHY_STS_IE09_HE_MU_SIG_A2_MASK_GEN2_H6) << 6; 3545 } else { 3546 sig_a1 = le64_get_bits(ie09->gen0.qw0, RTW89_PHY_STS_IE09_HE_MU_SIG_A1_MASK); 3547 sig_a2 = le64_get_bits(ie09->gen0.qw0, RTW89_PHY_STS_IE09_HE_MU_SIG_A2_MASK); 3548 } 3549 3550 t = u32_get_bits(sig_a1, RTW89_PHY_STS_IE09_HE_MU_SIG_A1_ULDL); 3551 he->data3 |= le16_encode_bits(t, IEEE80211_RADIOTAP_HE_DATA3_UL_DL); 3552 3553 t = u32_get_bits(sig_a1, RTW89_PHY_STS_IE09_HE_MU_SIG_A1_BSS_COLOR); 3554 he->data3 |= le16_encode_bits(t, IEEE80211_RADIOTAP_HE_DATA3_BSS_COLOR); 3555 3556 t = u32_get_bits(sig_a1, RTW89_PHY_STS_IE09_HE_MU_SIG_A1_SR); 3557 he->data4 |= le16_encode_bits(t, IEEE80211_RADIOTAP_HE_DATA4_SU_MU_SPTL_REUSE); 3558 3559 doppler = u32_get_bits(sig_a1, RTW89_PHY_STS_IE09_HE_MU_SIG_A1_DOPPLER); 3560 he->data6 |= le16_encode_bits(doppler, IEEE80211_RADIOTAP_HE_DATA6_DOPPLER); 3561 3562 t = u32_get_bits(sig_a2, RTW89_PHY_STS_IE09_HE_MU_SIG_A2_TXOP); 3563 he->data6 |= le16_encode_bits(t, IEEE80211_RADIOTAP_HE_DATA6_TXOP); 3564 3565 if (doppler) { 3566 t = u32_get_bits(sig_a2, RTW89_PHY_STS_IE09_HE_MU_SIG_A2_MID); 3567 he->data6 |= le16_encode_bits(t, IEEE80211_RADIOTAP_HE_DATA6_MIDAMBLE_PDCTY); 3568 } 3569 3570 t = u32_get_bits(sig_a2, RTW89_PHY_STS_IE09_HE_MU_SIG_A2_LPDC_XSYMSEG); 3571 he->data3 |= le16_encode_bits(t, IEEE80211_RADIOTAP_HE_DATA3_LDPC_XSYMSEG); 3572 3573 t = u32_get_bits(sig_a2, RTW89_PHY_STS_IE09_HE_MU_SIG_A2_FEC); 3574 he->data5 |= le16_encode_bits(t, IEEE80211_RADIOTAP_HE_DATA5_PRE_FEC_PAD); 3575 3576 t = u32_get_bits(sig_a2, RTW89_PHY_STS_IE09_HE_MU_SIG_A2_PE); 3577 he->data5 |= le16_encode_bits(t, IEEE80211_RADIOTAP_HE_DATA5_PE_DISAMBIG); 3578 3579 he_mu->flags1 |= cpu_to_le16(IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_MCS_KNOWN | 3580 IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_DCM_KNOWN | 3581 IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_SYMS_USERS_KNOWN | 3582 IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_COMP_KNOWN); 3583 he_mu->flags2 |= cpu_to_le16(IEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW_KNOWN); 3584 3585 t = u32_get_bits(sig_a1, RTW89_PHY_STS_IE09_HE_MU_SIG_A1_SIGB_MCS); 3586 he_mu->flags1 |= le16_encode_bits(t, IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_MCS); 3587 3588 t = u32_get_bits(sig_a1, RTW89_PHY_STS_IE09_HE_MU_SIG_A1_SIGB_DCM); 3589 he_mu->flags1 |= le16_encode_bits(t, IEEE80211_RADIOTAP_HE_MU_FLAGS1_SIG_B_DCM); 3590 3591 t = u32_get_bits(sig_a1, RTW89_PHY_STS_IE09_HE_MU_SIG_A1_SIGB_SYM_USR); 3592 he_mu->flags2 |= le16_encode_bits(t, IEEE80211_RADIOTAP_HE_MU_FLAGS2_SIG_B_SYMS_USERS); 3593 3594 comp = u32_get_bits(sig_a1, RTW89_PHY_STS_IE09_HE_MU_SIG_A1_SIGB_COM); 3595 he_mu->flags2 |= le16_encode_bits(comp, IEEE80211_RADIOTAP_HE_MU_FLAGS2_SIG_B_COMP); 3596 3597 bw = u32_get_bits(sig_a1, RTW89_PHY_STS_IE09_HE_MU_SIG_A1_BW); 3598 he_mu->flags2 |= le16_encode_bits(bw, IEEE80211_RADIOTAP_HE_MU_FLAGS2_BW_FROM_SIG_A_BW); 3599 3600 if (comp == 0 && bw <= 5) { 3601 u8 punc = clamp_t(int, bw - 3, 0, 2); 3602 3603 he_mu->flags2 |= 3604 cpu_to_le16(IEEE80211_RADIOTAP_HE_MU_FLAGS2_PUNC_FROM_SIG_A_BW_KNOWN); 3605 he_mu->flags2 |= 3606 le16_encode_bits(punc, IEEE80211_RADIOTAP_HE_MU_FLAGS2_PUNC_FROM_SIG_A_BW); 3607 } 3608 3609 /* the Common field in the HE-SIG-B field is not present */ 3610 if (comp || !ie10) 3611 return; 3612 3613 n_ru = rtw89_core_he_mu_get_n_ru_alloc(rtwdev, bw); 3614 n_center_26tone = bw >= 1; 3615 3616 rtw89_core_he_mu_get_cc_ptr(rtwdev, ie10, bw, n_ru, n_center_26tone, &c1, &c2); 3617 if (!c1) 3618 return; 3619 3620 he_mu->flags1 |= cpu_to_le16(IEEE80211_RADIOTAP_HE_MU_FLAGS1_CH1_RU_KNOWN | 3621 IEEE80211_RADIOTAP_HE_MU_FLAGS1_CH2_RU_KNOWN | 3622 IEEE80211_RADIOTAP_HE_MU_FLAGS1_CH1_CTR_26T_RU_KNOWN | 3623 IEEE80211_RADIOTAP_HE_MU_FLAGS1_CH2_CTR_26T_RU_KNOWN); 3624 3625 for (i = 0; i < n_ru; i++) { 3626 he_mu->ru_ch1[i] = c1[i]; 3627 if (c2) 3628 he_mu->ru_ch2[i] = c2[i]; 3629 } 3630 3631 if (n_center_26tone) { 3632 u8 ru; 3633 3634 ru = c1[n_ru] & BIT(0); 3635 he_mu->flags1 |= 3636 le16_encode_bits(ru, IEEE80211_RADIOTAP_HE_MU_FLAGS1_CH1_CTR_26T_RU); 3637 3638 ru = c2 ? c2[n_ru] & BIT(0) : 0; 3639 he_mu->flags1 |= 3640 le16_encode_bits(ru, IEEE80211_RADIOTAP_HE_MU_FLAGS2_CH2_CTR_26T_RU); 3641 } 3642 } 3643 3644 static u16 rtw89_core_get_radiotap_he_format(struct rtw89_rx_desc_info *desc_info) 3645 { 3646 switch (desc_info->ppdu_type) { 3647 case RTW89_RX_PPDU_T_HE_MU: 3648 return IEEE80211_RADIOTAP_HE_DATA1_FORMAT_MU; 3649 case RTW89_RX_PPDU_T_HE_ERSU: 3650 return IEEE80211_RADIOTAP_HE_DATA1_FORMAT_EXT_SU; 3651 case RTW89_RX_PPDU_T_HE_TB: 3652 return IEEE80211_RADIOTAP_HE_DATA1_FORMAT_TRIG; 3653 default: 3654 return IEEE80211_RADIOTAP_HE_DATA1_FORMAT_SU; 3655 } 3656 } 3657 3658 static void rtw89_core_update_radiotap_he(struct rtw89_dev *rtwdev, 3659 struct rtw89_rx_desc_info *desc_info, 3660 struct sk_buff *skb, 3661 struct ieee80211_rx_status *rx_status, 3662 struct rtw89_rx_phy_ppdu *phy_ppdu) 3663 { 3664 static const struct ieee80211_radiotap_he known_he = { 3665 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN | 3666 IEEE80211_RADIOTAP_HE_DATA1_CODING_KNOWN | 3667 IEEE80211_RADIOTAP_HE_DATA1_STBC_KNOWN | 3668 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN), 3669 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN), 3670 }; 3671 struct ieee80211_radiotap_he_mu *he_mu = NULL; 3672 const union rtw89_phy_sts_ie09 *ie09; 3673 const struct rtw89_phy_sts_ie10 *ie10; 3674 struct ieee80211_radiotap_he *he; 3675 u16 he_format; 3676 3677 he_format = rtw89_core_get_radiotap_he_format(desc_info); 3678 3679 /* Radiotap of HE-MU must be placed after HE (skb_push ahead) */ 3680 if (he_format == IEEE80211_RADIOTAP_HE_DATA1_FORMAT_MU) { 3681 rx_status->flag |= RX_FLAG_RADIOTAP_HE_MU; 3682 he_mu = skb_push(skb, sizeof(*he_mu)); 3683 memset(he_mu, 0, sizeof(*he_mu)); 3684 } 3685 3686 rx_status->flag |= RX_FLAG_RADIOTAP_HE; 3687 he = skb_push(skb, sizeof(*he)); 3688 *he = known_he; 3689 3690 he->data1 |= le16_encode_bits(he_format, IEEE80211_RADIOTAP_HE_DATA1_FORMAT_MASK); 3691 3692 if (!phy_ppdu) 3693 return; 3694 3695 ie09 = phy_ppdu->ie09; 3696 ie10 = phy_ppdu->ie10; 3697 3698 switch (he_format) { 3699 case IEEE80211_RADIOTAP_HE_DATA1_FORMAT_MU: 3700 rtw89_core_update_radiotap_he_mu(rtwdev, skb, rx_status, he, he_mu, 3701 ie09, ie10); 3702 break; 3703 case IEEE80211_RADIOTAP_HE_DATA1_FORMAT_TRIG: 3704 rtw89_core_update_radiotap_he_tb(rtwdev, skb, rx_status, he, ie09); 3705 break; 3706 default: 3707 rtw89_core_update_radiotap_he_su(rtwdev, skb, rx_status, he, ie09); 3708 break; 3709 } 3710 } 3711 3712 static const u8 rx_status_bw_to_radiotap_eht_usig[] = { 3713 [RATE_INFO_BW_20] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_20MHZ, 3714 [RATE_INFO_BW_5] = U8_MAX, 3715 [RATE_INFO_BW_10] = U8_MAX, 3716 [RATE_INFO_BW_40] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_40MHZ, 3717 [RATE_INFO_BW_80] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_80MHZ, 3718 [RATE_INFO_BW_160] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_160MHZ, 3719 [RATE_INFO_BW_HE_RU] = U8_MAX, 3720 [RATE_INFO_BW_320] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_320MHZ_1, 3721 [RATE_INFO_BW_EHT_RU] = U8_MAX, 3722 }; 3723 3724 static void rtw89_core_update_radiotap_eht(struct rtw89_dev *rtwdev, 3725 struct sk_buff *skb, 3726 struct ieee80211_rx_status *rx_status) 3727 { 3728 struct ieee80211_radiotap_eht_usig *usig; 3729 struct ieee80211_radiotap_eht *eht; 3730 struct ieee80211_radiotap_tlv *tlv; 3731 int eht_len = struct_size(eht, user_info, 1); 3732 int usig_len = sizeof(*usig); 3733 int len; 3734 u8 bw; 3735 3736 len = sizeof(*tlv) + ALIGN(eht_len, 4) + 3737 sizeof(*tlv) + ALIGN(usig_len, 4); 3738 3739 rx_status->flag |= RX_FLAG_RADIOTAP_TLV_AT_END; 3740 skb_reset_mac_header(skb); 3741 3742 /* EHT */ 3743 tlv = skb_push(skb, len); 3744 memset(tlv, 0, len); 3745 tlv->type = cpu_to_le16(IEEE80211_RADIOTAP_EHT); 3746 tlv->len = cpu_to_le16(eht_len); 3747 3748 eht = (struct ieee80211_radiotap_eht *)tlv->data; 3749 eht->known = cpu_to_le32(IEEE80211_RADIOTAP_EHT_KNOWN_GI); 3750 eht->data[0] = 3751 le32_encode_bits(rx_status->eht.gi, IEEE80211_RADIOTAP_EHT_DATA0_GI); 3752 3753 eht->user_info[0] = 3754 cpu_to_le32(IEEE80211_RADIOTAP_EHT_USER_INFO_MCS_KNOWN | 3755 IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_KNOWN_O | 3756 IEEE80211_RADIOTAP_EHT_USER_INFO_CODING_KNOWN); 3757 eht->user_info[0] |= 3758 le32_encode_bits(rx_status->rate_idx, IEEE80211_RADIOTAP_EHT_USER_INFO_MCS) | 3759 le32_encode_bits(rx_status->nss, IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_O); 3760 if (rx_status->enc_flags & RX_ENC_FLAG_LDPC) 3761 eht->user_info[0] |= 3762 cpu_to_le32(IEEE80211_RADIOTAP_EHT_USER_INFO_CODING); 3763 3764 /* U-SIG */ 3765 tlv = (void *)tlv + sizeof(*tlv) + ALIGN(eht_len, 4); 3766 tlv->type = cpu_to_le16(IEEE80211_RADIOTAP_EHT_USIG); 3767 tlv->len = cpu_to_le16(usig_len); 3768 3769 if (rx_status->bw >= ARRAY_SIZE(rx_status_bw_to_radiotap_eht_usig)) 3770 return; 3771 3772 bw = rx_status_bw_to_radiotap_eht_usig[rx_status->bw]; 3773 if (bw == U8_MAX) 3774 return; 3775 3776 usig = (struct ieee80211_radiotap_eht_usig *)tlv->data; 3777 usig->common = 3778 le32_encode_bits(1, IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_KNOWN) | 3779 le32_encode_bits(bw, IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW); 3780 } 3781 3782 static void rtw89_core_update_radiotap(struct rtw89_dev *rtwdev, 3783 struct rtw89_rx_desc_info *desc_info, 3784 struct sk_buff *skb, 3785 struct ieee80211_rx_status *rx_status, 3786 struct rtw89_rx_phy_ppdu *phy_ppdu) 3787 { 3788 if (!(rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR)) 3789 return; 3790 3791 /* 3792 * At transient adding a monitor vif from a station vif, the headroom 3793 * might not include radiotap. 3794 */ 3795 if (unlikely(skb_headroom(skb) < RTW89_RADIOTAP_ROOM + NET_SKB_PAD)) 3796 return; 3797 3798 if (rx_status->encoding == RX_ENC_VHT) 3799 rtw89_core_update_radiotap_vht(rtwdev, skb, rx_status, phy_ppdu); 3800 else if (rx_status->encoding == RX_ENC_HE) 3801 rtw89_core_update_radiotap_he(rtwdev, desc_info, skb, rx_status, phy_ppdu); 3802 else if (rx_status->encoding == RX_ENC_EHT) 3803 rtw89_core_update_radiotap_eht(rtwdev, skb, rx_status); 3804 } 3805 3806 static void rtw89_core_validate_rx_signal(struct ieee80211_rx_status *rx_status) 3807 { 3808 if (!rx_status->signal) 3809 rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL; 3810 } 3811 3812 static void rtw89_core_update_rx_freq_from_ie(struct rtw89_dev *rtwdev, 3813 struct sk_buff *skb, 3814 struct ieee80211_rx_status *rx_status) 3815 { 3816 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 3817 size_t hdr_len, ielen; 3818 u8 *variable; 3819 int chan; 3820 3821 if (!rtwdev->chip->rx_freq_from_ie) 3822 return; 3823 3824 if (!rtwdev->scanning) 3825 return; 3826 3827 if (ieee80211_is_beacon(mgmt->frame_control)) { 3828 variable = mgmt->u.beacon.variable; 3829 hdr_len = offsetof(struct ieee80211_mgmt, 3830 u.beacon.variable); 3831 } else if (ieee80211_is_probe_resp(mgmt->frame_control)) { 3832 variable = mgmt->u.probe_resp.variable; 3833 hdr_len = offsetof(struct ieee80211_mgmt, 3834 u.probe_resp.variable); 3835 } else { 3836 return; 3837 } 3838 3839 if (skb->len > hdr_len) 3840 ielen = skb->len - hdr_len; 3841 else 3842 return; 3843 3844 /* The parsing code for both 2GHz and 5GHz bands is the same in this 3845 * function. 3846 */ 3847 chan = cfg80211_get_ies_channel_number(variable, ielen, NL80211_BAND_2GHZ); 3848 if (chan == -1) 3849 return; 3850 3851 rx_status->band = chan > 14 ? RTW89_BAND_5G : RTW89_BAND_2G; 3852 rx_status->freq = ieee80211_channel_to_frequency(chan, rx_status->band); 3853 } 3854 3855 static void rtw89_core_correct_mcc_chan(struct rtw89_dev *rtwdev, 3856 struct rtw89_rx_desc_info *desc_info, 3857 struct ieee80211_rx_status *rx_status, 3858 struct rtw89_rx_phy_ppdu *phy_ppdu) 3859 { 3860 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen; 3861 struct rtw89_vif_link *rtwvif_link; 3862 struct rtw89_sta_link *rtwsta_link; 3863 const struct rtw89_chan *chan; 3864 u8 mac_id = desc_info->mac_id; 3865 enum rtw89_entity_mode mode; 3866 enum nl80211_band band; 3867 3868 mode = rtw89_get_entity_mode(rtwdev); 3869 if (likely(mode != RTW89_ENTITY_MODE_MCC)) 3870 return; 3871 3872 if (chip_gen == RTW89_CHIP_BE && phy_ppdu) 3873 mac_id = phy_ppdu->mac_id; 3874 3875 rcu_read_lock(); 3876 3877 rtwsta_link = rtw89_assoc_link_rcu_dereference(rtwdev, mac_id); 3878 if (!rtwsta_link) 3879 goto out; 3880 3881 rtwvif_link = rtwsta_link->rtwvif_link; 3882 chan = rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx); 3883 band = rtw89_hw_to_nl80211_band(chan->band_type); 3884 rx_status->freq = ieee80211_channel_to_frequency(chan->primary_channel, band); 3885 3886 out: 3887 rcu_read_unlock(); 3888 } 3889 3890 static void __rtw89_core_tid_rx_stats_reset(struct rtw89_tid_stats *tid_stats) 3891 { 3892 tid_stats->last_pn = -1LL; 3893 tid_stats->last_sn = IEEE80211_SN_MASK; 3894 } 3895 3896 void rtw89_core_tid_rx_stats_ctrl(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 3897 struct ieee80211_ampdu_params *params, bool enable) 3898 { 3899 struct rtw89_tid_stats *tid_stats; 3900 u16 tid = params->tid; 3901 3902 tid_stats = &rtwsta->tid_rx_stats[tid]; 3903 3904 if (enable) { 3905 __rtw89_core_tid_rx_stats_reset(tid_stats); 3906 tid_stats->started = true; 3907 } else { 3908 tid_stats->started = false; 3909 } 3910 } 3911 3912 void rtw89_core_tid_rx_stats_reset(struct rtw89_dev *rtwdev) 3913 { 3914 struct rtw89_tid_stats *tid_stats; 3915 struct ieee80211_sta *sta; 3916 struct rtw89_sta *rtwsta; 3917 u16 tid; 3918 3919 for_each_station(sta, rtwdev->hw) { 3920 rtwsta = sta_to_rtwsta(sta); 3921 3922 for (tid = 0; tid < IEEE80211_NUM_TIDS; tid++) { 3923 tid_stats = &rtwsta->tid_rx_stats[tid]; 3924 3925 if (!tid_stats->started) 3926 continue; 3927 3928 __rtw89_core_tid_rx_stats_reset(tid_stats); 3929 } 3930 } 3931 } 3932 3933 static bool rtw89_core_skb_pn_valid(struct rtw89_dev *rtwdev, 3934 struct rtw89_rx_desc_info *desc_info, 3935 struct sk_buff *skb) 3936 { 3937 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 3938 const struct rtw89_chip_info *chip = rtwdev->chip; 3939 struct rtw89_sta_link *rtwsta_link; 3940 struct rtw89_tid_stats *tid_stats; 3941 struct rtw89_sta *rtwsta; 3942 u8 tid, *ccmp_hdr_ptr; 3943 s64 pn, last_pn; 3944 u16 mpdu_sn; 3945 int hdrlen; 3946 3947 if (chip->chip_gen != RTW89_CHIP_AX) 3948 return true; 3949 3950 if (!ieee80211_is_data_qos(hdr->frame_control)) 3951 return true; 3952 3953 if (!desc_info->hw_dec || !desc_info->addr1_match) 3954 return true; 3955 3956 guard(rcu)(); 3957 3958 rtwsta_link = rtw89_assoc_link_rcu_dereference(rtwdev, desc_info->mac_id); 3959 if (!rtwsta_link) 3960 return true; 3961 3962 rtwsta = rtwsta_link->rtwsta; 3963 tid = ieee80211_get_tid(hdr); 3964 tid_stats = &rtwsta->tid_rx_stats[tid]; 3965 3966 if (!tid_stats->started) 3967 return true; 3968 3969 switch (desc_info->sec_type) { 3970 case RTW89_SEC_KEY_TYPE_CCMP128: 3971 case RTW89_SEC_KEY_TYPE_CCMP256: 3972 case RTW89_SEC_KEY_TYPE_GCMP128: 3973 case RTW89_SEC_KEY_TYPE_GCMP256: 3974 mpdu_sn = ieee80211_get_sn(hdr); 3975 hdrlen = ieee80211_hdrlen(hdr->frame_control); 3976 ccmp_hdr_ptr = skb->data + hdrlen; 3977 ccmp_hdr2pn(&pn, ccmp_hdr_ptr); 3978 last_pn = tid_stats->last_pn; 3979 3980 if (pn > last_pn) { 3981 if (last_pn != -1LL && 3982 ieee80211_sn_less(mpdu_sn, tid_stats->last_sn)) { 3983 dev_kfree_skb_any(skb); 3984 3985 return false; 3986 } 3987 3988 tid_stats->last_sn = mpdu_sn; 3989 tid_stats->last_pn = pn; 3990 } 3991 break; 3992 default: 3993 break; 3994 } 3995 3996 return true; 3997 } 3998 3999 static void rtw89_core_rx_to_mac80211(struct rtw89_dev *rtwdev, 4000 struct rtw89_rx_phy_ppdu *phy_ppdu, 4001 struct rtw89_rx_desc_info *desc_info, 4002 struct sk_buff *skb, 4003 struct ieee80211_rx_status *rx_status) 4004 { 4005 struct napi_struct *napi = &rtwdev->napi; 4006 4007 /* In low power mode, napi isn't scheduled. Receive it to netif. */ 4008 if (unlikely(!napi_is_scheduled(napi))) 4009 napi = NULL; 4010 4011 rtw89_core_hw_to_sband_rate(rx_status); 4012 rtw89_core_rx_stats(rtwdev, phy_ppdu, desc_info, skb); 4013 rtw89_core_update_rx_status_by_ppdu(rtwdev, rx_status, phy_ppdu); 4014 rtw89_core_update_radiotap(rtwdev, desc_info, skb, rx_status, phy_ppdu); 4015 rtw89_core_validate_rx_signal(rx_status); 4016 rtw89_core_update_rx_freq_from_ie(rtwdev, skb, rx_status); 4017 rtw89_core_correct_mcc_chan(rtwdev, desc_info, rx_status, phy_ppdu); 4018 4019 /* In low power mode, it does RX in thread context. */ 4020 local_bh_disable(); 4021 ieee80211_rx_napi(rtwdev->hw, NULL, skb, napi); 4022 local_bh_enable(); 4023 rtwdev->napi_budget_countdown--; 4024 } 4025 4026 static void rtw89_core_rx_pending_skb(struct rtw89_dev *rtwdev, 4027 struct rtw89_rx_phy_ppdu *phy_ppdu, 4028 struct rtw89_rx_desc_info *desc_ppdu, 4029 struct sk_buff *skb_ppdu) 4030 { 4031 u8 band = desc_ppdu->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 4032 int curr = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band]; 4033 struct sk_buff *skb = NULL, *tmp; 4034 struct ieee80211_rx_status *rx_status; 4035 4036 if (curr > RTW89_MAX_PPDU_CNT) 4037 return; 4038 4039 skb_queue_walk_safe(&rtwdev->ppdu_sts.rx_queue[band], skb, tmp) { 4040 skb_unlink(skb, &rtwdev->ppdu_sts.rx_queue[band]); 4041 rx_status = IEEE80211_SKB_RXCB(skb); 4042 if (rtw89_core_rx_ppdu_match(rtwdev, desc_ppdu, rx_status)) 4043 rtw89_chip_query_ppdu(rtwdev, phy_ppdu, rx_status); 4044 rtw89_correct_cck_chan(rtwdev, rx_status); 4045 rtw89_core_rx_to_mac80211(rtwdev, phy_ppdu, desc_ppdu, skb, rx_status); 4046 } 4047 } 4048 4049 static void rtw89_core_rx_process_ppdu_sts(struct rtw89_dev *rtwdev, 4050 struct rtw89_rx_desc_info *desc_ppdu, 4051 struct sk_buff *skb_ppdu) 4052 { 4053 struct rtw89_rx_phy_ppdu phy_ppdu = {.buf = skb_ppdu->data, .valid = false, 4054 .len = skb_ppdu->len, 4055 .to_self = desc_ppdu->addr1_match, 4056 .rate = desc_ppdu->data_rate, 4057 .mac_id = desc_ppdu->mac_id, 4058 .phy_idx = desc_ppdu->bb_sel}; 4059 int ret; 4060 4061 if (desc_ppdu->mac_info_valid) { 4062 ret = rtw89_core_rx_process_mac_ppdu(rtwdev, skb_ppdu, &phy_ppdu); 4063 if (ret) 4064 goto out; 4065 } 4066 4067 ret = rtw89_core_rx_process_phy_ppdu(rtwdev, &phy_ppdu); 4068 if (ret) 4069 goto out; 4070 4071 rtw89_core_rx_process_phy_sts(rtwdev, &phy_ppdu); 4072 4073 out: 4074 rtw89_core_rx_pending_skb(rtwdev, &phy_ppdu, desc_ppdu, skb_ppdu); 4075 dev_kfree_skb_any(skb_ppdu); 4076 } 4077 4078 static void rtw89_core_rx_process_report(struct rtw89_dev *rtwdev, 4079 struct rtw89_rx_desc_info *desc_info, 4080 struct sk_buff *skb) 4081 { 4082 switch (desc_info->pkt_type) { 4083 case RTW89_CORE_RX_TYPE_C2H: 4084 rtw89_fw_c2h_irqsafe(rtwdev, skb); 4085 break; 4086 case RTW89_CORE_RX_TYPE_PPDU_STAT: 4087 rtw89_core_rx_process_ppdu_sts(rtwdev, desc_info, skb); 4088 break; 4089 default: 4090 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "unhandled pkt_type=%d\n", 4091 desc_info->pkt_type); 4092 dev_kfree_skb_any(skb); 4093 break; 4094 } 4095 } 4096 4097 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 4098 struct rtw89_rx_desc_info *desc_info, 4099 u8 *data, u32 data_offset) 4100 { 4101 const struct rtw89_chip_info *chip = rtwdev->chip; 4102 struct rtw89_rxdesc_short *rxd_s; 4103 struct rtw89_rxdesc_long *rxd_l; 4104 u8 shift_len, drv_info_len; 4105 4106 rxd_s = (struct rtw89_rxdesc_short *)(data + data_offset); 4107 desc_info->pkt_size = le32_get_bits(rxd_s->dword0, AX_RXD_RPKT_LEN_MASK); 4108 desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, AX_RXD_DRV_INFO_SIZE_MASK); 4109 desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, AX_RXD_LONG_RXD); 4110 desc_info->pkt_type = le32_get_bits(rxd_s->dword0, AX_RXD_RPKT_TYPE_MASK); 4111 desc_info->mac_info_valid = le32_get_bits(rxd_s->dword0, AX_RXD_MAC_INFO_VLD); 4112 if (chip->chip_id == RTL8852C) 4113 desc_info->bw = le32_get_bits(rxd_s->dword1, AX_RXD_BW_v1_MASK); 4114 else 4115 desc_info->bw = le32_get_bits(rxd_s->dword1, AX_RXD_BW_MASK); 4116 desc_info->data_rate = le32_get_bits(rxd_s->dword1, AX_RXD_RX_DATARATE_MASK); 4117 desc_info->gi_ltf = le32_get_bits(rxd_s->dword1, AX_RXD_RX_GI_LTF_MASK); 4118 desc_info->user_id = le32_get_bits(rxd_s->dword1, AX_RXD_USER_ID_MASK); 4119 desc_info->sr_en = le32_get_bits(rxd_s->dword1, AX_RXD_SR_EN); 4120 desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword1, AX_RXD_PPDU_CNT_MASK); 4121 desc_info->ppdu_type = le32_get_bits(rxd_s->dword1, AX_RXD_PPDU_TYPE_MASK); 4122 desc_info->free_run_cnt = le32_get_bits(rxd_s->dword2, AX_RXD_FREERUN_CNT_MASK); 4123 desc_info->icv_err = le32_get_bits(rxd_s->dword3, AX_RXD_ICV_ERR); 4124 desc_info->crc32_err = le32_get_bits(rxd_s->dword3, AX_RXD_CRC32_ERR); 4125 desc_info->hw_dec = le32_get_bits(rxd_s->dword3, AX_RXD_HW_DEC); 4126 desc_info->sw_dec = le32_get_bits(rxd_s->dword3, AX_RXD_SW_DEC); 4127 desc_info->addr1_match = le32_get_bits(rxd_s->dword3, AX_RXD_A1_MATCH); 4128 desc_info->ampdu = le32_get_bits(rxd_s->dword3, AX_RXD_AMPDU); 4129 4130 shift_len = desc_info->shift << 1; /* 2-byte unit */ 4131 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */ 4132 desc_info->offset = data_offset + shift_len + drv_info_len; 4133 if (desc_info->long_rxdesc) 4134 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long); 4135 else 4136 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short); 4137 desc_info->ready = true; 4138 4139 if (!desc_info->long_rxdesc) 4140 return; 4141 4142 rxd_l = (struct rtw89_rxdesc_long *)(data + data_offset); 4143 desc_info->frame_type = le32_get_bits(rxd_l->dword4, AX_RXD_TYPE_MASK); 4144 desc_info->addr_cam_valid = le32_get_bits(rxd_l->dword5, AX_RXD_ADDR_CAM_VLD); 4145 desc_info->addr_cam_id = le32_get_bits(rxd_l->dword5, AX_RXD_ADDR_CAM_MASK); 4146 desc_info->sec_cam_id = le32_get_bits(rxd_l->dword5, AX_RXD_SEC_CAM_IDX_MASK); 4147 desc_info->mac_id = le32_get_bits(rxd_l->dword5, AX_RXD_MAC_ID_MASK); 4148 desc_info->rx_pl_id = le32_get_bits(rxd_l->dword5, AX_RXD_RX_PL_ID_MASK); 4149 desc_info->sec_type = le32_get_bits(rxd_l->dword7, AX_RXD_SEC_TYPE_MASK); 4150 } 4151 EXPORT_SYMBOL(rtw89_core_query_rxdesc); 4152 4153 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev, 4154 struct rtw89_rx_desc_info *desc_info, 4155 u8 *data, u32 data_offset) 4156 { 4157 struct rtw89_rxdesc_phy_rpt_v2 *rxd_rpt; 4158 struct rtw89_rxdesc_short_v2 *rxd_s; 4159 struct rtw89_rxdesc_long_v2 *rxd_l; 4160 u16 shift_len, drv_info_len, phy_rtp_len, hdr_cnv_len; 4161 4162 rxd_s = (struct rtw89_rxdesc_short_v2 *)(data + data_offset); 4163 4164 desc_info->pkt_size = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_LEN_MASK); 4165 desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, BE_RXD_DRV_INFO_SZ_MASK); 4166 desc_info->phy_rpt_size = le32_get_bits(rxd_s->dword0, BE_RXD_PHY_RPT_SZ_MASK); 4167 desc_info->hdr_cnv_size = le32_get_bits(rxd_s->dword0, BE_RXD_HDR_CNV_SZ_MASK); 4168 desc_info->shift = le32_get_bits(rxd_s->dword0, BE_RXD_SHIFT_MASK); 4169 desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, BE_RXD_LONG_RXD); 4170 desc_info->pkt_type = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_TYPE_MASK); 4171 desc_info->bb_sel = le32_get_bits(rxd_s->dword0, BE_RXD_BB_SEL); 4172 if (desc_info->pkt_type == RTW89_CORE_RX_TYPE_PPDU_STAT) 4173 desc_info->mac_info_valid = true; 4174 4175 desc_info->frame_type = le32_get_bits(rxd_s->dword2, BE_RXD_TYPE_MASK); 4176 desc_info->mac_id = le32_get_bits(rxd_s->dword2, BE_RXD_MAC_ID_MASK); 4177 desc_info->addr_cam_valid = le32_get_bits(rxd_s->dword2, BE_RXD_ADDR_CAM_VLD); 4178 4179 desc_info->sec_type = le32_get_bits(rxd_s->dword3, BE_RXD_SEC_TYPE_MASK); 4180 desc_info->icv_err = le32_get_bits(rxd_s->dword3, BE_RXD_ICV_ERR); 4181 desc_info->crc32_err = le32_get_bits(rxd_s->dword3, BE_RXD_CRC32_ERR); 4182 desc_info->hw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_HW_DEC); 4183 desc_info->sw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_SW_DEC); 4184 desc_info->addr1_match = le32_get_bits(rxd_s->dword3, BE_RXD_A1_MATCH); 4185 desc_info->ampdu = le32_get_bits(rxd_s->dword3, BE_RXD_AMPDU); 4186 4187 desc_info->bw = le32_get_bits(rxd_s->dword4, BE_RXD_BW_MASK); 4188 desc_info->data_rate = le32_get_bits(rxd_s->dword4, BE_RXD_RX_DATARATE_MASK); 4189 desc_info->gi_ltf = le32_get_bits(rxd_s->dword4, BE_RXD_RX_GI_LTF_MASK); 4190 desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_CNT_MASK); 4191 desc_info->ppdu_type = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_TYPE_MASK); 4192 4193 desc_info->free_run_cnt = le32_to_cpu(rxd_s->dword5); 4194 4195 shift_len = desc_info->shift << 1; /* 2-byte unit */ 4196 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */ 4197 phy_rtp_len = desc_info->phy_rpt_size << 3; /* 8-byte unit */ 4198 hdr_cnv_len = desc_info->hdr_cnv_size << 4; /* 16-byte unit */ 4199 desc_info->offset = data_offset + shift_len + drv_info_len + 4200 phy_rtp_len + hdr_cnv_len; 4201 4202 if (desc_info->long_rxdesc) 4203 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long_v2); 4204 else 4205 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short_v2); 4206 desc_info->ready = true; 4207 4208 if (phy_rtp_len == sizeof(*rxd_rpt)) { 4209 rxd_rpt = (struct rtw89_rxdesc_phy_rpt_v2 *)(data + data_offset + 4210 desc_info->rxd_len); 4211 desc_info->rssi = le32_get_bits(rxd_rpt->dword0, BE_RXD_PHY_RSSI); 4212 } 4213 4214 if (!desc_info->long_rxdesc) 4215 return; 4216 4217 rxd_l = (struct rtw89_rxdesc_long_v2 *)(data + data_offset); 4218 4219 desc_info->sr_en = le32_get_bits(rxd_l->dword6, BE_RXD_SR_EN); 4220 desc_info->user_id = le32_get_bits(rxd_l->dword6, BE_RXD_USER_ID_MASK); 4221 desc_info->addr_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_ADDR_CAM_MASK); 4222 desc_info->sec_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_SEC_CAM_IDX_MASK); 4223 4224 desc_info->rx_pl_id = le32_get_bits(rxd_l->dword7, BE_RXD_RX_PL_ID_MASK); 4225 } 4226 EXPORT_SYMBOL(rtw89_core_query_rxdesc_v2); 4227 4228 void rtw89_core_query_rxdesc_v3(struct rtw89_dev *rtwdev, 4229 struct rtw89_rx_desc_info *desc_info, 4230 u8 *data, u32 data_offset) 4231 { 4232 struct rtw89_rxdesc_phy_rpt_v2 *rxd_rpt; 4233 struct rtw89_rxdesc_short_v3 *rxd_s; 4234 struct rtw89_rxdesc_long_v3 *rxd_l; 4235 u16 shift_len, drv_info_len, phy_rtp_len, hdr_cnv_len; 4236 4237 rxd_s = (struct rtw89_rxdesc_short_v3 *)(data + data_offset); 4238 4239 desc_info->pkt_size = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_LEN_MASK); 4240 desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, BE_RXD_DRV_INFO_SZ_MASK); 4241 desc_info->phy_rpt_size = le32_get_bits(rxd_s->dword0, BE_RXD_PHY_RPT_SZ_MASK); 4242 desc_info->hdr_cnv_size = le32_get_bits(rxd_s->dword0, BE_RXD_HDR_CNV_SZ_MASK); 4243 desc_info->shift = le32_get_bits(rxd_s->dword0, BE_RXD_SHIFT_MASK); 4244 desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, BE_RXD_LONG_RXD); 4245 desc_info->pkt_type = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_TYPE_MASK); 4246 desc_info->bb_sel = le32_get_bits(rxd_s->dword0, BE_RXD_BB_SEL); 4247 if (desc_info->pkt_type == RTW89_CORE_RX_TYPE_PPDU_STAT) 4248 desc_info->mac_info_valid = true; 4249 4250 desc_info->frame_type = le32_get_bits(rxd_s->dword2, BE_RXD_TYPE_MASK); 4251 desc_info->mac_id = le32_get_bits(rxd_s->dword2, BE_RXD_MAC_ID_V1); 4252 desc_info->addr_cam_valid = le32_get_bits(rxd_s->dword2, BE_RXD_ADDR_CAM_VLD); 4253 4254 desc_info->sec_type = le32_get_bits(rxd_s->dword3, BE_RXD_SEC_TYPE_MASK); 4255 desc_info->icv_err = le32_get_bits(rxd_s->dword3, BE_RXD_ICV_ERR); 4256 desc_info->crc32_err = le32_get_bits(rxd_s->dword3, BE_RXD_CRC32_ERR); 4257 desc_info->hw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_HW_DEC); 4258 desc_info->sw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_SW_DEC); 4259 desc_info->addr1_match = le32_get_bits(rxd_s->dword3, BE_RXD_A1_MATCH); 4260 desc_info->ampdu = le32_get_bits(rxd_s->dword3, BE_RXD_AMPDU); 4261 4262 desc_info->bw = le32_get_bits(rxd_s->dword4, BE_RXD_BW_MASK); 4263 desc_info->data_rate = le32_get_bits(rxd_s->dword4, BE_RXD_RX_DATARATE_MASK); 4264 desc_info->gi_ltf = le32_get_bits(rxd_s->dword4, BE_RXD_RX_GI_LTF_MASK); 4265 desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_CNT_MASK); 4266 desc_info->ppdu_type = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_TYPE_MASK); 4267 4268 desc_info->free_run_cnt = le32_to_cpu(rxd_s->dword5); 4269 4270 shift_len = desc_info->shift << 1; /* 2-byte unit */ 4271 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */ 4272 phy_rtp_len = desc_info->phy_rpt_size << 3; /* 8-byte unit */ 4273 hdr_cnv_len = desc_info->hdr_cnv_size << 4; /* 16-byte unit */ 4274 desc_info->offset = data_offset + shift_len + drv_info_len + 4275 phy_rtp_len + hdr_cnv_len; 4276 4277 if (desc_info->long_rxdesc) 4278 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long_v3); 4279 else 4280 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short_v3); 4281 desc_info->ready = true; 4282 4283 if (phy_rtp_len == sizeof(*rxd_rpt)) { 4284 rxd_rpt = (struct rtw89_rxdesc_phy_rpt_v2 *)(data + data_offset + 4285 desc_info->rxd_len); 4286 desc_info->rssi = le32_get_bits(rxd_rpt->dword0, BE_RXD_PHY_RSSI); 4287 } 4288 4289 if (!desc_info->long_rxdesc) 4290 return; 4291 4292 rxd_l = (struct rtw89_rxdesc_long_v3 *)(data + data_offset); 4293 4294 desc_info->sr_en = le32_get_bits(rxd_l->dword6, BE_RXD_SR_EN); 4295 desc_info->user_id = le32_get_bits(rxd_l->dword6, BE_RXD_USER_ID_MASK); 4296 desc_info->addr_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_ADDR_CAM_V1); 4297 desc_info->sec_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_SEC_CAM_IDX_V1); 4298 4299 desc_info->rx_pl_id = le32_get_bits(rxd_l->dword7, BE_RXD_RX_PL_ID_MASK); 4300 } 4301 EXPORT_SYMBOL(rtw89_core_query_rxdesc_v3); 4302 4303 struct rtw89_core_iter_rx_status { 4304 struct rtw89_dev *rtwdev; 4305 struct ieee80211_rx_status *rx_status; 4306 struct rtw89_rx_desc_info *desc_info; 4307 u8 mac_id; 4308 }; 4309 4310 static 4311 void rtw89_core_stats_sta_rx_status_iter(void *data, struct ieee80211_sta *sta) 4312 { 4313 struct rtw89_core_iter_rx_status *iter_data = 4314 (struct rtw89_core_iter_rx_status *)data; 4315 struct ieee80211_rx_status *rx_status = iter_data->rx_status; 4316 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info; 4317 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 4318 struct rtw89_sta_link *rtwsta_link; 4319 u8 mac_id = iter_data->mac_id; 4320 4321 rtwsta_link = rtw89_sta_get_link_inst(rtwsta, desc_info->bb_sel); 4322 if (unlikely(!rtwsta_link)) 4323 return; 4324 4325 if (mac_id != rtwsta_link->mac_id) 4326 return; 4327 4328 rtwsta_link->rx_status = *rx_status; 4329 rtwsta_link->rx_hw_rate = desc_info->data_rate; 4330 } 4331 4332 static void rtw89_core_stats_sta_rx_status(struct rtw89_dev *rtwdev, 4333 struct rtw89_rx_desc_info *desc_info, 4334 struct ieee80211_rx_status *rx_status) 4335 { 4336 struct rtw89_core_iter_rx_status iter_data; 4337 4338 if (!desc_info->addr1_match || !desc_info->long_rxdesc) 4339 return; 4340 4341 if (desc_info->frame_type != RTW89_RX_TYPE_DATA) 4342 return; 4343 4344 iter_data.rtwdev = rtwdev; 4345 iter_data.rx_status = rx_status; 4346 iter_data.desc_info = desc_info; 4347 iter_data.mac_id = desc_info->mac_id; 4348 ieee80211_iterate_stations_atomic(rtwdev->hw, 4349 rtw89_core_stats_sta_rx_status_iter, 4350 &iter_data); 4351 } 4352 4353 static void rtw89_core_update_rx_status(struct rtw89_dev *rtwdev, 4354 struct sk_buff *skb, 4355 struct rtw89_rx_desc_info *desc_info, 4356 struct ieee80211_rx_status *rx_status) 4357 { 4358 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 4359 const struct cfg80211_chan_def *chandef = 4360 rtw89_chandef_get(rtwdev, RTW89_CHANCTX_0); 4361 u16 data_rate; 4362 u8 data_rate_mode; 4363 bool eht = false; 4364 u8 gi; 4365 4366 /* currently using single PHY */ 4367 rx_status->freq = chandef->chan->center_freq; 4368 rx_status->band = chandef->chan->band; 4369 4370 if (ieee80211_is_beacon(hdr->frame_control) || 4371 ieee80211_is_probe_resp(hdr->frame_control)) 4372 rx_status->boottime_ns = ktime_get_boottime_ns(); 4373 4374 if (rtwdev->scanning && 4375 RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &rtwdev->fw)) { 4376 const struct rtw89_chan *cur = rtw89_scan_chan_get(rtwdev); 4377 u8 chan = cur->primary_channel; 4378 u8 band = cur->band_type; 4379 enum nl80211_band nl_band; 4380 4381 nl_band = rtw89_hw_to_nl80211_band(band); 4382 rx_status->freq = ieee80211_channel_to_frequency(chan, nl_band); 4383 rx_status->band = nl_band; 4384 } 4385 4386 if (desc_info->icv_err || desc_info->crc32_err) 4387 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 4388 4389 if (desc_info->hw_dec && 4390 !(desc_info->sw_dec || desc_info->icv_err)) 4391 rx_status->flag |= RX_FLAG_DECRYPTED; 4392 4393 if (desc_info->ampdu) { 4394 rx_status->flag |= RX_FLAG_AMPDU_DETAILS; 4395 rx_status->ampdu_reference = desc_info->ppdu_cnt; 4396 } 4397 4398 rx_status->bw = rtw89_hw_to_rate_info_bw(desc_info->bw); 4399 4400 data_rate = desc_info->data_rate; 4401 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate); 4402 if (data_rate_mode == DATA_RATE_MODE_NON_HT) { 4403 rx_status->encoding = RX_ENC_LEGACY; 4404 rx_status->rate_idx = rtw89_get_data_not_ht_idx(rtwdev, data_rate); 4405 /* convert rate_idx after we get the correct band */ 4406 } else if (data_rate_mode == DATA_RATE_MODE_HT) { 4407 rx_status->encoding = RX_ENC_HT; 4408 rx_status->rate_idx = rtw89_get_data_ht_mcs(rtwdev, data_rate); 4409 if (desc_info->gi_ltf) 4410 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 4411 } else if (data_rate_mode == DATA_RATE_MODE_VHT) { 4412 rx_status->encoding = RX_ENC_VHT; 4413 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 4414 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1; 4415 if (desc_info->gi_ltf) 4416 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 4417 } else if (data_rate_mode == DATA_RATE_MODE_HE) { 4418 rx_status->encoding = RX_ENC_HE; 4419 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 4420 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1; 4421 } else if (data_rate_mode == DATA_RATE_MODE_EHT) { 4422 rx_status->encoding = RX_ENC_EHT; 4423 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 4424 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1; 4425 eht = true; 4426 } else { 4427 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); 4428 } 4429 4430 /* he_gi is used to match ppdu, so we always fill it. */ 4431 gi = rtw89_rxdesc_to_nl_he_eht_gi(rtwdev, desc_info->gi_ltf, true, eht); 4432 if (eht) 4433 rx_status->eht.gi = gi; 4434 else 4435 rx_status->he_gi = gi; 4436 rx_status->flag |= RX_FLAG_MACTIME_START; 4437 rx_status->mactime = desc_info->free_run_cnt; 4438 4439 rtw89_chip_phy_rpt_to_rssi(rtwdev, desc_info, rx_status); 4440 rtw89_core_stats_sta_rx_status(rtwdev, desc_info, rx_status); 4441 } 4442 4443 static enum rtw89_ps_mode rtw89_update_ps_mode(struct rtw89_dev *rtwdev) 4444 { 4445 const struct rtw89_chip_info *chip = rtwdev->chip; 4446 4447 if (rtwdev->hci.type != RTW89_HCI_TYPE_PCIE) 4448 return RTW89_PS_MODE_NONE; 4449 4450 if (rtw89_disable_ps_mode || !chip->ps_mode_supported || 4451 RTW89_CHK_FW_FEATURE(NO_DEEP_PS, &rtwdev->fw)) 4452 return RTW89_PS_MODE_NONE; 4453 4454 if ((chip->ps_mode_supported & BIT(RTW89_PS_MODE_PWR_GATED)) && 4455 !RTW89_CHK_FW_FEATURE(NO_LPS_PG, &rtwdev->fw)) 4456 return RTW89_PS_MODE_PWR_GATED; 4457 4458 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_CLK_GATED)) 4459 return RTW89_PS_MODE_CLK_GATED; 4460 4461 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_RFOFF)) 4462 return RTW89_PS_MODE_RFOFF; 4463 4464 return RTW89_PS_MODE_NONE; 4465 } 4466 4467 static void rtw89_core_flush_ppdu_rx_queue(struct rtw89_dev *rtwdev, 4468 struct rtw89_rx_desc_info *desc_info) 4469 { 4470 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts; 4471 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 4472 struct ieee80211_rx_status *rx_status; 4473 struct sk_buff *skb, *tmp; 4474 4475 skb_queue_walk_safe(&ppdu_sts->rx_queue[band], skb, tmp) { 4476 skb_unlink(skb, &ppdu_sts->rx_queue[band]); 4477 rx_status = IEEE80211_SKB_RXCB(skb); 4478 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb, rx_status); 4479 } 4480 } 4481 4482 static 4483 void rtw89_core_rx_pkt_hdl(struct rtw89_dev *rtwdev, const struct sk_buff *skb, 4484 const struct rtw89_rx_desc_info *desc_info) 4485 { 4486 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 4487 struct rtw89_sta_link *rtwsta_link; 4488 struct ieee80211_sta *sta; 4489 struct rtw89_sta *rtwsta; 4490 u8 macid = desc_info->mac_id; 4491 4492 if (!refcount_read(&rtwdev->refcount_ap_info)) 4493 return; 4494 4495 rcu_read_lock(); 4496 4497 rtwsta_link = rtw89_assoc_link_rcu_dereference(rtwdev, macid); 4498 if (!rtwsta_link) 4499 goto out; 4500 4501 rtwsta = rtwsta_link->rtwsta; 4502 if (!test_bit(RTW89_REMOTE_STA_IN_PS, rtwsta->flags)) 4503 goto out; 4504 4505 sta = rtwsta_to_sta(rtwsta); 4506 if (ieee80211_is_pspoll(hdr->frame_control)) 4507 ieee80211_sta_pspoll(sta); 4508 else if (ieee80211_has_pm(hdr->frame_control) && 4509 (ieee80211_is_data_qos(hdr->frame_control) || 4510 ieee80211_is_qos_nullfunc(hdr->frame_control))) 4511 ieee80211_sta_uapsd_trigger(sta, ieee80211_get_tid(hdr)); 4512 4513 out: 4514 rcu_read_unlock(); 4515 } 4516 4517 void rtw89_core_rx(struct rtw89_dev *rtwdev, 4518 struct rtw89_rx_desc_info *desc_info, 4519 struct sk_buff *skb) 4520 { 4521 struct ieee80211_rx_status *rx_status; 4522 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts; 4523 u8 ppdu_cnt = desc_info->ppdu_cnt; 4524 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 4525 4526 if (desc_info->pkt_type != RTW89_CORE_RX_TYPE_WIFI) { 4527 rtw89_core_rx_process_report(rtwdev, desc_info, skb); 4528 return; 4529 } 4530 4531 if (ppdu_sts->curr_rx_ppdu_cnt[band] != ppdu_cnt) { 4532 rtw89_core_flush_ppdu_rx_queue(rtwdev, desc_info); 4533 ppdu_sts->curr_rx_ppdu_cnt[band] = ppdu_cnt; 4534 } 4535 4536 rx_status = IEEE80211_SKB_RXCB(skb); 4537 memset(rx_status, 0, sizeof(*rx_status)); 4538 rtw89_core_update_rx_status(rtwdev, skb, desc_info, rx_status); 4539 rtw89_core_rx_pkt_hdl(rtwdev, skb, desc_info); 4540 4541 if (!rtw89_core_skb_pn_valid(rtwdev, desc_info, skb)) 4542 return; 4543 4544 if (desc_info->long_rxdesc && 4545 BIT(desc_info->frame_type) & PPDU_FILTER_BITMAP) 4546 skb_queue_tail(&ppdu_sts->rx_queue[band], skb); 4547 else 4548 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb, rx_status); 4549 } 4550 EXPORT_SYMBOL(rtw89_core_rx); 4551 4552 void rtw89_core_napi_start(struct rtw89_dev *rtwdev) 4553 { 4554 if (test_and_set_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags)) 4555 return; 4556 4557 napi_enable(&rtwdev->napi); 4558 } 4559 EXPORT_SYMBOL(rtw89_core_napi_start); 4560 4561 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev) 4562 { 4563 if (!test_and_clear_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags)) 4564 return; 4565 4566 napi_synchronize(&rtwdev->napi); 4567 napi_disable(&rtwdev->napi); 4568 } 4569 EXPORT_SYMBOL(rtw89_core_napi_stop); 4570 4571 int rtw89_core_napi_init(struct rtw89_dev *rtwdev) 4572 { 4573 rtwdev->netdev = alloc_netdev_dummy(0); 4574 if (!rtwdev->netdev) 4575 return -ENOMEM; 4576 4577 netif_napi_add(rtwdev->netdev, &rtwdev->napi, 4578 rtwdev->hci.ops->napi_poll); 4579 return 0; 4580 } 4581 EXPORT_SYMBOL(rtw89_core_napi_init); 4582 4583 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev) 4584 { 4585 rtw89_core_napi_stop(rtwdev); 4586 netif_napi_del(&rtwdev->napi); 4587 free_netdev(rtwdev->netdev); 4588 } 4589 EXPORT_SYMBOL(rtw89_core_napi_deinit); 4590 4591 static void rtw89_core_ba_work(struct work_struct *work) 4592 { 4593 struct rtw89_dev *rtwdev = 4594 container_of(work, struct rtw89_dev, ba_work); 4595 struct rtw89_txq *rtwtxq, *tmp; 4596 int ret; 4597 4598 spin_lock_bh(&rtwdev->ba_lock); 4599 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) { 4600 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 4601 struct ieee80211_sta *sta = txq->sta; 4602 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 4603 u8 tid = txq->tid; 4604 4605 if (!sta) { 4606 rtw89_warn(rtwdev, "cannot start BA without sta\n"); 4607 goto skip_ba_work; 4608 } 4609 4610 if (rtwsta->disassoc) { 4611 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 4612 "cannot start BA with disassoc sta\n"); 4613 goto skip_ba_work; 4614 } 4615 4616 ret = ieee80211_start_tx_ba_session(sta, tid, 0); 4617 if (ret) { 4618 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 4619 "failed to setup BA session for %pM:%2d: %d\n", 4620 sta->addr, tid, ret); 4621 if (ret == -EINVAL) 4622 set_bit(RTW89_TXQ_F_BLOCK_BA, rtwtxq->flags); 4623 } 4624 skip_ba_work: 4625 list_del_init(&rtwtxq->list); 4626 } 4627 spin_unlock_bh(&rtwdev->ba_lock); 4628 } 4629 4630 void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev, 4631 struct ieee80211_sta *sta) 4632 { 4633 struct rtw89_txq *rtwtxq, *tmp; 4634 4635 spin_lock_bh(&rtwdev->ba_lock); 4636 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) { 4637 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 4638 4639 if (sta == txq->sta) 4640 list_del_init(&rtwtxq->list); 4641 } 4642 spin_unlock_bh(&rtwdev->ba_lock); 4643 } 4644 4645 void rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev *rtwdev, 4646 struct ieee80211_sta *sta) 4647 { 4648 struct rtw89_txq *rtwtxq, *tmp; 4649 4650 spin_lock_bh(&rtwdev->ba_lock); 4651 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) { 4652 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 4653 4654 if (sta == txq->sta) { 4655 clear_bit(RTW89_TXQ_F_FORBID_BA, rtwtxq->flags); 4656 list_del_init(&rtwtxq->list); 4657 } 4658 } 4659 spin_unlock_bh(&rtwdev->ba_lock); 4660 } 4661 4662 void rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev *rtwdev, 4663 struct ieee80211_sta *sta) 4664 { 4665 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 4666 struct sk_buff *skb; 4667 4668 while ((skb = skb_dequeue(&rtwsta->roc_queue))) 4669 dev_kfree_skb_any(skb); 4670 } 4671 4672 static void rtw89_core_stop_tx_ba_session(struct rtw89_dev *rtwdev, 4673 struct rtw89_txq *rtwtxq) 4674 { 4675 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 4676 struct ieee80211_sta *sta = txq->sta; 4677 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 4678 4679 if (unlikely(!rtwsta) || unlikely(rtwsta->disassoc)) 4680 return; 4681 4682 if (!test_bit(RTW89_TXQ_F_AMPDU, rtwtxq->flags) || 4683 test_bit(RTW89_TXQ_F_FORBID_BA, rtwtxq->flags)) 4684 return; 4685 4686 spin_lock_bh(&rtwdev->ba_lock); 4687 if (!test_and_set_bit(RTW89_TXQ_F_FORBID_BA, rtwtxq->flags)) 4688 list_add_tail(&rtwtxq->list, &rtwdev->forbid_ba_list); 4689 spin_unlock_bh(&rtwdev->ba_lock); 4690 4691 ieee80211_stop_tx_ba_session(sta, txq->tid); 4692 cancel_delayed_work(&rtwdev->forbid_ba_work); 4693 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->forbid_ba_work, 4694 RTW89_FORBID_BA_TIMER); 4695 } 4696 4697 static void rtw89_core_txq_check_agg(struct rtw89_dev *rtwdev, 4698 struct rtw89_txq *rtwtxq, 4699 struct sk_buff *skb) 4700 { 4701 struct ieee80211_hw *hw = rtwdev->hw; 4702 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 4703 struct ieee80211_sta *sta = txq->sta; 4704 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 4705 4706 if (test_bit(RTW89_TXQ_F_FORBID_BA, rtwtxq->flags)) 4707 return; 4708 4709 if (unlikely(skb->protocol == cpu_to_be16(ETH_P_PAE))) { 4710 rtw89_core_stop_tx_ba_session(rtwdev, rtwtxq); 4711 return; 4712 } 4713 4714 if (unlikely(!sta)) 4715 return; 4716 4717 if (unlikely(test_bit(RTW89_TXQ_F_BLOCK_BA, rtwtxq->flags))) 4718 return; 4719 4720 if (test_bit(RTW89_TXQ_F_AMPDU, rtwtxq->flags)) { 4721 IEEE80211_SKB_CB(skb)->flags |= IEEE80211_TX_CTL_AMPDU; 4722 return; 4723 } 4724 4725 spin_lock_bh(&rtwdev->ba_lock); 4726 if (!rtwsta->disassoc && list_empty(&rtwtxq->list)) { 4727 list_add_tail(&rtwtxq->list, &rtwdev->ba_list); 4728 ieee80211_queue_work(hw, &rtwdev->ba_work); 4729 } 4730 spin_unlock_bh(&rtwdev->ba_lock); 4731 } 4732 4733 static void rtw89_core_txq_push(struct rtw89_dev *rtwdev, 4734 struct rtw89_txq *rtwtxq, 4735 unsigned long frame_cnt, 4736 unsigned long byte_cnt) 4737 { 4738 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 4739 struct ieee80211_vif *vif = txq->vif; 4740 struct ieee80211_sta *sta = txq->sta; 4741 struct sk_buff *skb; 4742 unsigned long i; 4743 int ret; 4744 4745 rcu_read_lock(); 4746 for (i = 0; i < frame_cnt; i++) { 4747 skb = ieee80211_tx_dequeue_ni(rtwdev->hw, txq); 4748 if (!skb) { 4749 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "dequeue a NULL skb\n"); 4750 goto out; 4751 } 4752 rtw89_core_txq_check_agg(rtwdev, rtwtxq, skb); 4753 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, NULL); 4754 if (ret) { 4755 rtw89_err(rtwdev, "failed to push txq: %d\n", ret); 4756 ieee80211_free_txskb(rtwdev->hw, skb); 4757 break; 4758 } 4759 } 4760 out: 4761 rcu_read_unlock(); 4762 } 4763 4764 static u32 rtw89_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 tid) 4765 { 4766 u8 qsel, ch_dma; 4767 4768 qsel = rtw89_core_get_qsel(rtwdev, tid); 4769 ch_dma = rtw89_chip_get_ch_dma(rtwdev, qsel); 4770 4771 return rtw89_hci_check_and_reclaim_tx_resource(rtwdev, ch_dma); 4772 } 4773 4774 static bool rtw89_core_txq_agg_wait(struct rtw89_dev *rtwdev, 4775 struct ieee80211_txq *txq, 4776 unsigned long *frame_cnt, 4777 bool *sched_txq, bool *reinvoke) 4778 { 4779 struct rtw89_txq *rtwtxq = (struct rtw89_txq *)txq->drv_priv; 4780 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(txq->sta); 4781 struct rtw89_sta_link *rtwsta_link; 4782 4783 if (!rtwsta) 4784 return false; 4785 4786 rtwsta_link = rtw89_get_designated_link(rtwsta); 4787 if (unlikely(!rtwsta_link)) { 4788 rtw89_err(rtwdev, "agg wait: find no designated link\n"); 4789 return false; 4790 } 4791 4792 if (rtwsta_link->max_agg_wait <= 0) 4793 return false; 4794 4795 if (rtwdev->stats.tx_tfc_lv <= RTW89_TFC_MID) 4796 return false; 4797 4798 if (*frame_cnt > 1) { 4799 *frame_cnt -= 1; 4800 *sched_txq = true; 4801 *reinvoke = true; 4802 rtwtxq->wait_cnt = 1; 4803 return false; 4804 } 4805 4806 if (*frame_cnt == 1 && rtwtxq->wait_cnt < rtwsta_link->max_agg_wait) { 4807 *reinvoke = true; 4808 rtwtxq->wait_cnt++; 4809 return true; 4810 } 4811 4812 rtwtxq->wait_cnt = 0; 4813 return false; 4814 } 4815 4816 static void rtw89_core_txq_schedule(struct rtw89_dev *rtwdev, u8 ac, bool *reinvoke) 4817 { 4818 struct ieee80211_hw *hw = rtwdev->hw; 4819 struct ieee80211_txq *txq; 4820 struct rtw89_vif *rtwvif; 4821 struct rtw89_txq *rtwtxq; 4822 unsigned long frame_cnt; 4823 unsigned long byte_cnt; 4824 u32 tx_resource; 4825 bool sched_txq; 4826 4827 ieee80211_txq_schedule_start(hw, ac); 4828 while ((txq = ieee80211_next_txq(hw, ac))) { 4829 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 4830 rtwvif = vif_to_rtwvif(txq->vif); 4831 4832 if (rtwvif->offchan) { 4833 ieee80211_return_txq(hw, txq, true); 4834 continue; 4835 } 4836 tx_resource = rtw89_check_and_reclaim_tx_resource(rtwdev, txq->tid); 4837 sched_txq = false; 4838 4839 ieee80211_txq_get_depth(txq, &frame_cnt, &byte_cnt); 4840 if (rtw89_core_txq_agg_wait(rtwdev, txq, &frame_cnt, &sched_txq, reinvoke)) { 4841 ieee80211_return_txq(hw, txq, true); 4842 continue; 4843 } 4844 frame_cnt = min_t(unsigned long, frame_cnt, tx_resource); 4845 rtw89_core_txq_push(rtwdev, rtwtxq, frame_cnt, byte_cnt); 4846 ieee80211_return_txq(hw, txq, sched_txq); 4847 if (frame_cnt != 0) 4848 rtw89_core_tx_kick_off(rtwdev, rtw89_core_get_qsel(rtwdev, txq->tid)); 4849 4850 /* bound of tx_resource could get stuck due to burst traffic */ 4851 if (frame_cnt == tx_resource) 4852 *reinvoke = true; 4853 } 4854 ieee80211_txq_schedule_end(hw, ac); 4855 } 4856 4857 static void rtw89_ips_work(struct wiphy *wiphy, struct wiphy_work *work) 4858 { 4859 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 4860 ips_work); 4861 4862 lockdep_assert_wiphy(wiphy); 4863 4864 rtw89_enter_ips_by_hwflags(rtwdev); 4865 } 4866 4867 static void rtw89_core_txq_work(struct work_struct *w) 4868 { 4869 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, txq_work); 4870 bool reinvoke = false; 4871 u8 ac; 4872 4873 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) 4874 rtw89_core_txq_schedule(rtwdev, ac, &reinvoke); 4875 4876 if (reinvoke) { 4877 /* reinvoke to process the last frame */ 4878 mod_delayed_work(rtwdev->txq_wq, &rtwdev->txq_reinvoke_work, 1); 4879 } 4880 } 4881 4882 static void rtw89_core_txq_reinvoke_work(struct work_struct *w) 4883 { 4884 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, 4885 txq_reinvoke_work.work); 4886 4887 queue_work(rtwdev->txq_wq, &rtwdev->txq_work); 4888 } 4889 4890 static void rtw89_forbid_ba_work(struct work_struct *w) 4891 { 4892 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, 4893 forbid_ba_work.work); 4894 struct rtw89_txq *rtwtxq, *tmp; 4895 4896 spin_lock_bh(&rtwdev->ba_lock); 4897 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) { 4898 clear_bit(RTW89_TXQ_F_FORBID_BA, rtwtxq->flags); 4899 list_del_init(&rtwtxq->list); 4900 } 4901 spin_unlock_bh(&rtwdev->ba_lock); 4902 } 4903 4904 static void rtw89_core_sta_pending_tx_iter(void *data, 4905 struct ieee80211_sta *sta) 4906 { 4907 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 4908 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 4909 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 4910 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 4911 struct rtw89_vif_link *target = data; 4912 struct rtw89_vif_link *rtwvif_link; 4913 unsigned int link_id; 4914 struct sk_buff *skb; 4915 int qsel, ret; 4916 4917 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 4918 if (rtwvif_link->chanctx_idx == target->chanctx_idx) 4919 goto bottom; 4920 4921 return; 4922 4923 bottom: 4924 if (skb_queue_len(&rtwsta->roc_queue) == 0) 4925 return; 4926 4927 while ((skb = skb_dequeue(&rtwsta->roc_queue))) { 4928 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, &qsel); 4929 if (ret) { 4930 rtw89_warn(rtwdev, "pending tx failed with %d\n", ret); 4931 dev_kfree_skb_any(skb); 4932 } else { 4933 rtw89_core_tx_kick_off(rtwdev, qsel); 4934 } 4935 } 4936 } 4937 4938 static void rtw89_core_handle_sta_pending_tx(struct rtw89_dev *rtwdev, 4939 struct rtw89_vif_link *rtwvif_link) 4940 { 4941 ieee80211_iterate_stations_atomic(rtwdev->hw, 4942 rtw89_core_sta_pending_tx_iter, 4943 rtwvif_link); 4944 } 4945 4946 int rtw89_core_send_nullfunc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 4947 bool qos, bool ps, int timeout) 4948 { 4949 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 4950 int link_id = ieee80211_vif_is_mld(vif) ? rtwvif_link->link_id : -1; 4951 struct rtw89_sta_link *rtwsta_link; 4952 struct rtw89_tx_wait_info *wait; 4953 struct ieee80211_sta *sta; 4954 struct ieee80211_hdr *hdr; 4955 struct rtw89_sta *rtwsta; 4956 struct sk_buff *skb; 4957 int ret, qsel; 4958 4959 if (vif->type != NL80211_IFTYPE_STATION || !vif->cfg.assoc) 4960 return 0; 4961 4962 wait = kzalloc_obj(*wait); 4963 if (!wait) 4964 return -ENOMEM; 4965 4966 init_completion(&wait->completion); 4967 4968 rcu_read_lock(); 4969 sta = ieee80211_find_sta(vif, vif->cfg.ap_addr); 4970 if (!sta) { 4971 ret = -EINVAL; 4972 goto out; 4973 } 4974 rtwsta = sta_to_rtwsta(sta); 4975 4976 skb = ieee80211_nullfunc_get(rtwdev->hw, vif, link_id, qos); 4977 if (!skb) { 4978 ret = -ENOMEM; 4979 goto out; 4980 } 4981 4982 wait->skb = skb; 4983 4984 hdr = (struct ieee80211_hdr *)skb->data; 4985 if (ps) 4986 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 4987 4988 rtwsta_link = rtwsta->links[rtwvif_link->link_id]; 4989 if (unlikely(!rtwsta_link)) { 4990 ret = -ENOLINK; 4991 dev_kfree_skb_any(skb); 4992 goto out; 4993 } 4994 4995 ret = rtw89_core_tx_write_link(rtwdev, rtwvif_link, rtwsta_link, skb, &qsel, wait); 4996 if (ret) { 4997 rtw89_warn(rtwdev, "nullfunc transmit failed: %d\n", ret); 4998 dev_kfree_skb_any(skb); 4999 goto out; 5000 } 5001 5002 rcu_read_unlock(); 5003 5004 return rtw89_core_tx_kick_off_and_wait(rtwdev, skb, wait, qsel, 5005 timeout); 5006 out: 5007 rcu_read_unlock(); 5008 kfree(wait); 5009 5010 return ret; 5011 } 5012 5013 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 5014 { 5015 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 5016 struct rtw89_chanctx_pause_parm pause_parm = { 5017 .rsn = RTW89_CHANCTX_PAUSE_REASON_ROC, 5018 }; 5019 struct ieee80211_hw *hw = rtwdev->hw; 5020 struct rtw89_roc *roc = &rtwvif->roc; 5021 struct rtw89_vif_link *rtwvif_link; 5022 struct cfg80211_chan_def roc_chan; 5023 struct rtw89_vif *tmp_vif; 5024 u32 reg; 5025 int ret; 5026 5027 lockdep_assert_wiphy(hw->wiphy); 5028 5029 rtw89_leave_ips_by_hwflags(rtwdev); 5030 rtw89_leave_lps(rtwdev); 5031 5032 rtwvif_link = rtw89_get_designated_link(rtwvif); 5033 if (unlikely(!rtwvif_link)) { 5034 rtw89_err(rtwdev, "roc start: find no designated link\n"); 5035 return; 5036 } 5037 5038 roc->link_id = rtwvif_link->link_id; 5039 5040 pause_parm.trigger = rtwvif_link; 5041 rtw89_chanctx_pause(rtwdev, &pause_parm); 5042 5043 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif_link, true, true, 5044 RTW89_ROC_TX_TIMEOUT); 5045 if (ret) 5046 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 5047 "roc send null-1 failed: %d\n", ret); 5048 5049 rtw89_for_each_rtwvif(rtwdev, tmp_vif) { 5050 struct rtw89_vif_link *tmp_link; 5051 unsigned int link_id; 5052 5053 rtw89_vif_for_each_link(tmp_vif, tmp_link, link_id) { 5054 if (tmp_link->chanctx_idx == rtwvif_link->chanctx_idx) { 5055 tmp_vif->offchan = true; 5056 break; 5057 } 5058 } 5059 } 5060 5061 cfg80211_chandef_create(&roc_chan, &roc->chan, NL80211_CHAN_NO_HT); 5062 rtw89_config_roc_chandef(rtwdev, rtwvif_link, &roc_chan); 5063 rtw89_set_channel(rtwdev); 5064 5065 reg = rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, rtwvif_link->mac_idx); 5066 rtw89_write32_clr(rtwdev, reg, B_AX_A_UC_CAM_MATCH | B_AX_A_BC_CAM_MATCH); 5067 5068 rtw89_phy_dig_suspend(rtwdev); 5069 ieee80211_ready_on_channel(hw); 5070 wiphy_delayed_work_cancel(hw->wiphy, &rtwvif->roc.roc_work); 5071 wiphy_delayed_work_queue(hw->wiphy, &rtwvif->roc.roc_work, 5072 msecs_to_jiffies(rtwvif->roc.duration)); 5073 } 5074 5075 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 5076 { 5077 struct ieee80211_hw *hw = rtwdev->hw; 5078 struct rtw89_roc *roc = &rtwvif->roc; 5079 struct rtw89_vif_link *rtwvif_link; 5080 struct rtw89_vif *tmp_vif; 5081 int ret; 5082 5083 lockdep_assert_wiphy(hw->wiphy); 5084 5085 ieee80211_remain_on_channel_expired(hw); 5086 5087 rtw89_leave_ips_by_hwflags(rtwdev); 5088 rtw89_leave_lps(rtwdev); 5089 5090 rtwvif_link = rtwvif->links[roc->link_id]; 5091 if (unlikely(!rtwvif_link)) { 5092 rtw89_err(rtwdev, "roc end: find no link (link id %u)\n", 5093 roc->link_id); 5094 return; 5095 } 5096 5097 rtw89_mac_set_rx_fltr(rtwdev, rtwvif_link->mac_idx, rtwdev->hal.rx_fltr); 5098 5099 roc->state = RTW89_ROC_IDLE; 5100 rtw89_config_roc_chandef(rtwdev, rtwvif_link, NULL); 5101 rtw89_chanctx_proceed(rtwdev, NULL); 5102 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif_link, true, false, 5103 RTW89_ROC_TX_TIMEOUT); 5104 if (ret) 5105 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 5106 "roc send null-0 failed: %d\n", ret); 5107 5108 rtw89_for_each_rtwvif(rtwdev, tmp_vif) 5109 tmp_vif->offchan = false; 5110 5111 rtw89_core_handle_sta_pending_tx(rtwdev, rtwvif_link); 5112 queue_work(rtwdev->txq_wq, &rtwdev->txq_work); 5113 rtw89_phy_dig_resume(rtwdev, true); 5114 5115 if (hw->conf.flags & IEEE80211_CONF_IDLE) 5116 wiphy_delayed_work_queue(hw->wiphy, &roc->roc_work, 5117 msecs_to_jiffies(RTW89_ROC_IDLE_TIMEOUT)); 5118 } 5119 5120 void rtw89_roc_work(struct wiphy *wiphy, struct wiphy_work *work) 5121 { 5122 struct rtw89_vif *rtwvif = container_of(work, struct rtw89_vif, 5123 roc.roc_work.work); 5124 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 5125 struct rtw89_roc *roc = &rtwvif->roc; 5126 5127 lockdep_assert_wiphy(wiphy); 5128 5129 switch (roc->state) { 5130 case RTW89_ROC_IDLE: 5131 rtw89_enter_ips_by_hwflags(rtwdev); 5132 break; 5133 case RTW89_ROC_MGMT: 5134 case RTW89_ROC_NORMAL: 5135 rtw89_roc_end(rtwdev, rtwvif); 5136 break; 5137 default: 5138 break; 5139 } 5140 } 5141 5142 static enum rtw89_tfc_lv rtw89_get_traffic_level(struct rtw89_dev *rtwdev, 5143 u32 throughput, u64 cnt, 5144 enum rtw89_tfc_interval interval) 5145 { 5146 u64 cnt_level; 5147 5148 switch (interval) { 5149 default: 5150 case RTW89_TFC_INTERVAL_100MS: 5151 cnt_level = 5; 5152 break; 5153 case RTW89_TFC_INTERVAL_2SEC: 5154 cnt_level = 100; 5155 break; 5156 } 5157 5158 if (cnt < cnt_level) 5159 return RTW89_TFC_IDLE; 5160 if (throughput > 50) 5161 return RTW89_TFC_HIGH; 5162 if (throughput > 10) 5163 return RTW89_TFC_MID; 5164 if (throughput > 2) 5165 return RTW89_TFC_LOW; 5166 return RTW89_TFC_ULTRA_LOW; 5167 } 5168 5169 static void rtw89_calc_vif_active_histogram(struct rtw89_dev *rtwdev, 5170 struct rtw89_traffic_stats *stats, 5171 enum rtw89_tfc_interval interval) 5172 { 5173 struct rtw89_vif *rtwvif; 5174 5175 stats->udp_ratio = stats->tx_cnt ? 5176 DIV_ROUND_DOWN_ULL(stats->udp * 100, stats->tx_cnt) : 0; 5177 stats->active_histogram <<= 1; 5178 5179 switch (interval) { 5180 case RTW89_TFC_INTERVAL_2SEC: 5181 rtwvif = container_of(stats, struct rtw89_vif, stats); 5182 5183 if (stats->tcp >= RTW89_TCP_TH && stats->tx_cnt >= stats->rx_cnt) 5184 stats->active_histogram |= BIT(0); 5185 5186 if (stats->active_histogram & RTW89_RECENT_ACTIVE_HIST) 5187 rtwvif->burst_active = true; 5188 else 5189 rtwvif->burst_active = false; 5190 5191 break; 5192 case RTW89_TFC_INTERVAL_100MS: 5193 if (stats->udp_ratio >= RTW89_UDP_RATIO_TH) 5194 stats->active_histogram |= BIT(0); 5195 break; 5196 } 5197 5198 stats->tcp = 0; 5199 stats->udp = 0; 5200 } 5201 5202 static bool rtw89_traffic_stats_calc(struct rtw89_dev *rtwdev, 5203 struct rtw89_traffic_stats *stats, 5204 enum rtw89_tfc_interval interval, bool by_vif) 5205 { 5206 enum rtw89_tfc_lv tx_tfc_lv = stats->tx_tfc_lv; 5207 enum rtw89_tfc_lv rx_tfc_lv = stats->rx_tfc_lv; 5208 5209 stats->tx_throughput_raw = rtw89_bytes_to_mbps(stats->tx_unicast, interval); 5210 stats->rx_throughput_raw = rtw89_bytes_to_mbps(stats->rx_unicast, interval); 5211 5212 ewma_tp_add(&stats->tx_ewma_tp, stats->tx_throughput_raw); 5213 ewma_tp_add(&stats->rx_ewma_tp, stats->rx_throughput_raw); 5214 5215 stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp); 5216 stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp); 5217 stats->tx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->tx_throughput, 5218 stats->tx_cnt, interval); 5219 stats->rx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->rx_throughput, 5220 stats->rx_cnt, interval); 5221 stats->tx_avg_len = stats->tx_cnt ? 5222 DIV_ROUND_DOWN_ULL(stats->tx_unicast, stats->tx_cnt) : 0; 5223 stats->rx_avg_len = stats->rx_cnt ? 5224 DIV_ROUND_DOWN_ULL(stats->rx_unicast, stats->rx_cnt) : 0; 5225 5226 if (by_vif) 5227 rtw89_calc_vif_active_histogram(rtwdev, stats, interval); 5228 5229 stats->tx_unicast = 0; 5230 stats->rx_unicast = 0; 5231 stats->tx_cnt = 0; 5232 stats->rx_cnt = 0; 5233 stats->rx_tf_periodic = stats->rx_tf_acc; 5234 stats->rx_tf_acc = 0; 5235 5236 if (tx_tfc_lv != stats->tx_tfc_lv || rx_tfc_lv != stats->rx_tfc_lv) 5237 return true; 5238 5239 return false; 5240 } 5241 5242 static bool rtw89_traffic_stats_track(struct rtw89_dev *rtwdev) 5243 { 5244 struct rtw89_vif_link *rtwvif_link; 5245 struct rtw89_vif *rtwvif; 5246 unsigned int link_id; 5247 bool tfc_changed; 5248 5249 tfc_changed = rtw89_traffic_stats_calc(rtwdev, &rtwdev->stats, 5250 RTW89_TFC_INTERVAL_2SEC, false); 5251 5252 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 5253 rtw89_traffic_stats_calc(rtwdev, &rtwvif->stats, 5254 RTW89_TFC_INTERVAL_2SEC, true); 5255 5256 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 5257 rtw89_fw_h2c_tp_offload(rtwdev, rtwvif_link); 5258 } 5259 5260 return tfc_changed; 5261 } 5262 5263 static void rtw89_enter_lps_track(struct rtw89_dev *rtwdev, 5264 enum rtw89_tfc_interval interval) 5265 { 5266 struct rtw89_hal *hal = &rtwdev->hal; 5267 struct ieee80211_vif *vif; 5268 struct rtw89_vif *rtwvif; 5269 5270 /* 5271 * If vcore level is set, temperature is high and voltage is low. As 5272 * entering power save must reset voltage to default, avoid power save 5273 * until vcore decreases to zero resulting from temperature becomes low. 5274 */ 5275 if (hal->thermal_prot_vlv) 5276 return; 5277 5278 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 5279 if (rtwvif->tdls_peer) 5280 continue; 5281 if (rtwvif->offchan) 5282 continue; 5283 5284 if (rtwvif->stats_ps.tx_tfc_lv >= RTW89_TFC_MID || 5285 rtwvif->stats_ps.rx_tfc_lv >= RTW89_TFC_MID) 5286 continue; 5287 5288 vif = rtwvif_to_vif(rtwvif); 5289 5290 if (!(vif->type == NL80211_IFTYPE_STATION || 5291 vif->type == NL80211_IFTYPE_P2P_CLIENT)) 5292 continue; 5293 5294 if (!rtw89_core_bcn_track_can_lps(rtwdev)) 5295 continue; 5296 5297 if (!rtw89_core_proto_stats_can_lps(rtwdev, rtwvif, interval)) 5298 continue; 5299 5300 rtw89_enter_lps(rtwdev, rtwvif, true); 5301 } 5302 } 5303 5304 static void rtw89_core_rfk_tssi_record(struct rtw89_dev *rtwdev) 5305 { 5306 const struct rtw89_chip_info *chip = rtwdev->chip; 5307 u8 path_num = min(chip->rf_path_num, RTW89_RFK_RECORD_PATH_NR); 5308 struct rtw89_rfk_wait_info *info = &rtwdev->rfk_wait; 5309 int i = info->record_tssi_idx; 5310 u32 base; 5311 u32 mask; 5312 int path; 5313 5314 if (chip->chip_gen == RTW89_CHIP_AX) 5315 return; 5316 5317 info->record_tssi_idx = (info->record_tssi_idx + 1) % 5318 RTW89_RFK_RECORD_HISTORY_NR; 5319 5320 if (chip->chip_id == RTL8922A) { 5321 base = 0x2ee10; 5322 mask = 0x7fc00; 5323 } else { 5324 base = 0x2f918; 5325 mask = 0x000001ff; 5326 } 5327 5328 for (path = 0; path < path_num; path++) { 5329 u32 addr = base + 0x100 * path; 5330 5331 info->tssi_code[i][path] = rtw89_read32_mask(rtwdev, addr, mask); 5332 } 5333 } 5334 5335 static void rtw89_core_rfk_track(struct rtw89_dev *rtwdev) 5336 { 5337 enum rtw89_entity_mode mode; 5338 5339 mode = rtw89_get_entity_mode(rtwdev); 5340 if (mode == RTW89_ENTITY_MODE_MCC) 5341 return; 5342 5343 rtw89_chip_rfk_track(rtwdev); 5344 5345 rtw89_core_rfk_tssi_record(rtwdev); 5346 } 5347 5348 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev, 5349 struct rtw89_vif_link *rtwvif_link, 5350 struct ieee80211_bss_conf *bss_conf) 5351 { 5352 enum rtw89_entity_mode mode = rtw89_get_entity_mode(rtwdev); 5353 5354 if (mode == RTW89_ENTITY_MODE_MCC) 5355 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_P2P_PS_CHANGE); 5356 else 5357 rtw89_process_p2p_ps(rtwdev, rtwvif_link, bss_conf); 5358 } 5359 5360 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 5361 struct rtw89_traffic_stats *stats) 5362 { 5363 stats->tx_unicast = 0; 5364 stats->rx_unicast = 0; 5365 stats->tx_cnt = 0; 5366 stats->rx_cnt = 0; 5367 ewma_tp_init(&stats->tx_ewma_tp); 5368 ewma_tp_init(&stats->rx_ewma_tp); 5369 } 5370 5371 #define RTW89_MLSR_GOTO_2GHZ_THRESHOLD -53 5372 #define RTW89_MLSR_EXIT_2GHZ_THRESHOLD -38 5373 static void rtw89_core_mlsr_link_decision(struct rtw89_dev *rtwdev, 5374 struct rtw89_vif *rtwvif) 5375 { 5376 unsigned int sel_link_id = IEEE80211_MLD_MAX_NUM_LINKS; 5377 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 5378 u8 decided_bands = BIT(RTW89_BAND_NUM) - 1; 5379 struct rtw89_vif_link *rtwvif_link; 5380 const struct rtw89_chan *chan; 5381 unsigned long usable_links; 5382 struct rtw89_bb_ctx *bb; 5383 unsigned int link_id; 5384 u8 rssi; 5385 5386 usable_links = ieee80211_vif_usable_links(vif); 5387 5388 rtwvif_link = rtw89_get_designated_link(rtwvif); 5389 if (unlikely(!rtwvif_link)) 5390 goto select; 5391 5392 bb = rtw89_get_bb_ctx(rtwdev, rtwvif_link->phy_idx); 5393 rssi = ewma_rssi_read(&bb->bcn_rssi); 5394 if (unlikely(!rssi)) 5395 return; 5396 5397 if (RTW89_RSSI_RAW_TO_DBM(rssi) >= RTW89_MLSR_EXIT_2GHZ_THRESHOLD) 5398 decided_bands = BIT(RTW89_BAND_5G) | BIT(RTW89_BAND_6G); 5399 else if (RTW89_RSSI_RAW_TO_DBM(rssi) <= RTW89_MLSR_GOTO_2GHZ_THRESHOLD) 5400 decided_bands = BIT(RTW89_BAND_2G); 5401 else 5402 return; 5403 5404 chan = rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx); 5405 if (decided_bands & BIT(chan->band_type)) 5406 return; 5407 5408 usable_links &= ~BIT(rtwvif_link->link_id); 5409 5410 select: 5411 rcu_read_lock(); 5412 5413 for_each_set_bit(link_id, &usable_links, IEEE80211_MLD_MAX_NUM_LINKS) { 5414 struct ieee80211_bss_conf *link_conf; 5415 struct ieee80211_channel *channel; 5416 enum rtw89_band band; 5417 5418 link_conf = rcu_dereference(vif->link_conf[link_id]); 5419 if (unlikely(!link_conf)) 5420 continue; 5421 5422 channel = link_conf->chanreq.oper.chan; 5423 if (unlikely(!channel)) 5424 continue; 5425 5426 band = rtw89_nl80211_to_hw_band(channel->band); 5427 if (decided_bands & BIT(band)) { 5428 sel_link_id = link_id; 5429 break; 5430 } 5431 } 5432 5433 rcu_read_unlock(); 5434 5435 if (sel_link_id == IEEE80211_MLD_MAX_NUM_LINKS) 5436 return; 5437 5438 rtw89_core_mlsr_switch(rtwdev, rtwvif, sel_link_id); 5439 } 5440 5441 static void rtw89_core_mlo_track(struct rtw89_dev *rtwdev) 5442 { 5443 struct rtw89_hal *hal = &rtwdev->hal; 5444 struct ieee80211_vif *vif; 5445 struct rtw89_vif *rtwvif; 5446 5447 if (hal->disabled_dm_bitmap & BIT(RTW89_DM_MLO)) 5448 return; 5449 5450 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 5451 vif = rtwvif_to_vif(rtwvif); 5452 if (!vif->cfg.assoc || !ieee80211_vif_is_mld(vif)) 5453 continue; 5454 5455 switch (rtwvif->mlo_mode) { 5456 case RTW89_MLO_MODE_MLSR: 5457 rtw89_core_mlsr_link_decision(rtwdev, rtwvif); 5458 break; 5459 default: 5460 break; 5461 } 5462 } 5463 } 5464 5465 static void rtw89_track_ps_work(struct wiphy *wiphy, struct wiphy_work *work) 5466 { 5467 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 5468 track_ps_work.work); 5469 struct rtw89_vif *rtwvif; 5470 5471 lockdep_assert_wiphy(wiphy); 5472 5473 if (test_bit(RTW89_FLAG_FORBIDDEN_TRACK_WORK, rtwdev->flags)) 5474 return; 5475 5476 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) 5477 return; 5478 5479 wiphy_delayed_work_queue(wiphy, &rtwdev->track_ps_work, 5480 RTW89_TRACK_PS_WORK_PERIOD); 5481 5482 rtw89_for_each_rtwvif(rtwdev, rtwvif) 5483 rtw89_traffic_stats_calc(rtwdev, &rtwvif->stats_ps, 5484 RTW89_TFC_INTERVAL_100MS, true); 5485 5486 if (rtwdev->scanning) 5487 return; 5488 5489 if (rtw89_chanctx_paused(rtwdev)) 5490 return; 5491 5492 if (rtwdev->lps_enabled && !rtwdev->btc.btc_ctrl_lps) 5493 rtw89_enter_lps_track(rtwdev, RTW89_TFC_INTERVAL_100MS); 5494 } 5495 5496 static void rtw89_track_work(struct wiphy *wiphy, struct wiphy_work *work) 5497 { 5498 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 5499 track_work.work); 5500 bool tfc_changed; 5501 5502 lockdep_assert_wiphy(wiphy); 5503 5504 if (test_bit(RTW89_FLAG_FORBIDDEN_TRACK_WORK, rtwdev->flags)) 5505 return; 5506 5507 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) 5508 return; 5509 5510 wiphy_delayed_work_queue(wiphy, &rtwdev->track_work, 5511 RTW89_TRACK_WORK_PERIOD); 5512 5513 tfc_changed = rtw89_traffic_stats_track(rtwdev); 5514 if (rtwdev->scanning) 5515 return; 5516 5517 if (rtw89_chanctx_paused(rtwdev)) 5518 return; 5519 5520 rtw89_leave_lps(rtwdev); 5521 5522 if (tfc_changed) { 5523 rtw89_hci_recalc_int_mit(rtwdev); 5524 rtw89_btc_ntfy_wl_sta(rtwdev); 5525 } 5526 rtw89_mac_bf_monitor_track(rtwdev); 5527 rtw89_core_bcn_track(rtwdev); 5528 rtw89_phy_stat_track(rtwdev); 5529 rtw89_phy_env_monitor_track(rtwdev); 5530 rtw89_phy_dig(rtwdev); 5531 rtw89_core_rfk_track(rtwdev); 5532 rtw89_phy_ra_update(rtwdev); 5533 rtw89_phy_cfo_track(rtwdev); 5534 rtw89_phy_tx_path_div_track(rtwdev); 5535 rtw89_phy_antdiv_track(rtwdev); 5536 rtw89_phy_ul_tb_ctrl_track(rtwdev); 5537 rtw89_phy_edcca_track(rtwdev); 5538 rtw89_sar_track(rtwdev); 5539 rtw89_chanctx_track(rtwdev); 5540 rtw89_core_rfkill_poll(rtwdev, false); 5541 rtw89_core_mlo_track(rtwdev); 5542 5543 if (rtwdev->lps_enabled && !rtwdev->btc.btc_ctrl_lps) 5544 rtw89_enter_lps_track(rtwdev, RTW89_TFC_INTERVAL_2SEC); 5545 } 5546 5547 void rtw89_core_dm_disable_cfg(struct rtw89_dev *rtwdev, u32 new) 5548 { 5549 struct rtw89_hal *hal = &rtwdev->hal; 5550 u32 old = hal->disabled_dm_bitmap; 5551 5552 if (new == old) 5553 return; 5554 5555 hal->disabled_dm_bitmap = new; 5556 5557 rtw89_debug(rtwdev, RTW89_DBG_STATE, "Disable DM: 0x%x -> 0x%x\n", old, new); 5558 } 5559 5560 void rtw89_core_dm_disable_set(struct rtw89_dev *rtwdev, enum rtw89_dm_type type) 5561 { 5562 struct rtw89_hal *hal = &rtwdev->hal; 5563 u32 cur = hal->disabled_dm_bitmap; 5564 5565 rtw89_core_dm_disable_cfg(rtwdev, cur | BIT(type)); 5566 } 5567 5568 void rtw89_core_dm_disable_clr(struct rtw89_dev *rtwdev, enum rtw89_dm_type type) 5569 { 5570 struct rtw89_hal *hal = &rtwdev->hal; 5571 u32 cur = hal->disabled_dm_bitmap; 5572 5573 rtw89_core_dm_disable_cfg(rtwdev, cur & ~BIT(type)); 5574 } 5575 5576 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size) 5577 { 5578 unsigned long bit; 5579 5580 bit = find_first_zero_bit(addr, size); 5581 if (bit < size) 5582 set_bit(bit, addr); 5583 5584 return bit; 5585 } 5586 5587 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit) 5588 { 5589 clear_bit(bit, addr); 5590 } 5591 5592 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits) 5593 { 5594 bitmap_zero(addr, nbits); 5595 } 5596 5597 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 5598 struct rtw89_sta *rtwsta, u8 tid, 5599 u8 *cam_idx) 5600 { 5601 const struct rtw89_chip_info *chip = rtwdev->chip; 5602 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 5603 struct rtw89_ba_cam_entry *entry = NULL, *tmp; 5604 u8 idx; 5605 int i; 5606 5607 lockdep_assert_wiphy(rtwdev->hw->wiphy); 5608 5609 idx = rtw89_core_acquire_bit_map(cam_info->ba_cam_map, chip->bacam_num); 5610 if (idx == chip->bacam_num) { 5611 /* allocate a static BA CAM to tid=0/5, so replace the existing 5612 * one if BA CAM is full. Hardware will process the original tid 5613 * automatically. 5614 */ 5615 if (tid != 0 && tid != 5) 5616 return -ENOSPC; 5617 5618 for_each_set_bit(i, cam_info->ba_cam_map, chip->bacam_num) { 5619 tmp = &cam_info->ba_cam_entry[i]; 5620 if (tmp->tid == 0 || tmp->tid == 5) 5621 continue; 5622 5623 idx = i; 5624 entry = tmp; 5625 list_del(&entry->list); 5626 break; 5627 } 5628 5629 if (!entry) 5630 return -ENOSPC; 5631 } else { 5632 entry = &cam_info->ba_cam_entry[idx]; 5633 } 5634 5635 entry->tid = tid; 5636 list_add_tail(&entry->list, &rtwsta->ba_cam_list); 5637 5638 *cam_idx = idx; 5639 5640 return 0; 5641 } 5642 5643 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 5644 struct rtw89_sta *rtwsta, u8 tid, 5645 u8 *cam_idx) 5646 { 5647 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 5648 struct rtw89_ba_cam_entry *entry = NULL, *tmp; 5649 u8 idx; 5650 5651 lockdep_assert_wiphy(rtwdev->hw->wiphy); 5652 5653 list_for_each_entry_safe(entry, tmp, &rtwsta->ba_cam_list, list) { 5654 if (entry->tid != tid) 5655 continue; 5656 5657 idx = entry - cam_info->ba_cam_entry; 5658 list_del(&entry->list); 5659 5660 rtw89_core_release_bit_map(cam_info->ba_cam_map, idx); 5661 *cam_idx = idx; 5662 return 0; 5663 } 5664 5665 return -ENOENT; 5666 } 5667 5668 #define RTW89_TYPE_MAPPING(_type) \ 5669 case NL80211_IFTYPE_ ## _type: \ 5670 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_ ## _type; \ 5671 break 5672 void rtw89_vif_type_mapping(struct rtw89_vif_link *rtwvif_link, bool assoc) 5673 { 5674 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 5675 const struct ieee80211_bss_conf *bss_conf; 5676 5677 switch (vif->type) { 5678 case NL80211_IFTYPE_STATION: 5679 if (vif->p2p) 5680 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_P2P_CLIENT; 5681 else 5682 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_STATION; 5683 break; 5684 case NL80211_IFTYPE_AP: 5685 if (vif->p2p) 5686 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_P2P_GO; 5687 else 5688 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_AP; 5689 break; 5690 RTW89_TYPE_MAPPING(P2P_DEVICE); 5691 RTW89_TYPE_MAPPING(ADHOC); 5692 RTW89_TYPE_MAPPING(MONITOR); 5693 RTW89_TYPE_MAPPING(MESH_POINT); 5694 default: 5695 WARN_ON(1); 5696 break; 5697 } 5698 5699 switch (vif->type) { 5700 case NL80211_IFTYPE_AP: 5701 case NL80211_IFTYPE_MESH_POINT: 5702 rtwvif_link->net_type = RTW89_NET_TYPE_AP_MODE; 5703 rtwvif_link->self_role = RTW89_SELF_ROLE_AP; 5704 break; 5705 case NL80211_IFTYPE_ADHOC: 5706 rtwvif_link->net_type = RTW89_NET_TYPE_AD_HOC; 5707 rtwvif_link->self_role = RTW89_SELF_ROLE_CLIENT; 5708 break; 5709 case NL80211_IFTYPE_STATION: 5710 if (assoc) { 5711 rtwvif_link->net_type = RTW89_NET_TYPE_INFRA; 5712 5713 rcu_read_lock(); 5714 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false); 5715 rtwvif_link->trigger = bss_conf->he_support; 5716 rcu_read_unlock(); 5717 } else { 5718 rtwvif_link->net_type = RTW89_NET_TYPE_NO_LINK; 5719 rtwvif_link->trigger = false; 5720 } 5721 rtwvif_link->self_role = RTW89_SELF_ROLE_CLIENT; 5722 rtwvif_link->addr_cam.sec_ent_mode = RTW89_ADDR_CAM_SEC_NORMAL; 5723 break; 5724 case NL80211_IFTYPE_P2P_DEVICE: 5725 rtwvif_link->net_type = RTW89_NET_TYPE_NO_LINK; 5726 rtwvif_link->self_role = RTW89_SELF_ROLE_CLIENT; 5727 break; 5728 case NL80211_IFTYPE_MONITOR: 5729 break; 5730 default: 5731 WARN_ON(1); 5732 break; 5733 } 5734 } 5735 5736 int rtw89_core_sta_link_add(struct rtw89_dev *rtwdev, 5737 struct rtw89_vif_link *rtwvif_link, 5738 struct rtw89_sta_link *rtwsta_link) 5739 { 5740 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 5741 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 5742 struct rtw89_hal *hal = &rtwdev->hal; 5743 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num; 5744 int i; 5745 int ret; 5746 5747 rtwsta_link->prev_rssi = 0; 5748 ewma_rssi_init(&rtwsta_link->avg_rssi); 5749 ewma_snr_init(&rtwsta_link->avg_snr); 5750 ewma_evm_init(&rtwsta_link->evm_1ss); 5751 for (i = 0; i < ant_num; i++) { 5752 ewma_rssi_init(&rtwsta_link->rssi[i]); 5753 ewma_evm_init(&rtwsta_link->evm_min[i]); 5754 ewma_evm_init(&rtwsta_link->evm_max[i]); 5755 } 5756 5757 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 5758 /* must do rtw89_reg_6ghz_recalc() before rfk channel */ 5759 ret = rtw89_reg_6ghz_recalc(rtwdev, rtwvif_link, true); 5760 if (ret) 5761 return ret; 5762 5763 rtw89_btc_ntfy_role_info(rtwdev, rtwvif_link, rtwsta_link, 5764 BTC_ROLE_MSTS_STA_CONN_START); 5765 rtw89_chip_rfk_channel(rtwdev, rtwvif_link); 5766 5767 if (vif->p2p) { 5768 rtw89_mac_get_tx_retry_limit(rtwdev, rtwsta_link, 5769 &rtwsta_link->tx_retry); 5770 rtw89_mac_set_tx_retry_limit(rtwdev, rtwsta_link, false, 60); 5771 } 5772 rtw89_phy_dig_suspend(rtwdev); 5773 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 5774 ret = rtw89_mac_set_macid_pause(rtwdev, rtwsta_link->mac_id, false); 5775 if (ret) { 5776 rtw89_warn(rtwdev, "failed to send h2c macid pause\n"); 5777 return ret; 5778 } 5779 5780 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif_link, rtwsta_link, 5781 RTW89_ROLE_CREATE); 5782 if (ret) { 5783 rtw89_warn(rtwdev, "failed to send h2c role info\n"); 5784 return ret; 5785 } 5786 5787 ret = rtw89_chip_h2c_default_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link); 5788 if (ret) 5789 return ret; 5790 5791 ret = rtw89_chip_h2c_default_dmac_tbl(rtwdev, rtwvif_link, rtwsta_link); 5792 if (ret) 5793 return ret; 5794 } 5795 5796 return 0; 5797 } 5798 5799 int rtw89_core_sta_link_disassoc(struct rtw89_dev *rtwdev, 5800 struct rtw89_vif_link *rtwvif_link, 5801 struct rtw89_sta_link *rtwsta_link) 5802 { 5803 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 5804 5805 rtw89_assoc_link_clr(rtwsta_link); 5806 5807 if (vif->type == NL80211_IFTYPE_STATION) { 5808 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, rtwvif_link, false); 5809 rtw89_core_bcn_track_reset(rtwdev); 5810 } 5811 5812 if (rtwvif_link->wifi_role == RTW89_WIFI_ROLE_P2P_CLIENT) 5813 rtw89_p2p_noa_once_deinit(rtwvif_link); 5814 5815 return 0; 5816 } 5817 5818 int rtw89_core_sta_link_disconnect(struct rtw89_dev *rtwdev, 5819 struct rtw89_vif_link *rtwvif_link, 5820 struct rtw89_sta_link *rtwsta_link) 5821 { 5822 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 5823 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 5824 int ret; 5825 5826 rtw89_mac_bf_monitor_calc(rtwdev, rtwsta_link, true); 5827 rtw89_mac_bf_disassoc(rtwdev, rtwvif_link, rtwsta_link); 5828 5829 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) 5830 rtw89_cam_deinit_addr_cam(rtwdev, &rtwsta_link->addr_cam); 5831 if (sta->tdls) 5832 rtw89_cam_deinit_bssid_cam(rtwdev, &rtwsta_link->bssid_cam); 5833 5834 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 5835 rtw89_vif_type_mapping(rtwvif_link, false); 5836 rtw89_fw_release_general_pkt_list_vif(rtwdev, rtwvif_link, true); 5837 } 5838 5839 ret = rtw89_chip_h2c_assoc_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link); 5840 if (ret) { 5841 rtw89_warn(rtwdev, "failed to send h2c cmac table\n"); 5842 return ret; 5843 } 5844 5845 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif_link, rtwsta_link, true); 5846 if (ret) { 5847 rtw89_warn(rtwdev, "failed to send h2c join info\n"); 5848 return ret; 5849 } 5850 5851 /* update cam aid mac_id net_type */ 5852 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, rtwsta_link, NULL, 5853 RTW89_ROLE_CON_DISCONN); 5854 if (ret) { 5855 rtw89_warn(rtwdev, "failed to send h2c cam\n"); 5856 return ret; 5857 } 5858 5859 return ret; 5860 } 5861 5862 static bool rtw89_sta_link_can_er(struct rtw89_dev *rtwdev, 5863 struct ieee80211_bss_conf *bss_conf, 5864 struct ieee80211_link_sta *link_sta) 5865 { 5866 if (!bss_conf->he_support || 5867 bss_conf->he_oper.params & IEEE80211_HE_OPERATION_ER_SU_DISABLE) 5868 return false; 5869 5870 if (rtwdev->chip->chip_id == RTL8852C && 5871 rtw89_sta_link_has_su_mu_4xhe08(link_sta) && 5872 !rtw89_sta_link_has_er_su_4xhe08(link_sta)) 5873 return false; 5874 5875 return true; 5876 } 5877 5878 int rtw89_core_sta_link_assoc(struct rtw89_dev *rtwdev, 5879 struct rtw89_vif_link *rtwvif_link, 5880 struct rtw89_sta_link *rtwsta_link) 5881 { 5882 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 5883 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 5884 struct rtw89_bssid_cam_entry *bssid_cam = rtw89_get_bssid_cam_of(rtwvif_link, 5885 rtwsta_link); 5886 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 5887 rtwvif_link->chanctx_idx); 5888 struct rtw89_bb_ctx *bb = rtw89_get_bb_ctx(rtwdev, rtwvif_link->phy_idx); 5889 struct ieee80211_link_sta *link_sta; 5890 int ret; 5891 5892 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 5893 if (sta->tdls) { 5894 rcu_read_lock(); 5895 5896 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 5897 ret = rtw89_cam_init_bssid_cam(rtwdev, rtwvif_link, bssid_cam, 5898 link_sta->addr); 5899 if (ret) { 5900 rtw89_warn(rtwdev, "failed to send h2c init bssid cam for TDLS\n"); 5901 rcu_read_unlock(); 5902 return ret; 5903 } 5904 5905 rcu_read_unlock(); 5906 } 5907 5908 ret = rtw89_cam_init_addr_cam(rtwdev, &rtwsta_link->addr_cam, bssid_cam); 5909 if (ret) { 5910 rtw89_warn(rtwdev, "failed to send h2c init addr cam\n"); 5911 return ret; 5912 } 5913 } 5914 5915 ret = rtw89_chip_h2c_assoc_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link); 5916 if (ret) { 5917 rtw89_warn(rtwdev, "failed to send h2c cmac table\n"); 5918 return ret; 5919 } 5920 5921 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif_link, rtwsta_link, false); 5922 if (ret) { 5923 rtw89_warn(rtwdev, "failed to send h2c join info\n"); 5924 return ret; 5925 } 5926 5927 /* update cam aid mac_id net_type */ 5928 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, rtwsta_link, NULL, 5929 RTW89_ROLE_CON_DISCONN); 5930 if (ret) { 5931 rtw89_warn(rtwdev, "failed to send h2c cam\n"); 5932 return ret; 5933 } 5934 5935 rtw89_phy_ra_assoc(rtwdev, rtwsta_link); 5936 rtw89_mac_bf_assoc(rtwdev, rtwvif_link, rtwsta_link); 5937 rtw89_mac_bf_monitor_calc(rtwdev, rtwsta_link, false); 5938 5939 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 5940 struct ieee80211_bss_conf *bss_conf; 5941 u8 link_mode = 0; 5942 5943 rcu_read_lock(); 5944 5945 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 5946 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 5947 rtwsta_link->er_cap = rtw89_sta_link_can_er(rtwdev, bss_conf, link_sta); 5948 5949 if (link_sta->he_cap.has_he || link_sta->eht_cap.has_eht) 5950 link_mode = 2; 5951 else if (link_sta->vht_cap.vht_supported) 5952 link_mode = 1; 5953 bb->path_diff.link_mode = link_mode; 5954 5955 rcu_read_unlock(); 5956 5957 rtw89_btc_ntfy_role_info(rtwdev, rtwvif_link, rtwsta_link, 5958 BTC_ROLE_MSTS_STA_CONN_END); 5959 rtw89_core_get_no_ul_ofdma_htc(rtwdev, &rtwsta_link->htc_template, chan); 5960 rtw89_phy_ul_tb_assoc(rtwdev, rtwvif_link); 5961 rtw89_core_bcn_track_assoc(rtwdev, rtwvif_link); 5962 5963 ret = rtw89_fw_h2c_general_pkt(rtwdev, rtwvif_link, rtwsta_link->mac_id); 5964 if (ret) { 5965 rtw89_warn(rtwdev, "failed to send h2c general packet\n"); 5966 return ret; 5967 } 5968 5969 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, rtwvif_link, true); 5970 5971 if (vif->p2p) 5972 rtw89_mac_set_tx_retry_limit(rtwdev, rtwsta_link, false, 5973 rtwsta_link->tx_retry); 5974 rtw89_phy_dig_resume(rtwdev, false); 5975 } 5976 5977 rtw89_assoc_link_set(rtwsta_link); 5978 return ret; 5979 } 5980 5981 int rtw89_core_sta_link_remove(struct rtw89_dev *rtwdev, 5982 struct rtw89_vif_link *rtwvif_link, 5983 struct rtw89_sta_link *rtwsta_link) 5984 { 5985 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 5986 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 5987 int ret; 5988 5989 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 5990 rtw89_reg_6ghz_recalc(rtwdev, rtwvif_link, false); 5991 rtw89_btc_ntfy_role_info(rtwdev, rtwvif_link, rtwsta_link, 5992 BTC_ROLE_MSTS_STA_DIS_CONN); 5993 5994 if (vif->p2p) 5995 rtw89_mac_set_tx_retry_limit(rtwdev, rtwsta_link, false, 5996 rtwsta_link->tx_retry); 5997 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 5998 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif_link, rtwsta_link, 5999 RTW89_ROLE_REMOVE); 6000 if (ret) { 6001 rtw89_warn(rtwdev, "failed to send h2c role info\n"); 6002 return ret; 6003 } 6004 } 6005 6006 return 0; 6007 } 6008 6009 static void _rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 6010 struct ieee80211_sta *sta, 6011 struct cfg80211_tid_cfg *tid_conf) 6012 { 6013 struct ieee80211_txq *txq; 6014 struct rtw89_txq *rtwtxq; 6015 u32 mask = tid_conf->mask; 6016 u8 tids = tid_conf->tids; 6017 int tids_nbit = BITS_PER_BYTE; 6018 int i; 6019 6020 for (i = 0; i < tids_nbit; i++, tids >>= 1) { 6021 if (!tids) 6022 break; 6023 6024 if (!(tids & BIT(0))) 6025 continue; 6026 6027 txq = sta->txq[i]; 6028 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 6029 6030 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL)) { 6031 if (tid_conf->ampdu == NL80211_TID_CONFIG_ENABLE) { 6032 clear_bit(RTW89_TXQ_F_FORBID_BA, rtwtxq->flags); 6033 } else { 6034 if (test_bit(RTW89_TXQ_F_AMPDU, rtwtxq->flags)) 6035 ieee80211_stop_tx_ba_session(sta, txq->tid); 6036 spin_lock_bh(&rtwdev->ba_lock); 6037 list_del_init(&rtwtxq->list); 6038 set_bit(RTW89_TXQ_F_FORBID_BA, rtwtxq->flags); 6039 spin_unlock_bh(&rtwdev->ba_lock); 6040 } 6041 } 6042 6043 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL) && tids == 0xff) { 6044 if (tid_conf->amsdu == NL80211_TID_CONFIG_ENABLE) 6045 sta->max_amsdu_subframes = 0; 6046 else 6047 sta->max_amsdu_subframes = 1; 6048 } 6049 } 6050 } 6051 6052 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 6053 struct ieee80211_sta *sta, 6054 struct cfg80211_tid_config *tid_config) 6055 { 6056 int i; 6057 6058 for (i = 0; i < tid_config->n_tid_conf; i++) 6059 _rtw89_core_set_tid_config(rtwdev, sta, 6060 &tid_config->tid_conf[i]); 6061 } 6062 6063 static void rtw89_init_ht_cap(struct rtw89_dev *rtwdev, 6064 struct ieee80211_sta_ht_cap *ht_cap) 6065 { 6066 static const __le16 highest[RF_PATH_MAX] = { 6067 cpu_to_le16(150), cpu_to_le16(300), cpu_to_le16(450), cpu_to_le16(600), 6068 }; 6069 struct rtw89_hal *hal = &rtwdev->hal; 6070 u8 nss = hal->rx_nss; 6071 int i; 6072 6073 ht_cap->ht_supported = true; 6074 ht_cap->cap = 0; 6075 ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 | 6076 IEEE80211_HT_CAP_MAX_AMSDU | 6077 IEEE80211_HT_CAP_TX_STBC | 6078 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); 6079 ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING; 6080 ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 6081 IEEE80211_HT_CAP_DSSSCCK40 | 6082 IEEE80211_HT_CAP_SGI_40; 6083 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 6084 ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_NONE; 6085 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 6086 for (i = 0; i < nss; i++) 6087 ht_cap->mcs.rx_mask[i] = 0xFF; 6088 ht_cap->mcs.rx_mask[4] = 0x01; 6089 ht_cap->mcs.rx_highest = highest[nss - 1]; 6090 } 6091 6092 static void rtw89_init_vht_cap(struct rtw89_dev *rtwdev, 6093 struct ieee80211_sta_vht_cap *vht_cap) 6094 { 6095 static const __le16 highest_bw80[RF_PATH_MAX] = { 6096 cpu_to_le16(433), cpu_to_le16(867), cpu_to_le16(1300), cpu_to_le16(1733), 6097 }; 6098 static const __le16 highest_bw160[RF_PATH_MAX] = { 6099 cpu_to_le16(867), cpu_to_le16(1733), cpu_to_le16(2600), cpu_to_le16(3467), 6100 }; 6101 const struct rtw89_chip_info *chip = rtwdev->chip; 6102 const __le16 *highest = chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160) ? 6103 highest_bw160 : highest_bw80; 6104 struct rtw89_hal *hal = &rtwdev->hal; 6105 u16 tx_mcs_map = 0, rx_mcs_map = 0; 6106 u8 sts_cap = 3; 6107 int i; 6108 6109 for (i = 0; i < 8; i++) { 6110 if (i < hal->tx_nss) 6111 tx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2); 6112 else 6113 tx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2); 6114 if (i < hal->rx_nss) 6115 rx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2); 6116 else 6117 rx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2); 6118 } 6119 6120 vht_cap->vht_supported = true; 6121 vht_cap->cap = chip->max_vht_mpdu_cap | 6122 IEEE80211_VHT_CAP_SHORT_GI_80 | 6123 IEEE80211_VHT_CAP_RXSTBC_1 | 6124 IEEE80211_VHT_CAP_HTC_VHT | 6125 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK | 6126 0; 6127 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC; 6128 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; 6129 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 6130 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE; 6131 vht_cap->cap |= sts_cap << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT; 6132 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 6133 vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ | 6134 IEEE80211_VHT_CAP_SHORT_GI_160; 6135 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(rx_mcs_map); 6136 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(tx_mcs_map); 6137 vht_cap->vht_mcs.rx_highest = highest[hal->rx_nss - 1]; 6138 vht_cap->vht_mcs.tx_highest = highest[hal->tx_nss - 1]; 6139 6140 if (ieee80211_hw_check(rtwdev->hw, SUPPORTS_VHT_EXT_NSS_BW)) 6141 vht_cap->vht_mcs.tx_highest |= 6142 cpu_to_le16(IEEE80211_VHT_EXT_NSS_BW_CAPABLE); 6143 } 6144 6145 static void rtw89_init_he_cap(struct rtw89_dev *rtwdev, 6146 enum nl80211_band band, 6147 enum nl80211_iftype iftype, 6148 struct ieee80211_sband_iftype_data *iftype_data) 6149 { 6150 const struct rtw89_chip_info *chip = rtwdev->chip; 6151 struct rtw89_hal *hal = &rtwdev->hal; 6152 bool no_ng16 = (chip->chip_id == RTL8852A && hal->cv == CHIP_CBV) || 6153 (chip->chip_id == RTL8852B && hal->cv == CHIP_CAV); 6154 struct ieee80211_sta_he_cap *he_cap; 6155 int nss = hal->rx_nss; 6156 u8 *mac_cap_info; 6157 u8 *phy_cap_info; 6158 u16 mcs_map = 0; 6159 int i; 6160 6161 for (i = 0; i < 8; i++) { 6162 if (i < nss) 6163 mcs_map |= IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2); 6164 else 6165 mcs_map |= IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2); 6166 } 6167 6168 he_cap = &iftype_data->he_cap; 6169 mac_cap_info = he_cap->he_cap_elem.mac_cap_info; 6170 phy_cap_info = he_cap->he_cap_elem.phy_cap_info; 6171 6172 he_cap->has_he = true; 6173 mac_cap_info[0] = IEEE80211_HE_MAC_CAP0_HTC_HE; 6174 if (iftype == NL80211_IFTYPE_STATION) 6175 mac_cap_info[1] = IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US; 6176 mac_cap_info[2] = IEEE80211_HE_MAC_CAP2_ALL_ACK | 6177 IEEE80211_HE_MAC_CAP2_BSR; 6178 mac_cap_info[3] = IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_2; 6179 if (iftype == NL80211_IFTYPE_AP) 6180 mac_cap_info[3] |= IEEE80211_HE_MAC_CAP3_OMI_CONTROL; 6181 mac_cap_info[4] = IEEE80211_HE_MAC_CAP4_OPS | 6182 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU; 6183 if (iftype == NL80211_IFTYPE_STATION) 6184 mac_cap_info[5] = IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX; 6185 if (band == NL80211_BAND_2GHZ) { 6186 phy_cap_info[0] = 6187 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G; 6188 } else { 6189 phy_cap_info[0] = 6190 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G; 6191 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 6192 phy_cap_info[0] |= IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; 6193 } 6194 phy_cap_info[1] = IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 6195 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD | 6196 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US; 6197 phy_cap_info[2] = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US | 6198 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ | 6199 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ | 6200 IEEE80211_HE_PHY_CAP2_DOPPLER_TX; 6201 phy_cap_info[3] = IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM; 6202 if (iftype == NL80211_IFTYPE_STATION) 6203 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_16_QAM | 6204 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_2; 6205 if (iftype == NL80211_IFTYPE_AP) 6206 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_RX_PARTIAL_BW_SU_IN_20MHZ_MU; 6207 phy_cap_info[4] = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | 6208 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4; 6209 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 6210 phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4; 6211 phy_cap_info[5] = no_ng16 ? 0 : 6212 IEEE80211_HE_PHY_CAP5_NG16_SU_FEEDBACK | 6213 IEEE80211_HE_PHY_CAP5_NG16_MU_FEEDBACK; 6214 phy_cap_info[6] = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU | 6215 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU | 6216 IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 6217 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE; 6218 phy_cap_info[7] = IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP | 6219 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI | 6220 IEEE80211_HE_PHY_CAP7_MAX_NC_1; 6221 phy_cap_info[8] = IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI | 6222 IEEE80211_HE_PHY_CAP8_HE_ER_SU_1XLTF_AND_08_US_GI | 6223 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_996; 6224 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 6225 phy_cap_info[8] |= IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 6226 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU; 6227 phy_cap_info[9] = IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM | 6228 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU | 6229 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 6230 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB | 6231 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US, 6232 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK); 6233 if (iftype == NL80211_IFTYPE_STATION) 6234 phy_cap_info[9] |= IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU; 6235 he_cap->he_mcs_nss_supp.rx_mcs_80 = cpu_to_le16(mcs_map); 6236 he_cap->he_mcs_nss_supp.tx_mcs_80 = cpu_to_le16(mcs_map); 6237 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) { 6238 he_cap->he_mcs_nss_supp.rx_mcs_160 = cpu_to_le16(mcs_map); 6239 he_cap->he_mcs_nss_supp.tx_mcs_160 = cpu_to_le16(mcs_map); 6240 } 6241 6242 if (band == NL80211_BAND_6GHZ) { 6243 __le16 capa; 6244 6245 capa = le16_encode_bits(IEEE80211_HT_MPDU_DENSITY_NONE, 6246 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) | 6247 le16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K, 6248 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) | 6249 le16_encode_bits(chip->max_vht_mpdu_cap, 6250 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN); 6251 iftype_data->he_6ghz_capa.capa = capa; 6252 } 6253 } 6254 6255 static void rtw89_init_eht_cap(struct rtw89_dev *rtwdev, 6256 enum nl80211_band band, 6257 enum nl80211_iftype iftype, 6258 struct ieee80211_sband_iftype_data *iftype_data) 6259 { 6260 const struct rtw89_chip_info *chip = rtwdev->chip; 6261 struct ieee80211_eht_cap_elem_fixed *eht_cap_elem; 6262 struct ieee80211_eht_mcs_nss_supp *eht_nss; 6263 struct ieee80211_sta_eht_cap *eht_cap; 6264 struct rtw89_hal *hal = &rtwdev->hal; 6265 bool support_mcs_12_13 = true; 6266 bool support_320mhz = false; 6267 u8 val, val_mcs13; 6268 int sts = 8; 6269 6270 if (chip->chip_gen == RTW89_CHIP_AX || hal->no_eht) 6271 return; 6272 6273 if (hal->no_mcs_12_13) 6274 support_mcs_12_13 = false; 6275 6276 if (band == NL80211_BAND_6GHZ && 6277 chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_320)) 6278 support_320mhz = true; 6279 6280 eht_cap = &iftype_data->eht_cap; 6281 eht_cap_elem = &eht_cap->eht_cap_elem; 6282 eht_nss = &eht_cap->eht_mcs_nss_supp; 6283 6284 eht_cap->has_eht = true; 6285 6286 eht_cap_elem->mac_cap_info[0] = 6287 u8_encode_bits(chip->max_eht_mpdu_cap, 6288 IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_MASK); 6289 eht_cap_elem->mac_cap_info[1] = 0; 6290 6291 eht_cap_elem->phy_cap_info[0] = 6292 IEEE80211_EHT_PHY_CAP0_NDP_4_EHT_LFT_32_GI | 6293 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMEE; 6294 if (support_320mhz) 6295 eht_cap_elem->phy_cap_info[0] |= 6296 IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ; 6297 6298 eht_cap_elem->phy_cap_info[0] |= 6299 u8_encode_bits(u8_get_bits(sts - 1, BIT(0)), 6300 IEEE80211_EHT_PHY_CAP0_BEAMFORMEE_SS_80MHZ_MASK); 6301 eht_cap_elem->phy_cap_info[1] = 6302 u8_encode_bits(u8_get_bits(sts - 1, GENMASK(2, 1)), 6303 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_80MHZ_MASK) | 6304 u8_encode_bits(sts - 1, 6305 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_160MHZ_MASK); 6306 if (support_320mhz) 6307 eht_cap_elem->phy_cap_info[1] |= 6308 u8_encode_bits(sts - 1, 6309 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_320MHZ_MASK); 6310 6311 eht_cap_elem->phy_cap_info[2] = 0; 6312 6313 eht_cap_elem->phy_cap_info[3] = 6314 IEEE80211_EHT_PHY_CAP3_CODEBOOK_4_2_SU_FDBK | 6315 IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK | 6316 IEEE80211_EHT_PHY_CAP3_TRIG_SU_BF_FDBK | 6317 IEEE80211_EHT_PHY_CAP3_TRIG_MU_BF_PART_BW_FDBK; 6318 6319 eht_cap_elem->phy_cap_info[4] = 6320 IEEE80211_EHT_PHY_CAP4_POWER_BOOST_FACT_SUPP | 6321 u8_encode_bits(1, IEEE80211_EHT_PHY_CAP4_MAX_NC_MASK); 6322 6323 eht_cap_elem->phy_cap_info[5] = 6324 u8_encode_bits(IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_20US, 6325 IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_MASK); 6326 6327 eht_cap_elem->phy_cap_info[6] = 0; 6328 eht_cap_elem->phy_cap_info[7] = 0; 6329 eht_cap_elem->phy_cap_info[8] = 0; 6330 6331 val = u8_encode_bits(hal->rx_nss, IEEE80211_EHT_MCS_NSS_RX) | 6332 u8_encode_bits(hal->tx_nss, IEEE80211_EHT_MCS_NSS_TX); 6333 val_mcs13 = support_mcs_12_13 ? val : 0; 6334 6335 eht_nss->bw._80.rx_tx_mcs9_max_nss = val; 6336 eht_nss->bw._80.rx_tx_mcs11_max_nss = val; 6337 eht_nss->bw._80.rx_tx_mcs13_max_nss = val_mcs13; 6338 eht_nss->bw._160.rx_tx_mcs9_max_nss = val; 6339 eht_nss->bw._160.rx_tx_mcs11_max_nss = val; 6340 eht_nss->bw._160.rx_tx_mcs13_max_nss = val_mcs13; 6341 if (support_320mhz) { 6342 eht_nss->bw._320.rx_tx_mcs9_max_nss = val; 6343 eht_nss->bw._320.rx_tx_mcs11_max_nss = val; 6344 eht_nss->bw._320.rx_tx_mcs13_max_nss = val_mcs13; 6345 } 6346 } 6347 6348 #define RTW89_SBAND_IFTYPES_NR 2 6349 6350 static int rtw89_init_he_eht_cap(struct rtw89_dev *rtwdev, 6351 enum nl80211_band band, 6352 struct ieee80211_supported_band *sband) 6353 { 6354 struct ieee80211_sband_iftype_data *iftype_data; 6355 enum nl80211_iftype iftype; 6356 int idx = 0; 6357 6358 iftype_data = devm_kcalloc(rtwdev->dev, RTW89_SBAND_IFTYPES_NR, 6359 sizeof(*iftype_data), GFP_KERNEL); 6360 if (!iftype_data) 6361 return -ENOMEM; 6362 6363 for (iftype = 0; iftype < NUM_NL80211_IFTYPES; iftype++) { 6364 switch (iftype) { 6365 case NL80211_IFTYPE_STATION: 6366 case NL80211_IFTYPE_AP: 6367 break; 6368 default: 6369 continue; 6370 } 6371 6372 if (idx >= RTW89_SBAND_IFTYPES_NR) { 6373 rtw89_warn(rtwdev, "run out of iftype_data\n"); 6374 break; 6375 } 6376 6377 iftype_data[idx].types_mask = BIT(iftype); 6378 6379 rtw89_init_he_cap(rtwdev, band, iftype, &iftype_data[idx]); 6380 rtw89_init_eht_cap(rtwdev, band, iftype, &iftype_data[idx]); 6381 6382 idx++; 6383 } 6384 6385 _ieee80211_set_sband_iftype_data(sband, iftype_data, idx); 6386 return 0; 6387 } 6388 6389 static struct ieee80211_supported_band * 6390 rtw89_core_sband_dup(struct rtw89_dev *rtwdev, 6391 const struct ieee80211_supported_band *sband) 6392 { 6393 struct ieee80211_supported_band *dup; 6394 6395 dup = devm_kmemdup(rtwdev->dev, sband, sizeof(*sband), GFP_KERNEL); 6396 if (!dup) 6397 return NULL; 6398 6399 dup->channels = devm_kmemdup(rtwdev->dev, sband->channels, 6400 sizeof(*sband->channels) * sband->n_channels, 6401 GFP_KERNEL); 6402 if (!dup->channels) 6403 return NULL; 6404 6405 dup->bitrates = devm_kmemdup(rtwdev->dev, sband->bitrates, 6406 sizeof(*sband->bitrates) * sband->n_bitrates, 6407 GFP_KERNEL); 6408 if (!dup->bitrates) 6409 return NULL; 6410 6411 return dup; 6412 } 6413 6414 static int rtw89_core_set_supported_band(struct rtw89_dev *rtwdev) 6415 { 6416 struct ieee80211_hw *hw = rtwdev->hw; 6417 struct ieee80211_supported_band *sband; 6418 u8 support_bands = rtwdev->chip->support_bands; 6419 int ret; 6420 6421 if (test_bit(RTW89_QUIRK_DISABLE_2GHZ, rtwdev->quirks)) 6422 support_bands &= ~BIT(NL80211_BAND_2GHZ); 6423 6424 if (support_bands & BIT(NL80211_BAND_2GHZ)) { 6425 sband = rtw89_core_sband_dup(rtwdev, &rtw89_sband_2ghz); 6426 if (!sband) 6427 return -ENOMEM; 6428 rtw89_init_ht_cap(rtwdev, &sband->ht_cap); 6429 ret = rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_2GHZ, sband); 6430 if (ret) 6431 return ret; 6432 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband; 6433 } 6434 6435 if (support_bands & BIT(NL80211_BAND_5GHZ)) { 6436 sband = rtw89_core_sband_dup(rtwdev, &rtw89_sband_5ghz); 6437 if (!sband) 6438 return -ENOMEM; 6439 rtw89_init_ht_cap(rtwdev, &sband->ht_cap); 6440 rtw89_init_vht_cap(rtwdev, &sband->vht_cap); 6441 ret = rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_5GHZ, sband); 6442 if (ret) 6443 return ret; 6444 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband; 6445 } 6446 6447 if (support_bands & BIT(NL80211_BAND_6GHZ)) { 6448 sband = rtw89_core_sband_dup(rtwdev, &rtw89_sband_6ghz); 6449 if (!sband) 6450 return -ENOMEM; 6451 ret = rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_6GHZ, sband); 6452 if (ret) 6453 return ret; 6454 hw->wiphy->bands[NL80211_BAND_6GHZ] = sband; 6455 } 6456 6457 return 0; 6458 } 6459 6460 static void rtw89_core_ppdu_sts_init(struct rtw89_dev *rtwdev) 6461 { 6462 int i; 6463 6464 for (i = 0; i < RTW89_PHY_NUM; i++) 6465 skb_queue_head_init(&rtwdev->ppdu_sts.rx_queue[i]); 6466 for (i = 0; i < RTW89_PHY_NUM; i++) 6467 rtwdev->ppdu_sts.curr_rx_ppdu_cnt[i] = U8_MAX; 6468 } 6469 6470 void rtw89_core_update_beacon_work(struct wiphy *wiphy, struct wiphy_work *work) 6471 { 6472 struct rtw89_dev *rtwdev; 6473 struct rtw89_vif_link *rtwvif_link = container_of(work, struct rtw89_vif_link, 6474 update_beacon_work); 6475 6476 lockdep_assert_wiphy(wiphy); 6477 6478 if (rtwvif_link->net_type != RTW89_NET_TYPE_AP_MODE) 6479 return; 6480 6481 rtwdev = rtwvif_link->rtwvif->rtwdev; 6482 6483 rtw89_chip_h2c_update_beacon(rtwdev, rtwvif_link); 6484 } 6485 6486 void rtw89_core_csa_beacon_work(struct wiphy *wiphy, struct wiphy_work *work) 6487 { 6488 struct rtw89_vif_link *rtwvif_link = 6489 container_of(work, struct rtw89_vif_link, csa_beacon_work.work); 6490 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 6491 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 6492 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 6493 struct ieee80211_bss_conf *bss_conf; 6494 unsigned int delay; 6495 6496 lockdep_assert_wiphy(wiphy); 6497 6498 if (rtwvif_link->net_type != RTW89_NET_TYPE_AP_MODE) 6499 return; 6500 6501 rcu_read_lock(); 6502 6503 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 6504 if (!bss_conf->csa_active) { 6505 rcu_read_unlock(); 6506 return; 6507 } 6508 6509 delay = ieee80211_tu_to_usec(bss_conf->beacon_int); 6510 6511 rcu_read_unlock(); 6512 6513 if (!ieee80211_beacon_cntdwn_is_complete(vif, rtwvif_link->link_id)) { 6514 rtw89_chip_h2c_update_beacon(rtwdev, rtwvif_link); 6515 6516 wiphy_delayed_work_queue(wiphy, &rtwvif_link->csa_beacon_work, 6517 usecs_to_jiffies(delay)); 6518 } else { 6519 ieee80211_csa_finish(vif, rtwvif_link->link_id); 6520 } 6521 } 6522 6523 struct rtw89_wait_response * 6524 rtw89_wait_for_cond_prep(struct rtw89_wait_info *wait, unsigned int cond) 6525 { 6526 struct rtw89_wait_response *prep; 6527 unsigned int cur; 6528 6529 /* use -EPERM _iff_ telling eval side not to make any changes */ 6530 6531 cur = atomic_cmpxchg(&wait->cond, RTW89_WAIT_COND_IDLE, cond); 6532 if (cur != RTW89_WAIT_COND_IDLE) 6533 return ERR_PTR(-EPERM); 6534 6535 prep = kzalloc_obj(*prep); 6536 if (!prep) 6537 return ERR_PTR(-ENOMEM); 6538 6539 init_completion(&prep->completion); 6540 6541 rcu_assign_pointer(wait->resp, prep); 6542 6543 return prep; 6544 } 6545 6546 int rtw89_wait_for_cond_eval(struct rtw89_wait_info *wait, 6547 struct rtw89_wait_response *prep, int err) 6548 { 6549 unsigned long time_left; 6550 6551 if (IS_ERR(prep)) { 6552 err = err ?: PTR_ERR(prep); 6553 6554 /* special error case: no permission to reset anything */ 6555 if (PTR_ERR(prep) == -EPERM) 6556 return err; 6557 6558 goto reset; 6559 } 6560 6561 if (err) 6562 goto cleanup; 6563 6564 time_left = wait_for_completion_timeout(&prep->completion, 6565 RTW89_WAIT_FOR_COND_TIMEOUT); 6566 if (time_left == 0) { 6567 err = -ETIMEDOUT; 6568 goto cleanup; 6569 } 6570 6571 wait->data = prep->data; 6572 6573 cleanup: 6574 rcu_assign_pointer(wait->resp, NULL); 6575 kfree_rcu(prep, rcu_head); 6576 6577 reset: 6578 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 6579 6580 if (err) 6581 return err; 6582 6583 if (wait->data.err) 6584 return -EFAULT; 6585 6586 return 0; 6587 } 6588 6589 static void rtw89_complete_cond_resp(struct rtw89_wait_response *resp, 6590 const struct rtw89_completion_data *data) 6591 { 6592 resp->data = *data; 6593 complete(&resp->completion); 6594 } 6595 6596 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 6597 const struct rtw89_completion_data *data) 6598 { 6599 struct rtw89_wait_response *resp; 6600 unsigned int cur; 6601 6602 guard(rcu)(); 6603 6604 resp = rcu_dereference(wait->resp); 6605 if (!resp) 6606 return; 6607 6608 cur = atomic_cmpxchg(&wait->cond, cond, RTW89_WAIT_COND_IDLE); 6609 if (cur != cond) 6610 return; 6611 6612 rtw89_complete_cond_resp(resp, data); 6613 } 6614 6615 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, 6616 enum rtw89_btc_hmsg event, 6617 enum rtw89_phy_idx phy_idx) 6618 { 6619 u16 bt_slot_req[RTW89_PHY_NUM]; 6620 6621 switch (event) { 6622 case RTW89_BTC_HMSG_SET_BT_REQ_SLOT: 6623 bt_slot_req[phy_idx] = rtw89_coex_query_bt_req_len(rtwdev, phy_idx); 6624 rtw89_debug(rtwdev, RTW89_DBG_BTC, 6625 "coex updates PHY-%d BT req len to %d TU\n", 6626 phy_idx, bt_slot_req[phy_idx]); 6627 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_BT_SLOT_CHANGE); 6628 break; 6629 default: 6630 if (event < NUM_OF_RTW89_BTC_HMSG) 6631 rtw89_debug(rtwdev, RTW89_DBG_BTC, 6632 "unhandled BTC HMSG event: %d\n", event); 6633 else 6634 rtw89_warn(rtwdev, 6635 "unrecognized BTC HMSG event: %d\n", event); 6636 break; 6637 } 6638 } 6639 6640 void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks) 6641 { 6642 const struct dmi_system_id *match; 6643 enum rtw89_quirks quirk; 6644 6645 if (!quirks) 6646 return; 6647 6648 for (match = dmi_first_match(quirks); match; match = dmi_first_match(match + 1)) { 6649 quirk = (uintptr_t)match->driver_data; 6650 if (quirk >= NUM_OF_RTW89_QUIRKS) 6651 continue; 6652 6653 set_bit(quirk, rtwdev->quirks); 6654 } 6655 } 6656 EXPORT_SYMBOL(rtw89_check_quirks); 6657 6658 int rtw89_core_start(struct rtw89_dev *rtwdev) 6659 { 6660 bool no_bbmcu = !rtwdev->chip->bbmcu_nr; 6661 int ret; 6662 6663 ret = rtw89_mac_preinit(rtwdev); 6664 if (ret) { 6665 rtw89_err(rtwdev, "mac preinit fail, ret: %d\n", ret); 6666 return ret; 6667 } 6668 6669 if (no_bbmcu) 6670 rtw89_chip_bb_preinit(rtwdev); 6671 6672 rtw89_phy_init_bb_afe(rtwdev); 6673 6674 /* above do preinit before downloading firmware */ 6675 6676 ret = rtw89_mac_init(rtwdev); 6677 if (ret) { 6678 rtw89_err(rtwdev, "mac init fail, ret:%d\n", ret); 6679 return ret; 6680 } 6681 6682 rtw89_btc_ntfy_poweron(rtwdev); 6683 6684 /* efuse process */ 6685 6686 /* pre-config BB/RF, BB reset/RFC reset */ 6687 ret = rtw89_chip_reset_bb_rf(rtwdev); 6688 if (ret) 6689 return ret; 6690 6691 rtw89_phy_init_bb_reg(rtwdev); 6692 rtw89_chip_bb_postinit(rtwdev); 6693 rtw89_phy_init_rf_reg(rtwdev, false); 6694 6695 rtw89_btc_ntfy_init(rtwdev, BTC_MODE_NORMAL); 6696 6697 rtw89_phy_dm_init(rtwdev); 6698 6699 rtw89_mac_set_edcca_mode_bands(rtwdev, true); 6700 rtw89_mac_cfg_ppdu_status_bands(rtwdev, true); 6701 rtw89_mac_cfg_phy_rpt_bands(rtwdev, true); 6702 rtw89_mac_update_rts_threshold(rtwdev); 6703 6704 ret = rtw89_hci_start(rtwdev); 6705 if (ret) { 6706 rtw89_err(rtwdev, "failed to start hci\n"); 6707 return ret; 6708 } 6709 6710 wiphy_delayed_work_queue(rtwdev->hw->wiphy, &rtwdev->track_work, 6711 RTW89_TRACK_WORK_PERIOD); 6712 wiphy_delayed_work_queue(rtwdev->hw->wiphy, &rtwdev->track_ps_work, 6713 RTW89_TRACK_PS_WORK_PERIOD); 6714 6715 set_bit(RTW89_FLAG_RUNNING, rtwdev->flags); 6716 6717 rtw89_chip_rfk_init_late(rtwdev); 6718 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_ON); 6719 rtw89_fw_h2c_fw_log(rtwdev, rtwdev->fw.log.enable); 6720 rtw89_fw_h2c_init_ba_cam(rtwdev); 6721 rtw89_tas_fw_timer_enable(rtwdev, true); 6722 rtwdev->ps_hang_cnt = 0; 6723 6724 return 0; 6725 } 6726 6727 void rtw89_core_stop(struct rtw89_dev *rtwdev) 6728 { 6729 struct wiphy *wiphy = rtwdev->hw->wiphy; 6730 struct rtw89_btc *btc = &rtwdev->btc; 6731 6732 lockdep_assert_wiphy(wiphy); 6733 6734 /* Prvent to stop twice; enter_ips and ops_stop */ 6735 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) 6736 return; 6737 6738 rtw89_tas_fw_timer_enable(rtwdev, false); 6739 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_OFF); 6740 6741 clear_bit(RTW89_FLAG_RUNNING, rtwdev->flags); 6742 6743 wiphy_work_cancel(wiphy, &rtwdev->c2h_work); 6744 wiphy_work_cancel(wiphy, &rtwdev->cancel_6ghz_probe_work); 6745 wiphy_work_cancel(wiphy, &btc->eapol_notify_work); 6746 wiphy_work_cancel(wiphy, &btc->arp_notify_work); 6747 wiphy_work_cancel(wiphy, &btc->dhcp_notify_work); 6748 wiphy_work_cancel(wiphy, &btc->icmp_notify_work); 6749 cancel_delayed_work_sync(&rtwdev->txq_reinvoke_work); 6750 wiphy_delayed_work_cancel(wiphy, &rtwdev->tx_wait_work); 6751 wiphy_delayed_work_cancel(wiphy, &rtwdev->track_work); 6752 wiphy_delayed_work_cancel(wiphy, &rtwdev->track_ps_work); 6753 wiphy_delayed_work_cancel(wiphy, &rtwdev->chanctx_work); 6754 wiphy_delayed_work_cancel(wiphy, &rtwdev->coex_act1_work); 6755 wiphy_delayed_work_cancel(wiphy, &rtwdev->coex_bt_devinfo_work); 6756 wiphy_delayed_work_cancel(wiphy, &rtwdev->coex_rfk_chk_work); 6757 wiphy_delayed_work_cancel(wiphy, &rtwdev->cfo_track_work); 6758 wiphy_delayed_work_cancel(wiphy, &rtwdev->mcc_prepare_done_work); 6759 cancel_delayed_work_sync(&rtwdev->forbid_ba_work); 6760 wiphy_delayed_work_cancel(wiphy, &rtwdev->antdiv_work); 6761 6762 rtw89_btc_ntfy_poweroff(rtwdev); 6763 rtw89_hci_flush_queues(rtwdev, BIT(rtwdev->hw->queues) - 1, true); 6764 rtw89_mac_flush_txq(rtwdev, BIT(rtwdev->hw->queues) - 1, true); 6765 rtw89_hci_stop(rtwdev); 6766 rtw89_hci_deinit(rtwdev); 6767 rtw89_mac_pwr_off(rtwdev); 6768 rtw89_hci_reset(rtwdev); 6769 } 6770 6771 u8 rtw89_acquire_mac_id(struct rtw89_dev *rtwdev) 6772 { 6773 const struct rtw89_chip_info *chip = rtwdev->chip; 6774 u8 mac_id_num; 6775 u8 mac_id; 6776 6777 if (rtwdev->support_mlo) 6778 mac_id_num = chip->support_macid_num / chip->support_link_num; 6779 else 6780 mac_id_num = chip->support_macid_num; 6781 6782 mac_id = find_first_zero_bit(rtwdev->mac_id_map, mac_id_num); 6783 if (mac_id == mac_id_num) 6784 return RTW89_MAX_MAC_ID_NUM; 6785 6786 set_bit(mac_id, rtwdev->mac_id_map); 6787 return mac_id; 6788 } 6789 6790 void rtw89_release_mac_id(struct rtw89_dev *rtwdev, u8 mac_id) 6791 { 6792 clear_bit(mac_id, rtwdev->mac_id_map); 6793 } 6794 6795 void rtw89_init_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 6796 u8 mac_id, u8 port) 6797 { 6798 const struct rtw89_chip_info *chip = rtwdev->chip; 6799 u8 support_link_num = chip->support_link_num; 6800 u8 support_mld_num = 0; 6801 unsigned int link_id; 6802 u8 index; 6803 6804 bitmap_zero(rtwvif->links_inst_map, __RTW89_MLD_MAX_LINK_NUM); 6805 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) 6806 rtwvif->links[link_id] = NULL; 6807 6808 rtwvif->rtwdev = rtwdev; 6809 6810 if (rtwdev->support_mlo) { 6811 rtwvif->links_inst_valid_num = support_link_num; 6812 support_mld_num = chip->support_macid_num / support_link_num; 6813 } else { 6814 rtwvif->links_inst_valid_num = 1; 6815 } 6816 6817 for (index = 0; index < rtwvif->links_inst_valid_num; index++) { 6818 struct rtw89_vif_link *inst = &rtwvif->links_inst[index]; 6819 6820 inst->rtwvif = rtwvif; 6821 inst->mac_id = mac_id + index * support_mld_num; 6822 inst->mac_idx = RTW89_MAC_0 + index; 6823 inst->phy_idx = RTW89_PHY_0 + index; 6824 6825 /* multi-link use the same port id on different HW bands */ 6826 inst->port = port; 6827 } 6828 } 6829 6830 void rtw89_init_sta(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 6831 struct rtw89_sta *rtwsta, u8 mac_id) 6832 { 6833 const struct rtw89_chip_info *chip = rtwdev->chip; 6834 u8 support_link_num = chip->support_link_num; 6835 u8 support_mld_num = 0; 6836 unsigned int link_id; 6837 u8 index; 6838 6839 bitmap_zero(rtwsta->links_inst_map, __RTW89_MLD_MAX_LINK_NUM); 6840 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) 6841 rtwsta->links[link_id] = NULL; 6842 6843 rtwsta->rtwdev = rtwdev; 6844 rtwsta->rtwvif = rtwvif; 6845 6846 if (rtwdev->support_mlo) { 6847 rtwsta->links_inst_valid_num = support_link_num; 6848 support_mld_num = chip->support_macid_num / support_link_num; 6849 } else { 6850 rtwsta->links_inst_valid_num = 1; 6851 } 6852 6853 for (index = 0; index < rtwsta->links_inst_valid_num; index++) { 6854 struct rtw89_sta_link *inst = &rtwsta->links_inst[index]; 6855 6856 inst->rtwvif_link = &rtwvif->links_inst[index]; 6857 6858 inst->rtwsta = rtwsta; 6859 inst->mac_id = mac_id + index * support_mld_num; 6860 } 6861 } 6862 6863 struct rtw89_vif_link *rtw89_vif_set_link(struct rtw89_vif *rtwvif, 6864 unsigned int link_id) 6865 { 6866 struct rtw89_vif_link *rtwvif_link = rtwvif->links[link_id]; 6867 u8 index; 6868 int ret; 6869 6870 if (rtwvif_link) 6871 return rtwvif_link; 6872 6873 index = find_first_zero_bit(rtwvif->links_inst_map, 6874 rtwvif->links_inst_valid_num); 6875 if (index == rtwvif->links_inst_valid_num) { 6876 ret = -EBUSY; 6877 goto err; 6878 } 6879 6880 rtwvif_link = &rtwvif->links_inst[index]; 6881 rtwvif_link->link_id = link_id; 6882 6883 set_bit(index, rtwvif->links_inst_map); 6884 rtwvif->links[link_id] = rtwvif_link; 6885 list_add_tail(&rtwvif_link->dlink_schd, &rtwvif->dlink_pool); 6886 return rtwvif_link; 6887 6888 err: 6889 rtw89_err(rtwvif->rtwdev, "vif (link_id %u) failed to set link: %d\n", 6890 link_id, ret); 6891 return NULL; 6892 } 6893 6894 void rtw89_vif_unset_link(struct rtw89_vif *rtwvif, unsigned int link_id) 6895 { 6896 struct rtw89_vif_link **container = &rtwvif->links[link_id]; 6897 struct rtw89_vif_link *link = *container; 6898 u8 index; 6899 6900 if (!link) 6901 return; 6902 6903 index = rtw89_vif_link_inst_get_index(link); 6904 clear_bit(index, rtwvif->links_inst_map); 6905 *container = NULL; 6906 list_del(&link->dlink_schd); 6907 } 6908 6909 struct rtw89_sta_link *rtw89_sta_set_link(struct rtw89_sta *rtwsta, 6910 unsigned int link_id) 6911 { 6912 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 6913 struct rtw89_vif_link *rtwvif_link = rtwvif->links[link_id]; 6914 struct rtw89_sta_link *rtwsta_link = rtwsta->links[link_id]; 6915 u8 index; 6916 int ret; 6917 6918 if (rtwsta_link) 6919 return rtwsta_link; 6920 6921 if (!rtwvif_link) { 6922 ret = -ENOLINK; 6923 goto err; 6924 } 6925 6926 index = rtw89_vif_link_inst_get_index(rtwvif_link); 6927 if (test_bit(index, rtwsta->links_inst_map)) { 6928 ret = -EBUSY; 6929 goto err; 6930 } 6931 6932 rtwsta_link = &rtwsta->links_inst[index]; 6933 rtwsta_link->link_id = link_id; 6934 6935 set_bit(index, rtwsta->links_inst_map); 6936 rtwsta->links[link_id] = rtwsta_link; 6937 list_add_tail(&rtwsta_link->dlink_schd, &rtwsta->dlink_pool); 6938 return rtwsta_link; 6939 6940 err: 6941 rtw89_err(rtwsta->rtwdev, "sta (link_id %u) failed to set link: %d\n", 6942 link_id, ret); 6943 return NULL; 6944 } 6945 6946 void rtw89_sta_unset_link(struct rtw89_sta *rtwsta, unsigned int link_id) 6947 { 6948 struct rtw89_sta_link **container = &rtwsta->links[link_id]; 6949 struct rtw89_sta_link *link = *container; 6950 u8 index; 6951 6952 if (!link) 6953 return; 6954 6955 index = rtw89_sta_link_inst_get_index(link); 6956 clear_bit(index, rtwsta->links_inst_map); 6957 *container = NULL; 6958 list_del(&link->dlink_schd); 6959 } 6960 6961 int rtw89_core_init(struct rtw89_dev *rtwdev) 6962 { 6963 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6964 struct rtw89_btc *btc = &rtwdev->btc; 6965 u8 band; 6966 6967 rtwdev->io = rtw89_fw_cmd_ofld_alloc_and_get_io_ops(rtwdev); 6968 6969 bitmap_or(rtwdev->quirks, rtwdev->quirks, &rtwdev->chip->default_quirks, 6970 NUM_OF_RTW89_QUIRKS); 6971 6972 INIT_LIST_HEAD(&rtwdev->ba_list); 6973 INIT_LIST_HEAD(&rtwdev->forbid_ba_list); 6974 INIT_LIST_HEAD(&rtwdev->rtwvifs_list); 6975 INIT_LIST_HEAD(&rtwdev->early_h2c_list); 6976 for (band = NL80211_BAND_2GHZ; band < NUM_NL80211_BANDS; band++) { 6977 if (!(rtwdev->chip->support_bands & BIT(band))) 6978 continue; 6979 INIT_LIST_HEAD(&rtwdev->scan_info.pkt_list[band]); 6980 } 6981 INIT_LIST_HEAD(&rtwdev->scan_info.chan_list); 6982 INIT_LIST_HEAD(&rtwdev->tx_waits); 6983 INIT_LIST_HEAD(&rtwdev->fw.dup_data_list); 6984 INIT_WORK(&rtwdev->ba_work, rtw89_core_ba_work); 6985 INIT_WORK(&rtwdev->txq_work, rtw89_core_txq_work); 6986 INIT_DELAYED_WORK(&rtwdev->txq_reinvoke_work, rtw89_core_txq_reinvoke_work); 6987 wiphy_delayed_work_init(&rtwdev->track_work, rtw89_track_work); 6988 wiphy_delayed_work_init(&rtwdev->track_ps_work, rtw89_track_ps_work); 6989 wiphy_delayed_work_init(&rtwdev->chanctx_work, rtw89_chanctx_work); 6990 wiphy_delayed_work_init(&rtwdev->coex_act1_work, rtw89_coex_act1_work); 6991 wiphy_delayed_work_init(&rtwdev->coex_bt_devinfo_work, rtw89_coex_bt_devinfo_work); 6992 wiphy_delayed_work_init(&rtwdev->coex_rfk_chk_work, rtw89_coex_rfk_chk_work); 6993 wiphy_delayed_work_init(&rtwdev->cfo_track_work, rtw89_phy_cfo_track_work); 6994 wiphy_delayed_work_init(&rtwdev->mcc_prepare_done_work, rtw89_mcc_prepare_done_work); 6995 wiphy_delayed_work_init(&rtwdev->tx_wait_work, rtw89_tx_wait_work); 6996 INIT_DELAYED_WORK(&rtwdev->forbid_ba_work, rtw89_forbid_ba_work); 6997 wiphy_delayed_work_init(&rtwdev->antdiv_work, rtw89_phy_antdiv_work); 6998 rtwdev->txq_wq = alloc_workqueue("rtw89_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0); 6999 if (!rtwdev->txq_wq) 7000 return -ENOMEM; 7001 spin_lock_init(&rtwdev->ba_lock); 7002 spin_lock_init(&rtwdev->rpwm_lock); 7003 rtwdev->total_sta_assoc = 0; 7004 7005 rtw89_init_wait(&rtwdev->mcc.wait); 7006 rtw89_init_wait(&rtwdev->mlo.wait); 7007 rtw89_init_wait(&rtwdev->mac.fw_ofld_wait); 7008 rtw89_init_wait(&rtwdev->wow.wait); 7009 rtw89_init_wait(&rtwdev->mac.ps_wait); 7010 7011 wiphy_work_init(&rtwdev->c2h_work, rtw89_fw_c2h_work); 7012 wiphy_work_init(&rtwdev->ips_work, rtw89_ips_work); 7013 wiphy_work_init(&rtwdev->cancel_6ghz_probe_work, rtw89_cancel_6ghz_probe_work); 7014 INIT_WORK(&rtwdev->load_firmware_work, rtw89_load_firmware_work); 7015 7016 spin_lock_init(&rtwdev->tx_rpt.skb_lock); 7017 skb_queue_head_init(&rtwdev->c2h_queue); 7018 rtw89_core_ppdu_sts_init(rtwdev); 7019 rtw89_traffic_stats_init(rtwdev, &rtwdev->stats); 7020 7021 rtwdev->hal.rx_fltr = mac->default_rx_fltr; 7022 rtwdev->dbcc_en = false; 7023 rtwdev->mlo_dbcc_mode = MLO_DBCC_NOT_SUPPORT; 7024 rtwdev->mac.qta_mode = RTW89_QTA_SCC; 7025 7026 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) { 7027 rtwdev->dbcc_en = true; 7028 rtwdev->mac.qta_mode = RTW89_QTA_DBCC; 7029 rtwdev->mlo_dbcc_mode = MLO_1_PLUS_1_1RF; 7030 } 7031 7032 rtwdev->bbs[RTW89_PHY_0].phy_idx = RTW89_PHY_0; 7033 rtwdev->bbs[RTW89_PHY_1].phy_idx = RTW89_PHY_1; 7034 7035 wiphy_work_init(&btc->eapol_notify_work, rtw89_btc_ntfy_eapol_packet_work); 7036 wiphy_work_init(&btc->arp_notify_work, rtw89_btc_ntfy_arp_packet_work); 7037 wiphy_work_init(&btc->dhcp_notify_work, rtw89_btc_ntfy_dhcp_packet_work); 7038 wiphy_work_init(&btc->icmp_notify_work, rtw89_btc_ntfy_icmp_packet_work); 7039 7040 init_completion(&rtwdev->fw.req.completion); 7041 init_completion(&rtwdev->rfk_wait.completion); 7042 7043 schedule_work(&rtwdev->load_firmware_work); 7044 7045 rtw89_ser_init(rtwdev); 7046 rtw89_entity_init(rtwdev); 7047 rtw89_sar_init(rtwdev); 7048 rtw89_phy_ant_gain_init(rtwdev); 7049 7050 return 0; 7051 } 7052 EXPORT_SYMBOL(rtw89_core_init); 7053 7054 void rtw89_core_deinit(struct rtw89_dev *rtwdev) 7055 { 7056 rtw89_ser_deinit(rtwdev); 7057 rtw89_unload_firmware(rtwdev); 7058 __rtw89_fw_free_all_early_h2c(rtwdev); 7059 7060 destroy_workqueue(rtwdev->txq_wq); 7061 } 7062 EXPORT_SYMBOL(rtw89_core_deinit); 7063 7064 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 7065 const u8 *mac_addr, bool hw_scan) 7066 { 7067 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 7068 rtwvif_link->chanctx_idx); 7069 struct rtw89_bb_ctx *bb = rtw89_get_bb_ctx(rtwdev, rtwvif_link->phy_idx); 7070 7071 rtwdev->scanning = true; 7072 7073 ether_addr_copy(rtwvif_link->mac_addr, mac_addr); 7074 rtw89_btc_ntfy_scan_start(rtwdev, rtwvif_link->phy_idx, chan->band_type); 7075 rtw89_chip_rfk_scan(rtwdev, rtwvif_link, true); 7076 rtw89_hci_recalc_int_mit(rtwdev); 7077 rtw89_phy_config_edcca(rtwdev, bb, true); 7078 rtw89_tas_scan(rtwdev, true); 7079 7080 rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, mac_addr, 7081 RTW89_ROLE_INFO_CHANGE); 7082 } 7083 7084 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 7085 struct rtw89_vif_link *rtwvif_link, bool hw_scan) 7086 { 7087 struct ieee80211_bss_conf *bss_conf; 7088 struct rtw89_bb_ctx *bb; 7089 int ret; 7090 7091 if (!rtwvif_link) 7092 return; 7093 7094 rcu_read_lock(); 7095 7096 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 7097 ether_addr_copy(rtwvif_link->mac_addr, bss_conf->addr); 7098 7099 rcu_read_unlock(); 7100 7101 rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, NULL, 7102 RTW89_ROLE_INFO_CHANGE); 7103 7104 rtw89_chip_rfk_scan(rtwdev, rtwvif_link, false); 7105 rtw89_btc_ntfy_scan_finish(rtwdev, rtwvif_link->phy_idx); 7106 bb = rtw89_get_bb_ctx(rtwdev, rtwvif_link->phy_idx); 7107 rtw89_phy_config_edcca(rtwdev, bb, false); 7108 rtw89_tas_scan(rtwdev, false); 7109 7110 if (hw_scan) { 7111 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif_link, false, false, 7112 RTW89_SCAN_NULL_TIMEOUT); 7113 if (ret) 7114 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 7115 "scan send null-0 failed: %d\n", ret); 7116 } 7117 7118 rtwdev->scanning = false; 7119 rtw89_for_each_active_bb(rtwdev, bb) 7120 bb->dig.bypass_dig = true; 7121 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)) 7122 wiphy_work_queue(rtwdev->hw->wiphy, &rtwdev->ips_work); 7123 } 7124 7125 static void rtw89_read_chip_ver(struct rtw89_dev *rtwdev) 7126 { 7127 const struct rtw89_chip_info *chip = rtwdev->chip; 7128 struct rtw89_hal *hal = &rtwdev->hal; 7129 int ret; 7130 u8 val2; 7131 u8 val; 7132 u8 cv; 7133 7134 cv = rtw89_read32_mask(rtwdev, R_AX_SYS_CFG1, B_AX_CHIP_VER_MASK); 7135 if (chip->chip_id == RTL8852A && cv <= CHIP_CBV) { 7136 if (rtw89_read32(rtwdev, R_AX_GPIO0_7_FUNC_SEL) == RTW89_R32_DEAD) 7137 cv = CHIP_CAV; 7138 else 7139 cv = CHIP_CBV; 7140 } 7141 7142 hal->cv = cv; 7143 7144 if (rtw89_is_rtl885xb(rtwdev) || chip->chip_gen >= RTW89_CHIP_BE) { 7145 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_CV, &val); 7146 if (ret) 7147 return; 7148 7149 hal->acv = u8_get_bits(val, XTAL_SI_ACV_MASK); 7150 } 7151 7152 if (chip->chip_gen >= RTW89_CHIP_BE) { 7153 hal->cid = 7154 rtw89_read32_mask(rtwdev, R_BE_SYS_CHIPINFO, B_BE_HW_ID_MASK); 7155 7156 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_CHIP_ID_L, &val); 7157 if (ret) 7158 return; 7159 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_CHIP_ID_H, &val2); 7160 if (ret) 7161 return; 7162 7163 hal->aid = val | val2 << 8; 7164 } 7165 } 7166 7167 static void rtw89_core_setup_phycap(struct rtw89_dev *rtwdev) 7168 { 7169 const struct rtw89_chip_info *chip = rtwdev->chip; 7170 7171 rtwdev->hal.support_cckpd = 7172 !(rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV) && 7173 !(rtwdev->chip->chip_id == RTL8852B && rtwdev->hal.cv <= CHIP_CAV); 7174 rtwdev->hal.support_igi = 7175 rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV; 7176 7177 if (test_bit(RTW89_QUIRK_THERMAL_PROT_120C, rtwdev->quirks)) 7178 rtwdev->hal.thermal_prot_th = chip->thermal_th[1]; 7179 else if (test_bit(RTW89_QUIRK_THERMAL_PROT_110C, rtwdev->quirks)) 7180 rtwdev->hal.thermal_prot_th = chip->thermal_th[0]; 7181 else 7182 rtwdev->hal.thermal_prot_th = 0; 7183 } 7184 7185 static void rtw89_core_setup_rfe_parms(struct rtw89_dev *rtwdev) 7186 { 7187 const struct rtw89_chip_info *chip = rtwdev->chip; 7188 const struct rtw89_rfe_parms_conf *conf = chip->rfe_parms_conf; 7189 struct rtw89_efuse *efuse = &rtwdev->efuse; 7190 const struct rtw89_rfe_parms *sel; 7191 u8 rfe_type = efuse->rfe_type; 7192 7193 if (!conf) { 7194 sel = chip->dflt_parms; 7195 goto out; 7196 } 7197 7198 while (conf->rfe_parms) { 7199 if (rfe_type == conf->rfe_type) { 7200 sel = conf->rfe_parms; 7201 goto out; 7202 } 7203 conf++; 7204 } 7205 7206 sel = chip->dflt_parms; 7207 7208 out: 7209 rtwdev->rfe_parms = rtw89_load_rfe_data_from_fw(rtwdev, sel); 7210 rtw89_load_txpwr_table(rtwdev, rtwdev->rfe_parms->byr_tbl); 7211 } 7212 7213 int rtw89_core_mlsr_switch(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 7214 unsigned int link_id) 7215 { 7216 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 7217 u16 usable_links = ieee80211_vif_usable_links(vif); 7218 u16 active_links = vif->active_links; 7219 struct rtw89_vif_link *target; 7220 int ret; 7221 7222 lockdep_assert_wiphy(rtwdev->hw->wiphy); 7223 7224 if (unlikely(!ieee80211_vif_is_mld(vif))) 7225 return -EOPNOTSUPP; 7226 7227 if (unlikely(link_id >= IEEE80211_MLD_MAX_NUM_LINKS || 7228 !(usable_links & BIT(link_id)))) { 7229 rtw89_warn(rtwdev, "%s: link id %u is not usable\n", __func__, 7230 link_id); 7231 return -ENOLINK; 7232 } 7233 7234 if (active_links == BIT(link_id)) 7235 return 0; 7236 7237 rtw89_debug(rtwdev, RTW89_DBG_STATE, "%s: switch to link id %u MLSR\n", 7238 __func__, link_id); 7239 7240 rtw89_leave_lps(rtwdev); 7241 7242 ieee80211_stop_queues(rtwdev->hw); 7243 flush_work(&rtwdev->txq_work); 7244 7245 ret = ieee80211_set_active_links(vif, BIT(link_id)); 7246 if (ret) { 7247 rtw89_err(rtwdev, "%s: failed to work on link id %u\n", 7248 __func__, link_id); 7249 goto wake_queue; 7250 } 7251 7252 target = rtwvif->links[link_id]; 7253 if (unlikely(!target)) { 7254 rtw89_err(rtwdev, "%s: failed to confirm link id %u\n", 7255 __func__, link_id); 7256 7257 ieee80211_set_active_links(vif, active_links); 7258 ret = -EFAULT; 7259 goto wake_queue; 7260 } 7261 7262 if (RTW89_CHK_FW_FEATURE_GROUP(WITH_RFK_PRE_NOTIFY, &rtwdev->fw)) 7263 rtw89_chip_rfk_channel(rtwdev, target); 7264 7265 rtw89_fw_h2c_tx_history(rtwdev, target->mac_id); 7266 7267 rtwvif->mlo_mode = RTW89_MLO_MODE_MLSR; 7268 7269 wake_queue: 7270 ieee80211_wake_queues(rtwdev->hw); 7271 7272 return ret; 7273 } 7274 7275 static int rtw89_chip_efuse_info_setup(struct rtw89_dev *rtwdev) 7276 { 7277 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 7278 const struct rtw89_chip_info *chip = rtwdev->chip; 7279 bool bb_preinit = false; 7280 int ret; 7281 7282 /* 7283 * Normally in probe stage, we don't need to do BB pre-initialization. 7284 * However, RTL8922D firmware can access BB registers at firmware 7285 * initial state, so initialize it to avoid BB IO stuck in firmware. 7286 */ 7287 if (chip->chip_id == RTL8922D) 7288 bb_preinit = true; 7289 7290 ret = rtw89_mac_partial_init(rtwdev, false, bb_preinit); 7291 if (ret) 7292 return ret; 7293 7294 ret = mac->parse_efuse_map(rtwdev); 7295 if (ret) 7296 return ret; 7297 7298 ret = mac->parse_phycap_map(rtwdev); 7299 if (ret) 7300 return ret; 7301 7302 ret = rtw89_mac_setup_phycap(rtwdev); 7303 if (ret) 7304 return ret; 7305 7306 rtw89_core_setup_phycap(rtwdev); 7307 7308 rtw89_hci_mac_pre_deinit(rtwdev); 7309 7310 return 0; 7311 } 7312 7313 static int rtw89_chip_board_info_setup(struct rtw89_dev *rtwdev) 7314 { 7315 rtw89_chip_fem_setup(rtwdev); 7316 7317 return 0; 7318 } 7319 7320 static bool rtw89_chip_has_rfkill(struct rtw89_dev *rtwdev) 7321 { 7322 return !!rtwdev->chip->rfkill_init; 7323 } 7324 7325 static void rtw89_core_rfkill_init(struct rtw89_dev *rtwdev) 7326 { 7327 const struct rtw89_rfkill_regs *regs = rtwdev->chip->rfkill_init; 7328 7329 rtw89_write16_mask(rtwdev, regs->pinmux.addr, 7330 regs->pinmux.mask, regs->pinmux.data); 7331 rtw89_write16_mask(rtwdev, regs->mode.addr, 7332 regs->mode.mask, regs->mode.data); 7333 } 7334 7335 static bool rtw89_core_rfkill_get(struct rtw89_dev *rtwdev) 7336 { 7337 const struct rtw89_reg_def *reg = &rtwdev->chip->rfkill_get; 7338 7339 return !rtw89_read8_mask(rtwdev, reg->addr, reg->mask); 7340 } 7341 7342 static void rtw89_rfkill_polling_init(struct rtw89_dev *rtwdev) 7343 { 7344 if (!rtw89_chip_has_rfkill(rtwdev)) 7345 return; 7346 7347 rtw89_core_rfkill_init(rtwdev); 7348 rtw89_core_rfkill_poll(rtwdev, true); 7349 wiphy_rfkill_start_polling(rtwdev->hw->wiphy); 7350 } 7351 7352 static void rtw89_rfkill_polling_deinit(struct rtw89_dev *rtwdev) 7353 { 7354 if (!rtw89_chip_has_rfkill(rtwdev)) 7355 return; 7356 7357 wiphy_rfkill_stop_polling(rtwdev->hw->wiphy); 7358 } 7359 7360 void rtw89_core_rfkill_poll(struct rtw89_dev *rtwdev, bool force) 7361 { 7362 bool prev, blocked; 7363 7364 if (!rtw89_chip_has_rfkill(rtwdev)) 7365 return; 7366 7367 prev = test_bit(RTW89_FLAG_HW_RFKILL_STATE, rtwdev->flags); 7368 blocked = rtw89_core_rfkill_get(rtwdev); 7369 7370 if (!force && prev == blocked) 7371 return; 7372 7373 rtw89_info(rtwdev, "rfkill hardware state changed to %s\n", 7374 str_enable_disable(!blocked)); 7375 7376 assign_bit(RTW89_FLAG_HW_RFKILL_STATE, rtwdev->flags, blocked); 7377 7378 wiphy_rfkill_set_hw_state(rtwdev->hw->wiphy, blocked); 7379 } 7380 7381 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev) 7382 { 7383 struct rtw89_fw_req_info *fw_req = &rtwdev->fw.req; 7384 struct rtw89_efuse *efuse = &rtwdev->efuse; 7385 struct rtw89_hal *hal = &rtwdev->hal; 7386 int ret; 7387 7388 rtw89_read_chip_ver(rtwdev); 7389 7390 ret = rtw89_mac_pwr_on(rtwdev); 7391 if (ret) { 7392 rtw89_err(rtwdev, "failed to power on\n"); 7393 return ret; 7394 } 7395 7396 ret = rtw89_wait_firmware_completion(rtwdev); 7397 if (ret) { 7398 rtw89_err(rtwdev, "failed to wait firmware completion\n"); 7399 goto out; 7400 } 7401 7402 ret = rtw89_fw_recognize(rtwdev); 7403 if (ret) { 7404 rtw89_err(rtwdev, "failed to recognize firmware\n"); 7405 goto out; 7406 } 7407 7408 ret = rtw89_chip_efuse_info_setup(rtwdev); 7409 if (ret) 7410 goto out; 7411 7412 ret = rtw89_fw_recognize_elements(rtwdev); 7413 if (ret) { 7414 rtw89_err(rtwdev, "failed to recognize firmware elements\n"); 7415 goto out; 7416 } 7417 7418 ret = rtw89_chip_board_info_setup(rtwdev); 7419 if (ret) 7420 goto out; 7421 7422 ret = rtw89_chip_data_setup(rtwdev); 7423 if (ret) 7424 goto out; 7425 7426 rtw89_core_setup_rfe_parms(rtwdev); 7427 rtwdev->ps_mode = rtw89_update_ps_mode(rtwdev); 7428 7429 rtw89_info(rtwdev, "chip info CID: %x, CV: %x, AID: %x, ACV: %x, RFE: %d\n", 7430 hal->cid, hal->cv, hal->aid, hal->acv, efuse->rfe_type); 7431 7432 out: 7433 if (fw_req->free_after_probe) 7434 __rtw89_unload_firmware(rtwdev); 7435 7436 rtw89_mac_pwr_off(rtwdev); 7437 7438 return ret; 7439 } 7440 EXPORT_SYMBOL(rtw89_chip_info_setup); 7441 7442 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 7443 struct rtw89_vif_link *rtwvif_link) 7444 { 7445 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 7446 const struct rtw89_chip_info *chip = rtwdev->chip; 7447 struct ieee80211_bss_conf *bss_conf; 7448 7449 rcu_read_lock(); 7450 7451 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false); 7452 if (!bss_conf->he_support || !vif->cfg.assoc) { 7453 rcu_read_unlock(); 7454 return; 7455 } 7456 7457 rcu_read_unlock(); 7458 7459 if (chip->ops->set_txpwr_ul_tb_offset) 7460 chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif_link->mac_idx); 7461 } 7462 7463 static int rtw89_core_register_hw(struct rtw89_dev *rtwdev) 7464 { 7465 const struct rtw89_chip_info *chip = rtwdev->chip; 7466 u8 n = rtwdev->support_mlo ? chip->support_link_num : 1; 7467 struct ieee80211_hw *hw = rtwdev->hw; 7468 struct rtw89_efuse *efuse = &rtwdev->efuse; 7469 struct rtw89_hal *hal = &rtwdev->hal; 7470 int ret; 7471 int tx_headroom = IEEE80211_HT_CTL_LEN; 7472 7473 if (rtwdev->hci.type == RTW89_HCI_TYPE_USB) 7474 tx_headroom += chip->txwd_body_size + chip->txwd_info_size; 7475 7476 hw->vif_data_size = struct_size_t(struct rtw89_vif, links_inst, n); 7477 hw->sta_data_size = struct_size_t(struct rtw89_sta, links_inst, n); 7478 hw->txq_data_size = sizeof(struct rtw89_txq); 7479 hw->chanctx_data_size = sizeof(struct rtw89_chanctx_cfg); 7480 7481 SET_IEEE80211_PERM_ADDR(hw, efuse->addr); 7482 7483 hw->extra_tx_headroom = tx_headroom; 7484 hw->queues = IEEE80211_NUM_ACS; 7485 hw->max_rx_aggregation_subframes = chip->max_rx_agg_num; 7486 hw->max_tx_aggregation_subframes = chip->max_tx_agg_num; 7487 hw->uapsd_max_sp_len = IEEE80211_WMM_IE_STA_QOSINFO_SP_ALL; 7488 7489 hw->radiotap_mcs_details |= IEEE80211_RADIOTAP_MCS_HAVE_FEC | 7490 IEEE80211_RADIOTAP_MCS_HAVE_STBC; 7491 hw->radiotap_vht_details |= IEEE80211_RADIOTAP_VHT_KNOWN_STBC | 7492 IEEE80211_RADIOTAP_VHT_KNOWN_BEAMFORMED; 7493 7494 ieee80211_hw_set(hw, SIGNAL_DBM); 7495 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 7496 ieee80211_hw_set(hw, MFP_CAPABLE); 7497 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS); 7498 ieee80211_hw_set(hw, AMPDU_AGGREGATION); 7499 ieee80211_hw_set(hw, RX_INCLUDES_FCS); 7500 ieee80211_hw_set(hw, TX_AMSDU); 7501 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); 7502 ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU); 7503 ieee80211_hw_set(hw, SUPPORTS_PS); 7504 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS); 7505 ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS); 7506 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID); 7507 ieee80211_hw_set(hw, WANT_MONITOR_VIF); 7508 ieee80211_hw_set(hw, CHANCTX_STA_CSA); 7509 7510 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 7511 ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW); 7512 7513 if (RTW89_CHK_FW_FEATURE(BEACON_FILTER, &rtwdev->fw)) 7514 ieee80211_hw_set(hw, CONNECTION_MONITOR); 7515 7516 if (RTW89_CHK_FW_FEATURE(NOTIFY_AP_INFO, &rtwdev->fw)) 7517 ieee80211_hw_set(hw, AP_LINK_PS); 7518 7519 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | 7520 BIT(NL80211_IFTYPE_AP) | 7521 BIT(NL80211_IFTYPE_P2P_CLIENT) | 7522 BIT(NL80211_IFTYPE_P2P_GO) | 7523 BIT(NL80211_IFTYPE_P2P_DEVICE); 7524 7525 if (hal->ant_diversity) { 7526 hw->wiphy->available_antennas_tx = 0x3; 7527 hw->wiphy->available_antennas_rx = 0x3; 7528 } else { 7529 hw->wiphy->available_antennas_tx = BIT(rtwdev->chip->rf_path_num) - 1; 7530 hw->wiphy->available_antennas_rx = BIT(rtwdev->chip->rf_path_num) - 1; 7531 } 7532 7533 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS | 7534 WIPHY_FLAG_TDLS_EXTERNAL_SETUP | 7535 WIPHY_FLAG_AP_UAPSD | 7536 WIPHY_FLAG_HAS_CHANNEL_SWITCH | 7537 WIPHY_FLAG_SUPPORTS_EXT_KEK_KCK; 7538 7539 if (!chip->support_rnr) 7540 hw->wiphy->flags |= WIPHY_FLAG_SPLIT_SCAN_6GHZ; 7541 7542 if (rtwdev->support_mlo) { 7543 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_MLO; 7544 hw->wiphy->iftype_ext_capab = rtw89_iftypes_ext_capa; 7545 hw->wiphy->num_iftype_ext_capab = ARRAY_SIZE(rtw89_iftypes_ext_capa); 7546 } 7547 7548 hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR; 7549 7550 hw->wiphy->max_scan_ssids = RTW89_SCANOFLD_MAX_SSID; 7551 hw->wiphy->max_scan_ie_len = RTW89_SCANOFLD_MAX_IE_LEN; 7552 7553 #ifdef CONFIG_PM 7554 hw->wiphy->wowlan = rtwdev->chip->wowlan_stub; 7555 hw->wiphy->max_sched_scan_ssids = RTW89_SCANOFLD_MAX_SSID; 7556 #endif 7557 7558 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL); 7559 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL); 7560 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL); 7561 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL); 7562 hw->wiphy->max_remain_on_channel_duration = 1000; 7563 7564 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 7565 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SCAN_RANDOM_SN); 7566 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SET_SCAN_DWELL); 7567 7568 ret = rtw89_core_set_supported_band(rtwdev); 7569 if (ret) { 7570 rtw89_err(rtwdev, "failed to set supported band\n"); 7571 return ret; 7572 } 7573 7574 ret = rtw89_regd_setup(rtwdev); 7575 if (ret) { 7576 rtw89_err(rtwdev, "failed to set up regd\n"); 7577 return ret; 7578 } 7579 7580 hw->wiphy->sar_capa = &rtw89_sar_capa; 7581 7582 ret = ieee80211_register_hw(hw); 7583 if (ret) { 7584 rtw89_err(rtwdev, "failed to register hw\n"); 7585 return ret; 7586 } 7587 7588 ret = rtw89_regd_init_hint(rtwdev); 7589 if (ret) { 7590 rtw89_err(rtwdev, "failed to init regd\n"); 7591 goto err_unregister_hw; 7592 } 7593 7594 rtw89_rfkill_polling_init(rtwdev); 7595 rtw89_btc_init(rtwdev); 7596 rtw89_led_init(rtwdev); 7597 7598 return 0; 7599 7600 err_unregister_hw: 7601 ieee80211_unregister_hw(hw); 7602 7603 return ret; 7604 } 7605 7606 static void rtw89_core_unregister_hw(struct rtw89_dev *rtwdev) 7607 { 7608 struct ieee80211_hw *hw = rtwdev->hw; 7609 7610 rtw89_led_deinit(rtwdev); 7611 rtw89_rfkill_polling_deinit(rtwdev); 7612 ieee80211_unregister_hw(hw); 7613 } 7614 7615 int rtw89_core_register(struct rtw89_dev *rtwdev) 7616 { 7617 int ret; 7618 7619 ret = rtw89_core_register_hw(rtwdev); 7620 if (ret) { 7621 rtw89_err(rtwdev, "failed to register core hw\n"); 7622 return ret; 7623 } 7624 7625 rtw89_phy_dm_init_data(rtwdev); 7626 rtw89_debugfs_init(rtwdev); 7627 7628 return 0; 7629 } 7630 EXPORT_SYMBOL(rtw89_core_register); 7631 7632 void rtw89_core_unregister(struct rtw89_dev *rtwdev) 7633 { 7634 rtw89_core_unregister_hw(rtwdev); 7635 7636 rtw89_debugfs_deinit(rtwdev); 7637 } 7638 EXPORT_SYMBOL(rtw89_core_unregister); 7639 7640 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 7641 u32 bus_data_size, 7642 const struct rtw89_driver_info *info) 7643 { 7644 const unsigned long *dev_id_quirks = &info->dev_id_quirks; 7645 const struct rtw89_chip_variant *variant = info->variant; 7646 const struct rtw89_chip_info *chip = info->chip; 7647 struct rtw89_fw_info early_fw = {}; 7648 const struct firmware *firmware; 7649 struct ieee80211_hw *hw; 7650 struct rtw89_dev *rtwdev; 7651 struct ieee80211_ops *ops; 7652 u32 driver_data_size; 7653 int fw_format = -1; 7654 bool support_mlo; 7655 bool no_chanctx; 7656 7657 firmware = rtw89_early_fw_feature_recognize(device, chip, variant, 7658 &early_fw, &fw_format); 7659 7660 ops = kmemdup(&rtw89_ops, sizeof(rtw89_ops), GFP_KERNEL); 7661 if (!ops) 7662 goto err; 7663 7664 no_chanctx = chip->support_chanctx_num == 0 || 7665 !RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &early_fw) || 7666 !RTW89_CHK_FW_FEATURE(BEACON_FILTER, &early_fw); 7667 7668 if (no_chanctx) { 7669 ops->add_chanctx = ieee80211_emulate_add_chanctx; 7670 ops->remove_chanctx = ieee80211_emulate_remove_chanctx; 7671 ops->change_chanctx = ieee80211_emulate_change_chanctx; 7672 ops->switch_vif_chanctx = ieee80211_emulate_switch_vif_chanctx; 7673 ops->assign_vif_chanctx = NULL; 7674 ops->unassign_vif_chanctx = NULL; 7675 ops->remain_on_channel = NULL; 7676 ops->cancel_remain_on_channel = NULL; 7677 } 7678 7679 if (!chip->support_noise) 7680 ops->get_survey = NULL; 7681 7682 driver_data_size = sizeof(struct rtw89_dev) + bus_data_size; 7683 hw = ieee80211_alloc_hw(driver_data_size, ops); 7684 if (!hw) 7685 goto err; 7686 7687 /* Currently, our AP_LINK_PS handling only works for non-MLD softap 7688 * or MLD-single-link softap. If RTW89_MLD_NON_STA_LINK_NUM enlarges, 7689 * please tweak entire AP_LINKS_PS handling before supporting MLO. 7690 */ 7691 support_mlo = !no_chanctx && chip->support_link_num && 7692 RTW89_CHK_FW_FEATURE(NOTIFY_AP_INFO, &early_fw) && 7693 RTW89_MLD_NON_STA_LINK_NUM == 1; 7694 7695 hw->wiphy->iface_combinations = rtw89_iface_combs; 7696 7697 if (no_chanctx || chip->support_chanctx_num == 1) 7698 hw->wiphy->n_iface_combinations = 1; 7699 else 7700 hw->wiphy->n_iface_combinations = ARRAY_SIZE(rtw89_iface_combs); 7701 7702 rtwdev = hw->priv; 7703 rtwdev->hw = hw; 7704 rtwdev->dev = device; 7705 rtwdev->ops = ops; 7706 rtwdev->chip = chip; 7707 rtwdev->variant = variant; 7708 rtwdev->board = info->board; 7709 rtwdev->fw.req.firmware = firmware; 7710 rtwdev->fw.fw_format = fw_format; 7711 rtwdev->support_mlo = support_mlo; 7712 7713 bitmap_or(rtwdev->quirks, rtwdev->quirks, dev_id_quirks, 7714 NUM_OF_RTW89_QUIRKS); 7715 7716 rtw89_debug(rtwdev, RTW89_DBG_CHAN, "probe driver %s chanctx\n", 7717 no_chanctx ? "without" : "with"); 7718 rtw89_debug(rtwdev, RTW89_DBG_CHAN, "probe driver %s MLO cap\n", 7719 support_mlo ? "with" : "without"); 7720 7721 return rtwdev; 7722 7723 err: 7724 kfree(ops); 7725 release_firmware(firmware); 7726 return NULL; 7727 } 7728 EXPORT_SYMBOL(rtw89_alloc_ieee80211_hw); 7729 7730 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev) 7731 { 7732 kfree(rtwdev->ops); 7733 kfree(rtwdev->rfe_data); 7734 release_firmware(rtwdev->fw.req.firmware); 7735 ieee80211_free_hw(rtwdev->hw); 7736 } 7737 EXPORT_SYMBOL(rtw89_free_ieee80211_hw); 7738 7739 MODULE_FIRMWARE(RTW89_FWNAME_BOARD_ELM); 7740 MODULE_AUTHOR("Realtek Corporation"); 7741 MODULE_DESCRIPTION("Realtek 802.11ax wireless core module"); 7742 MODULE_LICENSE("Dual BSD/GPL"); 7743