1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2024 Realtek Corporation
3 */
4
5 #include "coex.h"
6 #include "fw.h"
7 #include "mac.h"
8 #include "phy.h"
9 #include "reg.h"
10 #include "rtw8852bt.h"
11 #include "rtw8852bt_rfk.h"
12 #include "rtw8852b_common.h"
13
14 #define RTW8852BT_FW_FORMAT_MAX 0
15 #define RTW8852BT_FW_BASENAME "rtw89/rtw8852bt_fw"
16 #define RTW8852BT_MODULE_FIRMWARE \
17 RTW8852BT_FW_BASENAME ".bin"
18
19 static const struct rtw89_hfc_ch_cfg rtw8852bt_hfc_chcfg_pcie[] = {
20 {16, 742, grp_0}, /* ACH 0 */
21 {16, 742, grp_0}, /* ACH 1 */
22 {16, 742, grp_0}, /* ACH 2 */
23 {16, 742, grp_0}, /* ACH 3 */
24 {0, 0, grp_0}, /* ACH 4 */
25 {0, 0, grp_0}, /* ACH 5 */
26 {0, 0, grp_0}, /* ACH 6 */
27 {0, 0, grp_0}, /* ACH 7 */
28 {15, 743, grp_0}, /* B0MGQ */
29 {15, 743, grp_0}, /* B0HIQ */
30 {0, 0, grp_0}, /* B1MGQ */
31 {0, 0, grp_0}, /* B1HIQ */
32 {40, 0, 0} /* FWCMDQ */
33 };
34
35 static const struct rtw89_hfc_pub_cfg rtw8852bt_hfc_pubcfg_pcie = {
36 958, /* Group 0 */
37 0, /* Group 1 */
38 958, /* Public Max */
39 0 /* WP threshold */
40 };
41
42 static const struct rtw89_hfc_param_ini rtw8852bt_hfc_param_ini_pcie[] = {
43 [RTW89_QTA_SCC] = {rtw8852bt_hfc_chcfg_pcie, &rtw8852bt_hfc_pubcfg_pcie,
44 &rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH},
45 [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_preccfg_pcie,
46 RTW89_HCIFC_POH},
47 [RTW89_QTA_INVALID] = {NULL},
48 };
49
50 static const struct rtw89_dle_mem rtw8852bt_dle_mem_pcie[] = {
51 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size23,
52 &rtw89_mac_size.ple_size9, &rtw89_mac_size.wde_qt23,
53 &rtw89_mac_size.wde_qt23, &rtw89_mac_size.ple_qt57,
54 &rtw89_mac_size.ple_qt59},
55 [RTW89_QTA_WOW] = {RTW89_QTA_WOW, &rtw89_mac_size.wde_size23,
56 &rtw89_mac_size.ple_size9, &rtw89_mac_size.wde_qt23,
57 &rtw89_mac_size.wde_qt23, &rtw89_mac_size.ple_qt57,
58 &rtw89_mac_size.ple_qt_52bt_wow},
59 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size4,
60 &rtw89_mac_size.ple_size4, &rtw89_mac_size.wde_qt4,
61 &rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13,
62 &rtw89_mac_size.ple_qt13},
63 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL,
64 NULL},
65 };
66
67 static const u32 rtw8852bt_h2c_regs[RTW89_H2CREG_MAX] = {
68 R_AX_H2CREG_DATA0, R_AX_H2CREG_DATA1, R_AX_H2CREG_DATA2,
69 R_AX_H2CREG_DATA3
70 };
71
72 static const u32 rtw8852bt_c2h_regs[RTW89_C2HREG_MAX] = {
73 R_AX_C2HREG_DATA0, R_AX_C2HREG_DATA1, R_AX_C2HREG_DATA2,
74 R_AX_C2HREG_DATA3
75 };
76
77 static const u32 rtw8852bt_wow_wakeup_regs[RTW89_WOW_REASON_NUM] = {
78 R_AX_C2HREG_DATA3 + 3, R_AX_C2HREG_DATA3 + 3,
79 };
80
81 static const struct rtw89_page_regs rtw8852bt_page_regs = {
82 .hci_fc_ctrl = R_AX_HCI_FC_CTRL,
83 .ch_page_ctrl = R_AX_CH_PAGE_CTRL,
84 .ach_page_ctrl = R_AX_ACH0_PAGE_CTRL,
85 .ach_page_info = R_AX_ACH0_PAGE_INFO,
86 .pub_page_info3 = R_AX_PUB_PAGE_INFO3,
87 .pub_page_ctrl1 = R_AX_PUB_PAGE_CTRL1,
88 .pub_page_ctrl2 = R_AX_PUB_PAGE_CTRL2,
89 .pub_page_info1 = R_AX_PUB_PAGE_INFO1,
90 .pub_page_info2 = R_AX_PUB_PAGE_INFO2,
91 .wp_page_ctrl1 = R_AX_WP_PAGE_CTRL1,
92 .wp_page_ctrl2 = R_AX_WP_PAGE_CTRL2,
93 .wp_page_info1 = R_AX_WP_PAGE_INFO1,
94 };
95
96 static const struct rtw89_reg_def rtw8852bt_dcfo_comp = {
97 R_DCFO_COMP_S0, B_DCFO_COMP_S0_MSK
98 };
99
100 static const struct rtw89_imr_info rtw8852bt_imr_info = {
101 .wdrls_imr_set = B_AX_WDRLS_IMR_SET,
102 .wsec_imr_reg = R_AX_SEC_DEBUG,
103 .wsec_imr_set = B_AX_IMR_ERROR,
104 .mpdu_tx_imr_set = 0,
105 .mpdu_rx_imr_set = 0,
106 .sta_sch_imr_set = B_AX_STA_SCHEDULER_IMR_SET,
107 .txpktctl_imr_b0_reg = R_AX_TXPKTCTL_ERR_IMR_ISR,
108 .txpktctl_imr_b0_clr = B_AX_TXPKTCTL_IMR_B0_CLR,
109 .txpktctl_imr_b0_set = B_AX_TXPKTCTL_IMR_B0_SET,
110 .txpktctl_imr_b1_reg = R_AX_TXPKTCTL_ERR_IMR_ISR_B1,
111 .txpktctl_imr_b1_clr = B_AX_TXPKTCTL_IMR_B1_CLR,
112 .txpktctl_imr_b1_set = B_AX_TXPKTCTL_IMR_B1_SET,
113 .wde_imr_clr = B_AX_WDE_IMR_CLR_V01,
114 .wde_imr_set = B_AX_WDE_IMR_SET_V01,
115 .ple_imr_clr = B_AX_PLE_IMR_CLR,
116 .ple_imr_set = B_AX_PLE_IMR_SET,
117 .host_disp_imr_clr = B_AX_HOST_DISP_IMR_CLR,
118 .host_disp_imr_set = B_AX_HOST_DISP_IMR_SET_V01,
119 .cpu_disp_imr_clr = B_AX_CPU_DISP_IMR_CLR,
120 .cpu_disp_imr_set = B_AX_CPU_DISP_IMR_SET,
121 .other_disp_imr_clr = B_AX_OTHER_DISP_IMR_CLR,
122 .other_disp_imr_set = 0,
123 .bbrpt_com_err_imr_reg = R_AX_BBRPT_COM_ERR_IMR_ISR,
124 .bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR_ISR,
125 .bbrpt_err_imr_set = 0,
126 .bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR_ISR,
127 .ptcl_imr_clr = B_AX_PTCL_IMR_CLR_ALL,
128 .ptcl_imr_set = B_AX_PTCL_IMR_SET,
129 .cdma_imr_0_reg = R_AX_DLE_CTRL,
130 .cdma_imr_0_clr = B_AX_DLE_IMR_CLR,
131 .cdma_imr_0_set = B_AX_DLE_IMR_SET,
132 .cdma_imr_1_reg = 0,
133 .cdma_imr_1_clr = 0,
134 .cdma_imr_1_set = 0,
135 .phy_intf_imr_reg = R_AX_PHYINFO_ERR_IMR,
136 .phy_intf_imr_clr = B_AX_PHYINFO_IMR_EN_ALL,
137 .phy_intf_imr_set = B_AX_PHYINFO_IMR_SET,
138 .rmac_imr_reg = R_AX_RMAC_ERR_ISR,
139 .rmac_imr_clr = B_AX_RMAC_IMR_CLR,
140 .rmac_imr_set = B_AX_RMAC_IMR_SET,
141 .tmac_imr_reg = R_AX_TMAC_ERR_IMR_ISR,
142 .tmac_imr_clr = B_AX_TMAC_IMR_CLR,
143 .tmac_imr_set = B_AX_TMAC_IMR_SET,
144 };
145
146 static const struct rtw89_rrsr_cfgs rtw8852bt_rrsr_cfgs = {
147 .ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0},
148 .rsc = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_RSC_MASK, 2},
149 };
150
151 static const struct rtw89_rfkill_regs rtw8852bt_rfkill_regs = {
152 .pinmux = {R_AX_GPIO8_15_FUNC_SEL,
153 B_AX_PINMUX_GPIO9_FUNC_SEL_MASK,
154 0xf},
155 .mode = {R_AX_GPIO_EXT_CTRL + 2,
156 (B_AX_GPIO_MOD_9 | B_AX_GPIO_IO_SEL_9) >> 16,
157 0x0},
158 };
159
160 static const struct rtw89_dig_regs rtw8852bt_dig_regs = {
161 .seg0_pd_reg = R_SEG0R_PD_V1,
162 .pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK,
163 .pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK_V1,
164 .bmode_pd_reg = R_BMODE_PDTH_EN_V1,
165 .bmode_cca_rssi_limit_en = B_BMODE_PDTH_LIMIT_EN_MSK_V1,
166 .bmode_pd_lower_bound_reg = R_BMODE_PDTH_V1,
167 .bmode_rssi_nocca_low_th_mask = B_BMODE_PDTH_LOWER_BOUND_MSK_V1,
168 .p0_lna_init = {R_PATH0_LNA_INIT_V1, B_PATH0_LNA_INIT_IDX_MSK},
169 .p1_lna_init = {R_PATH1_LNA_INIT_V1, B_PATH1_LNA_INIT_IDX_MSK},
170 .p0_tia_init = {R_PATH0_TIA_INIT_V1, B_PATH0_TIA_INIT_IDX_MSK_V1},
171 .p1_tia_init = {R_PATH1_TIA_INIT_V1, B_PATH1_TIA_INIT_IDX_MSK_V1},
172 .p0_rxb_init = {R_PATH0_RXB_INIT_V1, B_PATH0_RXB_INIT_IDX_MSK_V1},
173 .p1_rxb_init = {R_PATH1_RXB_INIT_V1, B_PATH1_RXB_INIT_IDX_MSK_V1},
174 .p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC_V2,
175 B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
176 .p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC_V2,
177 B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
178 .p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC_V2,
179 B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
180 .p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC_V2,
181 B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
182 };
183
184 static const struct rtw89_edcca_regs rtw8852bt_edcca_regs = {
185 .edcca_level = R_SEG0R_EDCCA_LVL_V1,
186 .edcca_mask = B_EDCCA_LVL_MSK0,
187 .edcca_p_mask = B_EDCCA_LVL_MSK1,
188 .ppdu_level = R_SEG0R_EDCCA_LVL_V1,
189 .ppdu_mask = B_EDCCA_LVL_MSK3,
190 .p = {{
191 .rpt_a = R_EDCCA_RPT_A,
192 .rpt_b = R_EDCCA_RPT_B,
193 .rpt_sel = R_EDCCA_RPT_SEL,
194 .rpt_sel_mask = B_EDCCA_RPT_SEL_MSK,
195 }, {
196 .rpt_a = R_EDCCA_RPT_P1_A,
197 .rpt_b = R_EDCCA_RPT_P1_B,
198 .rpt_sel = R_EDCCA_RPT_SEL,
199 .rpt_sel_mask = B_EDCCA_RPT_SEL_P1_MSK,
200 }},
201 .tx_collision_t2r_st = R_TX_COLLISION_T2R_ST,
202 .tx_collision_t2r_st_mask = B_TX_COLLISION_T2R_ST_M,
203 };
204
205 static const struct rtw89_btc_rf_trx_para rtw89_btc_8852bt_rf_ul[] = {
206 {255, 0, 0, 7}, /* 0 -> original */
207 {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */
208 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
209 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
210 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
211 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */
212 {6, 1, 0, 7},
213 {13, 1, 0, 7},
214 {13, 1, 0, 7}
215 };
216
217 static const struct rtw89_btc_rf_trx_para rtw89_btc_8852bt_rf_dl[] = {
218 {255, 0, 0, 7}, /* 0 -> original */
219 {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */
220 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
221 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
222 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
223 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */
224 {255, 1, 0, 7},
225 {255, 1, 0, 7},
226 {255, 1, 0, 7}
227 };
228
229 static const struct rtw89_btc_fbtc_mreg rtw89_btc_8852bt_mon_reg[] = {
230 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24),
231 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda28),
232 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda2c),
233 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30),
234 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c),
235 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda10),
236 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda20),
237 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34),
238 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xcef4),
239 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x8424),
240 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd200),
241 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd220),
242 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980),
243 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4aa4),
244 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4778),
245 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x476c),
246 };
247
248 static const u8 rtw89_btc_8852bt_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {70, 60, 50, 40};
249 static const u8 rtw89_btc_8852bt_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {50, 40, 30, 20};
250
rtw8852bt_pwr_on_func(struct rtw89_dev * rtwdev)251 static int rtw8852bt_pwr_on_func(struct rtw89_dev *rtwdev)
252 {
253 u32 val32;
254 int ret;
255
256 rtw89_write32_set(rtwdev, R_AX_LDO_AON_CTRL0, B_AX_PD_REGU_L);
257 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_AFSM_WLSUS_EN |
258 B_AX_AFSM_PCIE_SUS_EN);
259 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_DIS_WLBT_PDNSUSEN_SOPC);
260 rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_DIS_WLBT_LPSEN_LOPC);
261 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APDM_HPDN);
262 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS);
263 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_OCP_L1_MASK, 7);
264
265 ret = read_poll_timeout(rtw89_read32, val32, val32 & B_AX_RDY_SYSPWR,
266 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
267 if (ret)
268 return ret;
269
270 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON);
271 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC);
272
273 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFN_ONMAC),
274 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
275 if (ret)
276 return ret;
277
278 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
279 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
280 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
281 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
282 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
283 rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_CALIB_EN_V1);
284 rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3);
285
286 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL,
287 XTAL_SI_GND_SHDN_WL, XTAL_SI_GND_SHDN_WL);
288 if (ret)
289 return ret;
290
291 rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3);
292
293 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL,
294 XTAL_SI_SHDN_WL, XTAL_SI_SHDN_WL);
295 if (ret)
296 return ret;
297 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_WEI,
298 XTAL_SI_OFF_WEI);
299 if (ret)
300 return ret;
301 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_EI,
302 XTAL_SI_OFF_EI);
303 if (ret)
304 return ret;
305 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_RFC2RF);
306 if (ret)
307 return ret;
308 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_WEI,
309 XTAL_SI_PON_WEI);
310 if (ret)
311 return ret;
312 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_EI,
313 XTAL_SI_PON_EI);
314 if (ret)
315 return ret;
316 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SRAM2RFC);
317 if (ret)
318 return ret;
319 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_SRAM_CTRL, 0, XTAL_SI_SRAM_DIS);
320 if (ret)
321 return ret;
322 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_2, 0, XTAL_SI_LDO_LPS);
323 if (ret)
324 return ret;
325 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_4, 0, XTAL_SI_LPS_CAP);
326 if (ret)
327 return ret;
328
329 rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
330 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_ISO_EB2CORE);
331 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B15);
332
333 fsleep(1000);
334
335 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B14);
336 rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
337
338 if (!rtwdev->efuse.valid || rtwdev->efuse.power_k_valid)
339 goto func_en;
340
341 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_VOL_L1_MASK, 0x9);
342 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_VREFPFM_L_MASK, 0xA);
343
344 func_en:
345 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN,
346 B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_MPDU_PROC_EN |
347 B_AX_WD_RLS_EN | B_AX_DLE_WDE_EN | B_AX_TXPKT_CTRL_EN |
348 B_AX_STA_SCH_EN | B_AX_DLE_PLE_EN | B_AX_PKT_BUF_EN |
349 B_AX_DMAC_TBL_EN | B_AX_PKT_IN_EN | B_AX_DLE_CPUIO_EN |
350 B_AX_DISPATCHER_EN | B_AX_BBRPT_EN | B_AX_MAC_SEC_EN |
351 B_AX_DMACREG_GCKEN);
352 rtw89_write32_set(rtwdev, R_AX_CMAC_FUNC_EN,
353 B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN |
354 B_AX_FORCE_CMACREG_GCKEN | B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN |
355 B_AX_PTCLTOP_EN | B_AX_SCHEDULER_EN | B_AX_TMAC_EN |
356 B_AX_RMAC_EN);
357
358 rtw89_write32_mask(rtwdev, R_AX_EECS_EESK_FUNC_SEL,
359 B_AX_PINMUX_EESK_FUNC_SEL_MASK, 0x1);
360
361 return 0;
362 }
363
rtw8852bt_pwr_off_func(struct rtw89_dev * rtwdev)364 static int rtw8852bt_pwr_off_func(struct rtw89_dev *rtwdev)
365 {
366 u32 val32;
367 int ret;
368
369 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_RFC2RF,
370 XTAL_SI_RFC2RF);
371 if (ret)
372 return ret;
373 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_EI);
374 if (ret)
375 return ret;
376 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_WEI);
377 if (ret)
378 return ret;
379 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0, XTAL_SI_RF00);
380 if (ret)
381 return ret;
382 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0, XTAL_SI_RF10);
383 if (ret)
384 return ret;
385 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_SRAM2RFC,
386 XTAL_SI_SRAM2RFC);
387 if (ret)
388 return ret;
389 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_EI);
390 if (ret)
391 return ret;
392 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_WEI);
393 if (ret)
394 return ret;
395
396 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON);
397 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
398 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, B_AX_FEN_BB_GLB_RSTN | B_AX_FEN_BBRSTB);
399 rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3);
400
401 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SHDN_WL);
402 if (ret)
403 return ret;
404
405 rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3);
406
407 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_GND_SHDN_WL);
408 if (ret)
409 return ret;
410
411 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_OFFMAC);
412
413 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFM_OFFMAC),
414 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
415 if (ret)
416 return ret;
417
418 rtw89_write32(rtwdev, R_AX_WLLPS_CTRL, SW_LPS_OPTION);
419 rtw89_write32_set(rtwdev, R_AX_SYS_SWR_CTRL1, B_AX_SYM_CTRL_SPS_PWMFREQ);
420 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_REG_ZCDC_H_MASK, 0x3);
421 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS);
422
423 return 0;
424 }
425
rtw8852bt_bb_reset_en(struct rtw89_dev * rtwdev,enum rtw89_band band,enum rtw89_phy_idx phy_idx,bool en)426 static void rtw8852bt_bb_reset_en(struct rtw89_dev *rtwdev, enum rtw89_band band,
427 enum rtw89_phy_idx phy_idx, bool en)
428 {
429 if (en) {
430 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS,
431 B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx);
432 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS,
433 B_S1_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx);
434 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);
435 if (band == RTW89_BAND_2G)
436 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x0);
437 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x0);
438 } else {
439 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x1);
440 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x1);
441 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS,
442 B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx);
443 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS,
444 B_S1_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx);
445 fsleep(1);
446 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx);
447 }
448 }
449
rtw8852bt_bb_reset(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)450 static void rtw8852bt_bb_reset(struct rtw89_dev *rtwdev,
451 enum rtw89_phy_idx phy_idx)
452 {
453 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB,
454 B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI, 0x1);
455 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
456 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB,
457 B_P1_TXPW_RSTB_MANON | B_P1_TXPW_RSTB_TSSI, 0x1);
458 rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
459 rtw8852bx_bb_reset_all(rtwdev, phy_idx);
460 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB,
461 B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI, 3);
462 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
463 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB,
464 B_P1_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI, 0x3);
465 rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
466 }
467
rtw8852bt_set_channel(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)468 static void rtw8852bt_set_channel(struct rtw89_dev *rtwdev,
469 const struct rtw89_chan *chan,
470 enum rtw89_mac_idx mac_idx,
471 enum rtw89_phy_idx phy_idx)
472 {
473 rtw8852bx_set_channel_mac(rtwdev, chan, mac_idx);
474 rtw8852bx_set_channel_bb(rtwdev, chan, phy_idx);
475 rtw8852bt_set_channel_rf(rtwdev, chan, phy_idx);
476 }
477
rtw8852bt_tssi_cont_en(struct rtw89_dev * rtwdev,bool en,enum rtw89_rf_path path)478 static void rtw8852bt_tssi_cont_en(struct rtw89_dev *rtwdev, bool en,
479 enum rtw89_rf_path path)
480 {
481 static const u32 tssi_trk[2] = {R_P0_TSSI_TRK, R_P1_TSSI_TRK};
482
483 if (en)
484 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], B_P0_TSSI_TRK_EN, 0x0);
485 else
486 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], B_P0_TSSI_TRK_EN, 0x1);
487 }
488
rtw8852bt_tssi_cont_en_phyidx(struct rtw89_dev * rtwdev,bool en,u8 phy_idx,const struct rtw89_chan * chan)489 static void rtw8852bt_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en,
490 u8 phy_idx, const struct rtw89_chan *chan)
491 {
492 if (!rtwdev->dbcc_en) {
493 rtw8852bt_tssi_cont_en(rtwdev, en, RF_PATH_A);
494 rtw8852bt_tssi_cont_en(rtwdev, en, RF_PATH_B);
495 rtw8852bt_tssi_scan(rtwdev, phy_idx, chan);
496 } else {
497 if (phy_idx == RTW89_PHY_0)
498 rtw8852bt_tssi_cont_en(rtwdev, en, RF_PATH_A);
499 else
500 rtw8852bt_tssi_cont_en(rtwdev, en, RF_PATH_B);
501 }
502 }
503
rtw8852bt_adc_en(struct rtw89_dev * rtwdev,bool en)504 static void rtw8852bt_adc_en(struct rtw89_dev *rtwdev, bool en)
505 {
506 if (en)
507 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0x0);
508 else
509 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0xf);
510 }
511
rtw8852bt_set_channel_help(struct rtw89_dev * rtwdev,bool enter,struct rtw89_channel_help_params * p,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)512 static void rtw8852bt_set_channel_help(struct rtw89_dev *rtwdev, bool enter,
513 struct rtw89_channel_help_params *p,
514 const struct rtw89_chan *chan,
515 enum rtw89_mac_idx mac_idx,
516 enum rtw89_phy_idx phy_idx)
517 {
518 if (enter) {
519 rtw89_chip_stop_sch_tx(rtwdev, RTW89_MAC_0, &p->tx_en, RTW89_SCH_TX_SEL_ALL);
520 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false);
521 rtw8852bt_tssi_cont_en_phyidx(rtwdev, false, RTW89_PHY_0, chan);
522 rtw8852bt_adc_en(rtwdev, false);
523 fsleep(40);
524 rtw8852bt_bb_reset_en(rtwdev, chan->band_type, phy_idx, false);
525 } else {
526 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true);
527 rtw8852bt_adc_en(rtwdev, true);
528 rtw8852bt_tssi_cont_en_phyidx(rtwdev, true, RTW89_PHY_0, chan);
529 rtw8852bt_bb_reset_en(rtwdev, chan->band_type, phy_idx, true);
530 rtw89_chip_resume_sch_tx(rtwdev, RTW89_MAC_0, p->tx_en);
531 }
532 }
533
rtw8852bt_rfk_init(struct rtw89_dev * rtwdev)534 static void rtw8852bt_rfk_init(struct rtw89_dev *rtwdev)
535 {
536 rtwdev->is_tssi_mode[RF_PATH_A] = false;
537 rtwdev->is_tssi_mode[RF_PATH_B] = false;
538
539 rtw8852bt_dpk_init(rtwdev);
540 rtw8852bt_rck(rtwdev);
541 rtw8852bt_dack(rtwdev, RTW89_CHANCTX_0);
542 rtw8852bt_rx_dck(rtwdev, RTW89_PHY_0, RTW89_CHANCTX_0);
543 }
544
rtw8852bt_rfk_channel(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)545 static void rtw8852bt_rfk_channel(struct rtw89_dev *rtwdev,
546 struct rtw89_vif_link *rtwvif_link)
547 {
548 enum rtw89_chanctx_idx chanctx_idx = rtwvif_link->chanctx_idx;
549 enum rtw89_phy_idx phy_idx = rtwvif_link->phy_idx;
550
551 rtw89_btc_ntfy_conn_rfk(rtwdev, true);
552
553 rtw8852bt_rx_dck(rtwdev, phy_idx, chanctx_idx);
554 rtw8852bt_iqk(rtwdev, phy_idx, chanctx_idx);
555 rtw89_btc_ntfy_preserve_bt_time(rtwdev, 30);
556 rtw8852bt_tssi(rtwdev, phy_idx, true, chanctx_idx);
557 rtw89_btc_ntfy_preserve_bt_time(rtwdev, 30);
558 rtw8852bt_dpk(rtwdev, phy_idx, chanctx_idx);
559
560 rtw89_btc_ntfy_conn_rfk(rtwdev, false);
561 }
562
rtw8852bt_rfk_band_changed(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan)563 static void rtw8852bt_rfk_band_changed(struct rtw89_dev *rtwdev,
564 enum rtw89_phy_idx phy_idx,
565 const struct rtw89_chan *chan)
566 {
567 rtw8852bt_tssi_scan(rtwdev, phy_idx, chan);
568 }
569
rtw8852bt_rfk_scan(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,bool start)570 static void rtw8852bt_rfk_scan(struct rtw89_dev *rtwdev,
571 struct rtw89_vif_link *rtwvif_link,
572 bool start)
573 {
574 rtw8852bt_wifi_scan_notify(rtwdev, start, rtwvif_link->phy_idx,
575 rtwvif_link->chanctx_idx);
576 }
577
rtw8852bt_rfk_track(struct rtw89_dev * rtwdev)578 static void rtw8852bt_rfk_track(struct rtw89_dev *rtwdev)
579 {
580 rtw8852bt_dpk_track(rtwdev);
581 }
582
rtw8852bt_btc_set_rfe(struct rtw89_dev * rtwdev)583 static void rtw8852bt_btc_set_rfe(struct rtw89_dev *rtwdev)
584 {
585 const struct rtw89_btc_ver *ver = rtwdev->btc.ver;
586 union rtw89_btc_module_info *md = &rtwdev->btc.mdinfo;
587
588 if (ver->fcxinit == 7) {
589 md->md_v7.rfe_type = rtwdev->efuse.rfe_type;
590 md->md_v7.kt_ver = rtwdev->hal.cv;
591 md->md_v7.kt_ver_adie = rtwdev->hal.acv;
592 md->md_v7.bt_solo = 0;
593 md->md_v7.bt_pos = BTC_BT_BTG;
594 md->md_v7.switch_type = BTC_SWITCH_INTERNAL;
595 md->md_v7.wa_type = 0;
596
597 md->md_v7.ant.type = BTC_ANT_SHARED;
598 md->md_v7.ant.num = 2;
599 md->md_v7.ant.isolation = 10;
600 md->md_v7.ant.diversity = 0;
601 /* WL 1-stream+1-Ant is located at 0:s0(path-A) or 1:s1(path-B) */
602 md->md_v7.ant.single_pos = RF_PATH_A;
603 md->md_v7.ant.btg_pos = RF_PATH_B;
604
605 if (md->md_v7.rfe_type == 0) {
606 rtwdev->btc.dm.error.map.rfe_type0 = true;
607 return;
608 }
609
610 md->md_v7.ant.num = (md->md_v7.rfe_type % 2) ? 2 : 3;
611 md->md_v7.ant.stream_cnt = 2;
612 md->md_v7.wa_type |= BTC_WA_INIT_SCAN;
613
614 if (md->md_v7.ant.num == 2) {
615 md->md_v7.ant.type = BTC_ANT_SHARED;
616 md->md_v7.bt_pos = BTC_BT_BTG;
617 md->md_v7.wa_type |= BTC_WA_HFP_LAG;
618 } else {
619 md->md_v7.ant.type = BTC_ANT_DEDICATED;
620 md->md_v7.bt_pos = BTC_BT_ALONE;
621 }
622 } else {
623 return;
624 }
625 }
626
627 static void
rtw8852bt_btc_set_wl_txpwr_ctrl(struct rtw89_dev * rtwdev,u32 txpwr_val)628 rtw8852bt_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val)
629 {
630 u16 ctrl_all_time = u32_get_bits(txpwr_val, GENMASK(15, 0));
631 u16 ctrl_gnt_bt = u32_get_bits(txpwr_val, GENMASK(31, 16));
632
633 switch (ctrl_all_time) {
634 case 0xffff:
635 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_AX_PWR_RATE_CTRL,
636 B_AX_FORCE_PWR_BY_RATE_EN, 0x0);
637 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_AX_PWR_RATE_CTRL,
638 B_AX_FORCE_PWR_BY_RATE_VALUE_MASK, 0x0);
639 break;
640 default:
641 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_AX_PWR_RATE_CTRL,
642 B_AX_FORCE_PWR_BY_RATE_VALUE_MASK,
643 ctrl_all_time);
644 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_AX_PWR_RATE_CTRL,
645 B_AX_FORCE_PWR_BY_RATE_EN, 0x1);
646 break;
647 }
648
649 switch (ctrl_gnt_bt) {
650 case 0xffff:
651 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_AX_PWR_COEXT_CTRL,
652 B_AX_TXAGC_BT_EN, 0x0);
653 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_AX_PWR_COEXT_CTRL,
654 B_AX_TXAGC_BT_MASK, 0x0);
655 break;
656 default:
657 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_AX_PWR_COEXT_CTRL,
658 B_AX_TXAGC_BT_MASK, ctrl_gnt_bt);
659 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_AX_PWR_COEXT_CTRL,
660 B_AX_TXAGC_BT_EN, 0x1);
661 break;
662 }
663 }
664
665 static const struct rtw89_chip_ops rtw8852bt_chip_ops = {
666 .enable_bb_rf = rtw8852bx_mac_enable_bb_rf,
667 .disable_bb_rf = rtw8852bx_mac_disable_bb_rf,
668 .bb_preinit = NULL,
669 .bb_postinit = NULL,
670 .bb_reset = rtw8852bt_bb_reset,
671 .bb_sethw = rtw8852bx_bb_sethw,
672 .read_rf = rtw89_phy_read_rf_v1,
673 .write_rf = rtw89_phy_write_rf_v1,
674 .set_channel = rtw8852bt_set_channel,
675 .set_channel_help = rtw8852bt_set_channel_help,
676 .read_efuse = rtw8852bx_read_efuse,
677 .read_phycap = rtw8852bx_read_phycap,
678 .fem_setup = NULL,
679 .rfe_gpio = NULL,
680 .rfk_hw_init = NULL,
681 .rfk_init = rtw8852bt_rfk_init,
682 .rfk_init_late = NULL,
683 .rfk_channel = rtw8852bt_rfk_channel,
684 .rfk_band_changed = rtw8852bt_rfk_band_changed,
685 .rfk_scan = rtw8852bt_rfk_scan,
686 .rfk_track = rtw8852bt_rfk_track,
687 .power_trim = rtw8852bx_power_trim,
688 .set_txpwr = rtw8852bx_set_txpwr,
689 .set_txpwr_ctrl = rtw8852bx_set_txpwr_ctrl,
690 .init_txpwr_unit = rtw8852bx_init_txpwr_unit,
691 .get_thermal = rtw8852bx_get_thermal,
692 .ctrl_btg_bt_rx = rtw8852bx_ctrl_btg_bt_rx,
693 .query_ppdu = rtw8852bx_query_ppdu,
694 .convert_rpl_to_rssi = rtw8852bx_convert_rpl_to_rssi,
695 .phy_rpt_to_rssi = NULL,
696 .ctrl_nbtg_bt_tx = rtw8852bx_ctrl_nbtg_bt_tx,
697 .cfg_txrx_path = rtw8852bx_bb_cfg_txrx_path,
698 .set_txpwr_ul_tb_offset = rtw8852bx_set_txpwr_ul_tb_offset,
699 .digital_pwr_comp = NULL,
700 .pwr_on_func = rtw8852bt_pwr_on_func,
701 .pwr_off_func = rtw8852bt_pwr_off_func,
702 .query_rxdesc = rtw89_core_query_rxdesc,
703 .fill_txdesc = rtw89_core_fill_txdesc,
704 .fill_txdesc_fwcmd = rtw89_core_fill_txdesc,
705 .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path,
706 .mac_cfg_gnt = rtw89_mac_cfg_gnt,
707 .stop_sch_tx = rtw89_mac_stop_sch_tx,
708 .resume_sch_tx = rtw89_mac_resume_sch_tx,
709 .h2c_dctl_sec_cam = NULL,
710 .h2c_default_cmac_tbl = rtw89_fw_h2c_default_cmac_tbl,
711 .h2c_assoc_cmac_tbl = rtw89_fw_h2c_assoc_cmac_tbl,
712 .h2c_ampdu_cmac_tbl = NULL,
713 .h2c_txtime_cmac_tbl = rtw89_fw_h2c_txtime_cmac_tbl,
714 .h2c_default_dmac_tbl = NULL,
715 .h2c_update_beacon = rtw89_fw_h2c_update_beacon,
716 .h2c_ba_cam = rtw89_fw_h2c_ba_cam,
717
718 .btc_set_rfe = rtw8852bt_btc_set_rfe,
719 .btc_init_cfg = rtw8852bx_btc_init_cfg,
720 .btc_set_wl_pri = rtw8852bx_btc_set_wl_pri,
721 .btc_set_wl_txpwr_ctrl = rtw8852bt_btc_set_wl_txpwr_ctrl,
722 .btc_get_bt_rssi = rtw8852bx_btc_get_bt_rssi,
723 .btc_update_bt_cnt = rtw8852bx_btc_update_bt_cnt,
724 .btc_wl_s1_standby = rtw8852bx_btc_wl_s1_standby,
725 .btc_set_wl_rx_gain = rtw8852bx_btc_set_wl_rx_gain,
726 .btc_set_policy = rtw89_btc_set_policy_v1,
727 };
728
729 #ifdef CONFIG_PM
730 static const struct wiphy_wowlan_support rtw_wowlan_stub_8852bt = {
731 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT,
732 .n_patterns = RTW89_MAX_PATTERN_NUM,
733 .pattern_max_len = RTW89_MAX_PATTERN_SIZE,
734 .pattern_min_len = 1,
735 };
736 #endif
737
738 const struct rtw89_chip_info rtw8852bt_chip_info = {
739 .chip_id = RTL8852BT,
740 .chip_gen = RTW89_CHIP_AX,
741 .ops = &rtw8852bt_chip_ops,
742 .mac_def = &rtw89_mac_gen_ax,
743 .phy_def = &rtw89_phy_gen_ax,
744 .fw_basename = RTW8852BT_FW_BASENAME,
745 .fw_format_max = RTW8852BT_FW_FORMAT_MAX,
746 .try_ce_fw = true,
747 .bbmcu_nr = 0,
748 .needed_fw_elms = RTW89_AX_GEN_DEF_NEEDED_FW_ELEMENTS_NO_6GHZ,
749 .fw_blacklist = &rtw89_fw_blacklist_default,
750 .fifo_size = 458752,
751 .small_fifo_size = true,
752 .dle_scc_rsvd_size = 98304,
753 .max_amsdu_limit = 5000,
754 .dis_2g_40m_ul_ofdma = true,
755 .rsvd_ple_ofst = 0x6f800,
756 .hfc_param_ini = rtw8852bt_hfc_param_ini_pcie,
757 .dle_mem = rtw8852bt_dle_mem_pcie,
758 .wde_qempty_acq_grpnum = 4,
759 .wde_qempty_mgq_grpsel = 4,
760 .rf_base_addr = {0xe000, 0xf000},
761 .thermal_th = {0x32, 0x35},
762 .pwr_on_seq = NULL,
763 .pwr_off_seq = NULL,
764 .bb_table = NULL,
765 .bb_gain_table = NULL,
766 .rf_table = {},
767 .nctl_table = NULL,
768 .nctl_post_table = NULL,
769 .dflt_parms = NULL,
770 .rfe_parms_conf = NULL,
771 .txpwr_factor_bb = 3,
772 .txpwr_factor_rf = 2,
773 .txpwr_factor_mac = 1,
774 .dig_table = NULL,
775 .dig_regs = &rtw8852bt_dig_regs,
776 .tssi_dbw_table = NULL,
777 .support_macid_num = RTW89_MAX_MAC_ID_NUM,
778 .support_link_num = 0,
779 .support_chanctx_num = 1,
780 .support_rnr = false,
781 .support_bands = BIT(NL80211_BAND_2GHZ) |
782 BIT(NL80211_BAND_5GHZ),
783 .support_bandwidths = BIT(NL80211_CHAN_WIDTH_20) |
784 BIT(NL80211_CHAN_WIDTH_40) |
785 BIT(NL80211_CHAN_WIDTH_80),
786 .support_unii4 = true,
787 .support_ant_gain = true,
788 .support_tas = false,
789 .ul_tb_waveform_ctrl = true,
790 .ul_tb_pwr_diff = false,
791 .rx_freq_frome_ie = true,
792 .hw_sec_hdr = false,
793 .hw_mgmt_tx_encrypt = false,
794 .hw_tkip_crypto = true,
795 .rf_path_num = 2,
796 .tx_nss = 2,
797 .rx_nss = 2,
798 .acam_num = 128,
799 .bcam_num = 10,
800 .scam_num = 128,
801 .bacam_num = 2,
802 .bacam_dynamic_num = 4,
803 .bacam_ver = RTW89_BACAM_V0,
804 .ppdu_max_usr = 4,
805 .sec_ctrl_efuse_size = 4,
806 .physical_efuse_size = 1216,
807 .logical_efuse_size = 2048,
808 .limit_efuse_size = 1280,
809 .dav_phy_efuse_size = 96,
810 .dav_log_efuse_size = 16,
811 .efuse_blocks = NULL,
812 .phycap_addr = 0x580,
813 .phycap_size = 128,
814 .para_ver = 0,
815 .wlcx_desired = 0x070e0000,
816 .btcx_desired = 0x7,
817 .scbd = 0x1,
818 .mailbox = 0x1,
819
820 .afh_guard_ch = 6,
821 .wl_rssi_thres = rtw89_btc_8852bt_wl_rssi_thres,
822 .bt_rssi_thres = rtw89_btc_8852bt_bt_rssi_thres,
823 .rssi_tol = 2,
824 .mon_reg_num = ARRAY_SIZE(rtw89_btc_8852bt_mon_reg),
825 .mon_reg = rtw89_btc_8852bt_mon_reg,
826 .rf_para_ulink_num = ARRAY_SIZE(rtw89_btc_8852bt_rf_ul),
827 .rf_para_ulink = rtw89_btc_8852bt_rf_ul,
828 .rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8852bt_rf_dl),
829 .rf_para_dlink = rtw89_btc_8852bt_rf_dl,
830 .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) |
831 BIT(RTW89_PS_MODE_CLK_GATED) |
832 BIT(RTW89_PS_MODE_PWR_GATED),
833 .low_power_hci_modes = 0,
834 .h2c_cctl_func_id = H2C_FUNC_MAC_CCTLINFO_UD,
835 .hci_func_en_addr = R_AX_HCI_FUNC_EN,
836 .h2c_desc_size = sizeof(struct rtw89_txwd_body),
837 .txwd_body_size = sizeof(struct rtw89_txwd_body),
838 .txwd_info_size = sizeof(struct rtw89_txwd_info),
839 .h2c_ctrl_reg = R_AX_H2CREG_CTRL,
840 .h2c_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_H2C_DEQ_CNT_MASK >> 8},
841 .h2c_regs = rtw8852bt_h2c_regs,
842 .c2h_ctrl_reg = R_AX_C2HREG_CTRL,
843 .c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8},
844 .c2h_regs = rtw8852bt_c2h_regs,
845 .page_regs = &rtw8852bt_page_regs,
846 .wow_reason_reg = rtw8852bt_wow_wakeup_regs,
847 .cfo_src_fd = true,
848 .cfo_hw_comp = true,
849 .dcfo_comp = &rtw8852bt_dcfo_comp,
850 .dcfo_comp_sft = 10,
851 .imr_info = &rtw8852bt_imr_info,
852 .imr_dmac_table = NULL,
853 .imr_cmac_table = NULL,
854 .rrsr_cfgs = &rtw8852bt_rrsr_cfgs,
855 .bss_clr_vld = {R_BSS_CLR_MAP_V1, B_BSS_CLR_MAP_VLD0},
856 .bss_clr_map_reg = R_BSS_CLR_MAP_V1,
857 .rfkill_init = &rtw8852bt_rfkill_regs,
858 .rfkill_get = {R_AX_GPIO_EXT_CTRL, B_AX_GPIO_IN_9},
859 .dma_ch_mask = BIT(RTW89_DMA_ACH4) | BIT(RTW89_DMA_ACH5) |
860 BIT(RTW89_DMA_ACH6) | BIT(RTW89_DMA_ACH7) |
861 BIT(RTW89_DMA_B1MG) | BIT(RTW89_DMA_B1HI),
862 .edcca_regs = &rtw8852bt_edcca_regs,
863 #ifdef CONFIG_PM
864 .wowlan_stub = &rtw_wowlan_stub_8852bt,
865 #endif
866 .xtal_info = NULL,
867 };
868 EXPORT_SYMBOL(rtw8852bt_chip_info);
869
870 MODULE_FIRMWARE(RTW8852BT_MODULE_FIRMWARE);
871 MODULE_AUTHOR("Realtek Corporation");
872 MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852BT driver");
873 MODULE_LICENSE("Dual BSD/GPL");
874