1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2022 Realtek Corporation
3 */
4
5 #include "coex.h"
6 #include "fw.h"
7 #include "mac.h"
8 #include "phy.h"
9 #include "reg.h"
10 #include "rtw8852b.h"
11 #include "rtw8852b_common.h"
12 #include "rtw8852b_rfk.h"
13 #include "rtw8852b_table.h"
14 #include "txrx.h"
15
16 #define RTW8852B_FW_FORMAT_MAX 1
17 #define RTW8852B_FW_BASENAME "rtw89/rtw8852b_fw"
18 #define RTW8852B_MODULE_FIRMWARE \
19 RTW8852B_FW_BASENAME "-" __stringify(RTW8852B_FW_FORMAT_MAX) ".bin"
20
21 static const struct rtw89_hfc_ch_cfg rtw8852b_hfc_chcfg_pcie[] = {
22 {5, 341, grp_0}, /* ACH 0 */
23 {5, 341, grp_0}, /* ACH 1 */
24 {4, 342, grp_0}, /* ACH 2 */
25 {4, 342, grp_0}, /* ACH 3 */
26 {0, 0, grp_0}, /* ACH 4 */
27 {0, 0, grp_0}, /* ACH 5 */
28 {0, 0, grp_0}, /* ACH 6 */
29 {0, 0, grp_0}, /* ACH 7 */
30 {4, 342, grp_0}, /* B0MGQ */
31 {4, 342, grp_0}, /* B0HIQ */
32 {0, 0, grp_0}, /* B1MGQ */
33 {0, 0, grp_0}, /* B1HIQ */
34 {40, 0, 0} /* FWCMDQ */
35 };
36
37 static const struct rtw89_hfc_pub_cfg rtw8852b_hfc_pubcfg_pcie = {
38 446, /* Group 0 */
39 0, /* Group 1 */
40 446, /* Public Max */
41 0 /* WP threshold */
42 };
43
44 static const struct rtw89_hfc_param_ini rtw8852b_hfc_param_ini_pcie[] = {
45 [RTW89_QTA_SCC] = {rtw8852b_hfc_chcfg_pcie, &rtw8852b_hfc_pubcfg_pcie,
46 &rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH},
47 [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_preccfg_pcie,
48 RTW89_HCIFC_POH},
49 [RTW89_QTA_INVALID] = {NULL},
50 };
51
52 static const struct rtw89_dle_mem rtw8852b_dle_mem_pcie[] = {
53 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size7,
54 &rtw89_mac_size.ple_size6, &rtw89_mac_size.wde_qt7,
55 &rtw89_mac_size.wde_qt7, &rtw89_mac_size.ple_qt18,
56 &rtw89_mac_size.ple_qt58},
57 [RTW89_QTA_WOW] = {RTW89_QTA_WOW, &rtw89_mac_size.wde_size7,
58 &rtw89_mac_size.ple_size6, &rtw89_mac_size.wde_qt7,
59 &rtw89_mac_size.wde_qt7, &rtw89_mac_size.ple_qt18,
60 &rtw89_mac_size.ple_qt_52b_wow},
61 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size9,
62 &rtw89_mac_size.ple_size8, &rtw89_mac_size.wde_qt4,
63 &rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13,
64 &rtw89_mac_size.ple_qt13},
65 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL,
66 NULL},
67 };
68
69 static const u32 rtw8852b_h2c_regs[RTW89_H2CREG_MAX] = {
70 R_AX_H2CREG_DATA0, R_AX_H2CREG_DATA1, R_AX_H2CREG_DATA2,
71 R_AX_H2CREG_DATA3
72 };
73
74 static const u32 rtw8852b_c2h_regs[RTW89_C2HREG_MAX] = {
75 R_AX_C2HREG_DATA0, R_AX_C2HREG_DATA1, R_AX_C2HREG_DATA2,
76 R_AX_C2HREG_DATA3
77 };
78
79 static const u32 rtw8852b_wow_wakeup_regs[RTW89_WOW_REASON_NUM] = {
80 R_AX_C2HREG_DATA3 + 3, R_AX_C2HREG_DATA3 + 3,
81 };
82
83 static const struct rtw89_page_regs rtw8852b_page_regs = {
84 .hci_fc_ctrl = R_AX_HCI_FC_CTRL,
85 .ch_page_ctrl = R_AX_CH_PAGE_CTRL,
86 .ach_page_ctrl = R_AX_ACH0_PAGE_CTRL,
87 .ach_page_info = R_AX_ACH0_PAGE_INFO,
88 .pub_page_info3 = R_AX_PUB_PAGE_INFO3,
89 .pub_page_ctrl1 = R_AX_PUB_PAGE_CTRL1,
90 .pub_page_ctrl2 = R_AX_PUB_PAGE_CTRL2,
91 .pub_page_info1 = R_AX_PUB_PAGE_INFO1,
92 .pub_page_info2 = R_AX_PUB_PAGE_INFO2,
93 .wp_page_ctrl1 = R_AX_WP_PAGE_CTRL1,
94 .wp_page_ctrl2 = R_AX_WP_PAGE_CTRL2,
95 .wp_page_info1 = R_AX_WP_PAGE_INFO1,
96 };
97
98 static const struct rtw89_reg_def rtw8852b_dcfo_comp = {
99 R_DCFO_COMP_S0, B_DCFO_COMP_S0_MSK
100 };
101
102 static const struct rtw89_imr_info rtw8852b_imr_info = {
103 .wdrls_imr_set = B_AX_WDRLS_IMR_SET,
104 .wsec_imr_reg = R_AX_SEC_DEBUG,
105 .wsec_imr_set = B_AX_IMR_ERROR,
106 .mpdu_tx_imr_set = 0,
107 .mpdu_rx_imr_set = 0,
108 .sta_sch_imr_set = B_AX_STA_SCHEDULER_IMR_SET,
109 .txpktctl_imr_b0_reg = R_AX_TXPKTCTL_ERR_IMR_ISR,
110 .txpktctl_imr_b0_clr = B_AX_TXPKTCTL_IMR_B0_CLR,
111 .txpktctl_imr_b0_set = B_AX_TXPKTCTL_IMR_B0_SET,
112 .txpktctl_imr_b1_reg = R_AX_TXPKTCTL_ERR_IMR_ISR_B1,
113 .txpktctl_imr_b1_clr = B_AX_TXPKTCTL_IMR_B1_CLR,
114 .txpktctl_imr_b1_set = B_AX_TXPKTCTL_IMR_B1_SET,
115 .wde_imr_clr = B_AX_WDE_IMR_CLR,
116 .wde_imr_set = B_AX_WDE_IMR_SET,
117 .ple_imr_clr = B_AX_PLE_IMR_CLR,
118 .ple_imr_set = B_AX_PLE_IMR_SET,
119 .host_disp_imr_clr = B_AX_HOST_DISP_IMR_CLR,
120 .host_disp_imr_set = B_AX_HOST_DISP_IMR_SET,
121 .cpu_disp_imr_clr = B_AX_CPU_DISP_IMR_CLR,
122 .cpu_disp_imr_set = B_AX_CPU_DISP_IMR_SET,
123 .other_disp_imr_clr = B_AX_OTHER_DISP_IMR_CLR,
124 .other_disp_imr_set = 0,
125 .bbrpt_com_err_imr_reg = R_AX_BBRPT_COM_ERR_IMR_ISR,
126 .bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR_ISR,
127 .bbrpt_err_imr_set = 0,
128 .bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR_ISR,
129 .ptcl_imr_clr = B_AX_PTCL_IMR_CLR_ALL,
130 .ptcl_imr_set = B_AX_PTCL_IMR_SET,
131 .cdma_imr_0_reg = R_AX_DLE_CTRL,
132 .cdma_imr_0_clr = B_AX_DLE_IMR_CLR,
133 .cdma_imr_0_set = B_AX_DLE_IMR_SET,
134 .cdma_imr_1_reg = 0,
135 .cdma_imr_1_clr = 0,
136 .cdma_imr_1_set = 0,
137 .phy_intf_imr_reg = R_AX_PHYINFO_ERR_IMR,
138 .phy_intf_imr_clr = 0,
139 .phy_intf_imr_set = 0,
140 .rmac_imr_reg = R_AX_RMAC_ERR_ISR,
141 .rmac_imr_clr = B_AX_RMAC_IMR_CLR,
142 .rmac_imr_set = B_AX_RMAC_IMR_SET,
143 .tmac_imr_reg = R_AX_TMAC_ERR_IMR_ISR,
144 .tmac_imr_clr = B_AX_TMAC_IMR_CLR,
145 .tmac_imr_set = B_AX_TMAC_IMR_SET,
146 };
147
148 static const struct rtw89_rrsr_cfgs rtw8852b_rrsr_cfgs = {
149 .ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0},
150 .rsc = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_RSC_MASK, 2},
151 };
152
153 static const struct rtw89_rfkill_regs rtw8852b_rfkill_regs = {
154 .pinmux = {R_AX_GPIO8_15_FUNC_SEL,
155 B_AX_PINMUX_GPIO9_FUNC_SEL_MASK,
156 0xf},
157 .mode = {R_AX_GPIO_EXT_CTRL + 2,
158 (B_AX_GPIO_MOD_9 | B_AX_GPIO_IO_SEL_9) >> 16,
159 0x0},
160 };
161
162 static const struct rtw89_dig_regs rtw8852b_dig_regs = {
163 .seg0_pd_reg = R_SEG0R_PD_V1,
164 .pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK,
165 .pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK_V1,
166 .bmode_pd_reg = R_BMODE_PDTH_EN_V1,
167 .bmode_cca_rssi_limit_en = B_BMODE_PDTH_LIMIT_EN_MSK_V1,
168 .bmode_pd_lower_bound_reg = R_BMODE_PDTH_V1,
169 .bmode_rssi_nocca_low_th_mask = B_BMODE_PDTH_LOWER_BOUND_MSK_V1,
170 .p0_lna_init = {R_PATH0_LNA_INIT_V1, B_PATH0_LNA_INIT_IDX_MSK},
171 .p1_lna_init = {R_PATH1_LNA_INIT_V1, B_PATH1_LNA_INIT_IDX_MSK},
172 .p0_tia_init = {R_PATH0_TIA_INIT_V1, B_PATH0_TIA_INIT_IDX_MSK_V1},
173 .p1_tia_init = {R_PATH1_TIA_INIT_V1, B_PATH1_TIA_INIT_IDX_MSK_V1},
174 .p0_rxb_init = {R_PATH0_RXB_INIT_V1, B_PATH0_RXB_INIT_IDX_MSK_V1},
175 .p1_rxb_init = {R_PATH1_RXB_INIT_V1, B_PATH1_RXB_INIT_IDX_MSK_V1},
176 .p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC_V2,
177 B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
178 .p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC_V2,
179 B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
180 .p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC_V2,
181 B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
182 .p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC_V2,
183 B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
184 };
185
186 static const struct rtw89_edcca_regs rtw8852b_edcca_regs = {
187 .edcca_level = R_SEG0R_EDCCA_LVL_V1,
188 .edcca_mask = B_EDCCA_LVL_MSK0,
189 .edcca_p_mask = B_EDCCA_LVL_MSK1,
190 .ppdu_level = R_SEG0R_EDCCA_LVL_V1,
191 .ppdu_mask = B_EDCCA_LVL_MSK3,
192 .rpt_a = R_EDCCA_RPT_A,
193 .rpt_b = R_EDCCA_RPT_B,
194 .rpt_sel = R_EDCCA_RPT_SEL,
195 .rpt_sel_mask = B_EDCCA_RPT_SEL_MSK,
196 .tx_collision_t2r_st = R_TX_COLLISION_T2R_ST,
197 .tx_collision_t2r_st_mask = B_TX_COLLISION_T2R_ST_M,
198 };
199
200 static const struct rtw89_btc_rf_trx_para rtw89_btc_8852b_rf_ul[] = {
201 {255, 0, 0, 7}, /* 0 -> original */
202 {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */
203 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
204 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
205 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
206 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */
207 {6, 1, 0, 7},
208 {13, 1, 0, 7},
209 {13, 1, 0, 7}
210 };
211
212 static const struct rtw89_btc_rf_trx_para rtw89_btc_8852b_rf_dl[] = {
213 {255, 0, 0, 7}, /* 0 -> original */
214 {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */
215 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
216 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
217 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
218 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */
219 {255, 1, 0, 7},
220 {255, 1, 0, 7},
221 {255, 1, 0, 7}
222 };
223
224 static const struct rtw89_btc_fbtc_mreg rtw89_btc_8852b_mon_reg[] = {
225 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24),
226 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda28),
227 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda2c),
228 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30),
229 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c),
230 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda10),
231 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda20),
232 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34),
233 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xcef4),
234 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x8424),
235 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd200),
236 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd220),
237 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980),
238 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4738),
239 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4688),
240 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4694),
241 };
242
243 static const u8 rtw89_btc_8852b_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {70, 60, 50, 40};
244 static const u8 rtw89_btc_8852b_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {50, 40, 30, 20};
245
rtw8852b_pwr_sps_ana(struct rtw89_dev * rtwdev)246 static void rtw8852b_pwr_sps_ana(struct rtw89_dev *rtwdev)
247 {
248 struct rtw89_efuse *efuse = &rtwdev->efuse;
249
250 if (efuse->rfe_type == 0x5)
251 rtw89_write16(rtwdev, R_AX_SPS_ANA_ON_CTRL2, RTL8852B_RFE_05_SPS_ANA);
252 }
253
rtw8852b_pwr_on_func(struct rtw89_dev * rtwdev)254 static int rtw8852b_pwr_on_func(struct rtw89_dev *rtwdev)
255 {
256 u32 val32;
257 u32 ret;
258
259 rtw8852b_pwr_sps_ana(rtwdev);
260
261 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_AFSM_WLSUS_EN |
262 B_AX_AFSM_PCIE_SUS_EN);
263 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_DIS_WLBT_PDNSUSEN_SOPC);
264 rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_DIS_WLBT_LPSEN_LOPC);
265 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APDM_HPDN);
266 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS);
267
268 ret = read_poll_timeout(rtw89_read32, val32, val32 & B_AX_RDY_SYSPWR,
269 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
270 if (ret)
271 return ret;
272
273 rtw89_write32_set(rtwdev, R_AX_AFE_LDO_CTRL, B_AX_AON_OFF_PC_EN);
274 ret = read_poll_timeout(rtw89_read32, val32, val32 & B_AX_AON_OFF_PC_EN,
275 1000, 20000, false, rtwdev, R_AX_AFE_LDO_CTRL);
276 if (ret)
277 return ret;
278
279 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_OFF_CTRL0, B_AX_C1_L1_MASK, 0x1);
280 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_OFF_CTRL0, B_AX_C3_L1_MASK, 0x3);
281 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON);
282 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC);
283
284 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFN_ONMAC),
285 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
286 if (ret)
287 return ret;
288
289 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
290 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
291 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
292 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
293
294 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
295 rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_CALIB_EN_V1);
296
297 rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3);
298
299 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL,
300 XTAL_SI_GND_SHDN_WL, XTAL_SI_GND_SHDN_WL);
301 if (ret)
302 return ret;
303
304 rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3);
305
306 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL,
307 XTAL_SI_SHDN_WL, XTAL_SI_SHDN_WL);
308 if (ret)
309 return ret;
310 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_WEI,
311 XTAL_SI_OFF_WEI);
312 if (ret)
313 return ret;
314 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_EI,
315 XTAL_SI_OFF_EI);
316 if (ret)
317 return ret;
318 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_RFC2RF);
319 if (ret)
320 return ret;
321 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_WEI,
322 XTAL_SI_PON_WEI);
323 if (ret)
324 return ret;
325 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_EI,
326 XTAL_SI_PON_EI);
327 if (ret)
328 return ret;
329 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SRAM2RFC);
330 if (ret)
331 return ret;
332 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_SRAM_CTRL, 0, XTAL_SI_SRAM_DIS);
333 if (ret)
334 return ret;
335 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_2, 0, XTAL_SI_LDO_LPS);
336 if (ret)
337 return ret;
338 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_4, 0, XTAL_SI_LPS_CAP);
339 if (ret)
340 return ret;
341
342 rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
343 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_ISO_EB2CORE);
344 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B15);
345
346 fsleep(1000);
347
348 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B14);
349 rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
350
351 if (!rtwdev->efuse.valid || rtwdev->efuse.power_k_valid)
352 goto func_en;
353
354 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_VOL_L1_MASK, 0x9);
355 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_VREFPFM_L_MASK, 0xA);
356
357 if (rtwdev->hal.cv == CHIP_CBV) {
358 rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
359 rtw89_write16_mask(rtwdev, R_AX_HCI_LDO_CTRL, B_AX_R_AX_VADJ_MASK, 0xA);
360 rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
361 }
362
363 func_en:
364 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN,
365 B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_MPDU_PROC_EN |
366 B_AX_WD_RLS_EN | B_AX_DLE_WDE_EN | B_AX_TXPKT_CTRL_EN |
367 B_AX_STA_SCH_EN | B_AX_DLE_PLE_EN | B_AX_PKT_BUF_EN |
368 B_AX_DMAC_TBL_EN | B_AX_PKT_IN_EN | B_AX_DLE_CPUIO_EN |
369 B_AX_DISPATCHER_EN | B_AX_BBRPT_EN | B_AX_MAC_SEC_EN |
370 B_AX_DMACREG_GCKEN);
371 rtw89_write32_set(rtwdev, R_AX_CMAC_FUNC_EN,
372 B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN |
373 B_AX_FORCE_CMACREG_GCKEN | B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN |
374 B_AX_PTCLTOP_EN | B_AX_SCHEDULER_EN | B_AX_TMAC_EN |
375 B_AX_RMAC_EN);
376
377 rtw89_write32_mask(rtwdev, R_AX_EECS_EESK_FUNC_SEL, B_AX_PINMUX_EESK_FUNC_SEL_MASK,
378 PINMUX_EESK_FUNC_SEL_BT_LOG);
379
380 return 0;
381 }
382
rtw8852b_pwr_off_func(struct rtw89_dev * rtwdev)383 static int rtw8852b_pwr_off_func(struct rtw89_dev *rtwdev)
384 {
385 u32 val32;
386 u32 ret;
387
388 rtw8852b_pwr_sps_ana(rtwdev);
389
390 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_RFC2RF,
391 XTAL_SI_RFC2RF);
392 if (ret)
393 return ret;
394 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_EI);
395 if (ret)
396 return ret;
397 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_WEI);
398 if (ret)
399 return ret;
400 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0, XTAL_SI_RF00);
401 if (ret)
402 return ret;
403 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0, XTAL_SI_RF10);
404 if (ret)
405 return ret;
406 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_SRAM2RFC,
407 XTAL_SI_SRAM2RFC);
408 if (ret)
409 return ret;
410 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_EI);
411 if (ret)
412 return ret;
413 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_WEI);
414 if (ret)
415 return ret;
416
417 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON);
418 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
419 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, B_AX_FEN_BB_GLB_RSTN | B_AX_FEN_BBRSTB);
420 rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3);
421
422 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SHDN_WL);
423 if (ret)
424 return ret;
425
426 rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3);
427
428 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_GND_SHDN_WL);
429 if (ret)
430 return ret;
431
432 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_OFFMAC);
433
434 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFM_OFFMAC),
435 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
436 if (ret)
437 return ret;
438
439 rtw89_write32(rtwdev, R_AX_WLLPS_CTRL, SW_LPS_OPTION);
440 rtw89_write32_set(rtwdev, R_AX_SYS_SWR_CTRL1, B_AX_SYM_CTRL_SPS_PWMFREQ);
441 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_REG_ZCDC_H_MASK, 0x3);
442 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS);
443
444 return 0;
445 }
446
rtw8852b_bb_reset_en(struct rtw89_dev * rtwdev,enum rtw89_band band,enum rtw89_phy_idx phy_idx,bool en)447 static void rtw8852b_bb_reset_en(struct rtw89_dev *rtwdev, enum rtw89_band band,
448 enum rtw89_phy_idx phy_idx, bool en)
449 {
450 if (en) {
451 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS,
452 B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx);
453 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS,
454 B_S1_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx);
455 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);
456 if (band == RTW89_BAND_2G)
457 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x0);
458 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x0);
459 } else {
460 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x1);
461 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x1);
462 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS,
463 B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx);
464 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS,
465 B_S1_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx);
466 fsleep(1);
467 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx);
468 }
469 }
470
rtw8852b_bb_reset(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)471 static void rtw8852b_bb_reset(struct rtw89_dev *rtwdev,
472 enum rtw89_phy_idx phy_idx)
473 {
474 rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON);
475 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
476 rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON);
477 rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
478 rtw8852bx_bb_reset_all(rtwdev, phy_idx);
479 rtw89_phy_write32_clr(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON);
480 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
481 rtw89_phy_write32_clr(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON);
482 rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
483 }
484
rtw8852b_set_channel(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)485 static void rtw8852b_set_channel(struct rtw89_dev *rtwdev,
486 const struct rtw89_chan *chan,
487 enum rtw89_mac_idx mac_idx,
488 enum rtw89_phy_idx phy_idx)
489 {
490 rtw8852bx_set_channel_mac(rtwdev, chan, mac_idx);
491 rtw8852bx_set_channel_bb(rtwdev, chan, phy_idx);
492 rtw8852b_set_channel_rf(rtwdev, chan, phy_idx);
493 }
494
rtw8852b_tssi_cont_en(struct rtw89_dev * rtwdev,bool en,enum rtw89_rf_path path)495 static void rtw8852b_tssi_cont_en(struct rtw89_dev *rtwdev, bool en,
496 enum rtw89_rf_path path)
497 {
498 static const u32 tssi_trk[2] = {R_P0_TSSI_TRK, R_P1_TSSI_TRK};
499 static const u32 ctrl_bbrst[2] = {R_P0_TXPW_RSTB, R_P1_TXPW_RSTB};
500
501 if (en) {
502 rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], B_P0_TXPW_RSTB_MANON, 0x0);
503 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], B_P0_TSSI_TRK_EN, 0x0);
504 } else {
505 rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], B_P0_TXPW_RSTB_MANON, 0x1);
506 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], B_P0_TSSI_TRK_EN, 0x1);
507 }
508 }
509
rtw8852b_tssi_cont_en_phyidx(struct rtw89_dev * rtwdev,bool en,u8 phy_idx)510 static void rtw8852b_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en,
511 u8 phy_idx)
512 {
513 if (!rtwdev->dbcc_en) {
514 rtw8852b_tssi_cont_en(rtwdev, en, RF_PATH_A);
515 rtw8852b_tssi_cont_en(rtwdev, en, RF_PATH_B);
516 } else {
517 if (phy_idx == RTW89_PHY_0)
518 rtw8852b_tssi_cont_en(rtwdev, en, RF_PATH_A);
519 else
520 rtw8852b_tssi_cont_en(rtwdev, en, RF_PATH_B);
521 }
522 }
523
rtw8852b_adc_en(struct rtw89_dev * rtwdev,bool en)524 static void rtw8852b_adc_en(struct rtw89_dev *rtwdev, bool en)
525 {
526 if (en)
527 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0x0);
528 else
529 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0xf);
530 }
531
rtw8852b_set_channel_help(struct rtw89_dev * rtwdev,bool enter,struct rtw89_channel_help_params * p,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)532 static void rtw8852b_set_channel_help(struct rtw89_dev *rtwdev, bool enter,
533 struct rtw89_channel_help_params *p,
534 const struct rtw89_chan *chan,
535 enum rtw89_mac_idx mac_idx,
536 enum rtw89_phy_idx phy_idx)
537 {
538 if (enter) {
539 rtw89_chip_stop_sch_tx(rtwdev, RTW89_MAC_0, &p->tx_en, RTW89_SCH_TX_SEL_ALL);
540 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false);
541 rtw8852b_tssi_cont_en_phyidx(rtwdev, false, RTW89_PHY_0);
542 rtw8852b_adc_en(rtwdev, false);
543 fsleep(40);
544 rtw8852b_bb_reset_en(rtwdev, chan->band_type, phy_idx, false);
545 } else {
546 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true);
547 rtw8852b_adc_en(rtwdev, true);
548 rtw8852b_tssi_cont_en_phyidx(rtwdev, true, RTW89_PHY_0);
549 rtw8852b_bb_reset_en(rtwdev, chan->band_type, phy_idx, true);
550 rtw89_chip_resume_sch_tx(rtwdev, RTW89_MAC_0, p->tx_en);
551 }
552 }
553
rtw8852b_rfk_init(struct rtw89_dev * rtwdev)554 static void rtw8852b_rfk_init(struct rtw89_dev *rtwdev)
555 {
556 rtwdev->is_tssi_mode[RF_PATH_A] = false;
557 rtwdev->is_tssi_mode[RF_PATH_B] = false;
558
559 rtw8852b_dpk_init(rtwdev);
560 rtw8852b_rck(rtwdev);
561 rtw8852b_dack(rtwdev, RTW89_CHANCTX_0);
562 rtw8852b_rx_dck(rtwdev, RTW89_PHY_0, RTW89_CHANCTX_0);
563 }
564
rtw8852b_rfk_channel(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)565 static void rtw8852b_rfk_channel(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
566 {
567 enum rtw89_chanctx_idx chanctx_idx = rtwvif->chanctx_idx;
568 enum rtw89_phy_idx phy_idx = rtwvif->phy_idx;
569
570 rtw8852b_rx_dck(rtwdev, phy_idx, chanctx_idx);
571 rtw8852b_iqk(rtwdev, phy_idx, chanctx_idx);
572 rtw8852b_tssi(rtwdev, phy_idx, true, chanctx_idx);
573 rtw8852b_dpk(rtwdev, phy_idx, chanctx_idx);
574 }
575
rtw8852b_rfk_band_changed(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan)576 static void rtw8852b_rfk_band_changed(struct rtw89_dev *rtwdev,
577 enum rtw89_phy_idx phy_idx,
578 const struct rtw89_chan *chan)
579 {
580 rtw8852b_tssi_scan(rtwdev, phy_idx, chan);
581 }
582
rtw8852b_rfk_scan(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,bool start)583 static void rtw8852b_rfk_scan(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
584 bool start)
585 {
586 rtw8852b_wifi_scan_notify(rtwdev, start, rtwvif->phy_idx, rtwvif->chanctx_idx);
587 }
588
rtw8852b_rfk_track(struct rtw89_dev * rtwdev)589 static void rtw8852b_rfk_track(struct rtw89_dev *rtwdev)
590 {
591 rtw8852b_dpk_track(rtwdev);
592 }
593
rtw8852b_btc_set_rfe(struct rtw89_dev * rtwdev)594 static void rtw8852b_btc_set_rfe(struct rtw89_dev *rtwdev)
595 {
596 const struct rtw89_btc_ver *ver = rtwdev->btc.ver;
597 union rtw89_btc_module_info *md = &rtwdev->btc.mdinfo;
598
599 if (ver->fcxinit == 7) {
600 md->md_v7.rfe_type = rtwdev->efuse.rfe_type;
601 md->md_v7.kt_ver = rtwdev->hal.cv;
602 md->md_v7.bt_solo = 0;
603 md->md_v7.switch_type = BTC_SWITCH_INTERNAL;
604
605 if (md->md_v7.rfe_type > 0)
606 md->md_v7.ant.num = (md->md_v7.rfe_type % 2 ? 2 : 3);
607 else
608 md->md_v7.ant.num = 2;
609
610 md->md_v7.ant.diversity = 0;
611 md->md_v7.ant.isolation = 10;
612
613 if (md->md_v7.ant.num == 3) {
614 md->md_v7.ant.type = BTC_ANT_DEDICATED;
615 md->md_v7.bt_pos = BTC_BT_ALONE;
616 } else {
617 md->md_v7.ant.type = BTC_ANT_SHARED;
618 md->md_v7.bt_pos = BTC_BT_BTG;
619 }
620 rtwdev->btc.btg_pos = md->md_v7.ant.btg_pos;
621 rtwdev->btc.ant_type = md->md_v7.ant.type;
622 } else {
623 md->md.rfe_type = rtwdev->efuse.rfe_type;
624 md->md.cv = rtwdev->hal.cv;
625 md->md.bt_solo = 0;
626 md->md.switch_type = BTC_SWITCH_INTERNAL;
627
628 if (md->md.rfe_type > 0)
629 md->md.ant.num = (md->md.rfe_type % 2 ? 2 : 3);
630 else
631 md->md.ant.num = 2;
632
633 md->md.ant.diversity = 0;
634 md->md.ant.isolation = 10;
635
636 if (md->md.ant.num == 3) {
637 md->md.ant.type = BTC_ANT_DEDICATED;
638 md->md.bt_pos = BTC_BT_ALONE;
639 } else {
640 md->md.ant.type = BTC_ANT_SHARED;
641 md->md.bt_pos = BTC_BT_BTG;
642 }
643 rtwdev->btc.btg_pos = md->md.ant.btg_pos;
644 rtwdev->btc.ant_type = md->md.ant.type;
645 }
646 }
647
648 union rtw8852b_btc_wl_txpwr_ctrl {
649 u32 txpwr_val;
650 struct {
651 union {
652 u16 ctrl_all_time;
653 struct {
654 s16 data:9;
655 u16 rsvd:6;
656 u16 flag:1;
657 } all_time;
658 };
659 union {
660 u16 ctrl_gnt_bt;
661 struct {
662 s16 data:9;
663 u16 rsvd:7;
664 } gnt_bt;
665 };
666 };
667 } __packed;
668
669 static void
rtw8852b_btc_set_wl_txpwr_ctrl(struct rtw89_dev * rtwdev,u32 txpwr_val)670 rtw8852b_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val)
671 {
672 union rtw8852b_btc_wl_txpwr_ctrl arg = { .txpwr_val = txpwr_val };
673 s32 val;
674
675 #define __write_ctrl(_reg, _msk, _val, _en, _cond) \
676 do { \
677 u32 _wrt = FIELD_PREP(_msk, _val); \
678 BUILD_BUG_ON(!!(_msk & _en)); \
679 if (_cond) \
680 _wrt |= _en; \
681 else \
682 _wrt &= ~_en; \
683 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, _reg, \
684 _msk | _en, _wrt); \
685 } while (0)
686
687 switch (arg.ctrl_all_time) {
688 case 0xffff:
689 val = 0;
690 break;
691 default:
692 val = arg.all_time.data;
693 break;
694 }
695
696 __write_ctrl(R_AX_PWR_RATE_CTRL, B_AX_FORCE_PWR_BY_RATE_VALUE_MASK,
697 val, B_AX_FORCE_PWR_BY_RATE_EN,
698 arg.ctrl_all_time != 0xffff);
699
700 switch (arg.ctrl_gnt_bt) {
701 case 0xffff:
702 val = 0;
703 break;
704 default:
705 val = arg.gnt_bt.data;
706 break;
707 }
708
709 __write_ctrl(R_AX_PWR_COEXT_CTRL, B_AX_TXAGC_BT_MASK, val,
710 B_AX_TXAGC_BT_EN, arg.ctrl_gnt_bt != 0xffff);
711
712 #undef __write_ctrl
713 }
714
715 static const struct rtw89_chip_ops rtw8852b_chip_ops = {
716 .enable_bb_rf = rtw8852bx_mac_enable_bb_rf,
717 .disable_bb_rf = rtw8852bx_mac_disable_bb_rf,
718 .bb_preinit = NULL,
719 .bb_postinit = NULL,
720 .bb_reset = rtw8852b_bb_reset,
721 .bb_sethw = rtw8852bx_bb_sethw,
722 .read_rf = rtw89_phy_read_rf_v1,
723 .write_rf = rtw89_phy_write_rf_v1,
724 .set_channel = rtw8852b_set_channel,
725 .set_channel_help = rtw8852b_set_channel_help,
726 .read_efuse = rtw8852bx_read_efuse,
727 .read_phycap = rtw8852bx_read_phycap,
728 .fem_setup = NULL,
729 .rfe_gpio = NULL,
730 .rfk_hw_init = NULL,
731 .rfk_init = rtw8852b_rfk_init,
732 .rfk_init_late = NULL,
733 .rfk_channel = rtw8852b_rfk_channel,
734 .rfk_band_changed = rtw8852b_rfk_band_changed,
735 .rfk_scan = rtw8852b_rfk_scan,
736 .rfk_track = rtw8852b_rfk_track,
737 .power_trim = rtw8852bx_power_trim,
738 .set_txpwr = rtw8852bx_set_txpwr,
739 .set_txpwr_ctrl = rtw8852bx_set_txpwr_ctrl,
740 .init_txpwr_unit = rtw8852bx_init_txpwr_unit,
741 .get_thermal = rtw8852bx_get_thermal,
742 .ctrl_btg_bt_rx = rtw8852bx_ctrl_btg_bt_rx,
743 .query_ppdu = rtw8852bx_query_ppdu,
744 .convert_rpl_to_rssi = rtw8852bx_convert_rpl_to_rssi,
745 .ctrl_nbtg_bt_tx = rtw8852bx_ctrl_nbtg_bt_tx,
746 .cfg_txrx_path = rtw8852bx_bb_cfg_txrx_path,
747 .set_txpwr_ul_tb_offset = rtw8852bx_set_txpwr_ul_tb_offset,
748 .digital_pwr_comp = NULL,
749 .pwr_on_func = rtw8852b_pwr_on_func,
750 .pwr_off_func = rtw8852b_pwr_off_func,
751 .query_rxdesc = rtw89_core_query_rxdesc,
752 .fill_txdesc = rtw89_core_fill_txdesc,
753 .fill_txdesc_fwcmd = rtw89_core_fill_txdesc,
754 .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path,
755 .mac_cfg_gnt = rtw89_mac_cfg_gnt,
756 .stop_sch_tx = rtw89_mac_stop_sch_tx,
757 .resume_sch_tx = rtw89_mac_resume_sch_tx,
758 .h2c_dctl_sec_cam = NULL,
759 .h2c_default_cmac_tbl = rtw89_fw_h2c_default_cmac_tbl,
760 .h2c_assoc_cmac_tbl = rtw89_fw_h2c_assoc_cmac_tbl,
761 .h2c_ampdu_cmac_tbl = NULL,
762 .h2c_default_dmac_tbl = NULL,
763 .h2c_update_beacon = rtw89_fw_h2c_update_beacon,
764 .h2c_ba_cam = rtw89_fw_h2c_ba_cam,
765
766 .btc_set_rfe = rtw8852b_btc_set_rfe,
767 .btc_init_cfg = rtw8852bx_btc_init_cfg,
768 .btc_set_wl_pri = rtw8852bx_btc_set_wl_pri,
769 .btc_set_wl_txpwr_ctrl = rtw8852b_btc_set_wl_txpwr_ctrl,
770 .btc_get_bt_rssi = rtw8852bx_btc_get_bt_rssi,
771 .btc_update_bt_cnt = rtw8852bx_btc_update_bt_cnt,
772 .btc_wl_s1_standby = rtw8852bx_btc_wl_s1_standby,
773 .btc_set_wl_rx_gain = rtw8852bx_btc_set_wl_rx_gain,
774 .btc_set_policy = rtw89_btc_set_policy_v1,
775 };
776
777 #ifdef CONFIG_PM
778 static const struct wiphy_wowlan_support rtw_wowlan_stub_8852b = {
779 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT,
780 .n_patterns = RTW89_MAX_PATTERN_NUM,
781 .pattern_max_len = RTW89_MAX_PATTERN_SIZE,
782 .pattern_min_len = 1,
783 };
784 #endif
785
786 const struct rtw89_chip_info rtw8852b_chip_info = {
787 .chip_id = RTL8852B,
788 .chip_gen = RTW89_CHIP_AX,
789 .ops = &rtw8852b_chip_ops,
790 .mac_def = &rtw89_mac_gen_ax,
791 .phy_def = &rtw89_phy_gen_ax,
792 .fw_basename = RTW8852B_FW_BASENAME,
793 .fw_format_max = RTW8852B_FW_FORMAT_MAX,
794 .try_ce_fw = true,
795 .bbmcu_nr = 0,
796 .needed_fw_elms = 0,
797 .fifo_size = 196608,
798 .small_fifo_size = true,
799 .dle_scc_rsvd_size = 98304,
800 .max_amsdu_limit = 5000,
801 .dis_2g_40m_ul_ofdma = true,
802 .rsvd_ple_ofst = 0x2f800,
803 .hfc_param_ini = rtw8852b_hfc_param_ini_pcie,
804 .dle_mem = rtw8852b_dle_mem_pcie,
805 .wde_qempty_acq_grpnum = 4,
806 .wde_qempty_mgq_grpsel = 4,
807 .rf_base_addr = {0xe000, 0xf000},
808 .pwr_on_seq = NULL,
809 .pwr_off_seq = NULL,
810 .bb_table = &rtw89_8852b_phy_bb_table,
811 .bb_gain_table = &rtw89_8852b_phy_bb_gain_table,
812 .rf_table = {&rtw89_8852b_phy_radioa_table,
813 &rtw89_8852b_phy_radiob_table,},
814 .nctl_table = &rtw89_8852b_phy_nctl_table,
815 .nctl_post_table = NULL,
816 .dflt_parms = &rtw89_8852b_dflt_parms,
817 .rfe_parms_conf = NULL,
818 .txpwr_factor_rf = 2,
819 .txpwr_factor_mac = 1,
820 .dig_table = NULL,
821 .dig_regs = &rtw8852b_dig_regs,
822 .tssi_dbw_table = NULL,
823 .support_macid_num = RTW89_MAX_MAC_ID_NUM,
824 .support_link_num = 0,
825 .support_chanctx_num = 0,
826 .support_rnr = false,
827 .support_bands = BIT(NL80211_BAND_2GHZ) |
828 BIT(NL80211_BAND_5GHZ),
829 .support_bandwidths = BIT(NL80211_CHAN_WIDTH_20) |
830 BIT(NL80211_CHAN_WIDTH_40) |
831 BIT(NL80211_CHAN_WIDTH_80),
832 .support_unii4 = true,
833 .ul_tb_waveform_ctrl = true,
834 .ul_tb_pwr_diff = false,
835 .hw_sec_hdr = false,
836 .hw_mgmt_tx_encrypt = false,
837 .rf_path_num = 2,
838 .tx_nss = 2,
839 .rx_nss = 2,
840 .acam_num = 128,
841 .bcam_num = 10,
842 .scam_num = 128,
843 .bacam_num = 2,
844 .bacam_dynamic_num = 4,
845 .bacam_ver = RTW89_BACAM_V0,
846 .ppdu_max_usr = 4,
847 .sec_ctrl_efuse_size = 4,
848 .physical_efuse_size = 1216,
849 .logical_efuse_size = 2048,
850 .limit_efuse_size = 1280,
851 .dav_phy_efuse_size = 96,
852 .dav_log_efuse_size = 16,
853 .efuse_blocks = NULL,
854 .phycap_addr = 0x580,
855 .phycap_size = 128,
856 .para_ver = 0,
857 .wlcx_desired = 0x05050000,
858 .btcx_desired = 0x5,
859 .scbd = 0x1,
860 .mailbox = 0x1,
861
862 .afh_guard_ch = 6,
863 .wl_rssi_thres = rtw89_btc_8852b_wl_rssi_thres,
864 .bt_rssi_thres = rtw89_btc_8852b_bt_rssi_thres,
865 .rssi_tol = 2,
866 .mon_reg_num = ARRAY_SIZE(rtw89_btc_8852b_mon_reg),
867 .mon_reg = rtw89_btc_8852b_mon_reg,
868 .rf_para_ulink_num = ARRAY_SIZE(rtw89_btc_8852b_rf_ul),
869 .rf_para_ulink = rtw89_btc_8852b_rf_ul,
870 .rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8852b_rf_dl),
871 .rf_para_dlink = rtw89_btc_8852b_rf_dl,
872 .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) |
873 BIT(RTW89_PS_MODE_CLK_GATED) |
874 BIT(RTW89_PS_MODE_PWR_GATED),
875 .low_power_hci_modes = 0,
876 .h2c_cctl_func_id = H2C_FUNC_MAC_CCTLINFO_UD,
877 .hci_func_en_addr = R_AX_HCI_FUNC_EN,
878 .h2c_desc_size = sizeof(struct rtw89_txwd_body),
879 .txwd_body_size = sizeof(struct rtw89_txwd_body),
880 .txwd_info_size = sizeof(struct rtw89_txwd_info),
881 .h2c_ctrl_reg = R_AX_H2CREG_CTRL,
882 .h2c_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_H2C_DEQ_CNT_MASK >> 8},
883 .h2c_regs = rtw8852b_h2c_regs,
884 .c2h_ctrl_reg = R_AX_C2HREG_CTRL,
885 .c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8},
886 .c2h_regs = rtw8852b_c2h_regs,
887 .page_regs = &rtw8852b_page_regs,
888 .wow_reason_reg = rtw8852b_wow_wakeup_regs,
889 .cfo_src_fd = true,
890 .cfo_hw_comp = true,
891 .dcfo_comp = &rtw8852b_dcfo_comp,
892 .dcfo_comp_sft = 10,
893 .imr_info = &rtw8852b_imr_info,
894 .imr_dmac_table = NULL,
895 .imr_cmac_table = NULL,
896 .rrsr_cfgs = &rtw8852b_rrsr_cfgs,
897 .bss_clr_vld = {R_BSS_CLR_MAP_V1, B_BSS_CLR_MAP_VLD0},
898 .bss_clr_map_reg = R_BSS_CLR_MAP_V1,
899 .rfkill_init = &rtw8852b_rfkill_regs,
900 .rfkill_get = {R_AX_GPIO_EXT_CTRL, B_AX_GPIO_IN_9},
901 .dma_ch_mask = BIT(RTW89_DMA_ACH4) | BIT(RTW89_DMA_ACH5) |
902 BIT(RTW89_DMA_ACH6) | BIT(RTW89_DMA_ACH7) |
903 BIT(RTW89_DMA_B1MG) | BIT(RTW89_DMA_B1HI),
904 .edcca_regs = &rtw8852b_edcca_regs,
905 #ifdef CONFIG_PM
906 .wowlan_stub = &rtw_wowlan_stub_8852b,
907 #endif
908 .xtal_info = NULL,
909 };
910 EXPORT_SYMBOL(rtw8852b_chip_info);
911
912 MODULE_FIRMWARE(RTW8852B_MODULE_FIRMWARE);
913 MODULE_AUTHOR("Realtek Corporation");
914 MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852B driver");
915 MODULE_LICENSE("Dual BSD/GPL");
916