1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
3 */
4
5 #include <linux/module.h>
6 #include "main.h"
7 #include "coex.h"
8 #include "fw.h"
9 #include "tx.h"
10 #include "rx.h"
11 #include "phy.h"
12 #include "rtw8822b.h"
13 #include "rtw8822b_table.h"
14 #include "mac.h"
15 #include "reg.h"
16 #include "debug.h"
17 #include "bf.h"
18 #include "regd.h"
19
20 static void rtw8822b_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path,
21 u8 rx_path, bool is_tx2_path);
22
rtw8822be_efuse_parsing(struct rtw_efuse * efuse,struct rtw8822b_efuse * map)23 static void rtw8822be_efuse_parsing(struct rtw_efuse *efuse,
24 struct rtw8822b_efuse *map)
25 {
26 ether_addr_copy(efuse->addr, map->e.mac_addr);
27 }
28
rtw8822bu_efuse_parsing(struct rtw_efuse * efuse,struct rtw8822b_efuse * map)29 static void rtw8822bu_efuse_parsing(struct rtw_efuse *efuse,
30 struct rtw8822b_efuse *map)
31 {
32 ether_addr_copy(efuse->addr, map->u.mac_addr);
33 }
34
rtw8822bs_efuse_parsing(struct rtw_efuse * efuse,struct rtw8822b_efuse * map)35 static void rtw8822bs_efuse_parsing(struct rtw_efuse *efuse,
36 struct rtw8822b_efuse *map)
37 {
38 ether_addr_copy(efuse->addr, map->s.mac_addr);
39 }
40
rtw8822b_read_efuse(struct rtw_dev * rtwdev,u8 * log_map)41 static int rtw8822b_read_efuse(struct rtw_dev *rtwdev, u8 *log_map)
42 {
43 struct rtw_efuse *efuse = &rtwdev->efuse;
44 struct rtw8822b_efuse *map;
45 int i;
46
47 map = (struct rtw8822b_efuse *)log_map;
48
49 efuse->usb_mode_switch = u8_get_bits(map->usb_mode, BIT(7));
50 efuse->rfe_option = map->rfe_option;
51 efuse->rf_board_option = map->rf_board_option;
52 efuse->crystal_cap = map->xtal_k;
53 efuse->pa_type_2g = map->pa_type;
54 efuse->pa_type_5g = map->pa_type;
55 efuse->lna_type_2g = map->lna_type_2g[0];
56 efuse->lna_type_5g = map->lna_type_5g[0];
57 efuse->channel_plan = map->channel_plan;
58 efuse->country_code[0] = map->country_code[0];
59 efuse->country_code[1] = map->country_code[1];
60 efuse->bt_setting = map->rf_bt_setting;
61 efuse->regd = map->rf_board_option & 0x7;
62 efuse->thermal_meter[RF_PATH_A] = map->thermal_meter;
63 efuse->thermal_meter_k = map->thermal_meter;
64
65 for (i = 0; i < 4; i++)
66 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i];
67
68 switch (rtw_hci_type(rtwdev)) {
69 case RTW_HCI_TYPE_PCIE:
70 rtw8822be_efuse_parsing(efuse, map);
71 break;
72 case RTW_HCI_TYPE_USB:
73 rtw8822bu_efuse_parsing(efuse, map);
74 break;
75 case RTW_HCI_TYPE_SDIO:
76 rtw8822bs_efuse_parsing(efuse, map);
77 break;
78 default:
79 /* unsupported now */
80 return -ENOTSUPP;
81 }
82
83 return 0;
84 }
85
rtw8822b_phy_rfe_init(struct rtw_dev * rtwdev)86 static void rtw8822b_phy_rfe_init(struct rtw_dev *rtwdev)
87 {
88 /* chip top mux */
89 rtw_write32_mask(rtwdev, 0x64, BIT(29) | BIT(28), 0x3);
90 rtw_write32_mask(rtwdev, 0x4c, BIT(26) | BIT(25), 0x0);
91 rtw_write32_mask(rtwdev, 0x40, BIT(2), 0x1);
92
93 /* from s0 or s1 */
94 rtw_write32_mask(rtwdev, 0x1990, 0x3f, 0x30);
95 rtw_write32_mask(rtwdev, 0x1990, (BIT(11) | BIT(10)), 0x3);
96
97 /* input or output */
98 rtw_write32_mask(rtwdev, 0x974, 0x3f, 0x3f);
99 rtw_write32_mask(rtwdev, 0x974, (BIT(11) | BIT(10)), 0x3);
100 }
101
102 #define RTW_TXSCALE_SIZE 37
103 static const u32 rtw8822b_txscale_tbl[RTW_TXSCALE_SIZE] = {
104 0x081, 0x088, 0x090, 0x099, 0x0a2, 0x0ac, 0x0b6, 0x0c0, 0x0cc, 0x0d8,
105 0x0e5, 0x0f2, 0x101, 0x110, 0x120, 0x131, 0x143, 0x156, 0x16a, 0x180,
106 0x197, 0x1af, 0x1c8, 0x1e3, 0x200, 0x21e, 0x23e, 0x261, 0x285, 0x2ab,
107 0x2d3, 0x2fe, 0x32b, 0x35c, 0x38e, 0x3c4, 0x3fe
108 };
109
rtw8822b_get_swing_index(struct rtw_dev * rtwdev)110 static u8 rtw8822b_get_swing_index(struct rtw_dev *rtwdev)
111 {
112 u8 i = 0;
113 u32 swing, table_value;
114
115 swing = rtw_read32_mask(rtwdev, 0xc1c, 0xffe00000);
116 for (i = 0; i < RTW_TXSCALE_SIZE; i++) {
117 table_value = rtw8822b_txscale_tbl[i];
118 if (swing == table_value)
119 break;
120 }
121
122 return i;
123 }
124
rtw8822b_pwrtrack_init(struct rtw_dev * rtwdev)125 static void rtw8822b_pwrtrack_init(struct rtw_dev *rtwdev)
126 {
127 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
128 u8 swing_idx = rtw8822b_get_swing_index(rtwdev);
129 u8 path;
130
131 if (swing_idx >= RTW_TXSCALE_SIZE)
132 dm_info->default_ofdm_index = 24;
133 else
134 dm_info->default_ofdm_index = swing_idx;
135
136 for (path = RF_PATH_A; path < rtwdev->hal.rf_path_num; path++) {
137 ewma_thermal_init(&dm_info->avg_thermal[path]);
138 dm_info->delta_power_index[path] = 0;
139 }
140 dm_info->pwr_trk_triggered = false;
141 dm_info->pwr_trk_init_trigger = true;
142 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k;
143 }
144
rtw8822b_phy_bf_init(struct rtw_dev * rtwdev)145 static void rtw8822b_phy_bf_init(struct rtw_dev *rtwdev)
146 {
147 rtw_bf_phy_init(rtwdev);
148 /* Grouping bitmap parameters */
149 rtw_write32(rtwdev, 0x1C94, 0xAFFFAFFF);
150 }
151
rtw8822b_phy_set_param(struct rtw_dev * rtwdev)152 static void rtw8822b_phy_set_param(struct rtw_dev *rtwdev)
153 {
154 struct rtw_hal *hal = &rtwdev->hal;
155 u8 crystal_cap;
156 bool is_tx2_path;
157
158 /* power on BB/RF domain */
159 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN,
160 BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST);
161 rtw_write8_set(rtwdev, REG_RF_CTRL,
162 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB);
163 rtw_write32_set(rtwdev, REG_WLRF1, BIT_WLRF1_BBRF_EN);
164
165 /* pre init before header files config */
166 rtw_write32_clr(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST);
167
168 rtw_phy_load_tables(rtwdev);
169
170 crystal_cap = rtwdev->efuse.crystal_cap & 0x3F;
171 rtw_write32_mask(rtwdev, 0x24, 0x7e000000, crystal_cap);
172 rtw_write32_mask(rtwdev, 0x28, 0x7e, crystal_cap);
173
174 /* post init after header files config */
175 rtw_write32_set(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST);
176
177 is_tx2_path = false;
178 rtw8822b_config_trx_mode(rtwdev, hal->antenna_tx, hal->antenna_rx,
179 is_tx2_path);
180 rtw_phy_init(rtwdev);
181
182 rtw8822b_phy_rfe_init(rtwdev);
183 rtw8822b_pwrtrack_init(rtwdev);
184
185 rtw8822b_phy_bf_init(rtwdev);
186 }
187
188 #define WLAN_SLOT_TIME 0x09
189 #define WLAN_PIFS_TIME 0x19
190 #define WLAN_SIFS_CCK_CONT_TX 0xA
191 #define WLAN_SIFS_OFDM_CONT_TX 0xE
192 #define WLAN_SIFS_CCK_TRX 0x10
193 #define WLAN_SIFS_OFDM_TRX 0x10
194 #define WLAN_VO_TXOP_LIMIT 0x186 /* unit : 32us */
195 #define WLAN_VI_TXOP_LIMIT 0x3BC /* unit : 32us */
196 #define WLAN_RDG_NAV 0x05
197 #define WLAN_TXOP_NAV 0x1B
198 #define WLAN_CCK_RX_TSF 0x30
199 #define WLAN_OFDM_RX_TSF 0x30
200 #define WLAN_TBTT_PROHIBIT 0x04 /* unit : 32us */
201 #define WLAN_TBTT_HOLD_TIME 0x064 /* unit : 32us */
202 #define WLAN_DRV_EARLY_INT 0x04
203 #define WLAN_BCN_DMA_TIME 0x02
204
205 #define WLAN_RX_FILTER0 0x0FFFFFFF
206 #define WLAN_RX_FILTER2 0xFFFF
207 #define WLAN_RCR_CFG 0xE400220E
208 #define WLAN_RXPKT_MAX_SZ 12288
209 #define WLAN_RXPKT_MAX_SZ_512 (WLAN_RXPKT_MAX_SZ >> 9)
210
211 #define WLAN_AMPDU_MAX_TIME 0x70
212 #define WLAN_RTS_LEN_TH 0xFF
213 #define WLAN_RTS_TX_TIME_TH 0x08
214 #define WLAN_MAX_AGG_PKT_LIMIT 0x20
215 #define WLAN_RTS_MAX_AGG_PKT_LIMIT 0x20
216 #define FAST_EDCA_VO_TH 0x06
217 #define FAST_EDCA_VI_TH 0x06
218 #define FAST_EDCA_BE_TH 0x06
219 #define FAST_EDCA_BK_TH 0x06
220 #define WLAN_BAR_RETRY_LIMIT 0x01
221 #define WLAN_RA_TRY_RATE_AGG_LIMIT 0x08
222
223 #define WLAN_TX_FUNC_CFG1 0x30
224 #define WLAN_TX_FUNC_CFG2 0x30
225 #define WLAN_MAC_OPT_NORM_FUNC1 0x98
226 #define WLAN_MAC_OPT_LB_FUNC1 0x80
227 #define WLAN_MAC_OPT_FUNC2 0xb0810041
228
229 #define WLAN_SIFS_CFG (WLAN_SIFS_CCK_CONT_TX | \
230 (WLAN_SIFS_OFDM_CONT_TX << BIT_SHIFT_SIFS_OFDM_CTX) | \
231 (WLAN_SIFS_CCK_TRX << BIT_SHIFT_SIFS_CCK_TRX) | \
232 (WLAN_SIFS_OFDM_TRX << BIT_SHIFT_SIFS_OFDM_TRX))
233
234 #define WLAN_TBTT_TIME (WLAN_TBTT_PROHIBIT |\
235 (WLAN_TBTT_HOLD_TIME << BIT_SHIFT_TBTT_HOLD_TIME_AP))
236
237 #define WLAN_NAV_CFG (WLAN_RDG_NAV | (WLAN_TXOP_NAV << 16))
238 #define WLAN_RX_TSF_CFG (WLAN_CCK_RX_TSF | (WLAN_OFDM_RX_TSF) << 8)
239
rtw8822b_mac_init(struct rtw_dev * rtwdev)240 static int rtw8822b_mac_init(struct rtw_dev *rtwdev)
241 {
242 u32 value32;
243
244 /* protocol configuration */
245 rtw_write8_clr(rtwdev, REG_SW_AMPDU_BURST_MODE_CTRL, BIT_PRE_TX_CMD);
246 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME);
247 rtw_write8_set(rtwdev, REG_TX_HANG_CTRL, BIT_EN_EOF_V1);
248 value32 = WLAN_RTS_LEN_TH | (WLAN_RTS_TX_TIME_TH << 8) |
249 (WLAN_MAX_AGG_PKT_LIMIT << 16) |
250 (WLAN_RTS_MAX_AGG_PKT_LIMIT << 24);
251 rtw_write32(rtwdev, REG_PROT_MODE_CTRL, value32);
252 rtw_write16(rtwdev, REG_BAR_MODE_CTRL + 2,
253 WLAN_BAR_RETRY_LIMIT | WLAN_RA_TRY_RATE_AGG_LIMIT << 8);
254 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING, FAST_EDCA_VO_TH);
255 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING + 2, FAST_EDCA_VI_TH);
256 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING, FAST_EDCA_BE_TH);
257 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING + 2, FAST_EDCA_BK_TH);
258 /* EDCA configuration */
259 rtw_write8_clr(rtwdev, REG_TIMER0_SRC_SEL, BIT_TSFT_SEL_TIMER0);
260 rtw_write16(rtwdev, REG_TXPAUSE, 0x0000);
261 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME);
262 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_TIME);
263 rtw_write32(rtwdev, REG_SIFS, WLAN_SIFS_CFG);
264 rtw_write16(rtwdev, REG_EDCA_VO_PARAM + 2, WLAN_VO_TXOP_LIMIT);
265 rtw_write16(rtwdev, REG_EDCA_VI_PARAM + 2, WLAN_VI_TXOP_LIMIT);
266 rtw_write32(rtwdev, REG_RD_NAV_NXT, WLAN_NAV_CFG);
267 rtw_write16(rtwdev, REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG);
268 /* Set beacon cotnrol - enable TSF and other related functions */
269 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
270 /* Set send beacon related registers */
271 rtw_write32(rtwdev, REG_TBTT_PROHIBIT, WLAN_TBTT_TIME);
272 rtw_write8(rtwdev, REG_DRVERLYINT, WLAN_DRV_EARLY_INT);
273 rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME);
274 rtw_write8_clr(rtwdev, REG_TX_PTCL_CTRL + 1, BIT_SIFS_BK_EN >> 8);
275 /* WMAC configuration */
276 rtw_write32(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0);
277 rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2);
278 rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG);
279 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512);
280 rtw_write8(rtwdev, REG_TCR + 2, WLAN_TX_FUNC_CFG2);
281 rtw_write8(rtwdev, REG_TCR + 1, WLAN_TX_FUNC_CFG1);
282 rtw_write32(rtwdev, REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2);
283 rtw_write8(rtwdev, REG_WMAC_OPTION_FUNCTION + 4, WLAN_MAC_OPT_NORM_FUNC1);
284 rtw_write8_set(rtwdev, REG_SND_PTCL_CTRL,
285 BIT_DIS_CHK_VHTSIGB_CRC);
286
287 return 0;
288 }
289
rtw8822b_set_channel_rfe_efem(struct rtw_dev * rtwdev,u8 channel)290 static void rtw8822b_set_channel_rfe_efem(struct rtw_dev *rtwdev, u8 channel)
291 {
292 struct rtw_hal *hal = &rtwdev->hal;
293
294 if (IS_CH_2G_BAND(channel)) {
295 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x705770);
296 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x57);
297 rtw_write32s_mask(rtwdev, REG_RFECTL, BIT(4), 0);
298 } else {
299 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x177517);
300 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x75);
301 rtw_write32s_mask(rtwdev, REG_RFECTL, BIT(5), 0);
302 }
303
304 rtw_write32s_mask(rtwdev, REG_RFEINV, BIT(11) | BIT(10) | 0x3f, 0x0);
305
306 if (hal->antenna_rx == BB_PATH_AB ||
307 hal->antenna_tx == BB_PATH_AB) {
308 /* 2TX or 2RX */
309 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa501);
310 } else if (hal->antenna_rx == hal->antenna_tx) {
311 /* TXA+RXA or TXB+RXB */
312 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa500);
313 } else {
314 /* TXB+RXA or TXA+RXB */
315 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa005);
316 }
317 }
318
rtw8822b_set_channel_rfe_ifem(struct rtw_dev * rtwdev,u8 channel)319 static void rtw8822b_set_channel_rfe_ifem(struct rtw_dev *rtwdev, u8 channel)
320 {
321 struct rtw_hal *hal = &rtwdev->hal;
322
323 if (IS_CH_2G_BAND(channel)) {
324 /* signal source */
325 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x745774);
326 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x57);
327 } else {
328 /* signal source */
329 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x477547);
330 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x75);
331 }
332
333 rtw_write32s_mask(rtwdev, REG_RFEINV, BIT(11) | BIT(10) | 0x3f, 0x0);
334
335 if (IS_CH_2G_BAND(channel)) {
336 if (hal->antenna_rx == BB_PATH_AB ||
337 hal->antenna_tx == BB_PATH_AB) {
338 /* 2TX or 2RX */
339 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa501);
340 } else if (hal->antenna_rx == hal->antenna_tx) {
341 /* TXA+RXA or TXB+RXB */
342 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa500);
343 } else {
344 /* TXB+RXA or TXA+RXB */
345 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa005);
346 }
347 } else {
348 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa5a5);
349 }
350 }
351
352 enum {
353 CCUT_IDX_1R_2G,
354 CCUT_IDX_2R_2G,
355 CCUT_IDX_1R_5G,
356 CCUT_IDX_2R_5G,
357 CCUT_IDX_NR,
358 };
359
360 struct cca_ccut {
361 u32 reg82c[CCUT_IDX_NR];
362 u32 reg830[CCUT_IDX_NR];
363 u32 reg838[CCUT_IDX_NR];
364 };
365
366 static const struct cca_ccut cca_ifem_ccut = {
367 {0x75C97010, 0x75C97010, 0x75C97010, 0x75C97010}, /*Reg82C*/
368 {0x79a0eaaa, 0x79A0EAAC, 0x79a0eaaa, 0x79a0eaaa}, /*Reg830*/
369 {0x87765541, 0x87746341, 0x87765541, 0x87746341}, /*Reg838*/
370 };
371
372 static const struct cca_ccut cca_efem_ccut = {
373 {0x75B86010, 0x75B76010, 0x75B86010, 0x75B76010}, /*Reg82C*/
374 {0x79A0EAA8, 0x79A0EAAC, 0x79A0EAA8, 0x79a0eaaa}, /*Reg830*/
375 {0x87766451, 0x87766431, 0x87766451, 0x87766431}, /*Reg838*/
376 };
377
378 static const struct cca_ccut cca_ifem_ccut_ext = {
379 {0x75da8010, 0x75da8010, 0x75da8010, 0x75da8010}, /*Reg82C*/
380 {0x79a0eaaa, 0x97A0EAAC, 0x79a0eaaa, 0x79a0eaaa}, /*Reg830*/
381 {0x87765541, 0x86666341, 0x87765561, 0x86666361}, /*Reg838*/
382 };
383
rtw8822b_get_cca_val(const struct cca_ccut * cca_ccut,u8 col,u32 * reg82c,u32 * reg830,u32 * reg838)384 static void rtw8822b_get_cca_val(const struct cca_ccut *cca_ccut, u8 col,
385 u32 *reg82c, u32 *reg830, u32 *reg838)
386 {
387 *reg82c = cca_ccut->reg82c[col];
388 *reg830 = cca_ccut->reg830[col];
389 *reg838 = cca_ccut->reg838[col];
390 }
391
392 struct rtw8822b_rfe_info {
393 const struct cca_ccut *cca_ccut_2g;
394 const struct cca_ccut *cca_ccut_5g;
395 enum rtw_rfe_fem fem;
396 bool ifem_ext;
397 void (*rtw_set_channel_rfe)(struct rtw_dev *rtwdev, u8 channel);
398 };
399
400 #define I2GE5G_CCUT(set_ch) { \
401 .cca_ccut_2g = &cca_ifem_ccut, \
402 .cca_ccut_5g = &cca_efem_ccut, \
403 .fem = RTW_RFE_IFEM2G_EFEM5G, \
404 .ifem_ext = false, \
405 .rtw_set_channel_rfe = &rtw8822b_set_channel_rfe_ ## set_ch, \
406 }
407 #define IFEM_EXT_CCUT(set_ch) { \
408 .cca_ccut_2g = &cca_ifem_ccut_ext, \
409 .cca_ccut_5g = &cca_ifem_ccut_ext, \
410 .fem = RTW_RFE_IFEM, \
411 .ifem_ext = true, \
412 .rtw_set_channel_rfe = &rtw8822b_set_channel_rfe_ ## set_ch, \
413 }
414
415 static const struct rtw8822b_rfe_info rtw8822b_rfe_info[] = {
416 [2] = I2GE5G_CCUT(efem),
417 [3] = IFEM_EXT_CCUT(ifem),
418 [5] = IFEM_EXT_CCUT(ifem),
419 };
420
rtw8822b_set_channel_cca(struct rtw_dev * rtwdev,u8 channel,u8 bw,const struct rtw8822b_rfe_info * rfe_info)421 static void rtw8822b_set_channel_cca(struct rtw_dev *rtwdev, u8 channel, u8 bw,
422 const struct rtw8822b_rfe_info *rfe_info)
423 {
424 struct rtw_hal *hal = &rtwdev->hal;
425 struct rtw_efuse *efuse = &rtwdev->efuse;
426 const struct cca_ccut *cca_ccut;
427 u8 col;
428 u32 reg82c, reg830, reg838;
429 bool is_efem_cca = false, is_ifem_cca = false, is_rfe_type = false;
430
431 if (IS_CH_2G_BAND(channel)) {
432 cca_ccut = rfe_info->cca_ccut_2g;
433
434 if (hal->antenna_rx == BB_PATH_A ||
435 hal->antenna_rx == BB_PATH_B)
436 col = CCUT_IDX_1R_2G;
437 else
438 col = CCUT_IDX_2R_2G;
439 } else {
440 cca_ccut = rfe_info->cca_ccut_5g;
441
442 if (hal->antenna_rx == BB_PATH_A ||
443 hal->antenna_rx == BB_PATH_B)
444 col = CCUT_IDX_1R_5G;
445 else
446 col = CCUT_IDX_2R_5G;
447 }
448
449 rtw8822b_get_cca_val(cca_ccut, col, ®82c, ®830, ®838);
450
451 switch (rfe_info->fem) {
452 case RTW_RFE_IFEM:
453 default:
454 is_ifem_cca = true;
455 if (rfe_info->ifem_ext)
456 is_rfe_type = true;
457 break;
458 case RTW_RFE_EFEM:
459 is_efem_cca = true;
460 break;
461 case RTW_RFE_IFEM2G_EFEM5G:
462 if (IS_CH_2G_BAND(channel))
463 is_ifem_cca = true;
464 else
465 is_efem_cca = true;
466 break;
467 }
468
469 if (is_ifem_cca) {
470 if ((hal->cut_version == RTW_CHIP_VER_CUT_B &&
471 (col == CCUT_IDX_2R_2G || col == CCUT_IDX_2R_5G) &&
472 bw == RTW_CHANNEL_WIDTH_40) ||
473 (!is_rfe_type && col == CCUT_IDX_2R_5G &&
474 bw == RTW_CHANNEL_WIDTH_40) ||
475 (efuse->rfe_option == 5 && col == CCUT_IDX_2R_5G))
476 reg830 = 0x79a0ea28;
477 }
478
479 rtw_write32_mask(rtwdev, REG_CCASEL, MASKDWORD, reg82c);
480 rtw_write32_mask(rtwdev, REG_PDMFTH, MASKDWORD, reg830);
481 rtw_write32_mask(rtwdev, REG_CCA2ND, MASKDWORD, reg838);
482
483 if (is_efem_cca && !(hal->cut_version == RTW_CHIP_VER_CUT_B))
484 rtw_write32_mask(rtwdev, REG_L1WT, MASKDWORD, 0x9194b2b9);
485
486 if (bw == RTW_CHANNEL_WIDTH_20 && IS_CH_5G_BAND_MID(channel))
487 rtw_write32_mask(rtwdev, REG_CCA2ND, 0xf0, 0x4);
488 }
489
490 static const u8 low_band[15] = {0x7, 0x6, 0x6, 0x5, 0x0, 0x0, 0x7, 0xff, 0x6,
491 0x5, 0x0, 0x0, 0x7, 0x6, 0x6};
492 static const u8 middle_band[23] = {0x6, 0x5, 0x0, 0x0, 0x7, 0x6, 0x6, 0xff, 0x0,
493 0x0, 0x7, 0x6, 0x6, 0x5, 0x0, 0xff, 0x7, 0x6,
494 0x6, 0x5, 0x0, 0x0, 0x7};
495 static const u8 high_band[15] = {0x5, 0x5, 0x0, 0x7, 0x7, 0x6, 0x5, 0xff, 0x0,
496 0x7, 0x7, 0x6, 0x5, 0x5, 0x0};
497
rtw8822b_set_channel_rf(struct rtw_dev * rtwdev,u8 channel,u8 bw)498 static void rtw8822b_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw)
499 {
500 #define RF18_BAND_MASK (BIT(16) | BIT(9) | BIT(8))
501 #define RF18_BAND_2G (0)
502 #define RF18_BAND_5G (BIT(16) | BIT(8))
503 #define RF18_CHANNEL_MASK (MASKBYTE0)
504 #define RF18_RFSI_MASK (BIT(18) | BIT(17))
505 #define RF18_RFSI_GE_CH80 (BIT(17))
506 #define RF18_RFSI_GT_CH144 (BIT(18))
507 #define RF18_BW_MASK (BIT(11) | BIT(10))
508 #define RF18_BW_20M (BIT(11) | BIT(10))
509 #define RF18_BW_40M (BIT(11))
510 #define RF18_BW_80M (BIT(10))
511 #define RFBE_MASK (BIT(17) | BIT(16) | BIT(15))
512
513 struct rtw_hal *hal = &rtwdev->hal;
514 u32 rf_reg18, rf_reg_be;
515
516 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK);
517
518 rf_reg18 &= ~(RF18_BAND_MASK | RF18_CHANNEL_MASK | RF18_RFSI_MASK |
519 RF18_BW_MASK);
520
521 rf_reg18 |= (IS_CH_2G_BAND(channel) ? RF18_BAND_2G : RF18_BAND_5G);
522 rf_reg18 |= (channel & RF18_CHANNEL_MASK);
523 if (channel > 144)
524 rf_reg18 |= RF18_RFSI_GT_CH144;
525 else if (channel >= 80)
526 rf_reg18 |= RF18_RFSI_GE_CH80;
527
528 switch (bw) {
529 case RTW_CHANNEL_WIDTH_5:
530 case RTW_CHANNEL_WIDTH_10:
531 case RTW_CHANNEL_WIDTH_20:
532 default:
533 rf_reg18 |= RF18_BW_20M;
534 break;
535 case RTW_CHANNEL_WIDTH_40:
536 rf_reg18 |= RF18_BW_40M;
537 break;
538 case RTW_CHANNEL_WIDTH_80:
539 rf_reg18 |= RF18_BW_80M;
540 break;
541 }
542
543 if (IS_CH_2G_BAND(channel))
544 rf_reg_be = 0x0;
545 else if (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel))
546 rf_reg_be = low_band[(channel - 36) >> 1];
547 else if (IS_CH_5G_BAND_3(channel))
548 rf_reg_be = middle_band[(channel - 100) >> 1];
549 else if (IS_CH_5G_BAND_4(channel))
550 rf_reg_be = high_band[(channel - 149) >> 1];
551 else
552 goto err;
553
554 rtw_write_rf(rtwdev, RF_PATH_A, RF_MALSEL, RFBE_MASK, rf_reg_be);
555
556 /* need to set 0xdf[18]=1 before writing RF18 when channel 144 */
557 if (channel == 144)
558 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(18), 0x1);
559 else
560 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(18), 0x0);
561
562 rtw_write_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK, rf_reg18);
563 if (hal->rf_type > RF_1T1R)
564 rtw_write_rf(rtwdev, RF_PATH_B, 0x18, RFREG_MASK, rf_reg18);
565
566 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 0);
567 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 1);
568
569 return;
570
571 err:
572 WARN_ON(1);
573 }
574
rtw8822b_toggle_igi(struct rtw_dev * rtwdev)575 static void rtw8822b_toggle_igi(struct rtw_dev *rtwdev)
576 {
577 struct rtw_hal *hal = &rtwdev->hal;
578 u32 igi;
579
580 igi = rtw_read32_mask(rtwdev, REG_RXIGI_A, 0x7f);
581 rtw_write32_mask(rtwdev, REG_RXIGI_A, 0x7f, igi - 2);
582 rtw_write32_mask(rtwdev, REG_RXIGI_A, 0x7f, igi);
583 rtw_write32_mask(rtwdev, REG_RXIGI_B, 0x7f, igi - 2);
584 rtw_write32_mask(rtwdev, REG_RXIGI_B, 0x7f, igi);
585
586 rtw_write32_mask(rtwdev, REG_RXPSEL, MASKBYTE0, 0x0);
587 rtw_write32_mask(rtwdev, REG_RXPSEL, MASKBYTE0,
588 hal->antenna_rx | (hal->antenna_rx << 4));
589 }
590
rtw8822b_set_channel_rxdfir(struct rtw_dev * rtwdev,u8 bw)591 static void rtw8822b_set_channel_rxdfir(struct rtw_dev *rtwdev, u8 bw)
592 {
593 if (bw == RTW_CHANNEL_WIDTH_40) {
594 /* RX DFIR for BW40 */
595 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x1);
596 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x0);
597 rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0);
598 } else if (bw == RTW_CHANNEL_WIDTH_80) {
599 /* RX DFIR for BW80 */
600 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2);
601 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x1);
602 rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0);
603 } else {
604 /* RX DFIR for BW20, BW10 and BW5*/
605 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2);
606 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2);
607 rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x1);
608 }
609 }
610
rtw8822b_set_channel_bb(struct rtw_dev * rtwdev,u8 channel,u8 bw,u8 primary_ch_idx)611 static void rtw8822b_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw,
612 u8 primary_ch_idx)
613 {
614 struct rtw_efuse *efuse = &rtwdev->efuse;
615 u8 rfe_option = efuse->rfe_option;
616 u32 val32;
617
618 if (IS_CH_2G_BAND(channel)) {
619 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1);
620 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x0);
621 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x0);
622 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15);
623
624 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x0);
625 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x96a);
626 if (channel == 14) {
627 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x00006577);
628 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x0000);
629 } else {
630 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x384f6577);
631 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x1525);
632 }
633
634 rtw_write32_mask(rtwdev, REG_RFEINV, 0x300, 0x2);
635 } else if (IS_CH_5G_BAND(channel)) {
636 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x1);
637 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x1);
638 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0);
639 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 34);
640
641 if (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel))
642 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x1);
643 else if (IS_CH_5G_BAND_3(channel))
644 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x2);
645 else if (IS_CH_5G_BAND_4(channel))
646 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x3);
647
648 if (IS_CH_5G_BAND_1(channel))
649 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x494);
650 else if (IS_CH_5G_BAND_2(channel))
651 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x453);
652 else if (channel >= 100 && channel <= 116)
653 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x452);
654 else if (channel >= 118 && channel <= 177)
655 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x412);
656
657 rtw_write32_mask(rtwdev, 0xcbc, 0x300, 0x1);
658 }
659
660 switch (bw) {
661 case RTW_CHANNEL_WIDTH_20:
662 default:
663 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
664 val32 &= 0xFFCFFC00;
665 val32 |= (RTW_CHANNEL_WIDTH_20);
666 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
667
668 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);
669 break;
670 case RTW_CHANNEL_WIDTH_40:
671 if (primary_ch_idx == RTW_SC_20_UPPER)
672 rtw_write32_set(rtwdev, REG_RXSB, BIT(4));
673 else
674 rtw_write32_clr(rtwdev, REG_RXSB, BIT(4));
675
676 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
677 val32 &= 0xFF3FF300;
678 val32 |= (((primary_ch_idx & 0xf) << 2) | RTW_CHANNEL_WIDTH_40);
679 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
680
681 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);
682 break;
683 case RTW_CHANNEL_WIDTH_80:
684 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
685 val32 &= 0xFCEFCF00;
686 val32 |= (((primary_ch_idx & 0xf) << 2) | RTW_CHANNEL_WIDTH_80);
687 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
688
689 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);
690
691 if (rfe_option == 2 || rfe_option == 3) {
692 rtw_write32_mask(rtwdev, REG_L1PKWT, 0x0000f000, 0x6);
693 rtw_write32_mask(rtwdev, REG_ADC40, BIT(10), 0x1);
694 }
695 break;
696 case RTW_CHANNEL_WIDTH_5:
697 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
698 val32 &= 0xEFEEFE00;
699 val32 |= ((BIT(6) | RTW_CHANNEL_WIDTH_20));
700 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
701
702 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0);
703 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1);
704 break;
705 case RTW_CHANNEL_WIDTH_10:
706 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
707 val32 &= 0xEFFEFF00;
708 val32 |= ((BIT(7) | RTW_CHANNEL_WIDTH_20));
709 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
710
711 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0);
712 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1);
713 break;
714 }
715 }
716
rtw8822b_set_channel(struct rtw_dev * rtwdev,u8 channel,u8 bw,u8 primary_chan_idx)717 static void rtw8822b_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw,
718 u8 primary_chan_idx)
719 {
720 struct rtw_efuse *efuse = &rtwdev->efuse;
721 const struct rtw8822b_rfe_info *rfe_info;
722
723 if (WARN(efuse->rfe_option >= ARRAY_SIZE(rtw8822b_rfe_info),
724 "rfe_option %d is out of boundary\n", efuse->rfe_option))
725 return;
726
727 rfe_info = &rtw8822b_rfe_info[efuse->rfe_option];
728
729 rtw8822b_set_channel_bb(rtwdev, channel, bw, primary_chan_idx);
730 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx);
731 rtw8822b_set_channel_rf(rtwdev, channel, bw);
732 rtw8822b_set_channel_rxdfir(rtwdev, bw);
733 rtw8822b_toggle_igi(rtwdev);
734 rtw8822b_set_channel_cca(rtwdev, channel, bw, rfe_info);
735 (*rfe_info->rtw_set_channel_rfe)(rtwdev, channel);
736 }
737
rtw8822b_config_trx_mode(struct rtw_dev * rtwdev,u8 tx_path,u8 rx_path,bool is_tx2_path)738 static void rtw8822b_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path,
739 u8 rx_path, bool is_tx2_path)
740 {
741 struct rtw_efuse *efuse = &rtwdev->efuse;
742 const struct rtw8822b_rfe_info *rfe_info;
743 u8 ch = rtwdev->hal.current_channel;
744 u8 tx_path_sel, rx_path_sel;
745 int counter;
746
747 if (WARN(efuse->rfe_option >= ARRAY_SIZE(rtw8822b_rfe_info),
748 "rfe_option %d is out of boundary\n", efuse->rfe_option))
749 return;
750
751 rfe_info = &rtw8822b_rfe_info[efuse->rfe_option];
752
753 if ((tx_path | rx_path) & BB_PATH_A)
754 rtw_write32_mask(rtwdev, REG_AGCTR_A, MASKLWORD, 0x3231);
755 else
756 rtw_write32_mask(rtwdev, REG_AGCTR_A, MASKLWORD, 0x1111);
757
758 if ((tx_path | rx_path) & BB_PATH_B)
759 rtw_write32_mask(rtwdev, REG_AGCTR_B, MASKLWORD, 0x3231);
760 else
761 rtw_write32_mask(rtwdev, REG_AGCTR_B, MASKLWORD, 0x1111);
762
763 rtw_write32_mask(rtwdev, REG_CDDTXP, (BIT(19) | BIT(18)), 0x3);
764 rtw_write32_mask(rtwdev, REG_TXPSEL, (BIT(29) | BIT(28)), 0x1);
765 rtw_write32_mask(rtwdev, REG_TXPSEL, BIT(30), 0x1);
766
767 if (tx_path & BB_PATH_A) {
768 rtw_write32_mask(rtwdev, REG_CDDTXP, 0xfff00000, 0x001);
769 rtw_write32_mask(rtwdev, REG_ADCINI, 0xf0000000, 0x8);
770 } else if (tx_path & BB_PATH_B) {
771 rtw_write32_mask(rtwdev, REG_CDDTXP, 0xfff00000, 0x002);
772 rtw_write32_mask(rtwdev, REG_ADCINI, 0xf0000000, 0x4);
773 }
774
775 if (tx_path == BB_PATH_A || tx_path == BB_PATH_B)
776 rtw_write32_mask(rtwdev, REG_TXPSEL1, 0xfff0, 0x01);
777 else
778 rtw_write32_mask(rtwdev, REG_TXPSEL1, 0xfff0, 0x43);
779
780 tx_path_sel = (tx_path << 4) | tx_path;
781 rtw_write32_mask(rtwdev, REG_TXPSEL, MASKBYTE0, tx_path_sel);
782
783 if (tx_path != BB_PATH_A && tx_path != BB_PATH_B) {
784 if (is_tx2_path || rtwdev->mp_mode) {
785 rtw_write32_mask(rtwdev, REG_CDDTXP, 0xfff00000, 0x043);
786 rtw_write32_mask(rtwdev, REG_ADCINI, 0xf0000000, 0xc);
787 }
788 }
789
790 rtw_write32_mask(rtwdev, REG_RXDESC, BIT(22), 0x0);
791 rtw_write32_mask(rtwdev, REG_RXDESC, BIT(18), 0x0);
792
793 if (rx_path & BB_PATH_A)
794 rtw_write32_mask(rtwdev, REG_ADCINI, 0x0f000000, 0x0);
795 else if (rx_path & BB_PATH_B)
796 rtw_write32_mask(rtwdev, REG_ADCINI, 0x0f000000, 0x5);
797
798 rx_path_sel = (rx_path << 4) | rx_path;
799 rtw_write32_mask(rtwdev, REG_RXPSEL, MASKBYTE0, rx_path_sel);
800
801 if (rx_path == BB_PATH_A || rx_path == BB_PATH_B) {
802 rtw_write32_mask(rtwdev, REG_ANTWT, BIT(16), 0x0);
803 rtw_write32_mask(rtwdev, REG_HTSTFWT, BIT(28), 0x0);
804 rtw_write32_mask(rtwdev, REG_MRC, BIT(23), 0x0);
805 } else {
806 rtw_write32_mask(rtwdev, REG_ANTWT, BIT(16), 0x1);
807 rtw_write32_mask(rtwdev, REG_HTSTFWT, BIT(28), 0x1);
808 rtw_write32_mask(rtwdev, REG_MRC, BIT(23), 0x1);
809 }
810
811 for (counter = 100; counter > 0; counter--) {
812 u32 rf_reg33;
813
814 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x80000);
815 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00001);
816
817 udelay(2);
818 rf_reg33 = rtw_read_rf(rtwdev, RF_PATH_A, 0x33, RFREG_MASK);
819
820 if (rf_reg33 == 0x00001)
821 break;
822 }
823
824 if (WARN(counter <= 0, "write RF mode table fail\n"))
825 return;
826
827 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x80000);
828 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00001);
829 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD1, RFREG_MASK, 0x00034);
830 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x4080c);
831 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x00000);
832 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x00000);
833
834 rtw8822b_toggle_igi(rtwdev);
835 rtw8822b_set_channel_cca(rtwdev, 1, RTW_CHANNEL_WIDTH_20, rfe_info);
836 (*rfe_info->rtw_set_channel_rfe)(rtwdev, ch);
837 }
838
query_phy_status_page0(struct rtw_dev * rtwdev,u8 * phy_status,struct rtw_rx_pkt_stat * pkt_stat)839 static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status,
840 struct rtw_rx_pkt_stat *pkt_stat)
841 {
842 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
843 s8 min_rx_power = -120;
844 u8 pwdb = GET_PHY_STAT_P0_PWDB(phy_status);
845
846 /* 8822B uses only 1 antenna to RX CCK rates */
847 pkt_stat->rx_power[RF_PATH_A] = pwdb - 110;
848 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1);
849 pkt_stat->bw = RTW_CHANNEL_WIDTH_20;
850 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A],
851 min_rx_power);
852 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi;
853 }
854
query_phy_status_page1(struct rtw_dev * rtwdev,u8 * phy_status,struct rtw_rx_pkt_stat * pkt_stat)855 static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status,
856 struct rtw_rx_pkt_stat *pkt_stat)
857 {
858 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
859 u8 rxsc, bw;
860 s8 min_rx_power = -120;
861 s8 rx_evm;
862 u8 evm_dbm = 0;
863 u8 rssi;
864 int path;
865
866 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0)
867 rxsc = GET_PHY_STAT_P1_L_RXSC(phy_status);
868 else
869 rxsc = GET_PHY_STAT_P1_HT_RXSC(phy_status);
870
871 if (rxsc >= 1 && rxsc <= 8)
872 bw = RTW_CHANNEL_WIDTH_20;
873 else if (rxsc >= 9 && rxsc <= 12)
874 bw = RTW_CHANNEL_WIDTH_40;
875 else if (rxsc >= 13)
876 bw = RTW_CHANNEL_WIDTH_80;
877 else
878 bw = GET_PHY_STAT_P1_RF_MODE(phy_status);
879
880 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110;
881 pkt_stat->rx_power[RF_PATH_B] = GET_PHY_STAT_P1_PWDB_B(phy_status) - 110;
882 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 2);
883 pkt_stat->bw = bw;
884 pkt_stat->signal_power = max3(pkt_stat->rx_power[RF_PATH_A],
885 pkt_stat->rx_power[RF_PATH_B],
886 min_rx_power);
887
888 dm_info->curr_rx_rate = pkt_stat->rate;
889
890 pkt_stat->rx_evm[RF_PATH_A] = GET_PHY_STAT_P1_RXEVM_A(phy_status);
891 pkt_stat->rx_evm[RF_PATH_B] = GET_PHY_STAT_P1_RXEVM_B(phy_status);
892
893 pkt_stat->rx_snr[RF_PATH_A] = GET_PHY_STAT_P1_RXSNR_A(phy_status);
894 pkt_stat->rx_snr[RF_PATH_B] = GET_PHY_STAT_P1_RXSNR_B(phy_status);
895
896 pkt_stat->cfo_tail[RF_PATH_A] = GET_PHY_STAT_P1_CFO_TAIL_A(phy_status);
897 pkt_stat->cfo_tail[RF_PATH_B] = GET_PHY_STAT_P1_CFO_TAIL_B(phy_status);
898
899 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) {
900 rssi = rtw_phy_rf_power_2_rssi(&pkt_stat->rx_power[path], 1);
901 dm_info->rssi[path] = rssi;
902 dm_info->rx_snr[path] = pkt_stat->rx_snr[path] >> 1;
903 dm_info->cfo_tail[path] = (pkt_stat->cfo_tail[path] * 5) >> 1;
904
905 rx_evm = pkt_stat->rx_evm[path];
906
907 if (rx_evm < 0) {
908 if (rx_evm == S8_MIN)
909 evm_dbm = 0;
910 else
911 evm_dbm = ((u8)-rx_evm >> 1);
912 }
913 dm_info->rx_evm_dbm[path] = evm_dbm;
914 }
915 }
916
query_phy_status(struct rtw_dev * rtwdev,u8 * phy_status,struct rtw_rx_pkt_stat * pkt_stat)917 static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status,
918 struct rtw_rx_pkt_stat *pkt_stat)
919 {
920 u8 page;
921
922 page = *phy_status & 0xf;
923
924 switch (page) {
925 case 0:
926 query_phy_status_page0(rtwdev, phy_status, pkt_stat);
927 break;
928 case 1:
929 query_phy_status_page1(rtwdev, phy_status, pkt_stat);
930 break;
931 default:
932 rtw_warn(rtwdev, "unused phy status page (%d)\n", page);
933 return;
934 }
935 }
936
937 static void
rtw8822b_set_tx_power_index_by_rate(struct rtw_dev * rtwdev,u8 path,u8 rs,u32 * phy_pwr_idx)938 rtw8822b_set_tx_power_index_by_rate(struct rtw_dev *rtwdev, u8 path,
939 u8 rs, u32 *phy_pwr_idx)
940 {
941 struct rtw_hal *hal = &rtwdev->hal;
942 static const u32 offset_txagc[2] = {0x1d00, 0x1d80};
943 u8 rate, rate_idx, pwr_index, shift;
944 int j;
945
946 for (j = 0; j < rtw_rate_size[rs]; j++) {
947 rate = rtw_rate_section[rs][j];
948 pwr_index = hal->tx_pwr_tbl[path][rate];
949 shift = rate & 0x3;
950 *phy_pwr_idx |= ((u32)pwr_index << (shift * 8));
951 if (shift == 0x3) {
952 rate_idx = rate & 0xfc;
953 rtw_write32(rtwdev, offset_txagc[path] + rate_idx,
954 *phy_pwr_idx);
955 *phy_pwr_idx = 0;
956 }
957 }
958 }
959
rtw8822b_set_tx_power_index(struct rtw_dev * rtwdev)960 static void rtw8822b_set_tx_power_index(struct rtw_dev *rtwdev)
961 {
962 struct rtw_hal *hal = &rtwdev->hal;
963 u32 phy_pwr_idx = 0;
964 int rs, path;
965
966 for (path = 0; path < hal->rf_path_num; path++) {
967 for (rs = 0; rs <= __RTW_RATE_SECTION_2SS_MAX; rs++)
968 rtw8822b_set_tx_power_index_by_rate(rtwdev, path, rs,
969 &phy_pwr_idx);
970 }
971 }
972
rtw8822b_check_rf_path(u8 antenna)973 static bool rtw8822b_check_rf_path(u8 antenna)
974 {
975 switch (antenna) {
976 case BB_PATH_A:
977 case BB_PATH_B:
978 case BB_PATH_AB:
979 return true;
980 default:
981 return false;
982 }
983 }
984
rtw8822b_set_antenna(struct rtw_dev * rtwdev,u32 antenna_tx,u32 antenna_rx)985 static int rtw8822b_set_antenna(struct rtw_dev *rtwdev,
986 u32 antenna_tx,
987 u32 antenna_rx)
988 {
989 struct rtw_hal *hal = &rtwdev->hal;
990
991 rtw_dbg(rtwdev, RTW_DBG_PHY, "config RF path, tx=0x%x rx=0x%x\n",
992 antenna_tx, antenna_rx);
993
994 if (!rtw8822b_check_rf_path(antenna_tx)) {
995 rtw_warn(rtwdev, "unsupported tx path 0x%x\n", antenna_tx);
996 return -EINVAL;
997 }
998
999 if (!rtw8822b_check_rf_path(antenna_rx)) {
1000 rtw_warn(rtwdev, "unsupported rx path 0x%x\n", antenna_rx);
1001 return -EINVAL;
1002 }
1003
1004 hal->antenna_tx = antenna_tx;
1005 hal->antenna_rx = antenna_rx;
1006
1007 rtw8822b_config_trx_mode(rtwdev, antenna_tx, antenna_rx, false);
1008
1009 return 0;
1010 }
1011
rtw8822b_cfg_ldo25(struct rtw_dev * rtwdev,bool enable)1012 static void rtw8822b_cfg_ldo25(struct rtw_dev *rtwdev, bool enable)
1013 {
1014 u8 ldo_pwr;
1015
1016 ldo_pwr = rtw_read8(rtwdev, REG_LDO_EFUSE_CTRL + 3);
1017 ldo_pwr = enable ? ldo_pwr | BIT_LDO25_EN : ldo_pwr & ~BIT_LDO25_EN;
1018 rtw_write8(rtwdev, REG_LDO_EFUSE_CTRL + 3, ldo_pwr);
1019 }
1020
rtw8822b_false_alarm_statistics(struct rtw_dev * rtwdev)1021 static void rtw8822b_false_alarm_statistics(struct rtw_dev *rtwdev)
1022 {
1023 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1024 u32 cck_enable;
1025 u32 cck_fa_cnt;
1026 u32 ofdm_fa_cnt;
1027 u32 crc32_cnt;
1028 u32 cca32_cnt;
1029
1030 cck_enable = rtw_read32(rtwdev, 0x808) & BIT(28);
1031 cck_fa_cnt = rtw_read16(rtwdev, 0xa5c);
1032 ofdm_fa_cnt = rtw_read16(rtwdev, 0xf48);
1033
1034 dm_info->cck_fa_cnt = cck_fa_cnt;
1035 dm_info->ofdm_fa_cnt = ofdm_fa_cnt;
1036 dm_info->total_fa_cnt = ofdm_fa_cnt;
1037 dm_info->total_fa_cnt += cck_enable ? cck_fa_cnt : 0;
1038
1039 crc32_cnt = rtw_read32(rtwdev, 0xf04);
1040 dm_info->cck_ok_cnt = crc32_cnt & 0xffff;
1041 dm_info->cck_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
1042 crc32_cnt = rtw_read32(rtwdev, 0xf14);
1043 dm_info->ofdm_ok_cnt = crc32_cnt & 0xffff;
1044 dm_info->ofdm_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
1045 crc32_cnt = rtw_read32(rtwdev, 0xf10);
1046 dm_info->ht_ok_cnt = crc32_cnt & 0xffff;
1047 dm_info->ht_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
1048 crc32_cnt = rtw_read32(rtwdev, 0xf0c);
1049 dm_info->vht_ok_cnt = crc32_cnt & 0xffff;
1050 dm_info->vht_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
1051
1052 cca32_cnt = rtw_read32(rtwdev, 0xf08);
1053 dm_info->ofdm_cca_cnt = ((cca32_cnt & 0xffff0000) >> 16);
1054 dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt;
1055 if (cck_enable) {
1056 cca32_cnt = rtw_read32(rtwdev, 0xfcc);
1057 dm_info->cck_cca_cnt = cca32_cnt & 0xffff;
1058 dm_info->total_cca_cnt += dm_info->cck_cca_cnt;
1059 }
1060
1061 rtw_write32_set(rtwdev, 0x9a4, BIT(17));
1062 rtw_write32_clr(rtwdev, 0x9a4, BIT(17));
1063 rtw_write32_clr(rtwdev, 0xa2c, BIT(15));
1064 rtw_write32_set(rtwdev, 0xa2c, BIT(15));
1065 rtw_write32_set(rtwdev, 0xb58, BIT(0));
1066 rtw_write32_clr(rtwdev, 0xb58, BIT(0));
1067 }
1068
rtw8822b_do_iqk(struct rtw_dev * rtwdev)1069 static void rtw8822b_do_iqk(struct rtw_dev *rtwdev)
1070 {
1071 static int do_iqk_cnt;
1072 struct rtw_iqk_para para = {.clear = 0, .segment_iqk = 0};
1073 u32 rf_reg, iqk_fail_mask;
1074 int counter;
1075 bool reload;
1076
1077 rtw_fw_do_iqk(rtwdev, ¶);
1078
1079 for (counter = 0; counter < 300; counter++) {
1080 rf_reg = rtw_read_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK);
1081 if (rf_reg == 0xabcde)
1082 break;
1083 msleep(20);
1084 }
1085 rtw_write_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK, 0x0);
1086
1087 reload = !!rtw_read32_mask(rtwdev, REG_IQKFAILMSK, BIT(16));
1088 iqk_fail_mask = rtw_read32_mask(rtwdev, REG_IQKFAILMSK, GENMASK(7, 0));
1089 rtw_dbg(rtwdev, RTW_DBG_PHY,
1090 "iqk counter=%d reload=%d do_iqk_cnt=%d n_iqk_fail(mask)=0x%02x\n",
1091 counter, reload, ++do_iqk_cnt, iqk_fail_mask);
1092 }
1093
rtw8822b_phy_calibration(struct rtw_dev * rtwdev)1094 static void rtw8822b_phy_calibration(struct rtw_dev *rtwdev)
1095 {
1096 rtw8822b_do_iqk(rtwdev);
1097 }
1098
rtw8822b_coex_cfg_init(struct rtw_dev * rtwdev)1099 static void rtw8822b_coex_cfg_init(struct rtw_dev *rtwdev)
1100 {
1101 /* enable TBTT nterrupt */
1102 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
1103
1104 /* BT report packet sample rate */
1105 /* 0x790[5:0]=0x5 */
1106 rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5);
1107
1108 /* enable BT counter statistics */
1109 rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1);
1110
1111 /* enable PTA (3-wire function form BT side) */
1112 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN);
1113 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_PO_BT_PTA_PINS);
1114
1115 /* enable PTA (tx/rx signal form WiFi side) */
1116 rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN);
1117 /* wl tx signal to PTA not case EDCCA */
1118 rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT_PTA_EDCCA_EN);
1119 /* GNT_BT=1 while select both */
1120 rtw_write16_set(rtwdev, REG_BT_COEX_V2, BIT_GNT_BT_POLARITY);
1121 }
1122
rtw8822b_coex_cfg_ant_switch(struct rtw_dev * rtwdev,u8 ctrl_type,u8 pos_type)1123 static void rtw8822b_coex_cfg_ant_switch(struct rtw_dev *rtwdev,
1124 u8 ctrl_type, u8 pos_type)
1125 {
1126 struct rtw_coex *coex = &rtwdev->coex;
1127 struct rtw_coex_dm *coex_dm = &coex->dm;
1128 struct rtw_coex_rfe *coex_rfe = &coex->rfe;
1129 bool polarity_inverse;
1130 u8 regval = 0;
1131
1132 if (((ctrl_type << 8) + pos_type) == coex_dm->cur_switch_status)
1133 return;
1134
1135 coex_dm->cur_switch_status = (ctrl_type << 8) + pos_type;
1136
1137 if (coex_rfe->ant_switch_diversity &&
1138 ctrl_type == COEX_SWITCH_CTRL_BY_BBSW)
1139 ctrl_type = COEX_SWITCH_CTRL_BY_ANTDIV;
1140
1141 polarity_inverse = (coex_rfe->ant_switch_polarity == 1);
1142
1143 switch (ctrl_type) {
1144 default:
1145 case COEX_SWITCH_CTRL_BY_BBSW:
1146 /* 0x4c[23] = 0 */
1147 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0);
1148 /* 0x4c[24] = 1 */
1149 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1);
1150 /* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */
1151 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 0x77);
1152
1153 if (pos_type == COEX_SWITCH_TO_WLG_BT) {
1154 if (coex_rfe->rfe_module_type != 0x4 &&
1155 coex_rfe->rfe_module_type != 0x2)
1156 regval = 0x3;
1157 else
1158 regval = (!polarity_inverse ? 0x2 : 0x1);
1159 } else if (pos_type == COEX_SWITCH_TO_WLG) {
1160 regval = (!polarity_inverse ? 0x2 : 0x1);
1161 } else {
1162 regval = (!polarity_inverse ? 0x1 : 0x2);
1163 }
1164
1165 rtw_write8_mask(rtwdev, REG_RFE_INV8, BIT_MASK_RFE_INV89, regval);
1166 break;
1167 case COEX_SWITCH_CTRL_BY_PTA:
1168 /* 0x4c[23] = 0 */
1169 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0);
1170 /* 0x4c[24] = 1 */
1171 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1);
1172 /* PTA, DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */
1173 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 0x66);
1174
1175 regval = (!polarity_inverse ? 0x2 : 0x1);
1176 rtw_write8_mask(rtwdev, REG_RFE_INV8, BIT_MASK_RFE_INV89, regval);
1177 break;
1178 case COEX_SWITCH_CTRL_BY_ANTDIV:
1179 /* 0x4c[23] = 0 */
1180 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0);
1181 /* 0x4c[24] = 1 */
1182 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1);
1183 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 0x88);
1184 break;
1185 case COEX_SWITCH_CTRL_BY_MAC:
1186 /* 0x4c[23] = 1 */
1187 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x1);
1188
1189 regval = (!polarity_inverse ? 0x0 : 0x1);
1190 rtw_write8_mask(rtwdev, REG_PAD_CTRL1, BIT_SW_DPDT_SEL_DATA, regval);
1191 break;
1192 case COEX_SWITCH_CTRL_BY_FW:
1193 /* 0x4c[23] = 0 */
1194 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0);
1195 /* 0x4c[24] = 1 */
1196 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1);
1197 break;
1198 case COEX_SWITCH_CTRL_BY_BT:
1199 /* 0x4c[23] = 0 */
1200 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0);
1201 /* 0x4c[24] = 0 */
1202 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x0);
1203 break;
1204 }
1205 }
1206
rtw8822b_coex_cfg_gnt_fix(struct rtw_dev * rtwdev)1207 static void rtw8822b_coex_cfg_gnt_fix(struct rtw_dev *rtwdev)
1208 {
1209 }
1210
rtw8822b_coex_cfg_gnt_debug(struct rtw_dev * rtwdev)1211 static void rtw8822b_coex_cfg_gnt_debug(struct rtw_dev *rtwdev)
1212 {
1213 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 2, BIT_BTGP_SPI_EN >> 16, 0);
1214 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT_BTGP_JTAG_EN >> 24, 0);
1215 rtw_write8_mask(rtwdev, REG_GPIO_MUXCFG + 2, BIT_FSPI_EN >> 16, 0);
1216 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 1, BIT_LED1DIS >> 8, 0);
1217 rtw_write8_mask(rtwdev, REG_SYS_SDIO_CTRL + 3, BIT_DBG_GNT_WL_BT >> 24, 0);
1218 }
1219
rtw8822b_coex_cfg_rfe_type(struct rtw_dev * rtwdev)1220 static void rtw8822b_coex_cfg_rfe_type(struct rtw_dev *rtwdev)
1221 {
1222 struct rtw_coex *coex = &rtwdev->coex;
1223 struct rtw_coex_rfe *coex_rfe = &coex->rfe;
1224 struct rtw_efuse *efuse = &rtwdev->efuse;
1225 bool is_ext_fem = false;
1226
1227 coex_rfe->rfe_module_type = rtwdev->efuse.rfe_option;
1228 coex_rfe->ant_switch_polarity = 0;
1229 coex_rfe->ant_switch_diversity = false;
1230 if (coex_rfe->rfe_module_type == 0x12 ||
1231 coex_rfe->rfe_module_type == 0x15 ||
1232 coex_rfe->rfe_module_type == 0x16)
1233 coex_rfe->ant_switch_exist = false;
1234 else
1235 coex_rfe->ant_switch_exist = true;
1236
1237 if (coex_rfe->rfe_module_type == 2 ||
1238 coex_rfe->rfe_module_type == 4) {
1239 rtw_coex_write_scbd(rtwdev, COEX_SCBD_EXTFEM, true);
1240 is_ext_fem = true;
1241 } else {
1242 rtw_coex_write_scbd(rtwdev, COEX_SCBD_EXTFEM, false);
1243 }
1244
1245 coex_rfe->wlg_at_btg = false;
1246
1247 if (efuse->share_ant &&
1248 coex_rfe->ant_switch_exist && !is_ext_fem)
1249 coex_rfe->ant_switch_with_bt = true;
1250 else
1251 coex_rfe->ant_switch_with_bt = false;
1252
1253 /* Ext switch buffer mux */
1254 rtw_write8(rtwdev, REG_RFE_CTRL_E, 0xff);
1255 rtw_write8_mask(rtwdev, REG_RFESEL_CTRL + 1, 0x3, 0x0);
1256 rtw_write8_mask(rtwdev, REG_RFE_INV16, BIT_RFE_BUF_EN, 0x0);
1257
1258 /* Disable LTE Coex Function in WiFi side */
1259 rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, BIT_LTE_COEX_EN, 0);
1260
1261 /* BTC_CTT_WL_VS_LTE */
1262 rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff);
1263
1264 /* BTC_CTT_BT_VS_LTE */
1265 rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff);
1266 }
1267
rtw8822b_coex_cfg_wl_tx_power(struct rtw_dev * rtwdev,u8 wl_pwr)1268 static void rtw8822b_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr)
1269 {
1270 struct rtw_coex *coex = &rtwdev->coex;
1271 struct rtw_coex_dm *coex_dm = &coex->dm;
1272 static const u16 reg_addr[] = {0xc58, 0xe58};
1273 static const u8 wl_tx_power[] = {0xd8, 0xd4, 0xd0, 0xcc, 0xc8};
1274 u8 i, pwr;
1275
1276 if (wl_pwr == coex_dm->cur_wl_pwr_lvl)
1277 return;
1278
1279 coex_dm->cur_wl_pwr_lvl = wl_pwr;
1280
1281 if (coex_dm->cur_wl_pwr_lvl >= ARRAY_SIZE(wl_tx_power))
1282 coex_dm->cur_wl_pwr_lvl = ARRAY_SIZE(wl_tx_power) - 1;
1283
1284 pwr = wl_tx_power[coex_dm->cur_wl_pwr_lvl];
1285
1286 for (i = 0; i < ARRAY_SIZE(reg_addr); i++)
1287 rtw_write8_mask(rtwdev, reg_addr[i], 0xff, pwr);
1288 }
1289
rtw8822b_coex_cfg_wl_rx_gain(struct rtw_dev * rtwdev,bool low_gain)1290 static void rtw8822b_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain)
1291 {
1292 struct rtw_coex *coex = &rtwdev->coex;
1293 struct rtw_coex_dm *coex_dm = &coex->dm;
1294 /* WL Rx Low gain on */
1295 static const u32 wl_rx_low_gain_on[] = {
1296 0xff000003, 0xbd120003, 0xbe100003, 0xbf080003, 0xbf060003,
1297 0xbf050003, 0xbc140003, 0xbb160003, 0xba180003, 0xb91a0003,
1298 0xb81c0003, 0xb71e0003, 0xb4200003, 0xb5220003, 0xb4240003,
1299 0xb3260003, 0xb2280003, 0xb12a0003, 0xb02c0003, 0xaf2e0003,
1300 0xae300003, 0xad320003, 0xac340003, 0xab360003, 0x8d380003,
1301 0x8c3a0003, 0x8b3c0003, 0x8a3e0003, 0x6e400003, 0x6d420003,
1302 0x6c440003, 0x6b460003, 0x6a480003, 0x694a0003, 0x684c0003,
1303 0x674e0003, 0x66500003, 0x65520003, 0x64540003, 0x64560003,
1304 0x007e0403
1305 };
1306
1307 /* WL Rx Low gain off */
1308 static const u32 wl_rx_low_gain_off[] = {
1309 0xff000003, 0xf4120003, 0xf5100003, 0xf60e0003, 0xf70c0003,
1310 0xf80a0003, 0xf3140003, 0xf2160003, 0xf1180003, 0xf01a0003,
1311 0xef1c0003, 0xee1e0003, 0xed200003, 0xec220003, 0xeb240003,
1312 0xea260003, 0xe9280003, 0xe82a0003, 0xe72c0003, 0xe62e0003,
1313 0xe5300003, 0xc8320003, 0xc7340003, 0xc6360003, 0xc5380003,
1314 0xc43a0003, 0xc33c0003, 0xc23e0003, 0xc1400003, 0xc0420003,
1315 0xa5440003, 0xa4460003, 0xa3480003, 0xa24a0003, 0xa14c0003,
1316 0x834e0003, 0x82500003, 0x81520003, 0x80540003, 0x65560003,
1317 0x007e0403
1318 };
1319 u8 i;
1320
1321 if (low_gain == coex_dm->cur_wl_rx_low_gain_en)
1322 return;
1323
1324 coex_dm->cur_wl_rx_low_gain_en = low_gain;
1325
1326 if (coex_dm->cur_wl_rx_low_gain_en) {
1327 rtw_dbg(rtwdev, RTW_DBG_COEX, "[BTCoex], Hi-Li Table On!\n");
1328 for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_on); i++)
1329 rtw_write32(rtwdev, REG_RX_GAIN_EN, wl_rx_low_gain_on[i]);
1330
1331 /* set Rx filter corner RCK offset */
1332 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, 0x2, 0x1);
1333 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, 0x3f, 0x3f);
1334 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, 0x2, 0x1);
1335 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, 0x3f, 0x3f);
1336 } else {
1337 rtw_dbg(rtwdev, RTW_DBG_COEX, "[BTCoex], Hi-Li Table Off!\n");
1338 for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_off); i++)
1339 rtw_write32(rtwdev, 0x81c, wl_rx_low_gain_off[i]);
1340
1341 /* set Rx filter corner RCK offset */
1342 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, 0x3f, 0x4);
1343 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, 0x2, 0x0);
1344 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, 0x3f, 0x4);
1345 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, 0x2, 0x0);
1346 }
1347 }
1348
rtw8822b_txagc_swing_offset(struct rtw_dev * rtwdev,u8 path,u8 tx_pwr_idx_offset,s8 * txagc_idx,u8 * swing_idx)1349 static void rtw8822b_txagc_swing_offset(struct rtw_dev *rtwdev, u8 path,
1350 u8 tx_pwr_idx_offset,
1351 s8 *txagc_idx, u8 *swing_idx)
1352 {
1353 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1354 s8 delta_pwr_idx = dm_info->delta_power_index[path];
1355 u8 swing_upper_bound = dm_info->default_ofdm_index + 10;
1356 u8 swing_lower_bound = 0;
1357 u8 max_tx_pwr_idx_offset = 0xf;
1358 s8 agc_index = 0;
1359 u8 swing_index = dm_info->default_ofdm_index;
1360
1361 tx_pwr_idx_offset = min_t(u8, tx_pwr_idx_offset, max_tx_pwr_idx_offset);
1362
1363 if (delta_pwr_idx >= 0) {
1364 if (delta_pwr_idx <= tx_pwr_idx_offset) {
1365 agc_index = delta_pwr_idx;
1366 swing_index = dm_info->default_ofdm_index;
1367 } else if (delta_pwr_idx > tx_pwr_idx_offset) {
1368 agc_index = tx_pwr_idx_offset;
1369 swing_index = dm_info->default_ofdm_index +
1370 delta_pwr_idx - tx_pwr_idx_offset;
1371 swing_index = min_t(u8, swing_index, swing_upper_bound);
1372 }
1373 } else {
1374 if (dm_info->default_ofdm_index > abs(delta_pwr_idx))
1375 swing_index =
1376 dm_info->default_ofdm_index + delta_pwr_idx;
1377 else
1378 swing_index = swing_lower_bound;
1379 swing_index = max_t(u8, swing_index, swing_lower_bound);
1380
1381 agc_index = 0;
1382 }
1383
1384 if (swing_index >= RTW_TXSCALE_SIZE) {
1385 rtw_warn(rtwdev, "swing index overflow\n");
1386 swing_index = RTW_TXSCALE_SIZE - 1;
1387 }
1388 *txagc_idx = agc_index;
1389 *swing_idx = swing_index;
1390 }
1391
rtw8822b_pwrtrack_set_pwr(struct rtw_dev * rtwdev,u8 path,u8 pwr_idx_offset)1392 static void rtw8822b_pwrtrack_set_pwr(struct rtw_dev *rtwdev, u8 path,
1393 u8 pwr_idx_offset)
1394 {
1395 s8 txagc_idx;
1396 u8 swing_idx;
1397 u32 reg1, reg2;
1398
1399 if (path == RF_PATH_A) {
1400 reg1 = 0xc94;
1401 reg2 = 0xc1c;
1402 } else if (path == RF_PATH_B) {
1403 reg1 = 0xe94;
1404 reg2 = 0xe1c;
1405 } else {
1406 return;
1407 }
1408
1409 rtw8822b_txagc_swing_offset(rtwdev, path, pwr_idx_offset,
1410 &txagc_idx, &swing_idx);
1411 rtw_write32_mask(rtwdev, reg1, GENMASK(29, 25), txagc_idx);
1412 rtw_write32_mask(rtwdev, reg2, GENMASK(31, 21),
1413 rtw8822b_txscale_tbl[swing_idx]);
1414 }
1415
rtw8822b_pwrtrack_set(struct rtw_dev * rtwdev,u8 path)1416 static void rtw8822b_pwrtrack_set(struct rtw_dev *rtwdev, u8 path)
1417 {
1418 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1419 u8 pwr_idx_offset, tx_pwr_idx;
1420 u8 channel = rtwdev->hal.current_channel;
1421 u8 band_width = rtwdev->hal.current_band_width;
1422 u8 regd = rtw_regd_get(rtwdev);
1423 u8 tx_rate = dm_info->tx_rate;
1424 u8 max_pwr_idx = rtwdev->chip->max_power_index;
1425
1426 tx_pwr_idx = rtw_phy_get_tx_power_index(rtwdev, path, tx_rate,
1427 band_width, channel, regd);
1428
1429 tx_pwr_idx = min_t(u8, tx_pwr_idx, max_pwr_idx);
1430
1431 pwr_idx_offset = max_pwr_idx - tx_pwr_idx;
1432
1433 rtw8822b_pwrtrack_set_pwr(rtwdev, path, pwr_idx_offset);
1434 }
1435
rtw8822b_phy_pwrtrack_path(struct rtw_dev * rtwdev,struct rtw_swing_table * swing_table,u8 path)1436 static void rtw8822b_phy_pwrtrack_path(struct rtw_dev *rtwdev,
1437 struct rtw_swing_table *swing_table,
1438 u8 path)
1439 {
1440 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1441 u8 power_idx_cur, power_idx_last;
1442 u8 delta;
1443
1444 /* 8822B only has one thermal meter at PATH A */
1445 delta = rtw_phy_pwrtrack_get_delta(rtwdev, RF_PATH_A);
1446
1447 power_idx_last = dm_info->delta_power_index[path];
1448 power_idx_cur = rtw_phy_pwrtrack_get_pwridx(rtwdev, swing_table,
1449 path, RF_PATH_A, delta);
1450
1451 /* if delta of power indexes are the same, just skip */
1452 if (power_idx_cur == power_idx_last)
1453 return;
1454
1455 dm_info->delta_power_index[path] = power_idx_cur;
1456 rtw8822b_pwrtrack_set(rtwdev, path);
1457 }
1458
rtw8822b_phy_pwrtrack(struct rtw_dev * rtwdev)1459 static void rtw8822b_phy_pwrtrack(struct rtw_dev *rtwdev)
1460 {
1461 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1462 struct rtw_swing_table swing_table;
1463 u8 thermal_value, path;
1464
1465 rtw_phy_config_swing_table(rtwdev, &swing_table);
1466
1467 if (rtwdev->efuse.thermal_meter[RF_PATH_A] == 0xff)
1468 return;
1469
1470 thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00);
1471
1472 rtw_phy_pwrtrack_avg(rtwdev, thermal_value, RF_PATH_A);
1473
1474 if (dm_info->pwr_trk_init_trigger)
1475 dm_info->pwr_trk_init_trigger = false;
1476 else if (!rtw_phy_pwrtrack_thermal_changed(rtwdev, thermal_value,
1477 RF_PATH_A))
1478 goto iqk;
1479
1480 for (path = 0; path < rtwdev->hal.rf_path_num; path++)
1481 rtw8822b_phy_pwrtrack_path(rtwdev, &swing_table, path);
1482
1483 iqk:
1484 if (rtw_phy_pwrtrack_need_iqk(rtwdev))
1485 rtw8822b_do_iqk(rtwdev);
1486 }
1487
rtw8822b_pwr_track(struct rtw_dev * rtwdev)1488 static void rtw8822b_pwr_track(struct rtw_dev *rtwdev)
1489 {
1490 struct rtw_efuse *efuse = &rtwdev->efuse;
1491 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1492
1493 if (efuse->power_track_type != 0)
1494 return;
1495
1496 if (!dm_info->pwr_trk_triggered) {
1497 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER,
1498 GENMASK(17, 16), 0x03);
1499 dm_info->pwr_trk_triggered = true;
1500 return;
1501 }
1502
1503 rtw8822b_phy_pwrtrack(rtwdev);
1504 dm_info->pwr_trk_triggered = false;
1505 }
1506
rtw8822b_bf_config_bfee_su(struct rtw_dev * rtwdev,struct rtw_vif * vif,struct rtw_bfee * bfee,bool enable)1507 static void rtw8822b_bf_config_bfee_su(struct rtw_dev *rtwdev,
1508 struct rtw_vif *vif,
1509 struct rtw_bfee *bfee, bool enable)
1510 {
1511 if (enable)
1512 rtw_bf_enable_bfee_su(rtwdev, vif, bfee);
1513 else
1514 rtw_bf_remove_bfee_su(rtwdev, bfee);
1515 }
1516
rtw8822b_bf_config_bfee_mu(struct rtw_dev * rtwdev,struct rtw_vif * vif,struct rtw_bfee * bfee,bool enable)1517 static void rtw8822b_bf_config_bfee_mu(struct rtw_dev *rtwdev,
1518 struct rtw_vif *vif,
1519 struct rtw_bfee *bfee, bool enable)
1520 {
1521 if (enable)
1522 rtw_bf_enable_bfee_mu(rtwdev, vif, bfee);
1523 else
1524 rtw_bf_remove_bfee_mu(rtwdev, bfee);
1525 }
1526
rtw8822b_bf_config_bfee(struct rtw_dev * rtwdev,struct rtw_vif * vif,struct rtw_bfee * bfee,bool enable)1527 static void rtw8822b_bf_config_bfee(struct rtw_dev *rtwdev, struct rtw_vif *vif,
1528 struct rtw_bfee *bfee, bool enable)
1529 {
1530 if (bfee->role == RTW_BFEE_SU)
1531 rtw8822b_bf_config_bfee_su(rtwdev, vif, bfee, enable);
1532 else if (bfee->role == RTW_BFEE_MU)
1533 rtw8822b_bf_config_bfee_mu(rtwdev, vif, bfee, enable);
1534 else
1535 rtw_warn(rtwdev, "wrong bfee role\n");
1536 }
1537
rtw8822b_adaptivity_init(struct rtw_dev * rtwdev)1538 static void rtw8822b_adaptivity_init(struct rtw_dev *rtwdev)
1539 {
1540 rtw_phy_set_edcca_th(rtwdev, RTW8822B_EDCCA_MAX, RTW8822B_EDCCA_MAX);
1541
1542 /* mac edcca state setting */
1543 rtw_write32_clr(rtwdev, REG_TX_PTCL_CTRL, BIT_DIS_EDCCA);
1544 rtw_write32_set(rtwdev, REG_RD_CTRL, BIT_EDCCA_MSK_CNTDOWN_EN);
1545 rtw_write32_mask(rtwdev, REG_EDCCA_SOURCE, BIT_SOURCE_OPTION,
1546 RTW8822B_EDCCA_SRC_DEF);
1547 rtw_write32_mask(rtwdev, REG_EDCCA_POW_MA, BIT_MA_LEVEL, 0);
1548
1549 /* edcca decision opt */
1550 rtw_write32_set(rtwdev, REG_EDCCA_DECISION, BIT_EDCCA_OPTION);
1551 }
1552
rtw8822b_adaptivity(struct rtw_dev * rtwdev)1553 static void rtw8822b_adaptivity(struct rtw_dev *rtwdev)
1554 {
1555 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1556 s8 l2h, h2l;
1557 u8 igi;
1558
1559 igi = dm_info->igi_history[0];
1560 if (dm_info->edcca_mode == RTW_EDCCA_NORMAL) {
1561 l2h = max_t(s8, igi + EDCCA_IGI_L2H_DIFF, EDCCA_TH_L2H_LB);
1562 h2l = l2h - EDCCA_L2H_H2L_DIFF_NORMAL;
1563 } else {
1564 l2h = min_t(s8, igi, dm_info->l2h_th_ini);
1565 h2l = l2h - EDCCA_L2H_H2L_DIFF;
1566 }
1567
1568 rtw_phy_set_edcca_th(rtwdev, l2h, h2l);
1569 }
1570
rtw8822b_led_set(struct led_classdev * led,enum led_brightness brightness)1571 static void rtw8822b_led_set(struct led_classdev *led,
1572 enum led_brightness brightness)
1573 {
1574 struct rtw_dev *rtwdev = container_of(led, struct rtw_dev, led_cdev);
1575 u32 ledcfg;
1576
1577 ledcfg = rtw_read32(rtwdev, REG_LED_CFG);
1578 u32p_replace_bits(&ledcfg, BIT_LED_MODE_SW_CTRL, BIT_LED2_CM);
1579 ledcfg &= ~BIT_GPIO13_14_WL_CTRL_EN;
1580
1581 if (brightness == LED_OFF)
1582 ledcfg |= BIT_LED2_SV;
1583 else
1584 ledcfg &= ~BIT_LED2_SV;
1585
1586 rtw_write32(rtwdev, REG_LED_CFG, ledcfg);
1587 }
1588
rtw8822b_fill_txdesc_checksum(struct rtw_dev * rtwdev,struct rtw_tx_pkt_info * pkt_info,u8 * txdesc)1589 static void rtw8822b_fill_txdesc_checksum(struct rtw_dev *rtwdev,
1590 struct rtw_tx_pkt_info *pkt_info,
1591 u8 *txdesc)
1592 {
1593 size_t words = 32 / 2; /* calculate the first 32 bytes (16 words) */
1594
1595 fill_txdesc_checksum_common(txdesc, words);
1596 }
1597
1598 static const struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8822b[] = {
1599 {0x0086,
1600 RTW_PWR_CUT_ALL_MSK,
1601 RTW_PWR_INTF_SDIO_MSK,
1602 RTW_PWR_ADDR_SDIO,
1603 RTW_PWR_CMD_WRITE, BIT(0), 0},
1604 {0x0086,
1605 RTW_PWR_CUT_ALL_MSK,
1606 RTW_PWR_INTF_SDIO_MSK,
1607 RTW_PWR_ADDR_SDIO,
1608 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
1609 {0x004A,
1610 RTW_PWR_CUT_ALL_MSK,
1611 RTW_PWR_INTF_USB_MSK,
1612 RTW_PWR_ADDR_MAC,
1613 RTW_PWR_CMD_WRITE, BIT(0), 0},
1614 {0x0005,
1615 RTW_PWR_CUT_ALL_MSK,
1616 RTW_PWR_INTF_ALL_MSK,
1617 RTW_PWR_ADDR_MAC,
1618 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0},
1619 {0x0300,
1620 RTW_PWR_CUT_ALL_MSK,
1621 RTW_PWR_INTF_PCI_MSK,
1622 RTW_PWR_ADDR_MAC,
1623 RTW_PWR_CMD_WRITE, 0xFF, 0},
1624 {0x0301,
1625 RTW_PWR_CUT_ALL_MSK,
1626 RTW_PWR_INTF_PCI_MSK,
1627 RTW_PWR_ADDR_MAC,
1628 RTW_PWR_CMD_WRITE, 0xFF, 0},
1629 {0xFFFF,
1630 RTW_PWR_CUT_ALL_MSK,
1631 RTW_PWR_INTF_ALL_MSK,
1632 0,
1633 RTW_PWR_CMD_END, 0, 0},
1634 };
1635
1636 static const struct rtw_pwr_seq_cmd trans_cardemu_to_act_8822b[] = {
1637 {0x0012,
1638 RTW_PWR_CUT_ALL_MSK,
1639 RTW_PWR_INTF_ALL_MSK,
1640 RTW_PWR_ADDR_MAC,
1641 RTW_PWR_CMD_WRITE, BIT(1), 0},
1642 {0x0012,
1643 RTW_PWR_CUT_ALL_MSK,
1644 RTW_PWR_INTF_ALL_MSK,
1645 RTW_PWR_ADDR_MAC,
1646 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1647 {0x0020,
1648 RTW_PWR_CUT_ALL_MSK,
1649 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1650 RTW_PWR_ADDR_MAC,
1651 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1652 {0x0001,
1653 RTW_PWR_CUT_ALL_MSK,
1654 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1655 RTW_PWR_ADDR_MAC,
1656 RTW_PWR_CMD_DELAY, 1, RTW_PWR_DELAY_MS},
1657 {0x0000,
1658 RTW_PWR_CUT_ALL_MSK,
1659 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1660 RTW_PWR_ADDR_MAC,
1661 RTW_PWR_CMD_WRITE, BIT(5), 0},
1662 {0x0005,
1663 RTW_PWR_CUT_ALL_MSK,
1664 RTW_PWR_INTF_ALL_MSK,
1665 RTW_PWR_ADDR_MAC,
1666 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
1667 {0x0075,
1668 RTW_PWR_CUT_ALL_MSK,
1669 RTW_PWR_INTF_PCI_MSK,
1670 RTW_PWR_ADDR_MAC,
1671 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1672 {0x0006,
1673 RTW_PWR_CUT_ALL_MSK,
1674 RTW_PWR_INTF_ALL_MSK,
1675 RTW_PWR_ADDR_MAC,
1676 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
1677 {0x0075,
1678 RTW_PWR_CUT_ALL_MSK,
1679 RTW_PWR_INTF_PCI_MSK,
1680 RTW_PWR_ADDR_MAC,
1681 RTW_PWR_CMD_WRITE, BIT(0), 0},
1682 {0xFF1A,
1683 RTW_PWR_CUT_ALL_MSK,
1684 RTW_PWR_INTF_USB_MSK,
1685 RTW_PWR_ADDR_MAC,
1686 RTW_PWR_CMD_WRITE, 0xFF, 0},
1687 {0x0006,
1688 RTW_PWR_CUT_ALL_MSK,
1689 RTW_PWR_INTF_ALL_MSK,
1690 RTW_PWR_ADDR_MAC,
1691 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1692 {0x0005,
1693 RTW_PWR_CUT_ALL_MSK,
1694 RTW_PWR_INTF_ALL_MSK,
1695 RTW_PWR_ADDR_MAC,
1696 RTW_PWR_CMD_WRITE, BIT(7), 0},
1697 {0x0005,
1698 RTW_PWR_CUT_ALL_MSK,
1699 RTW_PWR_INTF_ALL_MSK,
1700 RTW_PWR_ADDR_MAC,
1701 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
1702 {0x10C3,
1703 RTW_PWR_CUT_ALL_MSK,
1704 RTW_PWR_INTF_USB_MSK,
1705 RTW_PWR_ADDR_MAC,
1706 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1707 {0x0005,
1708 RTW_PWR_CUT_ALL_MSK,
1709 RTW_PWR_INTF_ALL_MSK,
1710 RTW_PWR_ADDR_MAC,
1711 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1712 {0x0005,
1713 RTW_PWR_CUT_ALL_MSK,
1714 RTW_PWR_INTF_ALL_MSK,
1715 RTW_PWR_ADDR_MAC,
1716 RTW_PWR_CMD_POLLING, BIT(0), 0},
1717 {0x0020,
1718 RTW_PWR_CUT_ALL_MSK,
1719 RTW_PWR_INTF_ALL_MSK,
1720 RTW_PWR_ADDR_MAC,
1721 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)},
1722 {0x10A8,
1723 RTW_PWR_CUT_C_MSK,
1724 RTW_PWR_INTF_ALL_MSK,
1725 RTW_PWR_ADDR_MAC,
1726 RTW_PWR_CMD_WRITE, 0xFF, 0},
1727 {0x10A9,
1728 RTW_PWR_CUT_C_MSK,
1729 RTW_PWR_INTF_ALL_MSK,
1730 RTW_PWR_ADDR_MAC,
1731 RTW_PWR_CMD_WRITE, 0xFF, 0xef},
1732 {0x10AA,
1733 RTW_PWR_CUT_C_MSK,
1734 RTW_PWR_INTF_ALL_MSK,
1735 RTW_PWR_ADDR_MAC,
1736 RTW_PWR_CMD_WRITE, 0xFF, 0x0c},
1737 {0x0068,
1738 RTW_PWR_CUT_C_MSK,
1739 RTW_PWR_INTF_SDIO_MSK,
1740 RTW_PWR_ADDR_MAC,
1741 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)},
1742 {0x0029,
1743 RTW_PWR_CUT_ALL_MSK,
1744 RTW_PWR_INTF_ALL_MSK,
1745 RTW_PWR_ADDR_MAC,
1746 RTW_PWR_CMD_WRITE, 0xFF, 0xF9},
1747 {0x0024,
1748 RTW_PWR_CUT_ALL_MSK,
1749 RTW_PWR_INTF_ALL_MSK,
1750 RTW_PWR_ADDR_MAC,
1751 RTW_PWR_CMD_WRITE, BIT(2), 0},
1752 {0x0074,
1753 RTW_PWR_CUT_ALL_MSK,
1754 RTW_PWR_INTF_PCI_MSK,
1755 RTW_PWR_ADDR_MAC,
1756 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1757 {0x00AF,
1758 RTW_PWR_CUT_ALL_MSK,
1759 RTW_PWR_INTF_ALL_MSK,
1760 RTW_PWR_ADDR_MAC,
1761 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1762 {0xFFFF,
1763 RTW_PWR_CUT_ALL_MSK,
1764 RTW_PWR_INTF_ALL_MSK,
1765 0,
1766 RTW_PWR_CMD_END, 0, 0},
1767 };
1768
1769 static const struct rtw_pwr_seq_cmd trans_act_to_cardemu_8822b[] = {
1770 {0x0003,
1771 RTW_PWR_CUT_ALL_MSK,
1772 RTW_PWR_INTF_SDIO_MSK,
1773 RTW_PWR_ADDR_MAC,
1774 RTW_PWR_CMD_WRITE, BIT(2), 0},
1775 {0x0093,
1776 RTW_PWR_CUT_ALL_MSK,
1777 RTW_PWR_INTF_ALL_MSK,
1778 RTW_PWR_ADDR_MAC,
1779 RTW_PWR_CMD_WRITE, BIT(3), 0},
1780 {0x001F,
1781 RTW_PWR_CUT_ALL_MSK,
1782 RTW_PWR_INTF_ALL_MSK,
1783 RTW_PWR_ADDR_MAC,
1784 RTW_PWR_CMD_WRITE, 0xFF, 0},
1785 {0x00EF,
1786 RTW_PWR_CUT_ALL_MSK,
1787 RTW_PWR_INTF_ALL_MSK,
1788 RTW_PWR_ADDR_MAC,
1789 RTW_PWR_CMD_WRITE, 0xFF, 0},
1790 {0xFF1A,
1791 RTW_PWR_CUT_ALL_MSK,
1792 RTW_PWR_INTF_USB_MSK,
1793 RTW_PWR_ADDR_MAC,
1794 RTW_PWR_CMD_WRITE, 0xFF, 0x30},
1795 {0x0049,
1796 RTW_PWR_CUT_ALL_MSK,
1797 RTW_PWR_INTF_ALL_MSK,
1798 RTW_PWR_ADDR_MAC,
1799 RTW_PWR_CMD_WRITE, BIT(1), 0},
1800 {0x0006,
1801 RTW_PWR_CUT_ALL_MSK,
1802 RTW_PWR_INTF_ALL_MSK,
1803 RTW_PWR_ADDR_MAC,
1804 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1805 {0x0002,
1806 RTW_PWR_CUT_ALL_MSK,
1807 RTW_PWR_INTF_ALL_MSK,
1808 RTW_PWR_ADDR_MAC,
1809 RTW_PWR_CMD_WRITE, BIT(1), 0},
1810 {0x10C3,
1811 RTW_PWR_CUT_ALL_MSK,
1812 RTW_PWR_INTF_USB_MSK,
1813 RTW_PWR_ADDR_MAC,
1814 RTW_PWR_CMD_WRITE, BIT(0), 0},
1815 {0x0005,
1816 RTW_PWR_CUT_ALL_MSK,
1817 RTW_PWR_INTF_ALL_MSK,
1818 RTW_PWR_ADDR_MAC,
1819 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
1820 {0x0005,
1821 RTW_PWR_CUT_ALL_MSK,
1822 RTW_PWR_INTF_ALL_MSK,
1823 RTW_PWR_ADDR_MAC,
1824 RTW_PWR_CMD_POLLING, BIT(1), 0},
1825 {0x0020,
1826 RTW_PWR_CUT_ALL_MSK,
1827 RTW_PWR_INTF_ALL_MSK,
1828 RTW_PWR_ADDR_MAC,
1829 RTW_PWR_CMD_WRITE, BIT(3), 0},
1830 {0x0000,
1831 RTW_PWR_CUT_ALL_MSK,
1832 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1833 RTW_PWR_ADDR_MAC,
1834 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1835 {0xFFFF,
1836 RTW_PWR_CUT_ALL_MSK,
1837 RTW_PWR_INTF_ALL_MSK,
1838 0,
1839 RTW_PWR_CMD_END, 0, 0},
1840 };
1841
1842 static const struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8822b[] = {
1843 {0x0005,
1844 RTW_PWR_CUT_ALL_MSK,
1845 RTW_PWR_INTF_SDIO_MSK,
1846 RTW_PWR_ADDR_MAC,
1847 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)},
1848 {0x0007,
1849 RTW_PWR_CUT_ALL_MSK,
1850 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1851 RTW_PWR_ADDR_MAC,
1852 RTW_PWR_CMD_WRITE, 0xFF, 0x20},
1853 {0x0067,
1854 RTW_PWR_CUT_ALL_MSK,
1855 RTW_PWR_INTF_ALL_MSK,
1856 RTW_PWR_ADDR_MAC,
1857 RTW_PWR_CMD_WRITE, BIT(5), 0},
1858 {0x0005,
1859 RTW_PWR_CUT_ALL_MSK,
1860 RTW_PWR_INTF_PCI_MSK,
1861 RTW_PWR_ADDR_MAC,
1862 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)},
1863 {0x004A,
1864 RTW_PWR_CUT_ALL_MSK,
1865 RTW_PWR_INTF_USB_MSK,
1866 RTW_PWR_ADDR_MAC,
1867 RTW_PWR_CMD_WRITE, BIT(0), 0},
1868 {0x0067,
1869 RTW_PWR_CUT_ALL_MSK,
1870 RTW_PWR_INTF_SDIO_MSK,
1871 RTW_PWR_ADDR_MAC,
1872 RTW_PWR_CMD_WRITE, BIT(5), 0},
1873 {0x0067,
1874 RTW_PWR_CUT_ALL_MSK,
1875 RTW_PWR_INTF_SDIO_MSK,
1876 RTW_PWR_ADDR_MAC,
1877 RTW_PWR_CMD_WRITE, BIT(4), 0},
1878 {0x004F,
1879 RTW_PWR_CUT_ALL_MSK,
1880 RTW_PWR_INTF_SDIO_MSK,
1881 RTW_PWR_ADDR_MAC,
1882 RTW_PWR_CMD_WRITE, BIT(0), 0},
1883 {0x0067,
1884 RTW_PWR_CUT_ALL_MSK,
1885 RTW_PWR_INTF_SDIO_MSK,
1886 RTW_PWR_ADDR_MAC,
1887 RTW_PWR_CMD_WRITE, BIT(1), 0},
1888 {0x0046,
1889 RTW_PWR_CUT_ALL_MSK,
1890 RTW_PWR_INTF_SDIO_MSK,
1891 RTW_PWR_ADDR_MAC,
1892 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)},
1893 {0x0067,
1894 RTW_PWR_CUT_ALL_MSK,
1895 RTW_PWR_INTF_SDIO_MSK,
1896 RTW_PWR_ADDR_MAC,
1897 RTW_PWR_CMD_WRITE, BIT(2), 0},
1898 {0x0046,
1899 RTW_PWR_CUT_ALL_MSK,
1900 RTW_PWR_INTF_SDIO_MSK,
1901 RTW_PWR_ADDR_MAC,
1902 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)},
1903 {0x0062,
1904 RTW_PWR_CUT_ALL_MSK,
1905 RTW_PWR_INTF_SDIO_MSK,
1906 RTW_PWR_ADDR_MAC,
1907 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)},
1908 {0x0081,
1909 RTW_PWR_CUT_ALL_MSK,
1910 RTW_PWR_INTF_ALL_MSK,
1911 RTW_PWR_ADDR_MAC,
1912 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0},
1913 {0x0005,
1914 RTW_PWR_CUT_ALL_MSK,
1915 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1916 RTW_PWR_ADDR_MAC,
1917 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)},
1918 {0x0086,
1919 RTW_PWR_CUT_ALL_MSK,
1920 RTW_PWR_INTF_SDIO_MSK,
1921 RTW_PWR_ADDR_SDIO,
1922 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1923 {0x0086,
1924 RTW_PWR_CUT_ALL_MSK,
1925 RTW_PWR_INTF_SDIO_MSK,
1926 RTW_PWR_ADDR_SDIO,
1927 RTW_PWR_CMD_POLLING, BIT(1), 0},
1928 {0x0090,
1929 RTW_PWR_CUT_ALL_MSK,
1930 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_PCI_MSK,
1931 RTW_PWR_ADDR_MAC,
1932 RTW_PWR_CMD_WRITE, BIT(1), 0},
1933 {0x0044,
1934 RTW_PWR_CUT_ALL_MSK,
1935 RTW_PWR_INTF_SDIO_MSK,
1936 RTW_PWR_ADDR_SDIO,
1937 RTW_PWR_CMD_WRITE, 0xFF, 0},
1938 {0x0040,
1939 RTW_PWR_CUT_ALL_MSK,
1940 RTW_PWR_INTF_SDIO_MSK,
1941 RTW_PWR_ADDR_SDIO,
1942 RTW_PWR_CMD_WRITE, 0xFF, 0x90},
1943 {0x0041,
1944 RTW_PWR_CUT_ALL_MSK,
1945 RTW_PWR_INTF_SDIO_MSK,
1946 RTW_PWR_ADDR_SDIO,
1947 RTW_PWR_CMD_WRITE, 0xFF, 0x00},
1948 {0x0042,
1949 RTW_PWR_CUT_ALL_MSK,
1950 RTW_PWR_INTF_SDIO_MSK,
1951 RTW_PWR_ADDR_SDIO,
1952 RTW_PWR_CMD_WRITE, 0xFF, 0x04},
1953 {0xFFFF,
1954 RTW_PWR_CUT_ALL_MSK,
1955 RTW_PWR_INTF_ALL_MSK,
1956 0,
1957 RTW_PWR_CMD_END, 0, 0},
1958 };
1959
1960 static const struct rtw_pwr_seq_cmd * const card_enable_flow_8822b[] = {
1961 trans_carddis_to_cardemu_8822b,
1962 trans_cardemu_to_act_8822b,
1963 NULL
1964 };
1965
1966 static const struct rtw_pwr_seq_cmd * const card_disable_flow_8822b[] = {
1967 trans_act_to_cardemu_8822b,
1968 trans_cardemu_to_carddis_8822b,
1969 NULL
1970 };
1971
1972 static const struct rtw_intf_phy_para usb2_param_8822b[] = {
1973 {0xFFFF, 0x00,
1974 RTW_IP_SEL_PHY,
1975 RTW_INTF_PHY_CUT_ALL,
1976 RTW_INTF_PHY_PLATFORM_ALL},
1977 };
1978
1979 static const struct rtw_intf_phy_para usb3_param_8822b[] = {
1980 {0x0001, 0xA841,
1981 RTW_IP_SEL_PHY,
1982 RTW_INTF_PHY_CUT_D,
1983 RTW_INTF_PHY_PLATFORM_ALL},
1984 {0xFFFF, 0x0000,
1985 RTW_IP_SEL_PHY,
1986 RTW_INTF_PHY_CUT_ALL,
1987 RTW_INTF_PHY_PLATFORM_ALL},
1988 };
1989
1990 static const struct rtw_intf_phy_para pcie_gen1_param_8822b[] = {
1991 {0x0001, 0xA841,
1992 RTW_IP_SEL_PHY,
1993 RTW_INTF_PHY_CUT_C,
1994 RTW_INTF_PHY_PLATFORM_ALL},
1995 {0x0002, 0x60C6,
1996 RTW_IP_SEL_PHY,
1997 RTW_INTF_PHY_CUT_C,
1998 RTW_INTF_PHY_PLATFORM_ALL},
1999 {0x0008, 0x3596,
2000 RTW_IP_SEL_PHY,
2001 RTW_INTF_PHY_CUT_C,
2002 RTW_INTF_PHY_PLATFORM_ALL},
2003 {0x0009, 0x321C,
2004 RTW_IP_SEL_PHY,
2005 RTW_INTF_PHY_CUT_C,
2006 RTW_INTF_PHY_PLATFORM_ALL},
2007 {0x000A, 0x9623,
2008 RTW_IP_SEL_PHY,
2009 RTW_INTF_PHY_CUT_C,
2010 RTW_INTF_PHY_PLATFORM_ALL},
2011 {0x0020, 0x94FF,
2012 RTW_IP_SEL_PHY,
2013 RTW_INTF_PHY_CUT_C,
2014 RTW_INTF_PHY_PLATFORM_ALL},
2015 {0x0021, 0xFFCF,
2016 RTW_IP_SEL_PHY,
2017 RTW_INTF_PHY_CUT_C,
2018 RTW_INTF_PHY_PLATFORM_ALL},
2019 {0x0026, 0xC006,
2020 RTW_IP_SEL_PHY,
2021 RTW_INTF_PHY_CUT_C,
2022 RTW_INTF_PHY_PLATFORM_ALL},
2023 {0x0029, 0xFF0E,
2024 RTW_IP_SEL_PHY,
2025 RTW_INTF_PHY_CUT_C,
2026 RTW_INTF_PHY_PLATFORM_ALL},
2027 {0x002A, 0x1840,
2028 RTW_IP_SEL_PHY,
2029 RTW_INTF_PHY_CUT_C,
2030 RTW_INTF_PHY_PLATFORM_ALL},
2031 {0xFFFF, 0x0000,
2032 RTW_IP_SEL_PHY,
2033 RTW_INTF_PHY_CUT_ALL,
2034 RTW_INTF_PHY_PLATFORM_ALL},
2035 };
2036
2037 static const struct rtw_intf_phy_para pcie_gen2_param_8822b[] = {
2038 {0x0001, 0xA841,
2039 RTW_IP_SEL_PHY,
2040 RTW_INTF_PHY_CUT_C,
2041 RTW_INTF_PHY_PLATFORM_ALL},
2042 {0x0002, 0x60C6,
2043 RTW_IP_SEL_PHY,
2044 RTW_INTF_PHY_CUT_C,
2045 RTW_INTF_PHY_PLATFORM_ALL},
2046 {0x0008, 0x3597,
2047 RTW_IP_SEL_PHY,
2048 RTW_INTF_PHY_CUT_C,
2049 RTW_INTF_PHY_PLATFORM_ALL},
2050 {0x0009, 0x321C,
2051 RTW_IP_SEL_PHY,
2052 RTW_INTF_PHY_CUT_C,
2053 RTW_INTF_PHY_PLATFORM_ALL},
2054 {0x000A, 0x9623,
2055 RTW_IP_SEL_PHY,
2056 RTW_INTF_PHY_CUT_C,
2057 RTW_INTF_PHY_PLATFORM_ALL},
2058 {0x0020, 0x94FF,
2059 RTW_IP_SEL_PHY,
2060 RTW_INTF_PHY_CUT_C,
2061 RTW_INTF_PHY_PLATFORM_ALL},
2062 {0x0021, 0xFFCF,
2063 RTW_IP_SEL_PHY,
2064 RTW_INTF_PHY_CUT_C,
2065 RTW_INTF_PHY_PLATFORM_ALL},
2066 {0x0026, 0xC006,
2067 RTW_IP_SEL_PHY,
2068 RTW_INTF_PHY_CUT_C,
2069 RTW_INTF_PHY_PLATFORM_ALL},
2070 {0x0029, 0xFF0E,
2071 RTW_IP_SEL_PHY,
2072 RTW_INTF_PHY_CUT_C,
2073 RTW_INTF_PHY_PLATFORM_ALL},
2074 {0x002A, 0x3040,
2075 RTW_IP_SEL_PHY,
2076 RTW_INTF_PHY_CUT_C,
2077 RTW_INTF_PHY_PLATFORM_ALL},
2078 {0xFFFF, 0x0000,
2079 RTW_IP_SEL_PHY,
2080 RTW_INTF_PHY_CUT_ALL,
2081 RTW_INTF_PHY_PLATFORM_ALL},
2082 };
2083
2084 static const struct rtw_intf_phy_para_table phy_para_table_8822b = {
2085 .usb2_para = usb2_param_8822b,
2086 .usb3_para = usb3_param_8822b,
2087 .gen1_para = pcie_gen1_param_8822b,
2088 .gen2_para = pcie_gen2_param_8822b,
2089 .n_usb2_para = ARRAY_SIZE(usb2_param_8822b),
2090 .n_usb3_para = ARRAY_SIZE(usb2_param_8822b),
2091 .n_gen1_para = ARRAY_SIZE(pcie_gen1_param_8822b),
2092 .n_gen2_para = ARRAY_SIZE(pcie_gen2_param_8822b),
2093 };
2094
2095 static const struct rtw_hw_reg rtw8822b_dig[] = {
2096 [0] = { .addr = 0xc50, .mask = 0x7f },
2097 [1] = { .addr = 0xe50, .mask = 0x7f },
2098 };
2099
2100 static const struct rtw_ltecoex_addr rtw8822b_ltecoex_addr = {
2101 .ctrl = LTECOEX_ACCESS_CTRL,
2102 .wdata = LTECOEX_WRITE_DATA,
2103 .rdata = LTECOEX_READ_DATA,
2104 };
2105
2106 static const struct rtw_page_table page_table_8822b[] = {
2107 {64, 64, 64, 64, 1},
2108 {64, 64, 64, 64, 1},
2109 {64, 64, 0, 0, 1},
2110 {64, 64, 64, 0, 1},
2111 {64, 64, 64, 64, 1},
2112 };
2113
2114 static const struct rtw_rqpn rqpn_table_8822b[] = {
2115 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
2116 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
2117 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
2118 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
2119 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
2120 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
2121 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
2122 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH,
2123 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
2124 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
2125 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
2126 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
2127 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
2128 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
2129 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
2130 };
2131
2132 static const struct rtw_prioq_addrs prioq_addrs_8822b = {
2133 .prio[RTW_DMA_MAPPING_EXTRA] = {
2134 .rsvd = REG_FIFOPAGE_INFO_4, .avail = REG_FIFOPAGE_INFO_4 + 2,
2135 },
2136 .prio[RTW_DMA_MAPPING_LOW] = {
2137 .rsvd = REG_FIFOPAGE_INFO_2, .avail = REG_FIFOPAGE_INFO_2 + 2,
2138 },
2139 .prio[RTW_DMA_MAPPING_NORMAL] = {
2140 .rsvd = REG_FIFOPAGE_INFO_3, .avail = REG_FIFOPAGE_INFO_3 + 2,
2141 },
2142 .prio[RTW_DMA_MAPPING_HIGH] = {
2143 .rsvd = REG_FIFOPAGE_INFO_1, .avail = REG_FIFOPAGE_INFO_1 + 2,
2144 },
2145 .wsize = true,
2146 };
2147
2148 static const struct rtw_chip_ops rtw8822b_ops = {
2149 .power_on = rtw_power_on,
2150 .power_off = rtw_power_off,
2151 .phy_set_param = rtw8822b_phy_set_param,
2152 .read_efuse = rtw8822b_read_efuse,
2153 .query_phy_status = query_phy_status,
2154 .set_channel = rtw8822b_set_channel,
2155 .mac_init = rtw8822b_mac_init,
2156 .read_rf = rtw_phy_read_rf,
2157 .write_rf = rtw_phy_write_rf_reg_sipi,
2158 .set_tx_power_index = rtw8822b_set_tx_power_index,
2159 .set_antenna = rtw8822b_set_antenna,
2160 .cfg_ldo25 = rtw8822b_cfg_ldo25,
2161 .false_alarm_statistics = rtw8822b_false_alarm_statistics,
2162 .phy_calibration = rtw8822b_phy_calibration,
2163 .pwr_track = rtw8822b_pwr_track,
2164 .config_bfee = rtw8822b_bf_config_bfee,
2165 .set_gid_table = rtw_bf_set_gid_table,
2166 .cfg_csi_rate = rtw_bf_cfg_csi_rate,
2167 .adaptivity_init = rtw8822b_adaptivity_init,
2168 .adaptivity = rtw8822b_adaptivity,
2169 .led_set = rtw8822b_led_set,
2170 .fill_txdesc_checksum = rtw8822b_fill_txdesc_checksum,
2171
2172 .coex_set_init = rtw8822b_coex_cfg_init,
2173 .coex_set_ant_switch = rtw8822b_coex_cfg_ant_switch,
2174 .coex_set_gnt_fix = rtw8822b_coex_cfg_gnt_fix,
2175 .coex_set_gnt_debug = rtw8822b_coex_cfg_gnt_debug,
2176 .coex_set_rfe_type = rtw8822b_coex_cfg_rfe_type,
2177 .coex_set_wl_tx_power = rtw8822b_coex_cfg_wl_tx_power,
2178 .coex_set_wl_rx_gain = rtw8822b_coex_cfg_wl_rx_gain,
2179 };
2180
2181 /* Shared-Antenna Coex Table */
2182 static const struct coex_table_para table_sant_8822b[] = {
2183 {0xffffffff, 0xffffffff}, /* case-0 */
2184 {0x55555555, 0x55555555},
2185 {0x66555555, 0x66555555},
2186 {0xaaaaaaaa, 0xaaaaaaaa},
2187 {0x5a5a5a5a, 0x5a5a5a5a},
2188 {0xfafafafa, 0xfafafafa}, /* case-5 */
2189 {0x6a5a5555, 0xaaaaaaaa},
2190 {0x6a5a56aa, 0x6a5a56aa},
2191 {0x6a5a5a5a, 0x6a5a5a5a},
2192 {0x66555555, 0x5a5a5a5a},
2193 {0x66555555, 0x6a5a5a5a}, /* case-10 */
2194 {0x66555555, 0xfafafafa},
2195 {0x66555555, 0x5a5a5aaa},
2196 {0x66555555, 0x6aaa5aaa},
2197 {0x66555555, 0xaaaa5aaa},
2198 {0x66555555, 0xaaaaaaaa}, /* case-15 */
2199 {0xffff55ff, 0xfafafafa},
2200 {0xffff55ff, 0x6afa5afa},
2201 {0xaaffffaa, 0xfafafafa},
2202 {0xaa5555aa, 0x5a5a5a5a},
2203 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
2204 {0xaa5555aa, 0xaaaaaaaa},
2205 {0xffffffff, 0x5a5a5a5a},
2206 {0xffffffff, 0x5a5a5a5a},
2207 {0xffffffff, 0x55555555},
2208 {0xffffffff, 0x6a5a5aaa}, /* case-25 */
2209 {0x55555555, 0x5a5a5a5a},
2210 {0x55555555, 0xaaaaaaaa},
2211 {0x55555555, 0x6a5a6a5a},
2212 {0x66556655, 0x66556655},
2213 {0x66556aaa, 0x6a5a6aaa}, /* case-30 */
2214 {0xffffffff, 0x5aaa5aaa},
2215 {0x56555555, 0x5a5a5aaa},
2216 };
2217
2218 /* Non-Shared-Antenna Coex Table */
2219 static const struct coex_table_para table_nsant_8822b[] = {
2220 {0xffffffff, 0xffffffff}, /* case-100 */
2221 {0x55555555, 0x55555555},
2222 {0x66555555, 0x66555555},
2223 {0xaaaaaaaa, 0xaaaaaaaa},
2224 {0x5a5a5a5a, 0x5a5a5a5a},
2225 {0xfafafafa, 0xfafafafa}, /* case-105 */
2226 {0x5afa5afa, 0x5afa5afa},
2227 {0x55555555, 0xfafafafa},
2228 {0x66555555, 0xfafafafa},
2229 {0x66555555, 0x5a5a5a5a},
2230 {0x66555555, 0x6a5a5a5a}, /* case-110 */
2231 {0x66555555, 0xaaaaaaaa},
2232 {0xffff55ff, 0xfafafafa},
2233 {0xffff55ff, 0x5afa5afa},
2234 {0xffff55ff, 0xaaaaaaaa},
2235 {0xffff55ff, 0xffff55ff}, /* case-115 */
2236 {0xaaffffaa, 0x5afa5afa},
2237 {0xaaffffaa, 0xaaaaaaaa},
2238 {0xffffffff, 0xfafafafa},
2239 {0xffffffff, 0x5afa5afa},
2240 {0xffffffff, 0xaaaaaaaa}, /* case-120 */
2241 {0x55ff55ff, 0x5afa5afa},
2242 {0x55ff55ff, 0xaaaaaaaa},
2243 {0x55ff55ff, 0x55ff55ff}
2244 };
2245
2246 /* Shared-Antenna TDMA */
2247 static const struct coex_tdma_para tdma_sant_8822b[] = {
2248 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
2249 { {0x61, 0x45, 0x03, 0x11, 0x11} },
2250 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
2251 { {0x61, 0x30, 0x03, 0x11, 0x11} },
2252 { {0x61, 0x20, 0x03, 0x11, 0x11} },
2253 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */
2254 { {0x61, 0x45, 0x03, 0x11, 0x10} },
2255 { {0x61, 0x3a, 0x03, 0x11, 0x10} },
2256 { {0x61, 0x30, 0x03, 0x11, 0x10} },
2257 { {0x61, 0x20, 0x03, 0x11, 0x10} },
2258 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
2259 { {0x61, 0x08, 0x03, 0x11, 0x14} },
2260 { {0x61, 0x08, 0x03, 0x10, 0x14} },
2261 { {0x51, 0x08, 0x03, 0x10, 0x54} },
2262 { {0x51, 0x08, 0x03, 0x10, 0x55} },
2263 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
2264 { {0x51, 0x45, 0x03, 0x10, 0x50} },
2265 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
2266 { {0x51, 0x30, 0x03, 0x10, 0x50} },
2267 { {0x51, 0x20, 0x03, 0x10, 0x50} },
2268 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
2269 { {0x51, 0x4a, 0x03, 0x10, 0x50} },
2270 { {0x51, 0x0c, 0x03, 0x10, 0x54} },
2271 { {0x55, 0x08, 0x03, 0x10, 0x54} },
2272 { {0x65, 0x10, 0x03, 0x11, 0x10} },
2273 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
2274 { {0x51, 0x08, 0x03, 0x10, 0x50} },
2275 { {0x61, 0x08, 0x03, 0x11, 0x11} }
2276 };
2277
2278 /* Non-Shared-Antenna TDMA */
2279 static const struct coex_tdma_para tdma_nsant_8822b[] = {
2280 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-100 */
2281 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-101 */
2282 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
2283 { {0x61, 0x30, 0x03, 0x11, 0x11} },
2284 { {0x61, 0x20, 0x03, 0x11, 0x11} },
2285 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */
2286 { {0x61, 0x45, 0x03, 0x11, 0x10} },
2287 { {0x61, 0x3a, 0x03, 0x11, 0x10} },
2288 { {0x61, 0x30, 0x03, 0x11, 0x10} },
2289 { {0x61, 0x20, 0x03, 0x11, 0x10} },
2290 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */
2291 { {0x61, 0x08, 0x03, 0x11, 0x14} },
2292 { {0x61, 0x08, 0x03, 0x10, 0x14} },
2293 { {0x51, 0x08, 0x03, 0x10, 0x54} },
2294 { {0x51, 0x08, 0x03, 0x10, 0x55} },
2295 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */
2296 { {0x51, 0x45, 0x03, 0x10, 0x50} },
2297 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
2298 { {0x51, 0x30, 0x03, 0x10, 0x50} },
2299 { {0x51, 0x20, 0x03, 0x10, 0x50} },
2300 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-120 */
2301 { {0x51, 0x08, 0x03, 0x10, 0x50} }
2302 };
2303
2304 /* rssi in percentage % (dbm = % - 100) */
2305 static const u8 wl_rssi_step_8822b[] = {60, 50, 44, 30};
2306 static const u8 bt_rssi_step_8822b[] = {30, 30, 30, 30};
2307
2308 /* wl_tx_dec_power, bt_tx_dec_power, wl_rx_gain, bt_rx_lna_constrain */
2309 static const struct coex_rf_para rf_para_tx_8822b[] = {
2310 {0, 0, false, 7}, /* for normal */
2311 {0, 16, false, 7}, /* for WL-CPT */
2312 {4, 0, true, 1},
2313 {3, 6, true, 1},
2314 {2, 9, true, 1},
2315 {1, 13, true, 1}
2316 };
2317
2318 static const struct coex_rf_para rf_para_rx_8822b[] = {
2319 {0, 0, false, 7}, /* for normal */
2320 {0, 16, false, 7}, /* for WL-CPT */
2321 {4, 0, true, 1},
2322 {3, 6, true, 1},
2323 {2, 9, true, 1},
2324 {1, 13, true, 1}
2325 };
2326
2327 static const struct coex_5g_afh_map afh_5g_8822b[] = {
2328 {120, 2, 4},
2329 {124, 8, 8},
2330 {128, 17, 8},
2331 {132, 26, 10},
2332 {136, 34, 8},
2333 {140, 42, 10},
2334 {144, 51, 8},
2335 {149, 62, 8},
2336 {153, 71, 10},
2337 {157, 77, 4},
2338 {118, 2, 4},
2339 {126, 12, 16},
2340 {134, 29, 16},
2341 {142, 46, 16},
2342 {151, 66, 16},
2343 {159, 76, 4},
2344 {122, 10, 20},
2345 {138, 37, 34},
2346 {155, 68, 20}
2347 };
2348 static_assert(ARRAY_SIZE(rf_para_tx_8822b) == ARRAY_SIZE(rf_para_rx_8822b));
2349
2350 static const u8
2351 rtw8822b_pwrtrk_5gb_n[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = {
2352 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2353 8, 8, 9, 10, 11, 11, 12, 13, 14, 14,
2354 15, 16, 17, 17, 18, 19, 20, 20, 21, 22 },
2355 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2356 8, 8, 9, 10, 11, 11, 12, 13, 14, 14,
2357 15, 16, 17, 17, 18, 19, 20, 20, 21, 22 },
2358 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2359 8, 8, 9, 10, 11, 11, 12, 13, 14, 14,
2360 15, 16, 17, 17, 18, 19, 20, 20, 21, 22 },
2361 };
2362
2363 static const u8
2364 rtw8822b_pwrtrk_5gb_p[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = {
2365 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2366 8, 9, 9, 10, 11, 12, 13, 14, 14, 15,
2367 16, 17, 18, 19, 19, 20, 21, 22, 22, 23 },
2368 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2369 8, 9, 9, 10, 11, 12, 13, 14, 14, 15,
2370 16, 17, 18, 19, 19, 20, 21, 22, 22, 23 },
2371 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2372 8, 9, 9, 10, 11, 12, 13, 14, 14, 15,
2373 16, 17, 18, 19, 19, 20, 21, 22, 22, 23 },
2374 };
2375
2376 static const u8
2377 rtw8822b_pwrtrk_5ga_n[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = {
2378 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2379 8, 8, 9, 10, 11, 11, 12, 13, 14, 14,
2380 15, 16, 17, 17, 18, 19, 20, 20, 21, 22 },
2381 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2382 8, 8, 9, 10, 11, 11, 12, 13, 14, 14,
2383 15, 16, 17, 17, 18, 19, 20, 20, 21, 22 },
2384 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2385 8, 8, 9, 10, 11, 11, 12, 13, 14, 14,
2386 15, 16, 17, 17, 18, 19, 20, 20, 21, 22 },
2387 };
2388
2389 static const u8
2390 rtw8822b_pwrtrk_5ga_p[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = {
2391 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2392 8, 9, 9, 10, 11, 12, 13, 14, 14, 15,
2393 16, 17, 18, 19, 19, 20, 21, 22, 22, 23},
2394 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2395 8, 9, 9, 10, 11, 12, 13, 14, 14, 15,
2396 16, 17, 18, 19, 19, 20, 21, 22, 22, 23},
2397 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2398 8, 9, 9, 10, 11, 12, 13, 14, 14, 15,
2399 16, 17, 18, 19, 19, 20, 21, 22, 22, 23},
2400 };
2401
2402 static const u8 rtw8822b_pwrtrk_2gb_n[RTW_PWR_TRK_TBL_SZ] = {
2403 0, 1, 1, 1, 2, 2, 3, 3, 3, 4,
2404 4, 5, 5, 5, 6, 6, 7, 7, 7, 8,
2405 8, 9, 9, 9, 10, 10, 11, 11, 11, 12
2406 };
2407
2408 static const u8 rtw8822b_pwrtrk_2gb_p[RTW_PWR_TRK_TBL_SZ] = {
2409 0, 0, 1, 1, 2, 2, 3, 3, 4, 4,
2410 5, 5, 6, 6, 6, 7, 7, 8, 8, 9,
2411 9, 10, 10, 11, 11, 12, 12, 12, 13, 13
2412 };
2413
2414 static const u8 rtw8822b_pwrtrk_2ga_n[RTW_PWR_TRK_TBL_SZ] = {
2415 0, 1, 1, 1, 2, 2, 3, 3, 3, 4,
2416 4, 5, 5, 5, 6, 6, 7, 7, 7, 8,
2417 8, 9, 9, 9, 10, 10, 11, 11, 11, 12
2418 };
2419
2420 static const u8 rtw8822b_pwrtrk_2ga_p[RTW_PWR_TRK_TBL_SZ] = {
2421 0, 1, 1, 2, 2, 3, 3, 4, 4, 5,
2422 5, 6, 6, 7, 7, 8, 8, 9, 9, 10,
2423 10, 11, 11, 12, 12, 13, 13, 14, 14, 15
2424 };
2425
2426 static const u8 rtw8822b_pwrtrk_2g_cck_b_n[RTW_PWR_TRK_TBL_SZ] = {
2427 0, 1, 1, 1, 2, 2, 3, 3, 3, 4,
2428 4, 5, 5, 5, 6, 6, 7, 7, 7, 8,
2429 8, 9, 9, 9, 10, 10, 11, 11, 11, 12
2430 };
2431
2432 static const u8 rtw8822b_pwrtrk_2g_cck_b_p[RTW_PWR_TRK_TBL_SZ] = {
2433 0, 0, 1, 1, 2, 2, 3, 3, 4, 4,
2434 5, 5, 6, 6, 6, 7, 7, 8, 8, 9,
2435 9, 10, 10, 11, 11, 12, 12, 12, 13, 13
2436 };
2437
2438 static const u8 rtw8822b_pwrtrk_2g_cck_a_n[RTW_PWR_TRK_TBL_SZ] = {
2439 0, 1, 1, 1, 2, 2, 3, 3, 3, 4,
2440 4, 5, 5, 5, 6, 6, 7, 7, 7, 8,
2441 8, 9, 9, 9, 10, 10, 11, 11, 11, 12
2442 };
2443
2444 static const u8 rtw8822b_pwrtrk_2g_cck_a_p[RTW_PWR_TRK_TBL_SZ] = {
2445 0, 1, 1, 2, 2, 3, 3, 4, 4, 5,
2446 5, 6, 6, 7, 7, 8, 8, 9, 9, 10,
2447 10, 11, 11, 12, 12, 13, 13, 14, 14, 15
2448 };
2449
2450 static const struct rtw_pwr_track_tbl rtw8822b_pwr_track_type0_tbl = {
2451 .pwrtrk_5gb_n[RTW_PWR_TRK_5G_1] = rtw8822b_pwrtrk_5gb_n[RTW_PWR_TRK_5G_1],
2452 .pwrtrk_5gb_n[RTW_PWR_TRK_5G_2] = rtw8822b_pwrtrk_5gb_n[RTW_PWR_TRK_5G_2],
2453 .pwrtrk_5gb_n[RTW_PWR_TRK_5G_3] = rtw8822b_pwrtrk_5gb_n[RTW_PWR_TRK_5G_3],
2454 .pwrtrk_5gb_p[RTW_PWR_TRK_5G_1] = rtw8822b_pwrtrk_5gb_p[RTW_PWR_TRK_5G_1],
2455 .pwrtrk_5gb_p[RTW_PWR_TRK_5G_2] = rtw8822b_pwrtrk_5gb_p[RTW_PWR_TRK_5G_2],
2456 .pwrtrk_5gb_p[RTW_PWR_TRK_5G_3] = rtw8822b_pwrtrk_5gb_p[RTW_PWR_TRK_5G_3],
2457 .pwrtrk_5ga_n[RTW_PWR_TRK_5G_1] = rtw8822b_pwrtrk_5ga_n[RTW_PWR_TRK_5G_1],
2458 .pwrtrk_5ga_n[RTW_PWR_TRK_5G_2] = rtw8822b_pwrtrk_5ga_n[RTW_PWR_TRK_5G_2],
2459 .pwrtrk_5ga_n[RTW_PWR_TRK_5G_3] = rtw8822b_pwrtrk_5ga_n[RTW_PWR_TRK_5G_3],
2460 .pwrtrk_5ga_p[RTW_PWR_TRK_5G_1] = rtw8822b_pwrtrk_5ga_p[RTW_PWR_TRK_5G_1],
2461 .pwrtrk_5ga_p[RTW_PWR_TRK_5G_2] = rtw8822b_pwrtrk_5ga_p[RTW_PWR_TRK_5G_2],
2462 .pwrtrk_5ga_p[RTW_PWR_TRK_5G_3] = rtw8822b_pwrtrk_5ga_p[RTW_PWR_TRK_5G_3],
2463 .pwrtrk_2gb_n = rtw8822b_pwrtrk_2gb_n,
2464 .pwrtrk_2gb_p = rtw8822b_pwrtrk_2gb_p,
2465 .pwrtrk_2ga_n = rtw8822b_pwrtrk_2ga_n,
2466 .pwrtrk_2ga_p = rtw8822b_pwrtrk_2ga_p,
2467 .pwrtrk_2g_cckb_n = rtw8822b_pwrtrk_2g_cck_b_n,
2468 .pwrtrk_2g_cckb_p = rtw8822b_pwrtrk_2g_cck_b_p,
2469 .pwrtrk_2g_ccka_n = rtw8822b_pwrtrk_2g_cck_a_n,
2470 .pwrtrk_2g_ccka_p = rtw8822b_pwrtrk_2g_cck_a_p,
2471 };
2472
2473 static const struct rtw_rfe_def rtw8822b_rfe_defs[] = {
2474 [2] = RTW_DEF_RFE(8822b, 2, 2, 0),
2475 [3] = RTW_DEF_RFE(8822b, 3, 0, 0),
2476 [5] = RTW_DEF_RFE(8822b, 5, 5, 0),
2477 };
2478
2479 static const struct rtw_reg_domain coex_info_hw_regs_8822b[] = {
2480 {0xcb0, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2481 {0xcb4, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2482 {0xcba, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2483 {0xcbd, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2484 {0xc58, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2485 {0xcbd, BIT(0), RTW_REG_DOMAIN_MAC8},
2486 {0, 0, RTW_REG_DOMAIN_NL},
2487 {0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2488 {0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2489 {0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16},
2490 {0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2491 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8},
2492 {0x454, MASKLWORD, RTW_REG_DOMAIN_MAC16},
2493 {0, 0, RTW_REG_DOMAIN_NL},
2494 {0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32},
2495 {0x64, BIT(0), RTW_REG_DOMAIN_MAC8},
2496 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8},
2497 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8},
2498 {0x1, RFREG_MASK, RTW_REG_DOMAIN_RF_B},
2499 {0, 0, RTW_REG_DOMAIN_NL},
2500 {0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2501 {0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2502 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8},
2503 {0xc50, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2504 };
2505
2506 static const struct rtw_hw_reg_offset rtw8822b_edcca_th[] = {
2507 [EDCCA_TH_L2H_IDX] = {{.addr = 0x8a4, .mask = MASKBYTE0}, .offset = 0},
2508 [EDCCA_TH_H2L_IDX] = {{.addr = 0x8a4, .mask = MASKBYTE1}, .offset = 0},
2509 };
2510
2511 const struct rtw_chip_info rtw8822b_hw_spec = {
2512 .ops = &rtw8822b_ops,
2513 .id = RTW_CHIP_TYPE_8822B,
2514 .fw_name = "rtw88/rtw8822b_fw.bin",
2515 .wlan_cpu = RTW_WCPU_11AC,
2516 .tx_pkt_desc_sz = 48,
2517 .tx_buf_desc_sz = 16,
2518 .rx_pkt_desc_sz = 24,
2519 .rx_buf_desc_sz = 8,
2520 .phy_efuse_size = 1024,
2521 .log_efuse_size = 768,
2522 .ptct_efuse_size = 96,
2523 .txff_size = 262144,
2524 .rxff_size = 24576,
2525 .fw_rxff_size = 12288,
2526 .rsvd_drv_pg_num = 8,
2527 .txgi_factor = 1,
2528 .is_pwr_by_rate_dec = true,
2529 .max_power_index = 0x3f,
2530 .csi_buf_pg_num = 0,
2531 .band = RTW_BAND_2G | RTW_BAND_5G,
2532 .page_size = TX_PAGE_SIZE,
2533 .dig_min = 0x1c,
2534 .usb_tx_agg_desc_num = 3,
2535 .hw_feature_report = true,
2536 .c2h_ra_report_size = 7,
2537 .old_datarate_fb_limit = false,
2538 .ht_supported = true,
2539 .vht_supported = true,
2540 .lps_deep_mode_supported = BIT(LPS_DEEP_MODE_LCLK),
2541 .sys_func_en = 0xDC,
2542 .pwr_on_seq = card_enable_flow_8822b,
2543 .pwr_off_seq = card_disable_flow_8822b,
2544 .page_table = page_table_8822b,
2545 .rqpn_table = rqpn_table_8822b,
2546 .prioq_addrs = &prioq_addrs_8822b,
2547 .intf_table = &phy_para_table_8822b,
2548 .dig = rtw8822b_dig,
2549 .dig_cck = NULL,
2550 .rf_base_addr = {0x2800, 0x2c00},
2551 .rf_sipi_addr = {0xc90, 0xe90},
2552 .ltecoex_addr = &rtw8822b_ltecoex_addr,
2553 .mac_tbl = &rtw8822b_mac_tbl,
2554 .agc_tbl = &rtw8822b_agc_tbl,
2555 .bb_tbl = &rtw8822b_bb_tbl,
2556 .rf_tbl = {&rtw8822b_rf_a_tbl, &rtw8822b_rf_b_tbl},
2557 .rfe_defs = rtw8822b_rfe_defs,
2558 .rfe_defs_size = ARRAY_SIZE(rtw8822b_rfe_defs),
2559 .iqk_threshold = 8,
2560 .bfer_su_max_num = 2,
2561 .bfer_mu_max_num = 1,
2562 .rx_ldpc = true,
2563 .edcca_th = rtw8822b_edcca_th,
2564 .l2h_th_ini_cs = 10 + EDCCA_IGI_BASE,
2565 .l2h_th_ini_ad = -14 + EDCCA_IGI_BASE,
2566 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_2,
2567 .max_scan_ie_len = IEEE80211_MAX_DATA_LEN,
2568
2569 .coex_para_ver = 0x20070206,
2570 .bt_desired_ver = 0x6,
2571 .scbd_support = true,
2572 .new_scbd10_def = false,
2573 .ble_hid_profile_support = false,
2574 .wl_mimo_ps_support = false,
2575 .pstdma_type = COEX_PSTDMA_FORCE_LPSOFF,
2576 .bt_rssi_type = COEX_BTRSSI_RATIO,
2577 .ant_isolation = 15,
2578 .rssi_tolerance = 2,
2579 .wl_rssi_step = wl_rssi_step_8822b,
2580 .bt_rssi_step = bt_rssi_step_8822b,
2581 .table_sant_num = ARRAY_SIZE(table_sant_8822b),
2582 .table_sant = table_sant_8822b,
2583 .table_nsant_num = ARRAY_SIZE(table_nsant_8822b),
2584 .table_nsant = table_nsant_8822b,
2585 .tdma_sant_num = ARRAY_SIZE(tdma_sant_8822b),
2586 .tdma_sant = tdma_sant_8822b,
2587 .tdma_nsant_num = ARRAY_SIZE(tdma_nsant_8822b),
2588 .tdma_nsant = tdma_nsant_8822b,
2589 .wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8822b),
2590 .wl_rf_para_tx = rf_para_tx_8822b,
2591 .wl_rf_para_rx = rf_para_rx_8822b,
2592 .bt_afh_span_bw20 = 0x24,
2593 .bt_afh_span_bw40 = 0x36,
2594 .afh_5g_num = ARRAY_SIZE(afh_5g_8822b),
2595 .afh_5g = afh_5g_8822b,
2596
2597 .coex_info_hw_regs_num = ARRAY_SIZE(coex_info_hw_regs_8822b),
2598 .coex_info_hw_regs = coex_info_hw_regs_8822b,
2599
2600 .fw_fifo_addr = {0x780, 0x700, 0x780, 0x660, 0x650, 0x680},
2601 };
2602 EXPORT_SYMBOL(rtw8822b_hw_spec);
2603
2604 MODULE_FIRMWARE("rtw88/rtw8822b_fw.bin");
2605
2606 MODULE_AUTHOR("Realtek Corporation");
2607 MODULE_DESCRIPTION("Realtek 802.11ac wireless 8822b driver");
2608 MODULE_LICENSE("Dual BSD/GPL");
2609