1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
3 */
4
5 #include "main.h"
6 #include "coex.h"
7 #include "fw.h"
8 #include "tx.h"
9 #include "rx.h"
10 #include "phy.h"
11 #include "rtw8821c.h"
12 #include "rtw8821c_table.h"
13 #include "mac.h"
14 #include "reg.h"
15 #include "debug.h"
16 #include "bf.h"
17 #include "regd.h"
18
19 static const s8 lna_gain_table_0[8] = {22, 8, -6, -22, -31, -40, -46, -52};
20 static const s8 lna_gain_table_1[16] = {10, 6, 2, -2, -6, -10, -14, -17,
21 -20, -24, -28, -31, -34, -37, -40, -44};
22
rtw8821ce_efuse_parsing(struct rtw_efuse * efuse,struct rtw8821c_efuse * map)23 static void rtw8821ce_efuse_parsing(struct rtw_efuse *efuse,
24 struct rtw8821c_efuse *map)
25 {
26 ether_addr_copy(efuse->addr, map->e.mac_addr);
27 }
28
rtw8821cu_efuse_parsing(struct rtw_efuse * efuse,struct rtw8821c_efuse * map)29 static void rtw8821cu_efuse_parsing(struct rtw_efuse *efuse,
30 struct rtw8821c_efuse *map)
31 {
32 ether_addr_copy(efuse->addr, map->u.mac_addr);
33 }
34
rtw8821cs_efuse_parsing(struct rtw_efuse * efuse,struct rtw8821c_efuse * map)35 static void rtw8821cs_efuse_parsing(struct rtw_efuse *efuse,
36 struct rtw8821c_efuse *map)
37 {
38 ether_addr_copy(efuse->addr, map->s.mac_addr);
39 }
40
41 enum rtw8821ce_rf_set {
42 SWITCH_TO_BTG,
43 SWITCH_TO_WLG,
44 SWITCH_TO_WLA,
45 SWITCH_TO_BT,
46 };
47
rtw8821c_read_efuse(struct rtw_dev * rtwdev,u8 * log_map)48 static int rtw8821c_read_efuse(struct rtw_dev *rtwdev, u8 *log_map)
49 {
50 struct rtw_hal *hal = &rtwdev->hal;
51 struct rtw_efuse *efuse = &rtwdev->efuse;
52 struct rtw8821c_efuse *map;
53 int i;
54
55 map = (struct rtw8821c_efuse *)log_map;
56
57 efuse->rfe_option = map->rfe_option & 0x1f;
58 efuse->rf_board_option = map->rf_board_option;
59 efuse->crystal_cap = map->xtal_k;
60 efuse->pa_type_2g = map->pa_type;
61 efuse->pa_type_5g = map->pa_type;
62 efuse->lna_type_2g = map->lna_type_2g[0];
63 efuse->lna_type_5g = map->lna_type_5g[0];
64 efuse->channel_plan = map->channel_plan;
65 efuse->country_code[0] = map->country_code[0];
66 efuse->country_code[1] = map->country_code[1];
67 efuse->bt_setting = map->rf_bt_setting;
68 efuse->regd = map->rf_board_option & 0x7;
69 efuse->thermal_meter[0] = map->thermal_meter;
70 efuse->thermal_meter_k = map->thermal_meter;
71 efuse->tx_bb_swing_setting_2g = map->tx_bb_swing_setting_2g;
72 efuse->tx_bb_swing_setting_5g = map->tx_bb_swing_setting_5g;
73
74 hal->pkg_type = map->rfe_option & BIT(5) ? 1 : 0;
75
76 switch (efuse->rfe_option) {
77 case 0x2:
78 case 0x4:
79 case 0x7:
80 case 0xa:
81 case 0xc:
82 case 0xf:
83 hal->rfe_btg = true;
84 break;
85 }
86
87 for (i = 0; i < 4; i++)
88 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i];
89
90 if (rtwdev->efuse.rfe_option == 2 || rtwdev->efuse.rfe_option == 4)
91 efuse->txpwr_idx_table[0].pwr_idx_2g = map->txpwr_idx_table[1].pwr_idx_2g;
92
93 switch (rtw_hci_type(rtwdev)) {
94 case RTW_HCI_TYPE_PCIE:
95 rtw8821ce_efuse_parsing(efuse, map);
96 break;
97 case RTW_HCI_TYPE_USB:
98 rtw8821cu_efuse_parsing(efuse, map);
99 break;
100 case RTW_HCI_TYPE_SDIO:
101 rtw8821cs_efuse_parsing(efuse, map);
102 break;
103 default:
104 /* unsupported now */
105 return -ENOTSUPP;
106 }
107
108 return 0;
109 }
110
111 static const u32 rtw8821c_txscale_tbl[] = {
112 0x081, 0x088, 0x090, 0x099, 0x0a2, 0x0ac, 0x0b6, 0x0c0, 0x0cc, 0x0d8,
113 0x0e5, 0x0f2, 0x101, 0x110, 0x120, 0x131, 0x143, 0x156, 0x16a, 0x180,
114 0x197, 0x1af, 0x1c8, 0x1e3, 0x200, 0x21e, 0x23e, 0x261, 0x285, 0x2ab,
115 0x2d3, 0x2fe, 0x32b, 0x35c, 0x38e, 0x3c4, 0x3fe
116 };
117
rtw8821c_get_swing_index(struct rtw_dev * rtwdev)118 static u8 rtw8821c_get_swing_index(struct rtw_dev *rtwdev)
119 {
120 u8 i = 0;
121 u32 swing, table_value;
122
123 swing = rtw_read32_mask(rtwdev, REG_TXSCALE_A, 0xffe00000);
124 for (i = 0; i < ARRAY_SIZE(rtw8821c_txscale_tbl); i++) {
125 table_value = rtw8821c_txscale_tbl[i];
126 if (swing == table_value)
127 break;
128 }
129
130 return i;
131 }
132
rtw8821c_pwrtrack_init(struct rtw_dev * rtwdev)133 static void rtw8821c_pwrtrack_init(struct rtw_dev *rtwdev)
134 {
135 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
136 u8 swing_idx = rtw8821c_get_swing_index(rtwdev);
137
138 if (swing_idx >= ARRAY_SIZE(rtw8821c_txscale_tbl))
139 dm_info->default_ofdm_index = 24;
140 else
141 dm_info->default_ofdm_index = swing_idx;
142
143 ewma_thermal_init(&dm_info->avg_thermal[RF_PATH_A]);
144 dm_info->delta_power_index[RF_PATH_A] = 0;
145 dm_info->delta_power_index_last[RF_PATH_A] = 0;
146 dm_info->pwr_trk_triggered = false;
147 dm_info->pwr_trk_init_trigger = true;
148 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k;
149 }
150
rtw8821c_phy_bf_init(struct rtw_dev * rtwdev)151 static void rtw8821c_phy_bf_init(struct rtw_dev *rtwdev)
152 {
153 rtw_bf_phy_init(rtwdev);
154 /* Grouping bitmap parameters */
155 rtw_write32(rtwdev, 0x1C94, 0xAFFFAFFF);
156 }
157
rtw8821c_phy_set_param(struct rtw_dev * rtwdev)158 static void rtw8821c_phy_set_param(struct rtw_dev *rtwdev)
159 {
160 struct rtw_hal *hal = &rtwdev->hal;
161 u8 crystal_cap, val;
162
163 /* power on BB/RF domain */
164 val = rtw_read8(rtwdev, REG_SYS_FUNC_EN);
165 val |= BIT_FEN_PCIEA;
166 rtw_write8(rtwdev, REG_SYS_FUNC_EN, val);
167
168 /* toggle BB reset */
169 val |= BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST;
170 rtw_write8(rtwdev, REG_SYS_FUNC_EN, val);
171 val &= ~(BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST);
172 rtw_write8(rtwdev, REG_SYS_FUNC_EN, val);
173 val |= BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST;
174 rtw_write8(rtwdev, REG_SYS_FUNC_EN, val);
175
176 rtw_write8(rtwdev, REG_RF_CTRL,
177 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB);
178 usleep_range(10, 11);
179 rtw_write8(rtwdev, REG_WLRF1 + 3,
180 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB);
181 usleep_range(10, 11);
182
183 /* pre init before header files config */
184 rtw_write32_clr(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST);
185
186 rtw_phy_load_tables(rtwdev);
187
188 crystal_cap = rtwdev->efuse.crystal_cap & 0x3F;
189 rtw_write32_mask(rtwdev, REG_AFE_XTAL_CTRL, 0x7e000000, crystal_cap);
190 rtw_write32_mask(rtwdev, REG_AFE_PLL_CTRL, 0x7e, crystal_cap);
191 rtw_write32_mask(rtwdev, REG_CCK0_FAREPORT, BIT(18) | BIT(22), 0);
192
193 /* post init after header files config */
194 rtw_write32_set(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST);
195 hal->ch_param[0] = rtw_read32_mask(rtwdev, REG_TXSF2, MASKDWORD);
196 hal->ch_param[1] = rtw_read32_mask(rtwdev, REG_TXSF6, MASKDWORD);
197 hal->ch_param[2] = rtw_read32_mask(rtwdev, REG_TXFILTER, MASKDWORD);
198
199 rtw_phy_init(rtwdev);
200 rtwdev->dm_info.cck_pd_default = rtw_read8(rtwdev, REG_CSRATIO) & 0x1f;
201
202 rtw8821c_pwrtrack_init(rtwdev);
203
204 rtw8821c_phy_bf_init(rtwdev);
205 }
206
rtw8821c_mac_init(struct rtw_dev * rtwdev)207 static int rtw8821c_mac_init(struct rtw_dev *rtwdev)
208 {
209 u32 value32;
210 u16 pre_txcnt;
211
212 /* protocol configuration */
213 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME);
214 rtw_write8_set(rtwdev, REG_TX_HANG_CTRL, BIT_EN_EOF_V1);
215 pre_txcnt = WLAN_PRE_TXCNT_TIME_TH | BIT_EN_PRECNT;
216 rtw_write8(rtwdev, REG_PRECNT_CTRL, (u8)(pre_txcnt & 0xFF));
217 rtw_write8(rtwdev, REG_PRECNT_CTRL + 1, (u8)(pre_txcnt >> 8));
218 value32 = WLAN_RTS_LEN_TH | (WLAN_RTS_TX_TIME_TH << 8) |
219 (WLAN_MAX_AGG_PKT_LIMIT << 16) |
220 (WLAN_RTS_MAX_AGG_PKT_LIMIT << 24);
221 rtw_write32(rtwdev, REG_PROT_MODE_CTRL, value32);
222 rtw_write16(rtwdev, REG_BAR_MODE_CTRL + 2,
223 WLAN_BAR_RETRY_LIMIT | WLAN_RA_TRY_RATE_AGG_LIMIT << 8);
224 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING, FAST_EDCA_VO_TH);
225 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING + 2, FAST_EDCA_VI_TH);
226 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING, FAST_EDCA_BE_TH);
227 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING + 2, FAST_EDCA_BK_TH);
228 rtw_write8_set(rtwdev, REG_INIRTS_RATE_SEL, BIT(5));
229
230 /* EDCA configuration */
231 rtw_write8_clr(rtwdev, REG_TIMER0_SRC_SEL, BIT_TSFT_SEL_TIMER0);
232 rtw_write16(rtwdev, REG_TXPAUSE, 0);
233 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME);
234 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_TIME);
235 rtw_write32(rtwdev, REG_SIFS, WLAN_SIFS_CFG);
236 rtw_write16(rtwdev, REG_EDCA_VO_PARAM + 2, WLAN_VO_TXOP_LIMIT);
237 rtw_write16(rtwdev, REG_EDCA_VI_PARAM + 2, WLAN_VI_TXOP_LIMIT);
238 rtw_write32(rtwdev, REG_RD_NAV_NXT, WLAN_NAV_CFG);
239 rtw_write16(rtwdev, REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG);
240
241 /* Set beacon cotnrol - enable TSF and other related functions */
242 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
243
244 /* Set send beacon related registers */
245 rtw_write32(rtwdev, REG_TBTT_PROHIBIT, WLAN_TBTT_TIME);
246 rtw_write8(rtwdev, REG_DRVERLYINT, WLAN_DRV_EARLY_INT);
247 rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME);
248 rtw_write8_clr(rtwdev, REG_TX_PTCL_CTRL + 1, BIT_SIFS_BK_EN >> 8);
249
250 /* WMAC configuration */
251 rtw_write32(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0);
252 rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2);
253 rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG);
254 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512);
255 rtw_write8(rtwdev, REG_TCR + 2, WLAN_TX_FUNC_CFG2);
256 rtw_write8(rtwdev, REG_TCR + 1, WLAN_TX_FUNC_CFG1);
257 rtw_write8(rtwdev, REG_ACKTO_CCK, 0x40);
258 rtw_write8_set(rtwdev, REG_WMAC_TRXPTCL_CTL_H, BIT(1));
259 rtw_write8_set(rtwdev, REG_SND_PTCL_CTRL,
260 BIT_DIS_CHK_VHTSIGB_CRC);
261 rtw_write32(rtwdev, REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2);
262 rtw_write8(rtwdev, REG_WMAC_OPTION_FUNCTION + 4, WLAN_MAC_OPT_NORM_FUNC1);
263
264 return 0;
265 }
266
rtw8821c_cfg_ldo25(struct rtw_dev * rtwdev,bool enable)267 static void rtw8821c_cfg_ldo25(struct rtw_dev *rtwdev, bool enable)
268 {
269 u8 ldo_pwr;
270
271 ldo_pwr = rtw_read8(rtwdev, REG_LDO_EFUSE_CTRL + 3);
272 ldo_pwr = enable ? ldo_pwr | BIT(7) : ldo_pwr & ~BIT(7);
273 rtw_write8(rtwdev, REG_LDO_EFUSE_CTRL + 3, ldo_pwr);
274 }
275
rtw8821c_switch_rf_set(struct rtw_dev * rtwdev,u8 rf_set)276 static void rtw8821c_switch_rf_set(struct rtw_dev *rtwdev, u8 rf_set)
277 {
278 u32 reg;
279
280 rtw_write32_set(rtwdev, REG_DMEM_CTRL, BIT_WL_RST);
281 rtw_write32_set(rtwdev, REG_SYS_CTRL, BIT_FEN_EN);
282
283 reg = rtw_read32(rtwdev, REG_RFECTL);
284 switch (rf_set) {
285 case SWITCH_TO_BTG:
286 reg |= B_BTG_SWITCH;
287 reg &= ~(B_CTRL_SWITCH | B_WL_SWITCH | B_WLG_SWITCH |
288 B_WLA_SWITCH);
289 rtw_write32_mask(rtwdev, REG_ENRXCCA, MASKBYTE2, BTG_CCA);
290 rtw_write32_mask(rtwdev, REG_ENTXCCK, MASKLWORD, BTG_LNA);
291 break;
292 case SWITCH_TO_WLG:
293 reg |= B_WL_SWITCH | B_WLG_SWITCH;
294 reg &= ~(B_BTG_SWITCH | B_CTRL_SWITCH | B_WLA_SWITCH);
295 rtw_write32_mask(rtwdev, REG_ENRXCCA, MASKBYTE2, WLG_CCA);
296 rtw_write32_mask(rtwdev, REG_ENTXCCK, MASKLWORD, WLG_LNA);
297 break;
298 case SWITCH_TO_WLA:
299 reg |= B_WL_SWITCH | B_WLA_SWITCH;
300 reg &= ~(B_BTG_SWITCH | B_CTRL_SWITCH | B_WLG_SWITCH);
301 break;
302 case SWITCH_TO_BT:
303 default:
304 break;
305 }
306
307 rtw_write32(rtwdev, REG_RFECTL, reg);
308 }
309
rtw8821c_set_channel_rf(struct rtw_dev * rtwdev,u8 channel,u8 bw)310 static void rtw8821c_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw)
311 {
312 struct rtw_hal *hal = &rtwdev->hal;
313 u32 rf_reg18;
314
315 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK);
316
317 rf_reg18 &= ~(RF18_BAND_MASK | RF18_CHANNEL_MASK | RF18_RFSI_MASK |
318 RF18_BW_MASK);
319
320 rf_reg18 |= (channel <= 14 ? RF18_BAND_2G : RF18_BAND_5G);
321 rf_reg18 |= (channel & RF18_CHANNEL_MASK);
322
323 if (channel >= 100 && channel <= 140)
324 rf_reg18 |= RF18_RFSI_GE;
325 else if (channel > 140)
326 rf_reg18 |= RF18_RFSI_GT;
327
328 switch (bw) {
329 case RTW_CHANNEL_WIDTH_5:
330 case RTW_CHANNEL_WIDTH_10:
331 case RTW_CHANNEL_WIDTH_20:
332 default:
333 rf_reg18 |= RF18_BW_20M;
334 break;
335 case RTW_CHANNEL_WIDTH_40:
336 rf_reg18 |= RF18_BW_40M;
337 break;
338 case RTW_CHANNEL_WIDTH_80:
339 rf_reg18 |= RF18_BW_80M;
340 break;
341 }
342
343 if (channel <= 14) {
344 if (hal->rfe_btg)
345 rtw8821c_switch_rf_set(rtwdev, SWITCH_TO_BTG);
346 else
347 rtw8821c_switch_rf_set(rtwdev, SWITCH_TO_WLG);
348 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x1);
349 rtw_write_rf(rtwdev, RF_PATH_A, 0x64, 0xf, 0xf);
350 } else {
351 rtw8821c_switch_rf_set(rtwdev, SWITCH_TO_WLA);
352 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x0);
353 }
354
355 rtw_write_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK, rf_reg18);
356
357 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 0);
358 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 1);
359 }
360
rtw8821c_set_channel_rxdfir(struct rtw_dev * rtwdev,u8 bw)361 static void rtw8821c_set_channel_rxdfir(struct rtw_dev *rtwdev, u8 bw)
362 {
363 if (bw == RTW_CHANNEL_WIDTH_40) {
364 /* RX DFIR for BW40 */
365 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2);
366 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2);
367 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0);
368 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0);
369 } else if (bw == RTW_CHANNEL_WIDTH_80) {
370 /* RX DFIR for BW80 */
371 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2);
372 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x1);
373 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0);
374 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x1);
375 } else {
376 /* RX DFIR for BW20, BW10 and BW5 */
377 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2);
378 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2);
379 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x1);
380 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0);
381 }
382 }
383
rtw8821c_cck_tx_filter_srrc(struct rtw_dev * rtwdev,u8 channel,u8 bw)384 static void rtw8821c_cck_tx_filter_srrc(struct rtw_dev *rtwdev, u8 channel, u8 bw)
385 {
386 struct rtw_hal *hal = &rtwdev->hal;
387
388 if (channel == 14) {
389 rtw_write32_mask(rtwdev, REG_CCA_FLTR, MASKHWORD, 0xe82c);
390 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x0000b81c);
391 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x0000);
392 rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD, 0x00003667);
393
394 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, RFREG_MASK, 0x00002);
395 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0001e);
396 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000);
397 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0001c);
398 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000);
399 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0000e);
400 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000);
401 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0000c);
402 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000);
403 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, RFREG_MASK, 0x00000);
404 } else if (channel == 13 ||
405 (channel == 11 && bw == RTW_CHANNEL_WIDTH_40)) {
406 rtw_write32_mask(rtwdev, REG_CCA_FLTR, MASKHWORD, 0xf8fe);
407 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x64b80c1c);
408 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x8810);
409 rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD, 0x01235667);
410
411 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, RFREG_MASK, 0x00002);
412 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0001e);
413 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00027);
414 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0001c);
415 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00027);
416 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0000e);
417 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00029);
418 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0000c);
419 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00026);
420 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, RFREG_MASK, 0x00000);
421 } else {
422 rtw_write32_mask(rtwdev, REG_CCA_FLTR, MASKHWORD, 0xe82c);
423 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD,
424 hal->ch_param[0]);
425 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD,
426 hal->ch_param[1] & MASKLWORD);
427 rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD,
428 hal->ch_param[2]);
429
430 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, RFREG_MASK, 0x00002);
431 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0001e);
432 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000);
433 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0001c);
434 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000);
435 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0000e);
436 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000);
437 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0000c);
438 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000);
439 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, RFREG_MASK, 0x00000);
440 }
441 }
442
rtw8821c_set_channel_bb(struct rtw_dev * rtwdev,u8 channel,u8 bw,u8 primary_ch_idx)443 static void rtw8821c_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw,
444 u8 primary_ch_idx)
445 {
446 struct rtw_hal *hal = &rtwdev->hal;
447 u32 val32;
448
449 if (channel <= 14) {
450 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1);
451 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x0);
452 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x0);
453 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15);
454
455 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x0);
456 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x96a);
457
458 if (rtw_regd_srrc(rtwdev)) {
459 rtw8821c_cck_tx_filter_srrc(rtwdev, channel, bw);
460 goto set_bw;
461 }
462
463 /* CCK TX filter parameters for default case */
464 if (channel == 14) {
465 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x0000b81c);
466 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x0000);
467 rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD, 0x00003667);
468 } else {
469 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD,
470 hal->ch_param[0]);
471 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD,
472 hal->ch_param[1] & MASKLWORD);
473 rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD,
474 hal->ch_param[2]);
475 }
476 } else if (channel > 35) {
477 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x1);
478 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x1);
479 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0);
480 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15);
481
482 if (channel >= 36 && channel <= 64)
483 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x1);
484 else if (channel >= 100 && channel <= 144)
485 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x2);
486 else if (channel >= 149)
487 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x3);
488
489 if (channel >= 36 && channel <= 48)
490 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x494);
491 else if (channel >= 52 && channel <= 64)
492 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x453);
493 else if (channel >= 100 && channel <= 116)
494 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x452);
495 else if (channel >= 118 && channel <= 177)
496 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x412);
497 }
498
499 set_bw:
500 switch (bw) {
501 case RTW_CHANNEL_WIDTH_20:
502 default:
503 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
504 val32 &= 0xffcffc00;
505 val32 |= 0x10010000;
506 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
507
508 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);
509 break;
510 case RTW_CHANNEL_WIDTH_40:
511 if (primary_ch_idx == 1)
512 rtw_write32_set(rtwdev, REG_RXSB, BIT(4));
513 else
514 rtw_write32_clr(rtwdev, REG_RXSB, BIT(4));
515
516 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
517 val32 &= 0xff3ff300;
518 val32 |= 0x20020000 | ((primary_ch_idx & 0xf) << 2) |
519 RTW_CHANNEL_WIDTH_40;
520 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
521
522 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);
523 break;
524 case RTW_CHANNEL_WIDTH_80:
525 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
526 val32 &= 0xfcffcf00;
527 val32 |= 0x40040000 | ((primary_ch_idx & 0xf) << 2) |
528 RTW_CHANNEL_WIDTH_80;
529 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
530
531 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);
532 break;
533 case RTW_CHANNEL_WIDTH_5:
534 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
535 val32 &= 0xefcefc00;
536 val32 |= 0x200240;
537 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
538
539 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0);
540 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1);
541 break;
542 case RTW_CHANNEL_WIDTH_10:
543 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD);
544 val32 &= 0xefcefc00;
545 val32 |= 0x300380;
546 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32);
547
548 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0);
549 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1);
550 break;
551 }
552 }
553
rtw8821c_get_bb_swing(struct rtw_dev * rtwdev,u8 channel)554 static u32 rtw8821c_get_bb_swing(struct rtw_dev *rtwdev, u8 channel)
555 {
556 struct rtw_efuse efuse = rtwdev->efuse;
557 u8 tx_bb_swing;
558 u32 swing2setting[4] = {0x200, 0x16a, 0x101, 0x0b6};
559
560 tx_bb_swing = channel <= 14 ? efuse.tx_bb_swing_setting_2g :
561 efuse.tx_bb_swing_setting_5g;
562 if (tx_bb_swing > 9)
563 tx_bb_swing = 0;
564
565 return swing2setting[(tx_bb_swing / 3)];
566 }
567
rtw8821c_set_channel_bb_swing(struct rtw_dev * rtwdev,u8 channel,u8 bw,u8 primary_ch_idx)568 static void rtw8821c_set_channel_bb_swing(struct rtw_dev *rtwdev, u8 channel,
569 u8 bw, u8 primary_ch_idx)
570 {
571 rtw_write32_mask(rtwdev, REG_TXSCALE_A, GENMASK(31, 21),
572 rtw8821c_get_bb_swing(rtwdev, channel));
573 rtw8821c_pwrtrack_init(rtwdev);
574 }
575
rtw8821c_set_channel(struct rtw_dev * rtwdev,u8 channel,u8 bw,u8 primary_chan_idx)576 static void rtw8821c_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw,
577 u8 primary_chan_idx)
578 {
579 rtw8821c_set_channel_bb(rtwdev, channel, bw, primary_chan_idx);
580 rtw8821c_set_channel_bb_swing(rtwdev, channel, bw, primary_chan_idx);
581 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx);
582 rtw8821c_set_channel_rf(rtwdev, channel, bw);
583 rtw8821c_set_channel_rxdfir(rtwdev, bw);
584 }
585
get_cck_rx_pwr(struct rtw_dev * rtwdev,u8 lna_idx,u8 vga_idx)586 static s8 get_cck_rx_pwr(struct rtw_dev *rtwdev, u8 lna_idx, u8 vga_idx)
587 {
588 struct rtw_efuse *efuse = &rtwdev->efuse;
589 const s8 *lna_gain_table;
590 int lna_gain_table_size;
591 s8 rx_pwr_all = 0;
592 s8 lna_gain = 0;
593
594 if (efuse->rfe_option == 0) {
595 lna_gain_table = lna_gain_table_0;
596 lna_gain_table_size = ARRAY_SIZE(lna_gain_table_0);
597 } else {
598 lna_gain_table = lna_gain_table_1;
599 lna_gain_table_size = ARRAY_SIZE(lna_gain_table_1);
600 }
601
602 if (lna_idx >= lna_gain_table_size) {
603 rtw_warn(rtwdev, "incorrect lna index (%d)\n", lna_idx);
604 return -120;
605 }
606
607 lna_gain = lna_gain_table[lna_idx];
608 rx_pwr_all = lna_gain - 2 * vga_idx;
609
610 return rx_pwr_all;
611 }
612
query_phy_status_page0(struct rtw_dev * rtwdev,u8 * phy_status,struct rtw_rx_pkt_stat * pkt_stat)613 static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status,
614 struct rtw_rx_pkt_stat *pkt_stat)
615 {
616 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
617 s8 rx_power;
618 u8 lna_idx = 0;
619 u8 vga_idx = 0;
620
621 vga_idx = GET_PHY_STAT_P0_VGA(phy_status);
622 lna_idx = FIELD_PREP(BIT_LNA_H_MASK, GET_PHY_STAT_P0_LNA_H(phy_status)) |
623 FIELD_PREP(BIT_LNA_L_MASK, GET_PHY_STAT_P0_LNA_L(phy_status));
624 rx_power = get_cck_rx_pwr(rtwdev, lna_idx, vga_idx);
625
626 pkt_stat->rx_power[RF_PATH_A] = rx_power;
627 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1);
628 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi;
629 pkt_stat->bw = RTW_CHANNEL_WIDTH_20;
630 pkt_stat->signal_power = rx_power;
631 }
632
query_phy_status_page1(struct rtw_dev * rtwdev,u8 * phy_status,struct rtw_rx_pkt_stat * pkt_stat)633 static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status,
634 struct rtw_rx_pkt_stat *pkt_stat)
635 {
636 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
637 u8 rxsc, bw;
638 s8 min_rx_power = -120;
639
640 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0)
641 rxsc = GET_PHY_STAT_P1_L_RXSC(phy_status);
642 else
643 rxsc = GET_PHY_STAT_P1_HT_RXSC(phy_status);
644
645 if (rxsc >= 1 && rxsc <= 8)
646 bw = RTW_CHANNEL_WIDTH_20;
647 else if (rxsc >= 9 && rxsc <= 12)
648 bw = RTW_CHANNEL_WIDTH_40;
649 else if (rxsc >= 13)
650 bw = RTW_CHANNEL_WIDTH_80;
651 else
652 bw = GET_PHY_STAT_P1_RF_MODE(phy_status);
653
654 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110;
655 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1);
656 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi;
657 pkt_stat->bw = bw;
658 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A],
659 min_rx_power);
660 }
661
query_phy_status(struct rtw_dev * rtwdev,u8 * phy_status,struct rtw_rx_pkt_stat * pkt_stat)662 static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status,
663 struct rtw_rx_pkt_stat *pkt_stat)
664 {
665 u8 page;
666
667 page = *phy_status & 0xf;
668
669 switch (page) {
670 case 0:
671 query_phy_status_page0(rtwdev, phy_status, pkt_stat);
672 break;
673 case 1:
674 query_phy_status_page1(rtwdev, phy_status, pkt_stat);
675 break;
676 default:
677 rtw_warn(rtwdev, "unused phy status page (%d)\n", page);
678 return;
679 }
680 }
681
682 static void
rtw8821c_set_tx_power_index_by_rate(struct rtw_dev * rtwdev,u8 path,u8 rs,u32 * phy_pwr_idx)683 rtw8821c_set_tx_power_index_by_rate(struct rtw_dev *rtwdev, u8 path,
684 u8 rs, u32 *phy_pwr_idx)
685 {
686 struct rtw_hal *hal = &rtwdev->hal;
687 static const u32 offset_txagc[2] = {0x1d00, 0x1d80};
688 u8 rate, rate_idx, pwr_index, shift;
689 int j;
690
691 for (j = 0; j < rtw_rate_size[rs]; j++) {
692 rate = rtw_rate_section[rs][j];
693 pwr_index = hal->tx_pwr_tbl[path][rate];
694 shift = rate & 0x3;
695 *phy_pwr_idx |= ((u32)pwr_index << (shift * 8));
696 if (shift == 0x3 || rate == DESC_RATEVHT1SS_MCS9) {
697 rate_idx = rate & 0xfc;
698 rtw_write32(rtwdev, offset_txagc[path] + rate_idx,
699 *phy_pwr_idx);
700 *phy_pwr_idx = 0;
701 }
702 }
703 }
704
rtw8821c_set_tx_power_index(struct rtw_dev * rtwdev)705 static void rtw8821c_set_tx_power_index(struct rtw_dev *rtwdev)
706 {
707 struct rtw_hal *hal = &rtwdev->hal;
708 u32 phy_pwr_idx = 0;
709 int rs, path;
710
711 for (path = 0; path < hal->rf_path_num; path++) {
712 for (rs = 0; rs <= __RTW_RATE_SECTION_2SS_MAX; rs++) {
713 if (rs == RTW_RATE_SECTION_HT_2S ||
714 rs == RTW_RATE_SECTION_VHT_2S)
715 continue;
716 rtw8821c_set_tx_power_index_by_rate(rtwdev, path, rs,
717 &phy_pwr_idx);
718 }
719 }
720 }
721
rtw8821c_false_alarm_statistics(struct rtw_dev * rtwdev)722 static void rtw8821c_false_alarm_statistics(struct rtw_dev *rtwdev)
723 {
724 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
725 u32 cck_enable;
726 u32 cck_fa_cnt;
727 u32 ofdm_fa_cnt;
728 u32 crc32_cnt;
729 u32 cca32_cnt;
730
731 cck_enable = rtw_read32(rtwdev, REG_RXPSEL) & BIT(28);
732 cck_fa_cnt = rtw_read16(rtwdev, REG_FA_CCK);
733 ofdm_fa_cnt = rtw_read16(rtwdev, REG_FA_OFDM);
734
735 dm_info->cck_fa_cnt = cck_fa_cnt;
736 dm_info->ofdm_fa_cnt = ofdm_fa_cnt;
737 dm_info->total_fa_cnt = ofdm_fa_cnt;
738 if (cck_enable)
739 dm_info->total_fa_cnt += cck_fa_cnt;
740
741 crc32_cnt = rtw_read32(rtwdev, REG_CRC_CCK);
742 dm_info->cck_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt);
743 dm_info->cck_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt);
744
745 crc32_cnt = rtw_read32(rtwdev, REG_CRC_OFDM);
746 dm_info->ofdm_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt);
747 dm_info->ofdm_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt);
748
749 crc32_cnt = rtw_read32(rtwdev, REG_CRC_HT);
750 dm_info->ht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt);
751 dm_info->ht_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt);
752
753 crc32_cnt = rtw_read32(rtwdev, REG_CRC_VHT);
754 dm_info->vht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt);
755 dm_info->vht_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt);
756
757 cca32_cnt = rtw_read32(rtwdev, REG_CCA_OFDM);
758 dm_info->ofdm_cca_cnt = FIELD_GET(GENMASK(31, 16), cca32_cnt);
759 dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt;
760 if (cck_enable) {
761 cca32_cnt = rtw_read32(rtwdev, REG_CCA_CCK);
762 dm_info->cck_cca_cnt = FIELD_GET(GENMASK(15, 0), cca32_cnt);
763 dm_info->total_cca_cnt += dm_info->cck_cca_cnt;
764 }
765
766 rtw_write32_set(rtwdev, REG_FAS, BIT(17));
767 rtw_write32_clr(rtwdev, REG_FAS, BIT(17));
768 rtw_write32_clr(rtwdev, REG_RXDESC, BIT(15));
769 rtw_write32_set(rtwdev, REG_RXDESC, BIT(15));
770 rtw_write32_set(rtwdev, REG_CNTRST, BIT(0));
771 rtw_write32_clr(rtwdev, REG_CNTRST, BIT(0));
772 }
773
rtw8821c_do_iqk(struct rtw_dev * rtwdev)774 static void rtw8821c_do_iqk(struct rtw_dev *rtwdev)
775 {
776 static int do_iqk_cnt;
777 struct rtw_iqk_para para = {.clear = 0, .segment_iqk = 0};
778 u32 rf_reg, iqk_fail_mask;
779 int counter;
780 bool reload;
781
782 if (rtw_is_assoc(rtwdev))
783 para.segment_iqk = 1;
784
785 rtw_fw_do_iqk(rtwdev, ¶);
786
787 for (counter = 0; counter < 300; counter++) {
788 rf_reg = rtw_read_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK);
789 if (rf_reg == 0xabcde)
790 break;
791 msleep(20);
792 }
793 rtw_write_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK, 0x0);
794
795 reload = !!rtw_read32_mask(rtwdev, REG_IQKFAILMSK, BIT(16));
796 iqk_fail_mask = rtw_read32_mask(rtwdev, REG_IQKFAILMSK, GENMASK(7, 0));
797 rtw_dbg(rtwdev, RTW_DBG_PHY,
798 "iqk counter=%d reload=%d do_iqk_cnt=%d n_iqk_fail(mask)=0x%02x\n",
799 counter, reload, ++do_iqk_cnt, iqk_fail_mask);
800 }
801
rtw8821c_phy_calibration(struct rtw_dev * rtwdev)802 static void rtw8821c_phy_calibration(struct rtw_dev *rtwdev)
803 {
804 rtw8821c_do_iqk(rtwdev);
805 }
806
807 /* for coex */
rtw8821c_coex_cfg_init(struct rtw_dev * rtwdev)808 static void rtw8821c_coex_cfg_init(struct rtw_dev *rtwdev)
809 {
810 /* enable TBTT nterrupt */
811 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
812
813 /* BT report packet sample rate */
814 rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5);
815
816 /* enable BT counter statistics */
817 rtw_write8(rtwdev, REG_BT_STAT_CTRL, BT_CNT_ENABLE);
818
819 /* enable PTA (3-wire function form BT side) */
820 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN);
821 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_PO_BT_PTA_PINS);
822
823 /* enable PTA (tx/rx signal form WiFi side) */
824 rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN);
825 /* wl tx signal to PTA not case EDCCA */
826 rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT_PTA_EDCCA_EN);
827 /* GNT_BT=1 while select both */
828 rtw_write16_set(rtwdev, REG_BT_COEX_V2, BIT_GNT_BT_POLARITY);
829
830 /* beacon queue always hi-pri */
831 rtw_write8_mask(rtwdev, REG_BT_COEX_TABLE_H + 3, BIT_BCN_QUEUE,
832 BCN_PRI_EN);
833 }
834
rtw8821c_coex_cfg_ant_switch(struct rtw_dev * rtwdev,u8 ctrl_type,u8 pos_type)835 static void rtw8821c_coex_cfg_ant_switch(struct rtw_dev *rtwdev, u8 ctrl_type,
836 u8 pos_type)
837 {
838 struct rtw_coex *coex = &rtwdev->coex;
839 struct rtw_coex_dm *coex_dm = &coex->dm;
840 struct rtw_coex_rfe *coex_rfe = &coex->rfe;
841 u32 switch_status = FIELD_PREP(CTRL_TYPE_MASK, ctrl_type) | pos_type;
842 bool polarity_inverse;
843 u8 regval = 0;
844
845 if (switch_status == coex_dm->cur_switch_status)
846 return;
847
848 if (coex_rfe->wlg_at_btg) {
849 ctrl_type = COEX_SWITCH_CTRL_BY_BBSW;
850
851 if (coex_rfe->ant_switch_polarity)
852 pos_type = COEX_SWITCH_TO_WLA;
853 else
854 pos_type = COEX_SWITCH_TO_WLG_BT;
855 }
856
857 coex_dm->cur_switch_status = switch_status;
858
859 if (coex_rfe->ant_switch_diversity &&
860 ctrl_type == COEX_SWITCH_CTRL_BY_BBSW)
861 ctrl_type = COEX_SWITCH_CTRL_BY_ANTDIV;
862
863 polarity_inverse = (coex_rfe->ant_switch_polarity == 1);
864
865 switch (ctrl_type) {
866 default:
867 case COEX_SWITCH_CTRL_BY_BBSW:
868 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
869 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL);
870 /* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */
871 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89,
872 DPDT_CTRL_PIN);
873
874 if (pos_type == COEX_SWITCH_TO_WLG_BT) {
875 if (coex_rfe->rfe_module_type != 0x4 &&
876 coex_rfe->rfe_module_type != 0x2)
877 regval = 0x3;
878 else
879 regval = (!polarity_inverse ? 0x2 : 0x1);
880 } else if (pos_type == COEX_SWITCH_TO_WLG) {
881 regval = (!polarity_inverse ? 0x2 : 0x1);
882 } else {
883 regval = (!polarity_inverse ? 0x1 : 0x2);
884 }
885
886 rtw_write32_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_R_RFE_SEL_15,
887 regval);
888 break;
889 case COEX_SWITCH_CTRL_BY_PTA:
890 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
891 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL);
892 /* PTA, DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */
893 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89,
894 PTA_CTRL_PIN);
895
896 regval = (!polarity_inverse ? 0x2 : 0x1);
897 rtw_write32_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_R_RFE_SEL_15,
898 regval);
899 break;
900 case COEX_SWITCH_CTRL_BY_ANTDIV:
901 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
902 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL);
903 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89,
904 ANTDIC_CTRL_PIN);
905 break;
906 case COEX_SWITCH_CTRL_BY_MAC:
907 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
908
909 regval = (!polarity_inverse ? 0x0 : 0x1);
910 rtw_write8_mask(rtwdev, REG_PAD_CTRL1, BIT_SW_DPDT_SEL_DATA,
911 regval);
912 break;
913 case COEX_SWITCH_CTRL_BY_FW:
914 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
915 rtw_write32_set(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL);
916 break;
917 case COEX_SWITCH_CTRL_BY_BT:
918 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN);
919 rtw_write32_clr(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL);
920 break;
921 }
922
923 if (ctrl_type == COEX_SWITCH_CTRL_BY_BT) {
924 rtw_write8_clr(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE1);
925 rtw_write8_clr(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE2);
926 } else {
927 rtw_write8_set(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE1);
928 rtw_write8_set(rtwdev, REG_CTRL_TYPE, BIT_CTRL_TYPE2);
929 }
930 }
931
rtw8821c_coex_cfg_gnt_fix(struct rtw_dev * rtwdev)932 static void rtw8821c_coex_cfg_gnt_fix(struct rtw_dev *rtwdev)
933 {}
934
rtw8821c_coex_cfg_gnt_debug(struct rtw_dev * rtwdev)935 static void rtw8821c_coex_cfg_gnt_debug(struct rtw_dev *rtwdev)
936 {
937 rtw_write32_clr(rtwdev, REG_PAD_CTRL1, BIT_BTGP_SPI_EN);
938 rtw_write32_clr(rtwdev, REG_PAD_CTRL1, BIT_BTGP_JTAG_EN);
939 rtw_write32_clr(rtwdev, REG_GPIO_MUXCFG, BIT_FSPI_EN);
940 rtw_write32_clr(rtwdev, REG_PAD_CTRL1, BIT_LED1DIS);
941 rtw_write32_clr(rtwdev, REG_SYS_SDIO_CTRL, BIT_SDIO_INT);
942 rtw_write32_clr(rtwdev, REG_SYS_SDIO_CTRL, BIT_DBG_GNT_WL_BT);
943 }
944
rtw8821c_coex_cfg_rfe_type(struct rtw_dev * rtwdev)945 static void rtw8821c_coex_cfg_rfe_type(struct rtw_dev *rtwdev)
946 {
947 struct rtw_coex *coex = &rtwdev->coex;
948 struct rtw_coex_rfe *coex_rfe = &coex->rfe;
949 struct rtw_efuse *efuse = &rtwdev->efuse;
950
951 coex_rfe->rfe_module_type = efuse->rfe_option;
952 coex_rfe->ant_switch_polarity = 0;
953 coex_rfe->ant_switch_exist = true;
954 coex_rfe->wlg_at_btg = false;
955
956 switch (coex_rfe->rfe_module_type) {
957 case 0:
958 case 8:
959 case 1:
960 case 9: /* 1-Ant, Main, WLG */
961 default: /* 2-Ant, DPDT, WLG */
962 break;
963 case 2:
964 case 10: /* 1-Ant, Main, BTG */
965 case 7:
966 case 15: /* 2-Ant, DPDT, BTG */
967 coex_rfe->wlg_at_btg = true;
968 break;
969 case 3:
970 case 11: /* 1-Ant, Aux, WLG */
971 coex_rfe->ant_switch_polarity = 1;
972 break;
973 case 4:
974 case 12: /* 1-Ant, Aux, BTG */
975 coex_rfe->wlg_at_btg = true;
976 coex_rfe->ant_switch_polarity = 1;
977 break;
978 case 5:
979 case 13: /* 2-Ant, no switch, WLG */
980 case 6:
981 case 14: /* 2-Ant, no antenna switch, WLG */
982 coex_rfe->ant_switch_exist = false;
983 break;
984 }
985 }
986
rtw8821c_coex_cfg_wl_tx_power(struct rtw_dev * rtwdev,u8 wl_pwr)987 static void rtw8821c_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr)
988 {
989 struct rtw_coex *coex = &rtwdev->coex;
990 struct rtw_coex_dm *coex_dm = &coex->dm;
991 struct rtw_efuse *efuse = &rtwdev->efuse;
992 bool share_ant = efuse->share_ant;
993
994 if (share_ant)
995 return;
996
997 if (wl_pwr == coex_dm->cur_wl_pwr_lvl)
998 return;
999
1000 coex_dm->cur_wl_pwr_lvl = wl_pwr;
1001 }
1002
rtw8821c_coex_cfg_wl_rx_gain(struct rtw_dev * rtwdev,bool low_gain)1003 static void rtw8821c_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain)
1004 {}
1005
1006 static void
rtw8821c_txagc_swing_offset(struct rtw_dev * rtwdev,u8 pwr_idx_offset,s8 pwr_idx_offset_lower,s8 * txagc_idx,u8 * swing_idx)1007 rtw8821c_txagc_swing_offset(struct rtw_dev *rtwdev, u8 pwr_idx_offset,
1008 s8 pwr_idx_offset_lower,
1009 s8 *txagc_idx, u8 *swing_idx)
1010 {
1011 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1012 s8 delta_pwr_idx = dm_info->delta_power_index[RF_PATH_A];
1013 u8 swing_upper_bound = dm_info->default_ofdm_index + 10;
1014 u8 swing_lower_bound = 0;
1015 u8 max_pwr_idx_offset = 0xf;
1016 s8 agc_index = 0;
1017 u8 swing_index = dm_info->default_ofdm_index;
1018
1019 pwr_idx_offset = min_t(u8, pwr_idx_offset, max_pwr_idx_offset);
1020 pwr_idx_offset_lower = max_t(s8, pwr_idx_offset_lower, -15);
1021
1022 if (delta_pwr_idx >= 0) {
1023 if (delta_pwr_idx <= pwr_idx_offset) {
1024 agc_index = delta_pwr_idx;
1025 swing_index = dm_info->default_ofdm_index;
1026 } else if (delta_pwr_idx > pwr_idx_offset) {
1027 agc_index = pwr_idx_offset;
1028 swing_index = dm_info->default_ofdm_index +
1029 delta_pwr_idx - pwr_idx_offset;
1030 swing_index = min_t(u8, swing_index, swing_upper_bound);
1031 }
1032 } else if (delta_pwr_idx < 0) {
1033 if (delta_pwr_idx >= pwr_idx_offset_lower) {
1034 agc_index = delta_pwr_idx;
1035 swing_index = dm_info->default_ofdm_index;
1036 } else if (delta_pwr_idx < pwr_idx_offset_lower) {
1037 if (dm_info->default_ofdm_index >
1038 (pwr_idx_offset_lower - delta_pwr_idx))
1039 swing_index = dm_info->default_ofdm_index +
1040 delta_pwr_idx - pwr_idx_offset_lower;
1041 else
1042 swing_index = swing_lower_bound;
1043
1044 agc_index = pwr_idx_offset_lower;
1045 }
1046 }
1047
1048 if (swing_index >= ARRAY_SIZE(rtw8821c_txscale_tbl)) {
1049 rtw_warn(rtwdev, "swing index overflow\n");
1050 swing_index = ARRAY_SIZE(rtw8821c_txscale_tbl) - 1;
1051 }
1052
1053 *txagc_idx = agc_index;
1054 *swing_idx = swing_index;
1055 }
1056
rtw8821c_pwrtrack_set_pwr(struct rtw_dev * rtwdev,u8 pwr_idx_offset,s8 pwr_idx_offset_lower)1057 static void rtw8821c_pwrtrack_set_pwr(struct rtw_dev *rtwdev, u8 pwr_idx_offset,
1058 s8 pwr_idx_offset_lower)
1059 {
1060 s8 txagc_idx;
1061 u8 swing_idx;
1062
1063 rtw8821c_txagc_swing_offset(rtwdev, pwr_idx_offset, pwr_idx_offset_lower,
1064 &txagc_idx, &swing_idx);
1065 rtw_write32_mask(rtwdev, REG_TXAGCIDX, GENMASK(6, 1), txagc_idx);
1066 rtw_write32_mask(rtwdev, REG_TXSCALE_A, GENMASK(31, 21),
1067 rtw8821c_txscale_tbl[swing_idx]);
1068 }
1069
rtw8821c_pwrtrack_set(struct rtw_dev * rtwdev)1070 static void rtw8821c_pwrtrack_set(struct rtw_dev *rtwdev)
1071 {
1072 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1073 u8 pwr_idx_offset, tx_pwr_idx;
1074 s8 pwr_idx_offset_lower;
1075 u8 channel = rtwdev->hal.current_channel;
1076 u8 band_width = rtwdev->hal.current_band_width;
1077 u8 regd = rtw_regd_get(rtwdev);
1078 u8 tx_rate = dm_info->tx_rate;
1079 u8 max_pwr_idx = rtwdev->chip->max_power_index;
1080
1081 tx_pwr_idx = rtw_phy_get_tx_power_index(rtwdev, RF_PATH_A, tx_rate,
1082 band_width, channel, regd);
1083
1084 tx_pwr_idx = min_t(u8, tx_pwr_idx, max_pwr_idx);
1085
1086 pwr_idx_offset = max_pwr_idx - tx_pwr_idx;
1087 pwr_idx_offset_lower = 0 - tx_pwr_idx;
1088
1089 rtw8821c_pwrtrack_set_pwr(rtwdev, pwr_idx_offset, pwr_idx_offset_lower);
1090 }
1091
rtw8821c_phy_pwrtrack(struct rtw_dev * rtwdev)1092 static void rtw8821c_phy_pwrtrack(struct rtw_dev *rtwdev)
1093 {
1094 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1095 struct rtw_swing_table swing_table;
1096 u8 thermal_value, delta;
1097
1098 rtw_phy_config_swing_table(rtwdev, &swing_table);
1099
1100 if (rtwdev->efuse.thermal_meter[0] == 0xff)
1101 return;
1102
1103 thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00);
1104
1105 rtw_phy_pwrtrack_avg(rtwdev, thermal_value, RF_PATH_A);
1106
1107 if (dm_info->pwr_trk_init_trigger)
1108 dm_info->pwr_trk_init_trigger = false;
1109 else if (!rtw_phy_pwrtrack_thermal_changed(rtwdev, thermal_value,
1110 RF_PATH_A))
1111 goto iqk;
1112
1113 delta = rtw_phy_pwrtrack_get_delta(rtwdev, RF_PATH_A);
1114
1115 delta = min_t(u8, delta, RTW_PWR_TRK_TBL_SZ - 1);
1116
1117 dm_info->delta_power_index[RF_PATH_A] =
1118 rtw_phy_pwrtrack_get_pwridx(rtwdev, &swing_table, RF_PATH_A,
1119 RF_PATH_A, delta);
1120 if (dm_info->delta_power_index[RF_PATH_A] ==
1121 dm_info->delta_power_index_last[RF_PATH_A])
1122 goto iqk;
1123 else
1124 dm_info->delta_power_index_last[RF_PATH_A] =
1125 dm_info->delta_power_index[RF_PATH_A];
1126 rtw8821c_pwrtrack_set(rtwdev);
1127
1128 iqk:
1129 if (rtw_phy_pwrtrack_need_iqk(rtwdev))
1130 rtw8821c_do_iqk(rtwdev);
1131 }
1132
rtw8821c_pwr_track(struct rtw_dev * rtwdev)1133 static void rtw8821c_pwr_track(struct rtw_dev *rtwdev)
1134 {
1135 struct rtw_efuse *efuse = &rtwdev->efuse;
1136 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1137
1138 if (efuse->power_track_type != 0)
1139 return;
1140
1141 if (!dm_info->pwr_trk_triggered) {
1142 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER,
1143 GENMASK(17, 16), 0x03);
1144 dm_info->pwr_trk_triggered = true;
1145 return;
1146 }
1147
1148 rtw8821c_phy_pwrtrack(rtwdev);
1149 dm_info->pwr_trk_triggered = false;
1150 }
1151
rtw8821c_bf_config_bfee_su(struct rtw_dev * rtwdev,struct rtw_vif * vif,struct rtw_bfee * bfee,bool enable)1152 static void rtw8821c_bf_config_bfee_su(struct rtw_dev *rtwdev,
1153 struct rtw_vif *vif,
1154 struct rtw_bfee *bfee, bool enable)
1155 {
1156 if (enable)
1157 rtw_bf_enable_bfee_su(rtwdev, vif, bfee);
1158 else
1159 rtw_bf_remove_bfee_su(rtwdev, bfee);
1160 }
1161
rtw8821c_bf_config_bfee_mu(struct rtw_dev * rtwdev,struct rtw_vif * vif,struct rtw_bfee * bfee,bool enable)1162 static void rtw8821c_bf_config_bfee_mu(struct rtw_dev *rtwdev,
1163 struct rtw_vif *vif,
1164 struct rtw_bfee *bfee, bool enable)
1165 {
1166 if (enable)
1167 rtw_bf_enable_bfee_mu(rtwdev, vif, bfee);
1168 else
1169 rtw_bf_remove_bfee_mu(rtwdev, bfee);
1170 }
1171
rtw8821c_bf_config_bfee(struct rtw_dev * rtwdev,struct rtw_vif * vif,struct rtw_bfee * bfee,bool enable)1172 static void rtw8821c_bf_config_bfee(struct rtw_dev *rtwdev, struct rtw_vif *vif,
1173 struct rtw_bfee *bfee, bool enable)
1174 {
1175 if (bfee->role == RTW_BFEE_SU)
1176 rtw8821c_bf_config_bfee_su(rtwdev, vif, bfee, enable);
1177 else if (bfee->role == RTW_BFEE_MU)
1178 rtw8821c_bf_config_bfee_mu(rtwdev, vif, bfee, enable);
1179 else
1180 rtw_warn(rtwdev, "wrong bfee role\n");
1181 }
1182
rtw8821c_phy_cck_pd_set(struct rtw_dev * rtwdev,u8 new_lvl)1183 static void rtw8821c_phy_cck_pd_set(struct rtw_dev *rtwdev, u8 new_lvl)
1184 {
1185 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1186 u8 pd[CCK_PD_LV_MAX] = {3, 7, 13, 13, 13};
1187 u8 cck_n_rx;
1188
1189 rtw_dbg(rtwdev, RTW_DBG_PHY, "lv: (%d) -> (%d)\n",
1190 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A], new_lvl);
1191
1192 if (dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] == new_lvl)
1193 return;
1194
1195 cck_n_rx = (rtw_read8_mask(rtwdev, REG_CCK0_FAREPORT, BIT_CCK0_2RX) &&
1196 rtw_read8_mask(rtwdev, REG_CCK0_FAREPORT, BIT_CCK0_MRC)) ? 2 : 1;
1197 rtw_dbg(rtwdev, RTW_DBG_PHY,
1198 "is_linked=%d, lv=%d, n_rx=%d, cs_ratio=0x%x, pd_th=0x%x, cck_fa_avg=%d\n",
1199 rtw_is_assoc(rtwdev), new_lvl, cck_n_rx,
1200 dm_info->cck_pd_default + new_lvl * 2,
1201 pd[new_lvl], dm_info->cck_fa_avg);
1202
1203 dm_info->cck_fa_avg = CCK_FA_AVG_RESET;
1204
1205 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] = new_lvl;
1206 rtw_write32_mask(rtwdev, REG_PWRTH, 0x3f0000, pd[new_lvl]);
1207 rtw_write32_mask(rtwdev, REG_PWRTH2, 0x1f0000,
1208 dm_info->cck_pd_default + new_lvl * 2);
1209 }
1210
rtw8821c_led_set(struct led_classdev * led,enum led_brightness brightness)1211 static void rtw8821c_led_set(struct led_classdev *led,
1212 enum led_brightness brightness)
1213 {
1214 struct rtw_dev *rtwdev = container_of(led, struct rtw_dev, led_cdev);
1215 u32 ledcfg;
1216
1217 ledcfg = rtw_read32(rtwdev, REG_LED_CFG);
1218 u32p_replace_bits(&ledcfg, BIT_LED_MODE_SW_CTRL, BIT_LED2_CM);
1219 ledcfg &= ~BIT_GPIO13_14_WL_CTRL_EN;
1220
1221 if (brightness == LED_OFF)
1222 ledcfg |= BIT_LED2_SV;
1223 else
1224 ledcfg &= ~BIT_LED2_SV;
1225
1226 rtw_write32(rtwdev, REG_LED_CFG, ledcfg);
1227 }
1228
rtw8821c_fill_txdesc_checksum(struct rtw_dev * rtwdev,struct rtw_tx_pkt_info * pkt_info,u8 * txdesc)1229 static void rtw8821c_fill_txdesc_checksum(struct rtw_dev *rtwdev,
1230 struct rtw_tx_pkt_info *pkt_info,
1231 u8 *txdesc)
1232 {
1233 fill_txdesc_checksum_common(txdesc, 16);
1234 }
1235
1236 static const struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8821c[] = {
1237 {0x0086,
1238 RTW_PWR_CUT_ALL_MSK,
1239 RTW_PWR_INTF_SDIO_MSK,
1240 RTW_PWR_ADDR_SDIO,
1241 RTW_PWR_CMD_WRITE, BIT(0), 0},
1242 {0x0086,
1243 RTW_PWR_CUT_ALL_MSK,
1244 RTW_PWR_INTF_SDIO_MSK,
1245 RTW_PWR_ADDR_SDIO,
1246 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
1247 {0x004A,
1248 RTW_PWR_CUT_ALL_MSK,
1249 RTW_PWR_INTF_USB_MSK,
1250 RTW_PWR_ADDR_MAC,
1251 RTW_PWR_CMD_WRITE, BIT(0), 0},
1252 {0x0005,
1253 RTW_PWR_CUT_ALL_MSK,
1254 RTW_PWR_INTF_ALL_MSK,
1255 RTW_PWR_ADDR_MAC,
1256 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0},
1257 {0x0300,
1258 RTW_PWR_CUT_ALL_MSK,
1259 RTW_PWR_INTF_PCI_MSK,
1260 RTW_PWR_ADDR_MAC,
1261 RTW_PWR_CMD_WRITE, 0xFF, 0},
1262 {0x0301,
1263 RTW_PWR_CUT_ALL_MSK,
1264 RTW_PWR_INTF_PCI_MSK,
1265 RTW_PWR_ADDR_MAC,
1266 RTW_PWR_CMD_WRITE, 0xFF, 0},
1267 {0xFFFF,
1268 RTW_PWR_CUT_ALL_MSK,
1269 RTW_PWR_INTF_ALL_MSK,
1270 0,
1271 RTW_PWR_CMD_END, 0, 0},
1272 };
1273
1274 static const struct rtw_pwr_seq_cmd trans_cardemu_to_act_8821c[] = {
1275 {0x0020,
1276 RTW_PWR_CUT_ALL_MSK,
1277 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1278 RTW_PWR_ADDR_MAC,
1279 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1280 {0x0001,
1281 RTW_PWR_CUT_ALL_MSK,
1282 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1283 RTW_PWR_ADDR_MAC,
1284 RTW_PWR_CMD_DELAY, 1, RTW_PWR_DELAY_MS},
1285 {0x0000,
1286 RTW_PWR_CUT_ALL_MSK,
1287 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1288 RTW_PWR_ADDR_MAC,
1289 RTW_PWR_CMD_WRITE, BIT(5), 0},
1290 {0x0005,
1291 RTW_PWR_CUT_ALL_MSK,
1292 RTW_PWR_INTF_ALL_MSK,
1293 RTW_PWR_ADDR_MAC,
1294 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
1295 {0x0075,
1296 RTW_PWR_CUT_ALL_MSK,
1297 RTW_PWR_INTF_PCI_MSK,
1298 RTW_PWR_ADDR_MAC,
1299 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1300 {0x0006,
1301 RTW_PWR_CUT_ALL_MSK,
1302 RTW_PWR_INTF_ALL_MSK,
1303 RTW_PWR_ADDR_MAC,
1304 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
1305 {0x0075,
1306 RTW_PWR_CUT_ALL_MSK,
1307 RTW_PWR_INTF_PCI_MSK,
1308 RTW_PWR_ADDR_MAC,
1309 RTW_PWR_CMD_WRITE, BIT(0), 0},
1310 {0x0006,
1311 RTW_PWR_CUT_ALL_MSK,
1312 RTW_PWR_INTF_ALL_MSK,
1313 RTW_PWR_ADDR_MAC,
1314 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1315 {0x0005,
1316 RTW_PWR_CUT_ALL_MSK,
1317 RTW_PWR_INTF_ALL_MSK,
1318 RTW_PWR_ADDR_MAC,
1319 RTW_PWR_CMD_WRITE, BIT(7), 0},
1320 {0x0005,
1321 RTW_PWR_CUT_ALL_MSK,
1322 RTW_PWR_INTF_ALL_MSK,
1323 RTW_PWR_ADDR_MAC,
1324 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
1325 {0x10C3,
1326 RTW_PWR_CUT_ALL_MSK,
1327 RTW_PWR_INTF_USB_MSK,
1328 RTW_PWR_ADDR_MAC,
1329 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1330 {0x0005,
1331 RTW_PWR_CUT_ALL_MSK,
1332 RTW_PWR_INTF_ALL_MSK,
1333 RTW_PWR_ADDR_MAC,
1334 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1335 {0x0005,
1336 RTW_PWR_CUT_ALL_MSK,
1337 RTW_PWR_INTF_ALL_MSK,
1338 RTW_PWR_ADDR_MAC,
1339 RTW_PWR_CMD_POLLING, BIT(0), 0},
1340 {0x0020,
1341 RTW_PWR_CUT_ALL_MSK,
1342 RTW_PWR_INTF_ALL_MSK,
1343 RTW_PWR_ADDR_MAC,
1344 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)},
1345 {0x0074,
1346 RTW_PWR_CUT_ALL_MSK,
1347 RTW_PWR_INTF_PCI_MSK,
1348 RTW_PWR_ADDR_MAC,
1349 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1350 {0x0022,
1351 RTW_PWR_CUT_ALL_MSK,
1352 RTW_PWR_INTF_PCI_MSK,
1353 RTW_PWR_ADDR_MAC,
1354 RTW_PWR_CMD_WRITE, BIT(1), 0},
1355 {0x0062,
1356 RTW_PWR_CUT_ALL_MSK,
1357 RTW_PWR_INTF_PCI_MSK,
1358 RTW_PWR_ADDR_MAC,
1359 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)),
1360 (BIT(7) | BIT(6) | BIT(5))},
1361 {0x0061,
1362 RTW_PWR_CUT_ALL_MSK,
1363 RTW_PWR_INTF_PCI_MSK,
1364 RTW_PWR_ADDR_MAC,
1365 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 0},
1366 {0x007C,
1367 RTW_PWR_CUT_ALL_MSK,
1368 RTW_PWR_INTF_ALL_MSK,
1369 RTW_PWR_ADDR_MAC,
1370 RTW_PWR_CMD_WRITE, BIT(1), 0},
1371 {0xFFFF,
1372 RTW_PWR_CUT_ALL_MSK,
1373 RTW_PWR_INTF_ALL_MSK,
1374 0,
1375 RTW_PWR_CMD_END, 0, 0},
1376 };
1377
1378 static const struct rtw_pwr_seq_cmd trans_act_to_cardemu_8821c[] = {
1379 {0x0093,
1380 RTW_PWR_CUT_ALL_MSK,
1381 RTW_PWR_INTF_ALL_MSK,
1382 RTW_PWR_ADDR_MAC,
1383 RTW_PWR_CMD_WRITE, BIT(3), 0},
1384 {0x001F,
1385 RTW_PWR_CUT_ALL_MSK,
1386 RTW_PWR_INTF_ALL_MSK,
1387 RTW_PWR_ADDR_MAC,
1388 RTW_PWR_CMD_WRITE, 0xFF, 0},
1389 {0x0049,
1390 RTW_PWR_CUT_ALL_MSK,
1391 RTW_PWR_INTF_ALL_MSK,
1392 RTW_PWR_ADDR_MAC,
1393 RTW_PWR_CMD_WRITE, BIT(1), 0},
1394 {0x0006,
1395 RTW_PWR_CUT_ALL_MSK,
1396 RTW_PWR_INTF_ALL_MSK,
1397 RTW_PWR_ADDR_MAC,
1398 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1399 {0x0002,
1400 RTW_PWR_CUT_ALL_MSK,
1401 RTW_PWR_INTF_ALL_MSK,
1402 RTW_PWR_ADDR_MAC,
1403 RTW_PWR_CMD_WRITE, BIT(1), 0},
1404 {0x10C3,
1405 RTW_PWR_CUT_ALL_MSK,
1406 RTW_PWR_INTF_USB_MSK,
1407 RTW_PWR_ADDR_MAC,
1408 RTW_PWR_CMD_WRITE, BIT(0), 0},
1409 {0x0005,
1410 RTW_PWR_CUT_ALL_MSK,
1411 RTW_PWR_INTF_ALL_MSK,
1412 RTW_PWR_ADDR_MAC,
1413 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
1414 {0x0005,
1415 RTW_PWR_CUT_ALL_MSK,
1416 RTW_PWR_INTF_ALL_MSK,
1417 RTW_PWR_ADDR_MAC,
1418 RTW_PWR_CMD_POLLING, BIT(1), 0},
1419 {0x0020,
1420 RTW_PWR_CUT_ALL_MSK,
1421 RTW_PWR_INTF_ALL_MSK,
1422 RTW_PWR_ADDR_MAC,
1423 RTW_PWR_CMD_WRITE, BIT(3), 0},
1424 {0x0000,
1425 RTW_PWR_CUT_ALL_MSK,
1426 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1427 RTW_PWR_ADDR_MAC,
1428 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1429 {0xFFFF,
1430 RTW_PWR_CUT_ALL_MSK,
1431 RTW_PWR_INTF_ALL_MSK,
1432 0,
1433 RTW_PWR_CMD_END, 0, 0},
1434 };
1435
1436 static const struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8821c[] = {
1437 {0x0007,
1438 RTW_PWR_CUT_ALL_MSK,
1439 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1440 RTW_PWR_ADDR_MAC,
1441 RTW_PWR_CMD_WRITE, 0xFF, 0x20},
1442 {0x0067,
1443 RTW_PWR_CUT_ALL_MSK,
1444 RTW_PWR_INTF_ALL_MSK,
1445 RTW_PWR_ADDR_MAC,
1446 RTW_PWR_CMD_WRITE, BIT(5), 0},
1447 {0x0005,
1448 RTW_PWR_CUT_ALL_MSK,
1449 RTW_PWR_INTF_PCI_MSK,
1450 RTW_PWR_ADDR_MAC,
1451 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)},
1452 {0x004A,
1453 RTW_PWR_CUT_ALL_MSK,
1454 RTW_PWR_INTF_USB_MSK,
1455 RTW_PWR_ADDR_MAC,
1456 RTW_PWR_CMD_WRITE, BIT(0), 0},
1457 {0x0067,
1458 RTW_PWR_CUT_ALL_MSK,
1459 RTW_PWR_INTF_SDIO_MSK,
1460 RTW_PWR_ADDR_MAC,
1461 RTW_PWR_CMD_WRITE, BIT(5), 0},
1462 {0x0067,
1463 RTW_PWR_CUT_ALL_MSK,
1464 RTW_PWR_INTF_SDIO_MSK,
1465 RTW_PWR_ADDR_MAC,
1466 RTW_PWR_CMD_WRITE, BIT(4), 0},
1467 {0x004F,
1468 RTW_PWR_CUT_ALL_MSK,
1469 RTW_PWR_INTF_SDIO_MSK,
1470 RTW_PWR_ADDR_MAC,
1471 RTW_PWR_CMD_WRITE, BIT(0), 0},
1472 {0x0067,
1473 RTW_PWR_CUT_ALL_MSK,
1474 RTW_PWR_INTF_SDIO_MSK,
1475 RTW_PWR_ADDR_MAC,
1476 RTW_PWR_CMD_WRITE, BIT(1), 0},
1477 {0x0046,
1478 RTW_PWR_CUT_ALL_MSK,
1479 RTW_PWR_INTF_SDIO_MSK,
1480 RTW_PWR_ADDR_MAC,
1481 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)},
1482 {0x0067,
1483 RTW_PWR_CUT_ALL_MSK,
1484 RTW_PWR_INTF_SDIO_MSK,
1485 RTW_PWR_ADDR_MAC,
1486 RTW_PWR_CMD_WRITE, BIT(2), 0},
1487 {0x0046,
1488 RTW_PWR_CUT_ALL_MSK,
1489 RTW_PWR_INTF_SDIO_MSK,
1490 RTW_PWR_ADDR_MAC,
1491 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)},
1492 {0x0062,
1493 RTW_PWR_CUT_ALL_MSK,
1494 RTW_PWR_INTF_SDIO_MSK,
1495 RTW_PWR_ADDR_MAC,
1496 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)},
1497 {0x0081,
1498 RTW_PWR_CUT_ALL_MSK,
1499 RTW_PWR_INTF_ALL_MSK,
1500 RTW_PWR_ADDR_MAC,
1501 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0},
1502 {0x0005,
1503 RTW_PWR_CUT_ALL_MSK,
1504 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1505 RTW_PWR_ADDR_MAC,
1506 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)},
1507 {0x0086,
1508 RTW_PWR_CUT_ALL_MSK,
1509 RTW_PWR_INTF_SDIO_MSK,
1510 RTW_PWR_ADDR_SDIO,
1511 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1512 {0x0086,
1513 RTW_PWR_CUT_ALL_MSK,
1514 RTW_PWR_INTF_SDIO_MSK,
1515 RTW_PWR_ADDR_SDIO,
1516 RTW_PWR_CMD_POLLING, BIT(1), 0},
1517 {0x0090,
1518 RTW_PWR_CUT_ALL_MSK,
1519 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_PCI_MSK,
1520 RTW_PWR_ADDR_MAC,
1521 RTW_PWR_CMD_WRITE, BIT(1), 0},
1522 {0x0044,
1523 RTW_PWR_CUT_ALL_MSK,
1524 RTW_PWR_INTF_SDIO_MSK,
1525 RTW_PWR_ADDR_SDIO,
1526 RTW_PWR_CMD_WRITE, 0xFF, 0},
1527 {0x0040,
1528 RTW_PWR_CUT_ALL_MSK,
1529 RTW_PWR_INTF_SDIO_MSK,
1530 RTW_PWR_ADDR_SDIO,
1531 RTW_PWR_CMD_WRITE, 0xFF, 0x90},
1532 {0x0041,
1533 RTW_PWR_CUT_ALL_MSK,
1534 RTW_PWR_INTF_SDIO_MSK,
1535 RTW_PWR_ADDR_SDIO,
1536 RTW_PWR_CMD_WRITE, 0xFF, 0x00},
1537 {0x0042,
1538 RTW_PWR_CUT_ALL_MSK,
1539 RTW_PWR_INTF_SDIO_MSK,
1540 RTW_PWR_ADDR_SDIO,
1541 RTW_PWR_CMD_WRITE, 0xFF, 0x04},
1542 {0xFFFF,
1543 RTW_PWR_CUT_ALL_MSK,
1544 RTW_PWR_INTF_ALL_MSK,
1545 0,
1546 RTW_PWR_CMD_END, 0, 0},
1547 };
1548
1549 static const struct rtw_pwr_seq_cmd * const card_enable_flow_8821c[] = {
1550 trans_carddis_to_cardemu_8821c,
1551 trans_cardemu_to_act_8821c,
1552 NULL
1553 };
1554
1555 static const struct rtw_pwr_seq_cmd * const card_disable_flow_8821c[] = {
1556 trans_act_to_cardemu_8821c,
1557 trans_cardemu_to_carddis_8821c,
1558 NULL
1559 };
1560
1561 static const struct rtw_intf_phy_para usb2_param_8821c[] = {
1562 {0xFFFF, 0x00,
1563 RTW_IP_SEL_PHY,
1564 RTW_INTF_PHY_CUT_ALL,
1565 RTW_INTF_PHY_PLATFORM_ALL},
1566 };
1567
1568 static const struct rtw_intf_phy_para usb3_param_8821c[] = {
1569 {0xFFFF, 0x0000,
1570 RTW_IP_SEL_PHY,
1571 RTW_INTF_PHY_CUT_ALL,
1572 RTW_INTF_PHY_PLATFORM_ALL},
1573 };
1574
1575 static const struct rtw_intf_phy_para pcie_gen1_param_8821c[] = {
1576 {0x0009, 0x6380,
1577 RTW_IP_SEL_PHY,
1578 RTW_INTF_PHY_CUT_ALL,
1579 RTW_INTF_PHY_PLATFORM_ALL},
1580 {0xFFFF, 0x0000,
1581 RTW_IP_SEL_PHY,
1582 RTW_INTF_PHY_CUT_ALL,
1583 RTW_INTF_PHY_PLATFORM_ALL},
1584 };
1585
1586 static const struct rtw_intf_phy_para pcie_gen2_param_8821c[] = {
1587 {0xFFFF, 0x0000,
1588 RTW_IP_SEL_PHY,
1589 RTW_INTF_PHY_CUT_ALL,
1590 RTW_INTF_PHY_PLATFORM_ALL},
1591 };
1592
1593 static const struct rtw_intf_phy_para_table phy_para_table_8821c = {
1594 .usb2_para = usb2_param_8821c,
1595 .usb3_para = usb3_param_8821c,
1596 .gen1_para = pcie_gen1_param_8821c,
1597 .gen2_para = pcie_gen2_param_8821c,
1598 .n_usb2_para = ARRAY_SIZE(usb2_param_8821c),
1599 .n_usb3_para = ARRAY_SIZE(usb2_param_8821c),
1600 .n_gen1_para = ARRAY_SIZE(pcie_gen1_param_8821c),
1601 .n_gen2_para = ARRAY_SIZE(pcie_gen2_param_8821c),
1602 };
1603
1604 static const struct rtw_hw_reg rtw8821c_dig[] = {
1605 [0] = { .addr = 0xc50, .mask = 0x7f },
1606 };
1607
1608 static const struct rtw_ltecoex_addr rtw8821c_ltecoex_addr = {
1609 .ctrl = LTECOEX_ACCESS_CTRL,
1610 .wdata = LTECOEX_WRITE_DATA,
1611 .rdata = LTECOEX_READ_DATA,
1612 };
1613
1614 static const struct rtw_page_table page_table_8821c[] = {
1615 /* not sure what [0] stands for */
1616 {16, 16, 16, 14, 1},
1617 {16, 16, 16, 14, 1},
1618 {16, 16, 0, 0, 1},
1619 {16, 16, 16, 0, 1},
1620 {16, 16, 16, 14, 1},
1621 };
1622
1623 static const struct rtw_rqpn rqpn_table_8821c[] = {
1624 /* not sure what [0] stands for */
1625 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1626 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
1627 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
1628 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1629 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
1630 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
1631 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1632 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH,
1633 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
1634 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1635 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
1636 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
1637 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
1638 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
1639 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
1640 };
1641
1642 static const struct rtw_prioq_addrs prioq_addrs_8821c = {
1643 .prio[RTW_DMA_MAPPING_EXTRA] = {
1644 .rsvd = REG_FIFOPAGE_INFO_4, .avail = REG_FIFOPAGE_INFO_4 + 2,
1645 },
1646 .prio[RTW_DMA_MAPPING_LOW] = {
1647 .rsvd = REG_FIFOPAGE_INFO_2, .avail = REG_FIFOPAGE_INFO_2 + 2,
1648 },
1649 .prio[RTW_DMA_MAPPING_NORMAL] = {
1650 .rsvd = REG_FIFOPAGE_INFO_3, .avail = REG_FIFOPAGE_INFO_3 + 2,
1651 },
1652 .prio[RTW_DMA_MAPPING_HIGH] = {
1653 .rsvd = REG_FIFOPAGE_INFO_1, .avail = REG_FIFOPAGE_INFO_1 + 2,
1654 },
1655 .wsize = true,
1656 };
1657
1658 static const struct rtw_chip_ops rtw8821c_ops = {
1659 .power_on = rtw_power_on,
1660 .power_off = rtw_power_off,
1661 .phy_set_param = rtw8821c_phy_set_param,
1662 .read_efuse = rtw8821c_read_efuse,
1663 .query_phy_status = query_phy_status,
1664 .set_channel = rtw8821c_set_channel,
1665 .mac_init = rtw8821c_mac_init,
1666 .read_rf = rtw_phy_read_rf,
1667 .write_rf = rtw_phy_write_rf_reg_sipi,
1668 .set_antenna = NULL,
1669 .set_tx_power_index = rtw8821c_set_tx_power_index,
1670 .cfg_ldo25 = rtw8821c_cfg_ldo25,
1671 .false_alarm_statistics = rtw8821c_false_alarm_statistics,
1672 .phy_calibration = rtw8821c_phy_calibration,
1673 .cck_pd_set = rtw8821c_phy_cck_pd_set,
1674 .pwr_track = rtw8821c_pwr_track,
1675 .config_bfee = rtw8821c_bf_config_bfee,
1676 .set_gid_table = rtw_bf_set_gid_table,
1677 .cfg_csi_rate = rtw_bf_cfg_csi_rate,
1678 .led_set = rtw8821c_led_set,
1679 .fill_txdesc_checksum = rtw8821c_fill_txdesc_checksum,
1680
1681 .coex_set_init = rtw8821c_coex_cfg_init,
1682 .coex_set_ant_switch = rtw8821c_coex_cfg_ant_switch,
1683 .coex_set_gnt_fix = rtw8821c_coex_cfg_gnt_fix,
1684 .coex_set_gnt_debug = rtw8821c_coex_cfg_gnt_debug,
1685 .coex_set_rfe_type = rtw8821c_coex_cfg_rfe_type,
1686 .coex_set_wl_tx_power = rtw8821c_coex_cfg_wl_tx_power,
1687 .coex_set_wl_rx_gain = rtw8821c_coex_cfg_wl_rx_gain,
1688 };
1689
1690 /* rssi in percentage % (dbm = % - 100) */
1691 static const u8 wl_rssi_step_8821c[] = {101, 45, 101, 40};
1692 static const u8 bt_rssi_step_8821c[] = {101, 101, 101, 101};
1693
1694 /* Shared-Antenna Coex Table */
1695 static const struct coex_table_para table_sant_8821c[] = {
1696 {0x55555555, 0x55555555}, /* case-0 */
1697 {0x55555555, 0x55555555},
1698 {0x66555555, 0x66555555},
1699 {0xaaaaaaaa, 0xaaaaaaaa},
1700 {0x5a5a5a5a, 0x5a5a5a5a},
1701 {0xfafafafa, 0xfafafafa}, /* case-5 */
1702 {0x6a5a5555, 0xaaaaaaaa},
1703 {0x6a5a56aa, 0x6a5a56aa},
1704 {0x6a5a5a5a, 0x6a5a5a5a},
1705 {0x66555555, 0x5a5a5a5a},
1706 {0x66555555, 0x6a5a5a5a}, /* case-10 */
1707 {0x66555555, 0xaaaaaaaa},
1708 {0x66555555, 0x6a5a5aaa},
1709 {0x66555555, 0x6aaa6aaa},
1710 {0x66555555, 0x6a5a5aaa},
1711 {0x66555555, 0xaaaaaaaa}, /* case-15 */
1712 {0xffff55ff, 0xfafafafa},
1713 {0xffff55ff, 0x6afa5afa},
1714 {0xaaffffaa, 0xfafafafa},
1715 {0xaa5555aa, 0x5a5a5a5a},
1716 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
1717 {0xaa5555aa, 0xaaaaaaaa},
1718 {0xffffffff, 0x55555555},
1719 {0xffffffff, 0x5a5a5a5a},
1720 {0xffffffff, 0x5a5a5a5a},
1721 {0xffffffff, 0x5a5a5aaa}, /* case-25 */
1722 {0x55555555, 0x5a5a5a5a},
1723 {0x55555555, 0xaaaaaaaa},
1724 {0x66555555, 0x6a5a6a5a},
1725 {0x66556655, 0x66556655},
1726 {0x66556aaa, 0x6a5a6aaa}, /* case-30 */
1727 {0xffffffff, 0x5aaa5aaa},
1728 {0x56555555, 0x5a5a5aaa}
1729 };
1730
1731 /* Non-Shared-Antenna Coex Table */
1732 static const struct coex_table_para table_nsant_8821c[] = {
1733 {0xffffffff, 0xffffffff}, /* case-100 */
1734 {0xffff55ff, 0xfafafafa},
1735 {0x66555555, 0x66555555},
1736 {0xaaaaaaaa, 0xaaaaaaaa},
1737 {0x5a5a5a5a, 0x5a5a5a5a},
1738 {0xffffffff, 0xffffffff}, /* case-105 */
1739 {0x5afa5afa, 0x5afa5afa},
1740 {0x55555555, 0xfafafafa},
1741 {0x66555555, 0xfafafafa},
1742 {0x66555555, 0x5a5a5a5a},
1743 {0x66555555, 0x6a5a5a5a}, /* case-110 */
1744 {0x66555555, 0xaaaaaaaa},
1745 {0xffff55ff, 0xfafafafa},
1746 {0xffff55ff, 0x5afa5afa},
1747 {0xffff55ff, 0xaaaaaaaa},
1748 {0xffff55ff, 0xffff55ff}, /* case-115 */
1749 {0xaaffffaa, 0x5afa5afa},
1750 {0xaaffffaa, 0xaaaaaaaa},
1751 {0xffffffff, 0xfafafafa},
1752 {0xffff55ff, 0xfafafafa},
1753 {0xffffffff, 0xaaaaaaaa}, /* case-120 */
1754 {0xffff55ff, 0x5afa5afa},
1755 {0xffff55ff, 0x5afa5afa},
1756 {0x55ff55ff, 0x55ff55ff}
1757 };
1758
1759 /* Shared-Antenna TDMA */
1760 static const struct coex_tdma_para tdma_sant_8821c[] = {
1761 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
1762 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */
1763 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
1764 { {0x61, 0x35, 0x03, 0x11, 0x11} },
1765 { {0x61, 0x20, 0x03, 0x11, 0x11} },
1766 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, /* case-5 */
1767 { {0x61, 0x45, 0x03, 0x11, 0x10} },
1768 { {0x61, 0x35, 0x03, 0x11, 0x10} },
1769 { {0x61, 0x30, 0x03, 0x11, 0x10} },
1770 { {0x61, 0x20, 0x03, 0x11, 0x10} },
1771 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
1772 { {0x61, 0x08, 0x03, 0x11, 0x15} },
1773 { {0x61, 0x08, 0x03, 0x10, 0x14} },
1774 { {0x51, 0x08, 0x03, 0x10, 0x54} },
1775 { {0x51, 0x08, 0x03, 0x10, 0x55} },
1776 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
1777 { {0x51, 0x45, 0x03, 0x10, 0x50} },
1778 { {0x51, 0x3a, 0x03, 0x11, 0x50} },
1779 { {0x51, 0x30, 0x03, 0x10, 0x50} },
1780 { {0x51, 0x21, 0x03, 0x10, 0x50} },
1781 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
1782 { {0x51, 0x4a, 0x03, 0x10, 0x50} },
1783 { {0x51, 0x08, 0x03, 0x30, 0x54} },
1784 { {0x55, 0x08, 0x03, 0x10, 0x54} },
1785 { {0x65, 0x10, 0x03, 0x11, 0x10} },
1786 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
1787 { {0x51, 0x21, 0x03, 0x10, 0x50} },
1788 { {0x61, 0x08, 0x03, 0x11, 0x11} }
1789 };
1790
1791 /* Non-Shared-Antenna TDMA */
1792 static const struct coex_tdma_para tdma_nsant_8821c[] = {
1793 { {0x00, 0x00, 0x00, 0x40, 0x00} }, /* case-100 */
1794 { {0x61, 0x45, 0x03, 0x11, 0x11} },
1795 { {0x61, 0x25, 0x03, 0x11, 0x11} },
1796 { {0x61, 0x35, 0x03, 0x11, 0x11} },
1797 { {0x61, 0x20, 0x03, 0x11, 0x11} },
1798 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */
1799 { {0x61, 0x45, 0x03, 0x11, 0x10} },
1800 { {0x61, 0x30, 0x03, 0x11, 0x10} },
1801 { {0x61, 0x30, 0x03, 0x11, 0x10} },
1802 { {0x61, 0x20, 0x03, 0x11, 0x10} },
1803 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */
1804 { {0x61, 0x10, 0x03, 0x11, 0x11} },
1805 { {0x61, 0x08, 0x03, 0x10, 0x14} },
1806 { {0x51, 0x08, 0x03, 0x10, 0x54} },
1807 { {0x51, 0x08, 0x03, 0x10, 0x55} },
1808 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */
1809 { {0x51, 0x45, 0x03, 0x10, 0x50} },
1810 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
1811 { {0x51, 0x30, 0x03, 0x10, 0x50} },
1812 { {0x51, 0x21, 0x03, 0x10, 0x50} },
1813 { {0x51, 0x21, 0x03, 0x10, 0x50} }, /* case-120 */
1814 { {0x51, 0x10, 0x03, 0x10, 0x50} }
1815 };
1816
1817 static const struct coex_5g_afh_map afh_5g_8821c[] = { {0, 0, 0} };
1818
1819 /* wl_tx_dec_power, bt_tx_dec_power, wl_rx_gain, bt_rx_lna_constrain */
1820 static const struct coex_rf_para rf_para_tx_8821c[] = {
1821 {0, 0, false, 7}, /* for normal */
1822 {0, 20, false, 7}, /* for WL-CPT */
1823 {8, 17, true, 4},
1824 {7, 18, true, 4},
1825 {6, 19, true, 4},
1826 {5, 20, true, 4}
1827 };
1828
1829 static const struct coex_rf_para rf_para_rx_8821c[] = {
1830 {0, 0, false, 7}, /* for normal */
1831 {0, 20, false, 7}, /* for WL-CPT */
1832 {3, 24, true, 5},
1833 {2, 26, true, 5},
1834 {1, 27, true, 5},
1835 {0, 28, true, 5}
1836 };
1837
1838 static_assert(ARRAY_SIZE(rf_para_tx_8821c) == ARRAY_SIZE(rf_para_rx_8821c));
1839
1840 static const u8 rtw8821c_pwrtrk_5gb_n[][RTW_PWR_TRK_TBL_SZ] = {
1841 {0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10,
1842 11, 11, 12, 12, 12, 12, 12},
1843 {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11,
1844 11, 12, 12, 12, 12, 12, 12, 12},
1845 {0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11,
1846 11, 12, 12, 12, 12, 12, 12},
1847 };
1848
1849 static const u8 rtw8821c_pwrtrk_5gb_p[][RTW_PWR_TRK_TBL_SZ] = {
1850 {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11,
1851 12, 12, 12, 12, 12, 12, 12},
1852 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11,
1853 12, 12, 12, 12, 12, 12, 12, 12},
1854 {0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11,
1855 11, 12, 12, 12, 12, 12, 12, 12},
1856 };
1857
1858 static const u8 rtw8821c_pwrtrk_5ga_n[][RTW_PWR_TRK_TBL_SZ] = {
1859 {0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10,
1860 11, 11, 12, 12, 12, 12, 12},
1861 {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11,
1862 11, 12, 12, 12, 12, 12, 12, 12},
1863 {0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11,
1864 11, 12, 12, 12, 12, 12, 12},
1865 };
1866
1867 static const u8 rtw8821c_pwrtrk_5ga_p[][RTW_PWR_TRK_TBL_SZ] = {
1868 {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11,
1869 12, 12, 12, 12, 12, 12, 12},
1870 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11,
1871 12, 12, 12, 12, 12, 12, 12, 12},
1872 {0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11,
1873 11, 12, 12, 12, 12, 12, 12, 12},
1874 };
1875
1876 static const u8 rtw8821c_pwrtrk_2gb_n[] = {
1877 0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4,
1878 4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9
1879 };
1880
1881 static const u8 rtw8821c_pwrtrk_2gb_p[] = {
1882 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5,
1883 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9
1884 };
1885
1886 static const u8 rtw8821c_pwrtrk_2ga_n[] = {
1887 0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4,
1888 4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9
1889 };
1890
1891 static const u8 rtw8821c_pwrtrk_2ga_p[] = {
1892 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5,
1893 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9
1894 };
1895
1896 static const u8 rtw8821c_pwrtrk_2g_cck_b_n[] = {
1897 0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4,
1898 4, 5, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9
1899 };
1900
1901 static const u8 rtw8821c_pwrtrk_2g_cck_b_p[] = {
1902 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5,
1903 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9
1904 };
1905
1906 static const u8 rtw8821c_pwrtrk_2g_cck_a_n[] = {
1907 0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4,
1908 4, 5, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9
1909 };
1910
1911 static const u8 rtw8821c_pwrtrk_2g_cck_a_p[] = {
1912 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5,
1913 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9
1914 };
1915
1916 static const struct rtw_pwr_track_tbl rtw8821c_pwr_track_type0_tbl = {
1917 .pwrtrk_5gb_n[0] = rtw8821c_pwrtrk_5gb_n[0],
1918 .pwrtrk_5gb_n[1] = rtw8821c_pwrtrk_5gb_n[1],
1919 .pwrtrk_5gb_n[2] = rtw8821c_pwrtrk_5gb_n[2],
1920 .pwrtrk_5gb_p[0] = rtw8821c_pwrtrk_5gb_p[0],
1921 .pwrtrk_5gb_p[1] = rtw8821c_pwrtrk_5gb_p[1],
1922 .pwrtrk_5gb_p[2] = rtw8821c_pwrtrk_5gb_p[2],
1923 .pwrtrk_5ga_n[0] = rtw8821c_pwrtrk_5ga_n[0],
1924 .pwrtrk_5ga_n[1] = rtw8821c_pwrtrk_5ga_n[1],
1925 .pwrtrk_5ga_n[2] = rtw8821c_pwrtrk_5ga_n[2],
1926 .pwrtrk_5ga_p[0] = rtw8821c_pwrtrk_5ga_p[0],
1927 .pwrtrk_5ga_p[1] = rtw8821c_pwrtrk_5ga_p[1],
1928 .pwrtrk_5ga_p[2] = rtw8821c_pwrtrk_5ga_p[2],
1929 .pwrtrk_2gb_n = rtw8821c_pwrtrk_2gb_n,
1930 .pwrtrk_2gb_p = rtw8821c_pwrtrk_2gb_p,
1931 .pwrtrk_2ga_n = rtw8821c_pwrtrk_2ga_n,
1932 .pwrtrk_2ga_p = rtw8821c_pwrtrk_2ga_p,
1933 .pwrtrk_2g_cckb_n = rtw8821c_pwrtrk_2g_cck_b_n,
1934 .pwrtrk_2g_cckb_p = rtw8821c_pwrtrk_2g_cck_b_p,
1935 .pwrtrk_2g_ccka_n = rtw8821c_pwrtrk_2g_cck_a_n,
1936 .pwrtrk_2g_ccka_p = rtw8821c_pwrtrk_2g_cck_a_p,
1937 };
1938
1939 static const struct rtw_rfe_def rtw8821c_rfe_defs[] = {
1940 [0] = RTW_DEF_RFE(8821c, 0, 0, 0),
1941 [2] = RTW_DEF_RFE_EXT(8821c, 0, 0, 0, 2),
1942 [4] = RTW_DEF_RFE_EXT(8821c, 0, 0, 0, 2),
1943 [6] = RTW_DEF_RFE(8821c, 0, 0, 0),
1944 };
1945
1946 static const struct rtw_reg_domain coex_info_hw_regs_8821c[] = {
1947 {0xCB0, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1948 {0xCB4, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1949 {0xCBA, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1950 {0, 0, RTW_REG_DOMAIN_NL},
1951 {0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1952 {0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1953 {0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16},
1954 {0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1955 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8},
1956 {0x454, MASKLWORD, RTW_REG_DOMAIN_MAC16},
1957 {0, 0, RTW_REG_DOMAIN_NL},
1958 {0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32},
1959 {0x64, BIT(0), RTW_REG_DOMAIN_MAC8},
1960 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8},
1961 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8},
1962 {0x1, RFREG_MASK, RTW_REG_DOMAIN_RF_A},
1963 {0, 0, RTW_REG_DOMAIN_NL},
1964 {0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1965 {0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1966 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8},
1967 {0xc50, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1968 {0x60A, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1969 };
1970
1971 const struct rtw_chip_info rtw8821c_hw_spec = {
1972 .ops = &rtw8821c_ops,
1973 .id = RTW_CHIP_TYPE_8821C,
1974 .fw_name = "rtw88/rtw8821c_fw.bin",
1975 .wlan_cpu = RTW_WCPU_11AC,
1976 .tx_pkt_desc_sz = 48,
1977 .tx_buf_desc_sz = 16,
1978 .rx_pkt_desc_sz = 24,
1979 .rx_buf_desc_sz = 8,
1980 .phy_efuse_size = 512,
1981 .log_efuse_size = 512,
1982 .ptct_efuse_size = 96,
1983 .txff_size = 65536,
1984 .rxff_size = 16384,
1985 .rsvd_drv_pg_num = 8,
1986 .txgi_factor = 1,
1987 .is_pwr_by_rate_dec = true,
1988 .max_power_index = 0x3f,
1989 .csi_buf_pg_num = 0,
1990 .band = RTW_BAND_2G | RTW_BAND_5G,
1991 .page_size = TX_PAGE_SIZE,
1992 .dig_min = 0x1c,
1993 .usb_tx_agg_desc_num = 3,
1994 .hw_feature_report = true,
1995 .c2h_ra_report_size = 7,
1996 .old_datarate_fb_limit = false,
1997 .ht_supported = true,
1998 .vht_supported = true,
1999 .lps_deep_mode_supported = BIT(LPS_DEEP_MODE_LCLK),
2000 .sys_func_en = 0xD8,
2001 .pwr_on_seq = card_enable_flow_8821c,
2002 .pwr_off_seq = card_disable_flow_8821c,
2003 .page_table = page_table_8821c,
2004 .rqpn_table = rqpn_table_8821c,
2005 .prioq_addrs = &prioq_addrs_8821c,
2006 .intf_table = &phy_para_table_8821c,
2007 .dig = rtw8821c_dig,
2008 .rf_base_addr = {0x2800, 0x2c00},
2009 .rf_sipi_addr = {0xc90, 0xe90},
2010 .ltecoex_addr = &rtw8821c_ltecoex_addr,
2011 .mac_tbl = &rtw8821c_mac_tbl,
2012 .agc_tbl = &rtw8821c_agc_tbl,
2013 .bb_tbl = &rtw8821c_bb_tbl,
2014 .rf_tbl = {&rtw8821c_rf_a_tbl},
2015 .rfe_defs = rtw8821c_rfe_defs,
2016 .rfe_defs_size = ARRAY_SIZE(rtw8821c_rfe_defs),
2017 .rx_ldpc = false,
2018 .iqk_threshold = 8,
2019 .bfer_su_max_num = 2,
2020 .bfer_mu_max_num = 1,
2021 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_2,
2022 .max_scan_ie_len = IEEE80211_MAX_DATA_LEN,
2023
2024 .coex_para_ver = 0x19092746,
2025 .bt_desired_ver = 0x46,
2026 .scbd_support = true,
2027 .new_scbd10_def = false,
2028 .ble_hid_profile_support = false,
2029 .wl_mimo_ps_support = false,
2030 .pstdma_type = COEX_PSTDMA_FORCE_LPSOFF,
2031 .bt_rssi_type = COEX_BTRSSI_RATIO,
2032 .ant_isolation = 15,
2033 .rssi_tolerance = 2,
2034 .wl_rssi_step = wl_rssi_step_8821c,
2035 .bt_rssi_step = bt_rssi_step_8821c,
2036 .table_sant_num = ARRAY_SIZE(table_sant_8821c),
2037 .table_sant = table_sant_8821c,
2038 .table_nsant_num = ARRAY_SIZE(table_nsant_8821c),
2039 .table_nsant = table_nsant_8821c,
2040 .tdma_sant_num = ARRAY_SIZE(tdma_sant_8821c),
2041 .tdma_sant = tdma_sant_8821c,
2042 .tdma_nsant_num = ARRAY_SIZE(tdma_nsant_8821c),
2043 .tdma_nsant = tdma_nsant_8821c,
2044 .wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8821c),
2045 .wl_rf_para_tx = rf_para_tx_8821c,
2046 .wl_rf_para_rx = rf_para_rx_8821c,
2047 .bt_afh_span_bw20 = 0x24,
2048 .bt_afh_span_bw40 = 0x36,
2049 .afh_5g_num = ARRAY_SIZE(afh_5g_8821c),
2050 .afh_5g = afh_5g_8821c,
2051
2052 .coex_info_hw_regs_num = ARRAY_SIZE(coex_info_hw_regs_8821c),
2053 .coex_info_hw_regs = coex_info_hw_regs_8821c,
2054 };
2055 EXPORT_SYMBOL(rtw8821c_hw_spec);
2056
2057 MODULE_FIRMWARE("rtw88/rtw8821c_fw.bin");
2058
2059 MODULE_AUTHOR("Realtek Corporation");
2060 MODULE_DESCRIPTION("Realtek 802.11ac wireless 8821c driver");
2061 MODULE_LICENSE("Dual BSD/GPL");
2062