1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
3 */
4
5 #include <linux/module.h>
6 #include "main.h"
7 #include "coex.h"
8 #include "fw.h"
9 #include "tx.h"
10 #include "rx.h"
11 #include "phy.h"
12 #include "rtw8723x.h"
13 #include "rtw8723d.h"
14 #include "rtw8723d_table.h"
15 #include "mac.h"
16 #include "reg.h"
17 #include "debug.h"
18
19 #define WLAN_SLOT_TIME 0x09
20 #define WLAN_RL_VAL 0x3030
21 #define WLAN_BAR_VAL 0x0201ffff
22 #define BIT_MASK_TBTT_HOLD 0x00000fff
23 #define BIT_SHIFT_TBTT_HOLD 8
24 #define BIT_MASK_TBTT_SETUP 0x000000ff
25 #define BIT_SHIFT_TBTT_SETUP 0
26 #define BIT_MASK_TBTT_MASK ((BIT_MASK_TBTT_HOLD << BIT_SHIFT_TBTT_HOLD) | \
27 (BIT_MASK_TBTT_SETUP << BIT_SHIFT_TBTT_SETUP))
28 #define TBTT_TIME(s, h)((((s) & BIT_MASK_TBTT_SETUP) << BIT_SHIFT_TBTT_SETUP) |\
29 (((h) & BIT_MASK_TBTT_HOLD) << BIT_SHIFT_TBTT_HOLD))
30 #define WLAN_TBTT_TIME_NORMAL TBTT_TIME(0x04, 0x80)
31 #define WLAN_TBTT_TIME_STOP_BCN TBTT_TIME(0x04, 0x64)
32 #define WLAN_PIFS_VAL 0
33 #define WLAN_AGG_BRK_TIME 0x16
34 #define WLAN_NAV_PROT_LEN 0x0040
35 #define WLAN_SPEC_SIFS 0x100a
36 #define WLAN_RX_PKT_LIMIT 0x17
37 #define WLAN_MAX_AGG_NR 0x0A
38 #define WLAN_AMPDU_MAX_TIME 0x1C
39 #define WLAN_ANT_SEL 0x82
40 #define WLAN_LTR_IDLE_LAT 0x90039003
41 #define WLAN_LTR_ACT_LAT 0x883c883c
42 #define WLAN_LTR_CTRL1 0xCB004010
43 #define WLAN_LTR_CTRL2 0x01233425
44
45 static const u32 rtw8723d_ofdm_swing_table[] = {
46 0x0b40002d, 0x0c000030, 0x0cc00033, 0x0d800036, 0x0e400039, 0x0f00003c,
47 0x10000040, 0x11000044, 0x12000048, 0x1300004c, 0x14400051, 0x15800056,
48 0x16c0005b, 0x18000060, 0x19800066, 0x1b00006c, 0x1c800072, 0x1e400079,
49 0x20000080, 0x22000088, 0x24000090, 0x26000098, 0x288000a2, 0x2ac000ab,
50 0x2d4000b5, 0x300000c0, 0x32c000cb, 0x35c000d7, 0x390000e4, 0x3c8000f2,
51 0x40000100, 0x43c0010f, 0x47c0011f, 0x4c000130, 0x50800142, 0x55400155,
52 0x5a400169, 0x5fc0017f, 0x65400195, 0x6b8001ae, 0x71c001c7, 0x788001e2,
53 0x7f8001fe,
54 };
55
56 static const u32 rtw8723d_cck_swing_table[] = {
57 0x0CD, 0x0D9, 0x0E6, 0x0F3, 0x102, 0x111, 0x121, 0x132, 0x144, 0x158,
58 0x16C, 0x182, 0x198, 0x1B1, 0x1CA, 0x1E5, 0x202, 0x221, 0x241, 0x263,
59 0x287, 0x2AE, 0x2D6, 0x301, 0x32F, 0x35F, 0x392, 0x3C9, 0x402, 0x43F,
60 0x47F, 0x4C3, 0x50C, 0x558, 0x5A9, 0x5FF, 0x65A, 0x6BA, 0x720, 0x78C,
61 0x7FF,
62 };
63
64 #define RTW_OFDM_SWING_TABLE_SIZE ARRAY_SIZE(rtw8723d_ofdm_swing_table)
65 #define RTW_CCK_SWING_TABLE_SIZE ARRAY_SIZE(rtw8723d_cck_swing_table)
66
rtw8723d_pwrtrack_init(struct rtw_dev * rtwdev)67 static void rtw8723d_pwrtrack_init(struct rtw_dev *rtwdev)
68 {
69 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
70 u8 path;
71
72 dm_info->default_ofdm_index = RTW_DEF_OFDM_SWING_INDEX;
73
74 for (path = RF_PATH_A; path < rtwdev->hal.rf_path_num; path++) {
75 ewma_thermal_init(&dm_info->avg_thermal[path]);
76 dm_info->delta_power_index[path] = 0;
77 }
78 dm_info->pwr_trk_triggered = false;
79 dm_info->pwr_trk_init_trigger = true;
80 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k;
81 dm_info->txagc_remnant_cck = 0;
82 dm_info->txagc_remnant_ofdm = 0;
83 }
84
rtw8723d_phy_set_param(struct rtw_dev * rtwdev)85 static void rtw8723d_phy_set_param(struct rtw_dev *rtwdev)
86 {
87 u8 xtal_cap;
88 u32 val32;
89
90 /* power on BB/RF domain */
91 rtw_write16_set(rtwdev, REG_SYS_FUNC_EN,
92 BIT_FEN_EN_25_1 | BIT_FEN_BB_GLB_RST | BIT_FEN_BB_RSTB);
93 rtw_write8_set(rtwdev, REG_RF_CTRL,
94 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB);
95 rtw_write8(rtwdev, REG_AFE_CTRL1 + 1, 0x80);
96
97 rtw_phy_load_tables(rtwdev);
98
99 /* post init after header files config */
100 rtw_write32_clr(rtwdev, REG_RCR, BIT_RCR_ADF);
101 rtw_write8_set(rtwdev, REG_HIQ_NO_LMT_EN, BIT_HIQ_NO_LMT_EN_ROOT);
102 rtw_write16_set(rtwdev, REG_AFE_CTRL_4, BIT_CK320M_AFE_EN | BIT_EN_SYN);
103
104 xtal_cap = rtwdev->efuse.crystal_cap & 0x3F;
105 rtw_write32_mask(rtwdev, REG_AFE_CTRL3, BIT_MASK_XTAL,
106 xtal_cap | (xtal_cap << 6));
107 rtw_write32_set(rtwdev, REG_FPGA0_RFMOD, BIT_CCKEN | BIT_OFDMEN);
108 if ((rtwdev->efuse.afe >> 4) == 14) {
109 rtw_write32_set(rtwdev, REG_AFE_CTRL3, BIT_XTAL_GMP_BIT4);
110 rtw_write32_clr(rtwdev, REG_AFE_CTRL1, BITS_PLL);
111 rtw_write32_set(rtwdev, REG_LDO_SWR_CTRL, BIT_XTA1);
112 rtw_write32_clr(rtwdev, REG_LDO_SWR_CTRL, BIT_XTA0);
113 }
114
115 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME);
116 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL + 1, WLAN_TXQ_RPT_EN);
117 rtw_write16(rtwdev, REG_RETRY_LIMIT, WLAN_RL_VAL);
118 rtw_write32(rtwdev, REG_BAR_MODE_CTRL, WLAN_BAR_VAL);
119 rtw_write8(rtwdev, REG_ATIMWND, 0x2);
120 rtw_write8(rtwdev, REG_BCN_CTRL,
121 BIT_DIS_TSF_UDT | BIT_EN_BCN_FUNCTION | BIT_EN_TXBCN_RPT);
122 val32 = rtw_read32(rtwdev, REG_TBTT_PROHIBIT);
123 val32 &= ~BIT_MASK_TBTT_MASK;
124 val32 |= WLAN_TBTT_TIME_STOP_BCN;
125 rtw_write8(rtwdev, REG_TBTT_PROHIBIT, val32);
126 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_VAL);
127 rtw_write8(rtwdev, REG_AGGR_BREAK_TIME, WLAN_AGG_BRK_TIME);
128 rtw_write16(rtwdev, REG_NAV_PROT_LEN, WLAN_NAV_PROT_LEN);
129 rtw_write16(rtwdev, REG_MAC_SPEC_SIFS, WLAN_SPEC_SIFS);
130 rtw_write16(rtwdev, REG_SIFS, WLAN_SPEC_SIFS);
131 rtw_write16(rtwdev, REG_SIFS + 2, WLAN_SPEC_SIFS);
132 rtw_write8(rtwdev, REG_SINGLE_AMPDU_CTRL, BIT_EN_SINGLE_APMDU);
133 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RX_PKT_LIMIT);
134 rtw_write8(rtwdev, REG_MAX_AGGR_NUM, WLAN_MAX_AGG_NR);
135 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME, WLAN_AMPDU_MAX_TIME);
136 rtw_write8(rtwdev, REG_LEDCFG2, WLAN_ANT_SEL);
137
138 rtw_write32(rtwdev, REG_LTR_IDLE_LATENCY, WLAN_LTR_IDLE_LAT);
139 rtw_write32(rtwdev, REG_LTR_ACTIVE_LATENCY, WLAN_LTR_ACT_LAT);
140 rtw_write32(rtwdev, REG_LTR_CTRL_BASIC, WLAN_LTR_CTRL1);
141 rtw_write32(rtwdev, REG_LTR_CTRL_BASIC + 4, WLAN_LTR_CTRL2);
142
143 rtw_phy_init(rtwdev);
144 rtwdev->dm_info.cck_pd_default = rtw_read8(rtwdev, REG_CSRATIO) & 0x1f;
145
146 rtw_write16_set(rtwdev, REG_TXDMA_OFFSET_CHK, BIT_DROP_DATA_EN);
147
148 rtw8723x_lck(rtwdev);
149
150 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x50);
151 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x20);
152
153 rtw8723d_pwrtrack_init(rtwdev);
154 }
155
query_phy_status_page0(struct rtw_dev * rtwdev,u8 * phy_status,struct rtw_rx_pkt_stat * pkt_stat)156 static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status,
157 struct rtw_rx_pkt_stat *pkt_stat)
158 {
159 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
160 s8 min_rx_power = -120;
161 u8 pwdb = GET_PHY_STAT_P0_PWDB(phy_status);
162
163 pkt_stat->rx_power[RF_PATH_A] = pwdb - 97;
164 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1);
165 pkt_stat->bw = RTW_CHANNEL_WIDTH_20;
166 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A],
167 min_rx_power);
168 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi;
169 }
170
query_phy_status_page1(struct rtw_dev * rtwdev,u8 * phy_status,struct rtw_rx_pkt_stat * pkt_stat)171 static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status,
172 struct rtw_rx_pkt_stat *pkt_stat)
173 {
174 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
175 u8 rxsc, bw;
176 s8 min_rx_power = -120;
177 s8 rx_evm;
178
179 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0)
180 rxsc = GET_PHY_STAT_P1_L_RXSC(phy_status);
181 else
182 rxsc = GET_PHY_STAT_P1_HT_RXSC(phy_status);
183
184 if (GET_PHY_STAT_P1_RF_MODE(phy_status) == 0)
185 bw = RTW_CHANNEL_WIDTH_20;
186 else if ((rxsc == 1) || (rxsc == 2))
187 bw = RTW_CHANNEL_WIDTH_20;
188 else
189 bw = RTW_CHANNEL_WIDTH_40;
190
191 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110;
192 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1);
193 pkt_stat->bw = bw;
194 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A],
195 min_rx_power);
196 pkt_stat->rx_evm[RF_PATH_A] = GET_PHY_STAT_P1_RXEVM_A(phy_status);
197 pkt_stat->rx_snr[RF_PATH_A] = GET_PHY_STAT_P1_RXSNR_A(phy_status);
198 pkt_stat->cfo_tail[RF_PATH_A] = GET_PHY_STAT_P1_CFO_TAIL_A(phy_status);
199
200 dm_info->curr_rx_rate = pkt_stat->rate;
201 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi;
202 dm_info->rx_snr[RF_PATH_A] = pkt_stat->rx_snr[RF_PATH_A] >> 1;
203 dm_info->cfo_tail[RF_PATH_A] = (pkt_stat->cfo_tail[RF_PATH_A] * 5) >> 1;
204
205 rx_evm = clamp_t(s8, -pkt_stat->rx_evm[RF_PATH_A] >> 1, 0, 64);
206 rx_evm &= 0x3F; /* 64->0: second path of 1SS rate is 64 */
207 dm_info->rx_evm_dbm[RF_PATH_A] = rx_evm;
208 }
209
query_phy_status(struct rtw_dev * rtwdev,u8 * phy_status,struct rtw_rx_pkt_stat * pkt_stat)210 static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status,
211 struct rtw_rx_pkt_stat *pkt_stat)
212 {
213 u8 page;
214
215 page = *phy_status & 0xf;
216
217 switch (page) {
218 case 0:
219 query_phy_status_page0(rtwdev, phy_status, pkt_stat);
220 break;
221 case 1:
222 query_phy_status_page1(rtwdev, phy_status, pkt_stat);
223 break;
224 default:
225 rtw_warn(rtwdev, "unused phy status page (%d)\n", page);
226 return;
227 }
228 }
229
rtw8723d_query_rx_desc(struct rtw_dev * rtwdev,u8 * rx_desc,struct rtw_rx_pkt_stat * pkt_stat,struct ieee80211_rx_status * rx_status)230 static void rtw8723d_query_rx_desc(struct rtw_dev *rtwdev, u8 *rx_desc,
231 struct rtw_rx_pkt_stat *pkt_stat,
232 struct ieee80211_rx_status *rx_status)
233 {
234 struct ieee80211_hdr *hdr;
235 u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz;
236 u8 *phy_status = NULL;
237
238 memset(pkt_stat, 0, sizeof(*pkt_stat));
239
240 pkt_stat->phy_status = GET_RX_DESC_PHYST(rx_desc);
241 pkt_stat->icv_err = GET_RX_DESC_ICV_ERR(rx_desc);
242 pkt_stat->crc_err = GET_RX_DESC_CRC32(rx_desc);
243 pkt_stat->decrypted = !GET_RX_DESC_SWDEC(rx_desc) &&
244 GET_RX_DESC_ENC_TYPE(rx_desc) != RX_DESC_ENC_NONE;
245 pkt_stat->is_c2h = GET_RX_DESC_C2H(rx_desc);
246 pkt_stat->pkt_len = GET_RX_DESC_PKT_LEN(rx_desc);
247 pkt_stat->drv_info_sz = GET_RX_DESC_DRV_INFO_SIZE(rx_desc);
248 pkt_stat->shift = GET_RX_DESC_SHIFT(rx_desc);
249 pkt_stat->rate = GET_RX_DESC_RX_RATE(rx_desc);
250 pkt_stat->cam_id = GET_RX_DESC_MACID(rx_desc);
251 pkt_stat->ppdu_cnt = 0;
252 pkt_stat->tsf_low = GET_RX_DESC_TSFL(rx_desc);
253
254 /* drv_info_sz is in unit of 8-bytes */
255 pkt_stat->drv_info_sz *= 8;
256
257 /* c2h cmd pkt's rx/phy status is not interested */
258 if (pkt_stat->is_c2h)
259 return;
260
261 hdr = (struct ieee80211_hdr *)(rx_desc + desc_sz + pkt_stat->shift +
262 pkt_stat->drv_info_sz);
263 if (pkt_stat->phy_status) {
264 phy_status = rx_desc + desc_sz + pkt_stat->shift;
265 query_phy_status(rtwdev, phy_status, pkt_stat);
266 }
267
268 rtw_rx_fill_rx_status(rtwdev, pkt_stat, hdr, rx_status, phy_status);
269 }
270
rtw8723d_check_spur_ov_thres(struct rtw_dev * rtwdev,u8 channel,u32 thres)271 static bool rtw8723d_check_spur_ov_thres(struct rtw_dev *rtwdev,
272 u8 channel, u32 thres)
273 {
274 u32 freq;
275 bool ret = false;
276
277 if (channel == 13)
278 freq = FREQ_CH13;
279 else if (channel == 14)
280 freq = FREQ_CH14;
281 else
282 return false;
283
284 rtw_write32(rtwdev, REG_ANALOG_P4, DIS_3WIRE);
285 rtw_write32(rtwdev, REG_PSDFN, freq);
286 rtw_write32(rtwdev, REG_PSDFN, START_PSD | freq);
287
288 msleep(30);
289 if (rtw_read32(rtwdev, REG_PSDRPT) >= thres)
290 ret = true;
291
292 rtw_write32(rtwdev, REG_PSDFN, freq);
293 rtw_write32(rtwdev, REG_ANALOG_P4, EN_3WIRE);
294
295 return ret;
296 }
297
rtw8723d_cfg_notch(struct rtw_dev * rtwdev,u8 channel,bool notch)298 static void rtw8723d_cfg_notch(struct rtw_dev *rtwdev, u8 channel, bool notch)
299 {
300 if (!notch) {
301 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x1f);
302 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0);
303 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000);
304 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000);
305 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000);
306 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000);
307 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0);
308 return;
309 }
310
311 switch (channel) {
312 case 13:
313 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0xb);
314 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1);
315 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x04000000);
316 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000);
317 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000);
318 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000);
319 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1);
320 break;
321 case 14:
322 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x5);
323 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1);
324 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000);
325 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000);
326 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000);
327 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00080000);
328 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1);
329 break;
330 default:
331 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0);
332 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0);
333 break;
334 }
335 }
336
rtw8723d_spur_cal(struct rtw_dev * rtwdev,u8 channel)337 static void rtw8723d_spur_cal(struct rtw_dev *rtwdev, u8 channel)
338 {
339 bool notch;
340
341 if (channel < 13) {
342 rtw8723d_cfg_notch(rtwdev, channel, false);
343 return;
344 }
345
346 notch = rtw8723d_check_spur_ov_thres(rtwdev, channel, SPUR_THRES);
347 rtw8723d_cfg_notch(rtwdev, channel, notch);
348 }
349
rtw8723d_set_channel_rf(struct rtw_dev * rtwdev,u8 channel,u8 bw)350 static void rtw8723d_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw)
351 {
352 u32 rf_cfgch_a, rf_cfgch_b;
353
354 rf_cfgch_a = rtw_read_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK);
355 rf_cfgch_b = rtw_read_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK);
356
357 rf_cfgch_a &= ~RFCFGCH_CHANNEL_MASK;
358 rf_cfgch_b &= ~RFCFGCH_CHANNEL_MASK;
359 rf_cfgch_a |= (channel & RFCFGCH_CHANNEL_MASK);
360 rf_cfgch_b |= (channel & RFCFGCH_CHANNEL_MASK);
361
362 rf_cfgch_a &= ~RFCFGCH_BW_MASK;
363 switch (bw) {
364 case RTW_CHANNEL_WIDTH_20:
365 rf_cfgch_a |= RFCFGCH_BW_20M;
366 break;
367 case RTW_CHANNEL_WIDTH_40:
368 rf_cfgch_a |= RFCFGCH_BW_40M;
369 break;
370 default:
371 break;
372 }
373
374 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, rf_cfgch_a);
375 rtw_write_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK, rf_cfgch_b);
376
377 rtw8723d_spur_cal(rtwdev, channel);
378 }
379
380 static const struct rtw_backup_info cck_dfir_cfg[][CCK_DFIR_NR] = {
381 [0] = {
382 { .len = 4, .reg = 0xA24, .val = 0x64B80C1C },
383 { .len = 4, .reg = 0xA28, .val = 0x00008810 },
384 { .len = 4, .reg = 0xAAC, .val = 0x01235667 },
385 },
386 [1] = {
387 { .len = 4, .reg = 0xA24, .val = 0x0000B81C },
388 { .len = 4, .reg = 0xA28, .val = 0x00000000 },
389 { .len = 4, .reg = 0xAAC, .val = 0x00003667 },
390 },
391 };
392
rtw8723d_set_channel_bb(struct rtw_dev * rtwdev,u8 channel,u8 bw,u8 primary_ch_idx)393 static void rtw8723d_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw,
394 u8 primary_ch_idx)
395 {
396 const struct rtw_backup_info *cck_dfir;
397 int i;
398
399 cck_dfir = channel <= 13 ? cck_dfir_cfg[0] : cck_dfir_cfg[1];
400
401 for (i = 0; i < CCK_DFIR_NR; i++, cck_dfir++)
402 rtw_write32(rtwdev, cck_dfir->reg, cck_dfir->val);
403
404 switch (bw) {
405 case RTW_CHANNEL_WIDTH_20:
406 rtw_write32_mask(rtwdev, REG_FPGA0_RFMOD, BIT_MASK_RFMOD, 0x0);
407 rtw_write32_mask(rtwdev, REG_FPGA1_RFMOD, BIT_MASK_RFMOD, 0x0);
408 rtw_write32_mask(rtwdev, REG_BBRX_DFIR, BIT_RXBB_DFIR_EN, 1);
409 rtw_write32_mask(rtwdev, REG_BBRX_DFIR, BIT_MASK_RXBB_DFIR, 0xa);
410 break;
411 case RTW_CHANNEL_WIDTH_40:
412 rtw_write32_mask(rtwdev, REG_FPGA0_RFMOD, BIT_MASK_RFMOD, 0x1);
413 rtw_write32_mask(rtwdev, REG_FPGA1_RFMOD, BIT_MASK_RFMOD, 0x1);
414 rtw_write32_mask(rtwdev, REG_BBRX_DFIR, BIT_RXBB_DFIR_EN, 0);
415 rtw_write32_mask(rtwdev, REG_CCK0_SYS, BIT_CCK_SIDE_BAND,
416 (primary_ch_idx == RTW_SC_20_UPPER ? 1 : 0));
417 break;
418 default:
419 break;
420 }
421 }
422
rtw8723d_set_channel(struct rtw_dev * rtwdev,u8 channel,u8 bw,u8 primary_chan_idx)423 static void rtw8723d_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw,
424 u8 primary_chan_idx)
425 {
426 rtw8723d_set_channel_rf(rtwdev, channel, bw);
427 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx);
428 rtw8723d_set_channel_bb(rtwdev, channel, bw, primary_chan_idx);
429 }
430
rtw8723d_shutdown(struct rtw_dev * rtwdev)431 static void rtw8723d_shutdown(struct rtw_dev *rtwdev)
432 {
433 rtw_write16_set(rtwdev, REG_HCI_OPT_CTRL, BIT_USB_SUS_DIS);
434 }
435
436 struct rtw_8723d_iqk_cfg {
437 const char *name;
438 u32 val_bb_sel_btg;
439 u32 reg_lutwe;
440 u32 val_txiqk_pi;
441 u32 reg_padlut;
442 u32 reg_gaintx;
443 u32 reg_bspad;
444 u32 val_wlint;
445 u32 val_wlsel;
446 u32 val_iqkpts;
447 };
448
449 static const struct rtw_8723d_iqk_cfg iqk_tx_cfg[PATH_NR] = {
450 [PATH_S1] = {
451 .name = "S1",
452 .val_bb_sel_btg = 0x99000000,
453 .reg_lutwe = RF_LUTWE,
454 .val_txiqk_pi = 0x8214019f,
455 .reg_padlut = RF_LUTDBG,
456 .reg_gaintx = RF_GAINTX,
457 .reg_bspad = RF_BSPAD,
458 .val_wlint = 0xe0d,
459 .val_wlsel = 0x60d,
460 .val_iqkpts = 0xfa000000,
461 },
462 [PATH_S0] = {
463 .name = "S0",
464 .val_bb_sel_btg = 0x99000280,
465 .reg_lutwe = RF_LUTWE2,
466 .val_txiqk_pi = 0x8214018a,
467 .reg_padlut = RF_TXADBG,
468 .reg_gaintx = RF_TRXIQ,
469 .reg_bspad = RF_TXATANK,
470 .val_wlint = 0xe6d,
471 .val_wlsel = 0x66d,
472 .val_iqkpts = 0xf9000000,
473 },
474 };
475
rtw8723d_iqk_check_tx_failed(struct rtw_dev * rtwdev,const struct rtw_8723d_iqk_cfg * iqk_cfg)476 static u8 rtw8723d_iqk_check_tx_failed(struct rtw_dev *rtwdev,
477 const struct rtw_8723d_iqk_cfg *iqk_cfg)
478 {
479 s32 tx_x, tx_y;
480 u32 tx_fail;
481
482 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xeac = 0x%x\n",
483 rtw_read32(rtwdev, REG_IQK_RES_RY));
484 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xe94 = 0x%x, 0xe9c = 0x%x\n",
485 rtw_read32(rtwdev, REG_IQK_RES_TX),
486 rtw_read32(rtwdev, REG_IQK_RES_TY));
487 rtw_dbg(rtwdev, RTW_DBG_RFK,
488 "[IQK] 0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n",
489 rtw_read32(rtwdev, 0xe90),
490 rtw_read32(rtwdev, 0xe98));
491
492 tx_fail = rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_IQK_TX_FAIL);
493 tx_x = rtw_read32_mask(rtwdev, REG_IQK_RES_TX, BIT_MASK_RES_TX);
494 tx_y = rtw_read32_mask(rtwdev, REG_IQK_RES_TY, BIT_MASK_RES_TY);
495
496 if (!tx_fail && tx_x != IQK_TX_X_ERR && tx_y != IQK_TX_Y_ERR)
497 return IQK_TX_OK;
498
499 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] %s TXIQK is failed\n",
500 iqk_cfg->name);
501
502 return 0;
503 }
504
rtw8723d_iqk_check_rx_failed(struct rtw_dev * rtwdev,const struct rtw_8723d_iqk_cfg * iqk_cfg)505 static u8 rtw8723d_iqk_check_rx_failed(struct rtw_dev *rtwdev,
506 const struct rtw_8723d_iqk_cfg *iqk_cfg)
507 {
508 s32 rx_x, rx_y;
509 u32 rx_fail;
510
511 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xea4 = 0x%x, 0xeac = 0x%x\n",
512 rtw_read32(rtwdev, REG_IQK_RES_RX),
513 rtw_read32(rtwdev, REG_IQK_RES_RY));
514
515 rtw_dbg(rtwdev, RTW_DBG_RFK,
516 "[IQK] 0xea0(before IQK)= 0x%x, 0xea8(afer IQK) = 0x%x\n",
517 rtw_read32(rtwdev, 0xea0),
518 rtw_read32(rtwdev, 0xea8));
519
520 rx_fail = rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_IQK_RX_FAIL);
521 rx_x = rtw_read32_mask(rtwdev, REG_IQK_RES_RX, BIT_MASK_RES_RX);
522 rx_y = rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_MASK_RES_RY);
523 rx_y = abs(iqkxy_to_s32(rx_y));
524
525 if (!rx_fail && rx_x < IQK_RX_X_UPPER && rx_x > IQK_RX_X_LOWER &&
526 rx_y < IQK_RX_Y_LMT)
527 return IQK_RX_OK;
528
529 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] %s RXIQK STEP2 is failed\n",
530 iqk_cfg->name);
531
532 return 0;
533 }
534
535 #define IQK_LTE_WRITE_VAL_8723D 0x0000ff00
536
rtw8723d_iqk_one_shot(struct rtw_dev * rtwdev,bool tx,const struct rtw_8723d_iqk_cfg * iqk_cfg)537 static void rtw8723d_iqk_one_shot(struct rtw_dev *rtwdev, bool tx,
538 const struct rtw_8723d_iqk_cfg *iqk_cfg)
539 {
540 u32 pts = (tx ? iqk_cfg->val_iqkpts : 0xf9000000);
541
542 /* enter IQK mode */
543 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, EN_IQK);
544 rtw8723x_iqk_config_lte_path_gnt(rtwdev, IQK_LTE_WRITE_VAL_8723D);
545
546 rtw_write32(rtwdev, REG_LTECOEX_CTRL, 0x800f0054);
547 mdelay(1);
548 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] GNT_BT @%s %sIQK1 = 0x%x\n",
549 iqk_cfg->name, tx ? "TX" : "RX",
550 rtw_read32(rtwdev, REG_LTECOEX_READ_DATA));
551 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x948 @%s %sIQK1 = 0x%x\n",
552 iqk_cfg->name, tx ? "TX" : "RX",
553 rtw_read32(rtwdev, REG_BB_SEL_BTG));
554
555 /* One shot, LOK & IQK */
556 rtw_write32(rtwdev, REG_IQK_AGC_PTS_11N, pts);
557 rtw_write32(rtwdev, REG_IQK_AGC_PTS_11N, 0xf8000000);
558
559 if (!check_hw_ready(rtwdev, REG_IQK_RES_RY, BIT_IQK_DONE, 1))
560 rtw_warn(rtwdev, "%s %s IQK isn't done\n", iqk_cfg->name,
561 tx ? "TX" : "RX");
562 }
563
rtw8723d_iqk_txrx_path_post(struct rtw_dev * rtwdev,const struct rtw_8723d_iqk_cfg * iqk_cfg,const struct rtw8723x_iqk_backup_regs * backup)564 static void rtw8723d_iqk_txrx_path_post(struct rtw_dev *rtwdev,
565 const struct rtw_8723d_iqk_cfg *iqk_cfg,
566 const struct rtw8723x_iqk_backup_regs *backup)
567 {
568 rtw8723x_iqk_restore_lte_path_gnt(rtwdev, backup);
569 rtw_write32(rtwdev, REG_BB_SEL_BTG, backup->bb_sel_btg);
570
571 /* leave IQK mode */
572 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK);
573 mdelay(1);
574 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_padlut, 0x800, 0x0);
575 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLINT, BIT(0), 0x0);
576 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLSEL, BIT(0), 0x0);
577 }
578
rtw8723d_iqk_tx_path(struct rtw_dev * rtwdev,const struct rtw_8723d_iqk_cfg * iqk_cfg,const struct rtw8723x_iqk_backup_regs * backup)579 static u8 rtw8723d_iqk_tx_path(struct rtw_dev *rtwdev,
580 const struct rtw_8723d_iqk_cfg *iqk_cfg,
581 const struct rtw8723x_iqk_backup_regs *backup)
582 {
583 u8 status;
584
585 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path %s TXIQK!!\n", iqk_cfg->name);
586 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x67 @%s TXIQK = 0x%x\n",
587 iqk_cfg->name,
588 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3));
589
590 rtw_write32(rtwdev, REG_BB_SEL_BTG, iqk_cfg->val_bb_sel_btg);
591 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK);
592 mdelay(1);
593 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x80000);
594 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00004);
595 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD1, RFREG_MASK, 0x0005d);
596 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0xBFFE0);
597 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x00000);
598
599 /* IQK setting */
600 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x08008c0c);
601 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x38008c1c);
602 rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, iqk_cfg->val_txiqk_pi);
603 rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28160200);
604 rtw_write32(rtwdev, REG_TXIQK_11N, 0x01007c00);
605 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800);
606
607 /* LOK setting */
608 rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x00462911);
609
610 /* PA, PAD setting */
611 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_padlut, 0x800, 0x1);
612 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_gaintx, 0x600, 0x0);
613 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_gaintx, 0x1E0, 0x3);
614 rtw_write_rf(rtwdev, RF_PATH_A, RF_RXIQGEN, 0x1F, 0xf);
615
616 /* LOK setting for 8723D */
617 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, 0x10, 0x1);
618 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_bspad, 0x1, 0x1);
619
620 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLINT, RFREG_MASK, iqk_cfg->val_wlint);
621 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLSEL, RFREG_MASK, iqk_cfg->val_wlsel);
622
623 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x1 @%s TXIQK = 0x%x\n",
624 iqk_cfg->name,
625 rtw_read_rf(rtwdev, RF_PATH_A, RF_WLINT, RFREG_MASK));
626 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x2 @%s TXIQK = 0x%x\n",
627 iqk_cfg->name,
628 rtw_read_rf(rtwdev, RF_PATH_A, RF_WLSEL, RFREG_MASK));
629
630 rtw8723d_iqk_one_shot(rtwdev, true, iqk_cfg);
631 status = rtw8723d_iqk_check_tx_failed(rtwdev, iqk_cfg);
632
633 rtw8723d_iqk_txrx_path_post(rtwdev, iqk_cfg, backup);
634
635 return status;
636 }
637
rtw8723d_iqk_rx_path(struct rtw_dev * rtwdev,const struct rtw_8723d_iqk_cfg * iqk_cfg,const struct rtw8723x_iqk_backup_regs * backup)638 static u8 rtw8723d_iqk_rx_path(struct rtw_dev *rtwdev,
639 const struct rtw_8723d_iqk_cfg *iqk_cfg,
640 const struct rtw8723x_iqk_backup_regs *backup)
641 {
642 u32 tx_x, tx_y;
643 u8 status;
644
645 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path %s RXIQK Step1!!\n",
646 iqk_cfg->name);
647 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x67 @%s RXIQK1 = 0x%x\n",
648 iqk_cfg->name,
649 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3));
650 rtw_write32(rtwdev, REG_BB_SEL_BTG, iqk_cfg->val_bb_sel_btg);
651
652 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK);
653
654 /* IQK setting */
655 rtw_write32(rtwdev, REG_TXIQK_11N, 0x01007c00);
656 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800);
657
658 /* path IQK setting */
659 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x18008c1c);
660 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x38008c1c);
661 rtw_write32(rtwdev, REG_TX_IQK_TONE_B, 0x38008c1c);
662 rtw_write32(rtwdev, REG_RX_IQK_TONE_B, 0x38008c1c);
663 rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, 0x82160000);
664 rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28160000);
665
666 /* LOK setting */
667 rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x0046a911);
668
669 /* RXIQK mode */
670 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x80000);
671 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00006);
672 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD1, RFREG_MASK, 0x0005f);
673 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0xa7ffb);
674 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x00000);
675
676 /* PA/PAD=0 */
677 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_padlut, 0x800, 0x1);
678 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_gaintx, 0x600, 0x0);
679 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLINT, RFREG_MASK, iqk_cfg->val_wlint);
680 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLSEL, RFREG_MASK, iqk_cfg->val_wlsel);
681
682 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x1@ path %s RXIQK1 = 0x%x\n",
683 iqk_cfg->name,
684 rtw_read_rf(rtwdev, RF_PATH_A, RF_WLINT, RFREG_MASK));
685 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x2@ path %s RXIQK1 = 0x%x\n",
686 iqk_cfg->name,
687 rtw_read_rf(rtwdev, RF_PATH_A, RF_WLSEL, RFREG_MASK));
688
689 rtw8723d_iqk_one_shot(rtwdev, false, iqk_cfg);
690 status = rtw8723d_iqk_check_tx_failed(rtwdev, iqk_cfg);
691
692 if (!status)
693 goto restore;
694
695 /* second round */
696 tx_x = rtw_read32_mask(rtwdev, REG_IQK_RES_TX, BIT_MASK_RES_TX);
697 tx_y = rtw_read32_mask(rtwdev, REG_IQK_RES_TY, BIT_MASK_RES_TY);
698
699 rtw_write32(rtwdev, REG_TXIQK_11N, BIT_SET_TXIQK_11N(tx_x, tx_y));
700 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xe40 = 0x%x u4tmp = 0x%x\n",
701 rtw_read32(rtwdev, REG_TXIQK_11N),
702 BIT_SET_TXIQK_11N(tx_x, tx_y));
703
704 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path %s RXIQK STEP2!!\n",
705 iqk_cfg->name);
706 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x67 @%s RXIQK2 = 0x%x\n",
707 iqk_cfg->name,
708 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3));
709
710 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800);
711 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x38008c1c);
712 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x18008c1c);
713 rtw_write32(rtwdev, REG_TX_IQK_TONE_B, 0x38008c1c);
714 rtw_write32(rtwdev, REG_RX_IQK_TONE_B, 0x38008c1c);
715 rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, 0x82170000);
716 rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28171400);
717
718 /* LOK setting */
719 rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x0046a8d1);
720
721 /* RXIQK mode */
722 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK);
723 mdelay(1);
724 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, 0x80000, 0x1);
725 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00007);
726 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD1, RFREG_MASK, 0x0005f);
727 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0xb3fdb);
728 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x00000);
729
730 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x1 @%s RXIQK2 = 0x%x\n",
731 iqk_cfg->name,
732 rtw_read_rf(rtwdev, RF_PATH_A, RF_WLINT, RFREG_MASK));
733 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x2 @%s RXIQK2 = 0x%x\n",
734 iqk_cfg->name,
735 rtw_read_rf(rtwdev, RF_PATH_A, RF_WLSEL, RFREG_MASK));
736
737 rtw8723d_iqk_one_shot(rtwdev, false, iqk_cfg);
738 status |= rtw8723d_iqk_check_rx_failed(rtwdev, iqk_cfg);
739
740 restore:
741 rtw8723d_iqk_txrx_path_post(rtwdev, iqk_cfg, backup);
742
743 return status;
744 }
745
746 static
rtw8723d_iqk_fill_s1_matrix(struct rtw_dev * rtwdev,const s32 result[])747 void rtw8723d_iqk_fill_s1_matrix(struct rtw_dev *rtwdev, const s32 result[])
748 {
749 s32 oldval_1;
750 s32 x, y;
751 s32 tx1_a, tx1_a_ext;
752 s32 tx1_c, tx1_c_ext;
753
754 if (result[IQK_S1_TX_X] == 0)
755 return;
756
757 oldval_1 = rtw_read32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE,
758 BIT_MASK_TXIQ_ELM_D);
759
760 x = iqkxy_to_s32(result[IQK_S1_TX_X]);
761 tx1_a = iqk_mult(x, oldval_1, &tx1_a_ext);
762 rtw_write32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE,
763 BIT_MASK_TXIQ_ELM_A, tx1_a);
764 rtw_write32_mask(rtwdev, REG_OFDM_0_ECCA_THRESHOLD,
765 BIT_MASK_OFDM0_EXT_A, tx1_a_ext);
766
767 y = iqkxy_to_s32(result[IQK_S1_TX_Y]);
768 tx1_c = iqk_mult(y, oldval_1, &tx1_c_ext);
769 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N, MASKH4BITS,
770 BIT_SET_TXIQ_ELM_C1(tx1_c));
771 rtw_write32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE,
772 BIT_MASK_TXIQ_ELM_C, BIT_SET_TXIQ_ELM_C2(tx1_c));
773 rtw_write32_mask(rtwdev, REG_OFDM_0_ECCA_THRESHOLD,
774 BIT_MASK_OFDM0_EXT_C, tx1_c_ext);
775
776 rtw_dbg(rtwdev, RTW_DBG_RFK,
777 "[IQK] X = 0x%x, TX1_A = 0x%x, oldval_1 0x%x\n",
778 x, tx1_a, oldval_1);
779 rtw_dbg(rtwdev, RTW_DBG_RFK,
780 "[IQK] Y = 0x%x, TX1_C = 0x%x\n", y, tx1_c);
781
782 if (result[IQK_S1_RX_X] == 0)
783 return;
784
785 rtw_write32_mask(rtwdev, REG_A_RXIQI, BIT_MASK_RXIQ_S1_X,
786 result[IQK_S1_RX_X]);
787 rtw_write32_mask(rtwdev, REG_A_RXIQI, BIT_MASK_RXIQ_S1_Y1,
788 BIT_SET_RXIQ_S1_Y1(result[IQK_S1_RX_Y]));
789 rtw_write32_mask(rtwdev, REG_RXIQK_MATRIX_LSB_11N, BIT_MASK_RXIQ_S1_Y2,
790 BIT_SET_RXIQ_S1_Y2(result[IQK_S1_RX_Y]));
791 }
792
793 static
rtw8723d_iqk_fill_s0_matrix(struct rtw_dev * rtwdev,const s32 result[])794 void rtw8723d_iqk_fill_s0_matrix(struct rtw_dev *rtwdev, const s32 result[])
795 {
796 s32 oldval_0;
797 s32 x, y;
798 s32 tx0_a, tx0_a_ext;
799 s32 tx0_c, tx0_c_ext;
800
801 if (result[IQK_S0_TX_X] == 0)
802 return;
803
804 oldval_0 = rtw_read32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_D_S0);
805
806 x = iqkxy_to_s32(result[IQK_S0_TX_X]);
807 tx0_a = iqk_mult(x, oldval_0, &tx0_a_ext);
808
809 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_S0, tx0_a);
810 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_EXT_S0, tx0_a_ext);
811
812 y = iqkxy_to_s32(result[IQK_S0_TX_Y]);
813 tx0_c = iqk_mult(y, oldval_0, &tx0_c_ext);
814
815 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_S0, tx0_c);
816 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_EXT_S0, tx0_c_ext);
817
818 if (result[IQK_S0_RX_X] == 0)
819 return;
820
821 rtw_write32_mask(rtwdev, REG_RXIQ_AB_S0, BIT_MASK_RXIQ_X_S0,
822 result[IQK_S0_RX_X]);
823 rtw_write32_mask(rtwdev, REG_RXIQ_AB_S0, BIT_MASK_RXIQ_Y_S0,
824 result[IQK_S0_RX_Y]);
825 }
826
rtw8723d_iqk_config_mac(struct rtw_dev * rtwdev)827 static void rtw8723d_iqk_config_mac(struct rtw_dev *rtwdev)
828 {
829 rtw_write8(rtwdev, REG_TXPAUSE, 0xff);
830 }
831
832 static
rtw8723d_iqk_rf_standby(struct rtw_dev * rtwdev,enum rtw_rf_path path)833 void rtw8723d_iqk_rf_standby(struct rtw_dev *rtwdev, enum rtw_rf_path path)
834 {
835 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path-%s standby mode!\n",
836 path == RF_PATH_A ? "S1" : "S0");
837
838 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK);
839 mdelay(1);
840 rtw_write_rf(rtwdev, path, RF_MODE, RFREG_MASK, 0x10000);
841 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, EN_IQK);
842 }
843
844 #define ADDA_ON_VAL_8723D 0x03c00016
845
846 static
rtw8723d_iqk_precfg_path(struct rtw_dev * rtwdev,enum rtw8723x_path path)847 void rtw8723d_iqk_precfg_path(struct rtw_dev *rtwdev, enum rtw8723x_path path)
848 {
849 if (path == PATH_S0) {
850 rtw8723d_iqk_rf_standby(rtwdev, RF_PATH_A);
851 rtw8723x_iqk_path_adda_on(rtwdev, ADDA_ON_VAL_8723D);
852 }
853
854 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, EN_IQK);
855 rtw_write32(rtwdev, REG_TXIQK_11N, 0x01007c00);
856 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800);
857
858 if (path == PATH_S1) {
859 rtw8723d_iqk_rf_standby(rtwdev, RF_PATH_B);
860 rtw8723x_iqk_path_adda_on(rtwdev, ADDA_ON_VAL_8723D);
861 }
862 }
863
864 static
rtw8723d_iqk_one_round(struct rtw_dev * rtwdev,s32 result[][IQK_NR],u8 t,const struct rtw8723x_iqk_backup_regs * backup)865 void rtw8723d_iqk_one_round(struct rtw_dev *rtwdev, s32 result[][IQK_NR], u8 t,
866 const struct rtw8723x_iqk_backup_regs *backup)
867 {
868 u32 i;
869 u8 s1_ok, s0_ok;
870
871 rtw_dbg(rtwdev, RTW_DBG_RFK,
872 "[IQK] IQ Calibration for 1T1R_S0/S1 for %d times\n", t);
873
874 rtw8723x_iqk_path_adda_on(rtwdev, ADDA_ON_VAL_8723D);
875 rtw8723d_iqk_config_mac(rtwdev);
876 rtw_write32_mask(rtwdev, REG_CCK_ANT_SEL_11N, 0x0f000000, 0xf);
877 rtw_write32(rtwdev, REG_BB_RX_PATH_11N, 0x03a05611);
878 rtw_write32(rtwdev, REG_TRMUX_11N, 0x000800e4);
879 rtw_write32(rtwdev, REG_BB_PWR_SAV1_11N, 0x25204200);
880 rtw8723d_iqk_precfg_path(rtwdev, PATH_S1);
881
882 for (i = 0; i < PATH_IQK_RETRY; i++) {
883 s1_ok = rtw8723d_iqk_tx_path(rtwdev, &iqk_tx_cfg[PATH_S1], backup);
884 if (s1_ok == IQK_TX_OK) {
885 rtw_dbg(rtwdev, RTW_DBG_RFK,
886 "[IQK] path S1 Tx IQK Success!!\n");
887 result[t][IQK_S1_TX_X] =
888 rtw_read32_mask(rtwdev, REG_IQK_RES_TX, BIT_MASK_RES_TX);
889 result[t][IQK_S1_TX_Y] =
890 rtw_read32_mask(rtwdev, REG_IQK_RES_TY, BIT_MASK_RES_TY);
891 break;
892 }
893
894 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path S1 Tx IQK Fail!!\n");
895 result[t][IQK_S1_TX_X] = 0x100;
896 result[t][IQK_S1_TX_Y] = 0x0;
897 }
898
899 for (i = 0; i < PATH_IQK_RETRY; i++) {
900 s1_ok = rtw8723d_iqk_rx_path(rtwdev, &iqk_tx_cfg[PATH_S1], backup);
901 if (s1_ok == (IQK_TX_OK | IQK_RX_OK)) {
902 rtw_dbg(rtwdev, RTW_DBG_RFK,
903 "[IQK] path S1 Rx IQK Success!!\n");
904 result[t][IQK_S1_RX_X] =
905 rtw_read32_mask(rtwdev, REG_IQK_RES_RX, BIT_MASK_RES_RX);
906 result[t][IQK_S1_RX_Y] =
907 rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_MASK_RES_RY);
908 break;
909 }
910
911 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path S1 Rx IQK Fail!!\n");
912 result[t][IQK_S1_RX_X] = 0x100;
913 result[t][IQK_S1_RX_Y] = 0x0;
914 }
915
916 if (s1_ok == 0x0)
917 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path S1 IQK is failed!!\n");
918
919 rtw8723d_iqk_precfg_path(rtwdev, PATH_S0);
920
921 for (i = 0; i < PATH_IQK_RETRY; i++) {
922 s0_ok = rtw8723d_iqk_tx_path(rtwdev, &iqk_tx_cfg[PATH_S0], backup);
923 if (s0_ok == IQK_TX_OK) {
924 rtw_dbg(rtwdev, RTW_DBG_RFK,
925 "[IQK] path S0 Tx IQK Success!!\n");
926 result[t][IQK_S0_TX_X] =
927 rtw_read32_mask(rtwdev, REG_IQK_RES_TX, BIT_MASK_RES_TX);
928 result[t][IQK_S0_TX_Y] =
929 rtw_read32_mask(rtwdev, REG_IQK_RES_TY, BIT_MASK_RES_TY);
930 break;
931 }
932
933 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path S0 Tx IQK Fail!!\n");
934 result[t][IQK_S0_TX_X] = 0x100;
935 result[t][IQK_S0_TX_Y] = 0x0;
936 }
937
938 for (i = 0; i < PATH_IQK_RETRY; i++) {
939 s0_ok = rtw8723d_iqk_rx_path(rtwdev, &iqk_tx_cfg[PATH_S0], backup);
940 if (s0_ok == (IQK_TX_OK | IQK_RX_OK)) {
941 rtw_dbg(rtwdev, RTW_DBG_RFK,
942 "[IQK] path S0 Rx IQK Success!!\n");
943
944 result[t][IQK_S0_RX_X] =
945 rtw_read32_mask(rtwdev, REG_IQK_RES_RX, BIT_MASK_RES_RX);
946 result[t][IQK_S0_RX_Y] =
947 rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_MASK_RES_RY);
948 break;
949 }
950
951 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path S0 Rx IQK Fail!!\n");
952 result[t][IQK_S0_RX_X] = 0x100;
953 result[t][IQK_S0_RX_Y] = 0x0;
954 }
955
956 if (s0_ok == 0x0)
957 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path S0 IQK is failed!!\n");
958
959 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK);
960 mdelay(1);
961
962 rtw_dbg(rtwdev, RTW_DBG_RFK,
963 "[IQK] back to BB mode, load original value!\n");
964 }
965
rtw8723d_phy_calibration(struct rtw_dev * rtwdev)966 static void rtw8723d_phy_calibration(struct rtw_dev *rtwdev)
967 {
968 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
969 s32 result[IQK_ROUND_SIZE][IQK_NR];
970 struct rtw8723x_iqk_backup_regs backup;
971 u8 i, j;
972 u8 final_candidate = IQK_ROUND_INVALID;
973 bool good;
974
975 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] Start!!!\n");
976
977 memset(result, 0, sizeof(result));
978
979 rtw8723x_iqk_backup_path_ctrl(rtwdev, &backup);
980 rtw8723x_iqk_backup_lte_path_gnt(rtwdev, &backup);
981 rtw8723x_iqk_backup_regs(rtwdev, &backup);
982
983 for (i = IQK_ROUND_0; i <= IQK_ROUND_2; i++) {
984 rtw8723x_iqk_config_path_ctrl(rtwdev);
985 rtw8723x_iqk_config_lte_path_gnt(rtwdev, IQK_LTE_WRITE_VAL_8723D);
986
987 rtw8723d_iqk_one_round(rtwdev, result, i, &backup);
988
989 if (i > IQK_ROUND_0)
990 rtw8723x_iqk_restore_regs(rtwdev, &backup);
991 rtw8723x_iqk_restore_lte_path_gnt(rtwdev, &backup);
992 rtw8723x_iqk_restore_path_ctrl(rtwdev, &backup);
993
994 for (j = IQK_ROUND_0; j < i; j++) {
995 good = rtw8723x_iqk_similarity_cmp(rtwdev, result, j, i);
996
997 if (good) {
998 final_candidate = j;
999 rtw_dbg(rtwdev, RTW_DBG_RFK,
1000 "[IQK] cmp %d:%d final_candidate is %x\n",
1001 j, i, final_candidate);
1002 goto iqk_done;
1003 }
1004 }
1005 }
1006
1007 if (final_candidate == IQK_ROUND_INVALID) {
1008 s32 reg_tmp = 0;
1009
1010 for (i = 0; i < IQK_NR; i++)
1011 reg_tmp += result[IQK_ROUND_HYBRID][i];
1012
1013 if (reg_tmp != 0) {
1014 final_candidate = IQK_ROUND_HYBRID;
1015 } else {
1016 WARN(1, "IQK is failed\n");
1017 goto out;
1018 }
1019 }
1020
1021 iqk_done:
1022 rtw8723d_iqk_fill_s1_matrix(rtwdev, result[final_candidate]);
1023 rtw8723d_iqk_fill_s0_matrix(rtwdev, result[final_candidate]);
1024
1025 dm_info->iqk.result.s1_x = result[final_candidate][IQK_S1_TX_X];
1026 dm_info->iqk.result.s1_y = result[final_candidate][IQK_S1_TX_Y];
1027 dm_info->iqk.result.s0_x = result[final_candidate][IQK_S0_TX_X];
1028 dm_info->iqk.result.s0_y = result[final_candidate][IQK_S0_TX_Y];
1029 dm_info->iqk.done = true;
1030
1031 out:
1032 rtw_write32(rtwdev, REG_BB_SEL_BTG, backup.bb_sel_btg);
1033
1034 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] final_candidate is %x\n",
1035 final_candidate);
1036
1037 for (i = IQK_ROUND_0; i < IQK_ROUND_SIZE; i++)
1038 rtw_dbg(rtwdev, RTW_DBG_RFK,
1039 "[IQK] Result %u: rege94_s1=%x rege9c_s1=%x regea4_s1=%x regeac_s1=%x rege94_s0=%x rege9c_s0=%x regea4_s0=%x regeac_s0=%x %s\n",
1040 i,
1041 result[i][0], result[i][1], result[i][2], result[i][3],
1042 result[i][4], result[i][5], result[i][6], result[i][7],
1043 final_candidate == i ? "(final candidate)" : "");
1044
1045 rtw_dbg(rtwdev, RTW_DBG_RFK,
1046 "[IQK]0xc80 = 0x%x 0xc94 = 0x%x 0xc14 = 0x%x 0xca0 = 0x%x\n",
1047 rtw_read32(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE),
1048 rtw_read32(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N),
1049 rtw_read32(rtwdev, REG_A_RXIQI),
1050 rtw_read32(rtwdev, REG_RXIQK_MATRIX_LSB_11N));
1051 rtw_dbg(rtwdev, RTW_DBG_RFK,
1052 "[IQK]0xcd0 = 0x%x 0xcd4 = 0x%x 0xcd8 = 0x%x\n",
1053 rtw_read32(rtwdev, REG_TXIQ_AB_S0),
1054 rtw_read32(rtwdev, REG_TXIQ_CD_S0),
1055 rtw_read32(rtwdev, REG_RXIQ_AB_S0));
1056
1057 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] finished\n");
1058 }
1059
rtw8723d_phy_cck_pd_set(struct rtw_dev * rtwdev,u8 new_lvl)1060 static void rtw8723d_phy_cck_pd_set(struct rtw_dev *rtwdev, u8 new_lvl)
1061 {
1062 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1063 u8 pd[CCK_PD_LV_MAX] = {3, 7, 13, 13, 13};
1064 u8 cck_n_rx;
1065
1066 rtw_dbg(rtwdev, RTW_DBG_PHY, "lv: (%d) -> (%d)\n",
1067 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A], new_lvl);
1068
1069 if (dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] == new_lvl)
1070 return;
1071
1072 cck_n_rx = (rtw_read8_mask(rtwdev, REG_CCK0_FAREPORT, BIT_CCK0_2RX) &&
1073 rtw_read8_mask(rtwdev, REG_CCK0_FAREPORT, BIT_CCK0_MRC)) ? 2 : 1;
1074 rtw_dbg(rtwdev, RTW_DBG_PHY,
1075 "is_linked=%d, lv=%d, n_rx=%d, cs_ratio=0x%x, pd_th=0x%x, cck_fa_avg=%d\n",
1076 rtw_is_assoc(rtwdev), new_lvl, cck_n_rx,
1077 dm_info->cck_pd_default + new_lvl * 2,
1078 pd[new_lvl], dm_info->cck_fa_avg);
1079
1080 dm_info->cck_fa_avg = CCK_FA_AVG_RESET;
1081
1082 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] = new_lvl;
1083 rtw_write32_mask(rtwdev, REG_PWRTH, 0x3f0000, pd[new_lvl]);
1084 rtw_write32_mask(rtwdev, REG_PWRTH2, 0x1f0000,
1085 dm_info->cck_pd_default + new_lvl * 2);
1086 }
1087
1088 /* for coex */
rtw8723d_coex_cfg_gnt_fix(struct rtw_dev * rtwdev)1089 static void rtw8723d_coex_cfg_gnt_fix(struct rtw_dev *rtwdev)
1090 {
1091 }
1092
rtw8723d_coex_cfg_gnt_debug(struct rtw_dev * rtwdev)1093 static void rtw8723d_coex_cfg_gnt_debug(struct rtw_dev *rtwdev)
1094 {
1095 rtw_write8_mask(rtwdev, REG_LEDCFG2, BIT(6), 0);
1096 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT(0), 0);
1097 rtw_write8_mask(rtwdev, REG_GPIO_INTM + 2, BIT(4), 0);
1098 rtw_write8_mask(rtwdev, REG_GPIO_MUXCFG + 2, BIT(1), 0);
1099 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT(1), 0);
1100 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 2, BIT(7), 0);
1101 rtw_write8_mask(rtwdev, REG_SYS_CLKR + 1, BIT(1), 0);
1102 rtw_write8_mask(rtwdev, REG_SYS_SDIO_CTRL + 3, BIT(3), 0);
1103 }
1104
rtw8723d_coex_cfg_rfe_type(struct rtw_dev * rtwdev)1105 static void rtw8723d_coex_cfg_rfe_type(struct rtw_dev *rtwdev)
1106 {
1107 struct rtw_efuse *efuse = &rtwdev->efuse;
1108 struct rtw_coex *coex = &rtwdev->coex;
1109 struct rtw_coex_rfe *coex_rfe = &coex->rfe;
1110 bool aux = efuse->bt_setting & BIT(6);
1111
1112 coex_rfe->rfe_module_type = rtwdev->efuse.rfe_option;
1113 coex_rfe->ant_switch_polarity = 0;
1114 coex_rfe->ant_switch_exist = false;
1115 coex_rfe->ant_switch_with_bt = false;
1116 coex_rfe->ant_switch_diversity = false;
1117 coex_rfe->wlg_at_btg = true;
1118
1119 /* decide antenna at main or aux */
1120 if (efuse->share_ant) {
1121 if (aux)
1122 rtw_write16(rtwdev, REG_BB_SEL_BTG, 0x80);
1123 else
1124 rtw_write16(rtwdev, REG_BB_SEL_BTG, 0x200);
1125 } else {
1126 if (aux)
1127 rtw_write16(rtwdev, REG_BB_SEL_BTG, 0x280);
1128 else
1129 rtw_write16(rtwdev, REG_BB_SEL_BTG, 0x0);
1130 }
1131
1132 /* disable LTE coex in wifi side */
1133 rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, BIT_LTE_COEX_EN, 0x0);
1134 rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff);
1135 rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff);
1136 }
1137
rtw8723d_coex_cfg_wl_tx_power(struct rtw_dev * rtwdev,u8 wl_pwr)1138 static void rtw8723d_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr)
1139 {
1140 struct rtw_coex *coex = &rtwdev->coex;
1141 struct rtw_coex_dm *coex_dm = &coex->dm;
1142 static const u8 wl_tx_power[] = {0xb2, 0x90};
1143 u8 pwr;
1144
1145 if (wl_pwr == coex_dm->cur_wl_pwr_lvl)
1146 return;
1147
1148 coex_dm->cur_wl_pwr_lvl = wl_pwr;
1149
1150 if (coex_dm->cur_wl_pwr_lvl >= ARRAY_SIZE(wl_tx_power))
1151 coex_dm->cur_wl_pwr_lvl = ARRAY_SIZE(wl_tx_power) - 1;
1152
1153 pwr = wl_tx_power[coex_dm->cur_wl_pwr_lvl];
1154
1155 rtw_write8(rtwdev, REG_ANA_PARAM1 + 3, pwr);
1156 }
1157
rtw8723d_coex_cfg_wl_rx_gain(struct rtw_dev * rtwdev,bool low_gain)1158 static void rtw8723d_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain)
1159 {
1160 struct rtw_coex *coex = &rtwdev->coex;
1161 struct rtw_coex_dm *coex_dm = &coex->dm;
1162 /* WL Rx Low gain on */
1163 static const u32 wl_rx_low_gain_on[] = {
1164 0xec120101, 0xeb130101, 0xce140101, 0xcd150101, 0xcc160101,
1165 0xcb170101, 0xca180101, 0x8d190101, 0x8c1a0101, 0x8b1b0101,
1166 0x4f1c0101, 0x4e1d0101, 0x4d1e0101, 0x4c1f0101, 0x0e200101,
1167 0x0d210101, 0x0c220101, 0x0b230101, 0xcf240001, 0xce250001,
1168 0xcd260001, 0xcc270001, 0x8f280001
1169 };
1170 /* WL Rx Low gain off */
1171 static const u32 wl_rx_low_gain_off[] = {
1172 0xec120101, 0xeb130101, 0xea140101, 0xe9150101, 0xe8160101,
1173 0xe7170101, 0xe6180101, 0xe5190101, 0xe41a0101, 0xe31b0101,
1174 0xe21c0101, 0xe11d0101, 0xe01e0101, 0x861f0101, 0x85200101,
1175 0x84210101, 0x83220101, 0x82230101, 0x81240101, 0x80250101,
1176 0x44260101, 0x43270101, 0x42280101
1177 };
1178 u8 i;
1179
1180 if (low_gain == coex_dm->cur_wl_rx_low_gain_en)
1181 return;
1182
1183 coex_dm->cur_wl_rx_low_gain_en = low_gain;
1184
1185 if (coex_dm->cur_wl_rx_low_gain_en) {
1186 for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_on); i++)
1187 rtw_write32(rtwdev, REG_AGCRSSI, wl_rx_low_gain_on[i]);
1188 } else {
1189 for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_off); i++)
1190 rtw_write32(rtwdev, REG_AGCRSSI, wl_rx_low_gain_off[i]);
1191 }
1192 }
1193
rtw8723d_set_iqk_matrix_by_result(struct rtw_dev * rtwdev,u32 ofdm_swing,u8 rf_path)1194 static void rtw8723d_set_iqk_matrix_by_result(struct rtw_dev *rtwdev,
1195 u32 ofdm_swing, u8 rf_path)
1196 {
1197 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1198 s32 ele_A, ele_D, ele_C;
1199 s32 ele_A_ext, ele_C_ext, ele_D_ext;
1200 s32 iqk_result_x;
1201 s32 iqk_result_y;
1202 s32 value32;
1203
1204 switch (rf_path) {
1205 default:
1206 case RF_PATH_A:
1207 iqk_result_x = dm_info->iqk.result.s1_x;
1208 iqk_result_y = dm_info->iqk.result.s1_y;
1209 break;
1210 case RF_PATH_B:
1211 iqk_result_x = dm_info->iqk.result.s0_x;
1212 iqk_result_y = dm_info->iqk.result.s0_y;
1213 break;
1214 }
1215
1216 /* new element D */
1217 ele_D = OFDM_SWING_D(ofdm_swing);
1218 iqk_mult(iqk_result_x, ele_D, &ele_D_ext);
1219 /* new element A */
1220 iqk_result_x = iqkxy_to_s32(iqk_result_x);
1221 ele_A = iqk_mult(iqk_result_x, ele_D, &ele_A_ext);
1222 /* new element C */
1223 iqk_result_y = iqkxy_to_s32(iqk_result_y);
1224 ele_C = iqk_mult(iqk_result_y, ele_D, &ele_C_ext);
1225
1226 switch (rf_path) {
1227 case RF_PATH_A:
1228 default:
1229 /* write new elements A, C, D, and element B is always 0 */
1230 value32 = BIT_SET_TXIQ_ELM_ACD(ele_A, ele_C, ele_D);
1231 rtw_write32(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, value32);
1232 value32 = BIT_SET_TXIQ_ELM_C1(ele_C);
1233 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N, MASKH4BITS,
1234 value32);
1235 value32 = rtw_read32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD);
1236 value32 &= ~BIT_MASK_OFDM0_EXTS;
1237 value32 |= BIT_SET_OFDM0_EXTS(ele_A_ext, ele_C_ext, ele_D_ext);
1238 rtw_write32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, value32);
1239 break;
1240
1241 case RF_PATH_B:
1242 /* write new elements A, C, D, and element B is always 0 */
1243 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_D_S0, ele_D);
1244 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_S0, ele_C);
1245 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_S0, ele_A);
1246
1247 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_D_EXT_S0,
1248 ele_D_ext);
1249 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_EXT_S0,
1250 ele_A_ext);
1251 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_EXT_S0,
1252 ele_C_ext);
1253 break;
1254 }
1255 }
1256
rtw8723d_set_iqk_matrix(struct rtw_dev * rtwdev,s8 ofdm_index,u8 rf_path)1257 static void rtw8723d_set_iqk_matrix(struct rtw_dev *rtwdev, s8 ofdm_index,
1258 u8 rf_path)
1259 {
1260 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1261 s32 value32;
1262 u32 ofdm_swing;
1263
1264 if (ofdm_index >= RTW_OFDM_SWING_TABLE_SIZE)
1265 ofdm_index = RTW_OFDM_SWING_TABLE_SIZE - 1;
1266 else if (ofdm_index < 0)
1267 ofdm_index = 0;
1268
1269 ofdm_swing = rtw8723d_ofdm_swing_table[ofdm_index];
1270
1271 if (dm_info->iqk.done) {
1272 rtw8723d_set_iqk_matrix_by_result(rtwdev, ofdm_swing, rf_path);
1273 return;
1274 }
1275
1276 switch (rf_path) {
1277 case RF_PATH_A:
1278 default:
1279 rtw_write32(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, ofdm_swing);
1280 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N, MASKH4BITS,
1281 0x00);
1282 value32 = rtw_read32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD);
1283 value32 &= ~BIT_MASK_OFDM0_EXTS;
1284 rtw_write32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, value32);
1285 break;
1286
1287 case RF_PATH_B:
1288 /* image S1:c80 to S0:Cd0 and Cd4 */
1289 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_S0,
1290 OFDM_SWING_A(ofdm_swing));
1291 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_B_S0,
1292 OFDM_SWING_B(ofdm_swing));
1293 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_S0,
1294 OFDM_SWING_C(ofdm_swing));
1295 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_D_S0,
1296 OFDM_SWING_D(ofdm_swing));
1297 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_D_EXT_S0, 0x0);
1298 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_EXT_S0, 0x0);
1299 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_EXT_S0, 0x0);
1300 break;
1301 }
1302 }
1303
rtw8723d_pwrtrack_set_ofdm_pwr(struct rtw_dev * rtwdev,s8 swing_idx,s8 txagc_idx)1304 static void rtw8723d_pwrtrack_set_ofdm_pwr(struct rtw_dev *rtwdev, s8 swing_idx,
1305 s8 txagc_idx)
1306 {
1307 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1308
1309 dm_info->txagc_remnant_ofdm = txagc_idx;
1310
1311 rtw8723d_set_iqk_matrix(rtwdev, swing_idx, RF_PATH_A);
1312 rtw8723d_set_iqk_matrix(rtwdev, swing_idx, RF_PATH_B);
1313 }
1314
rtw8723d_pwrtrack_set_cck_pwr(struct rtw_dev * rtwdev,s8 swing_idx,s8 txagc_idx)1315 static void rtw8723d_pwrtrack_set_cck_pwr(struct rtw_dev *rtwdev, s8 swing_idx,
1316 s8 txagc_idx)
1317 {
1318 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1319
1320 dm_info->txagc_remnant_cck = txagc_idx;
1321
1322 rtw_write32_mask(rtwdev, 0xab4, 0x000007FF,
1323 rtw8723d_cck_swing_table[swing_idx]);
1324 }
1325
rtw8723d_pwrtrack_set(struct rtw_dev * rtwdev,u8 path)1326 static void rtw8723d_pwrtrack_set(struct rtw_dev *rtwdev, u8 path)
1327 {
1328 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1329 struct rtw_hal *hal = &rtwdev->hal;
1330 u8 limit_ofdm;
1331 u8 limit_cck = 40;
1332 s8 final_ofdm_swing_index;
1333 s8 final_cck_swing_index;
1334
1335 limit_ofdm = rtw8723x_pwrtrack_get_limit_ofdm(rtwdev);
1336
1337 final_ofdm_swing_index = RTW_DEF_OFDM_SWING_INDEX +
1338 dm_info->delta_power_index[path];
1339 final_cck_swing_index = RTW_DEF_CCK_SWING_INDEX +
1340 dm_info->delta_power_index[path];
1341
1342 if (final_ofdm_swing_index > limit_ofdm)
1343 rtw8723d_pwrtrack_set_ofdm_pwr(rtwdev, limit_ofdm,
1344 final_ofdm_swing_index - limit_ofdm);
1345 else if (final_ofdm_swing_index < 0)
1346 rtw8723d_pwrtrack_set_ofdm_pwr(rtwdev, 0,
1347 final_ofdm_swing_index);
1348 else
1349 rtw8723d_pwrtrack_set_ofdm_pwr(rtwdev, final_ofdm_swing_index, 0);
1350
1351 if (final_cck_swing_index > limit_cck)
1352 rtw8723d_pwrtrack_set_cck_pwr(rtwdev, limit_cck,
1353 final_cck_swing_index - limit_cck);
1354 else if (final_cck_swing_index < 0)
1355 rtw8723d_pwrtrack_set_cck_pwr(rtwdev, 0,
1356 final_cck_swing_index);
1357 else
1358 rtw8723d_pwrtrack_set_cck_pwr(rtwdev, final_cck_swing_index, 0);
1359
1360 rtw_phy_set_tx_power_level(rtwdev, hal->current_channel);
1361 }
1362
rtw8723d_phy_pwrtrack(struct rtw_dev * rtwdev)1363 static void rtw8723d_phy_pwrtrack(struct rtw_dev *rtwdev)
1364 {
1365 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1366 struct rtw_swing_table swing_table;
1367 u8 thermal_value, delta, path;
1368 bool do_iqk = false;
1369
1370 rtw_phy_config_swing_table(rtwdev, &swing_table);
1371
1372 if (rtwdev->efuse.thermal_meter[0] == 0xff)
1373 return;
1374
1375 thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00);
1376
1377 rtw_phy_pwrtrack_avg(rtwdev, thermal_value, RF_PATH_A);
1378
1379 do_iqk = rtw_phy_pwrtrack_need_iqk(rtwdev);
1380
1381 if (do_iqk)
1382 rtw8723x_lck(rtwdev);
1383
1384 if (dm_info->pwr_trk_init_trigger)
1385 dm_info->pwr_trk_init_trigger = false;
1386 else if (!rtw_phy_pwrtrack_thermal_changed(rtwdev, thermal_value,
1387 RF_PATH_A))
1388 goto iqk;
1389
1390 delta = rtw_phy_pwrtrack_get_delta(rtwdev, RF_PATH_A);
1391
1392 delta = min_t(u8, delta, RTW_PWR_TRK_TBL_SZ - 1);
1393
1394 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1395 s8 delta_cur, delta_last;
1396
1397 delta_last = dm_info->delta_power_index[path];
1398 delta_cur = rtw_phy_pwrtrack_get_pwridx(rtwdev, &swing_table,
1399 path, RF_PATH_A, delta);
1400 if (delta_last == delta_cur)
1401 continue;
1402
1403 dm_info->delta_power_index[path] = delta_cur;
1404 rtw8723d_pwrtrack_set(rtwdev, path);
1405 }
1406
1407 rtw8723x_pwrtrack_set_xtal(rtwdev, RF_PATH_A, delta);
1408
1409 iqk:
1410 if (do_iqk)
1411 rtw8723d_phy_calibration(rtwdev);
1412 }
1413
rtw8723d_pwr_track(struct rtw_dev * rtwdev)1414 static void rtw8723d_pwr_track(struct rtw_dev *rtwdev)
1415 {
1416 struct rtw_efuse *efuse = &rtwdev->efuse;
1417 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1418
1419 if (efuse->power_track_type != 0)
1420 return;
1421
1422 if (!dm_info->pwr_trk_triggered) {
1423 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER,
1424 GENMASK(17, 16), 0x03);
1425 dm_info->pwr_trk_triggered = true;
1426 return;
1427 }
1428
1429 rtw8723d_phy_pwrtrack(rtwdev);
1430 dm_info->pwr_trk_triggered = false;
1431 }
1432
1433 static struct rtw_chip_ops rtw8723d_ops = {
1434 .phy_set_param = rtw8723d_phy_set_param,
1435 .read_efuse = rtw8723x_read_efuse,
1436 .query_rx_desc = rtw8723d_query_rx_desc,
1437 .set_channel = rtw8723d_set_channel,
1438 .mac_init = rtw8723x_mac_init,
1439 .shutdown = rtw8723d_shutdown,
1440 .read_rf = rtw_phy_read_rf_sipi,
1441 .write_rf = rtw_phy_write_rf_reg_sipi,
1442 .set_tx_power_index = rtw8723x_set_tx_power_index,
1443 .set_antenna = NULL,
1444 .cfg_ldo25 = rtw8723x_cfg_ldo25,
1445 .efuse_grant = rtw8723x_efuse_grant,
1446 .false_alarm_statistics = rtw8723x_false_alarm_statistics,
1447 .phy_calibration = rtw8723d_phy_calibration,
1448 .cck_pd_set = rtw8723d_phy_cck_pd_set,
1449 .pwr_track = rtw8723d_pwr_track,
1450 .config_bfee = NULL,
1451 .set_gid_table = NULL,
1452 .cfg_csi_rate = NULL,
1453 .fill_txdesc_checksum = rtw8723x_fill_txdesc_checksum,
1454
1455 .coex_set_init = rtw8723x_coex_cfg_init,
1456 .coex_set_ant_switch = NULL,
1457 .coex_set_gnt_fix = rtw8723d_coex_cfg_gnt_fix,
1458 .coex_set_gnt_debug = rtw8723d_coex_cfg_gnt_debug,
1459 .coex_set_rfe_type = rtw8723d_coex_cfg_rfe_type,
1460 .coex_set_wl_tx_power = rtw8723d_coex_cfg_wl_tx_power,
1461 .coex_set_wl_rx_gain = rtw8723d_coex_cfg_wl_rx_gain,
1462 };
1463
1464 /* Shared-Antenna Coex Table */
1465 static const struct coex_table_para table_sant_8723d[] = {
1466 {0xffffffff, 0xffffffff}, /* case-0 */
1467 {0x55555555, 0x55555555},
1468 {0x66555555, 0x66555555},
1469 {0xaaaaaaaa, 0xaaaaaaaa},
1470 {0x5a5a5a5a, 0x5a5a5a5a},
1471 {0xfafafafa, 0xfafafafa}, /* case-5 */
1472 {0x6a5a5555, 0xaaaaaaaa},
1473 {0x6a5a56aa, 0x6a5a56aa},
1474 {0x6a5a5a5a, 0x6a5a5a5a},
1475 {0x66555555, 0x5a5a5a5a},
1476 {0x66555555, 0x6a5a5a5a}, /* case-10 */
1477 {0x66555555, 0x6a5a5aaa},
1478 {0x66555555, 0x5a5a5aaa},
1479 {0x66555555, 0x6aaa5aaa},
1480 {0x66555555, 0xaaaa5aaa},
1481 {0x66555555, 0xaaaaaaaa}, /* case-15 */
1482 {0xffff55ff, 0xfafafafa},
1483 {0xffff55ff, 0x6afa5afa},
1484 {0xaaffffaa, 0xfafafafa},
1485 {0xaa5555aa, 0x5a5a5a5a},
1486 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
1487 {0xaa5555aa, 0xaaaaaaaa},
1488 {0xffffffff, 0x5a5a5a5a},
1489 {0xffffffff, 0x5a5a5a5a},
1490 {0xffffffff, 0x55555555},
1491 {0xffffffff, 0x5a5a5aaa}, /* case-25 */
1492 {0x55555555, 0x5a5a5a5a},
1493 {0x55555555, 0xaaaaaaaa},
1494 {0x55555555, 0x6a5a6a5a},
1495 {0x66556655, 0x66556655},
1496 {0x66556aaa, 0x6a5a6aaa}, /* case-30 */
1497 {0xffffffff, 0x5aaa5aaa},
1498 {0x56555555, 0x5a5a5aaa},
1499 };
1500
1501 /* Non-Shared-Antenna Coex Table */
1502 static const struct coex_table_para table_nsant_8723d[] = {
1503 {0xffffffff, 0xffffffff}, /* case-100 */
1504 {0x55555555, 0x55555555},
1505 {0x66555555, 0x66555555},
1506 {0xaaaaaaaa, 0xaaaaaaaa},
1507 {0x5a5a5a5a, 0x5a5a5a5a},
1508 {0xfafafafa, 0xfafafafa}, /* case-105 */
1509 {0x5afa5afa, 0x5afa5afa},
1510 {0x55555555, 0xfafafafa},
1511 {0x66555555, 0xfafafafa},
1512 {0x66555555, 0x5a5a5a5a},
1513 {0x66555555, 0x6a5a5a5a}, /* case-110 */
1514 {0x66555555, 0xaaaaaaaa},
1515 {0xffff55ff, 0xfafafafa},
1516 {0xffff55ff, 0x5afa5afa},
1517 {0xffff55ff, 0xaaaaaaaa},
1518 {0xffff55ff, 0xffff55ff}, /* case-115 */
1519 {0xaaffffaa, 0x5afa5afa},
1520 {0xaaffffaa, 0xaaaaaaaa},
1521 {0xffffffff, 0xfafafafa},
1522 {0xffffffff, 0x5afa5afa},
1523 {0xffffffff, 0xaaaaaaaa}, /* case-120 */
1524 {0x55ff55ff, 0x5afa5afa},
1525 {0x55ff55ff, 0xaaaaaaaa},
1526 {0x55ff55ff, 0x55ff55ff}
1527 };
1528
1529 /* Shared-Antenna TDMA */
1530 static const struct coex_tdma_para tdma_sant_8723d[] = {
1531 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
1532 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */
1533 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
1534 { {0x61, 0x30, 0x03, 0x11, 0x11} },
1535 { {0x61, 0x20, 0x03, 0x11, 0x11} },
1536 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */
1537 { {0x61, 0x45, 0x03, 0x11, 0x10} },
1538 { {0x61, 0x3a, 0x03, 0x11, 0x10} },
1539 { {0x61, 0x30, 0x03, 0x11, 0x10} },
1540 { {0x61, 0x20, 0x03, 0x11, 0x10} },
1541 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
1542 { {0x61, 0x08, 0x03, 0x11, 0x14} },
1543 { {0x61, 0x08, 0x03, 0x10, 0x14} },
1544 { {0x51, 0x08, 0x03, 0x10, 0x54} },
1545 { {0x51, 0x08, 0x03, 0x10, 0x55} },
1546 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
1547 { {0x51, 0x45, 0x03, 0x10, 0x50} },
1548 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
1549 { {0x51, 0x30, 0x03, 0x10, 0x50} },
1550 { {0x51, 0x20, 0x03, 0x10, 0x50} },
1551 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
1552 { {0x51, 0x4a, 0x03, 0x10, 0x50} },
1553 { {0x51, 0x0c, 0x03, 0x10, 0x54} },
1554 { {0x55, 0x08, 0x03, 0x10, 0x54} },
1555 { {0x65, 0x10, 0x03, 0x11, 0x10} },
1556 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
1557 { {0x51, 0x08, 0x03, 0x10, 0x50} },
1558 { {0x61, 0x08, 0x03, 0x11, 0x11} }
1559 };
1560
1561 /* Non-Shared-Antenna TDMA */
1562 static const struct coex_tdma_para tdma_nsant_8723d[] = {
1563 { {0x00, 0x00, 0x00, 0x00, 0x01} }, /* case-100 */
1564 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-101 */
1565 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
1566 { {0x61, 0x30, 0x03, 0x11, 0x11} },
1567 { {0x61, 0x20, 0x03, 0x11, 0x11} },
1568 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */
1569 { {0x61, 0x45, 0x03, 0x11, 0x10} },
1570 { {0x61, 0x3a, 0x03, 0x11, 0x10} },
1571 { {0x61, 0x30, 0x03, 0x11, 0x10} },
1572 { {0x61, 0x20, 0x03, 0x11, 0x10} },
1573 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */
1574 { {0x61, 0x08, 0x03, 0x11, 0x14} },
1575 { {0x61, 0x08, 0x03, 0x10, 0x14} },
1576 { {0x51, 0x08, 0x03, 0x10, 0x54} },
1577 { {0x51, 0x08, 0x03, 0x10, 0x55} },
1578 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */
1579 { {0x51, 0x45, 0x03, 0x10, 0x50} },
1580 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
1581 { {0x51, 0x30, 0x03, 0x10, 0x50} },
1582 { {0x51, 0x20, 0x03, 0x10, 0x50} },
1583 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-120 */
1584 { {0x51, 0x08, 0x03, 0x10, 0x50} }
1585 };
1586
1587 /* rssi in percentage % (dbm = % - 100) */
1588 static const u8 wl_rssi_step_8723d[] = {60, 50, 44, 30};
1589 static const u8 bt_rssi_step_8723d[] = {30, 30, 30, 30};
1590 static const struct coex_5g_afh_map afh_5g_8723d[] = { {0, 0, 0} };
1591
1592 static const struct rtw_hw_reg btg_reg_8723d = {
1593 .addr = REG_BTG_SEL, .mask = BIT_MASK_BTG_WL,
1594 };
1595
1596 /* wl_tx_dec_power, bt_tx_dec_power, wl_rx_gain, bt_rx_lna_constrain */
1597 static const struct coex_rf_para rf_para_tx_8723d[] = {
1598 {0, 0, false, 7}, /* for normal */
1599 {0, 10, false, 7}, /* for WL-CPT */
1600 {1, 0, true, 4},
1601 {1, 2, true, 4},
1602 {1, 10, true, 4},
1603 {1, 15, true, 4}
1604 };
1605
1606 static const struct coex_rf_para rf_para_rx_8723d[] = {
1607 {0, 0, false, 7}, /* for normal */
1608 {0, 10, false, 7}, /* for WL-CPT */
1609 {1, 0, true, 5},
1610 {1, 2, true, 5},
1611 {1, 10, true, 5},
1612 {1, 15, true, 5}
1613 };
1614
1615 static const struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8723d[] = {
1616 {0x0005,
1617 RTW_PWR_CUT_ALL_MSK,
1618 RTW_PWR_INTF_ALL_MSK,
1619 RTW_PWR_ADDR_MAC,
1620 RTW_PWR_CMD_WRITE, BIT(3) | BIT(7), 0},
1621 {0x0086,
1622 RTW_PWR_CUT_ALL_MSK,
1623 RTW_PWR_INTF_SDIO_MSK,
1624 RTW_PWR_ADDR_SDIO,
1625 RTW_PWR_CMD_WRITE, BIT(0), 0},
1626 {0x0086,
1627 RTW_PWR_CUT_ALL_MSK,
1628 RTW_PWR_INTF_SDIO_MSK,
1629 RTW_PWR_ADDR_SDIO,
1630 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
1631 {0x004A,
1632 RTW_PWR_CUT_ALL_MSK,
1633 RTW_PWR_INTF_USB_MSK,
1634 RTW_PWR_ADDR_MAC,
1635 RTW_PWR_CMD_WRITE, BIT(0), 0},
1636 {0x0005,
1637 RTW_PWR_CUT_ALL_MSK,
1638 RTW_PWR_INTF_ALL_MSK,
1639 RTW_PWR_ADDR_MAC,
1640 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), 0},
1641 {0x0023,
1642 RTW_PWR_CUT_ALL_MSK,
1643 RTW_PWR_INTF_SDIO_MSK,
1644 RTW_PWR_ADDR_MAC,
1645 RTW_PWR_CMD_WRITE, BIT(4), 0},
1646 {0x0301,
1647 RTW_PWR_CUT_ALL_MSK,
1648 RTW_PWR_INTF_PCI_MSK,
1649 RTW_PWR_ADDR_MAC,
1650 RTW_PWR_CMD_WRITE, 0xFF, 0},
1651 {0xFFFF,
1652 RTW_PWR_CUT_ALL_MSK,
1653 RTW_PWR_INTF_ALL_MSK,
1654 0,
1655 RTW_PWR_CMD_END, 0, 0},
1656 };
1657
1658 static const struct rtw_pwr_seq_cmd trans_cardemu_to_act_8723d[] = {
1659 {0x0020,
1660 RTW_PWR_CUT_ALL_MSK,
1661 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1662 RTW_PWR_ADDR_MAC,
1663 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1664 {0x0001,
1665 RTW_PWR_CUT_ALL_MSK,
1666 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1667 RTW_PWR_ADDR_MAC,
1668 RTW_PWR_CMD_DELAY, 1, RTW_PWR_DELAY_MS},
1669 {0x0000,
1670 RTW_PWR_CUT_ALL_MSK,
1671 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1672 RTW_PWR_ADDR_MAC,
1673 RTW_PWR_CMD_WRITE, BIT(5), 0},
1674 {0x0005,
1675 RTW_PWR_CUT_ALL_MSK,
1676 RTW_PWR_INTF_ALL_MSK,
1677 RTW_PWR_ADDR_MAC,
1678 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
1679 {0x0075,
1680 RTW_PWR_CUT_ALL_MSK,
1681 RTW_PWR_INTF_PCI_MSK,
1682 RTW_PWR_ADDR_MAC,
1683 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1684 {0x0006,
1685 RTW_PWR_CUT_ALL_MSK,
1686 RTW_PWR_INTF_ALL_MSK,
1687 RTW_PWR_ADDR_MAC,
1688 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
1689 {0x0075,
1690 RTW_PWR_CUT_ALL_MSK,
1691 RTW_PWR_INTF_PCI_MSK,
1692 RTW_PWR_ADDR_MAC,
1693 RTW_PWR_CMD_WRITE, BIT(0), 0},
1694 {0x0006,
1695 RTW_PWR_CUT_ALL_MSK,
1696 RTW_PWR_INTF_ALL_MSK,
1697 RTW_PWR_ADDR_MAC,
1698 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1699 {0x0005,
1700 RTW_PWR_CUT_ALL_MSK,
1701 RTW_PWR_INTF_ALL_MSK,
1702 RTW_PWR_ADDR_MAC,
1703 RTW_PWR_CMD_POLLING, (BIT(1) | BIT(0)), 0},
1704 {0x0005,
1705 RTW_PWR_CUT_ALL_MSK,
1706 RTW_PWR_INTF_ALL_MSK,
1707 RTW_PWR_ADDR_MAC,
1708 RTW_PWR_CMD_WRITE, BIT(7), 0},
1709 {0x0005,
1710 RTW_PWR_CUT_ALL_MSK,
1711 RTW_PWR_INTF_ALL_MSK,
1712 RTW_PWR_ADDR_MAC,
1713 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
1714 {0x0005,
1715 RTW_PWR_CUT_ALL_MSK,
1716 RTW_PWR_INTF_ALL_MSK,
1717 RTW_PWR_ADDR_MAC,
1718 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1719 {0x0005,
1720 RTW_PWR_CUT_ALL_MSK,
1721 RTW_PWR_INTF_ALL_MSK,
1722 RTW_PWR_ADDR_MAC,
1723 RTW_PWR_CMD_POLLING, BIT(0), 0},
1724 {0x0010,
1725 RTW_PWR_CUT_ALL_MSK,
1726 RTW_PWR_INTF_ALL_MSK,
1727 RTW_PWR_ADDR_MAC,
1728 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)},
1729 {0x0049,
1730 RTW_PWR_CUT_ALL_MSK,
1731 RTW_PWR_INTF_ALL_MSK,
1732 RTW_PWR_ADDR_MAC,
1733 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
1734 {0x0063,
1735 RTW_PWR_CUT_ALL_MSK,
1736 RTW_PWR_INTF_ALL_MSK,
1737 RTW_PWR_ADDR_MAC,
1738 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
1739 {0x0062,
1740 RTW_PWR_CUT_ALL_MSK,
1741 RTW_PWR_INTF_ALL_MSK,
1742 RTW_PWR_ADDR_MAC,
1743 RTW_PWR_CMD_WRITE, BIT(1), 0},
1744 {0x0058,
1745 RTW_PWR_CUT_ALL_MSK,
1746 RTW_PWR_INTF_ALL_MSK,
1747 RTW_PWR_ADDR_MAC,
1748 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1749 {0x005A,
1750 RTW_PWR_CUT_ALL_MSK,
1751 RTW_PWR_INTF_ALL_MSK,
1752 RTW_PWR_ADDR_MAC,
1753 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
1754 {0x0068,
1755 RTW_PWR_CUT_TEST_MSK,
1756 RTW_PWR_INTF_ALL_MSK,
1757 RTW_PWR_ADDR_MAC,
1758 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)},
1759 {0x0069,
1760 RTW_PWR_CUT_ALL_MSK,
1761 RTW_PWR_INTF_ALL_MSK,
1762 RTW_PWR_ADDR_MAC,
1763 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)},
1764 {0x001f,
1765 RTW_PWR_CUT_ALL_MSK,
1766 RTW_PWR_INTF_ALL_MSK,
1767 RTW_PWR_ADDR_MAC,
1768 RTW_PWR_CMD_WRITE, 0xFF, 0x00},
1769 {0x0077,
1770 RTW_PWR_CUT_ALL_MSK,
1771 RTW_PWR_INTF_ALL_MSK,
1772 RTW_PWR_ADDR_MAC,
1773 RTW_PWR_CMD_WRITE, 0xFF, 0x00},
1774 {0x001f,
1775 RTW_PWR_CUT_ALL_MSK,
1776 RTW_PWR_INTF_ALL_MSK,
1777 RTW_PWR_ADDR_MAC,
1778 RTW_PWR_CMD_WRITE, 0xFF, 0x07},
1779 {0x0077,
1780 RTW_PWR_CUT_ALL_MSK,
1781 RTW_PWR_INTF_ALL_MSK,
1782 RTW_PWR_ADDR_MAC,
1783 RTW_PWR_CMD_WRITE, 0xFF, 0x07},
1784 {0xFFFF,
1785 RTW_PWR_CUT_ALL_MSK,
1786 RTW_PWR_INTF_ALL_MSK,
1787 0,
1788 RTW_PWR_CMD_END, 0, 0},
1789 };
1790
1791 static const struct rtw_pwr_seq_cmd *card_enable_flow_8723d[] = {
1792 trans_carddis_to_cardemu_8723d,
1793 trans_cardemu_to_act_8723d,
1794 NULL
1795 };
1796
1797 static const struct rtw_pwr_seq_cmd trans_act_to_lps_8723d[] = {
1798 {0x0301,
1799 RTW_PWR_CUT_ALL_MSK,
1800 RTW_PWR_INTF_PCI_MSK,
1801 RTW_PWR_ADDR_MAC,
1802 RTW_PWR_CMD_WRITE, 0xFF, 0xFF},
1803 {0x0522,
1804 RTW_PWR_CUT_ALL_MSK,
1805 RTW_PWR_INTF_ALL_MSK,
1806 RTW_PWR_ADDR_MAC,
1807 RTW_PWR_CMD_WRITE, 0xFF, 0xFF},
1808 {0x05F8,
1809 RTW_PWR_CUT_ALL_MSK,
1810 RTW_PWR_INTF_ALL_MSK,
1811 RTW_PWR_ADDR_MAC,
1812 RTW_PWR_CMD_POLLING, 0xFF, 0},
1813 {0x05F9,
1814 RTW_PWR_CUT_ALL_MSK,
1815 RTW_PWR_INTF_ALL_MSK,
1816 RTW_PWR_ADDR_MAC,
1817 RTW_PWR_CMD_POLLING, 0xFF, 0},
1818 {0x05FA,
1819 RTW_PWR_CUT_ALL_MSK,
1820 RTW_PWR_INTF_ALL_MSK,
1821 RTW_PWR_ADDR_MAC,
1822 RTW_PWR_CMD_POLLING, 0xFF, 0},
1823 {0x05FB,
1824 RTW_PWR_CUT_ALL_MSK,
1825 RTW_PWR_INTF_ALL_MSK,
1826 RTW_PWR_ADDR_MAC,
1827 RTW_PWR_CMD_POLLING, 0xFF, 0},
1828 {0x0002,
1829 RTW_PWR_CUT_ALL_MSK,
1830 RTW_PWR_INTF_ALL_MSK,
1831 RTW_PWR_ADDR_MAC,
1832 RTW_PWR_CMD_WRITE, BIT(0), 0},
1833 {0x0002,
1834 RTW_PWR_CUT_ALL_MSK,
1835 RTW_PWR_INTF_ALL_MSK,
1836 RTW_PWR_ADDR_MAC,
1837 RTW_PWR_CMD_DELAY, 0, RTW_PWR_DELAY_US},
1838 {0x0002,
1839 RTW_PWR_CUT_ALL_MSK,
1840 RTW_PWR_INTF_ALL_MSK,
1841 RTW_PWR_ADDR_MAC,
1842 RTW_PWR_CMD_WRITE, BIT(1), 0},
1843 {0x0100,
1844 RTW_PWR_CUT_ALL_MSK,
1845 RTW_PWR_INTF_ALL_MSK,
1846 RTW_PWR_ADDR_MAC,
1847 RTW_PWR_CMD_WRITE, 0xFF, 0x03},
1848 {0x0101,
1849 RTW_PWR_CUT_ALL_MSK,
1850 RTW_PWR_INTF_ALL_MSK,
1851 RTW_PWR_ADDR_MAC,
1852 RTW_PWR_CMD_WRITE, BIT(1), 0},
1853 {0x0093,
1854 RTW_PWR_CUT_ALL_MSK,
1855 RTW_PWR_INTF_SDIO_MSK,
1856 RTW_PWR_ADDR_MAC,
1857 RTW_PWR_CMD_WRITE, 0xFF, 0x00},
1858 {0x0553,
1859 RTW_PWR_CUT_ALL_MSK,
1860 RTW_PWR_INTF_ALL_MSK,
1861 RTW_PWR_ADDR_MAC,
1862 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1863 {0xFFFF,
1864 RTW_PWR_CUT_ALL_MSK,
1865 RTW_PWR_INTF_ALL_MSK,
1866 0,
1867 RTW_PWR_CMD_END, 0, 0},
1868 };
1869
1870 static const struct rtw_pwr_seq_cmd trans_act_to_pre_carddis_8723d[] = {
1871 {0x0003,
1872 RTW_PWR_CUT_ALL_MSK,
1873 RTW_PWR_INTF_ALL_MSK,
1874 RTW_PWR_ADDR_MAC,
1875 RTW_PWR_CMD_WRITE, BIT(2), 0},
1876 {0x0080,
1877 RTW_PWR_CUT_ALL_MSK,
1878 RTW_PWR_INTF_ALL_MSK,
1879 RTW_PWR_ADDR_MAC,
1880 RTW_PWR_CMD_WRITE, 0xFF, 0},
1881 {0xFFFF,
1882 RTW_PWR_CUT_ALL_MSK,
1883 RTW_PWR_INTF_ALL_MSK,
1884 0,
1885 RTW_PWR_CMD_END, 0, 0},
1886 };
1887
1888 static const struct rtw_pwr_seq_cmd trans_act_to_cardemu_8723d[] = {
1889 {0x0002,
1890 RTW_PWR_CUT_ALL_MSK,
1891 RTW_PWR_INTF_ALL_MSK,
1892 RTW_PWR_ADDR_MAC,
1893 RTW_PWR_CMD_WRITE, BIT(0), 0},
1894 {0x0049,
1895 RTW_PWR_CUT_ALL_MSK,
1896 RTW_PWR_INTF_ALL_MSK,
1897 RTW_PWR_ADDR_MAC,
1898 RTW_PWR_CMD_WRITE, BIT(1), 0},
1899 {0x0006,
1900 RTW_PWR_CUT_ALL_MSK,
1901 RTW_PWR_INTF_ALL_MSK,
1902 RTW_PWR_ADDR_MAC,
1903 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1904 {0x0005,
1905 RTW_PWR_CUT_ALL_MSK,
1906 RTW_PWR_INTF_ALL_MSK,
1907 RTW_PWR_ADDR_MAC,
1908 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
1909 {0x0005,
1910 RTW_PWR_CUT_ALL_MSK,
1911 RTW_PWR_INTF_ALL_MSK,
1912 RTW_PWR_ADDR_MAC,
1913 RTW_PWR_CMD_POLLING, BIT(1), 0},
1914 {0x0010,
1915 RTW_PWR_CUT_ALL_MSK,
1916 RTW_PWR_INTF_ALL_MSK,
1917 RTW_PWR_ADDR_MAC,
1918 RTW_PWR_CMD_WRITE, BIT(6), 0},
1919 {0x0000,
1920 RTW_PWR_CUT_ALL_MSK,
1921 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1922 RTW_PWR_ADDR_MAC,
1923 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1924 {0x0020,
1925 RTW_PWR_CUT_ALL_MSK,
1926 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1927 RTW_PWR_ADDR_MAC,
1928 RTW_PWR_CMD_WRITE, BIT(0), 0},
1929 {0xFFFF,
1930 RTW_PWR_CUT_ALL_MSK,
1931 RTW_PWR_INTF_ALL_MSK,
1932 0,
1933 RTW_PWR_CMD_END, 0, 0},
1934 };
1935
1936 static const struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8723d[] = {
1937 {0x0007,
1938 RTW_PWR_CUT_ALL_MSK,
1939 RTW_PWR_INTF_SDIO_MSK,
1940 RTW_PWR_ADDR_MAC,
1941 RTW_PWR_CMD_WRITE, 0xFF, 0x20},
1942 {0x0005,
1943 RTW_PWR_CUT_ALL_MSK,
1944 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK,
1945 RTW_PWR_ADDR_MAC,
1946 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)},
1947 {0x0005,
1948 RTW_PWR_CUT_ALL_MSK,
1949 RTW_PWR_INTF_PCI_MSK,
1950 RTW_PWR_ADDR_MAC,
1951 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)},
1952 {0x0005,
1953 RTW_PWR_CUT_ALL_MSK,
1954 RTW_PWR_INTF_PCI_MSK,
1955 RTW_PWR_ADDR_MAC,
1956 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4)},
1957 {0x004A,
1958 RTW_PWR_CUT_ALL_MSK,
1959 RTW_PWR_INTF_USB_MSK,
1960 RTW_PWR_ADDR_MAC,
1961 RTW_PWR_CMD_WRITE, BIT(0), 1},
1962 {0x0023,
1963 RTW_PWR_CUT_ALL_MSK,
1964 RTW_PWR_INTF_SDIO_MSK,
1965 RTW_PWR_ADDR_MAC,
1966 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)},
1967 {0x0086,
1968 RTW_PWR_CUT_ALL_MSK,
1969 RTW_PWR_INTF_SDIO_MSK,
1970 RTW_PWR_ADDR_SDIO,
1971 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1972 {0x0086,
1973 RTW_PWR_CUT_ALL_MSK,
1974 RTW_PWR_INTF_SDIO_MSK,
1975 RTW_PWR_ADDR_SDIO,
1976 RTW_PWR_CMD_POLLING, BIT(1), 0},
1977 {0xFFFF,
1978 RTW_PWR_CUT_ALL_MSK,
1979 RTW_PWR_INTF_ALL_MSK,
1980 0,
1981 RTW_PWR_CMD_END, 0, 0},
1982 };
1983
1984 static const struct rtw_pwr_seq_cmd trans_act_to_post_carddis_8723d[] = {
1985 {0x001D,
1986 RTW_PWR_CUT_ALL_MSK,
1987 RTW_PWR_INTF_ALL_MSK,
1988 RTW_PWR_ADDR_MAC,
1989 RTW_PWR_CMD_WRITE, BIT(0), 0},
1990 {0x001D,
1991 RTW_PWR_CUT_ALL_MSK,
1992 RTW_PWR_INTF_ALL_MSK,
1993 RTW_PWR_ADDR_MAC,
1994 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1995 {0x001C,
1996 RTW_PWR_CUT_ALL_MSK,
1997 RTW_PWR_INTF_ALL_MSK,
1998 RTW_PWR_ADDR_MAC,
1999 RTW_PWR_CMD_WRITE, 0xFF, 0x0E},
2000 {0xFFFF,
2001 RTW_PWR_CUT_ALL_MSK,
2002 RTW_PWR_INTF_ALL_MSK,
2003 0,
2004 RTW_PWR_CMD_END, 0, 0},
2005 };
2006
2007 static const struct rtw_pwr_seq_cmd *card_disable_flow_8723d[] = {
2008 trans_act_to_lps_8723d,
2009 trans_act_to_pre_carddis_8723d,
2010 trans_act_to_cardemu_8723d,
2011 trans_cardemu_to_carddis_8723d,
2012 trans_act_to_post_carddis_8723d,
2013 NULL
2014 };
2015
2016 static const struct rtw_page_table page_table_8723d[] = {
2017 {12, 2, 2, 0, 1},
2018 {12, 2, 2, 0, 1},
2019 {12, 2, 2, 0, 1},
2020 {12, 2, 2, 0, 1},
2021 {12, 2, 2, 0, 1},
2022 };
2023
2024 static const struct rtw_rqpn rqpn_table_8723d[] = {
2025 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
2026 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
2027 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
2028 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
2029 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
2030 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
2031 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
2032 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH,
2033 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
2034 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
2035 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
2036 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
2037 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
2038 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
2039 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH},
2040 };
2041
2042 static const struct rtw_intf_phy_para pcie_gen1_param_8723d[] = {
2043 {0x0008, 0x4a22,
2044 RTW_IP_SEL_PHY,
2045 RTW_INTF_PHY_CUT_ALL,
2046 RTW_INTF_PHY_PLATFORM_ALL},
2047 {0x0009, 0x1000,
2048 RTW_IP_SEL_PHY,
2049 ~(RTW_INTF_PHY_CUT_A | RTW_INTF_PHY_CUT_B),
2050 RTW_INTF_PHY_PLATFORM_ALL},
2051 {0xFFFF, 0x0000,
2052 RTW_IP_SEL_PHY,
2053 RTW_INTF_PHY_CUT_ALL,
2054 RTW_INTF_PHY_PLATFORM_ALL},
2055 };
2056
2057 static const struct rtw_intf_phy_para_table phy_para_table_8723d = {
2058 .gen1_para = pcie_gen1_param_8723d,
2059 .n_gen1_para = ARRAY_SIZE(pcie_gen1_param_8723d),
2060 };
2061
2062 static const struct rtw_rfe_def rtw8723d_rfe_defs[] = {
2063 [0] = { .phy_pg_tbl = &rtw8723d_bb_pg_tbl,
2064 .txpwr_lmt_tbl = &rtw8723d_txpwr_lmt_tbl,},
2065 };
2066
2067 static const u8 rtw8723d_pwrtrk_2gb_n[] = {
2068 0, 0, 1, 1, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 5,
2069 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10
2070 };
2071
2072 static const u8 rtw8723d_pwrtrk_2gb_p[] = {
2073 0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7,
2074 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10
2075 };
2076
2077 static const u8 rtw8723d_pwrtrk_2ga_n[] = {
2078 0, 0, 1, 1, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 5,
2079 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10
2080 };
2081
2082 static const u8 rtw8723d_pwrtrk_2ga_p[] = {
2083 0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7,
2084 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10
2085 };
2086
2087 static const u8 rtw8723d_pwrtrk_2g_cck_b_n[] = {
2088 0, 1, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6,
2089 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11
2090 };
2091
2092 static const u8 rtw8723d_pwrtrk_2g_cck_b_p[] = {
2093 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7,
2094 7, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11
2095 };
2096
2097 static const u8 rtw8723d_pwrtrk_2g_cck_a_n[] = {
2098 0, 1, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6,
2099 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11
2100 };
2101
2102 static const u8 rtw8723d_pwrtrk_2g_cck_a_p[] = {
2103 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7,
2104 7, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11
2105 };
2106
2107 static const s8 rtw8723d_pwrtrk_xtal_n[] = {
2108 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2109 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
2110 };
2111
2112 static const s8 rtw8723d_pwrtrk_xtal_p[] = {
2113 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2114 0, -10, -12, -14, -16, -16, -16, -16, -16, -16, -16, -16, -16, -16, -16
2115 };
2116
2117 static const struct rtw_pwr_track_tbl rtw8723d_rtw_pwr_track_tbl = {
2118 .pwrtrk_2gb_n = rtw8723d_pwrtrk_2gb_n,
2119 .pwrtrk_2gb_p = rtw8723d_pwrtrk_2gb_p,
2120 .pwrtrk_2ga_n = rtw8723d_pwrtrk_2ga_n,
2121 .pwrtrk_2ga_p = rtw8723d_pwrtrk_2ga_p,
2122 .pwrtrk_2g_cckb_n = rtw8723d_pwrtrk_2g_cck_b_n,
2123 .pwrtrk_2g_cckb_p = rtw8723d_pwrtrk_2g_cck_b_p,
2124 .pwrtrk_2g_ccka_n = rtw8723d_pwrtrk_2g_cck_a_n,
2125 .pwrtrk_2g_ccka_p = rtw8723d_pwrtrk_2g_cck_a_p,
2126 .pwrtrk_xtal_p = rtw8723d_pwrtrk_xtal_p,
2127 .pwrtrk_xtal_n = rtw8723d_pwrtrk_xtal_n,
2128 };
2129
2130 static const struct rtw_reg_domain coex_info_hw_regs_8723d[] = {
2131 {0x948, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2132 {0x67, BIT(7), RTW_REG_DOMAIN_MAC8},
2133 {0, 0, RTW_REG_DOMAIN_NL},
2134 {0x964, BIT(1), RTW_REG_DOMAIN_MAC8},
2135 {0x864, BIT(0), RTW_REG_DOMAIN_MAC8},
2136 {0xab7, BIT(5), RTW_REG_DOMAIN_MAC8},
2137 {0xa01, BIT(7), RTW_REG_DOMAIN_MAC8},
2138 {0, 0, RTW_REG_DOMAIN_NL},
2139 {0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2140 {0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2141 {0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16},
2142 {0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2143 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8},
2144 {0, 0, RTW_REG_DOMAIN_NL},
2145 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8},
2146 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8},
2147 {0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2148 {0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2149 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8},
2150 };
2151
2152 const struct rtw_chip_info rtw8723d_hw_spec = {
2153 .ops = &rtw8723d_ops,
2154 .id = RTW_CHIP_TYPE_8723D,
2155 .fw_name = "rtw88/rtw8723d_fw.bin",
2156 .wlan_cpu = RTW_WCPU_11N,
2157 .tx_pkt_desc_sz = 40,
2158 .tx_buf_desc_sz = 16,
2159 .rx_pkt_desc_sz = 24,
2160 .rx_buf_desc_sz = 8,
2161 .phy_efuse_size = 512,
2162 .log_efuse_size = 512,
2163 .ptct_efuse_size = 96 + 1,
2164 .txff_size = 32768,
2165 .rxff_size = 16384,
2166 .rsvd_drv_pg_num = 8,
2167 .txgi_factor = 1,
2168 .is_pwr_by_rate_dec = true,
2169 .max_power_index = 0x3f,
2170 .csi_buf_pg_num = 0,
2171 .band = RTW_BAND_2G,
2172 .page_size = TX_PAGE_SIZE,
2173 .dig_min = 0x20,
2174 .usb_tx_agg_desc_num = 1,
2175 .ht_supported = true,
2176 .vht_supported = false,
2177 .lps_deep_mode_supported = 0,
2178 .sys_func_en = 0xFD,
2179 .pwr_on_seq = card_enable_flow_8723d,
2180 .pwr_off_seq = card_disable_flow_8723d,
2181 .page_table = page_table_8723d,
2182 .rqpn_table = rqpn_table_8723d,
2183 .prioq_addrs = &rtw8723x_common.prioq_addrs,
2184 .intf_table = &phy_para_table_8723d,
2185 .dig = rtw8723x_common.dig,
2186 .dig_cck = rtw8723x_common.dig_cck,
2187 .rf_sipi_addr = {0x840, 0x844},
2188 .rf_sipi_read_addr = rtw8723x_common.rf_sipi_addr,
2189 .fix_rf_phy_num = 2,
2190 .ltecoex_addr = &rtw8723x_common.ltecoex_addr,
2191 .mac_tbl = &rtw8723d_mac_tbl,
2192 .agc_tbl = &rtw8723d_agc_tbl,
2193 .bb_tbl = &rtw8723d_bb_tbl,
2194 .rf_tbl = {&rtw8723d_rf_a_tbl},
2195 .rfe_defs = rtw8723d_rfe_defs,
2196 .rfe_defs_size = ARRAY_SIZE(rtw8723d_rfe_defs),
2197 .rx_ldpc = false,
2198 .pwr_track_tbl = &rtw8723d_rtw_pwr_track_tbl,
2199 .iqk_threshold = 8,
2200 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
2201 .max_scan_ie_len = IEEE80211_MAX_DATA_LEN,
2202
2203 .coex_para_ver = 0x2007022f,
2204 .bt_desired_ver = 0x2f,
2205 .scbd_support = true,
2206 .new_scbd10_def = true,
2207 .ble_hid_profile_support = false,
2208 .wl_mimo_ps_support = false,
2209 .pstdma_type = COEX_PSTDMA_FORCE_LPSOFF,
2210 .bt_rssi_type = COEX_BTRSSI_RATIO,
2211 .ant_isolation = 15,
2212 .rssi_tolerance = 2,
2213 .wl_rssi_step = wl_rssi_step_8723d,
2214 .bt_rssi_step = bt_rssi_step_8723d,
2215 .table_sant_num = ARRAY_SIZE(table_sant_8723d),
2216 .table_sant = table_sant_8723d,
2217 .table_nsant_num = ARRAY_SIZE(table_nsant_8723d),
2218 .table_nsant = table_nsant_8723d,
2219 .tdma_sant_num = ARRAY_SIZE(tdma_sant_8723d),
2220 .tdma_sant = tdma_sant_8723d,
2221 .tdma_nsant_num = ARRAY_SIZE(tdma_nsant_8723d),
2222 .tdma_nsant = tdma_nsant_8723d,
2223 .wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8723d),
2224 .wl_rf_para_tx = rf_para_tx_8723d,
2225 .wl_rf_para_rx = rf_para_rx_8723d,
2226 .bt_afh_span_bw20 = 0x20,
2227 .bt_afh_span_bw40 = 0x30,
2228 .afh_5g_num = ARRAY_SIZE(afh_5g_8723d),
2229 .afh_5g = afh_5g_8723d,
2230 .btg_reg = &btg_reg_8723d,
2231
2232 .coex_info_hw_regs_num = ARRAY_SIZE(coex_info_hw_regs_8723d),
2233 .coex_info_hw_regs = coex_info_hw_regs_8723d,
2234 };
2235 EXPORT_SYMBOL(rtw8723d_hw_spec);
2236
2237 MODULE_FIRMWARE("rtw88/rtw8723d_fw.bin");
2238
2239 MODULE_AUTHOR("Realtek Corporation");
2240 MODULE_DESCRIPTION("Realtek 802.11n wireless 8723d driver");
2241 MODULE_LICENSE("Dual BSD/GPL");
2242