1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright (C) 2025 Intel Corporation */ 3 4 #ifndef _IXD_LAN_REGS_H_ 5 #define _IXD_LAN_REGS_H_ 6 7 /* Control Plane Function PCI ID */ 8 #define IXD_DEV_ID_CPF 0x1efe 9 10 /* Control Queue (Mailbox) */ 11 #define PF_FW_MBX_REG_LEN 4096 12 #define PF_FW_MBX 0x08400000 13 14 #define PF_FW_ARQBAL (PF_FW_MBX) 15 #define PF_FW_ARQBAH (PF_FW_MBX + 0x4) 16 #define PF_FW_ARQLEN (PF_FW_MBX + 0x8) 17 #define PF_FW_ARQLEN_ARQLEN_M GENMASK(12, 0) 18 #define PF_FW_ARQLEN_ARQENABLE_S 31 19 #define PF_FW_ARQLEN_ARQENABLE_M BIT(PF_FW_ARQLEN_ARQENABLE_S) 20 #define PF_FW_ARQH_ARQH_M GENMASK(12, 0) 21 #define PF_FW_ARQH (PF_FW_MBX + 0xC) 22 #define PF_FW_ARQT (PF_FW_MBX + 0x10) 23 24 #define PF_FW_ATQBAL (PF_FW_MBX + 0x14) 25 #define PF_FW_ATQBAH (PF_FW_MBX + 0x18) 26 #define PF_FW_ATQLEN (PF_FW_MBX + 0x1C) 27 #define PF_FW_ATQLEN_ATQLEN_M GENMASK(9, 0) 28 #define PF_FW_ATQLEN_ATQENABLE_S 31 29 #define PF_FW_ATQLEN_ATQENABLE_M BIT(PF_FW_ATQLEN_ATQENABLE_S) 30 #define PF_FW_ATQH_ATQH_M GENMASK(9, 0) 31 #define PF_FW_ATQH (PF_FW_MBX + 0x20) 32 #define PF_FW_ATQT (PF_FW_MBX + 0x24) 33 34 /* Reset registers */ 35 #define PFGEN_RTRIG_REG_LEN 2048 36 #define PFGEN_RTRIG 0x08407000 /* Device resets */ 37 #define PFGEN_RSTAT 0x08407008 /* PFR status */ 38 #define PFGEN_RSTAT_PFR_STATE_M GENMASK(1, 0) 39 #define PFGEN_CTRL 0x0840700C /* PFR trigger */ 40 #define PFGEN_CTRL_PFSWR BIT(0) 41 42 /** 43 * struct ixd_bar_region - BAR region description 44 * @offset: BAR region offset 45 * @size: BAR region size 46 */ 47 struct ixd_bar_region { 48 resource_size_t offset; 49 resource_size_t size; 50 }; 51 52 /** 53 * struct ixd_reset_reg - structure for reset registers 54 * @rstat: offset of status in register 55 * @rstat_m: status mask 56 * @rstat_ok_v: value that indicates PFR completed status 57 * @rtrigger: offset of reset trigger in register 58 * @rtrigger_m: reset trigger mask 59 */ 60 struct ixd_reset_reg { 61 u32 rstat; 62 u32 rstat_m; 63 u32 rstat_ok_v; 64 u32 rtrigger; 65 u32 rtrigger_m; 66 }; 67 68 #endif /* _IXD_LAN_REGS_H_ */ 69