1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2012 Realtek Corporation.*/
3
4 #include "wifi.h"
5 #include "core.h"
6 #include "pci.h"
7 #include "base.h"
8 #include "ps.h"
9 #include "efuse.h"
10 #include <linux/interrupt.h>
11 #include <linux/export.h>
12 #include <linux/module.h>
13
14 MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>");
15 MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
16 MODULE_AUTHOR("Larry Finger <Larry.FInger@lwfinger.net>");
17 MODULE_LICENSE("GPL");
18 MODULE_DESCRIPTION("PCI basic driver for rtlwifi");
19
20 static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
21 INTEL_VENDOR_ID,
22 ATI_VENDOR_ID,
23 AMD_VENDOR_ID,
24 SIS_VENDOR_ID
25 };
26
27 static const u8 ac_to_hwq[] = {
28 VO_QUEUE,
29 VI_QUEUE,
30 BE_QUEUE,
31 BK_QUEUE
32 };
33
_rtl_mac_to_hwqueue(struct ieee80211_hw * hw,struct sk_buff * skb)34 static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw, struct sk_buff *skb)
35 {
36 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
37 __le16 fc = rtl_get_fc(skb);
38 u8 queue_index = skb_get_queue_mapping(skb);
39 struct ieee80211_hdr *hdr;
40
41 if (unlikely(ieee80211_is_beacon(fc)))
42 return BEACON_QUEUE;
43 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc))
44 return MGNT_QUEUE;
45 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
46 if (ieee80211_is_nullfunc(fc))
47 return HIGH_QUEUE;
48 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) {
49 hdr = rtl_get_hdr(skb);
50
51 if (is_multicast_ether_addr(hdr->addr1) ||
52 is_broadcast_ether_addr(hdr->addr1))
53 return HIGH_QUEUE;
54 }
55
56 return ac_to_hwq[queue_index];
57 }
58
59 /* Update PCI dependent default settings*/
_rtl_pci_update_default_setting(struct ieee80211_hw * hw)60 static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw)
61 {
62 struct rtl_priv *rtlpriv = rtl_priv(hw);
63 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
64 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
65 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
66 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
67 u16 init_aspm;
68
69 ppsc->reg_rfps_level = 0;
70 ppsc->support_aspm = false;
71
72 /*Update PCI ASPM setting */
73 switch (rtlpci->const_pci_aspm) {
74 case 0:
75 /*No ASPM */
76 break;
77
78 case 1:
79 /*ASPM dynamically enabled/disable. */
80 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
81 break;
82
83 case 2:
84 /*ASPM with Clock Req dynamically enabled/disable. */
85 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM |
86 RT_RF_OFF_LEVL_CLK_REQ);
87 break;
88
89 case 3:
90 /* Always enable ASPM and Clock Req
91 * from initialization to halt.
92 */
93 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
94 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM |
95 RT_RF_OFF_LEVL_CLK_REQ);
96 break;
97
98 case 4:
99 /* Always enable ASPM without Clock Req
100 * from initialization to halt.
101 */
102 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM |
103 RT_RF_OFF_LEVL_CLK_REQ);
104 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
105 break;
106 }
107
108 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
109
110 /*Update Radio OFF setting */
111 switch (rtlpci->const_hwsw_rfoff_d3) {
112 case 1:
113 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
114 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
115 break;
116
117 case 2:
118 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
119 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
120 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
121 break;
122
123 case 3:
124 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
125 break;
126 }
127
128 /*Set HW definition to determine if it supports ASPM. */
129 switch (rtlpci->const_support_pciaspm) {
130 case 0:
131 /*Not support ASPM. */
132 ppsc->support_aspm = false;
133 break;
134 case 1:
135 /*Support ASPM. */
136 ppsc->support_aspm = true;
137 ppsc->support_backdoor = true;
138 break;
139 case 2:
140 /*ASPM value set by chipset. */
141 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
142 ppsc->support_aspm = true;
143 break;
144 default:
145 pr_err("switch case %#x not processed\n",
146 rtlpci->const_support_pciaspm);
147 break;
148 }
149
150 /* toshiba aspm issue, toshiba will set aspm selfly
151 * so we should not set aspm in driver
152 */
153 pcie_capability_read_word(rtlpci->pdev, PCI_EXP_LNKCTL, &init_aspm);
154 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE &&
155 ((u8)init_aspm) == (PCI_EXP_LNKCTL_ASPM_L0S |
156 PCI_EXP_LNKCTL_ASPM_L1 | PCI_EXP_LNKCTL_CCC))
157 ppsc->support_aspm = false;
158
159 /* RTL8723BE found on some ASUSTek laptops, such as F441U and
160 * X555UQ with subsystem ID 11ad:1723 are known to output large
161 * amounts of PCIe AER errors during and after boot up, causing
162 * heavy lags, poor network throughput, and occasional lock-ups.
163 */
164 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8723BE &&
165 (rtlpci->pdev->subsystem_vendor == 0x11ad &&
166 rtlpci->pdev->subsystem_device == 0x1723))
167 ppsc->support_aspm = false;
168 }
169
_rtl_pci_platform_switch_device_pci_aspm(struct ieee80211_hw * hw,u8 value)170 static bool _rtl_pci_platform_switch_device_pci_aspm(
171 struct ieee80211_hw *hw,
172 u8 value)
173 {
174 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
175 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
176
177 value &= PCI_EXP_LNKCTL_ASPMC;
178
179 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE)
180 value |= PCI_EXP_LNKCTL_CCC;
181
182 pcie_capability_clear_and_set_word(rtlpci->pdev, PCI_EXP_LNKCTL,
183 PCI_EXP_LNKCTL_ASPMC | value,
184 value);
185
186 return false;
187 }
188
189 /* @value is PCI_EXP_LNKCTL_CLKREQ_EN or 0 to enable/disable clk request. */
_rtl_pci_switch_clk_req(struct ieee80211_hw * hw,u16 value)190 static void _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u16 value)
191 {
192 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
193 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
194
195 value &= PCI_EXP_LNKCTL_CLKREQ_EN;
196
197 pcie_capability_clear_and_set_word(rtlpci->pdev, PCI_EXP_LNKCTL,
198 PCI_EXP_LNKCTL_CLKREQ_EN,
199 value);
200
201 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
202 udelay(100);
203 }
204
205 /*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/
rtl_pci_disable_aspm(struct ieee80211_hw * hw)206 static void rtl_pci_disable_aspm(struct ieee80211_hw *hw)
207 {
208 struct rtl_priv *rtlpriv = rtl_priv(hw);
209 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
210 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
211 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
212 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
213 /*Retrieve original configuration settings. */
214 u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg;
215 u16 aspmlevel = 0;
216 u16 tmp_u1b = 0;
217
218 if (!ppsc->support_aspm)
219 return;
220
221 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
222 rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE,
223 "PCI(Bridge) UNKNOWN\n");
224
225 return;
226 }
227
228 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
229 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
230 _rtl_pci_switch_clk_req(hw, 0x0);
231 }
232
233 /*for promising device will in L0 state after an I/O. */
234 pcie_capability_read_word(rtlpci->pdev, PCI_EXP_LNKCTL, &tmp_u1b);
235
236 /*Set corresponding value. */
237 aspmlevel |= PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1;
238 linkctrl_reg &= ~aspmlevel;
239
240 _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg);
241 }
242
243 /*Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
244 *power saving We should follow the sequence to enable
245 *RTL8192SE first then enable Pci Bridge ASPM
246 *or the system will show bluescreen.
247 */
rtl_pci_enable_aspm(struct ieee80211_hw * hw)248 static void rtl_pci_enable_aspm(struct ieee80211_hw *hw)
249 {
250 struct rtl_priv *rtlpriv = rtl_priv(hw);
251 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
252 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
253 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
254 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
255 u16 aspmlevel;
256 u8 u_device_aspmsetting;
257
258 if (!ppsc->support_aspm)
259 return;
260
261 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
262 rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE,
263 "PCI(Bridge) UNKNOWN\n");
264 return;
265 }
266
267 /*Get ASPM level (with/without Clock Req) */
268 aspmlevel = rtlpci->const_devicepci_aspm_setting;
269 u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg;
270
271 /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/
272 /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */
273
274 u_device_aspmsetting |= aspmlevel;
275
276 _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting);
277
278 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
279 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level &
280 RT_RF_OFF_LEVL_CLK_REQ) ?
281 PCI_EXP_LNKCTL_CLKREQ_EN : 0);
282 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
283 }
284 udelay(100);
285 }
286
rtl_pci_get_amd_l1_patch(struct ieee80211_hw * hw)287 static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw)
288 {
289 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
290
291 bool status = false;
292 u8 offset_e0;
293 unsigned int offset_e4;
294
295 pci_write_config_byte(rtlpci->pdev, 0xe0, 0xa0);
296
297 pci_read_config_byte(rtlpci->pdev, 0xe0, &offset_e0);
298
299 if (offset_e0 == 0xA0) {
300 pci_read_config_dword(rtlpci->pdev, 0xe4, &offset_e4);
301 if (offset_e4 & BIT(23))
302 status = true;
303 }
304
305 return status;
306 }
307
rtl_pci_parse_configuration(struct pci_dev * pdev,struct ieee80211_hw * hw)308 static void rtl_pci_parse_configuration(struct pci_dev *pdev,
309 struct ieee80211_hw *hw)
310 {
311 struct rtl_priv *rtlpriv = rtl_priv(hw);
312 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
313
314 u8 tmp;
315 u16 linkctrl_reg;
316
317 /*Link Control Register */
318 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &linkctrl_reg);
319 pcipriv->ndis_adapter.linkctrl_reg = (u8)linkctrl_reg;
320
321 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n",
322 pcipriv->ndis_adapter.linkctrl_reg);
323
324 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL2,
325 PCI_EXP_DEVCTL2_COMP_TMOUT_DIS);
326
327 tmp = 0x17;
328 pci_write_config_byte(pdev, 0x70f, tmp);
329 }
330
rtl_pci_init_aspm(struct ieee80211_hw * hw)331 static void rtl_pci_init_aspm(struct ieee80211_hw *hw)
332 {
333 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
334
335 _rtl_pci_update_default_setting(hw);
336
337 if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
338 /*Always enable ASPM & Clock Req. */
339 rtl_pci_enable_aspm(hw);
340 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM);
341 }
342 }
343
_rtl_pci_io_handler_init(struct device * dev,struct ieee80211_hw * hw)344 static void _rtl_pci_io_handler_init(struct device *dev,
345 struct ieee80211_hw *hw)
346 {
347 struct rtl_priv *rtlpriv = rtl_priv(hw);
348
349 rtlpriv->io.dev = dev;
350
351 rtlpriv->io.write8 = pci_write8_async;
352 rtlpriv->io.write16 = pci_write16_async;
353 rtlpriv->io.write32 = pci_write32_async;
354
355 rtlpriv->io.read8 = pci_read8_sync;
356 rtlpriv->io.read16 = pci_read16_sync;
357 rtlpriv->io.read32 = pci_read32_sync;
358 }
359
_rtl_update_earlymode_info(struct ieee80211_hw * hw,struct sk_buff * skb,struct rtl_tcb_desc * tcb_desc,u8 tid)360 static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw,
361 struct sk_buff *skb,
362 struct rtl_tcb_desc *tcb_desc, u8 tid)
363 {
364 struct rtl_priv *rtlpriv = rtl_priv(hw);
365 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
366 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
367 struct sk_buff *next_skb;
368 u8 additionlen = FCS_LEN;
369
370 /* here open is 4, wep/tkip is 8, aes is 12*/
371 if (info->control.hw_key)
372 additionlen += info->control.hw_key->icv_len;
373
374 /* The most skb num is 6 */
375 tcb_desc->empkt_num = 0;
376 spin_lock_bh(&rtlpriv->locks.waitq_lock);
377 skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) {
378 struct ieee80211_tx_info *next_info;
379
380 next_info = IEEE80211_SKB_CB(next_skb);
381 if (next_info->flags & IEEE80211_TX_CTL_AMPDU) {
382 tcb_desc->empkt_len[tcb_desc->empkt_num] =
383 next_skb->len + additionlen;
384 tcb_desc->empkt_num++;
385 } else {
386 break;
387 }
388
389 if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid],
390 next_skb))
391 break;
392
393 if (tcb_desc->empkt_num >= rtlhal->max_earlymode_num)
394 break;
395 }
396 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
397
398 return true;
399 }
400
401 /* just for early mode now */
_rtl_pci_tx_chk_waitq(struct ieee80211_hw * hw)402 static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw)
403 {
404 struct rtl_priv *rtlpriv = rtl_priv(hw);
405 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
406 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
407 struct sk_buff *skb = NULL;
408 struct ieee80211_tx_info *info = NULL;
409 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
410 int tid;
411
412 if (!rtlpriv->rtlhal.earlymode_enable)
413 return;
414
415 /* we just use em for BE/BK/VI/VO */
416 for (tid = 7; tid >= 0; tid--) {
417 u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(tid)];
418 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
419
420 while (!mac->act_scanning &&
421 rtlpriv->psc.rfpwr_state == ERFON) {
422 struct rtl_tcb_desc tcb_desc;
423
424 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
425
426 spin_lock(&rtlpriv->locks.waitq_lock);
427 if (!skb_queue_empty(&mac->skb_waitq[tid]) &&
428 (ring->entries - skb_queue_len(&ring->queue) >
429 rtlhal->max_earlymode_num)) {
430 skb = skb_dequeue(&mac->skb_waitq[tid]);
431 } else {
432 spin_unlock(&rtlpriv->locks.waitq_lock);
433 break;
434 }
435 spin_unlock(&rtlpriv->locks.waitq_lock);
436
437 /* Some macaddr can't do early mode. like
438 * multicast/broadcast/no_qos data
439 */
440 info = IEEE80211_SKB_CB(skb);
441 if (info->flags & IEEE80211_TX_CTL_AMPDU)
442 _rtl_update_earlymode_info(hw, skb,
443 &tcb_desc, tid);
444
445 rtlpriv->intf_ops->adapter_tx(hw, NULL, skb, &tcb_desc);
446 }
447 }
448 }
449
_rtl_pci_tx_isr(struct ieee80211_hw * hw,int prio)450 static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio)
451 {
452 struct rtl_priv *rtlpriv = rtl_priv(hw);
453 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
454
455 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
456
457 while (skb_queue_len(&ring->queue)) {
458 struct sk_buff *skb;
459 struct ieee80211_tx_info *info;
460 __le16 fc;
461 u8 tid;
462 u8 *entry;
463
464 if (rtlpriv->use_new_trx_flow)
465 entry = (u8 *)(&ring->buffer_desc[ring->idx]);
466 else
467 entry = (u8 *)(&ring->desc[ring->idx]);
468
469 if (!rtlpriv->cfg->ops->is_tx_desc_closed(hw, prio, ring->idx))
470 return;
471 ring->idx = (ring->idx + 1) % ring->entries;
472
473 skb = __skb_dequeue(&ring->queue);
474 dma_unmap_single(&rtlpci->pdev->dev,
475 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
476 true, HW_DESC_TXBUFF_ADDR),
477 skb->len, DMA_TO_DEVICE);
478
479 /* remove early mode header */
480 if (rtlpriv->rtlhal.earlymode_enable)
481 skb_pull(skb, EM_HDR_LEN);
482
483 rtl_dbg(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE,
484 "new ring->idx:%d, free: skb_queue_len:%d, free: seq:%x\n",
485 ring->idx,
486 skb_queue_len(&ring->queue),
487 *(u16 *)(skb->data + 22));
488
489 if (prio == TXCMD_QUEUE) {
490 dev_kfree_skb(skb);
491 goto tx_status_ok;
492 }
493
494 /* for sw LPS, just after NULL skb send out, we can
495 * sure AP knows we are sleeping, we should not let
496 * rf sleep
497 */
498 fc = rtl_get_fc(skb);
499 if (ieee80211_is_nullfunc(fc)) {
500 if (ieee80211_has_pm(fc)) {
501 rtlpriv->mac80211.offchan_delay = true;
502 rtlpriv->psc.state_inap = true;
503 } else {
504 rtlpriv->psc.state_inap = false;
505 }
506 }
507 if (ieee80211_is_action(fc)) {
508 struct ieee80211_mgmt *action_frame =
509 (struct ieee80211_mgmt *)skb->data;
510 if (action_frame->u.action.u.ht_smps.action ==
511 WLAN_HT_ACTION_SMPS) {
512 dev_kfree_skb(skb);
513 goto tx_status_ok;
514 }
515 }
516
517 /* update tid tx pkt num */
518 tid = rtl_get_tid(skb);
519 if (tid <= 7)
520 rtlpriv->link_info.tidtx_inperiod[tid]++;
521
522 info = IEEE80211_SKB_CB(skb);
523
524 if (likely(!ieee80211_is_nullfunc(fc))) {
525 ieee80211_tx_info_clear_status(info);
526 info->flags |= IEEE80211_TX_STAT_ACK;
527 /*info->status.rates[0].count = 1; */
528 ieee80211_tx_status_irqsafe(hw, skb);
529 } else {
530 rtl_tx_ackqueue(hw, skb);
531 }
532
533 if ((ring->entries - skb_queue_len(&ring->queue)) <= 4) {
534 rtl_dbg(rtlpriv, COMP_ERR, DBG_DMESG,
535 "more desc left, wake skb_queue@%d, ring->idx = %d, skb_queue_len = 0x%x\n",
536 prio, ring->idx,
537 skb_queue_len(&ring->queue));
538
539 ieee80211_wake_queue(hw, skb_get_queue_mapping(skb));
540 }
541 tx_status_ok:
542 skb = NULL;
543 }
544
545 if (((rtlpriv->link_info.num_rx_inperiod +
546 rtlpriv->link_info.num_tx_inperiod) > 8) ||
547 rtlpriv->link_info.num_rx_inperiod > 2)
548 rtl_lps_leave(hw, false);
549 }
550
_rtl_pci_init_one_rxdesc(struct ieee80211_hw * hw,struct sk_buff * new_skb,u8 * entry,int rxring_idx,int desc_idx)551 static int _rtl_pci_init_one_rxdesc(struct ieee80211_hw *hw,
552 struct sk_buff *new_skb, u8 *entry,
553 int rxring_idx, int desc_idx)
554 {
555 struct rtl_priv *rtlpriv = rtl_priv(hw);
556 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
557 u32 bufferaddress;
558 u8 tmp_one = 1;
559 struct sk_buff *skb;
560
561 if (likely(new_skb)) {
562 skb = new_skb;
563 goto remap;
564 }
565 skb = dev_alloc_skb(rtlpci->rxbuffersize);
566 if (!skb)
567 return 0;
568
569 remap:
570 /* just set skb->cb to mapping addr for pci_unmap_single use */
571 *((dma_addr_t *)skb->cb) =
572 dma_map_single(&rtlpci->pdev->dev, skb_tail_pointer(skb),
573 rtlpci->rxbuffersize, DMA_FROM_DEVICE);
574 bufferaddress = *((dma_addr_t *)skb->cb);
575 if (dma_mapping_error(&rtlpci->pdev->dev, bufferaddress)) {
576 if (!new_skb)
577 kfree_skb(skb);
578 return 0;
579 }
580 rtlpci->rx_ring[rxring_idx].rx_buf[desc_idx] = skb;
581 if (rtlpriv->use_new_trx_flow) {
582 /* skb->cb may be 64 bit address */
583 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
584 HW_DESC_RX_PREPARE,
585 (u8 *)(dma_addr_t *)skb->cb);
586 } else {
587 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
588 HW_DESC_RXBUFF_ADDR,
589 (u8 *)&bufferaddress);
590 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
591 HW_DESC_RXPKT_LEN,
592 (u8 *)&rtlpci->rxbuffersize);
593 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
594 HW_DESC_RXOWN,
595 (u8 *)&tmp_one);
596 }
597 return 1;
598 }
599
600 /* inorder to receive 8K AMSDU we have set skb to
601 * 9100bytes in init rx ring, but if this packet is
602 * not a AMSDU, this large packet will be sent to
603 * TCP/IP directly, this cause big packet ping fail
604 * like: "ping -s 65507", so here we will realloc skb
605 * based on the true size of packet, Mac80211
606 * Probably will do it better, but does not yet.
607 *
608 * Some platform will fail when alloc skb sometimes.
609 * in this condition, we will send the old skb to
610 * mac80211 directly, this will not cause any other
611 * issues, but only this packet will be lost by TCP/IP
612 */
_rtl_pci_rx_to_mac80211(struct ieee80211_hw * hw,struct sk_buff * skb,struct ieee80211_rx_status rx_status)613 static void _rtl_pci_rx_to_mac80211(struct ieee80211_hw *hw,
614 struct sk_buff *skb,
615 struct ieee80211_rx_status rx_status)
616 {
617 if (unlikely(!rtl_action_proc(hw, skb, false))) {
618 dev_kfree_skb_any(skb);
619 } else {
620 struct sk_buff *uskb = NULL;
621
622 uskb = dev_alloc_skb(skb->len + 128);
623 if (likely(uskb)) {
624 memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status,
625 sizeof(rx_status));
626 skb_put_data(uskb, skb->data, skb->len);
627 dev_kfree_skb_any(skb);
628 ieee80211_rx_irqsafe(hw, uskb);
629 } else {
630 ieee80211_rx_irqsafe(hw, skb);
631 }
632 }
633 }
634
635 /*hsisr interrupt handler*/
_rtl_pci_hs_interrupt(struct ieee80211_hw * hw)636 static void _rtl_pci_hs_interrupt(struct ieee80211_hw *hw)
637 {
638 struct rtl_priv *rtlpriv = rtl_priv(hw);
639 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
640
641 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR],
642 rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR]) |
643 rtlpci->sys_irq_mask);
644 }
645
_rtl_pci_rx_interrupt(struct ieee80211_hw * hw)646 static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
647 {
648 struct rtl_priv *rtlpriv = rtl_priv(hw);
649 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
650 int rxring_idx = RTL_PCI_RX_MPDU_QUEUE;
651 struct ieee80211_rx_status rx_status = { 0 };
652 unsigned int count = rtlpci->rxringcount;
653 u8 own;
654 u8 tmp_one;
655 bool unicast = false;
656 u8 hw_queue = 0;
657 unsigned int rx_remained_cnt = 0;
658 struct rtl_stats stats = {
659 .signal = 0,
660 .rate = 0,
661 };
662
663 /*RX NORMAL PKT */
664 while (count--) {
665 struct ieee80211_hdr *hdr;
666 __le16 fc;
667 u16 len;
668 /*rx buffer descriptor */
669 struct rtl_rx_buffer_desc *buffer_desc = NULL;
670 /*if use new trx flow, it means wifi info */
671 struct rtl_rx_desc *pdesc = NULL;
672 /*rx pkt */
673 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[
674 rtlpci->rx_ring[rxring_idx].idx];
675 struct sk_buff *new_skb;
676
677 if (rtlpriv->use_new_trx_flow) {
678 if (rx_remained_cnt == 0)
679 rx_remained_cnt =
680 rtlpriv->cfg->ops->rx_desc_buff_remained_cnt(hw,
681 hw_queue);
682 if (rx_remained_cnt == 0)
683 return;
684 buffer_desc = &rtlpci->rx_ring[rxring_idx].buffer_desc[
685 rtlpci->rx_ring[rxring_idx].idx];
686 pdesc = (struct rtl_rx_desc *)skb->data;
687 } else { /* rx descriptor */
688 pdesc = &rtlpci->rx_ring[rxring_idx].desc[
689 rtlpci->rx_ring[rxring_idx].idx];
690
691 own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc,
692 false,
693 HW_DESC_OWN);
694 if (own) /* wait data to be filled by hardware */
695 return;
696 }
697
698 /* Reaching this point means: data is filled already
699 * AAAAAAttention !!!
700 * We can NOT access 'skb' before 'pci_unmap_single'
701 */
702 dma_unmap_single(&rtlpci->pdev->dev, *((dma_addr_t *)skb->cb),
703 rtlpci->rxbuffersize, DMA_FROM_DEVICE);
704
705 /* get a new skb - if fail, old one will be reused */
706 new_skb = dev_alloc_skb(rtlpci->rxbuffersize);
707 if (unlikely(!new_skb))
708 goto no_new;
709 memset(&rx_status, 0, sizeof(rx_status));
710 rtlpriv->cfg->ops->query_rx_desc(hw, &stats,
711 &rx_status, (u8 *)pdesc, skb);
712
713 if (rtlpriv->use_new_trx_flow)
714 rtlpriv->cfg->ops->rx_check_dma_ok(hw,
715 (u8 *)buffer_desc,
716 hw_queue);
717
718 len = rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc, false,
719 HW_DESC_RXPKT_LEN);
720
721 if (skb->end - skb->tail > len) {
722 skb_put(skb, len);
723 if (rtlpriv->use_new_trx_flow)
724 skb_reserve(skb, stats.rx_drvinfo_size +
725 stats.rx_bufshift + 24);
726 else
727 skb_reserve(skb, stats.rx_drvinfo_size +
728 stats.rx_bufshift);
729 } else {
730 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
731 "skb->end - skb->tail = %d, len is %d\n",
732 skb->end - skb->tail, len);
733 dev_kfree_skb_any(skb);
734 goto new_trx_end;
735 }
736 /* handle command packet here */
737 if (stats.packet_report_type == C2H_PACKET) {
738 rtl_c2hcmd_enqueue(hw, skb);
739 goto new_trx_end;
740 }
741
742 /* NOTICE This can not be use for mac80211,
743 * this is done in mac80211 code,
744 * if done here sec DHCP will fail
745 * skb_trim(skb, skb->len - 4);
746 */
747
748 hdr = rtl_get_hdr(skb);
749 fc = rtl_get_fc(skb);
750
751 if (!stats.crc && !stats.hwerror && (skb->len > FCS_LEN)) {
752 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status,
753 sizeof(rx_status));
754
755 if (is_broadcast_ether_addr(hdr->addr1)) {
756 ;/*TODO*/
757 } else if (is_multicast_ether_addr(hdr->addr1)) {
758 ;/*TODO*/
759 } else {
760 unicast = true;
761 rtlpriv->stats.rxbytesunicast += skb->len;
762 }
763 rtl_is_special_data(hw, skb, false, true);
764
765 if (ieee80211_is_data(fc)) {
766 rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX);
767 if (unicast)
768 rtlpriv->link_info.num_rx_inperiod++;
769 }
770
771 rtl_collect_scan_list(hw, skb);
772
773 /* static bcn for roaming */
774 rtl_beacon_statistic(hw, skb);
775 rtl_p2p_info(hw, (void *)skb->data, skb->len);
776 /* for sw lps */
777 rtl_swlps_beacon(hw, (void *)skb->data, skb->len);
778 rtl_recognize_peer(hw, (void *)skb->data, skb->len);
779 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP &&
780 rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G &&
781 (ieee80211_is_beacon(fc) ||
782 ieee80211_is_probe_resp(fc))) {
783 dev_kfree_skb_any(skb);
784 } else {
785 _rtl_pci_rx_to_mac80211(hw, skb, rx_status);
786 }
787 } else {
788 /* drop packets with errors or those too short */
789 dev_kfree_skb_any(skb);
790 }
791 new_trx_end:
792 if (rtlpriv->use_new_trx_flow) {
793 rtlpci->rx_ring[hw_queue].next_rx_rp += 1;
794 rtlpci->rx_ring[hw_queue].next_rx_rp %=
795 RTL_PCI_MAX_RX_COUNT;
796
797 rx_remained_cnt--;
798 rtl_write_word(rtlpriv, 0x3B4,
799 rtlpci->rx_ring[hw_queue].next_rx_rp);
800 }
801 if (((rtlpriv->link_info.num_rx_inperiod +
802 rtlpriv->link_info.num_tx_inperiod) > 8) ||
803 rtlpriv->link_info.num_rx_inperiod > 2)
804 rtl_lps_leave(hw, false);
805 skb = new_skb;
806 no_new:
807 if (rtlpriv->use_new_trx_flow) {
808 if (!_rtl_pci_init_one_rxdesc(hw, skb, (u8 *)buffer_desc,
809 rxring_idx,
810 rtlpci->rx_ring[rxring_idx].idx)) {
811 if (new_skb)
812 dev_kfree_skb_any(skb);
813 }
814 } else {
815 if (!_rtl_pci_init_one_rxdesc(hw, skb, (u8 *)pdesc,
816 rxring_idx,
817 rtlpci->rx_ring[rxring_idx].idx)) {
818 if (new_skb)
819 dev_kfree_skb_any(skb);
820 }
821 if (rtlpci->rx_ring[rxring_idx].idx ==
822 rtlpci->rxringcount - 1)
823 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc,
824 false,
825 HW_DESC_RXERO,
826 (u8 *)&tmp_one);
827 }
828 rtlpci->rx_ring[rxring_idx].idx =
829 (rtlpci->rx_ring[rxring_idx].idx + 1) %
830 rtlpci->rxringcount;
831 }
832 }
833
_rtl_pci_interrupt(int irq,void * dev_id)834 static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id)
835 {
836 struct ieee80211_hw *hw = dev_id;
837 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
838 struct rtl_priv *rtlpriv = rtl_priv(hw);
839 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
840 unsigned long flags;
841 struct rtl_int intvec = {0};
842
843 irqreturn_t ret = IRQ_HANDLED;
844
845 if (rtlpci->irq_enabled == 0)
846 return ret;
847
848 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
849 rtlpriv->cfg->ops->disable_interrupt(hw);
850
851 /*read ISR: 4/8bytes */
852 rtlpriv->cfg->ops->interrupt_recognized(hw, &intvec);
853
854 /*Shared IRQ or HW disappeared */
855 if (!intvec.inta || intvec.inta == 0xffff)
856 goto done;
857
858 /*<1> beacon related */
859 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK])
860 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
861 "beacon ok interrupt!\n");
862
863 if (unlikely(intvec.inta & rtlpriv->cfg->maps[RTL_IMR_TBDER]))
864 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
865 "beacon err interrupt!\n");
866
867 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BDOK])
868 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, "beacon interrupt!\n");
869
870 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BCNINT]) {
871 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
872 "prepare beacon for interrupt!\n");
873 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet);
874 }
875
876 /*<2> Tx related */
877 if (unlikely(intvec.intb & rtlpriv->cfg->maps[RTL_IMR_TXFOVW]))
878 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, "IMR_TXFOVW!\n");
879
880 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) {
881 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
882 "Manage ok interrupt!\n");
883 _rtl_pci_tx_isr(hw, MGNT_QUEUE);
884 }
885
886 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) {
887 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
888 "HIGH_QUEUE ok interrupt!\n");
889 _rtl_pci_tx_isr(hw, HIGH_QUEUE);
890 }
891
892 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) {
893 rtlpriv->link_info.num_tx_inperiod++;
894
895 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
896 "BK Tx OK interrupt!\n");
897 _rtl_pci_tx_isr(hw, BK_QUEUE);
898 }
899
900 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) {
901 rtlpriv->link_info.num_tx_inperiod++;
902
903 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
904 "BE TX OK interrupt!\n");
905 _rtl_pci_tx_isr(hw, BE_QUEUE);
906 }
907
908 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) {
909 rtlpriv->link_info.num_tx_inperiod++;
910
911 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
912 "VI TX OK interrupt!\n");
913 _rtl_pci_tx_isr(hw, VI_QUEUE);
914 }
915
916 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) {
917 rtlpriv->link_info.num_tx_inperiod++;
918
919 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
920 "Vo TX OK interrupt!\n");
921 _rtl_pci_tx_isr(hw, VO_QUEUE);
922 }
923
924 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) {
925 if (intvec.intd & rtlpriv->cfg->maps[RTL_IMR_H2CDOK]) {
926 rtlpriv->link_info.num_tx_inperiod++;
927
928 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
929 "H2C TX OK interrupt!\n");
930 _rtl_pci_tx_isr(hw, H2C_QUEUE);
931 }
932 }
933
934 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) {
935 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) {
936 rtlpriv->link_info.num_tx_inperiod++;
937
938 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
939 "CMD TX OK interrupt!\n");
940 _rtl_pci_tx_isr(hw, TXCMD_QUEUE);
941 }
942 }
943
944 /*<3> Rx related */
945 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) {
946 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, "Rx ok interrupt!\n");
947 _rtl_pci_rx_interrupt(hw);
948 }
949
950 if (unlikely(intvec.inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) {
951 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
952 "rx descriptor unavailable!\n");
953 _rtl_pci_rx_interrupt(hw);
954 }
955
956 if (unlikely(intvec.intb & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) {
957 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, "rx overflow !\n");
958 _rtl_pci_rx_interrupt(hw);
959 }
960
961 /*<4> fw related*/
962 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE) {
963 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_C2HCMD]) {
964 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
965 "firmware interrupt!\n");
966 queue_delayed_work(rtlpriv->works.rtl_wq,
967 &rtlpriv->works.fwevt_wq, 0);
968 }
969 }
970
971 /*<5> hsisr related*/
972 /* Only 8188EE & 8723BE Supported.
973 * If Other ICs Come in, System will corrupt,
974 * because maps[RTL_IMR_HSISR_IND] & maps[MAC_HSISR]
975 * are not initialized
976 */
977 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8188EE ||
978 rtlhal->hw_type == HARDWARE_TYPE_RTL8723BE) {
979 if (unlikely(intvec.inta &
980 rtlpriv->cfg->maps[RTL_IMR_HSISR_IND])) {
981 rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE,
982 "hsisr interrupt!\n");
983 _rtl_pci_hs_interrupt(hw);
984 }
985 }
986
987 if (rtlpriv->rtlhal.earlymode_enable)
988 tasklet_schedule(&rtlpriv->works.irq_tasklet);
989
990 done:
991 rtlpriv->cfg->ops->enable_interrupt(hw);
992 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
993 return ret;
994 }
995
_rtl_pci_irq_tasklet(struct tasklet_struct * t)996 static void _rtl_pci_irq_tasklet(struct tasklet_struct *t)
997 {
998 struct rtl_priv *rtlpriv = from_tasklet(rtlpriv, t, works.irq_tasklet);
999 struct ieee80211_hw *hw = rtlpriv->hw;
1000 _rtl_pci_tx_chk_waitq(hw);
1001 }
1002
_rtl_pci_prepare_bcn_tasklet(struct tasklet_struct * t)1003 static void _rtl_pci_prepare_bcn_tasklet(struct tasklet_struct *t)
1004 {
1005 struct rtl_priv *rtlpriv = from_tasklet(rtlpriv, t,
1006 works.irq_prepare_bcn_tasklet);
1007 struct ieee80211_hw *hw = rtlpriv->hw;
1008 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1009 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1010 struct rtl8192_tx_ring *ring = NULL;
1011 struct ieee80211_hdr *hdr = NULL;
1012 struct ieee80211_tx_info *info = NULL;
1013 struct sk_buff *pskb = NULL;
1014 struct rtl_tx_desc *pdesc = NULL;
1015 struct rtl_tcb_desc tcb_desc;
1016 /*This is for new trx flow*/
1017 struct rtl_tx_buffer_desc *pbuffer_desc = NULL;
1018 u8 temp_one = 1;
1019 u8 *entry;
1020
1021 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
1022 ring = &rtlpci->tx_ring[BEACON_QUEUE];
1023 pskb = __skb_dequeue(&ring->queue);
1024 if (rtlpriv->use_new_trx_flow)
1025 entry = (u8 *)(&ring->buffer_desc[ring->idx]);
1026 else
1027 entry = (u8 *)(&ring->desc[ring->idx]);
1028 if (pskb) {
1029 dma_unmap_single(&rtlpci->pdev->dev,
1030 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
1031 true, HW_DESC_TXBUFF_ADDR),
1032 pskb->len, DMA_TO_DEVICE);
1033 kfree_skb(pskb);
1034 }
1035
1036 /*NB: the beacon data buffer must be 32-bit aligned. */
1037 pskb = ieee80211_beacon_get(hw, mac->vif, 0);
1038 if (!pskb)
1039 return;
1040 hdr = rtl_get_hdr(pskb);
1041 info = IEEE80211_SKB_CB(pskb);
1042 pdesc = &ring->desc[0];
1043 if (rtlpriv->use_new_trx_flow)
1044 pbuffer_desc = &ring->buffer_desc[0];
1045
1046 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1047 (u8 *)pbuffer_desc, info, NULL, pskb,
1048 BEACON_QUEUE, &tcb_desc);
1049
1050 __skb_queue_tail(&ring->queue, pskb);
1051
1052 if (rtlpriv->use_new_trx_flow) {
1053 temp_one = 4;
1054 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pbuffer_desc, true,
1055 HW_DESC_OWN, (u8 *)&temp_one);
1056 } else {
1057 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, HW_DESC_OWN,
1058 &temp_one);
1059 }
1060 }
1061
_rtl_pci_init_trx_var(struct ieee80211_hw * hw)1062 static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw)
1063 {
1064 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1065 struct rtl_priv *rtlpriv = rtl_priv(hw);
1066 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1067 u8 i;
1068 u16 desc_num;
1069
1070 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE)
1071 desc_num = TX_DESC_NUM_92E;
1072 else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE)
1073 desc_num = TX_DESC_NUM_8822B;
1074 else
1075 desc_num = RT_TXDESC_NUM;
1076
1077 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1078 rtlpci->txringcount[i] = desc_num;
1079
1080 /*we just alloc 2 desc for beacon queue,
1081 *because we just need first desc in hw beacon.
1082 */
1083 rtlpci->txringcount[BEACON_QUEUE] = 2;
1084
1085 /*BE queue need more descriptor for performance
1086 *consideration or, No more tx desc will happen,
1087 *and may cause mac80211 mem leakage.
1088 */
1089 if (!rtl_priv(hw)->use_new_trx_flow)
1090 rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE;
1091
1092 rtlpci->rxbuffersize = 9100; /*2048/1024; */
1093 rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT; /*64; */
1094 }
1095
_rtl_pci_init_struct(struct ieee80211_hw * hw,struct pci_dev * pdev)1096 static void _rtl_pci_init_struct(struct ieee80211_hw *hw,
1097 struct pci_dev *pdev)
1098 {
1099 struct rtl_priv *rtlpriv = rtl_priv(hw);
1100 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1101 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1102 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1103
1104 rtlpci->up_first_time = true;
1105 rtlpci->being_init_adapter = false;
1106
1107 rtlhal->hw = hw;
1108 rtlpci->pdev = pdev;
1109
1110 /*Tx/Rx related var */
1111 _rtl_pci_init_trx_var(hw);
1112
1113 /*IBSS*/
1114 mac->beacon_interval = 100;
1115
1116 /*AMPDU*/
1117 mac->min_space_cfg = 0;
1118 mac->max_mss_density = 0;
1119 /*set sane AMPDU defaults */
1120 mac->current_ampdu_density = 7;
1121 mac->current_ampdu_factor = 3;
1122
1123 /*Retry Limit*/
1124 mac->retry_short = 7;
1125 mac->retry_long = 7;
1126
1127 /*QOS*/
1128 rtlpci->acm_method = EACMWAY2_SW;
1129
1130 /*task */
1131 tasklet_setup(&rtlpriv->works.irq_tasklet, _rtl_pci_irq_tasklet);
1132 tasklet_setup(&rtlpriv->works.irq_prepare_bcn_tasklet,
1133 _rtl_pci_prepare_bcn_tasklet);
1134 INIT_WORK(&rtlpriv->works.lps_change_work,
1135 rtl_lps_change_work_callback);
1136 }
1137
_rtl_pci_init_tx_ring(struct ieee80211_hw * hw,unsigned int prio,unsigned int entries)1138 static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw,
1139 unsigned int prio, unsigned int entries)
1140 {
1141 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1142 struct rtl_priv *rtlpriv = rtl_priv(hw);
1143 struct rtl_tx_buffer_desc *buffer_desc;
1144 struct rtl_tx_desc *desc;
1145 dma_addr_t buffer_desc_dma, desc_dma;
1146 u32 nextdescaddress;
1147 int i;
1148
1149 /* alloc tx buffer desc for new trx flow*/
1150 if (rtlpriv->use_new_trx_flow) {
1151 buffer_desc =
1152 dma_alloc_coherent(&rtlpci->pdev->dev,
1153 sizeof(*buffer_desc) * entries,
1154 &buffer_desc_dma, GFP_KERNEL);
1155
1156 if (!buffer_desc || (unsigned long)buffer_desc & 0xFF) {
1157 pr_err("Cannot allocate TX ring (prio = %d)\n",
1158 prio);
1159 return -ENOMEM;
1160 }
1161
1162 rtlpci->tx_ring[prio].buffer_desc = buffer_desc;
1163 rtlpci->tx_ring[prio].buffer_desc_dma = buffer_desc_dma;
1164
1165 rtlpci->tx_ring[prio].cur_tx_rp = 0;
1166 rtlpci->tx_ring[prio].cur_tx_wp = 0;
1167 }
1168
1169 /* alloc dma for this ring */
1170 desc = dma_alloc_coherent(&rtlpci->pdev->dev, sizeof(*desc) * entries,
1171 &desc_dma, GFP_KERNEL);
1172
1173 if (!desc || (unsigned long)desc & 0xFF) {
1174 pr_err("Cannot allocate TX ring (prio = %d)\n", prio);
1175 return -ENOMEM;
1176 }
1177
1178 rtlpci->tx_ring[prio].desc = desc;
1179 rtlpci->tx_ring[prio].dma = desc_dma;
1180
1181 rtlpci->tx_ring[prio].idx = 0;
1182 rtlpci->tx_ring[prio].entries = entries;
1183 skb_queue_head_init(&rtlpci->tx_ring[prio].queue);
1184
1185 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "queue:%d, ring_addr:%p\n",
1186 prio, desc);
1187
1188 /* init every desc in this ring */
1189 if (!rtlpriv->use_new_trx_flow) {
1190 for (i = 0; i < entries; i++) {
1191 nextdescaddress = (u32)desc_dma +
1192 ((i + 1) % entries) *
1193 sizeof(*desc);
1194
1195 rtlpriv->cfg->ops->set_desc(hw, (u8 *)&desc[i],
1196 true,
1197 HW_DESC_TX_NEXTDESC_ADDR,
1198 (u8 *)&nextdescaddress);
1199 }
1200 }
1201 return 0;
1202 }
1203
_rtl_pci_init_rx_ring(struct ieee80211_hw * hw,int rxring_idx)1204 static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw, int rxring_idx)
1205 {
1206 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1207 struct rtl_priv *rtlpriv = rtl_priv(hw);
1208 int i;
1209
1210 if (rtlpriv->use_new_trx_flow) {
1211 struct rtl_rx_buffer_desc *entry = NULL;
1212 /* alloc dma for this ring */
1213 rtlpci->rx_ring[rxring_idx].buffer_desc =
1214 dma_alloc_coherent(&rtlpci->pdev->dev,
1215 sizeof(*rtlpci->rx_ring[rxring_idx].buffer_desc) *
1216 rtlpci->rxringcount,
1217 &rtlpci->rx_ring[rxring_idx].dma, GFP_KERNEL);
1218 if (!rtlpci->rx_ring[rxring_idx].buffer_desc ||
1219 (ulong)rtlpci->rx_ring[rxring_idx].buffer_desc & 0xFF) {
1220 pr_err("Cannot allocate RX ring\n");
1221 return -ENOMEM;
1222 }
1223
1224 /* init every desc in this ring */
1225 rtlpci->rx_ring[rxring_idx].idx = 0;
1226 for (i = 0; i < rtlpci->rxringcount; i++) {
1227 entry = &rtlpci->rx_ring[rxring_idx].buffer_desc[i];
1228 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry,
1229 rxring_idx, i))
1230 return -ENOMEM;
1231 }
1232 } else {
1233 struct rtl_rx_desc *entry = NULL;
1234 u8 tmp_one = 1;
1235 /* alloc dma for this ring */
1236 rtlpci->rx_ring[rxring_idx].desc =
1237 dma_alloc_coherent(&rtlpci->pdev->dev,
1238 sizeof(*rtlpci->rx_ring[rxring_idx].desc) *
1239 rtlpci->rxringcount,
1240 &rtlpci->rx_ring[rxring_idx].dma, GFP_KERNEL);
1241 if (!rtlpci->rx_ring[rxring_idx].desc ||
1242 (unsigned long)rtlpci->rx_ring[rxring_idx].desc & 0xFF) {
1243 pr_err("Cannot allocate RX ring\n");
1244 return -ENOMEM;
1245 }
1246
1247 /* init every desc in this ring */
1248 rtlpci->rx_ring[rxring_idx].idx = 0;
1249
1250 for (i = 0; i < rtlpci->rxringcount; i++) {
1251 entry = &rtlpci->rx_ring[rxring_idx].desc[i];
1252 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry,
1253 rxring_idx, i))
1254 return -ENOMEM;
1255 }
1256
1257 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
1258 HW_DESC_RXERO, &tmp_one);
1259 }
1260 return 0;
1261 }
1262
_rtl_pci_free_tx_ring(struct ieee80211_hw * hw,unsigned int prio)1263 static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw,
1264 unsigned int prio)
1265 {
1266 struct rtl_priv *rtlpriv = rtl_priv(hw);
1267 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1268 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
1269
1270 /* free every desc in this ring */
1271 while (skb_queue_len(&ring->queue)) {
1272 u8 *entry;
1273 struct sk_buff *skb = __skb_dequeue(&ring->queue);
1274
1275 if (rtlpriv->use_new_trx_flow)
1276 entry = (u8 *)(&ring->buffer_desc[ring->idx]);
1277 else
1278 entry = (u8 *)(&ring->desc[ring->idx]);
1279
1280 dma_unmap_single(&rtlpci->pdev->dev,
1281 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
1282 true, HW_DESC_TXBUFF_ADDR),
1283 skb->len, DMA_TO_DEVICE);
1284 kfree_skb(skb);
1285 ring->idx = (ring->idx + 1) % ring->entries;
1286 }
1287
1288 /* free dma of this ring */
1289 dma_free_coherent(&rtlpci->pdev->dev,
1290 sizeof(*ring->desc) * ring->entries, ring->desc,
1291 ring->dma);
1292 ring->desc = NULL;
1293 if (rtlpriv->use_new_trx_flow) {
1294 dma_free_coherent(&rtlpci->pdev->dev,
1295 sizeof(*ring->buffer_desc) * ring->entries,
1296 ring->buffer_desc, ring->buffer_desc_dma);
1297 ring->buffer_desc = NULL;
1298 }
1299 }
1300
_rtl_pci_free_rx_ring(struct ieee80211_hw * hw,int rxring_idx)1301 static void _rtl_pci_free_rx_ring(struct ieee80211_hw *hw, int rxring_idx)
1302 {
1303 struct rtl_priv *rtlpriv = rtl_priv(hw);
1304 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1305 int i;
1306
1307 /* free every desc in this ring */
1308 for (i = 0; i < rtlpci->rxringcount; i++) {
1309 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[i];
1310
1311 if (!skb)
1312 continue;
1313 dma_unmap_single(&rtlpci->pdev->dev, *((dma_addr_t *)skb->cb),
1314 rtlpci->rxbuffersize, DMA_FROM_DEVICE);
1315 kfree_skb(skb);
1316 }
1317
1318 /* free dma of this ring */
1319 if (rtlpriv->use_new_trx_flow) {
1320 dma_free_coherent(&rtlpci->pdev->dev,
1321 sizeof(*rtlpci->rx_ring[rxring_idx].buffer_desc) *
1322 rtlpci->rxringcount,
1323 rtlpci->rx_ring[rxring_idx].buffer_desc,
1324 rtlpci->rx_ring[rxring_idx].dma);
1325 rtlpci->rx_ring[rxring_idx].buffer_desc = NULL;
1326 } else {
1327 dma_free_coherent(&rtlpci->pdev->dev,
1328 sizeof(*rtlpci->rx_ring[rxring_idx].desc) *
1329 rtlpci->rxringcount,
1330 rtlpci->rx_ring[rxring_idx].desc,
1331 rtlpci->rx_ring[rxring_idx].dma);
1332 rtlpci->rx_ring[rxring_idx].desc = NULL;
1333 }
1334 }
1335
_rtl_pci_init_trx_ring(struct ieee80211_hw * hw)1336 static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw)
1337 {
1338 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1339 int ret;
1340 int i, rxring_idx;
1341
1342 /* rxring_idx 0:RX_MPDU_QUEUE
1343 * rxring_idx 1:RX_CMD_QUEUE
1344 */
1345 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) {
1346 ret = _rtl_pci_init_rx_ring(hw, rxring_idx);
1347 if (ret)
1348 return ret;
1349 }
1350
1351 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1352 ret = _rtl_pci_init_tx_ring(hw, i, rtlpci->txringcount[i]);
1353 if (ret)
1354 goto err_free_rings;
1355 }
1356
1357 return 0;
1358
1359 err_free_rings:
1360 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++)
1361 _rtl_pci_free_rx_ring(hw, rxring_idx);
1362
1363 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1364 if (rtlpci->tx_ring[i].desc ||
1365 rtlpci->tx_ring[i].buffer_desc)
1366 _rtl_pci_free_tx_ring(hw, i);
1367
1368 return 1;
1369 }
1370
_rtl_pci_deinit_trx_ring(struct ieee80211_hw * hw)1371 static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw)
1372 {
1373 u32 i, rxring_idx;
1374
1375 /*free rx rings */
1376 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++)
1377 _rtl_pci_free_rx_ring(hw, rxring_idx);
1378
1379 /*free tx rings */
1380 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1381 _rtl_pci_free_tx_ring(hw, i);
1382
1383 return 0;
1384 }
1385
rtl_pci_reset_trx_ring(struct ieee80211_hw * hw)1386 int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
1387 {
1388 struct rtl_priv *rtlpriv = rtl_priv(hw);
1389 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1390 int i, rxring_idx;
1391 unsigned long flags;
1392 u8 tmp_one = 1;
1393 u32 bufferaddress;
1394 /* rxring_idx 0:RX_MPDU_QUEUE */
1395 /* rxring_idx 1:RX_CMD_QUEUE */
1396 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) {
1397 /* force the rx_ring[RX_MPDU_QUEUE/
1398 * RX_CMD_QUEUE].idx to the first one
1399 *new trx flow, do nothing
1400 */
1401 if (!rtlpriv->use_new_trx_flow &&
1402 rtlpci->rx_ring[rxring_idx].desc) {
1403 struct rtl_rx_desc *entry = NULL;
1404
1405 rtlpci->rx_ring[rxring_idx].idx = 0;
1406 for (i = 0; i < rtlpci->rxringcount; i++) {
1407 entry = &rtlpci->rx_ring[rxring_idx].desc[i];
1408 bufferaddress =
1409 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
1410 false, HW_DESC_RXBUFF_ADDR);
1411 memset((u8 *)entry, 0,
1412 sizeof(*rtlpci->rx_ring
1413 [rxring_idx].desc));/*clear one entry*/
1414 if (rtlpriv->use_new_trx_flow) {
1415 rtlpriv->cfg->ops->set_desc(hw,
1416 (u8 *)entry, false,
1417 HW_DESC_RX_PREPARE,
1418 (u8 *)&bufferaddress);
1419 } else {
1420 rtlpriv->cfg->ops->set_desc(hw,
1421 (u8 *)entry, false,
1422 HW_DESC_RXBUFF_ADDR,
1423 (u8 *)&bufferaddress);
1424 rtlpriv->cfg->ops->set_desc(hw,
1425 (u8 *)entry, false,
1426 HW_DESC_RXPKT_LEN,
1427 (u8 *)&rtlpci->rxbuffersize);
1428 rtlpriv->cfg->ops->set_desc(hw,
1429 (u8 *)entry, false,
1430 HW_DESC_RXOWN,
1431 (u8 *)&tmp_one);
1432 }
1433 }
1434 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
1435 HW_DESC_RXERO, (u8 *)&tmp_one);
1436 }
1437 rtlpci->rx_ring[rxring_idx].idx = 0;
1438 }
1439
1440 /*after reset, release previous pending packet,
1441 *and force the tx idx to the first one
1442 */
1443 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1444 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1445 if (rtlpci->tx_ring[i].desc ||
1446 rtlpci->tx_ring[i].buffer_desc) {
1447 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i];
1448
1449 while (skb_queue_len(&ring->queue)) {
1450 u8 *entry;
1451 struct sk_buff *skb =
1452 __skb_dequeue(&ring->queue);
1453 if (rtlpriv->use_new_trx_flow)
1454 entry = (u8 *)(&ring->buffer_desc
1455 [ring->idx]);
1456 else
1457 entry = (u8 *)(&ring->desc[ring->idx]);
1458
1459 dma_unmap_single(&rtlpci->pdev->dev,
1460 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
1461 true, HW_DESC_TXBUFF_ADDR),
1462 skb->len, DMA_TO_DEVICE);
1463 dev_kfree_skb_irq(skb);
1464 ring->idx = (ring->idx + 1) % ring->entries;
1465 }
1466
1467 if (rtlpriv->use_new_trx_flow) {
1468 rtlpci->tx_ring[i].cur_tx_rp = 0;
1469 rtlpci->tx_ring[i].cur_tx_wp = 0;
1470 }
1471
1472 ring->idx = 0;
1473 ring->entries = rtlpci->txringcount[i];
1474 }
1475 }
1476 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1477
1478 return 0;
1479 }
1480
rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw * hw,struct ieee80211_sta * sta,struct sk_buff * skb)1481 static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw,
1482 struct ieee80211_sta *sta,
1483 struct sk_buff *skb)
1484 {
1485 struct rtl_priv *rtlpriv = rtl_priv(hw);
1486 struct rtl_sta_info *sta_entry = NULL;
1487 u8 tid = rtl_get_tid(skb);
1488 __le16 fc = rtl_get_fc(skb);
1489
1490 if (!sta)
1491 return false;
1492 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1493
1494 if (!rtlpriv->rtlhal.earlymode_enable)
1495 return false;
1496 if (ieee80211_is_nullfunc(fc))
1497 return false;
1498 if (ieee80211_is_qos_nullfunc(fc))
1499 return false;
1500 if (ieee80211_is_pspoll(fc))
1501 return false;
1502 if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL)
1503 return false;
1504 if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE)
1505 return false;
1506 if (tid > 7)
1507 return false;
1508
1509 /* maybe every tid should be checked */
1510 if (!rtlpriv->link_info.higher_busytxtraffic[tid])
1511 return false;
1512
1513 spin_lock_bh(&rtlpriv->locks.waitq_lock);
1514 skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb);
1515 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
1516
1517 return true;
1518 }
1519
rtl_pci_tx(struct ieee80211_hw * hw,struct ieee80211_sta * sta,struct sk_buff * skb,struct rtl_tcb_desc * ptcb_desc)1520 static int rtl_pci_tx(struct ieee80211_hw *hw,
1521 struct ieee80211_sta *sta,
1522 struct sk_buff *skb,
1523 struct rtl_tcb_desc *ptcb_desc)
1524 {
1525 struct rtl_priv *rtlpriv = rtl_priv(hw);
1526 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1527 struct rtl8192_tx_ring *ring;
1528 struct rtl_tx_desc *pdesc;
1529 struct rtl_tx_buffer_desc *ptx_bd_desc = NULL;
1530 u16 idx;
1531 u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb);
1532 unsigned long flags;
1533 struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
1534 __le16 fc = rtl_get_fc(skb);
1535 u8 *pda_addr = hdr->addr1;
1536 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1537 u8 own;
1538 u8 temp_one = 1;
1539
1540 if (ieee80211_is_mgmt(fc))
1541 rtl_tx_mgmt_proc(hw, skb);
1542
1543 if (rtlpriv->psc.sw_ps_enabled) {
1544 if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) &&
1545 !ieee80211_has_pm(fc))
1546 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1547 }
1548
1549 rtl_action_proc(hw, skb, true);
1550
1551 if (is_multicast_ether_addr(pda_addr))
1552 rtlpriv->stats.txbytesmulticast += skb->len;
1553 else if (is_broadcast_ether_addr(pda_addr))
1554 rtlpriv->stats.txbytesbroadcast += skb->len;
1555 else
1556 rtlpriv->stats.txbytesunicast += skb->len;
1557
1558 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1559 ring = &rtlpci->tx_ring[hw_queue];
1560 if (hw_queue != BEACON_QUEUE) {
1561 if (rtlpriv->use_new_trx_flow)
1562 idx = ring->cur_tx_wp;
1563 else
1564 idx = (ring->idx + skb_queue_len(&ring->queue)) %
1565 ring->entries;
1566 } else {
1567 idx = 0;
1568 }
1569
1570 pdesc = &ring->desc[idx];
1571 if (rtlpriv->use_new_trx_flow) {
1572 ptx_bd_desc = &ring->buffer_desc[idx];
1573 } else {
1574 own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc,
1575 true, HW_DESC_OWN);
1576
1577 if (own == 1 && hw_queue != BEACON_QUEUE) {
1578 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1579 "No more TX desc@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n",
1580 hw_queue, ring->idx, idx,
1581 skb_queue_len(&ring->queue));
1582
1583 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock,
1584 flags);
1585 return skb->len;
1586 }
1587 }
1588
1589 if (rtlpriv->cfg->ops->get_available_desc &&
1590 rtlpriv->cfg->ops->get_available_desc(hw, hw_queue) == 0) {
1591 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1592 "get_available_desc fail\n");
1593 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1594 return skb->len;
1595 }
1596
1597 if (ieee80211_is_data(fc))
1598 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX);
1599
1600 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1601 (u8 *)ptx_bd_desc, info, sta, skb, hw_queue, ptcb_desc);
1602
1603 __skb_queue_tail(&ring->queue, skb);
1604
1605 if (rtlpriv->use_new_trx_flow) {
1606 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true,
1607 HW_DESC_OWN, &hw_queue);
1608 } else {
1609 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true,
1610 HW_DESC_OWN, &temp_one);
1611 }
1612
1613 if ((ring->entries - skb_queue_len(&ring->queue)) < 2 &&
1614 hw_queue != BEACON_QUEUE) {
1615 rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
1616 "less desc left, stop skb_queue@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n",
1617 hw_queue, ring->idx, idx,
1618 skb_queue_len(&ring->queue));
1619
1620 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
1621 }
1622
1623 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1624
1625 rtlpriv->cfg->ops->tx_polling(hw, hw_queue);
1626
1627 return 0;
1628 }
1629
rtl_pci_flush(struct ieee80211_hw * hw,u32 queues,bool drop)1630 static void rtl_pci_flush(struct ieee80211_hw *hw, u32 queues, bool drop)
1631 {
1632 struct rtl_priv *rtlpriv = rtl_priv(hw);
1633 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1634 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1635 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1636 u16 i = 0;
1637 int queue_id;
1638 struct rtl8192_tx_ring *ring;
1639
1640 if (mac->skip_scan)
1641 return;
1642
1643 for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) {
1644 u32 queue_len;
1645
1646 if (((queues >> queue_id) & 0x1) == 0) {
1647 queue_id--;
1648 continue;
1649 }
1650 ring = &pcipriv->dev.tx_ring[queue_id];
1651 queue_len = skb_queue_len(&ring->queue);
1652 if (queue_len == 0 || queue_id == BEACON_QUEUE ||
1653 queue_id == TXCMD_QUEUE) {
1654 queue_id--;
1655 continue;
1656 } else {
1657 msleep(20);
1658 i++;
1659 }
1660
1661 /* we just wait 1s for all queues */
1662 if (rtlpriv->psc.rfpwr_state == ERFOFF ||
1663 is_hal_stop(rtlhal) || i >= 200)
1664 return;
1665 }
1666 }
1667
rtl_pci_deinit(struct ieee80211_hw * hw)1668 static void rtl_pci_deinit(struct ieee80211_hw *hw)
1669 {
1670 struct rtl_priv *rtlpriv = rtl_priv(hw);
1671 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1672
1673 _rtl_pci_deinit_trx_ring(hw);
1674
1675 synchronize_irq(rtlpci->pdev->irq);
1676 tasklet_kill(&rtlpriv->works.irq_tasklet);
1677 cancel_work_sync(&rtlpriv->works.lps_change_work);
1678 }
1679
rtl_pci_init(struct ieee80211_hw * hw,struct pci_dev * pdev)1680 static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev)
1681 {
1682 int err;
1683
1684 _rtl_pci_init_struct(hw, pdev);
1685
1686 err = _rtl_pci_init_trx_ring(hw);
1687 if (err) {
1688 pr_err("tx ring initialization failed\n");
1689 return err;
1690 }
1691
1692 return 0;
1693 }
1694
rtl_pci_start(struct ieee80211_hw * hw)1695 static int rtl_pci_start(struct ieee80211_hw *hw)
1696 {
1697 struct rtl_priv *rtlpriv = rtl_priv(hw);
1698 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1699 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1700 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1701 struct rtl_mac *rtlmac = rtl_mac(rtl_priv(hw));
1702 struct rtl_btc_ops *btc_ops = rtlpriv->btcoexist.btc_ops;
1703
1704 int err;
1705
1706 rtl_pci_reset_trx_ring(hw);
1707
1708 rtlpci->driver_is_goingto_unload = false;
1709 if (rtlpriv->cfg->ops->get_btc_status &&
1710 rtlpriv->cfg->ops->get_btc_status()) {
1711 rtlpriv->btcoexist.btc_info.ap_num = 36;
1712 btc_ops->btc_init_variables(rtlpriv);
1713 btc_ops->btc_init_hal_vars(rtlpriv);
1714 } else if (btc_ops) {
1715 btc_ops->btc_init_variables_wifi_only(rtlpriv);
1716 }
1717
1718 err = rtlpriv->cfg->ops->hw_init(hw);
1719 if (err) {
1720 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1721 "Failed to config hardware!\n");
1722 kfree(rtlpriv->btcoexist.btc_context);
1723 kfree(rtlpriv->btcoexist.wifi_only_context);
1724 return err;
1725 }
1726 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT,
1727 &rtlmac->retry_long);
1728
1729 rtlpriv->cfg->ops->enable_interrupt(hw);
1730 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "enable_interrupt OK\n");
1731
1732 rtl_init_rx_config(hw);
1733
1734 /*should be after adapter start and interrupt enable. */
1735 set_hal_start(rtlhal);
1736
1737 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1738
1739 rtlpci->up_first_time = false;
1740
1741 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "%s OK\n", __func__);
1742 return 0;
1743 }
1744
rtl_pci_stop(struct ieee80211_hw * hw)1745 static void rtl_pci_stop(struct ieee80211_hw *hw)
1746 {
1747 struct rtl_priv *rtlpriv = rtl_priv(hw);
1748 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1749 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1750 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1751 unsigned long flags;
1752 u8 rf_timeout = 0;
1753
1754 if (rtlpriv->cfg->ops->get_btc_status())
1755 rtlpriv->btcoexist.btc_ops->btc_halt_notify(rtlpriv);
1756
1757 if (rtlpriv->btcoexist.btc_ops)
1758 rtlpriv->btcoexist.btc_ops->btc_deinit_variables(rtlpriv);
1759
1760 /*should be before disable interrupt&adapter
1761 *and will do it immediately.
1762 */
1763 set_hal_stop(rtlhal);
1764
1765 rtlpci->driver_is_goingto_unload = true;
1766 rtlpriv->cfg->ops->disable_interrupt(hw);
1767 cancel_work_sync(&rtlpriv->works.lps_change_work);
1768
1769 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1770 while (ppsc->rfchange_inprogress) {
1771 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1772 if (rf_timeout > 100) {
1773 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1774 break;
1775 }
1776 mdelay(1);
1777 rf_timeout++;
1778 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1779 }
1780 ppsc->rfchange_inprogress = true;
1781 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1782
1783 rtlpriv->cfg->ops->hw_disable(hw);
1784 /* some things are not needed if firmware not available */
1785 if (!rtlpriv->max_fw_size)
1786 return;
1787 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1788
1789 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1790 ppsc->rfchange_inprogress = false;
1791 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1792
1793 rtl_pci_enable_aspm(hw);
1794 }
1795
_rtl_pci_find_adapter(struct pci_dev * pdev,struct ieee80211_hw * hw)1796 static bool _rtl_pci_find_adapter(struct pci_dev *pdev,
1797 struct ieee80211_hw *hw)
1798 {
1799 struct rtl_priv *rtlpriv = rtl_priv(hw);
1800 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1801 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1802 struct pci_dev *bridge_pdev = pdev->bus->self;
1803 u16 venderid;
1804 u16 deviceid;
1805 u8 revisionid;
1806 u16 irqline;
1807 u8 tmp;
1808
1809 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
1810 venderid = pdev->vendor;
1811 deviceid = pdev->device;
1812 pci_read_config_byte(pdev, 0x8, &revisionid);
1813 pci_read_config_word(pdev, 0x3C, &irqline);
1814
1815 /* PCI ID 0x10ec:0x8192 occurs for both RTL8192E, which uses
1816 * r8192e_pci, and RTL8192SE, which uses this driver. If the
1817 * revision ID is RTL_PCI_REVISION_ID_8192PCIE (0x01), then
1818 * the correct driver is r8192e_pci, thus this routine should
1819 * return false.
1820 */
1821 if (deviceid == RTL_PCI_8192SE_DID &&
1822 revisionid == RTL_PCI_REVISION_ID_8192PCIE)
1823 return false;
1824
1825 if (deviceid == RTL_PCI_8192_DID ||
1826 deviceid == RTL_PCI_0044_DID ||
1827 deviceid == RTL_PCI_0047_DID ||
1828 deviceid == RTL_PCI_8192SE_DID ||
1829 deviceid == RTL_PCI_8174_DID ||
1830 deviceid == RTL_PCI_8173_DID ||
1831 deviceid == RTL_PCI_8172_DID ||
1832 deviceid == RTL_PCI_8171_DID) {
1833 switch (revisionid) {
1834 case RTL_PCI_REVISION_ID_8192PCIE:
1835 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1836 "8192 PCI-E is found - vid/did=%x/%x\n",
1837 venderid, deviceid);
1838 rtlhal->hw_type = HARDWARE_TYPE_RTL8192E;
1839 return false;
1840 case RTL_PCI_REVISION_ID_8192SE:
1841 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1842 "8192SE is found - vid/did=%x/%x\n",
1843 venderid, deviceid);
1844 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1845 break;
1846 default:
1847 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1848 "Err: Unknown device - vid/did=%x/%x\n",
1849 venderid, deviceid);
1850 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1851 break;
1852 }
1853 } else if (deviceid == RTL_PCI_8723AE_DID) {
1854 rtlhal->hw_type = HARDWARE_TYPE_RTL8723AE;
1855 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1856 "8723AE PCI-E is found - vid/did=%x/%x\n",
1857 venderid, deviceid);
1858 } else if (deviceid == RTL_PCI_8192CET_DID ||
1859 deviceid == RTL_PCI_8192CE_DID ||
1860 deviceid == RTL_PCI_8191CE_DID ||
1861 deviceid == RTL_PCI_8188CE_DID) {
1862 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE;
1863 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1864 "8192C PCI-E is found - vid/did=%x/%x\n",
1865 venderid, deviceid);
1866 } else if (deviceid == RTL_PCI_8192DE_DID ||
1867 deviceid == RTL_PCI_8192DE_DID2) {
1868 rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE;
1869 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1870 "8192D PCI-E is found - vid/did=%x/%x\n",
1871 venderid, deviceid);
1872 } else if (deviceid == RTL_PCI_8188EE_DID) {
1873 rtlhal->hw_type = HARDWARE_TYPE_RTL8188EE;
1874 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1875 "Find adapter, Hardware type is 8188EE\n");
1876 } else if (deviceid == RTL_PCI_8723BE_DID) {
1877 rtlhal->hw_type = HARDWARE_TYPE_RTL8723BE;
1878 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1879 "Find adapter, Hardware type is 8723BE\n");
1880 } else if (deviceid == RTL_PCI_8192EE_DID) {
1881 rtlhal->hw_type = HARDWARE_TYPE_RTL8192EE;
1882 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1883 "Find adapter, Hardware type is 8192EE\n");
1884 } else if (deviceid == RTL_PCI_8821AE_DID) {
1885 rtlhal->hw_type = HARDWARE_TYPE_RTL8821AE;
1886 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1887 "Find adapter, Hardware type is 8821AE\n");
1888 } else if (deviceid == RTL_PCI_8812AE_DID) {
1889 rtlhal->hw_type = HARDWARE_TYPE_RTL8812AE;
1890 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1891 "Find adapter, Hardware type is 8812AE\n");
1892 } else if (deviceid == RTL_PCI_8822BE_DID) {
1893 rtlhal->hw_type = HARDWARE_TYPE_RTL8822BE;
1894 rtlhal->bandset = BAND_ON_BOTH;
1895 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1896 "Find adapter, Hardware type is 8822BE\n");
1897 } else {
1898 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1899 "Err: Unknown device - vid/did=%x/%x\n",
1900 venderid, deviceid);
1901
1902 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE;
1903 }
1904
1905 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) {
1906 if (revisionid == 0 || revisionid == 1) {
1907 if (revisionid == 0) {
1908 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1909 "Find 92DE MAC0\n");
1910 rtlhal->interfaceindex = 0;
1911 } else if (revisionid == 1) {
1912 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1913 "Find 92DE MAC1\n");
1914 rtlhal->interfaceindex = 1;
1915 }
1916 } else {
1917 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1918 "Unknown device - VendorID/DeviceID=%x/%x, Revision=%x\n",
1919 venderid, deviceid, revisionid);
1920 rtlhal->interfaceindex = 0;
1921 }
1922 }
1923
1924 switch (rtlhal->hw_type) {
1925 case HARDWARE_TYPE_RTL8192EE:
1926 case HARDWARE_TYPE_RTL8822BE:
1927 /* use new trx flow */
1928 rtlpriv->use_new_trx_flow = true;
1929 break;
1930
1931 default:
1932 rtlpriv->use_new_trx_flow = false;
1933 break;
1934 }
1935
1936 /*find bus info */
1937 pcipriv->ndis_adapter.busnumber = pdev->bus->number;
1938 pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn);
1939 pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn);
1940
1941 /*find bridge info */
1942 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
1943 /* some ARM have no bridge_pdev and will crash here
1944 * so we should check if bridge_pdev is NULL
1945 */
1946 if (bridge_pdev) {
1947 /*find bridge info if available */
1948 for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) {
1949 if (bridge_pdev->vendor == pcibridge_vendors[tmp]) {
1950 pcipriv->ndis_adapter.pcibridge_vendor = tmp;
1951 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1952 "Pci Bridge Vendor is found index: %d\n",
1953 tmp);
1954 break;
1955 }
1956 }
1957 }
1958
1959 if (pcipriv->ndis_adapter.pcibridge_vendor !=
1960 PCI_BRIDGE_VENDOR_UNKNOWN) {
1961 pcipriv->ndis_adapter.pcibridge_busnum =
1962 bridge_pdev->bus->number;
1963 pcipriv->ndis_adapter.pcibridge_devnum =
1964 PCI_SLOT(bridge_pdev->devfn);
1965 pcipriv->ndis_adapter.pcibridge_funcnum =
1966 PCI_FUNC(bridge_pdev->devfn);
1967
1968 if (pcipriv->ndis_adapter.pcibridge_vendor ==
1969 PCI_BRIDGE_VENDOR_AMD) {
1970 pcipriv->ndis_adapter.amd_l1_patch =
1971 rtl_pci_get_amd_l1_patch(hw);
1972 }
1973 }
1974
1975 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1976 "pcidev busnumber:devnumber:funcnumber:vendor:link_ctl %d:%d:%d:%x:%x\n",
1977 pcipriv->ndis_adapter.busnumber,
1978 pcipriv->ndis_adapter.devnumber,
1979 pcipriv->ndis_adapter.funcnumber,
1980 pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg);
1981
1982 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1983 "pci_bridge busnumber:devnumber:funcnumber:vendor:amd %d:%d:%d:%x:%x\n",
1984 pcipriv->ndis_adapter.pcibridge_busnum,
1985 pcipriv->ndis_adapter.pcibridge_devnum,
1986 pcipriv->ndis_adapter.pcibridge_funcnum,
1987 pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor],
1988 pcipriv->ndis_adapter.amd_l1_patch);
1989
1990 rtl_pci_parse_configuration(pdev, hw);
1991
1992 return true;
1993 }
1994
rtl_pci_intr_mode_msi(struct ieee80211_hw * hw)1995 static int rtl_pci_intr_mode_msi(struct ieee80211_hw *hw)
1996 {
1997 struct rtl_priv *rtlpriv = rtl_priv(hw);
1998 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1999 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2000 int ret;
2001
2002 ret = pci_enable_msi(rtlpci->pdev);
2003 if (ret < 0)
2004 return ret;
2005
2006 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
2007 IRQF_SHARED, KBUILD_MODNAME, hw);
2008 if (ret < 0) {
2009 pci_disable_msi(rtlpci->pdev);
2010 return ret;
2011 }
2012
2013 rtlpci->using_msi = true;
2014
2015 rtl_dbg(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG,
2016 "MSI Interrupt Mode!\n");
2017 return 0;
2018 }
2019
rtl_pci_intr_mode_legacy(struct ieee80211_hw * hw)2020 static int rtl_pci_intr_mode_legacy(struct ieee80211_hw *hw)
2021 {
2022 struct rtl_priv *rtlpriv = rtl_priv(hw);
2023 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2024 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2025 int ret;
2026
2027 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
2028 IRQF_SHARED, KBUILD_MODNAME, hw);
2029 if (ret < 0)
2030 return ret;
2031
2032 rtlpci->using_msi = false;
2033 rtl_dbg(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG,
2034 "Pin-based Interrupt Mode!\n");
2035 return 0;
2036 }
2037
rtl_pci_intr_mode_decide(struct ieee80211_hw * hw)2038 static int rtl_pci_intr_mode_decide(struct ieee80211_hw *hw)
2039 {
2040 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2041 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2042 int ret;
2043
2044 if (rtlpci->msi_support) {
2045 ret = rtl_pci_intr_mode_msi(hw);
2046 if (ret < 0)
2047 ret = rtl_pci_intr_mode_legacy(hw);
2048 } else {
2049 ret = rtl_pci_intr_mode_legacy(hw);
2050 }
2051 return ret;
2052 }
2053
platform_enable_dma64(struct pci_dev * pdev,bool dma64)2054 static void platform_enable_dma64(struct pci_dev *pdev, bool dma64)
2055 {
2056 u8 value;
2057
2058 pci_read_config_byte(pdev, 0x719, &value);
2059
2060 /* 0x719 Bit5 is DMA64 bit fetch. */
2061 if (dma64)
2062 value |= BIT(5);
2063 else
2064 value &= ~BIT(5);
2065
2066 pci_write_config_byte(pdev, 0x719, value);
2067 }
2068
rtl_pci_probe(struct pci_dev * pdev,const struct pci_device_id * id)2069 int rtl_pci_probe(struct pci_dev *pdev,
2070 const struct pci_device_id *id)
2071 {
2072 struct ieee80211_hw *hw = NULL;
2073
2074 struct rtl_priv *rtlpriv = NULL;
2075 struct rtl_pci_priv *pcipriv = NULL;
2076 struct rtl_pci *rtlpci;
2077 unsigned long pmem_start, pmem_len, pmem_flags;
2078 int err;
2079
2080 err = pci_enable_device(pdev);
2081 if (err) {
2082 WARN_ONCE(true, "%s : Cannot enable new PCI device\n",
2083 pci_name(pdev));
2084 return err;
2085 }
2086
2087 if (((struct rtl_hal_cfg *)id->driver_data)->mod_params->dma64 &&
2088 !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
2089 if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
2090 WARN_ONCE(true,
2091 "Unable to obtain 64bit DMA for consistent allocations\n");
2092 err = -ENOMEM;
2093 goto fail1;
2094 }
2095
2096 platform_enable_dma64(pdev, true);
2097 } else if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
2098 if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32))) {
2099 WARN_ONCE(true,
2100 "rtlwifi: Unable to obtain 32bit DMA for consistent allocations\n");
2101 err = -ENOMEM;
2102 goto fail1;
2103 }
2104
2105 platform_enable_dma64(pdev, false);
2106 }
2107
2108 pci_set_master(pdev);
2109
2110 hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) +
2111 sizeof(struct rtl_priv), &rtl_ops);
2112 if (!hw) {
2113 WARN_ONCE(true,
2114 "%s : ieee80211 alloc failed\n", pci_name(pdev));
2115 err = -ENOMEM;
2116 goto fail1;
2117 }
2118
2119 SET_IEEE80211_DEV(hw, &pdev->dev);
2120 pci_set_drvdata(pdev, hw);
2121
2122 rtlpriv = hw->priv;
2123 rtlpriv->hw = hw;
2124 pcipriv = (void *)rtlpriv->priv;
2125 pcipriv->dev.pdev = pdev;
2126 init_completion(&rtlpriv->firmware_loading_complete);
2127 /*proximity init here*/
2128 rtlpriv->proximity.proxim_on = false;
2129
2130 pcipriv = (void *)rtlpriv->priv;
2131 pcipriv->dev.pdev = pdev;
2132
2133 /* init cfg & intf_ops */
2134 rtlpriv->rtlhal.interface = INTF_PCI;
2135 rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data);
2136 rtlpriv->intf_ops = &rtl_pci_ops;
2137 rtl_efuse_ops_init(hw);
2138
2139 /* MEM map */
2140 err = pci_request_regions(pdev, KBUILD_MODNAME);
2141 if (err) {
2142 WARN_ONCE(true, "rtlwifi: Can't obtain PCI resources\n");
2143 goto fail1;
2144 }
2145
2146 pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id);
2147 pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id);
2148 pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id);
2149
2150 /*shared mem start */
2151 rtlpriv->io.pci_mem_start =
2152 (unsigned long)pci_iomap(pdev,
2153 rtlpriv->cfg->bar_id, pmem_len);
2154 if (rtlpriv->io.pci_mem_start == 0) {
2155 WARN_ONCE(true, "rtlwifi: Can't map PCI mem\n");
2156 err = -ENOMEM;
2157 goto fail2;
2158 }
2159
2160 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2161 "mem mapped space: start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n",
2162 pmem_start, pmem_len, pmem_flags,
2163 rtlpriv->io.pci_mem_start);
2164
2165 /* Disable Clk Request */
2166 pci_write_config_byte(pdev, 0x81, 0);
2167 /* leave D3 mode */
2168 pci_write_config_byte(pdev, 0x44, 0);
2169 pci_write_config_byte(pdev, 0x04, 0x06);
2170 pci_write_config_byte(pdev, 0x04, 0x07);
2171
2172 /* find adapter */
2173 if (!_rtl_pci_find_adapter(pdev, hw)) {
2174 err = -ENODEV;
2175 goto fail2;
2176 }
2177
2178 /* Init IO handler */
2179 _rtl_pci_io_handler_init(&pdev->dev, hw);
2180
2181 /*like read eeprom and so on */
2182 rtlpriv->cfg->ops->read_eeprom_info(hw);
2183
2184 if (rtlpriv->cfg->ops->init_sw_vars(hw)) {
2185 pr_err("Can't init_sw_vars\n");
2186 err = -ENODEV;
2187 goto fail2;
2188 }
2189 rtl_init_sw_leds(hw);
2190
2191 /*aspm */
2192 rtl_pci_init_aspm(hw);
2193
2194 /* Init mac80211 sw */
2195 err = rtl_init_core(hw);
2196 if (err) {
2197 pr_err("Can't allocate sw for mac80211\n");
2198 goto fail3;
2199 }
2200
2201 /* Init PCI sw */
2202 err = rtl_pci_init(hw, pdev);
2203 if (err) {
2204 pr_err("Failed to init PCI\n");
2205 goto fail4;
2206 }
2207
2208 err = ieee80211_register_hw(hw);
2209 if (err) {
2210 pr_err("Can't register mac80211 hw.\n");
2211 err = -ENODEV;
2212 goto fail5;
2213 }
2214 rtlpriv->mac80211.mac80211_registered = 1;
2215
2216 /* add for debug */
2217 rtl_debug_add_one(hw);
2218
2219 /*init rfkill */
2220 rtl_init_rfkill(hw); /* Init PCI sw */
2221
2222 rtlpci = rtl_pcidev(pcipriv);
2223 err = rtl_pci_intr_mode_decide(hw);
2224 if (err) {
2225 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
2226 "%s: failed to register IRQ handler\n",
2227 wiphy_name(hw->wiphy));
2228 goto fail3;
2229 }
2230 rtlpci->irq_alloc = 1;
2231
2232 set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
2233 return 0;
2234
2235 fail5:
2236 rtl_pci_deinit(hw);
2237 fail4:
2238 rtl_deinit_core(hw);
2239 fail3:
2240 wait_for_completion(&rtlpriv->firmware_loading_complete);
2241 rtlpriv->cfg->ops->deinit_sw_vars(hw);
2242
2243 fail2:
2244 if (rtlpriv->io.pci_mem_start != 0)
2245 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
2246
2247 pci_release_regions(pdev);
2248
2249 fail1:
2250 if (hw)
2251 ieee80211_free_hw(hw);
2252 pci_disable_device(pdev);
2253
2254 return err;
2255 }
2256 EXPORT_SYMBOL(rtl_pci_probe);
2257
rtl_pci_disconnect(struct pci_dev * pdev)2258 void rtl_pci_disconnect(struct pci_dev *pdev)
2259 {
2260 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2261 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2262 struct rtl_priv *rtlpriv = rtl_priv(hw);
2263 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2264 struct rtl_mac *rtlmac = rtl_mac(rtlpriv);
2265
2266 /* just in case driver is removed before firmware callback */
2267 wait_for_completion(&rtlpriv->firmware_loading_complete);
2268 clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
2269
2270 /* remove form debug */
2271 rtl_debug_remove_one(hw);
2272
2273 /*ieee80211_unregister_hw will call ops_stop */
2274 if (rtlmac->mac80211_registered == 1) {
2275 ieee80211_unregister_hw(hw);
2276 rtlmac->mac80211_registered = 0;
2277 } else {
2278 rtl_deinit_deferred_work(hw, false);
2279 rtlpriv->intf_ops->adapter_stop(hw);
2280 }
2281 rtlpriv->cfg->ops->disable_interrupt(hw);
2282
2283 /*deinit rfkill */
2284 rtl_deinit_rfkill(hw);
2285
2286 rtl_pci_deinit(hw);
2287 rtl_deinit_core(hw);
2288 rtlpriv->cfg->ops->deinit_sw_vars(hw);
2289
2290 if (rtlpci->irq_alloc) {
2291 free_irq(rtlpci->pdev->irq, hw);
2292 rtlpci->irq_alloc = 0;
2293 }
2294
2295 if (rtlpci->using_msi)
2296 pci_disable_msi(rtlpci->pdev);
2297
2298 if (rtlpriv->io.pci_mem_start != 0) {
2299 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
2300 pci_release_regions(pdev);
2301 }
2302
2303 pci_disable_device(pdev);
2304
2305 rtl_pci_disable_aspm(hw);
2306
2307 pci_set_drvdata(pdev, NULL);
2308
2309 ieee80211_free_hw(hw);
2310 }
2311 EXPORT_SYMBOL(rtl_pci_disconnect);
2312
2313 #ifdef CONFIG_PM_SLEEP
2314 /***************************************
2315 * kernel pci power state define:
2316 * PCI_D0 ((pci_power_t __force) 0)
2317 * PCI_D1 ((pci_power_t __force) 1)
2318 * PCI_D2 ((pci_power_t __force) 2)
2319 * PCI_D3hot ((pci_power_t __force) 3)
2320 * PCI_D3cold ((pci_power_t __force) 4)
2321 * PCI_UNKNOWN ((pci_power_t __force) 5)
2322
2323 * This function is called when system
2324 * goes into suspend state mac80211 will
2325 * call rtl_mac_stop() from the mac80211
2326 * suspend function first, So there is
2327 * no need to call hw_disable here.
2328 ****************************************/
rtl_pci_suspend(struct device * dev)2329 int rtl_pci_suspend(struct device *dev)
2330 {
2331 struct ieee80211_hw *hw = dev_get_drvdata(dev);
2332 struct rtl_priv *rtlpriv = rtl_priv(hw);
2333
2334 rtlpriv->cfg->ops->hw_suspend(hw);
2335 rtl_deinit_rfkill(hw);
2336
2337 return 0;
2338 }
2339 EXPORT_SYMBOL(rtl_pci_suspend);
2340
rtl_pci_resume(struct device * dev)2341 int rtl_pci_resume(struct device *dev)
2342 {
2343 struct ieee80211_hw *hw = dev_get_drvdata(dev);
2344 struct rtl_priv *rtlpriv = rtl_priv(hw);
2345
2346 rtlpriv->cfg->ops->hw_resume(hw);
2347 rtl_init_rfkill(hw);
2348 return 0;
2349 }
2350 EXPORT_SYMBOL(rtl_pci_resume);
2351 #endif /* CONFIG_PM_SLEEP */
2352
2353 const struct rtl_intf_ops rtl_pci_ops = {
2354 .adapter_start = rtl_pci_start,
2355 .adapter_stop = rtl_pci_stop,
2356 .adapter_tx = rtl_pci_tx,
2357 .flush = rtl_pci_flush,
2358 .reset_trx_ring = rtl_pci_reset_trx_ring,
2359 .waitq_insert = rtl_pci_tx_chk_waitq_insert,
2360
2361 .disable_aspm = rtl_pci_disable_aspm,
2362 .enable_aspm = rtl_pci_enable_aspm,
2363 };
2364