1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2014 Realtek Corporation.*/
3
4 #include "../wifi.h"
5 #include "../base.h"
6 #include "../pci.h"
7 #include "../core.h"
8 #include "reg.h"
9 #include "def.h"
10 #include "phy.h"
11 #include "dm.h"
12 #include "fw.h"
13 #include "trx.h"
14
rtl92ee_dm_false_alarm_counter_statistics(struct ieee80211_hw * hw)15 static void rtl92ee_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
16 {
17 u32 ret_value;
18 struct rtl_priv *rtlpriv = rtl_priv(hw);
19 struct false_alarm_statistics *falsealm_cnt = &rtlpriv->falsealm_cnt;
20
21 rtl_set_bbreg(hw, DM_REG_OFDM_FA_HOLDC_11N, BIT(31), 1);
22 rtl_set_bbreg(hw, DM_REG_OFDM_FA_RSTD_11N, BIT(31), 1);
23
24 ret_value = rtl_get_bbreg(hw, DM_REG_OFDM_FA_TYPE1_11N, MASKDWORD);
25 falsealm_cnt->cnt_fast_fsync_fail = (ret_value & 0xffff);
26 falsealm_cnt->cnt_sb_search_fail = ((ret_value & 0xffff0000) >> 16);
27
28 ret_value = rtl_get_bbreg(hw, DM_REG_OFDM_FA_TYPE2_11N, MASKDWORD);
29 falsealm_cnt->cnt_ofdm_cca = (ret_value & 0xffff);
30 falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16);
31
32 ret_value = rtl_get_bbreg(hw, DM_REG_OFDM_FA_TYPE3_11N, MASKDWORD);
33 falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff);
34 falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16);
35
36 ret_value = rtl_get_bbreg(hw, DM_REG_OFDM_FA_TYPE4_11N, MASKDWORD);
37 falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff);
38
39 falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail +
40 falsealm_cnt->cnt_rate_illegal +
41 falsealm_cnt->cnt_crc8_fail +
42 falsealm_cnt->cnt_mcs_fail +
43 falsealm_cnt->cnt_fast_fsync_fail +
44 falsealm_cnt->cnt_sb_search_fail;
45
46 ret_value = rtl_get_bbreg(hw, DM_REG_SC_CNT_11N, MASKDWORD);
47 falsealm_cnt->cnt_bw_lsc = (ret_value & 0xffff);
48 falsealm_cnt->cnt_bw_usc = ((ret_value & 0xffff0000) >> 16);
49
50 rtl_set_bbreg(hw, DM_REG_CCK_FA_RST_11N, BIT(12), 1);
51 rtl_set_bbreg(hw, DM_REG_CCK_FA_RST_11N, BIT(14), 1);
52
53 ret_value = rtl_get_bbreg(hw, DM_REG_CCK_FA_LSB_11N, MASKBYTE0);
54 falsealm_cnt->cnt_cck_fail = ret_value;
55
56 ret_value = rtl_get_bbreg(hw, DM_REG_CCK_FA_MSB_11N, MASKBYTE3);
57 falsealm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8;
58
59 ret_value = rtl_get_bbreg(hw, DM_REG_CCK_CCA_CNT_11N, MASKDWORD);
60 falsealm_cnt->cnt_cck_cca = ((ret_value & 0xff) << 8) |
61 ((ret_value & 0xFF00) >> 8);
62
63 falsealm_cnt->cnt_all = falsealm_cnt->cnt_fast_fsync_fail +
64 falsealm_cnt->cnt_sb_search_fail +
65 falsealm_cnt->cnt_parity_fail +
66 falsealm_cnt->cnt_rate_illegal +
67 falsealm_cnt->cnt_crc8_fail +
68 falsealm_cnt->cnt_mcs_fail +
69 falsealm_cnt->cnt_cck_fail;
70
71 falsealm_cnt->cnt_cca_all = falsealm_cnt->cnt_ofdm_cca +
72 falsealm_cnt->cnt_cck_cca;
73
74 /*reset false alarm counter registers*/
75 rtl_set_bbreg(hw, DM_REG_OFDM_FA_RSTC_11N, BIT(31), 1);
76 rtl_set_bbreg(hw, DM_REG_OFDM_FA_RSTC_11N, BIT(31), 0);
77 rtl_set_bbreg(hw, DM_REG_OFDM_FA_RSTD_11N, BIT(27), 1);
78 rtl_set_bbreg(hw, DM_REG_OFDM_FA_RSTD_11N, BIT(27), 0);
79 /*update ofdm counter*/
80 rtl_set_bbreg(hw, DM_REG_OFDM_FA_HOLDC_11N, BIT(31), 0);
81 rtl_set_bbreg(hw, DM_REG_OFDM_FA_RSTD_11N, BIT(31), 0);
82 /*reset CCK CCA counter*/
83 rtl_set_bbreg(hw, DM_REG_CCK_FA_RST_11N, BIT(13) | BIT(12), 0);
84 rtl_set_bbreg(hw, DM_REG_CCK_FA_RST_11N, BIT(13) | BIT(12), 2);
85 /*reset CCK FA counter*/
86 rtl_set_bbreg(hw, DM_REG_CCK_FA_RST_11N, BIT(15) | BIT(14), 0);
87 rtl_set_bbreg(hw, DM_REG_CCK_FA_RST_11N, BIT(15) | BIT(14), 2);
88
89 rtl_dbg(rtlpriv, COMP_DIG, DBG_TRACE,
90 "cnt_parity_fail = %d, cnt_rate_illegal = %d, cnt_crc8_fail = %d, cnt_mcs_fail = %d\n",
91 falsealm_cnt->cnt_parity_fail,
92 falsealm_cnt->cnt_rate_illegal,
93 falsealm_cnt->cnt_crc8_fail, falsealm_cnt->cnt_mcs_fail);
94
95 rtl_dbg(rtlpriv, COMP_DIG, DBG_TRACE,
96 "cnt_ofdm_fail = %x, cnt_cck_fail = %x, cnt_all = %x\n",
97 falsealm_cnt->cnt_ofdm_fail,
98 falsealm_cnt->cnt_cck_fail, falsealm_cnt->cnt_all);
99 }
100
rtl92ee_dm_cck_packet_detection_thresh(struct ieee80211_hw * hw)101 static void rtl92ee_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw)
102 {
103 struct rtl_priv *rtlpriv = rtl_priv(hw);
104 struct dig_t *dm_dig = &rtlpriv->dm_digtable;
105 u8 cur_cck_cca_thresh;
106
107 if (rtlpriv->mac80211.link_state >= MAC80211_LINKED) {
108 if (dm_dig->rssi_val_min > 25) {
109 cur_cck_cca_thresh = 0xcd;
110 } else if ((dm_dig->rssi_val_min <= 25) &&
111 (dm_dig->rssi_val_min > 10)) {
112 cur_cck_cca_thresh = 0x83;
113 } else {
114 if (rtlpriv->falsealm_cnt.cnt_cck_fail > 1000)
115 cur_cck_cca_thresh = 0x83;
116 else
117 cur_cck_cca_thresh = 0x40;
118 }
119 } else {
120 if (rtlpriv->falsealm_cnt.cnt_cck_fail > 1000)
121 cur_cck_cca_thresh = 0x83;
122 else
123 cur_cck_cca_thresh = 0x40;
124 }
125 rtl92ee_dm_write_cck_cca_thres(hw, cur_cck_cca_thresh);
126 }
127
rtl92ee_dm_dig(struct ieee80211_hw * hw)128 static void rtl92ee_dm_dig(struct ieee80211_hw *hw)
129 {
130 struct rtl_priv *rtlpriv = rtl_priv(hw);
131 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
132 struct dig_t *dm_dig = &rtlpriv->dm_digtable;
133 u8 dig_min_0, dig_maxofmin;
134 bool bfirstconnect , bfirstdisconnect;
135 u8 dm_dig_max, dm_dig_min;
136 u8 current_igi = dm_dig->cur_igvalue;
137 u8 offset;
138
139 /* AP,BT */
140 if (mac->act_scanning)
141 return;
142
143 dig_min_0 = dm_dig->dig_min_0;
144 bfirstconnect = (mac->link_state >= MAC80211_LINKED) &&
145 !dm_dig->media_connect_0;
146 bfirstdisconnect = (mac->link_state < MAC80211_LINKED) &&
147 dm_dig->media_connect_0;
148
149 dm_dig_max = 0x5a;
150 dm_dig_min = DM_DIG_MIN;
151 dig_maxofmin = DM_DIG_MAX_AP;
152
153 if (mac->link_state >= MAC80211_LINKED) {
154 if ((dm_dig->rssi_val_min + 10) > dm_dig_max)
155 dm_dig->rx_gain_max = dm_dig_max;
156 else if ((dm_dig->rssi_val_min + 10) < dm_dig_min)
157 dm_dig->rx_gain_max = dm_dig_min;
158 else
159 dm_dig->rx_gain_max = dm_dig->rssi_val_min + 10;
160
161 if (rtlpriv->dm.one_entry_only) {
162 offset = 0;
163 if (dm_dig->rssi_val_min - offset < dm_dig_min)
164 dig_min_0 = dm_dig_min;
165 else if (dm_dig->rssi_val_min - offset >
166 dig_maxofmin)
167 dig_min_0 = dig_maxofmin;
168 else
169 dig_min_0 = dm_dig->rssi_val_min - offset;
170 } else {
171 dig_min_0 = dm_dig_min;
172 }
173
174 } else {
175 dm_dig->rx_gain_max = dm_dig_max;
176 dig_min_0 = dm_dig_min;
177 rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "no link\n");
178 }
179
180 if (rtlpriv->falsealm_cnt.cnt_all > 10000) {
181 if (dm_dig->large_fa_hit != 3)
182 dm_dig->large_fa_hit++;
183 if (dm_dig->forbidden_igi < current_igi) {
184 dm_dig->forbidden_igi = current_igi;
185 dm_dig->large_fa_hit = 1;
186 }
187
188 if (dm_dig->large_fa_hit >= 3) {
189 if (dm_dig->forbidden_igi + 1 > dm_dig->rx_gain_max)
190 dm_dig->rx_gain_min =
191 dm_dig->rx_gain_max;
192 else
193 dm_dig->rx_gain_min =
194 dm_dig->forbidden_igi + 1;
195 dm_dig->recover_cnt = 3600;
196 }
197 } else {
198 if (dm_dig->recover_cnt != 0) {
199 dm_dig->recover_cnt--;
200 } else {
201 if (dm_dig->large_fa_hit < 3) {
202 if ((dm_dig->forbidden_igi - 1) <
203 dig_min_0) {
204 dm_dig->forbidden_igi = dig_min_0;
205 dm_dig->rx_gain_min =
206 dig_min_0;
207 } else {
208 dm_dig->forbidden_igi--;
209 dm_dig->rx_gain_min =
210 dm_dig->forbidden_igi + 1;
211 }
212 } else {
213 dm_dig->large_fa_hit = 0;
214 }
215 }
216 }
217
218 if (rtlpriv->dm.dbginfo.num_qry_beacon_pkt < 5)
219 dm_dig->rx_gain_min = dm_dig_min;
220
221 if (dm_dig->rx_gain_min > dm_dig->rx_gain_max)
222 dm_dig->rx_gain_min = dm_dig->rx_gain_max;
223
224 if (mac->link_state >= MAC80211_LINKED) {
225 if (bfirstconnect) {
226 if (dm_dig->rssi_val_min <= dig_maxofmin)
227 current_igi = dm_dig->rssi_val_min;
228 else
229 current_igi = dig_maxofmin;
230
231 dm_dig->large_fa_hit = 0;
232 } else {
233 if (rtlpriv->falsealm_cnt.cnt_all > DM_DIG_FA_TH2)
234 current_igi += 4;
235 else if (rtlpriv->falsealm_cnt.cnt_all > DM_DIG_FA_TH1)
236 current_igi += 2;
237 else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH0)
238 current_igi -= 2;
239
240 if (rtlpriv->dm.dbginfo.num_qry_beacon_pkt < 5 &&
241 rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH1)
242 current_igi = dm_dig->rx_gain_min;
243 }
244 } else {
245 if (bfirstdisconnect) {
246 current_igi = dm_dig->rx_gain_min;
247 } else {
248 if (rtlpriv->falsealm_cnt.cnt_all > 10000)
249 current_igi += 4;
250 else if (rtlpriv->falsealm_cnt.cnt_all > 8000)
251 current_igi += 2;
252 else if (rtlpriv->falsealm_cnt.cnt_all < 500)
253 current_igi -= 2;
254 }
255 }
256
257 if (current_igi > dm_dig->rx_gain_max)
258 current_igi = dm_dig->rx_gain_max;
259 if (current_igi < dm_dig->rx_gain_min)
260 current_igi = dm_dig->rx_gain_min;
261
262 rtl92ee_dm_write_dig(hw , current_igi);
263 dm_dig->media_connect_0 = ((mac->link_state >= MAC80211_LINKED) ?
264 true : false);
265 dm_dig->dig_min_0 = dig_min_0;
266 }
267
rtl92ee_dm_write_cck_cca_thres(struct ieee80211_hw * hw,u8 cur_thres)268 void rtl92ee_dm_write_cck_cca_thres(struct ieee80211_hw *hw, u8 cur_thres)
269 {
270 struct rtl_priv *rtlpriv = rtl_priv(hw);
271 struct dig_t *dm_dig = &rtlpriv->dm_digtable;
272
273 if (dm_dig->cur_cck_cca_thres != cur_thres)
274 rtl_write_byte(rtlpriv, DM_REG_CCK_CCA_11N, cur_thres);
275
276 dm_dig->pre_cck_cca_thres = dm_dig->cur_cck_cca_thres;
277 dm_dig->cur_cck_cca_thres = cur_thres;
278 }
279
rtl92ee_dm_write_dig(struct ieee80211_hw * hw,u8 current_igi)280 void rtl92ee_dm_write_dig(struct ieee80211_hw *hw, u8 current_igi)
281 {
282 struct rtl_priv *rtlpriv = rtl_priv(hw);
283 struct dig_t *dm_dig = &rtlpriv->dm_digtable;
284
285 if (dm_dig->stop_dig)
286 return;
287
288 if (dm_dig->cur_igvalue != current_igi) {
289 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f, current_igi);
290 if (rtlpriv->phy.rf_type != RF_1T1R)
291 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, 0x7f, current_igi);
292 }
293 dm_dig->pre_igvalue = dm_dig->cur_igvalue;
294 dm_dig->cur_igvalue = current_igi;
295 }
296
rtl92ee_rssi_dump_to_register(struct ieee80211_hw * hw)297 static void rtl92ee_rssi_dump_to_register(struct ieee80211_hw *hw)
298 {
299 struct rtl_priv *rtlpriv = rtl_priv(hw);
300
301 rtl_write_byte(rtlpriv, RA_RSSIDUMP,
302 rtlpriv->stats.rx_rssi_percentage[0]);
303 rtl_write_byte(rtlpriv, RB_RSSIDUMP,
304 rtlpriv->stats.rx_rssi_percentage[1]);
305 /*It seems the following values are not initialized.
306 *According to Windows code,
307 *these value will only be valid with JAGUAR chips
308 */
309 /* Rx EVM */
310 rtl_write_byte(rtlpriv, RS1_RXEVMDUMP, rtlpriv->stats.rx_evm_dbm[0]);
311 rtl_write_byte(rtlpriv, RS2_RXEVMDUMP, rtlpriv->stats.rx_evm_dbm[1]);
312 /* Rx SNR */
313 rtl_write_byte(rtlpriv, RA_RXSNRDUMP,
314 (u8)(rtlpriv->stats.rx_snr_db[0]));
315 rtl_write_byte(rtlpriv, RB_RXSNRDUMP,
316 (u8)(rtlpriv->stats.rx_snr_db[1]));
317 /* Rx Cfo_Short */
318 rtl_write_word(rtlpriv, RA_CFOSHORTDUMP,
319 rtlpriv->stats.rx_cfo_short[0]);
320 rtl_write_word(rtlpriv, RB_CFOSHORTDUMP,
321 rtlpriv->stats.rx_cfo_short[1]);
322 /* Rx Cfo_Tail */
323 rtl_write_word(rtlpriv, RA_CFOLONGDUMP, rtlpriv->stats.rx_cfo_tail[0]);
324 rtl_write_word(rtlpriv, RB_CFOLONGDUMP, rtlpriv->stats.rx_cfo_tail[1]);
325 }
326
rtl92ee_dm_find_minimum_rssi(struct ieee80211_hw * hw)327 static void rtl92ee_dm_find_minimum_rssi(struct ieee80211_hw *hw)
328 {
329 struct rtl_priv *rtlpriv = rtl_priv(hw);
330 struct dig_t *rtl_dm_dig = &rtlpriv->dm_digtable;
331 struct rtl_mac *mac = rtl_mac(rtlpriv);
332
333 /* Determine the minimum RSSI */
334 if ((mac->link_state < MAC80211_LINKED) &&
335 (rtlpriv->dm.entry_min_undec_sm_pwdb == 0)) {
336 rtl_dm_dig->min_undec_pwdb_for_dm = 0;
337 rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD,
338 "Not connected to any\n");
339 }
340 if (mac->link_state >= MAC80211_LINKED) {
341 if (mac->opmode == NL80211_IFTYPE_AP ||
342 mac->opmode == NL80211_IFTYPE_ADHOC) {
343 rtl_dm_dig->min_undec_pwdb_for_dm =
344 rtlpriv->dm.entry_min_undec_sm_pwdb;
345 rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD,
346 "AP Client PWDB = 0x%lx\n",
347 rtlpriv->dm.entry_min_undec_sm_pwdb);
348 } else {
349 rtl_dm_dig->min_undec_pwdb_for_dm =
350 rtlpriv->dm.undec_sm_pwdb;
351 rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD,
352 "STA Default Port PWDB = 0x%x\n",
353 rtl_dm_dig->min_undec_pwdb_for_dm);
354 }
355 } else {
356 rtl_dm_dig->min_undec_pwdb_for_dm =
357 rtlpriv->dm.entry_min_undec_sm_pwdb;
358 rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD,
359 "AP Ext Port or disconnect PWDB = 0x%x\n",
360 rtl_dm_dig->min_undec_pwdb_for_dm);
361 }
362 rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD,
363 "MinUndecoratedPWDBForDM =%d\n",
364 rtl_dm_dig->min_undec_pwdb_for_dm);
365 }
366
rtl92ee_dm_check_rssi_monitor(struct ieee80211_hw * hw)367 static void rtl92ee_dm_check_rssi_monitor(struct ieee80211_hw *hw)
368 {
369 struct rtl_priv *rtlpriv = rtl_priv(hw);
370 struct dig_t *dm_dig = &rtlpriv->dm_digtable;
371 struct rtl_mac *mac = rtl_mac(rtlpriv);
372 struct rtl_dm *dm = rtl_dm(rtlpriv);
373 struct rtl_sta_info *drv_priv;
374 u8 h2c[4] = { 0 };
375 long max = 0, min = 0xff;
376 u8 i = 0;
377
378 if (mac->opmode == NL80211_IFTYPE_AP ||
379 mac->opmode == NL80211_IFTYPE_ADHOC ||
380 mac->opmode == NL80211_IFTYPE_MESH_POINT) {
381 /* AP & ADHOC & MESH */
382 spin_lock_bh(&rtlpriv->locks.entry_list_lock);
383 list_for_each_entry(drv_priv, &rtlpriv->entry_list, list) {
384 struct rssi_sta *stat = &drv_priv->rssi_stat;
385
386 if (stat->undec_sm_pwdb < min)
387 min = stat->undec_sm_pwdb;
388 if (stat->undec_sm_pwdb > max)
389 max = stat->undec_sm_pwdb;
390
391 h2c[3] = 0;
392 h2c[2] = (u8)(dm->undec_sm_pwdb & 0xFF);
393 h2c[1] = 0x20;
394 h2c[0] = ++i;
395 rtl92ee_fill_h2c_cmd(hw, H2C_92E_RSSI_REPORT, 4, h2c);
396 }
397 spin_unlock_bh(&rtlpriv->locks.entry_list_lock);
398
399 /* If associated entry is found */
400 if (max != 0) {
401 dm->entry_max_undec_sm_pwdb = max;
402 RTPRINT(rtlpriv, FDM, DM_PWDB,
403 "EntryMaxPWDB = 0x%lx(%ld)\n", max, max);
404 } else {
405 dm->entry_max_undec_sm_pwdb = 0;
406 }
407 /* If associated entry is found */
408 if (min != 0xff) {
409 dm->entry_min_undec_sm_pwdb = min;
410 RTPRINT(rtlpriv, FDM, DM_PWDB,
411 "EntryMinPWDB = 0x%lx(%ld)\n", min, min);
412 } else {
413 dm->entry_min_undec_sm_pwdb = 0;
414 }
415 }
416
417 /* Indicate Rx signal strength to FW. */
418 if (dm->useramask) {
419 h2c[3] = 0;
420 h2c[2] = (u8)(dm->undec_sm_pwdb & 0xFF);
421 h2c[1] = 0x20;
422 h2c[0] = 0;
423 rtl92ee_fill_h2c_cmd(hw, H2C_92E_RSSI_REPORT, 4, h2c);
424 } else {
425 rtl_write_byte(rtlpriv, 0x4fe, dm->undec_sm_pwdb);
426 }
427 rtl92ee_rssi_dump_to_register(hw);
428 rtl92ee_dm_find_minimum_rssi(hw);
429 dm_dig->rssi_val_min = rtlpriv->dm_digtable.min_undec_pwdb_for_dm;
430 }
431
rtl92ee_dm_init_primary_cca_check(struct ieee80211_hw * hw)432 static void rtl92ee_dm_init_primary_cca_check(struct ieee80211_hw *hw)
433 {
434 struct rtl_priv *rtlpriv = rtl_priv(hw);
435 struct dynamic_primary_cca *primarycca = &rtlpriv->primarycca;
436
437 primarycca->dup_rts_flag = 0;
438 primarycca->intf_flag = 0;
439 primarycca->intf_type = 0;
440 primarycca->monitor_flag = 0;
441 primarycca->ch_offset = 0;
442 primarycca->mf_state = 0;
443 }
444
rtl92ee_dm_is_edca_turbo_disable(struct ieee80211_hw * hw)445 static bool rtl92ee_dm_is_edca_turbo_disable(struct ieee80211_hw *hw)
446 {
447 struct rtl_priv *rtlpriv = rtl_priv(hw);
448
449 if (rtlpriv->mac80211.mode == WIRELESS_MODE_B)
450 return true;
451
452 return false;
453 }
454
rtl92ee_dm_init_edca_turbo(struct ieee80211_hw * hw)455 void rtl92ee_dm_init_edca_turbo(struct ieee80211_hw *hw)
456 {
457 struct rtl_priv *rtlpriv = rtl_priv(hw);
458
459 rtlpriv->dm.current_turbo_edca = false;
460 rtlpriv->dm.is_cur_rdlstate = false;
461 rtlpriv->dm.is_any_nonbepkts = false;
462 }
463
rtl92ee_dm_check_edca_turbo(struct ieee80211_hw * hw)464 static void rtl92ee_dm_check_edca_turbo(struct ieee80211_hw *hw)
465 {
466 struct rtl_priv *rtlpriv = rtl_priv(hw);
467
468 static u64 last_txok_cnt;
469 static u64 last_rxok_cnt;
470 u64 cur_txok_cnt = 0;
471 u64 cur_rxok_cnt = 0;
472 u32 edca_be_ul = 0x5ea42b;
473 u32 edca_be_dl = 0x5ea42b; /*not sure*/
474 u32 edca_be = 0x5ea42b;
475 bool is_cur_rdlstate;
476 bool b_edca_turbo_on = false;
477
478 if (rtlpriv->dm.dbginfo.num_non_be_pkt > 0x100)
479 rtlpriv->dm.is_any_nonbepkts = true;
480 rtlpriv->dm.dbginfo.num_non_be_pkt = 0;
481
482 cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt;
483 cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt;
484
485 /*b_bias_on_rx = false;*/
486 b_edca_turbo_on = ((!rtlpriv->dm.is_any_nonbepkts) &&
487 (!rtlpriv->dm.disable_framebursting)) ?
488 true : false;
489
490 if (rtl92ee_dm_is_edca_turbo_disable(hw))
491 goto check_exit;
492
493 if (b_edca_turbo_on) {
494 is_cur_rdlstate = (cur_rxok_cnt > cur_txok_cnt * 4) ?
495 true : false;
496
497 edca_be = is_cur_rdlstate ? edca_be_dl : edca_be_ul;
498 rtl_write_dword(rtlpriv , REG_EDCA_BE_PARAM , edca_be);
499 rtlpriv->dm.is_cur_rdlstate = is_cur_rdlstate;
500 rtlpriv->dm.current_turbo_edca = true;
501 } else {
502 if (rtlpriv->dm.current_turbo_edca) {
503 u8 tmp = AC0_BE;
504
505 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
506 (u8 *)(&tmp));
507 }
508 rtlpriv->dm.current_turbo_edca = false;
509 }
510
511 check_exit:
512 rtlpriv->dm.is_any_nonbepkts = false;
513 last_txok_cnt = rtlpriv->stats.txbytesunicast;
514 last_rxok_cnt = rtlpriv->stats.rxbytesunicast;
515 }
516
rtl92ee_dm_dynamic_edcca(struct ieee80211_hw * hw)517 static void rtl92ee_dm_dynamic_edcca(struct ieee80211_hw *hw)
518 {
519 struct rtl_priv *rtlpriv = rtl_priv(hw);
520 u8 reg_c50 , reg_c58;
521 bool fw_current_in_ps_mode = false;
522
523 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
524 (u8 *)(&fw_current_in_ps_mode));
525 if (fw_current_in_ps_mode)
526 return;
527
528 reg_c50 = rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);
529 reg_c58 = rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);
530
531 if (reg_c50 > 0x28 && reg_c58 > 0x28) {
532 if (!rtlpriv->rtlhal.pre_edcca_enable) {
533 rtl_write_byte(rtlpriv, ROFDM0_ECCATHRESHOLD, 0x03);
534 rtl_write_byte(rtlpriv, ROFDM0_ECCATHRESHOLD + 2, 0x00);
535 rtlpriv->rtlhal.pre_edcca_enable = true;
536 }
537 } else if (reg_c50 < 0x25 && reg_c58 < 0x25) {
538 if (rtlpriv->rtlhal.pre_edcca_enable) {
539 rtl_write_byte(rtlpriv, ROFDM0_ECCATHRESHOLD, 0x7f);
540 rtl_write_byte(rtlpriv, ROFDM0_ECCATHRESHOLD + 2, 0x7f);
541 rtlpriv->rtlhal.pre_edcca_enable = false;
542 }
543 }
544 }
545
rtl92ee_dm_adaptivity(struct ieee80211_hw * hw)546 static void rtl92ee_dm_adaptivity(struct ieee80211_hw *hw)
547 {
548 rtl92ee_dm_dynamic_edcca(hw);
549 }
550
rtl92ee_dm_write_dynamic_cca(struct ieee80211_hw * hw,u8 cur_mf_state)551 static void rtl92ee_dm_write_dynamic_cca(struct ieee80211_hw *hw,
552 u8 cur_mf_state)
553 {
554 struct dynamic_primary_cca *primarycca = &rtl_priv(hw)->primarycca;
555
556 if (primarycca->mf_state != cur_mf_state)
557 rtl_set_bbreg(hw, DM_REG_L1SBD_PD_CH_11N, BIT(8) | BIT(7),
558 cur_mf_state);
559
560 primarycca->mf_state = cur_mf_state;
561 }
562
rtl92ee_dm_dynamic_primary_cca_check(struct ieee80211_hw * hw)563 static void rtl92ee_dm_dynamic_primary_cca_check(struct ieee80211_hw *hw)
564 {
565 struct rtl_priv *rtlpriv = rtl_priv(hw);
566 struct false_alarm_statistics *falsealm_cnt = &rtlpriv->falsealm_cnt;
567 struct dynamic_primary_cca *primarycca = &rtlpriv->primarycca;
568 bool is40mhz = false;
569 u64 ofdm_cca, ofdm_fa, bw_usc_cnt, bw_lsc_cnt;
570 u8 sec_ch_offset;
571 u8 cur_mf_state;
572 static u8 count_down = MONITOR_TIME;
573
574 ofdm_cca = falsealm_cnt->cnt_ofdm_cca;
575 ofdm_fa = falsealm_cnt->cnt_ofdm_fail;
576 bw_usc_cnt = falsealm_cnt->cnt_bw_usc;
577 bw_lsc_cnt = falsealm_cnt->cnt_bw_lsc;
578 is40mhz = rtlpriv->mac80211.bw_40;
579 sec_ch_offset = rtlpriv->mac80211.cur_40_prime_sc;
580 /* NIC: 2: sec is below, 1: sec is above */
581
582 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP) {
583 cur_mf_state = MF_USC_LSC;
584 rtl92ee_dm_write_dynamic_cca(hw, cur_mf_state);
585 return;
586 }
587
588 if (rtlpriv->mac80211.link_state < MAC80211_LINKED)
589 return;
590
591 if (is40mhz)
592 return;
593
594 if (primarycca->pricca_flag == 0) {
595 /* Primary channel is above
596 * NOTE: duplicate CTS can remove this condition
597 */
598 if (sec_ch_offset == 2) {
599 if ((ofdm_cca > OFDMCCA_TH) &&
600 (bw_lsc_cnt > (bw_usc_cnt + BW_IND_BIAS)) &&
601 (ofdm_fa > (ofdm_cca >> 1))) {
602 primarycca->intf_type = 1;
603 primarycca->intf_flag = 1;
604 cur_mf_state = MF_USC;
605 rtl92ee_dm_write_dynamic_cca(hw, cur_mf_state);
606 primarycca->pricca_flag = 1;
607 } else if ((ofdm_cca > OFDMCCA_TH) &&
608 (bw_lsc_cnt > (bw_usc_cnt + BW_IND_BIAS)) &&
609 (ofdm_fa < (ofdm_cca >> 1))) {
610 primarycca->intf_type = 2;
611 primarycca->intf_flag = 1;
612 cur_mf_state = MF_USC;
613 rtl92ee_dm_write_dynamic_cca(hw, cur_mf_state);
614 primarycca->pricca_flag = 1;
615 primarycca->dup_rts_flag = 1;
616 } else {
617 primarycca->intf_type = 0;
618 primarycca->intf_flag = 0;
619 cur_mf_state = MF_USC_LSC;
620 rtl92ee_dm_write_dynamic_cca(hw, cur_mf_state);
621 primarycca->dup_rts_flag = 0;
622 }
623 } else if (sec_ch_offset == 1) {
624 if ((ofdm_cca > OFDMCCA_TH) &&
625 (bw_usc_cnt > (bw_lsc_cnt + BW_IND_BIAS)) &&
626 (ofdm_fa > (ofdm_cca >> 1))) {
627 primarycca->intf_type = 1;
628 primarycca->intf_flag = 1;
629 cur_mf_state = MF_LSC;
630 rtl92ee_dm_write_dynamic_cca(hw, cur_mf_state);
631 primarycca->pricca_flag = 1;
632 } else if ((ofdm_cca > OFDMCCA_TH) &&
633 (bw_usc_cnt > (bw_lsc_cnt + BW_IND_BIAS)) &&
634 (ofdm_fa < (ofdm_cca >> 1))) {
635 primarycca->intf_type = 2;
636 primarycca->intf_flag = 1;
637 cur_mf_state = MF_LSC;
638 rtl92ee_dm_write_dynamic_cca(hw, cur_mf_state);
639 primarycca->pricca_flag = 1;
640 primarycca->dup_rts_flag = 1;
641 } else {
642 primarycca->intf_type = 0;
643 primarycca->intf_flag = 0;
644 cur_mf_state = MF_USC_LSC;
645 rtl92ee_dm_write_dynamic_cca(hw, cur_mf_state);
646 primarycca->dup_rts_flag = 0;
647 }
648 }
649 } else {/* PrimaryCCA->PriCCA_flag==1 */
650 count_down--;
651 if (count_down == 0) {
652 count_down = MONITOR_TIME;
653 primarycca->pricca_flag = 0;
654 cur_mf_state = MF_USC_LSC;
655 /* default */
656 rtl92ee_dm_write_dynamic_cca(hw, cur_mf_state);
657 primarycca->dup_rts_flag = 0;
658 primarycca->intf_type = 0;
659 primarycca->intf_flag = 0;
660 }
661 }
662 }
663
rtl92ee_dm_dynamic_atc_switch(struct ieee80211_hw * hw)664 static void rtl92ee_dm_dynamic_atc_switch(struct ieee80211_hw *hw)
665 {
666 struct rtl_priv *rtlpriv = rtl_priv(hw);
667 struct rtl_dm *rtldm = rtl_dm(rtl_priv(hw));
668 u8 crystal_cap;
669 u32 packet_count;
670 int cfo_khz_a , cfo_khz_b , cfo_ave = 0, adjust_xtal = 0;
671 int cfo_ave_diff;
672
673 if (rtlpriv->mac80211.link_state < MAC80211_LINKED) {
674 if (rtldm->atc_status == ATC_STATUS_OFF) {
675 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(11),
676 ATC_STATUS_ON);
677 rtldm->atc_status = ATC_STATUS_ON;
678 }
679 /* Disable CFO tracking for BT */
680 if (rtlpriv->cfg->ops->get_btc_status()) {
681 if (!rtlpriv->btcoexist.btc_ops->
682 btc_is_bt_disabled(rtlpriv)) {
683 rtl_dbg(rtlpriv, COMP_BT_COEXIST, DBG_LOUD,
684 "odm_DynamicATCSwitch(): Disable CFO tracking for BT!!\n");
685 return;
686 }
687 }
688 /* Reset Crystal Cap */
689 if (rtldm->crystal_cap != rtlpriv->efuse.crystalcap) {
690 rtldm->crystal_cap = rtlpriv->efuse.crystalcap;
691 crystal_cap = rtldm->crystal_cap & 0x3f;
692 rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, 0xFFF000,
693 (crystal_cap | (crystal_cap << 6)));
694 }
695 } else {
696 cfo_khz_a = (int)(rtldm->cfo_tail[0] * 3125) / 1280;
697 cfo_khz_b = (int)(rtldm->cfo_tail[1] * 3125) / 1280;
698 packet_count = rtldm->packet_count;
699
700 if (packet_count == rtldm->packet_count_pre)
701 return;
702
703 rtldm->packet_count_pre = packet_count;
704
705 if (rtlpriv->phy.rf_type == RF_1T1R)
706 cfo_ave = cfo_khz_a;
707 else
708 cfo_ave = (int)(cfo_khz_a + cfo_khz_b) >> 1;
709
710 cfo_ave_diff = (rtldm->cfo_ave_pre >= cfo_ave) ?
711 (rtldm->cfo_ave_pre - cfo_ave) :
712 (cfo_ave - rtldm->cfo_ave_pre);
713
714 if (cfo_ave_diff > 20 && !rtldm->large_cfo_hit) {
715 rtldm->large_cfo_hit = true;
716 return;
717 }
718 rtldm->large_cfo_hit = false;
719
720 rtldm->cfo_ave_pre = cfo_ave;
721
722 if (cfo_ave >= -rtldm->cfo_threshold &&
723 cfo_ave <= rtldm->cfo_threshold && rtldm->is_freeze == 0) {
724 if (rtldm->cfo_threshold == CFO_THRESHOLD_XTAL) {
725 rtldm->cfo_threshold = CFO_THRESHOLD_XTAL + 10;
726 rtldm->is_freeze = 1;
727 } else {
728 rtldm->cfo_threshold = CFO_THRESHOLD_XTAL;
729 }
730 }
731
732 if (cfo_ave > rtldm->cfo_threshold && rtldm->crystal_cap < 0x3f)
733 adjust_xtal = ((cfo_ave - CFO_THRESHOLD_XTAL) >> 2) + 1;
734 else if ((cfo_ave < -rtlpriv->dm.cfo_threshold) &&
735 rtlpriv->dm.crystal_cap > 0)
736 adjust_xtal = ((cfo_ave + CFO_THRESHOLD_XTAL) >> 2) - 1;
737
738 if (adjust_xtal != 0) {
739 rtldm->is_freeze = 0;
740 rtldm->crystal_cap += adjust_xtal;
741
742 if (rtldm->crystal_cap > 0x3f)
743 rtldm->crystal_cap = 0x3f;
744 else if (rtldm->crystal_cap < 0)
745 rtldm->crystal_cap = 0;
746
747 crystal_cap = rtldm->crystal_cap & 0x3f;
748 rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, 0xFFF000,
749 (crystal_cap | (crystal_cap << 6)));
750 }
751
752 if (cfo_ave < CFO_THRESHOLD_ATC &&
753 cfo_ave > -CFO_THRESHOLD_ATC) {
754 if (rtldm->atc_status == ATC_STATUS_ON) {
755 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(11),
756 ATC_STATUS_OFF);
757 rtldm->atc_status = ATC_STATUS_OFF;
758 }
759 } else {
760 if (rtldm->atc_status == ATC_STATUS_OFF) {
761 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(11),
762 ATC_STATUS_ON);
763 rtldm->atc_status = ATC_STATUS_ON;
764 }
765 }
766 }
767 }
768
rtl92ee_dm_init_txpower_tracking(struct ieee80211_hw * hw)769 static void rtl92ee_dm_init_txpower_tracking(struct ieee80211_hw *hw)
770 {
771 struct rtl_priv *rtlpriv = rtl_priv(hw);
772 struct rtl_dm *dm = rtl_dm(rtlpriv);
773 u8 path;
774
775 dm->txpower_tracking = true;
776 dm->default_ofdm_index = 30;
777 dm->default_cck_index = 20;
778
779 dm->swing_idx_cck_base = dm->default_cck_index;
780 dm->cck_index = dm->default_cck_index;
781
782 for (path = RF90_PATH_A; path < MAX_RF_PATH; path++) {
783 dm->swing_idx_ofdm_base[path] = dm->default_ofdm_index;
784 dm->ofdm_index[path] = dm->default_ofdm_index;
785 dm->delta_power_index[path] = 0;
786 dm->delta_power_index_last[path] = 0;
787 dm->power_index_offset[path] = 0;
788 }
789 }
790
rtl92ee_dm_init_rate_adaptive_mask(struct ieee80211_hw * hw)791 void rtl92ee_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw)
792 {
793 struct rtl_priv *rtlpriv = rtl_priv(hw);
794 struct rate_adaptive *p_ra = &rtlpriv->ra;
795
796 p_ra->ratr_state = DM_RATR_STA_INIT;
797 p_ra->pre_ratr_state = DM_RATR_STA_INIT;
798
799 if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER)
800 rtlpriv->dm.useramask = true;
801 else
802 rtlpriv->dm.useramask = false;
803
804 p_ra->ldpc_thres = 35;
805 p_ra->use_ldpc = false;
806 p_ra->high_rssi_thresh_for_ra = 50;
807 p_ra->low_rssi_thresh_for_ra40m = 20;
808 }
809
_rtl92ee_dm_ra_state_check(struct ieee80211_hw * hw,s32 rssi,u8 * ratr_state)810 static bool _rtl92ee_dm_ra_state_check(struct ieee80211_hw *hw,
811 s32 rssi, u8 *ratr_state)
812 {
813 struct rtl_priv *rtlpriv = rtl_priv(hw);
814 struct rate_adaptive *p_ra = &rtlpriv->ra;
815 const u8 go_up_gap = 5;
816 u32 high_rssithresh_for_ra = p_ra->high_rssi_thresh_for_ra;
817 u32 low_rssithresh_for_ra = p_ra->low_rssi_thresh_for_ra40m;
818 u8 state;
819
820 /* Threshold Adjustment:
821 * when RSSI state trends to go up one or two levels,
822 * make sure RSSI is high enough.
823 * Here GoUpGap is added to solve
824 * the boundary's level alternation issue.
825 */
826 switch (*ratr_state) {
827 case DM_RATR_STA_INIT:
828 case DM_RATR_STA_HIGH:
829 break;
830 case DM_RATR_STA_MIDDLE:
831 high_rssithresh_for_ra += go_up_gap;
832 break;
833 case DM_RATR_STA_LOW:
834 high_rssithresh_for_ra += go_up_gap;
835 low_rssithresh_for_ra += go_up_gap;
836 break;
837 default:
838 rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG,
839 "wrong rssi level setting %d !\n", *ratr_state);
840 break;
841 }
842
843 /* Decide RATRState by RSSI. */
844 if (rssi > high_rssithresh_for_ra)
845 state = DM_RATR_STA_HIGH;
846 else if (rssi > low_rssithresh_for_ra)
847 state = DM_RATR_STA_MIDDLE;
848 else
849 state = DM_RATR_STA_LOW;
850
851 if (*ratr_state != state) {
852 *ratr_state = state;
853 return true;
854 }
855
856 return false;
857 }
858
rtl92ee_dm_refresh_rate_adaptive_mask(struct ieee80211_hw * hw)859 static void rtl92ee_dm_refresh_rate_adaptive_mask(struct ieee80211_hw *hw)
860 {
861 struct rtl_priv *rtlpriv = rtl_priv(hw);
862 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
863 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
864 struct rate_adaptive *p_ra = &rtlpriv->ra;
865 struct ieee80211_sta *sta = NULL;
866
867 if (is_hal_stop(rtlhal)) {
868 rtl_dbg(rtlpriv, COMP_RATE, DBG_LOUD,
869 "driver is going to unload\n");
870 return;
871 }
872
873 if (!rtlpriv->dm.useramask) {
874 rtl_dbg(rtlpriv, COMP_RATE, DBG_LOUD,
875 "driver does not control rate adaptive mask\n");
876 return;
877 }
878
879 if (mac->link_state == MAC80211_LINKED &&
880 mac->opmode == NL80211_IFTYPE_STATION) {
881 if (rtlpriv->dm.undec_sm_pwdb < p_ra->ldpc_thres) {
882 p_ra->use_ldpc = true;
883 p_ra->lower_rts_rate = true;
884 } else if (rtlpriv->dm.undec_sm_pwdb >
885 (p_ra->ldpc_thres - 5)) {
886 p_ra->use_ldpc = false;
887 p_ra->lower_rts_rate = false;
888 }
889 if (_rtl92ee_dm_ra_state_check(hw, rtlpriv->dm.undec_sm_pwdb,
890 &p_ra->ratr_state)) {
891 rcu_read_lock();
892 sta = rtl_find_sta(hw, mac->bssid);
893 if (sta)
894 rtlpriv->cfg->ops->update_rate_tbl(hw, sta,
895 p_ra->ratr_state,
896 true);
897 rcu_read_unlock();
898
899 p_ra->pre_ratr_state = p_ra->ratr_state;
900 }
901 }
902 }
903
rtl92ee_dm_init_dynamic_atc_switch(struct ieee80211_hw * hw)904 static void rtl92ee_dm_init_dynamic_atc_switch(struct ieee80211_hw *hw)
905 {
906 struct rtl_priv *rtlpriv = rtl_priv(hw);
907
908 rtlpriv->dm.crystal_cap = rtlpriv->efuse.crystalcap;
909
910 rtlpriv->dm.atc_status = rtl_get_bbreg(hw, ROFDM1_CFOTRACKING, BIT(11));
911 rtlpriv->dm.cfo_threshold = CFO_THRESHOLD_XTAL;
912 }
913
rtl92ee_dm_init(struct ieee80211_hw * hw)914 void rtl92ee_dm_init(struct ieee80211_hw *hw)
915 {
916 struct rtl_priv *rtlpriv = rtl_priv(hw);
917 u32 cur_igvalue = rtl_get_bbreg(hw, DM_REG_IGI_A_11N, DM_BIT_IGI_11N);
918
919 rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER;
920
921 rtl_dm_diginit(hw, cur_igvalue);
922 rtl92ee_dm_init_rate_adaptive_mask(hw);
923 rtl92ee_dm_init_primary_cca_check(hw);
924 rtl92ee_dm_init_edca_turbo(hw);
925 rtl92ee_dm_init_txpower_tracking(hw);
926 rtl92ee_dm_init_dynamic_atc_switch(hw);
927 }
928
rtl92ee_dm_common_info_self_update(struct ieee80211_hw * hw)929 static void rtl92ee_dm_common_info_self_update(struct ieee80211_hw *hw)
930 {
931 struct rtl_priv *rtlpriv = rtl_priv(hw);
932 u8 cnt;
933
934 rtlpriv->dm.one_entry_only = false;
935
936 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_STATION &&
937 rtlpriv->mac80211.link_state >= MAC80211_LINKED) {
938 rtlpriv->dm.one_entry_only = true;
939 return;
940 }
941
942 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP ||
943 rtlpriv->mac80211.opmode == NL80211_IFTYPE_ADHOC ||
944 rtlpriv->mac80211.opmode == NL80211_IFTYPE_MESH_POINT) {
945 spin_lock_bh(&rtlpriv->locks.entry_list_lock);
946 cnt = list_count_nodes(&rtlpriv->entry_list);
947 spin_unlock_bh(&rtlpriv->locks.entry_list_lock);
948
949 if (cnt == 1)
950 rtlpriv->dm.one_entry_only = true;
951 }
952 }
953
rtl92ee_dm_dynamic_arfb_select(struct ieee80211_hw * hw,u8 rate,bool collision_state)954 void rtl92ee_dm_dynamic_arfb_select(struct ieee80211_hw *hw,
955 u8 rate, bool collision_state)
956 {
957 struct rtl_priv *rtlpriv = rtl_priv(hw);
958
959 if (rate >= DESC92C_RATEMCS8 && rate <= DESC92C_RATEMCS12) {
960 if (collision_state == 1) {
961 if (rate == DESC92C_RATEMCS12) {
962 rtl_write_dword(rtlpriv, REG_DARFRC, 0x0);
963 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
964 0x07060501);
965 } else if (rate == DESC92C_RATEMCS11) {
966 rtl_write_dword(rtlpriv, REG_DARFRC, 0x0);
967 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
968 0x07070605);
969 } else if (rate == DESC92C_RATEMCS10) {
970 rtl_write_dword(rtlpriv, REG_DARFRC, 0x0);
971 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
972 0x08080706);
973 } else if (rate == DESC92C_RATEMCS9) {
974 rtl_write_dword(rtlpriv, REG_DARFRC, 0x0);
975 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
976 0x08080707);
977 } else {
978 rtl_write_dword(rtlpriv, REG_DARFRC, 0x0);
979 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
980 0x09090808);
981 }
982 } else { /* collision_state == 0 */
983 if (rate == DESC92C_RATEMCS12) {
984 rtl_write_dword(rtlpriv, REG_DARFRC,
985 0x05010000);
986 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
987 0x09080706);
988 } else if (rate == DESC92C_RATEMCS11) {
989 rtl_write_dword(rtlpriv, REG_DARFRC,
990 0x06050000);
991 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
992 0x09080807);
993 } else if (rate == DESC92C_RATEMCS10) {
994 rtl_write_dword(rtlpriv, REG_DARFRC,
995 0x07060000);
996 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
997 0x0a090908);
998 } else if (rate == DESC92C_RATEMCS9) {
999 rtl_write_dword(rtlpriv, REG_DARFRC,
1000 0x07070000);
1001 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1002 0x0a090808);
1003 } else {
1004 rtl_write_dword(rtlpriv, REG_DARFRC,
1005 0x08080000);
1006 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1007 0x0b0a0909);
1008 }
1009 }
1010 } else { /* MCS13~MCS15, 1SS, G-mode */
1011 if (collision_state == 1) {
1012 if (rate == DESC92C_RATEMCS15) {
1013 rtl_write_dword(rtlpriv, REG_DARFRC,
1014 0x00000000);
1015 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1016 0x05040302);
1017 } else if (rate == DESC92C_RATEMCS14) {
1018 rtl_write_dword(rtlpriv, REG_DARFRC,
1019 0x00000000);
1020 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1021 0x06050302);
1022 } else if (rate == DESC92C_RATEMCS13) {
1023 rtl_write_dword(rtlpriv, REG_DARFRC,
1024 0x00000000);
1025 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1026 0x07060502);
1027 } else {
1028 rtl_write_dword(rtlpriv, REG_DARFRC,
1029 0x00000000);
1030 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1031 0x06050402);
1032 }
1033 } else{ /* collision_state == 0 */
1034 if (rate == DESC92C_RATEMCS15) {
1035 rtl_write_dword(rtlpriv, REG_DARFRC,
1036 0x03020000);
1037 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1038 0x07060504);
1039 } else if (rate == DESC92C_RATEMCS14) {
1040 rtl_write_dword(rtlpriv, REG_DARFRC,
1041 0x03020000);
1042 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1043 0x08070605);
1044 } else if (rate == DESC92C_RATEMCS13) {
1045 rtl_write_dword(rtlpriv, REG_DARFRC,
1046 0x05020000);
1047 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1048 0x09080706);
1049 } else {
1050 rtl_write_dword(rtlpriv, REG_DARFRC,
1051 0x04020000);
1052 rtl_write_dword(rtlpriv, REG_DARFRC + 4,
1053 0x08070605);
1054 }
1055 }
1056 }
1057 }
1058
rtl92ee_dm_watchdog(struct ieee80211_hw * hw)1059 void rtl92ee_dm_watchdog(struct ieee80211_hw *hw)
1060 {
1061 struct rtl_priv *rtlpriv = rtl_priv(hw);
1062 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1063 bool fw_current_inpsmode = false;
1064 bool fw_ps_awake = true;
1065
1066 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
1067 (u8 *)(&fw_current_inpsmode));
1068 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FWLPS_RF_ON,
1069 (u8 *)(&fw_ps_awake));
1070 if (ppsc->p2p_ps_info.p2p_ps_mode)
1071 fw_ps_awake = false;
1072
1073 spin_lock(&rtlpriv->locks.rf_ps_lock);
1074 if ((ppsc->rfpwr_state == ERFON) &&
1075 ((!fw_current_inpsmode) && fw_ps_awake) &&
1076 (!ppsc->rfchange_inprogress)) {
1077 rtl92ee_dm_common_info_self_update(hw);
1078 rtl92ee_dm_false_alarm_counter_statistics(hw);
1079 rtl92ee_dm_check_rssi_monitor(hw);
1080 rtl92ee_dm_dig(hw);
1081 rtl92ee_dm_adaptivity(hw);
1082 rtl92ee_dm_cck_packet_detection_thresh(hw);
1083 rtl92ee_dm_refresh_rate_adaptive_mask(hw);
1084 rtl92ee_dm_check_edca_turbo(hw);
1085 rtl92ee_dm_dynamic_atc_switch(hw);
1086 rtl92ee_dm_dynamic_primary_cca_check(hw);
1087 }
1088 spin_unlock(&rtlpriv->locks.rf_ps_lock);
1089 }
1090