1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * RTL8XXXU mac80211 USB driver
4 *
5 * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com>
6 *
7 * Portions, notably calibration code:
8 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
9 *
10 * This driver was written as a replacement for the vendor provided
11 * rtl8723au driver. As the Realtek 8xxx chips are very similar in
12 * their programming interface, I have started adding support for
13 * additional 8xxx chips like the 8192cu, 8188cus, etc.
14 */
15
16 #include <linux/firmware.h>
17 #include "regs.h"
18 #include "rtl8xxxu.h"
19
20 #define DRIVER_NAME "rtl8xxxu"
21
22 int rtl8xxxu_debug;
23 static bool rtl8xxxu_ht40_2g;
24 static bool rtl8xxxu_dma_aggregation;
25 static int rtl8xxxu_dma_agg_timeout = -1;
26 static int rtl8xxxu_dma_agg_pages = -1;
27
28 MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@gmail.com>");
29 MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver");
30 MODULE_LICENSE("GPL");
31 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_A.bin");
32 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B.bin");
33 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B_NoBT.bin");
34 MODULE_FIRMWARE("rtlwifi/rtl8188eufw.bin");
35 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_A.bin");
36 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_B.bin");
37 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin");
38 MODULE_FIRMWARE("rtlwifi/rtl8192eu_nic.bin");
39 MODULE_FIRMWARE("rtlwifi/rtl8723bu_nic.bin");
40 MODULE_FIRMWARE("rtlwifi/rtl8723bu_bt.bin");
41 MODULE_FIRMWARE("rtlwifi/rtl8188fufw.bin");
42 MODULE_FIRMWARE("rtlwifi/rtl8710bufw_SMIC.bin");
43 MODULE_FIRMWARE("rtlwifi/rtl8710bufw_UMC.bin");
44 MODULE_FIRMWARE("rtlwifi/rtl8192fufw.bin");
45
46 module_param_named(debug, rtl8xxxu_debug, int, 0600);
47 MODULE_PARM_DESC(debug, "Set debug mask");
48 module_param_named(ht40_2g, rtl8xxxu_ht40_2g, bool, 0600);
49 MODULE_PARM_DESC(ht40_2g, "Enable HT40 support on the 2.4GHz band");
50 module_param_named(dma_aggregation, rtl8xxxu_dma_aggregation, bool, 0600);
51 MODULE_PARM_DESC(dma_aggregation, "Enable DMA packet aggregation");
52 module_param_named(dma_agg_timeout, rtl8xxxu_dma_agg_timeout, int, 0600);
53 MODULE_PARM_DESC(dma_agg_timeout, "Set DMA aggregation timeout (range 1-127)");
54 module_param_named(dma_agg_pages, rtl8xxxu_dma_agg_pages, int, 0600);
55 MODULE_PARM_DESC(dma_agg_pages, "Set DMA aggregation pages (range 1-127, 0 to disable)");
56
57 #define USB_VENDOR_ID_REALTEK 0x0bda
58 #define RTL8XXXU_RX_URBS 32
59 #define RTL8XXXU_RX_URB_PENDING_WATER 8
60 #define RTL8XXXU_TX_URBS 64
61 #define RTL8XXXU_TX_URB_LOW_WATER 25
62 #define RTL8XXXU_TX_URB_HIGH_WATER 32
63
64 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
65 struct rtl8xxxu_rx_urb *rx_urb);
66
67 static struct ieee80211_rate rtl8xxxu_rates[] = {
68 { .bitrate = 10, .hw_value = DESC_RATE_1M, .flags = 0 },
69 { .bitrate = 20, .hw_value = DESC_RATE_2M, .flags = 0 },
70 { .bitrate = 55, .hw_value = DESC_RATE_5_5M, .flags = 0 },
71 { .bitrate = 110, .hw_value = DESC_RATE_11M, .flags = 0 },
72 { .bitrate = 60, .hw_value = DESC_RATE_6M, .flags = 0 },
73 { .bitrate = 90, .hw_value = DESC_RATE_9M, .flags = 0 },
74 { .bitrate = 120, .hw_value = DESC_RATE_12M, .flags = 0 },
75 { .bitrate = 180, .hw_value = DESC_RATE_18M, .flags = 0 },
76 { .bitrate = 240, .hw_value = DESC_RATE_24M, .flags = 0 },
77 { .bitrate = 360, .hw_value = DESC_RATE_36M, .flags = 0 },
78 { .bitrate = 480, .hw_value = DESC_RATE_48M, .flags = 0 },
79 { .bitrate = 540, .hw_value = DESC_RATE_54M, .flags = 0 },
80 };
81
82 static struct ieee80211_channel rtl8xxxu_channels_2g[] = {
83 { .band = NL80211_BAND_2GHZ, .center_freq = 2412,
84 .hw_value = 1, .max_power = 30 },
85 { .band = NL80211_BAND_2GHZ, .center_freq = 2417,
86 .hw_value = 2, .max_power = 30 },
87 { .band = NL80211_BAND_2GHZ, .center_freq = 2422,
88 .hw_value = 3, .max_power = 30 },
89 { .band = NL80211_BAND_2GHZ, .center_freq = 2427,
90 .hw_value = 4, .max_power = 30 },
91 { .band = NL80211_BAND_2GHZ, .center_freq = 2432,
92 .hw_value = 5, .max_power = 30 },
93 { .band = NL80211_BAND_2GHZ, .center_freq = 2437,
94 .hw_value = 6, .max_power = 30 },
95 { .band = NL80211_BAND_2GHZ, .center_freq = 2442,
96 .hw_value = 7, .max_power = 30 },
97 { .band = NL80211_BAND_2GHZ, .center_freq = 2447,
98 .hw_value = 8, .max_power = 30 },
99 { .band = NL80211_BAND_2GHZ, .center_freq = 2452,
100 .hw_value = 9, .max_power = 30 },
101 { .band = NL80211_BAND_2GHZ, .center_freq = 2457,
102 .hw_value = 10, .max_power = 30 },
103 { .band = NL80211_BAND_2GHZ, .center_freq = 2462,
104 .hw_value = 11, .max_power = 30 },
105 { .band = NL80211_BAND_2GHZ, .center_freq = 2467,
106 .hw_value = 12, .max_power = 30 },
107 { .band = NL80211_BAND_2GHZ, .center_freq = 2472,
108 .hw_value = 13, .max_power = 30 },
109 { .band = NL80211_BAND_2GHZ, .center_freq = 2484,
110 .hw_value = 14, .max_power = 30 }
111 };
112
113 static struct ieee80211_supported_band rtl8xxxu_supported_band = {
114 .channels = rtl8xxxu_channels_2g,
115 .n_channels = ARRAY_SIZE(rtl8xxxu_channels_2g),
116 .bitrates = rtl8xxxu_rates,
117 .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates),
118 };
119
120 static const struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = {
121 {0x800, 0x80040000}, {0x804, 0x00000003},
122 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
123 {0x810, 0x10001331}, {0x814, 0x020c3d10},
124 {0x818, 0x02200385}, {0x81c, 0x00000000},
125 {0x820, 0x01000100}, {0x824, 0x00390004},
126 {0x828, 0x00000000}, {0x82c, 0x00000000},
127 {0x830, 0x00000000}, {0x834, 0x00000000},
128 {0x838, 0x00000000}, {0x83c, 0x00000000},
129 {0x840, 0x00010000}, {0x844, 0x00000000},
130 {0x848, 0x00000000}, {0x84c, 0x00000000},
131 {0x850, 0x00000000}, {0x854, 0x00000000},
132 {0x858, 0x569a569a}, {0x85c, 0x001b25a4},
133 {0x860, 0x66f60110}, {0x864, 0x061f0130},
134 {0x868, 0x00000000}, {0x86c, 0x32323200},
135 {0x870, 0x07000760}, {0x874, 0x22004000},
136 {0x878, 0x00000808}, {0x87c, 0x00000000},
137 {0x880, 0xc0083070}, {0x884, 0x000004d5},
138 {0x888, 0x00000000}, {0x88c, 0xccc000c0},
139 {0x890, 0x00000800}, {0x894, 0xfffffffe},
140 {0x898, 0x40302010}, {0x89c, 0x00706050},
141 {0x900, 0x00000000}, {0x904, 0x00000023},
142 {0x908, 0x00000000}, {0x90c, 0x81121111},
143 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
144 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
145 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
146 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
147 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
148 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
149 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
150 {0xa78, 0x00000900},
151 {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
152 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
153 {0xc10, 0x08800000}, {0xc14, 0x40000100},
154 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
155 {0xc20, 0x00000000}, {0xc24, 0x00000000},
156 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
157 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
158 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
159 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
160 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
161 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
162 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
163 {0xc60, 0x00000000}, {0xc64, 0x7112848b},
164 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
165 {0xc70, 0x2c7f000d}, {0xc74, 0x018610db},
166 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
167 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
168 {0xc88, 0x40000100}, {0xc8c, 0x20200000},
169 {0xc90, 0x00121820}, {0xc94, 0x00000000},
170 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
171 {0xca0, 0x00000000}, {0xca4, 0x00000080},
172 {0xca8, 0x00000000}, {0xcac, 0x00000000},
173 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
174 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
175 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
176 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
177 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
178 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
179 {0xce0, 0x00222222}, {0xce4, 0x00000000},
180 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
181 {0xd00, 0x00080740}, {0xd04, 0x00020401},
182 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
183 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
184 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
185 {0xd30, 0x00000000}, {0xd34, 0x80608000},
186 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
187 {0xd40, 0x00000000}, {0xd44, 0x00000000},
188 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
189 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
190 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
191 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
192 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
193 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
194 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
195 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
196 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
197 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
198 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
199 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
200 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
201 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
202 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
203 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
204 {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
205 {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0},
206 {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0},
207 {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0},
208 {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0},
209 {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0},
210 {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0},
211 {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0},
212 {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0},
213 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
214 {0xf00, 0x00000300},
215 {0xffff, 0xffffffff},
216 };
217
218 static const struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = {
219 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
220 {0x800, 0x80040002}, {0x804, 0x00000003},
221 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
222 {0x810, 0x10000330}, {0x814, 0x020c3d10},
223 {0x818, 0x02200385}, {0x81c, 0x00000000},
224 {0x820, 0x01000100}, {0x824, 0x00390004},
225 {0x828, 0x01000100}, {0x82c, 0x00390004},
226 {0x830, 0x27272727}, {0x834, 0x27272727},
227 {0x838, 0x27272727}, {0x83c, 0x27272727},
228 {0x840, 0x00010000}, {0x844, 0x00010000},
229 {0x848, 0x27272727}, {0x84c, 0x27272727},
230 {0x850, 0x00000000}, {0x854, 0x00000000},
231 {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4},
232 {0x860, 0x66e60230}, {0x864, 0x061f0130},
233 {0x868, 0x27272727}, {0x86c, 0x2b2b2b27},
234 {0x870, 0x07000700}, {0x874, 0x22184000},
235 {0x878, 0x08080808}, {0x87c, 0x00000000},
236 {0x880, 0xc0083070}, {0x884, 0x000004d5},
237 {0x888, 0x00000000}, {0x88c, 0xcc0000c0},
238 {0x890, 0x00000800}, {0x894, 0xfffffffe},
239 {0x898, 0x40302010}, {0x89c, 0x00706050},
240 {0x900, 0x00000000}, {0x904, 0x00000023},
241 {0x908, 0x00000000}, {0x90c, 0x81121313},
242 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
243 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
244 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
245 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
246 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
247 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
248 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
249 {0xc00, 0x48071d40}, {0xc04, 0x03a05633},
250 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
251 {0xc10, 0x08800000}, {0xc14, 0x40000100},
252 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
253 {0xc20, 0x00000000}, {0xc24, 0x00000000},
254 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
255 {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf},
256 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
257 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
258 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
259 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
260 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
261 {0xc60, 0x00000000}, {0xc64, 0x5116848b},
262 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
263 {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b},
264 {0xc78, 0x0000001f}, {0xc7c, 0x00b99612},
265 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
266 {0xc88, 0x40000100}, {0xc8c, 0xa0e40000},
267 {0xc90, 0x00121820}, {0xc94, 0x00000000},
268 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
269 {0xca0, 0x00000000}, {0xca4, 0x00000080},
270 {0xca8, 0x00000000}, {0xcac, 0x00000000},
271 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
272 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
273 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
274 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
275 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
276 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
277 {0xce0, 0x00222222}, {0xce4, 0x00000000},
278 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
279 {0xd00, 0x00080740}, {0xd04, 0x00020403},
280 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
281 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
282 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
283 {0xd30, 0x00000000}, {0xd34, 0x80608000},
284 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
285 {0xd40, 0x00000000}, {0xd44, 0x00000000},
286 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
287 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
288 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
289 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
290 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
291 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
292 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
293 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
294 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
295 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
296 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
297 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
298 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
299 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
300 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
301 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
302 {0xe5c, 0x28160d05}, {0xe60, 0x00000010},
303 {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4},
304 {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4},
305 {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4},
306 {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4},
307 {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4},
308 {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4},
309 {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4},
310 {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4},
311 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
312 {0xf00, 0x00000300},
313 {0xffff, 0xffffffff},
314 };
315
316 static const struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = {
317 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
318 {0x040, 0x000c0004}, {0x800, 0x80040000},
319 {0x804, 0x00000001}, {0x808, 0x0000fc00},
320 {0x80c, 0x0000000a}, {0x810, 0x10005388},
321 {0x814, 0x020c3d10}, {0x818, 0x02200385},
322 {0x81c, 0x00000000}, {0x820, 0x01000100},
323 {0x824, 0x00390204}, {0x828, 0x00000000},
324 {0x82c, 0x00000000}, {0x830, 0x00000000},
325 {0x834, 0x00000000}, {0x838, 0x00000000},
326 {0x83c, 0x00000000}, {0x840, 0x00010000},
327 {0x844, 0x00000000}, {0x848, 0x00000000},
328 {0x84c, 0x00000000}, {0x850, 0x00000000},
329 {0x854, 0x00000000}, {0x858, 0x569a569a},
330 {0x85c, 0x001b25a4}, {0x860, 0x66e60230},
331 {0x864, 0x061f0130}, {0x868, 0x00000000},
332 {0x86c, 0x20202000}, {0x870, 0x03000300},
333 {0x874, 0x22004000}, {0x878, 0x00000808},
334 {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070},
335 {0x884, 0x000004d5}, {0x888, 0x00000000},
336 {0x88c, 0xccc000c0}, {0x890, 0x00000800},
337 {0x894, 0xfffffffe}, {0x898, 0x40302010},
338 {0x89c, 0x00706050}, {0x900, 0x00000000},
339 {0x904, 0x00000023}, {0x908, 0x00000000},
340 {0x90c, 0x81121111}, {0xa00, 0x00d047c8},
341 {0xa04, 0x80ff000c}, {0xa08, 0x8c838300},
342 {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78},
343 {0xa14, 0x11144028}, {0xa18, 0x00881117},
344 {0xa1c, 0x89140f00}, {0xa20, 0x15160000},
345 {0xa24, 0x070b0f12}, {0xa28, 0x00000104},
346 {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00},
347 {0xa74, 0x00000007}, {0xc00, 0x48071d40},
348 {0xc04, 0x03a05611}, {0xc08, 0x000000e4},
349 {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000},
350 {0xc14, 0x40000100}, {0xc18, 0x08800000},
351 {0xc1c, 0x40000100}, {0xc20, 0x00000000},
352 {0xc24, 0x00000000}, {0xc28, 0x00000000},
353 {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44},
354 {0xc34, 0x469652cf}, {0xc38, 0x49795994},
355 {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f},
356 {0xc44, 0x000100b7}, {0xc48, 0xec020107},
357 {0xc4c, 0x007f037f}, {0xc50, 0x6954342e},
358 {0xc54, 0x43bc0094}, {0xc58, 0x6954342f},
359 {0xc5c, 0x433c0094}, {0xc60, 0x00000000},
360 {0xc64, 0x5116848b}, {0xc68, 0x47c00bff},
361 {0xc6c, 0x00000036}, {0xc70, 0x2c46000d},
362 {0xc74, 0x018610db}, {0xc78, 0x0000001f},
363 {0xc7c, 0x00b91612}, {0xc80, 0x24000090},
364 {0xc84, 0x20f60000}, {0xc88, 0x24000090},
365 {0xc8c, 0x20200000}, {0xc90, 0x00121820},
366 {0xc94, 0x00000000}, {0xc98, 0x00121820},
367 {0xc9c, 0x00007f7f}, {0xca0, 0x00000000},
368 {0xca4, 0x00000080}, {0xca8, 0x00000000},
369 {0xcac, 0x00000000}, {0xcb0, 0x00000000},
370 {0xcb4, 0x00000000}, {0xcb8, 0x00000000},
371 {0xcbc, 0x28000000}, {0xcc0, 0x00000000},
372 {0xcc4, 0x00000000}, {0xcc8, 0x00000000},
373 {0xccc, 0x00000000}, {0xcd0, 0x00000000},
374 {0xcd4, 0x00000000}, {0xcd8, 0x64b22427},
375 {0xcdc, 0x00766932}, {0xce0, 0x00222222},
376 {0xce4, 0x00000000}, {0xce8, 0x37644302},
377 {0xcec, 0x2f97d40c}, {0xd00, 0x00080740},
378 {0xd04, 0x00020401}, {0xd08, 0x0000907f},
379 {0xd0c, 0x20010201}, {0xd10, 0xa0633333},
380 {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b},
381 {0xd2c, 0xcc979975}, {0xd30, 0x00000000},
382 {0xd34, 0x80608000}, {0xd38, 0x00000000},
383 {0xd3c, 0x00027293}, {0xd40, 0x00000000},
384 {0xd44, 0x00000000}, {0xd48, 0x00000000},
385 {0xd4c, 0x00000000}, {0xd50, 0x6437140a},
386 {0xd54, 0x00000000}, {0xd58, 0x00000000},
387 {0xd5c, 0x30032064}, {0xd60, 0x4653de68},
388 {0xd64, 0x04518a3c}, {0xd68, 0x00002101},
389 {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e},
390 {0xd74, 0x322c2220}, {0xd78, 0x000e3c24},
391 {0xe00, 0x24242424}, {0xe04, 0x24242424},
392 {0xe08, 0x03902024}, {0xe10, 0x24242424},
393 {0xe14, 0x24242424}, {0xe18, 0x24242424},
394 {0xe1c, 0x24242424}, {0xe28, 0x00000000},
395 {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f},
396 {0xe38, 0x02140102}, {0xe3c, 0x681604c2},
397 {0xe40, 0x01007c00}, {0xe44, 0x01004800},
398 {0xe48, 0xfb000000}, {0xe4c, 0x000028d1},
399 {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f},
400 {0xe58, 0x02140102}, {0xe5c, 0x28160d05},
401 {0xe60, 0x00000008}, {0xe68, 0x001b25a4},
402 {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0},
403 {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0},
404 {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0},
405 {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0},
406 {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0},
407 {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0},
408 {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0},
409 {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448},
410 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
411 {0xf00, 0x00000300},
412 {0xffff, 0xffffffff},
413 };
414
415 static const struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = {
416 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
417 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
418 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
419 {0xc78, 0x7a060001}, {0xc78, 0x79070001},
420 {0xc78, 0x78080001}, {0xc78, 0x77090001},
421 {0xc78, 0x760a0001}, {0xc78, 0x750b0001},
422 {0xc78, 0x740c0001}, {0xc78, 0x730d0001},
423 {0xc78, 0x720e0001}, {0xc78, 0x710f0001},
424 {0xc78, 0x70100001}, {0xc78, 0x6f110001},
425 {0xc78, 0x6e120001}, {0xc78, 0x6d130001},
426 {0xc78, 0x6c140001}, {0xc78, 0x6b150001},
427 {0xc78, 0x6a160001}, {0xc78, 0x69170001},
428 {0xc78, 0x68180001}, {0xc78, 0x67190001},
429 {0xc78, 0x661a0001}, {0xc78, 0x651b0001},
430 {0xc78, 0x641c0001}, {0xc78, 0x631d0001},
431 {0xc78, 0x621e0001}, {0xc78, 0x611f0001},
432 {0xc78, 0x60200001}, {0xc78, 0x49210001},
433 {0xc78, 0x48220001}, {0xc78, 0x47230001},
434 {0xc78, 0x46240001}, {0xc78, 0x45250001},
435 {0xc78, 0x44260001}, {0xc78, 0x43270001},
436 {0xc78, 0x42280001}, {0xc78, 0x41290001},
437 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
438 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
439 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
440 {0xc78, 0x21300001}, {0xc78, 0x20310001},
441 {0xc78, 0x06320001}, {0xc78, 0x05330001},
442 {0xc78, 0x04340001}, {0xc78, 0x03350001},
443 {0xc78, 0x02360001}, {0xc78, 0x01370001},
444 {0xc78, 0x00380001}, {0xc78, 0x00390001},
445 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
446 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
447 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
448 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
449 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
450 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
451 {0xc78, 0x7a460001}, {0xc78, 0x79470001},
452 {0xc78, 0x78480001}, {0xc78, 0x77490001},
453 {0xc78, 0x764a0001}, {0xc78, 0x754b0001},
454 {0xc78, 0x744c0001}, {0xc78, 0x734d0001},
455 {0xc78, 0x724e0001}, {0xc78, 0x714f0001},
456 {0xc78, 0x70500001}, {0xc78, 0x6f510001},
457 {0xc78, 0x6e520001}, {0xc78, 0x6d530001},
458 {0xc78, 0x6c540001}, {0xc78, 0x6b550001},
459 {0xc78, 0x6a560001}, {0xc78, 0x69570001},
460 {0xc78, 0x68580001}, {0xc78, 0x67590001},
461 {0xc78, 0x665a0001}, {0xc78, 0x655b0001},
462 {0xc78, 0x645c0001}, {0xc78, 0x635d0001},
463 {0xc78, 0x625e0001}, {0xc78, 0x615f0001},
464 {0xc78, 0x60600001}, {0xc78, 0x49610001},
465 {0xc78, 0x48620001}, {0xc78, 0x47630001},
466 {0xc78, 0x46640001}, {0xc78, 0x45650001},
467 {0xc78, 0x44660001}, {0xc78, 0x43670001},
468 {0xc78, 0x42680001}, {0xc78, 0x41690001},
469 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
470 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
471 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
472 {0xc78, 0x21700001}, {0xc78, 0x20710001},
473 {0xc78, 0x06720001}, {0xc78, 0x05730001},
474 {0xc78, 0x04740001}, {0xc78, 0x03750001},
475 {0xc78, 0x02760001}, {0xc78, 0x01770001},
476 {0xc78, 0x00780001}, {0xc78, 0x00790001},
477 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
478 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
479 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
480 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
481 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
482 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
483 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
484 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
485 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
486 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
487 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
488 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
489 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
490 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
491 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
492 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
493 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
494 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
495 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
496 {0xffff, 0xffffffff}
497 };
498
499 static const struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = {
500 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
501 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
502 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
503 {0xc78, 0x7b060001}, {0xc78, 0x7b070001},
504 {0xc78, 0x7b080001}, {0xc78, 0x7a090001},
505 {0xc78, 0x790a0001}, {0xc78, 0x780b0001},
506 {0xc78, 0x770c0001}, {0xc78, 0x760d0001},
507 {0xc78, 0x750e0001}, {0xc78, 0x740f0001},
508 {0xc78, 0x73100001}, {0xc78, 0x72110001},
509 {0xc78, 0x71120001}, {0xc78, 0x70130001},
510 {0xc78, 0x6f140001}, {0xc78, 0x6e150001},
511 {0xc78, 0x6d160001}, {0xc78, 0x6c170001},
512 {0xc78, 0x6b180001}, {0xc78, 0x6a190001},
513 {0xc78, 0x691a0001}, {0xc78, 0x681b0001},
514 {0xc78, 0x671c0001}, {0xc78, 0x661d0001},
515 {0xc78, 0x651e0001}, {0xc78, 0x641f0001},
516 {0xc78, 0x63200001}, {0xc78, 0x62210001},
517 {0xc78, 0x61220001}, {0xc78, 0x60230001},
518 {0xc78, 0x46240001}, {0xc78, 0x45250001},
519 {0xc78, 0x44260001}, {0xc78, 0x43270001},
520 {0xc78, 0x42280001}, {0xc78, 0x41290001},
521 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
522 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
523 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
524 {0xc78, 0x21300001}, {0xc78, 0x20310001},
525 {0xc78, 0x06320001}, {0xc78, 0x05330001},
526 {0xc78, 0x04340001}, {0xc78, 0x03350001},
527 {0xc78, 0x02360001}, {0xc78, 0x01370001},
528 {0xc78, 0x00380001}, {0xc78, 0x00390001},
529 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
530 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
531 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
532 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
533 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
534 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
535 {0xc78, 0x7b460001}, {0xc78, 0x7b470001},
536 {0xc78, 0x7b480001}, {0xc78, 0x7a490001},
537 {0xc78, 0x794a0001}, {0xc78, 0x784b0001},
538 {0xc78, 0x774c0001}, {0xc78, 0x764d0001},
539 {0xc78, 0x754e0001}, {0xc78, 0x744f0001},
540 {0xc78, 0x73500001}, {0xc78, 0x72510001},
541 {0xc78, 0x71520001}, {0xc78, 0x70530001},
542 {0xc78, 0x6f540001}, {0xc78, 0x6e550001},
543 {0xc78, 0x6d560001}, {0xc78, 0x6c570001},
544 {0xc78, 0x6b580001}, {0xc78, 0x6a590001},
545 {0xc78, 0x695a0001}, {0xc78, 0x685b0001},
546 {0xc78, 0x675c0001}, {0xc78, 0x665d0001},
547 {0xc78, 0x655e0001}, {0xc78, 0x645f0001},
548 {0xc78, 0x63600001}, {0xc78, 0x62610001},
549 {0xc78, 0x61620001}, {0xc78, 0x60630001},
550 {0xc78, 0x46640001}, {0xc78, 0x45650001},
551 {0xc78, 0x44660001}, {0xc78, 0x43670001},
552 {0xc78, 0x42680001}, {0xc78, 0x41690001},
553 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
554 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
555 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
556 {0xc78, 0x21700001}, {0xc78, 0x20710001},
557 {0xc78, 0x06720001}, {0xc78, 0x05730001},
558 {0xc78, 0x04740001}, {0xc78, 0x03750001},
559 {0xc78, 0x02760001}, {0xc78, 0x01770001},
560 {0xc78, 0x00780001}, {0xc78, 0x00790001},
561 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
562 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
563 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
564 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
565 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
566 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
567 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
568 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
569 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
570 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
571 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
572 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
573 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
574 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
575 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
576 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
577 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
578 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
579 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
580 {0xffff, 0xffffffff}
581 };
582
583 static const struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = {
584 { /* RF_A */
585 .hssiparm1 = REG_FPGA0_XA_HSSI_PARM1,
586 .hssiparm2 = REG_FPGA0_XA_HSSI_PARM2,
587 .lssiparm = REG_FPGA0_XA_LSSI_PARM,
588 .hspiread = REG_HSPI_XA_READBACK,
589 .lssiread = REG_FPGA0_XA_LSSI_READBACK,
590 .rf_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL,
591 },
592 { /* RF_B */
593 .hssiparm1 = REG_FPGA0_XB_HSSI_PARM1,
594 .hssiparm2 = REG_FPGA0_XB_HSSI_PARM2,
595 .lssiparm = REG_FPGA0_XB_LSSI_PARM,
596 .hspiread = REG_HSPI_XB_READBACK,
597 .lssiread = REG_FPGA0_XB_LSSI_READBACK,
598 .rf_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL,
599 },
600 };
601
602 const u32 rtl8xxxu_iqk_phy_iq_bb_reg[RTL8XXXU_BB_REGS] = {
603 REG_OFDM0_XA_RX_IQ_IMBALANCE,
604 REG_OFDM0_XB_RX_IQ_IMBALANCE,
605 REG_OFDM0_ENERGY_CCA_THRES,
606 REG_OFDM0_AGC_RSSI_TABLE,
607 REG_OFDM0_XA_TX_IQ_IMBALANCE,
608 REG_OFDM0_XB_TX_IQ_IMBALANCE,
609 REG_OFDM0_XC_TX_AFE,
610 REG_OFDM0_XD_TX_AFE,
611 REG_OFDM0_RX_IQ_EXT_ANTA
612 };
613
rtl8xxxu_read8(struct rtl8xxxu_priv * priv,u16 addr)614 u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr)
615 {
616 struct usb_device *udev = priv->udev;
617 int len;
618 u8 data;
619
620 if (priv->rtl_chip == RTL8710B && addr <= 0xff)
621 addr |= 0x8000;
622
623 mutex_lock(&priv->usb_buf_mutex);
624 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
625 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
626 addr, 0, &priv->usb_buf.val8, sizeof(u8),
627 RTW_USB_CONTROL_MSG_TIMEOUT);
628 data = priv->usb_buf.val8;
629 mutex_unlock(&priv->usb_buf_mutex);
630
631 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
632 dev_info(&udev->dev, "%s(%04x) = 0x%02x, len %i\n",
633 __func__, addr, data, len);
634 return data;
635 }
636
rtl8xxxu_read16(struct rtl8xxxu_priv * priv,u16 addr)637 u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr)
638 {
639 struct usb_device *udev = priv->udev;
640 int len;
641 u16 data;
642
643 if (priv->rtl_chip == RTL8710B && addr <= 0xff)
644 addr |= 0x8000;
645
646 mutex_lock(&priv->usb_buf_mutex);
647 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
648 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
649 addr, 0, &priv->usb_buf.val16, sizeof(u16),
650 RTW_USB_CONTROL_MSG_TIMEOUT);
651 data = le16_to_cpu(priv->usb_buf.val16);
652 mutex_unlock(&priv->usb_buf_mutex);
653
654 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
655 dev_info(&udev->dev, "%s(%04x) = 0x%04x, len %i\n",
656 __func__, addr, data, len);
657 return data;
658 }
659
rtl8xxxu_read32(struct rtl8xxxu_priv * priv,u16 addr)660 u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr)
661 {
662 struct usb_device *udev = priv->udev;
663 int len;
664 u32 data;
665
666 if (priv->rtl_chip == RTL8710B && addr <= 0xff)
667 addr |= 0x8000;
668
669 mutex_lock(&priv->usb_buf_mutex);
670 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
671 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
672 addr, 0, &priv->usb_buf.val32, sizeof(u32),
673 RTW_USB_CONTROL_MSG_TIMEOUT);
674 data = le32_to_cpu(priv->usb_buf.val32);
675 mutex_unlock(&priv->usb_buf_mutex);
676
677 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
678 dev_info(&udev->dev, "%s(%04x) = 0x%08x, len %i\n",
679 __func__, addr, data, len);
680 return data;
681 }
682
rtl8xxxu_write8(struct rtl8xxxu_priv * priv,u16 addr,u8 val)683 int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val)
684 {
685 struct usb_device *udev = priv->udev;
686 int ret;
687
688 if (priv->rtl_chip == RTL8710B && addr <= 0xff)
689 addr |= 0x8000;
690
691 mutex_lock(&priv->usb_buf_mutex);
692 priv->usb_buf.val8 = val;
693 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
694 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
695 addr, 0, &priv->usb_buf.val8, sizeof(u8),
696 RTW_USB_CONTROL_MSG_TIMEOUT);
697
698 mutex_unlock(&priv->usb_buf_mutex);
699
700 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
701 dev_info(&udev->dev, "%s(%04x) = 0x%02x\n",
702 __func__, addr, val);
703 return ret;
704 }
705
rtl8xxxu_write16(struct rtl8xxxu_priv * priv,u16 addr,u16 val)706 int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val)
707 {
708 struct usb_device *udev = priv->udev;
709 int ret;
710
711 if (priv->rtl_chip == RTL8710B && addr <= 0xff)
712 addr |= 0x8000;
713
714 mutex_lock(&priv->usb_buf_mutex);
715 priv->usb_buf.val16 = cpu_to_le16(val);
716 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
717 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
718 addr, 0, &priv->usb_buf.val16, sizeof(u16),
719 RTW_USB_CONTROL_MSG_TIMEOUT);
720 mutex_unlock(&priv->usb_buf_mutex);
721
722 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
723 dev_info(&udev->dev, "%s(%04x) = 0x%04x\n",
724 __func__, addr, val);
725 return ret;
726 }
727
rtl8xxxu_write32(struct rtl8xxxu_priv * priv,u16 addr,u32 val)728 int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val)
729 {
730 struct usb_device *udev = priv->udev;
731 int ret;
732
733 if (priv->rtl_chip == RTL8710B && addr <= 0xff)
734 addr |= 0x8000;
735
736 mutex_lock(&priv->usb_buf_mutex);
737 priv->usb_buf.val32 = cpu_to_le32(val);
738 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
739 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
740 addr, 0, &priv->usb_buf.val32, sizeof(u32),
741 RTW_USB_CONTROL_MSG_TIMEOUT);
742 mutex_unlock(&priv->usb_buf_mutex);
743
744 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
745 dev_info(&udev->dev, "%s(%04x) = 0x%08x\n",
746 __func__, addr, val);
747 return ret;
748 }
749
rtl8xxxu_write8_set(struct rtl8xxxu_priv * priv,u16 addr,u8 bits)750 int rtl8xxxu_write8_set(struct rtl8xxxu_priv *priv, u16 addr, u8 bits)
751 {
752 u8 val8;
753
754 val8 = rtl8xxxu_read8(priv, addr);
755 val8 |= bits;
756 return rtl8xxxu_write8(priv, addr, val8);
757 }
758
rtl8xxxu_write8_clear(struct rtl8xxxu_priv * priv,u16 addr,u8 bits)759 int rtl8xxxu_write8_clear(struct rtl8xxxu_priv *priv, u16 addr, u8 bits)
760 {
761 u8 val8;
762
763 val8 = rtl8xxxu_read8(priv, addr);
764 val8 &= ~bits;
765 return rtl8xxxu_write8(priv, addr, val8);
766 }
767
rtl8xxxu_write16_set(struct rtl8xxxu_priv * priv,u16 addr,u16 bits)768 int rtl8xxxu_write16_set(struct rtl8xxxu_priv *priv, u16 addr, u16 bits)
769 {
770 u16 val16;
771
772 val16 = rtl8xxxu_read16(priv, addr);
773 val16 |= bits;
774 return rtl8xxxu_write16(priv, addr, val16);
775 }
776
rtl8xxxu_write16_clear(struct rtl8xxxu_priv * priv,u16 addr,u16 bits)777 int rtl8xxxu_write16_clear(struct rtl8xxxu_priv *priv, u16 addr, u16 bits)
778 {
779 u16 val16;
780
781 val16 = rtl8xxxu_read16(priv, addr);
782 val16 &= ~bits;
783 return rtl8xxxu_write16(priv, addr, val16);
784 }
785
rtl8xxxu_write32_set(struct rtl8xxxu_priv * priv,u16 addr,u32 bits)786 int rtl8xxxu_write32_set(struct rtl8xxxu_priv *priv, u16 addr, u32 bits)
787 {
788 u32 val32;
789
790 val32 = rtl8xxxu_read32(priv, addr);
791 val32 |= bits;
792 return rtl8xxxu_write32(priv, addr, val32);
793 }
794
rtl8xxxu_write32_clear(struct rtl8xxxu_priv * priv,u16 addr,u32 bits)795 int rtl8xxxu_write32_clear(struct rtl8xxxu_priv *priv, u16 addr, u32 bits)
796 {
797 u32 val32;
798
799 val32 = rtl8xxxu_read32(priv, addr);
800 val32 &= ~bits;
801 return rtl8xxxu_write32(priv, addr, val32);
802 }
803
rtl8xxxu_write32_mask(struct rtl8xxxu_priv * priv,u16 addr,u32 mask,u32 val)804 int rtl8xxxu_write32_mask(struct rtl8xxxu_priv *priv, u16 addr,
805 u32 mask, u32 val)
806 {
807 u32 orig, new, shift;
808
809 shift = __ffs(mask);
810
811 orig = rtl8xxxu_read32(priv, addr);
812 new = (orig & ~mask) | ((val << shift) & mask);
813 return rtl8xxxu_write32(priv, addr, new);
814 }
815
rtl8xxxu_write_rfreg_mask(struct rtl8xxxu_priv * priv,enum rtl8xxxu_rfpath path,u8 reg,u32 mask,u32 val)816 int rtl8xxxu_write_rfreg_mask(struct rtl8xxxu_priv *priv,
817 enum rtl8xxxu_rfpath path, u8 reg,
818 u32 mask, u32 val)
819 {
820 u32 orig, new, shift;
821
822 shift = __ffs(mask);
823
824 orig = rtl8xxxu_read_rfreg(priv, path, reg);
825 new = (orig & ~mask) | ((val << shift) & mask);
826 return rtl8xxxu_write_rfreg(priv, path, reg, new);
827 }
828
829 static int
rtl8xxxu_writeN(struct rtl8xxxu_priv * priv,u16 addr,u8 * buf,u16 len)830 rtl8xxxu_writeN(struct rtl8xxxu_priv *priv, u16 addr, u8 *buf, u16 len)
831 {
832 struct usb_device *udev = priv->udev;
833 int blocksize = priv->fops->writeN_block_size;
834 int ret, i, count, remainder;
835
836 count = len / blocksize;
837 remainder = len % blocksize;
838
839 for (i = 0; i < count; i++) {
840 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
841 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
842 addr, 0, buf, blocksize,
843 RTW_USB_CONTROL_MSG_TIMEOUT);
844 if (ret != blocksize)
845 goto write_error;
846
847 addr += blocksize;
848 buf += blocksize;
849 }
850
851 if (remainder) {
852 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
853 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
854 addr, 0, buf, remainder,
855 RTW_USB_CONTROL_MSG_TIMEOUT);
856 if (ret != remainder)
857 goto write_error;
858 }
859
860 return len;
861
862 write_error:
863 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
864 dev_info(&udev->dev,
865 "%s: Failed to write block at addr: %04x size: %04x\n",
866 __func__, addr, blocksize);
867 return -EAGAIN;
868 }
869
rtl8xxxu_read_rfreg(struct rtl8xxxu_priv * priv,enum rtl8xxxu_rfpath path,u8 reg)870 u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv,
871 enum rtl8xxxu_rfpath path, u8 reg)
872 {
873 u32 hssia, val32, retval;
874
875 hssia = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
876 if (path != RF_A)
877 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2);
878 else
879 val32 = hssia;
880
881 val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK;
882 val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT);
883 val32 |= FPGA0_HSSI_PARM2_EDGE_READ;
884 hssia &= ~FPGA0_HSSI_PARM2_EDGE_READ;
885 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
886
887 udelay(10);
888
889 rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32);
890 udelay(100);
891
892 hssia |= FPGA0_HSSI_PARM2_EDGE_READ;
893 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
894 udelay(10);
895
896 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1);
897 if (val32 & FPGA0_HSSI_PARM1_PI)
898 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hspiread);
899 else
900 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].lssiread);
901
902 retval &= 0xfffff;
903
904 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_READ)
905 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
906 __func__, reg, retval);
907 return retval;
908 }
909
910 /*
911 * The RTL8723BU driver indicates that registers 0xb2 and 0xb6 can
912 * have write issues in high temperature conditions. We may have to
913 * retry writing them.
914 */
rtl8xxxu_write_rfreg(struct rtl8xxxu_priv * priv,enum rtl8xxxu_rfpath path,u8 reg,u32 data)915 int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv,
916 enum rtl8xxxu_rfpath path, u8 reg, u32 data)
917 {
918 int ret, retval;
919 u32 dataaddr, val32;
920
921 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_WRITE)
922 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
923 __func__, reg, data);
924
925 data &= FPGA0_LSSI_PARM_DATA_MASK;
926 dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data;
927
928 if (priv->rtl_chip == RTL8192E) {
929 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
930 val32 &= ~0x20000;
931 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
932 }
933
934 /* Use XB for path B */
935 ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr);
936 if (ret != sizeof(dataaddr))
937 retval = -EIO;
938 else
939 retval = 0;
940
941 udelay(1);
942
943 if (priv->rtl_chip == RTL8192E) {
944 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
945 val32 |= 0x20000;
946 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
947 }
948
949 return retval;
950 }
951
952 static int
rtl8xxxu_gen1_h2c_cmd(struct rtl8xxxu_priv * priv,struct h2c_cmd * h2c,int len)953 rtl8xxxu_gen1_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c, int len)
954 {
955 struct device *dev = &priv->udev->dev;
956 int mbox_nr, retry, retval = 0;
957 int mbox_reg, mbox_ext_reg;
958 u8 val8;
959
960 mutex_lock(&priv->h2c_mutex);
961
962 mbox_nr = priv->next_mbox;
963 mbox_reg = REG_HMBOX_0 + (mbox_nr * 4);
964 mbox_ext_reg = REG_HMBOX_EXT_0 + (mbox_nr * 2);
965
966 /*
967 * MBOX ready?
968 */
969 retry = 100;
970 do {
971 val8 = rtl8xxxu_read8(priv, REG_HMTFR);
972 if (!(val8 & BIT(mbox_nr)))
973 break;
974 } while (retry--);
975
976 if (!retry) {
977 dev_info(dev, "%s: Mailbox busy\n", __func__);
978 retval = -EBUSY;
979 goto error;
980 }
981
982 /*
983 * Need to swap as it's being swapped again by rtl8xxxu_write16/32()
984 */
985 if (len > sizeof(u32)) {
986 rtl8xxxu_write16(priv, mbox_ext_reg, le16_to_cpu(h2c->raw.ext));
987 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
988 dev_info(dev, "H2C_EXT %04x\n",
989 le16_to_cpu(h2c->raw.ext));
990 }
991 rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data));
992 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
993 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data));
994
995 priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX;
996
997 error:
998 mutex_unlock(&priv->h2c_mutex);
999 return retval;
1000 }
1001
1002 int
rtl8xxxu_gen2_h2c_cmd(struct rtl8xxxu_priv * priv,struct h2c_cmd * h2c,int len)1003 rtl8xxxu_gen2_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c, int len)
1004 {
1005 struct device *dev = &priv->udev->dev;
1006 int mbox_nr, retry, retval = 0;
1007 int mbox_reg, mbox_ext_reg;
1008 u8 val8;
1009
1010 mutex_lock(&priv->h2c_mutex);
1011
1012 mbox_nr = priv->next_mbox;
1013 mbox_reg = REG_HMBOX_0 + (mbox_nr * 4);
1014 mbox_ext_reg = REG_HMBOX_EXT0_8723B + (mbox_nr * 4);
1015
1016 /*
1017 * MBOX ready?
1018 */
1019 retry = 100;
1020 do {
1021 val8 = rtl8xxxu_read8(priv, REG_HMTFR);
1022 if (!(val8 & BIT(mbox_nr)))
1023 break;
1024 } while (retry--);
1025
1026 if (!retry) {
1027 dev_info(dev, "%s: Mailbox busy\n", __func__);
1028 retval = -EBUSY;
1029 goto error;
1030 }
1031
1032 /*
1033 * Need to swap as it's being swapped again by rtl8xxxu_write16/32()
1034 */
1035 if (len > sizeof(u32)) {
1036 rtl8xxxu_write32(priv, mbox_ext_reg,
1037 le32_to_cpu(h2c->raw_wide.ext));
1038 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1039 dev_info(dev, "H2C_EXT %08x\n",
1040 le32_to_cpu(h2c->raw_wide.ext));
1041 }
1042 rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data));
1043 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1044 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data));
1045
1046 priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX;
1047
1048 error:
1049 mutex_unlock(&priv->h2c_mutex);
1050 return retval;
1051 }
1052
rtl8xxxu_gen1_enable_rf(struct rtl8xxxu_priv * priv)1053 void rtl8xxxu_gen1_enable_rf(struct rtl8xxxu_priv *priv)
1054 {
1055 u8 val8;
1056 u32 val32;
1057
1058 val8 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1059 val8 |= BIT(0) | BIT(3);
1060 rtl8xxxu_write8(priv, REG_SPS0_CTRL, val8);
1061
1062 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1063 val32 &= ~(BIT(4) | BIT(5));
1064 val32 |= BIT(3);
1065 if (priv->rf_paths == 2) {
1066 val32 &= ~(BIT(20) | BIT(21));
1067 val32 |= BIT(19);
1068 }
1069 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1070
1071 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1072 val32 &= ~OFDM_RF_PATH_TX_MASK;
1073 if (priv->tx_paths == 2)
1074 val32 |= OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B;
1075 else if (priv->rtl_chip == RTL8192C || priv->rtl_chip == RTL8191C)
1076 val32 |= OFDM_RF_PATH_TX_B;
1077 else
1078 val32 |= OFDM_RF_PATH_TX_A;
1079 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1080
1081 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1082 val32 &= ~FPGA_RF_MODE_JAPAN;
1083 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1084
1085 if (priv->rf_paths == 2)
1086 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x63db25a0);
1087 else
1088 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x631b25a0);
1089
1090 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x32d95);
1091 if (priv->rf_paths == 2)
1092 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x32d95);
1093
1094 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
1095 }
1096
rtl8xxxu_gen1_disable_rf(struct rtl8xxxu_priv * priv)1097 void rtl8xxxu_gen1_disable_rf(struct rtl8xxxu_priv *priv)
1098 {
1099 u8 sps0;
1100 u32 val32;
1101
1102 sps0 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1103
1104 /* RF RX code for preamble power saving */
1105 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1106 val32 &= ~(BIT(3) | BIT(4) | BIT(5));
1107 if (priv->rf_paths == 2)
1108 val32 &= ~(BIT(19) | BIT(20) | BIT(21));
1109 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1110
1111 /* Disable TX for four paths */
1112 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1113 val32 &= ~OFDM_RF_PATH_TX_MASK;
1114 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1115
1116 /* Enable power saving */
1117 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1118 val32 |= FPGA_RF_MODE_JAPAN;
1119 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1120
1121 /* AFE control register to power down bits [30:22] */
1122 if (priv->rf_paths == 2)
1123 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00db25a0);
1124 else
1125 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x001b25a0);
1126
1127 /* Power down RF module */
1128 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0);
1129 if (priv->rf_paths == 2)
1130 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0);
1131
1132 sps0 &= ~(BIT(0) | BIT(3));
1133 rtl8xxxu_write8(priv, REG_SPS0_CTRL, sps0);
1134 }
1135
rtl8xxxu_stop_tx_beacon(struct rtl8xxxu_priv * priv)1136 static void rtl8xxxu_stop_tx_beacon(struct rtl8xxxu_priv *priv)
1137 {
1138 u8 val8;
1139
1140 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2);
1141 val8 &= ~BIT(6);
1142 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8);
1143
1144 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x64);
1145 val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2);
1146 val8 &= ~BIT(0);
1147 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8);
1148 }
1149
rtl8xxxu_start_tx_beacon(struct rtl8xxxu_priv * priv)1150 static void rtl8xxxu_start_tx_beacon(struct rtl8xxxu_priv *priv)
1151 {
1152 u8 val8;
1153
1154 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2);
1155 val8 |= EN_BCNQ_DL >> 16;
1156 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8);
1157
1158 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x80);
1159 val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2);
1160 val8 &= 0xF0;
1161 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8);
1162 }
1163
1164
1165 /*
1166 * The rtl8723a has 3 channel groups for its efuse settings. It only
1167 * supports the 2.4GHz band, so channels 1 - 14:
1168 * group 0: channels 1 - 3
1169 * group 1: channels 4 - 9
1170 * group 2: channels 10 - 14
1171 *
1172 * Note: We index from 0 in the code
1173 */
rtl8xxxu_gen1_channel_to_group(int channel)1174 static int rtl8xxxu_gen1_channel_to_group(int channel)
1175 {
1176 int group;
1177
1178 if (channel < 4)
1179 group = 0;
1180 else if (channel < 10)
1181 group = 1;
1182 else
1183 group = 2;
1184
1185 return group;
1186 }
1187
1188 /*
1189 * Valid for rtl8723bu and rtl8192eu
1190 */
rtl8xxxu_gen2_channel_to_group(int channel)1191 int rtl8xxxu_gen2_channel_to_group(int channel)
1192 {
1193 int group;
1194
1195 if (channel < 3)
1196 group = 0;
1197 else if (channel < 6)
1198 group = 1;
1199 else if (channel < 9)
1200 group = 2;
1201 else if (channel < 12)
1202 group = 3;
1203 else
1204 group = 4;
1205
1206 return group;
1207 }
1208
rtl8xxxu_gen1_config_channel(struct ieee80211_hw * hw)1209 void rtl8xxxu_gen1_config_channel(struct ieee80211_hw *hw)
1210 {
1211 struct rtl8xxxu_priv *priv = hw->priv;
1212 u32 val32, rsr;
1213 u8 val8, opmode;
1214 bool ht = true;
1215 int sec_ch_above, channel;
1216 int i;
1217
1218 opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE);
1219 rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
1220 channel = hw->conf.chandef.chan->hw_value;
1221
1222 switch (hw->conf.chandef.width) {
1223 case NL80211_CHAN_WIDTH_20_NOHT:
1224 ht = false;
1225 fallthrough;
1226 case NL80211_CHAN_WIDTH_20:
1227 opmode |= BW_OPMODE_20MHZ;
1228 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1229
1230 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1231 val32 &= ~FPGA_RF_MODE;
1232 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1233
1234 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1235 val32 &= ~FPGA_RF_MODE;
1236 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1237
1238 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1239 val32 |= FPGA0_ANALOG2_20MHZ;
1240 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1241 break;
1242 case NL80211_CHAN_WIDTH_40:
1243 if (hw->conf.chandef.center_freq1 >
1244 hw->conf.chandef.chan->center_freq) {
1245 sec_ch_above = 1;
1246 channel += 2;
1247 } else {
1248 sec_ch_above = 0;
1249 channel -= 2;
1250 }
1251
1252 opmode &= ~BW_OPMODE_20MHZ;
1253 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1254 rsr &= ~RSR_RSC_BANDWIDTH_40M;
1255 if (sec_ch_above)
1256 rsr |= RSR_RSC_UPPER_SUB_CHANNEL;
1257 else
1258 rsr |= RSR_RSC_LOWER_SUB_CHANNEL;
1259 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr);
1260
1261 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1262 val32 |= FPGA_RF_MODE;
1263 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1264
1265 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1266 val32 |= FPGA_RF_MODE;
1267 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1268
1269 /*
1270 * Set Control channel to upper or lower. These settings
1271 * are required only for 40MHz
1272 */
1273 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1274 val32 &= ~CCK0_SIDEBAND;
1275 if (!sec_ch_above)
1276 val32 |= CCK0_SIDEBAND;
1277 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1278
1279 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1280 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
1281 if (sec_ch_above)
1282 val32 |= OFDM_LSTF_PRIME_CH_LOW;
1283 else
1284 val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1285 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1286
1287 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1288 val32 &= ~FPGA0_ANALOG2_20MHZ;
1289 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1290
1291 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1292 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1293 if (sec_ch_above)
1294 val32 |= FPGA0_PS_UPPER_CHANNEL;
1295 else
1296 val32 |= FPGA0_PS_LOWER_CHANNEL;
1297 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1298 break;
1299
1300 default:
1301 break;
1302 }
1303
1304 for (i = RF_A; i < priv->rf_paths; i++) {
1305 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1306 val32 &= ~MODE_AG_CHANNEL_MASK;
1307 val32 |= channel;
1308 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1309 }
1310
1311 if (ht)
1312 val8 = 0x0e;
1313 else
1314 val8 = 0x0a;
1315
1316 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1317 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1318
1319 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1320 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1321
1322 for (i = RF_A; i < priv->rf_paths; i++) {
1323 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1324 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40)
1325 val32 &= ~MODE_AG_CHANNEL_20MHZ;
1326 else
1327 val32 |= MODE_AG_CHANNEL_20MHZ;
1328 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1329 }
1330 }
1331
rtl8xxxu_gen2_config_channel(struct ieee80211_hw * hw)1332 void rtl8xxxu_gen2_config_channel(struct ieee80211_hw *hw)
1333 {
1334 struct rtl8xxxu_priv *priv = hw->priv;
1335 u32 val32;
1336 u8 val8, subchannel;
1337 u16 rf_mode_bw;
1338 bool ht = true;
1339 int sec_ch_above, channel;
1340 int i;
1341
1342 rf_mode_bw = rtl8xxxu_read16(priv, REG_WMAC_TRXPTCL_CTL);
1343 rf_mode_bw &= ~WMAC_TRXPTCL_CTL_BW_MASK;
1344 channel = hw->conf.chandef.chan->hw_value;
1345
1346 /* Hack */
1347 subchannel = 0;
1348
1349 switch (hw->conf.chandef.width) {
1350 case NL80211_CHAN_WIDTH_20_NOHT:
1351 ht = false;
1352 fallthrough;
1353 case NL80211_CHAN_WIDTH_20:
1354 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_20;
1355 subchannel = 0;
1356
1357 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1358 val32 &= ~FPGA_RF_MODE;
1359 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1360
1361 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1362 val32 &= ~FPGA_RF_MODE;
1363 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1364
1365 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT);
1366 val32 &= ~(BIT(30) | BIT(31));
1367 rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32);
1368
1369 break;
1370 case NL80211_CHAN_WIDTH_40:
1371 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_40;
1372
1373 if (hw->conf.chandef.center_freq1 >
1374 hw->conf.chandef.chan->center_freq) {
1375 sec_ch_above = 1;
1376 channel += 2;
1377 } else {
1378 sec_ch_above = 0;
1379 channel -= 2;
1380 }
1381
1382 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1383 val32 |= FPGA_RF_MODE;
1384 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1385
1386 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1387 val32 |= FPGA_RF_MODE;
1388 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1389
1390 /*
1391 * Set Control channel to upper or lower. These settings
1392 * are required only for 40MHz
1393 */
1394 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1395 val32 &= ~CCK0_SIDEBAND;
1396 if (!sec_ch_above)
1397 val32 |= CCK0_SIDEBAND;
1398 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1399
1400 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1401 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
1402 if (sec_ch_above)
1403 val32 |= OFDM_LSTF_PRIME_CH_LOW;
1404 else
1405 val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1406 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1407
1408 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1409 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1410 if (sec_ch_above)
1411 val32 |= FPGA0_PS_UPPER_CHANNEL;
1412 else
1413 val32 |= FPGA0_PS_LOWER_CHANNEL;
1414 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1415 break;
1416 case NL80211_CHAN_WIDTH_80:
1417 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_80;
1418 break;
1419 default:
1420 break;
1421 }
1422
1423 for (i = RF_A; i < priv->rf_paths; i++) {
1424 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1425 val32 &= ~MODE_AG_CHANNEL_MASK;
1426 val32 |= channel;
1427 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1428 }
1429
1430 rtl8xxxu_write16(priv, REG_WMAC_TRXPTCL_CTL, rf_mode_bw);
1431 rtl8xxxu_write8(priv, REG_DATA_SUBCHANNEL, subchannel);
1432
1433 if (ht)
1434 val8 = 0x0e;
1435 else
1436 val8 = 0x0a;
1437
1438 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1439 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1440
1441 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1442 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1443
1444 for (i = RF_A; i < priv->rf_paths; i++) {
1445 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1446 val32 &= ~MODE_AG_BW_MASK;
1447 switch(hw->conf.chandef.width) {
1448 case NL80211_CHAN_WIDTH_80:
1449 val32 |= MODE_AG_BW_80MHZ_8723B;
1450 break;
1451 case NL80211_CHAN_WIDTH_40:
1452 val32 |= MODE_AG_BW_40MHZ_8723B;
1453 break;
1454 default:
1455 val32 |= MODE_AG_BW_20MHZ_8723B;
1456 break;
1457 }
1458 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1459 }
1460 }
1461
1462 void
rtl8xxxu_gen1_set_tx_power(struct rtl8xxxu_priv * priv,int channel,bool ht40)1463 rtl8xxxu_gen1_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
1464 {
1465 struct rtl8xxxu_power_base *power_base = priv->power_base;
1466 u8 cck[RTL8723A_MAX_RF_PATHS], ofdm[RTL8723A_MAX_RF_PATHS];
1467 u8 ofdmbase[RTL8723A_MAX_RF_PATHS], mcsbase[RTL8723A_MAX_RF_PATHS];
1468 u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b;
1469 u8 val8, base;
1470 int group, i;
1471
1472 group = rtl8xxxu_gen1_channel_to_group(channel);
1473
1474 cck[0] = priv->cck_tx_power_index_A[group];
1475 cck[1] = priv->cck_tx_power_index_B[group];
1476
1477 if (priv->hi_pa) {
1478 if (cck[0] > 0x20)
1479 cck[0] = 0x20;
1480 if (cck[1] > 0x20)
1481 cck[1] = 0x20;
1482 }
1483
1484 ofdm[0] = priv->ht40_1s_tx_power_index_A[group];
1485 ofdm[1] = priv->ht40_1s_tx_power_index_B[group];
1486
1487 ofdmbase[0] = ofdm[0] + priv->ofdm_tx_power_index_diff[group].a;
1488 ofdmbase[1] = ofdm[1] + priv->ofdm_tx_power_index_diff[group].b;
1489
1490 mcsbase[0] = ofdm[0];
1491 mcsbase[1] = ofdm[1];
1492 if (!ht40) {
1493 mcsbase[0] += priv->ht20_tx_power_index_diff[group].a;
1494 mcsbase[1] += priv->ht20_tx_power_index_diff[group].b;
1495 }
1496
1497 if (priv->tx_paths > 1) {
1498 if (ofdm[0] > priv->ht40_2s_tx_power_index_diff[group].a)
1499 ofdm[0] -= priv->ht40_2s_tx_power_index_diff[group].a;
1500 if (ofdm[1] > priv->ht40_2s_tx_power_index_diff[group].b)
1501 ofdm[1] -= priv->ht40_2s_tx_power_index_diff[group].b;
1502 }
1503
1504 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
1505 dev_info(&priv->udev->dev,
1506 "%s: Setting TX power CCK A: %02x, "
1507 "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n",
1508 __func__, cck[0], cck[1], ofdm[0], ofdm[1]);
1509
1510 for (i = 0; i < RTL8723A_MAX_RF_PATHS; i++) {
1511 if (cck[i] > RF6052_MAX_TX_PWR)
1512 cck[i] = RF6052_MAX_TX_PWR;
1513 if (ofdm[i] > RF6052_MAX_TX_PWR)
1514 ofdm[i] = RF6052_MAX_TX_PWR;
1515 }
1516
1517 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
1518 val32 &= 0xffff00ff;
1519 val32 |= (cck[0] << 8);
1520 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
1521
1522 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1523 val32 &= 0xff;
1524 val32 |= ((cck[0] << 8) | (cck[0] << 16) | (cck[0] << 24));
1525 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1526
1527 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1528 val32 &= 0xffffff00;
1529 val32 |= cck[1];
1530 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1531
1532 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32);
1533 val32 &= 0xff;
1534 val32 |= ((cck[1] << 8) | (cck[1] << 16) | (cck[1] << 24));
1535 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32);
1536
1537 ofdm_a = ofdmbase[0] | ofdmbase[0] << 8 |
1538 ofdmbase[0] << 16 | ofdmbase[0] << 24;
1539 ofdm_b = ofdmbase[1] | ofdmbase[1] << 8 |
1540 ofdmbase[1] << 16 | ofdmbase[1] << 24;
1541
1542 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06,
1543 ofdm_a + power_base->reg_0e00);
1544 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06,
1545 ofdm_b + power_base->reg_0830);
1546
1547 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24,
1548 ofdm_a + power_base->reg_0e04);
1549 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24,
1550 ofdm_b + power_base->reg_0834);
1551
1552 mcs_a = mcsbase[0] | mcsbase[0] << 8 |
1553 mcsbase[0] << 16 | mcsbase[0] << 24;
1554 mcs_b = mcsbase[1] | mcsbase[1] << 8 |
1555 mcsbase[1] << 16 | mcsbase[1] << 24;
1556
1557 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00,
1558 mcs_a + power_base->reg_0e10);
1559 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00,
1560 mcs_b + power_base->reg_083c);
1561
1562 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04,
1563 mcs_a + power_base->reg_0e14);
1564 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04,
1565 mcs_b + power_base->reg_0848);
1566
1567 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08,
1568 mcs_a + power_base->reg_0e18);
1569 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08,
1570 mcs_b + power_base->reg_084c);
1571
1572 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12,
1573 mcs_a + power_base->reg_0e1c);
1574 val8 = u32_get_bits(mcs_a + power_base->reg_0e1c, 0xff000000);
1575 for (i = 0; i < 3; i++) {
1576 base = i != 2 ? 8 : 6;
1577 val8 = max_t(int, val8 - base, 0);
1578 rtl8xxxu_write8(priv, REG_OFDM0_XC_TX_IQ_IMBALANCE + i, val8);
1579 }
1580
1581 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12,
1582 mcs_b + power_base->reg_0868);
1583 val8 = u32_get_bits(mcs_b + power_base->reg_0868, 0xff000000);
1584 for (i = 0; i < 3; i++) {
1585 base = i != 2 ? 8 : 6;
1586 val8 = max_t(int, val8 - base, 0);
1587 rtl8xxxu_write8(priv, REG_OFDM0_XD_TX_IQ_IMBALANCE + i, val8);
1588 }
1589 }
1590
rtl8xxxu_set_linktype(struct rtl8xxxu_priv * priv,enum nl80211_iftype linktype,int port_num)1591 static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv *priv,
1592 enum nl80211_iftype linktype, int port_num)
1593 {
1594 u8 val8, type;
1595
1596 switch (linktype) {
1597 case NL80211_IFTYPE_UNSPECIFIED:
1598 type = MSR_LINKTYPE_NONE;
1599 break;
1600 case NL80211_IFTYPE_ADHOC:
1601 type = MSR_LINKTYPE_ADHOC;
1602 break;
1603 case NL80211_IFTYPE_STATION:
1604 type = MSR_LINKTYPE_STATION;
1605 break;
1606 case NL80211_IFTYPE_AP:
1607 type = MSR_LINKTYPE_AP;
1608 break;
1609 default:
1610 return;
1611 }
1612
1613 switch (port_num) {
1614 case 0:
1615 val8 = rtl8xxxu_read8(priv, REG_MSR) & 0x0c;
1616 val8 |= type;
1617 break;
1618 case 1:
1619 val8 = rtl8xxxu_read8(priv, REG_MSR) & 0x03;
1620 val8 |= type << 2;
1621 break;
1622 default:
1623 return;
1624 }
1625
1626 rtl8xxxu_write8(priv, REG_MSR, val8);
1627 }
1628
1629 static void
rtl8xxxu_set_retry(struct rtl8xxxu_priv * priv,u16 short_retry,u16 long_retry)1630 rtl8xxxu_set_retry(struct rtl8xxxu_priv *priv, u16 short_retry, u16 long_retry)
1631 {
1632 u16 val16;
1633
1634 val16 = ((short_retry << RETRY_LIMIT_SHORT_SHIFT) &
1635 RETRY_LIMIT_SHORT_MASK) |
1636 ((long_retry << RETRY_LIMIT_LONG_SHIFT) &
1637 RETRY_LIMIT_LONG_MASK);
1638
1639 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
1640 }
1641
1642 static void
rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv * priv,u16 cck,u16 ofdm)1643 rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv *priv, u16 cck, u16 ofdm)
1644 {
1645 u16 val16;
1646
1647 val16 = ((cck << SPEC_SIFS_CCK_SHIFT) & SPEC_SIFS_CCK_MASK) |
1648 ((ofdm << SPEC_SIFS_OFDM_SHIFT) & SPEC_SIFS_OFDM_MASK);
1649
1650 rtl8xxxu_write16(priv, REG_SPEC_SIFS, val16);
1651 }
1652
rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv * priv)1653 static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv)
1654 {
1655 struct device *dev = &priv->udev->dev;
1656 char cut = 'A' + priv->chip_cut;
1657
1658 dev_info(dev,
1659 "RTL%s rev %c (%s) romver %d, %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n",
1660 priv->chip_name, cut, priv->chip_vendor, priv->rom_rev,
1661 priv->tx_paths, priv->rx_paths, priv->ep_tx_count,
1662 priv->has_wifi, priv->has_bluetooth, priv->has_gps,
1663 priv->hi_pa);
1664
1665 dev_info(dev, "RTL%s MAC: %pM\n", priv->chip_name, priv->mac_addr);
1666 }
1667
rtl8xxxu_identify_vendor_1bit(struct rtl8xxxu_priv * priv,u32 vendor)1668 void rtl8xxxu_identify_vendor_1bit(struct rtl8xxxu_priv *priv, u32 vendor)
1669 {
1670 if (vendor) {
1671 strscpy(priv->chip_vendor, "UMC", sizeof(priv->chip_vendor));
1672 priv->vendor_umc = 1;
1673 } else {
1674 strscpy(priv->chip_vendor, "TSMC", sizeof(priv->chip_vendor));
1675 }
1676 }
1677
rtl8xxxu_identify_vendor_2bits(struct rtl8xxxu_priv * priv,u32 vendor)1678 void rtl8xxxu_identify_vendor_2bits(struct rtl8xxxu_priv *priv, u32 vendor)
1679 {
1680 switch (vendor) {
1681 case SYS_CFG_VENDOR_ID_TSMC:
1682 strscpy(priv->chip_vendor, "TSMC", sizeof(priv->chip_vendor));
1683 break;
1684 case SYS_CFG_VENDOR_ID_SMIC:
1685 strscpy(priv->chip_vendor, "SMIC", sizeof(priv->chip_vendor));
1686 priv->vendor_smic = 1;
1687 break;
1688 case SYS_CFG_VENDOR_ID_UMC:
1689 strscpy(priv->chip_vendor, "UMC", sizeof(priv->chip_vendor));
1690 priv->vendor_umc = 1;
1691 break;
1692 default:
1693 strscpy(priv->chip_vendor, "unknown", sizeof(priv->chip_vendor));
1694 }
1695 }
1696
rtl8xxxu_config_endpoints_sie(struct rtl8xxxu_priv * priv)1697 void rtl8xxxu_config_endpoints_sie(struct rtl8xxxu_priv *priv)
1698 {
1699 u16 val16;
1700
1701 val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX);
1702
1703 if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) {
1704 priv->ep_tx_high_queue = 1;
1705 priv->ep_tx_count++;
1706 }
1707
1708 if (val16 & NORMAL_SIE_EP_TX_NORMAL_MASK) {
1709 priv->ep_tx_normal_queue = 1;
1710 priv->ep_tx_count++;
1711 }
1712
1713 if (val16 & NORMAL_SIE_EP_TX_LOW_MASK) {
1714 priv->ep_tx_low_queue = 1;
1715 priv->ep_tx_count++;
1716 }
1717 }
1718
rtl8xxxu_config_endpoints_no_sie(struct rtl8xxxu_priv * priv)1719 int rtl8xxxu_config_endpoints_no_sie(struct rtl8xxxu_priv *priv)
1720 {
1721 struct device *dev = &priv->udev->dev;
1722
1723 switch (priv->nr_out_eps) {
1724 case 6:
1725 case 5:
1726 case 4:
1727 case 3:
1728 priv->ep_tx_low_queue = 1;
1729 priv->ep_tx_count++;
1730 fallthrough;
1731 case 2:
1732 priv->ep_tx_normal_queue = 1;
1733 priv->ep_tx_count++;
1734 fallthrough;
1735 case 1:
1736 priv->ep_tx_high_queue = 1;
1737 priv->ep_tx_count++;
1738 break;
1739 default:
1740 dev_info(dev, "Unsupported USB TX end-points\n");
1741 return -ENOTSUPP;
1742 }
1743
1744 return 0;
1745 }
1746
1747 int
rtl8xxxu_read_efuse8(struct rtl8xxxu_priv * priv,u16 offset,u8 * data)1748 rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data)
1749 {
1750 int i;
1751 u8 val8;
1752 u32 val32;
1753
1754 /* Write Address */
1755 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 1, offset & 0xff);
1756 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 2);
1757 val8 &= 0xfc;
1758 val8 |= (offset >> 8) & 0x03;
1759 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 2, val8);
1760
1761 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 3);
1762 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 3, val8 & 0x7f);
1763
1764 /* Poll for data read */
1765 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
1766 for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) {
1767 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
1768 if (val32 & BIT(31))
1769 break;
1770 }
1771
1772 if (i == RTL8XXXU_MAX_REG_POLL)
1773 return -EIO;
1774
1775 udelay(50);
1776 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
1777
1778 *data = val32 & 0xff;
1779 return 0;
1780 }
1781
rtl8xxxu_read_efuse(struct rtl8xxxu_priv * priv)1782 int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv)
1783 {
1784 struct device *dev = &priv->udev->dev;
1785 int i, ret = 0;
1786 u8 val8, word_mask, header, extheader;
1787 u16 val16, efuse_addr, offset;
1788 u32 val32;
1789
1790 val16 = rtl8xxxu_read16(priv, REG_9346CR);
1791 if (val16 & EEPROM_ENABLE)
1792 priv->has_eeprom = 1;
1793 if (val16 & EEPROM_BOOT)
1794 priv->boot_eeprom = 1;
1795
1796 if (priv->is_multi_func) {
1797 val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST);
1798 val32 = (val32 & ~EFUSE_SELECT_MASK) | EFUSE_WIFI_SELECT;
1799 rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32);
1800 }
1801
1802 dev_dbg(dev, "Booting from %s\n",
1803 priv->boot_eeprom ? "EEPROM" : "EFUSE");
1804
1805 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_ENABLE);
1806
1807 /* 1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */
1808 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
1809 if (!(val16 & SYS_ISO_PWC_EV12V)) {
1810 val16 |= SYS_ISO_PWC_EV12V;
1811 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
1812 }
1813 /* Reset: 0x0000[28], default valid */
1814 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
1815 if (!(val16 & SYS_FUNC_ELDR)) {
1816 val16 |= SYS_FUNC_ELDR;
1817 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
1818 }
1819
1820 /*
1821 * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid
1822 */
1823 val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR);
1824 if (!(val16 & SYS_CLK_LOADER_ENABLE) || !(val16 & SYS_CLK_ANA8M)) {
1825 val16 |= (SYS_CLK_LOADER_ENABLE | SYS_CLK_ANA8M);
1826 rtl8xxxu_write16(priv, REG_SYS_CLKR, val16);
1827 }
1828
1829 /* Default value is 0xff */
1830 memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN);
1831
1832 efuse_addr = 0;
1833 while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) {
1834 u16 map_addr;
1835
1836 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &header);
1837 if (ret || header == 0xff)
1838 goto exit;
1839
1840 if ((header & 0x1f) == 0x0f) { /* extended header */
1841 offset = (header & 0xe0) >> 5;
1842
1843 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++,
1844 &extheader);
1845 if (ret)
1846 goto exit;
1847 /* All words disabled */
1848 if ((extheader & 0x0f) == 0x0f)
1849 continue;
1850
1851 offset |= ((extheader & 0xf0) >> 1);
1852 word_mask = extheader & 0x0f;
1853 } else {
1854 offset = (header >> 4) & 0x0f;
1855 word_mask = header & 0x0f;
1856 }
1857
1858 /* Get word enable value from PG header */
1859
1860 /* We have 8 bits to indicate validity */
1861 map_addr = offset * 8;
1862 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
1863 /* Check word enable condition in the section */
1864 if (word_mask & BIT(i)) {
1865 map_addr += 2;
1866 continue;
1867 }
1868
1869 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
1870 if (ret)
1871 goto exit;
1872 if (map_addr >= EFUSE_MAP_LEN - 1) {
1873 dev_warn(dev, "%s: Illegal map_addr (%04x), "
1874 "efuse corrupt!\n",
1875 __func__, map_addr);
1876 ret = -EINVAL;
1877 goto exit;
1878 }
1879 priv->efuse_wifi.raw[map_addr++] = val8;
1880
1881 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
1882 if (ret)
1883 goto exit;
1884 priv->efuse_wifi.raw[map_addr++] = val8;
1885 }
1886 }
1887
1888 exit:
1889 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_DISABLE);
1890
1891 return ret;
1892 }
1893
rtl8xxxu_dump_efuse(struct rtl8xxxu_priv * priv)1894 static void rtl8xxxu_dump_efuse(struct rtl8xxxu_priv *priv)
1895 {
1896 dev_info(&priv->udev->dev,
1897 "Dumping efuse for RTL%s (0x%02x bytes):\n",
1898 priv->chip_name, EFUSE_MAP_LEN);
1899
1900 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1,
1901 priv->efuse_wifi.raw, EFUSE_MAP_LEN, true);
1902 }
1903
rtl8xxxu_reset_8051(struct rtl8xxxu_priv * priv)1904 void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv)
1905 {
1906 u8 val8;
1907 u16 sys_func;
1908
1909 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
1910 val8 &= ~BIT(0);
1911 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
1912
1913 sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC);
1914 sys_func &= ~SYS_FUNC_CPU_ENABLE;
1915 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
1916
1917 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
1918 val8 |= BIT(0);
1919 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
1920
1921 sys_func |= SYS_FUNC_CPU_ENABLE;
1922 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
1923 }
1924
rtl8xxxu_start_firmware(struct rtl8xxxu_priv * priv)1925 static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv)
1926 {
1927 struct device *dev = &priv->udev->dev;
1928 u16 reg_mcu_fw_dl;
1929 int ret = 0, i;
1930 u32 val32;
1931
1932 if (priv->rtl_chip == RTL8710B)
1933 reg_mcu_fw_dl = REG_8051FW_CTRL_V1_8710B;
1934 else
1935 reg_mcu_fw_dl = REG_MCU_FW_DL;
1936
1937 /* Poll checksum report */
1938 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
1939 val32 = rtl8xxxu_read32(priv, reg_mcu_fw_dl);
1940 if (val32 & MCU_FW_DL_CSUM_REPORT)
1941 break;
1942 }
1943
1944 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
1945 dev_warn(dev, "Firmware checksum poll timed out\n");
1946 ret = -EAGAIN;
1947 goto exit;
1948 }
1949
1950 val32 = rtl8xxxu_read32(priv, reg_mcu_fw_dl);
1951 val32 |= MCU_FW_DL_READY;
1952 val32 &= ~MCU_WINT_INIT_READY;
1953 rtl8xxxu_write32(priv, reg_mcu_fw_dl, val32);
1954
1955 /*
1956 * Reset the 8051 in order for the firmware to start running,
1957 * otherwise it won't come up on the 8192eu
1958 */
1959 priv->fops->reset_8051(priv);
1960
1961 /* Wait for firmware to become ready */
1962 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
1963 val32 = rtl8xxxu_read32(priv, reg_mcu_fw_dl);
1964 if (val32 & MCU_WINT_INIT_READY)
1965 break;
1966
1967 udelay(100);
1968 }
1969
1970 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
1971 dev_warn(dev, "Firmware failed to start\n");
1972 ret = -EAGAIN;
1973 goto exit;
1974 }
1975
1976 /*
1977 * Init H2C command
1978 */
1979 if (priv->fops->init_reg_hmtfr)
1980 rtl8xxxu_write8(priv, REG_HMTFR, 0x0f);
1981 exit:
1982 return ret;
1983 }
1984
rtl8xxxu_download_firmware(struct rtl8xxxu_priv * priv)1985 static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv)
1986 {
1987 int pages, remainder, i, ret;
1988 u16 reg_fw_start_address;
1989 u16 reg_mcu_fw_dl;
1990 u8 val8;
1991 u16 val16;
1992 u32 val32;
1993 u8 *fwptr;
1994
1995 if (priv->rtl_chip == RTL8192F)
1996 reg_fw_start_address = REG_FW_START_ADDRESS_8192F;
1997 else
1998 reg_fw_start_address = REG_FW_START_ADDRESS;
1999
2000 if (priv->rtl_chip == RTL8710B) {
2001 reg_mcu_fw_dl = REG_8051FW_CTRL_V1_8710B;
2002 } else {
2003 reg_mcu_fw_dl = REG_MCU_FW_DL;
2004
2005 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC + 1);
2006 val8 |= 4;
2007 rtl8xxxu_write8(priv, REG_SYS_FUNC + 1, val8);
2008
2009 /* 8051 enable */
2010 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2011 val16 |= SYS_FUNC_CPU_ENABLE;
2012 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2013 }
2014
2015 val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl);
2016 if (val8 & MCU_FW_RAM_SEL) {
2017 dev_info(&priv->udev->dev,
2018 "Firmware is already running, resetting the MCU.\n");
2019 rtl8xxxu_write8(priv, reg_mcu_fw_dl, 0x00);
2020 priv->fops->reset_8051(priv);
2021 }
2022
2023 /* MCU firmware download enable */
2024 val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl);
2025 val8 |= MCU_FW_DL_ENABLE;
2026 rtl8xxxu_write8(priv, reg_mcu_fw_dl, val8);
2027
2028 /* 8051 reset */
2029 val32 = rtl8xxxu_read32(priv, reg_mcu_fw_dl);
2030 val32 &= ~BIT(19);
2031 rtl8xxxu_write32(priv, reg_mcu_fw_dl, val32);
2032
2033 if (priv->rtl_chip == RTL8710B) {
2034 /* We must set 0x8090[8]=1 before download FW. */
2035 val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl + 1);
2036 val8 |= BIT(0);
2037 rtl8xxxu_write8(priv, reg_mcu_fw_dl + 1, val8);
2038 }
2039
2040 /* Reset firmware download checksum */
2041 val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl);
2042 val8 |= MCU_FW_DL_CSUM_REPORT;
2043 rtl8xxxu_write8(priv, reg_mcu_fw_dl, val8);
2044
2045 pages = priv->fw_size / RTL_FW_PAGE_SIZE;
2046 remainder = priv->fw_size % RTL_FW_PAGE_SIZE;
2047
2048 fwptr = priv->fw_data->data;
2049
2050 for (i = 0; i < pages; i++) {
2051 val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl + 2) & 0xF8;
2052 val8 |= i;
2053 rtl8xxxu_write8(priv, reg_mcu_fw_dl + 2, val8);
2054
2055 ret = rtl8xxxu_writeN(priv, reg_fw_start_address,
2056 fwptr, RTL_FW_PAGE_SIZE);
2057 if (ret != RTL_FW_PAGE_SIZE) {
2058 ret = -EAGAIN;
2059 goto fw_abort;
2060 }
2061
2062 fwptr += RTL_FW_PAGE_SIZE;
2063 }
2064
2065 if (remainder) {
2066 val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl + 2) & 0xF8;
2067 val8 |= i;
2068 rtl8xxxu_write8(priv, reg_mcu_fw_dl + 2, val8);
2069 ret = rtl8xxxu_writeN(priv, reg_fw_start_address,
2070 fwptr, remainder);
2071 if (ret != remainder) {
2072 ret = -EAGAIN;
2073 goto fw_abort;
2074 }
2075 }
2076
2077 ret = 0;
2078 fw_abort:
2079 /* MCU firmware download disable */
2080 val16 = rtl8xxxu_read16(priv, reg_mcu_fw_dl);
2081 val16 &= ~MCU_FW_DL_ENABLE;
2082 rtl8xxxu_write16(priv, reg_mcu_fw_dl, val16);
2083
2084 return ret;
2085 }
2086
rtl8xxxu_load_firmware(struct rtl8xxxu_priv * priv,const char * fw_name)2087 int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, const char *fw_name)
2088 {
2089 struct device *dev = &priv->udev->dev;
2090 const struct firmware *fw;
2091 int ret = 0;
2092 u16 signature;
2093
2094 dev_info(dev, "%s: Loading firmware %s\n", DRIVER_NAME, fw_name);
2095 if (request_firmware(&fw, fw_name, &priv->udev->dev)) {
2096 dev_warn(dev, "request_firmware(%s) failed\n", fw_name);
2097 ret = -EAGAIN;
2098 goto exit;
2099 }
2100 if (!fw) {
2101 dev_warn(dev, "Firmware data not available\n");
2102 ret = -EINVAL;
2103 goto exit;
2104 }
2105
2106 priv->fw_data = kmemdup(fw->data, fw->size, GFP_KERNEL);
2107 if (!priv->fw_data) {
2108 ret = -ENOMEM;
2109 goto exit;
2110 }
2111 priv->fw_size = fw->size - sizeof(struct rtl8xxxu_firmware_header);
2112
2113 signature = le16_to_cpu(priv->fw_data->signature);
2114 switch (signature & 0xfff0) {
2115 case 0x92e0:
2116 case 0x92c0:
2117 case 0x88e0:
2118 case 0x88c0:
2119 case 0x5300:
2120 case 0x2300:
2121 case 0x88f0:
2122 case 0x10b0:
2123 case 0x92f0:
2124 break;
2125 default:
2126 ret = -EINVAL;
2127 dev_warn(dev, "%s: Invalid firmware signature: 0x%04x\n",
2128 __func__, signature);
2129 }
2130
2131 dev_info(dev, "Firmware revision %i.%i (signature 0x%04x)\n",
2132 le16_to_cpu(priv->fw_data->major_version),
2133 priv->fw_data->minor_version, signature);
2134
2135 exit:
2136 release_firmware(fw);
2137 return ret;
2138 }
2139
rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv * priv)2140 void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv)
2141 {
2142 u16 val16;
2143 int i = 100;
2144
2145 /* Inform 8051 to perform reset */
2146 rtl8xxxu_write8(priv, REG_HMTFR + 3, 0x20);
2147
2148 for (i = 100; i > 0; i--) {
2149 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2150
2151 if (!(val16 & SYS_FUNC_CPU_ENABLE)) {
2152 dev_dbg(&priv->udev->dev,
2153 "%s: Firmware self reset success!\n", __func__);
2154 break;
2155 }
2156 udelay(50);
2157 }
2158
2159 if (!i) {
2160 /* Force firmware reset */
2161 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2162 val16 &= ~SYS_FUNC_CPU_ENABLE;
2163 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2164 }
2165 }
2166
2167 static int
rtl8xxxu_init_mac(struct rtl8xxxu_priv * priv)2168 rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv)
2169 {
2170 const struct rtl8xxxu_reg8val *array = priv->fops->mactable;
2171 int i, ret;
2172 u16 reg;
2173 u8 val;
2174
2175 for (i = 0; ; i++) {
2176 reg = array[i].reg;
2177 val = array[i].val;
2178
2179 if (reg == 0xffff && val == 0xff)
2180 break;
2181
2182 ret = rtl8xxxu_write8(priv, reg, val);
2183 if (ret != 1) {
2184 dev_warn(&priv->udev->dev,
2185 "Failed to initialize MAC "
2186 "(reg: %04x, val %02x)\n", reg, val);
2187 return -EAGAIN;
2188 }
2189 }
2190
2191 switch (priv->rtl_chip) {
2192 case RTL8188C:
2193 case RTL8188R:
2194 case RTL8191C:
2195 case RTL8192C:
2196 case RTL8723A:
2197 rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a);
2198 break;
2199 case RTL8188E:
2200 rtl8xxxu_write16(priv, REG_MAX_AGGR_NUM, 0x0707);
2201 break;
2202 default:
2203 break;
2204 }
2205
2206 return 0;
2207 }
2208
rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv * priv,const struct rtl8xxxu_reg32val * array)2209 int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv,
2210 const struct rtl8xxxu_reg32val *array)
2211 {
2212 int i, ret;
2213 u16 reg;
2214 u32 val;
2215
2216 for (i = 0; ; i++) {
2217 reg = array[i].reg;
2218 val = array[i].val;
2219
2220 if (reg == 0xffff && val == 0xffffffff)
2221 break;
2222
2223 ret = rtl8xxxu_write32(priv, reg, val);
2224 if (ret != sizeof(val)) {
2225 dev_warn(&priv->udev->dev,
2226 "Failed to initialize PHY\n");
2227 return -EAGAIN;
2228 }
2229 udelay(1);
2230 }
2231
2232 return 0;
2233 }
2234
rtl8xxxu_gen1_init_phy_bb(struct rtl8xxxu_priv * priv)2235 void rtl8xxxu_gen1_init_phy_bb(struct rtl8xxxu_priv *priv)
2236 {
2237 u8 val8, ldoa15, ldov12d, lpldo, ldohci12;
2238 u16 val16;
2239 u32 val32;
2240
2241 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
2242 udelay(2);
2243 val8 |= AFE_PLL_320_ENABLE;
2244 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
2245 udelay(2);
2246
2247 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL + 1, 0xff);
2248 udelay(2);
2249
2250 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2251 val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB;
2252 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2253
2254 val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL);
2255 val32 &= ~AFE_XTAL_RF_GATE;
2256 if (priv->has_bluetooth)
2257 val32 &= ~AFE_XTAL_BT_GATE;
2258 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32);
2259
2260 /* 6. 0x1f[7:0] = 0x07 */
2261 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
2262 rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
2263
2264 if (priv->hi_pa)
2265 rtl8xxxu_init_phy_regs(priv, rtl8188ru_phy_1t_highpa_table);
2266 else if (priv->tx_paths == 2)
2267 rtl8xxxu_init_phy_regs(priv, rtl8192cu_phy_2t_init_table);
2268 else
2269 rtl8xxxu_init_phy_regs(priv, rtl8723a_phy_1t_init_table);
2270
2271 if (priv->rtl_chip == RTL8188R && priv->hi_pa &&
2272 priv->vendor_umc && priv->chip_cut == 1)
2273 rtl8xxxu_write8(priv, REG_OFDM0_AGC_PARM1 + 2, 0x50);
2274
2275 if (priv->hi_pa)
2276 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_highpa_table);
2277 else
2278 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_standard_table);
2279
2280 ldoa15 = LDOA15_ENABLE | LDOA15_OBUF;
2281 ldov12d = LDOV12D_ENABLE | BIT(2) | (2 << LDOV12D_VADJ_SHIFT);
2282 ldohci12 = 0x57;
2283 lpldo = 1;
2284 val32 = (lpldo << 24) | (ldohci12 << 16) | (ldov12d << 8) | ldoa15;
2285 rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32);
2286 }
2287
2288 /*
2289 * Most of this is black magic retrieved from the old rtl8723au driver
2290 */
rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv * priv)2291 static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv)
2292 {
2293 u32 val32;
2294
2295 priv->fops->init_phy_bb(priv);
2296
2297 if (priv->tx_paths == 1 && priv->rx_paths == 2) {
2298 /*
2299 * For 1T2R boards, patch the registers.
2300 *
2301 * It looks like 8191/2 1T2R boards use path B for TX
2302 */
2303 val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO);
2304 val32 &= ~(BIT(0) | BIT(1));
2305 val32 |= BIT(1);
2306 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32);
2307
2308 val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO);
2309 val32 &= ~0x300033;
2310 val32 |= 0x200022;
2311 rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32);
2312
2313 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
2314 val32 &= ~CCK0_AFE_RX_MASK;
2315 val32 &= 0x00ffffff;
2316 val32 |= 0x40000000;
2317 val32 |= CCK0_AFE_RX_ANT_B;
2318 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
2319
2320 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
2321 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK);
2322 val32 |= (OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B |
2323 OFDM_RF_PATH_TX_B);
2324 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
2325
2326 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1);
2327 val32 &= ~(BIT(4) | BIT(5));
2328 val32 |= BIT(4);
2329 rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32);
2330
2331 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON);
2332 val32 &= ~(BIT(27) | BIT(26));
2333 val32 |= BIT(27);
2334 rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32);
2335
2336 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON);
2337 val32 &= ~(BIT(27) | BIT(26));
2338 val32 |= BIT(27);
2339 rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32);
2340
2341 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON);
2342 val32 &= ~(BIT(27) | BIT(26));
2343 val32 |= BIT(27);
2344 rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32);
2345
2346 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON);
2347 val32 &= ~(BIT(27) | BIT(26));
2348 val32 |= BIT(27);
2349 rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32);
2350
2351 val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX);
2352 val32 &= ~(BIT(27) | BIT(26));
2353 val32 |= BIT(27);
2354 rtl8xxxu_write32(priv, REG_TX_TO_TX, val32);
2355 }
2356
2357 if (priv->fops->set_crystal_cap)
2358 priv->fops->set_crystal_cap(priv, priv->default_crystal_cap);
2359
2360 if (priv->rtl_chip == RTL8192E)
2361 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x000f81fb);
2362
2363 return 0;
2364 }
2365
rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv * priv,const struct rtl8xxxu_rfregval * array,enum rtl8xxxu_rfpath path)2366 static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv,
2367 const struct rtl8xxxu_rfregval *array,
2368 enum rtl8xxxu_rfpath path)
2369 {
2370 int i, ret;
2371 u8 reg;
2372 u32 val;
2373
2374 for (i = 0; ; i++) {
2375 reg = array[i].reg;
2376 val = array[i].val;
2377
2378 if (reg == 0xff && val == 0xffffffff)
2379 break;
2380
2381 switch (reg) {
2382 case 0xfe:
2383 msleep(50);
2384 continue;
2385 case 0xfd:
2386 mdelay(5);
2387 continue;
2388 case 0xfc:
2389 mdelay(1);
2390 continue;
2391 case 0xfb:
2392 udelay(50);
2393 continue;
2394 case 0xfa:
2395 udelay(5);
2396 continue;
2397 case 0xf9:
2398 udelay(1);
2399 continue;
2400 }
2401
2402 ret = rtl8xxxu_write_rfreg(priv, path, reg, val);
2403 if (ret) {
2404 dev_warn(&priv->udev->dev,
2405 "Failed to initialize RF\n");
2406 return -EAGAIN;
2407 }
2408 udelay(1);
2409 }
2410
2411 return 0;
2412 }
2413
rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv * priv,const struct rtl8xxxu_rfregval * table,enum rtl8xxxu_rfpath path)2414 int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv,
2415 const struct rtl8xxxu_rfregval *table,
2416 enum rtl8xxxu_rfpath path)
2417 {
2418 u32 val32;
2419 u16 val16, rfsi_rfenv;
2420 u16 reg_sw_ctrl, reg_int_oe, reg_hssi_parm2;
2421
2422 switch (path) {
2423 case RF_A:
2424 reg_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL;
2425 reg_int_oe = REG_FPGA0_XA_RF_INT_OE;
2426 reg_hssi_parm2 = REG_FPGA0_XA_HSSI_PARM2;
2427 break;
2428 case RF_B:
2429 reg_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL;
2430 reg_int_oe = REG_FPGA0_XB_RF_INT_OE;
2431 reg_hssi_parm2 = REG_FPGA0_XB_HSSI_PARM2;
2432 break;
2433 default:
2434 dev_err(&priv->udev->dev, "%s:Unsupported RF path %c\n",
2435 __func__, path + 'A');
2436 return -EINVAL;
2437 }
2438 /* For path B, use XB */
2439 rfsi_rfenv = rtl8xxxu_read16(priv, reg_sw_ctrl);
2440 rfsi_rfenv &= FPGA0_RF_RFENV;
2441
2442 /*
2443 * These two we might be able to optimize into one
2444 */
2445 val32 = rtl8xxxu_read32(priv, reg_int_oe);
2446 val32 |= BIT(20); /* 0x10 << 16 */
2447 rtl8xxxu_write32(priv, reg_int_oe, val32);
2448 udelay(1);
2449
2450 val32 = rtl8xxxu_read32(priv, reg_int_oe);
2451 val32 |= BIT(4);
2452 rtl8xxxu_write32(priv, reg_int_oe, val32);
2453 udelay(1);
2454
2455 /*
2456 * These two we might be able to optimize into one
2457 */
2458 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
2459 val32 &= ~FPGA0_HSSI_3WIRE_ADDR_LEN;
2460 rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
2461 udelay(1);
2462
2463 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
2464 val32 &= ~FPGA0_HSSI_3WIRE_DATA_LEN;
2465 rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
2466 udelay(1);
2467
2468 rtl8xxxu_init_rf_regs(priv, table, path);
2469
2470 /* For path B, use XB */
2471 val16 = rtl8xxxu_read16(priv, reg_sw_ctrl);
2472 val16 &= ~FPGA0_RF_RFENV;
2473 val16 |= rfsi_rfenv;
2474 rtl8xxxu_write16(priv, reg_sw_ctrl, val16);
2475
2476 return 0;
2477 }
2478
rtl8xxxu_llt_write(struct rtl8xxxu_priv * priv,u8 address,u8 data)2479 static int rtl8xxxu_llt_write(struct rtl8xxxu_priv *priv, u8 address, u8 data)
2480 {
2481 int ret = -EBUSY;
2482 int count = 0;
2483 u32 value;
2484
2485 value = LLT_OP_WRITE | address << 8 | data;
2486
2487 rtl8xxxu_write32(priv, REG_LLT_INIT, value);
2488
2489 do {
2490 value = rtl8xxxu_read32(priv, REG_LLT_INIT);
2491 if ((value & LLT_OP_MASK) == LLT_OP_INACTIVE) {
2492 ret = 0;
2493 break;
2494 }
2495 } while (count++ < 20);
2496
2497 return ret;
2498 }
2499
rtl8xxxu_init_llt_table(struct rtl8xxxu_priv * priv)2500 int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv)
2501 {
2502 int ret;
2503 int i, last_entry;
2504 u8 last_tx_page;
2505
2506 last_tx_page = priv->fops->total_page_num;
2507
2508 if (priv->fops->last_llt_entry)
2509 last_entry = priv->fops->last_llt_entry;
2510 else
2511 last_entry = 255;
2512
2513 for (i = 0; i < last_tx_page; i++) {
2514 ret = rtl8xxxu_llt_write(priv, i, i + 1);
2515 if (ret)
2516 goto exit;
2517 }
2518
2519 ret = rtl8xxxu_llt_write(priv, last_tx_page, 0xff);
2520 if (ret)
2521 goto exit;
2522
2523 /* Mark remaining pages as a ring buffer */
2524 for (i = last_tx_page + 1; i < last_entry; i++) {
2525 ret = rtl8xxxu_llt_write(priv, i, (i + 1));
2526 if (ret)
2527 goto exit;
2528 }
2529
2530 /* Let last entry point to the start entry of ring buffer */
2531 ret = rtl8xxxu_llt_write(priv, last_entry, last_tx_page + 1);
2532 if (ret)
2533 goto exit;
2534
2535 exit:
2536 return ret;
2537 }
2538
rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv * priv)2539 int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv)
2540 {
2541 u32 val32;
2542 int ret = 0;
2543 int i;
2544
2545 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
2546 val32 |= AUTO_LLT_INIT_LLT;
2547 rtl8xxxu_write32(priv, REG_AUTO_LLT, val32);
2548
2549 for (i = 500; i; i--) {
2550 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
2551 if (!(val32 & AUTO_LLT_INIT_LLT))
2552 break;
2553 usleep_range(2, 4);
2554 }
2555
2556 if (!i) {
2557 ret = -EBUSY;
2558 dev_warn(&priv->udev->dev, "LLT table init failed\n");
2559 }
2560
2561 return ret;
2562 }
2563
rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv * priv)2564 static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv)
2565 {
2566 u16 val16, hi, lo;
2567 u16 hiq, mgq, bkq, beq, viq, voq;
2568 int hip, mgp, bkp, bep, vip, vop;
2569 int ret = 0;
2570 u32 val32;
2571
2572 switch (priv->ep_tx_count) {
2573 case 1:
2574 if (priv->ep_tx_high_queue) {
2575 hi = TRXDMA_QUEUE_HIGH;
2576 } else if (priv->ep_tx_low_queue) {
2577 hi = TRXDMA_QUEUE_LOW;
2578 } else if (priv->ep_tx_normal_queue) {
2579 hi = TRXDMA_QUEUE_NORMAL;
2580 } else {
2581 hi = 0;
2582 ret = -EINVAL;
2583 }
2584
2585 hiq = hi;
2586 mgq = hi;
2587 bkq = hi;
2588 beq = hi;
2589 viq = hi;
2590 voq = hi;
2591
2592 hip = 0;
2593 mgp = 0;
2594 bkp = 0;
2595 bep = 0;
2596 vip = 0;
2597 vop = 0;
2598 break;
2599 case 2:
2600 if (priv->ep_tx_high_queue && priv->ep_tx_low_queue) {
2601 hi = TRXDMA_QUEUE_HIGH;
2602 lo = TRXDMA_QUEUE_LOW;
2603 } else if (priv->ep_tx_normal_queue && priv->ep_tx_low_queue) {
2604 hi = TRXDMA_QUEUE_NORMAL;
2605 lo = TRXDMA_QUEUE_LOW;
2606 } else if (priv->ep_tx_high_queue && priv->ep_tx_normal_queue) {
2607 hi = TRXDMA_QUEUE_HIGH;
2608 lo = TRXDMA_QUEUE_NORMAL;
2609 } else {
2610 ret = -EINVAL;
2611 hi = 0;
2612 lo = 0;
2613 }
2614
2615 hiq = hi;
2616 mgq = hi;
2617 bkq = lo;
2618 beq = lo;
2619 viq = hi;
2620 voq = hi;
2621
2622 hip = 0;
2623 mgp = 0;
2624 bkp = 1;
2625 bep = 1;
2626 vip = 0;
2627 vop = 0;
2628 break;
2629 case 3:
2630 beq = TRXDMA_QUEUE_LOW;
2631 bkq = TRXDMA_QUEUE_LOW;
2632 viq = TRXDMA_QUEUE_NORMAL;
2633 voq = TRXDMA_QUEUE_HIGH;
2634 mgq = TRXDMA_QUEUE_HIGH;
2635 hiq = TRXDMA_QUEUE_HIGH;
2636
2637 hip = hiq ^ 3;
2638 mgp = mgq ^ 3;
2639 bkp = bkq ^ 3;
2640 bep = beq ^ 3;
2641 vip = viq ^ 3;
2642 vop = viq ^ 3;
2643 break;
2644 default:
2645 ret = -EINVAL;
2646 }
2647
2648 /*
2649 * None of the vendor drivers are configuring the beacon
2650 * queue here .... why?
2651 */
2652 if (!ret) {
2653 /* Only RTL8192F seems to do it like this. */
2654 if (priv->rtl_chip == RTL8192F) {
2655 val32 = rtl8xxxu_read32(priv, REG_TRXDMA_CTRL);
2656 val32 &= 0x7;
2657 val32 |= (voq << TRXDMA_CTRL_VOQ_SHIFT_8192F) |
2658 (viq << TRXDMA_CTRL_VIQ_SHIFT_8192F) |
2659 (beq << TRXDMA_CTRL_BEQ_SHIFT_8192F) |
2660 (bkq << TRXDMA_CTRL_BKQ_SHIFT_8192F) |
2661 (mgq << TRXDMA_CTRL_MGQ_SHIFT_8192F) |
2662 (hiq << TRXDMA_CTRL_HIQ_SHIFT_8192F);
2663 rtl8xxxu_write32(priv, REG_TRXDMA_CTRL, val32);
2664 } else {
2665 val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL);
2666 val16 &= 0x7;
2667 val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) |
2668 (viq << TRXDMA_CTRL_VIQ_SHIFT) |
2669 (beq << TRXDMA_CTRL_BEQ_SHIFT) |
2670 (bkq << TRXDMA_CTRL_BKQ_SHIFT) |
2671 (mgq << TRXDMA_CTRL_MGQ_SHIFT) |
2672 (hiq << TRXDMA_CTRL_HIQ_SHIFT);
2673 rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16);
2674 }
2675
2676 priv->pipe_out[TXDESC_QUEUE_VO] =
2677 usb_sndbulkpipe(priv->udev, priv->out_ep[vop]);
2678 priv->pipe_out[TXDESC_QUEUE_VI] =
2679 usb_sndbulkpipe(priv->udev, priv->out_ep[vip]);
2680 priv->pipe_out[TXDESC_QUEUE_BE] =
2681 usb_sndbulkpipe(priv->udev, priv->out_ep[bep]);
2682 priv->pipe_out[TXDESC_QUEUE_BK] =
2683 usb_sndbulkpipe(priv->udev, priv->out_ep[bkp]);
2684 priv->pipe_out[TXDESC_QUEUE_BEACON] =
2685 usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
2686 priv->pipe_out[TXDESC_QUEUE_MGNT] =
2687 usb_sndbulkpipe(priv->udev, priv->out_ep[mgp]);
2688 priv->pipe_out[TXDESC_QUEUE_HIGH] =
2689 usb_sndbulkpipe(priv->udev, priv->out_ep[hip]);
2690 priv->pipe_out[TXDESC_QUEUE_CMD] =
2691 usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
2692 }
2693
2694 return ret;
2695 }
2696
rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv * priv,bool iqk_ok,int result[][8],int candidate,bool tx_only)2697 void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv, bool iqk_ok,
2698 int result[][8], int candidate, bool tx_only)
2699 {
2700 u32 oldval, x, tx0_a, reg;
2701 int y, tx0_c;
2702 u32 val32;
2703
2704 if (!iqk_ok)
2705 return;
2706
2707 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2708 oldval = val32 >> 22;
2709
2710 x = result[candidate][0];
2711 if ((x & 0x00000200) != 0)
2712 x = x | 0xfffffc00;
2713 tx0_a = (x * oldval) >> 8;
2714
2715 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2716 val32 &= ~0x3ff;
2717 val32 |= tx0_a;
2718 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
2719
2720 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2721 val32 &= ~BIT(31);
2722 if ((x * oldval >> 7) & 0x1)
2723 val32 |= BIT(31);
2724 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2725
2726 y = result[candidate][1];
2727 if ((y & 0x00000200) != 0)
2728 y = y | 0xfffffc00;
2729 tx0_c = (y * oldval) >> 8;
2730
2731 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE);
2732 val32 &= ~0xf0000000;
2733 val32 |= (((tx0_c & 0x3c0) >> 6) << 28);
2734 rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32);
2735
2736 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2737 val32 &= ~0x003f0000;
2738 val32 |= ((tx0_c & 0x3f) << 16);
2739 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
2740
2741 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2742 val32 &= ~BIT(29);
2743 if ((y * oldval >> 7) & 0x1)
2744 val32 |= BIT(29);
2745 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2746
2747 if (tx_only) {
2748 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
2749 return;
2750 }
2751
2752 reg = result[candidate][2];
2753
2754 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
2755 val32 &= ~0x3ff;
2756 val32 |= (reg & 0x3ff);
2757 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
2758
2759 reg = result[candidate][3] & 0x3F;
2760
2761 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
2762 val32 &= ~0xfc00;
2763 val32 |= ((reg << 10) & 0xfc00);
2764 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
2765
2766 reg = (result[candidate][3] >> 6) & 0xF;
2767
2768 val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA);
2769 val32 &= ~0xf0000000;
2770 val32 |= (reg << 28);
2771 rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32);
2772 }
2773
rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv * priv,bool iqk_ok,int result[][8],int candidate,bool tx_only)2774 void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv, bool iqk_ok,
2775 int result[][8], int candidate, bool tx_only)
2776 {
2777 u32 oldval, x, tx1_a, reg;
2778 int y, tx1_c;
2779 u32 val32;
2780
2781 if (!iqk_ok)
2782 return;
2783
2784 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2785 oldval = val32 >> 22;
2786
2787 x = result[candidate][4];
2788 if ((x & 0x00000200) != 0)
2789 x = x | 0xfffffc00;
2790 tx1_a = (x * oldval) >> 8;
2791
2792 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2793 val32 &= ~0x3ff;
2794 val32 |= tx1_a;
2795 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
2796
2797 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2798 val32 &= ~BIT(27);
2799 if ((x * oldval >> 7) & 0x1)
2800 val32 |= BIT(27);
2801 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2802
2803 y = result[candidate][5];
2804 if ((y & 0x00000200) != 0)
2805 y = y | 0xfffffc00;
2806 tx1_c = (y * oldval) >> 8;
2807
2808 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE);
2809 val32 &= ~0xf0000000;
2810 val32 |= (((tx1_c & 0x3c0) >> 6) << 28);
2811 rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32);
2812
2813 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2814 val32 &= ~0x003f0000;
2815 val32 |= ((tx1_c & 0x3f) << 16);
2816 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
2817
2818 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2819 val32 &= ~BIT(25);
2820 if ((y * oldval >> 7) & 0x1)
2821 val32 |= BIT(25);
2822 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2823
2824 if (tx_only) {
2825 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
2826 return;
2827 }
2828
2829 reg = result[candidate][6];
2830
2831 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
2832 val32 &= ~0x3ff;
2833 val32 |= (reg & 0x3ff);
2834 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
2835
2836 reg = result[candidate][7] & 0x3f;
2837
2838 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
2839 val32 &= ~0xfc00;
2840 val32 |= ((reg << 10) & 0xfc00);
2841 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
2842
2843 reg = (result[candidate][7] >> 6) & 0xf;
2844
2845 if (priv->rtl_chip == RTL8192F) {
2846 rtl8xxxu_write32_mask(priv, REG_RXIQB_EXT, 0x000000f0, reg);
2847 } else {
2848 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_RSSI_TABLE);
2849 val32 &= ~0x0000f000;
2850 val32 |= (reg << 12);
2851 rtl8xxxu_write32(priv, REG_OFDM0_AGC_RSSI_TABLE, val32);
2852 }
2853 }
2854
2855 #define MAX_TOLERANCE 5
2856
rtl8xxxu_simularity_compare(struct rtl8xxxu_priv * priv,int result[][8],int c1,int c2)2857 bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv,
2858 int result[][8], int c1, int c2)
2859 {
2860 u32 i, j, diff, simubitmap, bound = 0;
2861 int candidate[2] = {-1, -1}; /* for path A and path B */
2862 bool retval = true;
2863
2864 if (priv->tx_paths > 1)
2865 bound = 8;
2866 else
2867 bound = 4;
2868
2869 simubitmap = 0;
2870
2871 for (i = 0; i < bound; i++) {
2872 diff = (result[c1][i] > result[c2][i]) ?
2873 (result[c1][i] - result[c2][i]) :
2874 (result[c2][i] - result[c1][i]);
2875 if (diff > MAX_TOLERANCE) {
2876 if ((i == 2 || i == 6) && !simubitmap) {
2877 if (result[c1][i] + result[c1][i + 1] == 0)
2878 candidate[(i / 4)] = c2;
2879 else if (result[c2][i] + result[c2][i + 1] == 0)
2880 candidate[(i / 4)] = c1;
2881 else
2882 simubitmap = simubitmap | (1 << i);
2883 } else {
2884 simubitmap = simubitmap | (1 << i);
2885 }
2886 }
2887 }
2888
2889 if (simubitmap == 0) {
2890 for (i = 0; i < (bound / 4); i++) {
2891 if (candidate[i] >= 0) {
2892 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
2893 result[3][j] = result[candidate[i]][j];
2894 retval = false;
2895 }
2896 }
2897 return retval;
2898 } else if (!(simubitmap & 0x0f)) {
2899 /* path A OK */
2900 for (i = 0; i < 4; i++)
2901 result[3][i] = result[c1][i];
2902 } else if (!(simubitmap & 0xf0) && priv->tx_paths > 1) {
2903 /* path B OK */
2904 for (i = 4; i < 8; i++)
2905 result[3][i] = result[c1][i];
2906 }
2907
2908 return false;
2909 }
2910
rtl8xxxu_gen2_simularity_compare(struct rtl8xxxu_priv * priv,int result[][8],int c1,int c2)2911 bool rtl8xxxu_gen2_simularity_compare(struct rtl8xxxu_priv *priv,
2912 int result[][8], int c1, int c2)
2913 {
2914 u32 i, j, diff, simubitmap, bound = 0;
2915 int candidate[2] = {-1, -1}; /* for path A and path B */
2916 int tmp1, tmp2;
2917 bool retval = true;
2918
2919 if (priv->tx_paths > 1)
2920 bound = 8;
2921 else
2922 bound = 4;
2923
2924 simubitmap = 0;
2925
2926 for (i = 0; i < bound; i++) {
2927 if (i & 1) {
2928 if ((result[c1][i] & 0x00000200))
2929 tmp1 = result[c1][i] | 0xfffffc00;
2930 else
2931 tmp1 = result[c1][i];
2932
2933 if ((result[c2][i]& 0x00000200))
2934 tmp2 = result[c2][i] | 0xfffffc00;
2935 else
2936 tmp2 = result[c2][i];
2937 } else {
2938 tmp1 = result[c1][i];
2939 tmp2 = result[c2][i];
2940 }
2941
2942 diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1);
2943
2944 if (diff > MAX_TOLERANCE) {
2945 if ((i == 2 || i == 6) && !simubitmap) {
2946 if (result[c1][i] + result[c1][i + 1] == 0)
2947 candidate[(i / 4)] = c2;
2948 else if (result[c2][i] + result[c2][i + 1] == 0)
2949 candidate[(i / 4)] = c1;
2950 else
2951 simubitmap = simubitmap | (1 << i);
2952 } else {
2953 simubitmap = simubitmap | (1 << i);
2954 }
2955 }
2956 }
2957
2958 if (simubitmap == 0) {
2959 for (i = 0; i < (bound / 4); i++) {
2960 if (candidate[i] >= 0) {
2961 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
2962 result[3][j] = result[candidate[i]][j];
2963 retval = false;
2964 }
2965 }
2966 return retval;
2967 } else {
2968 if (!(simubitmap & 0x03)) {
2969 /* path A TX OK */
2970 for (i = 0; i < 2; i++)
2971 result[3][i] = result[c1][i];
2972 }
2973
2974 if (!(simubitmap & 0x0c)) {
2975 /* path A RX OK */
2976 for (i = 2; i < 4; i++)
2977 result[3][i] = result[c1][i];
2978 }
2979
2980 if (!(simubitmap & 0x30) && priv->tx_paths > 1) {
2981 /* path B TX OK */
2982 for (i = 4; i < 6; i++)
2983 result[3][i] = result[c1][i];
2984 }
2985
2986 if (!(simubitmap & 0xc0) && priv->tx_paths > 1) {
2987 /* path B RX OK */
2988 for (i = 6; i < 8; i++)
2989 result[3][i] = result[c1][i];
2990 }
2991 }
2992
2993 return false;
2994 }
2995
2996 void
rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv * priv,const u32 * reg,u32 * backup)2997 rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup)
2998 {
2999 int i;
3000
3001 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
3002 backup[i] = rtl8xxxu_read8(priv, reg[i]);
3003
3004 backup[i] = rtl8xxxu_read32(priv, reg[i]);
3005 }
3006
rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv * priv,const u32 * reg,u32 * backup)3007 void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv,
3008 const u32 *reg, u32 *backup)
3009 {
3010 int i;
3011
3012 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
3013 rtl8xxxu_write8(priv, reg[i], backup[i]);
3014
3015 rtl8xxxu_write32(priv, reg[i], backup[i]);
3016 }
3017
rtl8xxxu_save_regs(struct rtl8xxxu_priv * priv,const u32 * regs,u32 * backup,int count)3018 void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
3019 u32 *backup, int count)
3020 {
3021 int i;
3022
3023 for (i = 0; i < count; i++)
3024 backup[i] = rtl8xxxu_read32(priv, regs[i]);
3025 }
3026
rtl8xxxu_restore_regs(struct rtl8xxxu_priv * priv,const u32 * regs,u32 * backup,int count)3027 void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
3028 u32 *backup, int count)
3029 {
3030 int i;
3031
3032 for (i = 0; i < count; i++)
3033 rtl8xxxu_write32(priv, regs[i], backup[i]);
3034 }
3035
3036
rtl8xxxu_path_adda_on(struct rtl8xxxu_priv * priv,const u32 * regs,bool path_a_on)3037 void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs,
3038 bool path_a_on)
3039 {
3040 u32 path_on;
3041 int i;
3042
3043 if (priv->tx_paths == 1) {
3044 path_on = priv->fops->adda_1t_path_on;
3045 rtl8xxxu_write32(priv, regs[0], priv->fops->adda_1t_init);
3046 } else {
3047 path_on = path_a_on ? priv->fops->adda_2t_path_on_a :
3048 priv->fops->adda_2t_path_on_b;
3049
3050 rtl8xxxu_write32(priv, regs[0], path_on);
3051 }
3052
3053 for (i = 1 ; i < RTL8XXXU_ADDA_REGS ; i++)
3054 rtl8xxxu_write32(priv, regs[i], path_on);
3055 }
3056
rtl8xxxu_mac_calibration(struct rtl8xxxu_priv * priv,const u32 * regs,u32 * backup)3057 void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv,
3058 const u32 *regs, u32 *backup)
3059 {
3060 int i = 0;
3061
3062 rtl8xxxu_write8(priv, regs[i], 0x3f);
3063
3064 for (i = 1 ; i < (RTL8XXXU_MAC_REGS - 1); i++)
3065 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(3)));
3066
3067 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(5)));
3068 }
3069
rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv * priv)3070 static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv *priv)
3071 {
3072 u32 reg_eac, reg_e94, reg_e9c, reg_ea4, val32;
3073 int result = 0;
3074
3075 /* path-A IQK setting */
3076 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1f);
3077 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1f);
3078 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140102);
3079
3080 val32 = (priv->rf_paths > 1) ? 0x28160202 :
3081 /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */
3082 0x28160502;
3083 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32);
3084
3085 /* path-B IQK setting */
3086 if (priv->rf_paths > 1) {
3087 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x10008c22);
3088 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x10008c22);
3089 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140102);
3090 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160202);
3091 }
3092
3093 /* LO calibration setting */
3094 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x001028d1);
3095
3096 /* One shot, path A LOK & IQK */
3097 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
3098 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
3099
3100 mdelay(1);
3101
3102 /* Check failed */
3103 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3104 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
3105 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
3106 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
3107
3108 if (!(reg_eac & BIT(28)) &&
3109 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
3110 ((reg_e9c & 0x03ff0000) != 0x00420000))
3111 result |= 0x01;
3112 else /* If TX not OK, ignore RX */
3113 goto out;
3114
3115 /* If TX is OK, check whether RX is OK */
3116 if (!(reg_eac & BIT(27)) &&
3117 ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
3118 ((reg_eac & 0x03ff0000) != 0x00360000))
3119 result |= 0x02;
3120 else
3121 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n",
3122 __func__);
3123 out:
3124 return result;
3125 }
3126
rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv * priv)3127 static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv *priv)
3128 {
3129 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3130 int result = 0;
3131
3132 /* One shot, path B LOK & IQK */
3133 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002);
3134 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000);
3135
3136 mdelay(1);
3137
3138 /* Check failed */
3139 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3140 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3141 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3142 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3143 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3144
3145 if (!(reg_eac & BIT(31)) &&
3146 ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
3147 ((reg_ebc & 0x03ff0000) != 0x00420000))
3148 result |= 0x01;
3149 else
3150 goto out;
3151
3152 if (!(reg_eac & BIT(30)) &&
3153 (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) &&
3154 (((reg_ecc & 0x03ff0000) >> 16) != 0x36))
3155 result |= 0x02;
3156 else
3157 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
3158 __func__);
3159 out:
3160 return result;
3161 }
3162
rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv * priv,int result[][8],int t)3163 static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
3164 int result[][8], int t)
3165 {
3166 struct device *dev = &priv->udev->dev;
3167 u32 i, val32;
3168 int path_a_ok, path_b_ok;
3169 int retry = 2;
3170 static const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
3171 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
3172 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
3173 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
3174 REG_TX_OFDM_BBON, REG_TX_TO_RX,
3175 REG_TX_TO_TX, REG_RX_CCK,
3176 REG_RX_OFDM, REG_RX_WAIT_RIFS,
3177 REG_RX_TO_RX, REG_STANDBY,
3178 REG_SLEEP, REG_PMPD_ANAEN
3179 };
3180 static const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
3181 REG_TXPAUSE, REG_BEACON_CTRL,
3182 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
3183 };
3184 static const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
3185 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
3186 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
3187 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
3188 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
3189 };
3190
3191 /*
3192 * Note: IQ calibration must be performed after loading
3193 * PHY_REG.txt , and radio_a, radio_b.txt
3194 */
3195
3196 if (t == 0) {
3197 /* Save ADDA parameters, turn Path A ADDA on */
3198 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
3199 RTL8XXXU_ADDA_REGS);
3200 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
3201 rtl8xxxu_save_regs(priv, iqk_bb_regs,
3202 priv->bb_backup, RTL8XXXU_BB_REGS);
3203 }
3204
3205 rtl8xxxu_path_adda_on(priv, adda_regs, true);
3206
3207 if (t == 0) {
3208 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1);
3209 if (val32 & FPGA0_HSSI_PARM1_PI)
3210 priv->pi_enabled = 1;
3211 }
3212
3213 if (!priv->pi_enabled) {
3214 /* Switch BB to PI mode to do IQ Calibration. */
3215 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100);
3216 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100);
3217 }
3218
3219 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
3220 val32 &= ~FPGA_RF_MODE_CCK;
3221 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
3222
3223 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
3224 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
3225 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
3226
3227 if (!priv->no_pape) {
3228 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL);
3229 val32 |= (FPGA0_RF_PAPE |
3230 (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
3231 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
3232 }
3233
3234 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE);
3235 val32 &= ~BIT(10);
3236 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32);
3237 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);
3238 val32 &= ~BIT(10);
3239 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32);
3240
3241 if (priv->tx_paths > 1) {
3242 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
3243 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000);
3244 }
3245
3246 /* MAC settings */
3247 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
3248
3249 /* Page B init */
3250 rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x00080000);
3251
3252 if (priv->tx_paths > 1)
3253 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x00080000);
3254
3255 /* IQ calibration setting */
3256 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
3257 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
3258 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
3259
3260 for (i = 0; i < retry; i++) {
3261 path_a_ok = rtl8xxxu_iqk_path_a(priv);
3262 if (path_a_ok == 0x03) {
3263 val32 = rtl8xxxu_read32(priv,
3264 REG_TX_POWER_BEFORE_IQK_A);
3265 result[t][0] = (val32 >> 16) & 0x3ff;
3266 val32 = rtl8xxxu_read32(priv,
3267 REG_TX_POWER_AFTER_IQK_A);
3268 result[t][1] = (val32 >> 16) & 0x3ff;
3269 val32 = rtl8xxxu_read32(priv,
3270 REG_RX_POWER_BEFORE_IQK_A_2);
3271 result[t][2] = (val32 >> 16) & 0x3ff;
3272 val32 = rtl8xxxu_read32(priv,
3273 REG_RX_POWER_AFTER_IQK_A_2);
3274 result[t][3] = (val32 >> 16) & 0x3ff;
3275 break;
3276 } else if (i == (retry - 1) && path_a_ok == 0x01) {
3277 /* TX IQK OK */
3278 dev_dbg(dev, "%s: Path A IQK Only Tx Success!!\n",
3279 __func__);
3280
3281 val32 = rtl8xxxu_read32(priv,
3282 REG_TX_POWER_BEFORE_IQK_A);
3283 result[t][0] = (val32 >> 16) & 0x3ff;
3284 val32 = rtl8xxxu_read32(priv,
3285 REG_TX_POWER_AFTER_IQK_A);
3286 result[t][1] = (val32 >> 16) & 0x3ff;
3287 }
3288 }
3289
3290 if (!path_a_ok)
3291 dev_dbg(dev, "%s: Path A IQK failed!\n", __func__);
3292
3293 if (priv->tx_paths > 1) {
3294 /*
3295 * Path A into standby
3296 */
3297 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0);
3298 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
3299 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
3300
3301 /* Turn Path B ADDA on */
3302 rtl8xxxu_path_adda_on(priv, adda_regs, false);
3303
3304 for (i = 0; i < retry; i++) {
3305 path_b_ok = rtl8xxxu_iqk_path_b(priv);
3306 if (path_b_ok == 0x03) {
3307 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3308 result[t][4] = (val32 >> 16) & 0x3ff;
3309 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3310 result[t][5] = (val32 >> 16) & 0x3ff;
3311 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3312 result[t][6] = (val32 >> 16) & 0x3ff;
3313 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3314 result[t][7] = (val32 >> 16) & 0x3ff;
3315 break;
3316 } else if (i == (retry - 1) && path_b_ok == 0x01) {
3317 /* TX IQK OK */
3318 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3319 result[t][4] = (val32 >> 16) & 0x3ff;
3320 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3321 result[t][5] = (val32 >> 16) & 0x3ff;
3322 }
3323 }
3324
3325 if (!path_b_ok)
3326 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
3327 }
3328
3329 /* Back to BB mode, load original value */
3330 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0);
3331
3332 if (t) {
3333 if (!priv->pi_enabled) {
3334 /*
3335 * Switch back BB to SI mode after finishing
3336 * IQ Calibration
3337 */
3338 val32 = 0x01000000;
3339 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32);
3340 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32);
3341 }
3342
3343 /* Reload ADDA power saving parameters */
3344 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
3345 RTL8XXXU_ADDA_REGS);
3346
3347 /* Reload MAC parameters */
3348 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
3349
3350 /* Reload BB parameters */
3351 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
3352 priv->bb_backup, RTL8XXXU_BB_REGS);
3353
3354 /* Restore RX initial gain */
3355 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3);
3356
3357 if (priv->tx_paths > 1) {
3358 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM,
3359 0x00032ed3);
3360 }
3361
3362 /* Load 0xe30 IQC default value */
3363 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
3364 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
3365 }
3366 }
3367
rtl8xxxu_gen2_prepare_calibrate(struct rtl8xxxu_priv * priv,u8 start)3368 void rtl8xxxu_gen2_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start)
3369 {
3370 struct h2c_cmd h2c;
3371
3372 memset(&h2c, 0, sizeof(struct h2c_cmd));
3373 h2c.bt_wlan_calibration.cmd = H2C_8723B_BT_WLAN_CALIBRATION;
3374 h2c.bt_wlan_calibration.data = start;
3375
3376 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_wlan_calibration));
3377 }
3378
rtl8xxxu_gen1_phy_iq_calibrate(struct rtl8xxxu_priv * priv)3379 void rtl8xxxu_gen1_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
3380 {
3381 struct device *dev = &priv->udev->dev;
3382 int result[4][8]; /* last is final result */
3383 int i, candidate;
3384 bool path_a_ok, path_b_ok;
3385 u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
3386 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3387 s32 reg_tmp = 0;
3388 bool simu;
3389
3390 memset(result, 0, sizeof(result));
3391 candidate = -1;
3392
3393 path_a_ok = false;
3394 path_b_ok = false;
3395
3396 rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
3397
3398 for (i = 0; i < 3; i++) {
3399 rtl8xxxu_phy_iqcalibrate(priv, result, i);
3400
3401 if (i == 1) {
3402 simu = rtl8xxxu_simularity_compare(priv, result, 0, 1);
3403 if (simu) {
3404 candidate = 0;
3405 break;
3406 }
3407 }
3408
3409 if (i == 2) {
3410 simu = rtl8xxxu_simularity_compare(priv, result, 0, 2);
3411 if (simu) {
3412 candidate = 0;
3413 break;
3414 }
3415
3416 simu = rtl8xxxu_simularity_compare(priv, result, 1, 2);
3417 if (simu) {
3418 candidate = 1;
3419 } else {
3420 for (i = 0; i < 8; i++)
3421 reg_tmp += result[3][i];
3422
3423 if (reg_tmp)
3424 candidate = 3;
3425 else
3426 candidate = -1;
3427 }
3428 }
3429 }
3430
3431 for (i = 0; i < 4; i++) {
3432 reg_e94 = result[i][0];
3433 reg_e9c = result[i][1];
3434 reg_ea4 = result[i][2];
3435 reg_eac = result[i][3];
3436 reg_eb4 = result[i][4];
3437 reg_ebc = result[i][5];
3438 reg_ec4 = result[i][6];
3439 reg_ecc = result[i][7];
3440 }
3441
3442 if (candidate >= 0) {
3443 reg_e94 = result[candidate][0];
3444 priv->rege94 = reg_e94;
3445 reg_e9c = result[candidate][1];
3446 priv->rege9c = reg_e9c;
3447 reg_ea4 = result[candidate][2];
3448 reg_eac = result[candidate][3];
3449 reg_eb4 = result[candidate][4];
3450 priv->regeb4 = reg_eb4;
3451 reg_ebc = result[candidate][5];
3452 priv->regebc = reg_ebc;
3453 reg_ec4 = result[candidate][6];
3454 reg_ecc = result[candidate][7];
3455 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
3456 dev_dbg(dev,
3457 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x ecc=%x\n",
3458 __func__, reg_e94, reg_e9c,
3459 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
3460 path_a_ok = true;
3461 path_b_ok = true;
3462 } else {
3463 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
3464 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
3465 }
3466
3467 if (reg_e94 && candidate >= 0)
3468 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
3469 candidate, (reg_ea4 == 0));
3470
3471 if (priv->tx_paths > 1 && reg_eb4)
3472 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
3473 candidate, (reg_ec4 == 0));
3474
3475 rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg,
3476 priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
3477 }
3478
rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv * priv)3479 void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv)
3480 {
3481 u32 val32;
3482 u32 rf_amode, rf_bmode = 0, lstf;
3483
3484 /* Check continuous TX and Packet TX */
3485 lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
3486
3487 if (lstf & OFDM_LSTF_MASK) {
3488 /* Disable all continuous TX */
3489 val32 = lstf & ~OFDM_LSTF_MASK;
3490 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
3491
3492 /* Read original RF mode Path A */
3493 rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_AC);
3494
3495 /* Set RF mode to standby Path A */
3496 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC,
3497 (rf_amode & 0x8ffff) | 0x10000);
3498
3499 /* Path-B */
3500 if (priv->tx_paths > 1) {
3501 rf_bmode = rtl8xxxu_read_rfreg(priv, RF_B,
3502 RF6052_REG_AC);
3503
3504 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
3505 (rf_bmode & 0x8ffff) | 0x10000);
3506 }
3507 } else {
3508 /* Deal with Packet TX case */
3509 /* block all queues */
3510 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
3511 }
3512
3513 /* Start LC calibration */
3514 if (priv->fops->has_s0s1)
3515 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdfbe0);
3516 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG);
3517 val32 |= 0x08000;
3518 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32);
3519
3520 msleep(100);
3521
3522 if (priv->fops->has_s0s1)
3523 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdffe0);
3524
3525 /* Restore original parameters */
3526 if (lstf & OFDM_LSTF_MASK) {
3527 /* Path-A */
3528 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf);
3529 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, rf_amode);
3530
3531 /* Path-B */
3532 if (priv->tx_paths > 1)
3533 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
3534 rf_bmode);
3535 } else /* Deal with Packet TX case */
3536 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
3537 }
3538
rtl8xxxu_set_mac(struct rtl8xxxu_priv * priv,int port_num)3539 static int rtl8xxxu_set_mac(struct rtl8xxxu_priv *priv, int port_num)
3540 {
3541 int i;
3542 u16 reg;
3543
3544 switch (port_num) {
3545 case 0:
3546 reg = REG_MACID;
3547 break;
3548 case 1:
3549 reg = REG_MACID1;
3550 break;
3551 default:
3552 WARN_ONCE(1, "%s: invalid port_num\n", __func__);
3553 return -EINVAL;
3554 }
3555
3556 for (i = 0; i < ETH_ALEN; i++)
3557 rtl8xxxu_write8(priv, reg + i, priv->vifs[port_num]->addr[i]);
3558
3559 return 0;
3560 }
3561
rtl8xxxu_set_bssid(struct rtl8xxxu_priv * priv,const u8 * bssid,int port_num)3562 static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv *priv, const u8 *bssid, int port_num)
3563 {
3564 int i;
3565 u16 reg;
3566
3567 dev_dbg(&priv->udev->dev, "%s: (%pM)\n", __func__, bssid);
3568
3569 switch (port_num) {
3570 case 0:
3571 reg = REG_BSSID;
3572 break;
3573 case 1:
3574 reg = REG_BSSID1;
3575 break;
3576 default:
3577 WARN_ONCE(1, "%s: invalid port_num\n", __func__);
3578 return -EINVAL;
3579 }
3580
3581 for (i = 0; i < ETH_ALEN; i++)
3582 rtl8xxxu_write8(priv, reg + i, bssid[i]);
3583
3584 return 0;
3585 }
3586
3587 static void
rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv * priv,u8 ampdu_factor)3588 rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv *priv, u8 ampdu_factor)
3589 {
3590 u8 vals[4] = { 0x41, 0xa8, 0x72, 0xb9 };
3591 u8 max_agg = 0xf;
3592 int i;
3593
3594 ampdu_factor = 1 << (ampdu_factor + 2);
3595 if (ampdu_factor > max_agg)
3596 ampdu_factor = max_agg;
3597
3598 for (i = 0; i < 4; i++) {
3599 if ((vals[i] & 0xf0) > (ampdu_factor << 4))
3600 vals[i] = (vals[i] & 0x0f) | (ampdu_factor << 4);
3601
3602 if ((vals[i] & 0x0f) > ampdu_factor)
3603 vals[i] = (vals[i] & 0xf0) | ampdu_factor;
3604
3605 rtl8xxxu_write8(priv, REG_AGGLEN_LMT + i, vals[i]);
3606 }
3607 }
3608
rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv * priv,u8 density)3609 static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv *priv, u8 density)
3610 {
3611 u8 val8;
3612
3613 val8 = rtl8xxxu_read8(priv, REG_AMPDU_MIN_SPACE);
3614 val8 &= 0xf8;
3615 val8 |= density;
3616 rtl8xxxu_write8(priv, REG_AMPDU_MIN_SPACE, val8);
3617 }
3618
rtl8xxxu_active_to_emu(struct rtl8xxxu_priv * priv)3619 static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv *priv)
3620 {
3621 u8 val8;
3622 int count, ret = 0;
3623
3624 /* Start of rtl8723AU_card_enable_flow */
3625 /* Act to Cardemu sequence*/
3626 /* Turn off RF */
3627 rtl8xxxu_write8(priv, REG_RF_CTRL, 0);
3628
3629 /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */
3630 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
3631 val8 &= ~LEDCFG2_DPDT_SELECT;
3632 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
3633
3634 /* 0x0005[1] = 1 turn off MAC by HW state machine*/
3635 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3636 val8 |= BIT(1);
3637 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3638
3639 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3640 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3641 if ((val8 & BIT(1)) == 0)
3642 break;
3643 udelay(10);
3644 }
3645
3646 if (!count) {
3647 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
3648 __func__);
3649 ret = -EBUSY;
3650 goto exit;
3651 }
3652
3653 /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
3654 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
3655 val8 |= SYS_ISO_ANALOG_IPS;
3656 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
3657
3658 /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
3659 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
3660 val8 &= ~LDOA15_ENABLE;
3661 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
3662
3663 exit:
3664 return ret;
3665 }
3666
rtl8xxxu_active_to_lps(struct rtl8xxxu_priv * priv)3667 int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv)
3668 {
3669 u8 val8;
3670 u8 val32;
3671 int count, ret = 0;
3672
3673 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
3674
3675 /*
3676 * Poll - wait for RX packet to complete
3677 */
3678 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3679 val32 = rtl8xxxu_read32(priv, 0x5f8);
3680 if (!val32)
3681 break;
3682 udelay(10);
3683 }
3684
3685 if (!count) {
3686 dev_warn(&priv->udev->dev,
3687 "%s: RX poll timed out (0x05f8)\n", __func__);
3688 ret = -EBUSY;
3689 goto exit;
3690 }
3691
3692 /* Disable CCK and OFDM, clock gated */
3693 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
3694 val8 &= ~SYS_FUNC_BBRSTB;
3695 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
3696
3697 udelay(2);
3698
3699 /* Reset baseband */
3700 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
3701 val8 &= ~SYS_FUNC_BB_GLB_RSTN;
3702 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
3703
3704 /* Reset MAC TRX */
3705 val8 = rtl8xxxu_read8(priv, REG_CR);
3706 val8 = CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE;
3707 rtl8xxxu_write8(priv, REG_CR, val8);
3708
3709 /* Reset MAC TRX */
3710 val8 = rtl8xxxu_read8(priv, REG_CR + 1);
3711 val8 &= ~BIT(1); /* CR_SECURITY_ENABLE */
3712 rtl8xxxu_write8(priv, REG_CR + 1, val8);
3713
3714 /* Respond TX OK to scheduler */
3715 val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST);
3716 val8 |= DUAL_TSF_TX_OK;
3717 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8);
3718
3719 exit:
3720 return ret;
3721 }
3722
rtl8xxxu_disabled_to_emu(struct rtl8xxxu_priv * priv)3723 void rtl8xxxu_disabled_to_emu(struct rtl8xxxu_priv *priv)
3724 {
3725 u8 val8;
3726
3727 /* Clear suspend enable and power down enable*/
3728 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3729 val8 &= ~(BIT(3) | BIT(7));
3730 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3731
3732 /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/
3733 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
3734 val8 &= ~BIT(0);
3735 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
3736
3737 /* 0x04[12:11] = 11 enable WL suspend*/
3738 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3739 val8 &= ~(BIT(3) | BIT(4));
3740 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3741 }
3742
rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv * priv)3743 static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv *priv)
3744 {
3745 u8 val8;
3746
3747 /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */
3748 rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20);
3749
3750 /* 0x04[12:11] = 01 enable WL suspend */
3751 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3752 val8 &= ~BIT(4);
3753 val8 |= BIT(3);
3754 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3755
3756 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3757 val8 |= BIT(7);
3758 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3759
3760 /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */
3761 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
3762 val8 |= BIT(0);
3763 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
3764
3765 return 0;
3766 }
3767
rtl8xxxu_flush_fifo(struct rtl8xxxu_priv * priv)3768 int rtl8xxxu_flush_fifo(struct rtl8xxxu_priv *priv)
3769 {
3770 struct device *dev = &priv->udev->dev;
3771 u32 val32;
3772 int retry, retval;
3773
3774 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
3775
3776 val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM);
3777 val32 |= RXPKT_NUM_RW_RELEASE_EN;
3778 rtl8xxxu_write32(priv, REG_RXPKT_NUM, val32);
3779
3780 retry = 100;
3781 retval = -EBUSY;
3782
3783 do {
3784 val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM);
3785 if (val32 & RXPKT_NUM_RXDMA_IDLE) {
3786 retval = 0;
3787 break;
3788 }
3789 } while (retry--);
3790
3791 rtl8xxxu_write16(priv, REG_RQPN_NPQ, 0);
3792 rtl8xxxu_write32(priv, REG_RQPN, 0x80000000);
3793 mdelay(2);
3794
3795 if (!retry)
3796 dev_warn(dev, "Failed to flush FIFO\n");
3797
3798 return retval;
3799 }
3800
rtl8xxxu_gen1_usb_quirks(struct rtl8xxxu_priv * priv)3801 void rtl8xxxu_gen1_usb_quirks(struct rtl8xxxu_priv *priv)
3802 {
3803 /* Fix USB interface interference issue */
3804 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
3805 rtl8xxxu_write8(priv, 0xfe41, 0x8d);
3806 rtl8xxxu_write8(priv, 0xfe42, 0x80);
3807 /*
3808 * This sets TXDMA_OFFSET_DROP_DATA_EN (bit 9) as well as bits
3809 * 8 and 5, for which I have found no documentation.
3810 */
3811 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, 0xfd0320);
3812
3813 /*
3814 * Solve too many protocol error on USB bus.
3815 * Can't do this for 8188/8192 UMC A cut parts
3816 */
3817 if (!(!priv->chip_cut && priv->vendor_umc)) {
3818 rtl8xxxu_write8(priv, 0xfe40, 0xe6);
3819 rtl8xxxu_write8(priv, 0xfe41, 0x94);
3820 rtl8xxxu_write8(priv, 0xfe42, 0x80);
3821
3822 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
3823 rtl8xxxu_write8(priv, 0xfe41, 0x19);
3824 rtl8xxxu_write8(priv, 0xfe42, 0x80);
3825
3826 rtl8xxxu_write8(priv, 0xfe40, 0xe5);
3827 rtl8xxxu_write8(priv, 0xfe41, 0x91);
3828 rtl8xxxu_write8(priv, 0xfe42, 0x80);
3829
3830 rtl8xxxu_write8(priv, 0xfe40, 0xe2);
3831 rtl8xxxu_write8(priv, 0xfe41, 0x81);
3832 rtl8xxxu_write8(priv, 0xfe42, 0x80);
3833 }
3834 }
3835
rtl8xxxu_gen2_usb_quirks(struct rtl8xxxu_priv * priv)3836 void rtl8xxxu_gen2_usb_quirks(struct rtl8xxxu_priv *priv)
3837 {
3838 u32 val32;
3839
3840 val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK);
3841 val32 |= TXDMA_OFFSET_DROP_DATA_EN;
3842 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32);
3843 }
3844
rtl8xxxu_power_off(struct rtl8xxxu_priv * priv)3845 void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv)
3846 {
3847 u8 val8;
3848 u16 val16;
3849 u32 val32;
3850
3851 /*
3852 * Workaround for 8188RU LNA power leakage problem.
3853 */
3854 if (priv->rtl_chip == RTL8188R) {
3855 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
3856 val32 |= BIT(1);
3857 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
3858 }
3859
3860 rtl8xxxu_flush_fifo(priv);
3861
3862 rtl8xxxu_active_to_lps(priv);
3863
3864 /* Turn off RF */
3865 rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00);
3866
3867 /* Reset Firmware if running in RAM */
3868 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
3869 rtl8xxxu_firmware_self_reset(priv);
3870
3871 /* Reset MCU */
3872 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3873 val16 &= ~SYS_FUNC_CPU_ENABLE;
3874 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3875
3876 /* Reset MCU ready status */
3877 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
3878
3879 rtl8xxxu_active_to_emu(priv);
3880 rtl8xxxu_emu_to_disabled(priv);
3881
3882 /* Reset MCU IO Wrapper */
3883 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
3884 val8 &= ~BIT(0);
3885 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
3886
3887 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
3888 val8 |= BIT(0);
3889 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
3890
3891 /* RSV_CTRL 0x1C[7:0] = 0x0e lock ISO/CLK/Power control register */
3892 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e);
3893 }
3894
rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv * priv,u8 arg1,u8 arg2,u8 arg3,u8 arg4,u8 arg5)3895 void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv *priv,
3896 u8 arg1, u8 arg2, u8 arg3, u8 arg4, u8 arg5)
3897 {
3898 struct h2c_cmd h2c;
3899
3900 memset(&h2c, 0, sizeof(struct h2c_cmd));
3901 h2c.b_type_dma.cmd = H2C_8723B_B_TYPE_TDMA;
3902 h2c.b_type_dma.data1 = arg1;
3903 h2c.b_type_dma.data2 = arg2;
3904 h2c.b_type_dma.data3 = arg3;
3905 h2c.b_type_dma.data4 = arg4;
3906 h2c.b_type_dma.data5 = arg5;
3907 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.b_type_dma));
3908 }
3909
rtl8xxxu_gen2_disable_rf(struct rtl8xxxu_priv * priv)3910 void rtl8xxxu_gen2_disable_rf(struct rtl8xxxu_priv *priv)
3911 {
3912 u32 val32;
3913
3914 val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA);
3915 val32 &= ~(BIT(22) | BIT(23));
3916 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32);
3917 }
3918
rtl8xxxu_init_queue_reserved_page(struct rtl8xxxu_priv * priv)3919 static void rtl8xxxu_init_queue_reserved_page(struct rtl8xxxu_priv *priv)
3920 {
3921 struct rtl8xxxu_fileops *fops = priv->fops;
3922 u32 hq, lq, nq, eq, pubq;
3923 u32 val32;
3924
3925 hq = 0;
3926 lq = 0;
3927 nq = 0;
3928 eq = 0;
3929 pubq = 0;
3930
3931 if (priv->ep_tx_high_queue)
3932 hq = fops->page_num_hi;
3933 if (priv->ep_tx_low_queue)
3934 lq = fops->page_num_lo;
3935 if (priv->ep_tx_normal_queue)
3936 nq = fops->page_num_norm;
3937
3938 val32 = (nq << RQPN_NPQ_SHIFT) | (eq << RQPN_EPQ_SHIFT);
3939 rtl8xxxu_write32(priv, REG_RQPN_NPQ, val32);
3940
3941 pubq = fops->total_page_num - hq - lq - nq - 1;
3942
3943 val32 = RQPN_LOAD;
3944 val32 |= (hq << RQPN_HI_PQ_SHIFT);
3945 val32 |= (lq << RQPN_LO_PQ_SHIFT);
3946 val32 |= (pubq << RQPN_PUB_PQ_SHIFT);
3947
3948 rtl8xxxu_write32(priv, REG_RQPN, val32);
3949 }
3950
rtl8xxxu_init_burst(struct rtl8xxxu_priv * priv)3951 void rtl8xxxu_init_burst(struct rtl8xxxu_priv *priv)
3952 {
3953 u8 val8;
3954
3955 /*
3956 * For USB high speed set 512B packets
3957 */
3958 val8 = rtl8xxxu_read8(priv, REG_RXDMA_PRO_8723B);
3959 u8p_replace_bits(&val8, 1, RXDMA_PRO_DMA_BURST_SIZE);
3960 u8p_replace_bits(&val8, 3, RXDMA_PRO_DMA_BURST_CNT);
3961 val8 |= RXDMA_PRO_DMA_MODE;
3962 rtl8xxxu_write8(priv, REG_RXDMA_PRO_8723B, val8);
3963
3964 /*
3965 * Enable single packet AMPDU
3966 */
3967 val8 = rtl8xxxu_read8(priv, REG_HT_SINGLE_AMPDU_8723B);
3968 val8 |= HT_SINGLE_AMPDU_ENABLE;
3969 rtl8xxxu_write8(priv, REG_HT_SINGLE_AMPDU_8723B, val8);
3970
3971 rtl8xxxu_write16(priv, REG_MAX_AGGR_NUM, priv->fops->max_aggr_num);
3972 rtl8xxxu_write8(priv, REG_AMPDU_MAX_TIME_8723B,
3973 priv->fops->ampdu_max_time);
3974 rtl8xxxu_write32(priv, REG_AGGLEN_LMT, 0xffffffff);
3975 rtl8xxxu_write8(priv, REG_RX_PKT_LIMIT, 0x18);
3976 rtl8xxxu_write8(priv, REG_PIFS, 0x00);
3977 if (priv->rtl_chip == RTL8188F || priv->rtl_chip == RTL8710B ||
3978 priv->rtl_chip == RTL8192F) {
3979 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, FWHW_TXQ_CTRL_AMPDU_RETRY);
3980 rtl8xxxu_write32(priv, REG_FAST_EDCA_CTRL, 0x03086666);
3981 }
3982 rtl8xxxu_write8(priv, REG_USTIME_TSF_8723B, priv->fops->ustime_tsf_edca);
3983 rtl8xxxu_write8(priv, REG_USTIME_EDCA, priv->fops->ustime_tsf_edca);
3984
3985 /* to prevent mac is reseted by bus. */
3986 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL);
3987 val8 |= RSV_CTRL_WLOCK_1C | RSV_CTRL_DIS_PRST;
3988 rtl8xxxu_write8(priv, REG_RSV_CTRL, val8);
3989 }
3990
rtl8xxxu_acquire_macid(struct rtl8xxxu_priv * priv)3991 static u8 rtl8xxxu_acquire_macid(struct rtl8xxxu_priv *priv)
3992 {
3993 u8 macid;
3994
3995 macid = find_first_zero_bit(priv->mac_id_map, RTL8XXXU_MAX_MAC_ID_NUM);
3996 if (macid < RTL8XXXU_MAX_MAC_ID_NUM)
3997 set_bit(macid, priv->mac_id_map);
3998
3999 return macid;
4000 }
4001
rtl8xxxu_release_macid(struct rtl8xxxu_priv * priv,u8 macid)4002 static void rtl8xxxu_release_macid(struct rtl8xxxu_priv *priv, u8 macid)
4003 {
4004 clear_bit(macid, priv->mac_id_map);
4005 }
4006
rtl8xxxu_get_macid(struct rtl8xxxu_priv * priv,struct ieee80211_sta * sta)4007 static inline u8 rtl8xxxu_get_macid(struct rtl8xxxu_priv *priv,
4008 struct ieee80211_sta *sta)
4009 {
4010 struct rtl8xxxu_sta_info *sta_info;
4011
4012 if (!sta)
4013 return 0;
4014
4015 sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv;
4016 if (!sta_info)
4017 return 0;
4018
4019 return sta_info->macid;
4020 }
4021
rtl8xxxu_init_device(struct ieee80211_hw * hw)4022 static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
4023 {
4024 struct rtl8xxxu_priv *priv = hw->priv;
4025 struct device *dev = &priv->udev->dev;
4026 struct rtl8xxxu_fileops *fops = priv->fops;
4027 bool macpower;
4028 int ret;
4029 u8 val8;
4030 u16 val16;
4031 u32 val32;
4032
4033 /* Check if MAC is already powered on */
4034 val8 = rtl8xxxu_read8(priv, REG_CR);
4035 val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR);
4036
4037 /*
4038 * Fix 92DU-VC S3 hang with the reason is that secondary mac is not
4039 * initialized. First MAC returns 0xea, second MAC returns 0x00
4040 */
4041 if (val8 == 0xea || !(val16 & SYS_CLK_MAC_CLK_ENABLE))
4042 macpower = false;
4043 else
4044 macpower = true;
4045
4046 if (fops->needs_full_init)
4047 macpower = false;
4048
4049 ret = fops->power_on(priv);
4050 if (ret < 0) {
4051 dev_warn(dev, "%s: Failed power on\n", __func__);
4052 goto exit;
4053 }
4054
4055 if (!macpower)
4056 rtl8xxxu_init_queue_reserved_page(priv);
4057
4058 ret = rtl8xxxu_init_queue_priority(priv);
4059 dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret);
4060 if (ret)
4061 goto exit;
4062
4063 /*
4064 * Set RX page boundary
4065 */
4066 rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, fops->trxff_boundary);
4067
4068 for (int retry = 5; retry >= 0 ; retry--) {
4069 ret = rtl8xxxu_download_firmware(priv);
4070 dev_dbg(dev, "%s: download_firmware %i\n", __func__, ret);
4071 if (ret != -EAGAIN)
4072 break;
4073 if (retry)
4074 dev_dbg(dev, "%s: retry firmware download\n", __func__);
4075 }
4076 if (ret)
4077 goto exit;
4078 ret = rtl8xxxu_start_firmware(priv);
4079 dev_dbg(dev, "%s: start_firmware %i\n", __func__, ret);
4080 if (ret)
4081 goto exit;
4082
4083 if (fops->phy_init_antenna_selection)
4084 fops->phy_init_antenna_selection(priv);
4085
4086 ret = rtl8xxxu_init_mac(priv);
4087
4088 dev_dbg(dev, "%s: init_mac %i\n", __func__, ret);
4089 if (ret)
4090 goto exit;
4091
4092 ret = rtl8xxxu_init_phy_bb(priv);
4093 dev_dbg(dev, "%s: init_phy_bb %i\n", __func__, ret);
4094 if (ret)
4095 goto exit;
4096
4097 ret = fops->init_phy_rf(priv);
4098 if (ret)
4099 goto exit;
4100
4101 /* Mac APLL Setting */
4102 if (priv->rtl_chip == RTL8192F)
4103 rtl8xxxu_write16_set(priv, REG_AFE_CTRL4, BIT(4) | BIT(15));
4104
4105 /* RFSW Control - clear bit 14 ?? */
4106 if (priv->rtl_chip != RTL8723B && priv->rtl_chip != RTL8192E &&
4107 priv->rtl_chip != RTL8188E && priv->rtl_chip != RTL8710B &&
4108 priv->rtl_chip != RTL8192F)
4109 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003);
4110
4111 val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW |
4112 FPGA0_RF_ANTSWB |
4113 ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB) << FPGA0_RF_BD_CTRL_SHIFT);
4114 if (!priv->no_pape) {
4115 val32 |= (FPGA0_RF_PAPE |
4116 (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
4117 }
4118 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
4119
4120 /* 0x860[6:5]= 00 - why? - this sets antenna B */
4121 if (priv->rtl_chip != RTL8192E && priv->rtl_chip != RTL8188E &&
4122 priv->rtl_chip != RTL8710B && priv->rtl_chip != RTL8192F)
4123 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66f60210);
4124
4125 if (!macpower) {
4126 /*
4127 * Set TX buffer boundary
4128 */
4129 val8 = fops->total_page_num + 1;
4130
4131 rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8);
4132 rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8);
4133 rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8);
4134 rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8);
4135 rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8);
4136 }
4137
4138 /*
4139 * The vendor drivers set PBP for all devices, except 8192e.
4140 * There is no explanation for this in any of the sources.
4141 */
4142 val8 = (fops->pbp_rx << PBP_PAGE_SIZE_RX_SHIFT) |
4143 (fops->pbp_tx << PBP_PAGE_SIZE_TX_SHIFT);
4144 if (priv->rtl_chip != RTL8192E)
4145 rtl8xxxu_write8(priv, REG_PBP, val8);
4146
4147 dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
4148 if (!macpower) {
4149 ret = fops->llt_init(priv);
4150 if (ret) {
4151 dev_warn(dev, "%s: LLT table init failed\n", __func__);
4152 goto exit;
4153 }
4154
4155 /*
4156 * Chip specific quirks
4157 */
4158 fops->usb_quirks(priv);
4159
4160 /*
4161 * Enable TX report and TX report timer for 8723bu/8188eu/...
4162 */
4163 if (fops->has_tx_report) {
4164 /*
4165 * The RTL8188EU has two types of TX reports:
4166 * rpt_sel=1:
4167 * One report for one frame. We can use this for frames
4168 * with IEEE80211_TX_CTL_REQ_TX_STATUS.
4169 * rpt_sel=2:
4170 * One report for many frames transmitted over a period
4171 * of time. (This is what REG_TX_REPORT_TIME is for.) The
4172 * report includes the number of frames transmitted
4173 * successfully, and the number of unsuccessful
4174 * transmissions. We use this for software rate control.
4175 *
4176 * Bit 0 of REG_TX_REPORT_CTRL is required for both types.
4177 * Bit 1 (TX_REPORT_CTRL_TIMER_ENABLE) is required for
4178 * type 2.
4179 */
4180 val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL);
4181 if (priv->rtl_chip == RTL8188E)
4182 val8 |= BIT(0);
4183 val8 |= TX_REPORT_CTRL_TIMER_ENABLE;
4184 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8);
4185 /* Set MAX RPT MACID */
4186 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL + 1, 0x02);
4187 /* TX report Timer. Unit: 32us */
4188 rtl8xxxu_write16(priv, REG_TX_REPORT_TIME, 0xcdf0);
4189
4190 /* tmp ps ? */
4191 val8 = rtl8xxxu_read8(priv, 0xa3);
4192 val8 &= 0xf8;
4193 rtl8xxxu_write8(priv, 0xa3, val8);
4194 }
4195
4196 if (priv->rtl_chip == RTL8710B || priv->rtl_chip == RTL8192F)
4197 rtl8xxxu_write8(priv, REG_EARLY_MODE_CONTROL_8710B, 0);
4198 }
4199
4200 /*
4201 * Unit in 8 bytes.
4202 * Get Rx PHY status in order to report RSSI and others.
4203 */
4204 rtl8xxxu_write8(priv, REG_RX_DRVINFO_SZ, 4);
4205
4206 if (priv->rtl_chip == RTL8192E) {
4207 rtl8xxxu_write32(priv, REG_HIMR0, 0x00);
4208 rtl8xxxu_write32(priv, REG_HIMR1, 0x00);
4209 } else if (priv->rtl_chip == RTL8188F) {
4210 rtl8xxxu_write32(priv, REG_HISR0, 0xffffffff);
4211 rtl8xxxu_write32(priv, REG_HISR1, 0xffffffff);
4212 } else if (priv->rtl_chip == RTL8188E) {
4213 rtl8xxxu_write32(priv, REG_HISR0, 0xffffffff);
4214 val32 = IMR0_PSTIMEOUT | IMR0_TBDER | IMR0_CPWM | IMR0_CPWM2;
4215 rtl8xxxu_write32(priv, REG_HIMR0, val32);
4216 val32 = IMR1_TXERR | IMR1_RXERR | IMR1_TXFOVW | IMR1_RXFOVW;
4217 rtl8xxxu_write32(priv, REG_HIMR1, val32);
4218 val8 = rtl8xxxu_read8(priv, REG_USB_SPECIAL_OPTION);
4219 val8 |= USB_SPEC_INT_BULK_SELECT;
4220 rtl8xxxu_write8(priv, REG_USB_SPECIAL_OPTION, val8);
4221 } else if (priv->rtl_chip == RTL8710B) {
4222 rtl8xxxu_write32(priv, REG_HIMR0_8710B, 0);
4223 } else if (priv->rtl_chip != RTL8192F) {
4224 /*
4225 * Enable all interrupts - not obvious USB needs to do this
4226 */
4227 rtl8xxxu_write32(priv, REG_HISR, 0xffffffff);
4228 rtl8xxxu_write32(priv, REG_HIMR, 0xffffffff);
4229 }
4230
4231 /*
4232 * Configure initial WMAC settings
4233 */
4234 val32 = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_MCAST | RCR_ACCEPT_BCAST |
4235 RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL |
4236 RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC;
4237 rtl8xxxu_write32(priv, REG_RCR, val32);
4238 priv->regrcr = val32;
4239
4240 if (fops->init_reg_rxfltmap) {
4241 /* Accept all data frames */
4242 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff);
4243
4244 /*
4245 * Since ADF is removed from RCR, ps-poll will not be indicate to driver,
4246 * RxFilterMap should mask ps-poll to gurantee AP mode can rx ps-poll.
4247 */
4248 rtl8xxxu_write16(priv, REG_RXFLTMAP1, 0x400);
4249
4250 /* Accept all management frames */
4251 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff);
4252 } else {
4253 /*
4254 * Accept all multicast
4255 */
4256 rtl8xxxu_write32(priv, REG_MAR, 0xffffffff);
4257 rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff);
4258 }
4259
4260 /*
4261 * Init adaptive controls
4262 */
4263 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4264 val32 &= ~RESPONSE_RATE_BITMAP_ALL;
4265 val32 |= RESPONSE_RATE_RRSR_CCK_ONLY_1M;
4266 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4267
4268 /* CCK = 0x0a, OFDM = 0x10 */
4269 rtl8xxxu_set_spec_sifs(priv, 0x10, 0x10);
4270 rtl8xxxu_set_retry(priv, 0x30, 0x30);
4271 rtl8xxxu_set_spec_sifs(priv, 0x0a, 0x10);
4272
4273 /*
4274 * Init EDCA
4275 */
4276 rtl8xxxu_write16(priv, REG_MAC_SPEC_SIFS, 0x100a);
4277
4278 /* Set CCK SIFS */
4279 rtl8xxxu_write16(priv, REG_SIFS_CCK, 0x100a);
4280
4281 /* Set OFDM SIFS */
4282 rtl8xxxu_write16(priv, REG_SIFS_OFDM, 0x100a);
4283
4284 /* TXOP */
4285 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, 0x005ea42b);
4286 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, 0x0000a44f);
4287 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, 0x005ea324);
4288 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, 0x002fa226);
4289
4290 /* Set data auto rate fallback retry count */
4291 rtl8xxxu_write32(priv, REG_DARFRC, 0x00000000);
4292 rtl8xxxu_write32(priv, REG_DARFRC + 4, 0x10080404);
4293 rtl8xxxu_write32(priv, REG_RARFRC, 0x04030201);
4294 rtl8xxxu_write32(priv, REG_RARFRC + 4, 0x08070605);
4295
4296 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL);
4297 val8 |= FWHW_TXQ_CTRL_AMPDU_RETRY;
4298 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, val8);
4299
4300 /* Set ACK timeout */
4301 rtl8xxxu_write8(priv, REG_ACKTO, 0x40);
4302
4303 /*
4304 * Initialize beacon parameters
4305 */
4306 val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8);
4307 rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16);
4308 rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404);
4309 if (priv->rtl_chip != RTL8188F && priv->rtl_chip != RTL8710B &&
4310 priv->rtl_chip != RTL8192F)
4311 /* Firmware will control REG_DRVERLYINT when power saving is enable, */
4312 /* so don't set this register on STA mode. */
4313 rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME);
4314 rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME);
4315 rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F);
4316
4317 /*
4318 * Initialize burst parameters
4319 */
4320 if (priv->fops->init_burst)
4321 priv->fops->init_burst(priv);
4322
4323 if (fops->init_aggregation)
4324 fops->init_aggregation(priv);
4325
4326 if (fops->init_reg_pkt_life_time) {
4327 rtl8xxxu_write16(priv, REG_PKT_VO_VI_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */
4328 rtl8xxxu_write16(priv, REG_PKT_BE_BK_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */
4329 }
4330
4331 /*
4332 * Enable CCK and OFDM block
4333 */
4334 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4335 val32 |= (FPGA_RF_MODE_CCK | FPGA_RF_MODE_OFDM);
4336 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4337
4338 /*
4339 * Invalidate all CAM entries - bit 30 is undocumented
4340 */
4341 rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30));
4342
4343 /*
4344 * Start out with default power levels for channel 6, 20MHz
4345 */
4346 fops->set_tx_power(priv, 1, false);
4347
4348 /* Let the 8051 take control of antenna setting */
4349 if (priv->rtl_chip != RTL8192E && priv->rtl_chip != RTL8188F &&
4350 priv->rtl_chip != RTL8710B && priv->rtl_chip != RTL8192C) {
4351 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
4352 val8 |= LEDCFG2_DPDT_SELECT;
4353 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
4354 }
4355
4356 rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, 0xff);
4357
4358 /* Disable BAR - not sure if this has any effect on USB */
4359 rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff);
4360
4361 if (priv->rtl_chip != RTL8188F && priv->rtl_chip != RTL8188E &&
4362 priv->rtl_chip != RTL8710B && priv->rtl_chip != RTL8192F)
4363 rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0);
4364
4365 if (fops->init_statistics)
4366 fops->init_statistics(priv);
4367
4368 if (priv->rtl_chip == RTL8192E) {
4369 /*
4370 * 0x4c6[3] 1: RTS BW = Data BW
4371 * 0: RTS BW depends on CCA / secondary CCA result.
4372 */
4373 val8 = rtl8xxxu_read8(priv, REG_QUEUE_CTRL);
4374 val8 &= ~BIT(3);
4375 rtl8xxxu_write8(priv, REG_QUEUE_CTRL, val8);
4376 /*
4377 * Reset USB mode switch setting
4378 */
4379 rtl8xxxu_write8(priv, REG_ACLK_MON, 0x00);
4380 } else if (priv->rtl_chip == RTL8188F || priv->rtl_chip == RTL8188E ||
4381 priv->rtl_chip == RTL8192F) {
4382 /*
4383 * Init GPIO settings for 8188f, 8188e, 8192f
4384 */
4385 val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG);
4386 val8 &= ~GPIO_MUXCFG_IO_SEL_ENBT;
4387 rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8);
4388 }
4389
4390 if (priv->rtl_chip == RTL8188F)
4391 /* CCK PD */
4392 rtl8xxxu_write8(priv, REG_CCK_PD_THRESH, CCK_PD_TYPE1_LV1_TH);
4393
4394 fops->phy_lc_calibrate(priv);
4395
4396 fops->phy_iq_calibrate(priv);
4397
4398 /*
4399 * This should enable thermal meter
4400 */
4401 if (fops->gen2_thermal_meter) {
4402 if (priv->rtl_chip == RTL8188F || priv->rtl_chip == RTL8710B) {
4403 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_T_METER_8723B);
4404 val32 |= 0x30000;
4405 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER_8723B, val32);
4406 } else {
4407 rtl8xxxu_write_rfreg(priv,
4408 RF_A, RF6052_REG_T_METER_8723B, 0x37cf8);
4409 }
4410 } else {
4411 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60);
4412 }
4413
4414 /* Set NAV_UPPER to 30000us */
4415 val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT);
4416 rtl8xxxu_write8(priv, REG_NAV_UPPER, val8);
4417
4418 if (priv->rtl_chip == RTL8723A) {
4419 /*
4420 * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test,
4421 * but we need to find root cause.
4422 * This is 8723au only.
4423 */
4424 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4425 if ((val32 & 0xff000000) != 0x83000000) {
4426 val32 |= FPGA_RF_MODE_CCK;
4427 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4428 }
4429 } else if (priv->rtl_chip == RTL8192E || priv->rtl_chip == RTL8188E) {
4430 rtl8xxxu_write8(priv, REG_USB_HRPWM, 0x00);
4431 }
4432
4433 val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL);
4434 val32 |= FWHW_TXQ_CTRL_XMIT_MGMT_ACK;
4435 /* ack for xmit mgmt frames. */
4436 rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32);
4437
4438 if (priv->rtl_chip == RTL8192E) {
4439 /*
4440 * Fix LDPC rx hang issue.
4441 */
4442 val32 = rtl8xxxu_read32(priv, REG_AFE_MISC);
4443 rtl8xxxu_write8(priv, REG_8192E_LDOV12_CTRL, 0x75);
4444 val32 &= 0xfff00fff;
4445 val32 |= 0x0007e000;
4446 rtl8xxxu_write32(priv, REG_AFE_MISC, val32);
4447
4448 /*
4449 * 0x824[9] = 0x82C[9] = 0xA80[7] those registers setting
4450 * should be equal or CCK RSSI report may be incorrect
4451 */
4452 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
4453 priv->cck_agc_report_type =
4454 u32_get_bits(val32, FPGA0_HSSI_PARM2_CCK_HIGH_PWR);
4455
4456 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_HSSI_PARM2);
4457 if (priv->cck_agc_report_type !=
4458 u32_get_bits(val32, FPGA0_HSSI_PARM2_CCK_HIGH_PWR)) {
4459 if (priv->cck_agc_report_type)
4460 val32 |= FPGA0_HSSI_PARM2_CCK_HIGH_PWR;
4461 else
4462 val32 &= ~FPGA0_HSSI_PARM2_CCK_HIGH_PWR;
4463 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM2, val32);
4464 }
4465
4466 val32 = rtl8xxxu_read32(priv, REG_AGC_RPT);
4467 if (priv->cck_agc_report_type)
4468 val32 |= AGC_RPT_CCK;
4469 else
4470 val32 &= ~AGC_RPT_CCK;
4471 rtl8xxxu_write32(priv, REG_AGC_RPT, val32);
4472 }
4473
4474 if (priv->rtl_chip == RTL8710B) {
4475 /*
4476 * 0x76D[5:4] is Port0,Port1 Enable Bit.
4477 * This is only for 8710B, 2b'00 for MP and 2b'11 for Normal Driver
4478 */
4479 val8 = rtl8xxxu_read8(priv, REG_PORT_CONTROL_8710B);
4480 val8 |= BIT(5) | BIT(4);
4481 rtl8xxxu_write8(priv, REG_PORT_CONTROL_8710B, val8);
4482
4483 /* Set 0x5c[8] and [2:0] = 1, LDO mode */
4484 val32 = rtl8xxxu_read32(priv, REG_WL_RF_PSS_8710B);
4485 val32 |= 0x107;
4486 rtl8xxxu_write32(priv, REG_WL_RF_PSS_8710B, val32);
4487 }
4488
4489 val32 = rtl8xxxu_read32(priv, 0xa9c);
4490 priv->cck_new_agc = u32_get_bits(val32, BIT(17));
4491
4492 /* Initialise the center frequency offset tracking */
4493 if (priv->fops->set_crystal_cap) {
4494 val32 = rtl8xxxu_read32(priv, REG_OFDM1_CFO_TRACKING);
4495 priv->cfo_tracking.atc_status = val32 & CFO_TRACKING_ATC_STATUS;
4496 priv->cfo_tracking.adjust = true;
4497 priv->cfo_tracking.crystal_cap = priv->default_crystal_cap;
4498 }
4499
4500 if (priv->rtl_chip == RTL8188E)
4501 rtl8188e_ra_info_init_all(&priv->ra_info);
4502
4503 set_bit(RTL8XXXU_BC_MC_MACID, priv->mac_id_map);
4504 set_bit(RTL8XXXU_BC_MC_MACID1, priv->mac_id_map);
4505
4506 exit:
4507 return ret;
4508 }
4509
rtl8xxxu_cam_write(struct rtl8xxxu_priv * priv,struct ieee80211_key_conf * key,const u8 * mac)4510 static void rtl8xxxu_cam_write(struct rtl8xxxu_priv *priv,
4511 struct ieee80211_key_conf *key, const u8 *mac)
4512 {
4513 u32 cmd, val32, addr, ctrl;
4514 int j, i, tmp_debug;
4515
4516 tmp_debug = rtl8xxxu_debug;
4517 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_KEY)
4518 rtl8xxxu_debug |= RTL8XXXU_DEBUG_REG_WRITE;
4519
4520 /*
4521 * This is a bit of a hack - the lower bits of the cipher
4522 * suite selector happens to match the cipher index in the CAM
4523 */
4524 addr = key->hw_key_idx << CAM_CMD_KEY_SHIFT;
4525 ctrl = (key->cipher & 0x0f) << 2 | key->keyidx | CAM_WRITE_VALID;
4526 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
4527 ctrl |= BIT(6);
4528
4529 for (j = 5; j >= 0; j--) {
4530 switch (j) {
4531 case 0:
4532 val32 = ctrl | (mac[0] << 16) | (mac[1] << 24);
4533 break;
4534 case 1:
4535 val32 = mac[2] | (mac[3] << 8) |
4536 (mac[4] << 16) | (mac[5] << 24);
4537 break;
4538 default:
4539 i = (j - 2) << 2;
4540 val32 = key->key[i] | (key->key[i + 1] << 8) |
4541 key->key[i + 2] << 16 | key->key[i + 3] << 24;
4542 break;
4543 }
4544
4545 rtl8xxxu_write32(priv, REG_CAM_WRITE, val32);
4546 cmd = CAM_CMD_POLLING | CAM_CMD_WRITE | (addr + j);
4547 rtl8xxxu_write32(priv, REG_CAM_CMD, cmd);
4548 udelay(100);
4549 }
4550
4551 rtl8xxxu_debug = tmp_debug;
4552 }
4553
4554 static
rtl8xxxu_get_antenna(struct ieee80211_hw * hw,int radio_idx,u32 * tx_ant,u32 * rx_ant)4555 int rtl8xxxu_get_antenna(struct ieee80211_hw *hw, int radio_idx, u32 *tx_ant,
4556 u32 *rx_ant)
4557 {
4558 struct rtl8xxxu_priv *priv = hw->priv;
4559
4560 *tx_ant = BIT(priv->tx_paths) - 1;
4561 *rx_ant = BIT(priv->rx_paths) - 1;
4562
4563 return 0;
4564 }
4565
rtl8xxxu_set_tim(struct ieee80211_hw * hw,struct ieee80211_sta * sta,bool set)4566 static int rtl8xxxu_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta,
4567 bool set)
4568 {
4569 struct rtl8xxxu_priv *priv = hw->priv;
4570
4571 schedule_delayed_work(&priv->update_beacon_work, 0);
4572
4573 return 0;
4574 }
4575
rtl8xxxu_sw_scan_start(struct ieee80211_hw * hw,struct ieee80211_vif * vif,const u8 * mac)4576 static void rtl8xxxu_sw_scan_start(struct ieee80211_hw *hw,
4577 struct ieee80211_vif *vif, const u8 *mac)
4578 {
4579 struct rtl8xxxu_priv *priv = hw->priv;
4580 u8 val8;
4581
4582 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4583 val8 |= BEACON_DISABLE_TSF_UPDATE;
4584 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4585 }
4586
rtl8xxxu_sw_scan_complete(struct ieee80211_hw * hw,struct ieee80211_vif * vif)4587 static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw,
4588 struct ieee80211_vif *vif)
4589 {
4590 struct rtl8xxxu_priv *priv = hw->priv;
4591 u8 val8;
4592
4593 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4594 val8 &= ~BEACON_DISABLE_TSF_UPDATE;
4595 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4596 }
4597
rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv * priv,u32 ramask,u8 rateid,int sgi,int txbw_40mhz,u8 macid)4598 void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv,
4599 u32 ramask, u8 rateid, int sgi, int txbw_40mhz,
4600 u8 macid)
4601 {
4602 struct h2c_cmd h2c;
4603
4604 memset(&h2c, 0, sizeof(struct h2c_cmd));
4605
4606 h2c.ramask.cmd = H2C_SET_RATE_MASK;
4607 h2c.ramask.mask_lo = cpu_to_le16(ramask & 0xffff);
4608 h2c.ramask.mask_hi = cpu_to_le16(ramask >> 16);
4609
4610 h2c.ramask.arg = 0x80;
4611 if (sgi)
4612 h2c.ramask.arg |= 0x20;
4613
4614 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n",
4615 __func__, ramask, h2c.ramask.arg, sizeof(h2c.ramask));
4616 rtl8xxxu_gen1_h2c_cmd(priv, &h2c, sizeof(h2c.ramask));
4617 }
4618
rtl8xxxu_gen2_update_rate_mask(struct rtl8xxxu_priv * priv,u32 ramask,u8 rateid,int sgi,int txbw_40mhz,u8 macid)4619 void rtl8xxxu_gen2_update_rate_mask(struct rtl8xxxu_priv *priv,
4620 u32 ramask, u8 rateid, int sgi, int txbw_40mhz,
4621 u8 macid)
4622 {
4623 struct h2c_cmd h2c;
4624 u8 bw;
4625
4626 if (txbw_40mhz)
4627 bw = RTL8XXXU_CHANNEL_WIDTH_40;
4628 else
4629 bw = RTL8XXXU_CHANNEL_WIDTH_20;
4630
4631 memset(&h2c, 0, sizeof(struct h2c_cmd));
4632
4633 h2c.b_macid_cfg.cmd = H2C_8723B_MACID_CFG_RAID;
4634 h2c.b_macid_cfg.ramask0 = ramask & 0xff;
4635 h2c.b_macid_cfg.ramask1 = (ramask >> 8) & 0xff;
4636 h2c.b_macid_cfg.ramask2 = (ramask >> 16) & 0xff;
4637 h2c.b_macid_cfg.ramask3 = (ramask >> 24) & 0xff;
4638 h2c.b_macid_cfg.macid = macid;
4639
4640 h2c.b_macid_cfg.data1 = rateid;
4641 if (sgi)
4642 h2c.b_macid_cfg.data1 |= BIT(7);
4643
4644 h2c.b_macid_cfg.data2 = bw;
4645
4646 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, rateid %02x, sgi %d, size %zi\n",
4647 __func__, ramask, rateid, sgi, sizeof(h2c.b_macid_cfg));
4648 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.b_macid_cfg));
4649 }
4650
rtl8xxxu_gen1_report_connect(struct rtl8xxxu_priv * priv,u8 macid,u8 role,bool connect)4651 void rtl8xxxu_gen1_report_connect(struct rtl8xxxu_priv *priv,
4652 u8 macid, u8 role, bool connect)
4653 {
4654 struct h2c_cmd h2c;
4655
4656 memset(&h2c, 0, sizeof(struct h2c_cmd));
4657
4658 h2c.joinbss.cmd = H2C_JOIN_BSS_REPORT;
4659
4660 if (connect)
4661 h2c.joinbss.data = H2C_JOIN_BSS_CONNECT;
4662 else
4663 h2c.joinbss.data = H2C_JOIN_BSS_DISCONNECT;
4664
4665 rtl8xxxu_gen1_h2c_cmd(priv, &h2c, sizeof(h2c.joinbss));
4666 }
4667
rtl8xxxu_gen2_report_connect(struct rtl8xxxu_priv * priv,u8 macid,u8 role,bool connect)4668 void rtl8xxxu_gen2_report_connect(struct rtl8xxxu_priv *priv,
4669 u8 macid, u8 role, bool connect)
4670 {
4671 /*
4672 * The firmware turns on the rate control when it knows it's
4673 * connected to a network.
4674 */
4675 struct h2c_cmd h2c;
4676
4677 memset(&h2c, 0, sizeof(struct h2c_cmd));
4678
4679 h2c.media_status_rpt.cmd = H2C_8723B_MEDIA_STATUS_RPT;
4680 if (connect)
4681 h2c.media_status_rpt.parm |= BIT(0);
4682 else
4683 h2c.media_status_rpt.parm &= ~BIT(0);
4684
4685 h2c.media_status_rpt.parm |= ((role << 4) & 0xf0);
4686 h2c.media_status_rpt.macid = macid;
4687
4688 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.media_status_rpt));
4689 }
4690
rtl8xxxu_gen1_report_rssi(struct rtl8xxxu_priv * priv,u8 macid,u8 rssi)4691 void rtl8xxxu_gen1_report_rssi(struct rtl8xxxu_priv *priv, u8 macid, u8 rssi)
4692 {
4693 struct h2c_cmd h2c;
4694 const int h2c_size = 4;
4695
4696 memset(&h2c, 0, sizeof(struct h2c_cmd));
4697
4698 h2c.rssi_report.cmd = H2C_SET_RSSI;
4699 h2c.rssi_report.macid = macid;
4700 h2c.rssi_report.rssi = rssi;
4701
4702 rtl8xxxu_gen1_h2c_cmd(priv, &h2c, h2c_size);
4703 }
4704
rtl8xxxu_gen2_report_rssi(struct rtl8xxxu_priv * priv,u8 macid,u8 rssi)4705 void rtl8xxxu_gen2_report_rssi(struct rtl8xxxu_priv *priv, u8 macid, u8 rssi)
4706 {
4707 struct h2c_cmd h2c;
4708 int h2c_size = sizeof(h2c.rssi_report);
4709
4710 if (priv->rtl_chip == RTL8723B)
4711 h2c_size = 4;
4712
4713 memset(&h2c, 0, sizeof(struct h2c_cmd));
4714
4715 h2c.rssi_report.cmd = H2C_8723B_RSSI_SETTING;
4716 h2c.rssi_report.macid = macid;
4717 h2c.rssi_report.rssi = rssi;
4718
4719 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, h2c_size);
4720 }
4721
rtl8xxxu_gen1_init_aggregation(struct rtl8xxxu_priv * priv)4722 void rtl8xxxu_gen1_init_aggregation(struct rtl8xxxu_priv *priv)
4723 {
4724 u8 agg_ctrl, usb_spec, page_thresh, timeout;
4725
4726 usb_spec = rtl8xxxu_read8(priv, REG_USB_SPECIAL_OPTION);
4727 usb_spec &= ~USB_SPEC_USB_AGG_ENABLE;
4728 rtl8xxxu_write8(priv, REG_USB_SPECIAL_OPTION, usb_spec);
4729
4730 agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL);
4731 agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN;
4732
4733 if (!rtl8xxxu_dma_aggregation) {
4734 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl);
4735 return;
4736 }
4737
4738 agg_ctrl |= TRXDMA_CTRL_RXDMA_AGG_EN;
4739 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl);
4740
4741 /*
4742 * The number of packets we can take looks to be buffer size / 512
4743 * which matches the 512 byte rounding we have to do when de-muxing
4744 * the packets.
4745 *
4746 * Sample numbers from the vendor driver:
4747 * USB High-Speed mode values:
4748 * RxAggBlockCount = 8 : 512 byte unit
4749 * RxAggBlockTimeout = 6
4750 * RxAggPageCount = 48 : 128 byte unit
4751 * RxAggPageTimeout = 4 or 6 (absolute time 34ms/(2^6))
4752 */
4753
4754 page_thresh = (priv->fops->rx_agg_buf_size / 512);
4755 if (rtl8xxxu_dma_agg_pages >= 0) {
4756 if (rtl8xxxu_dma_agg_pages <= page_thresh)
4757 timeout = page_thresh;
4758 else if (rtl8xxxu_dma_agg_pages <= 6)
4759 dev_err(&priv->udev->dev,
4760 "%s: dma_agg_pages=%i too small, minimum is 6\n",
4761 __func__, rtl8xxxu_dma_agg_pages);
4762 else
4763 dev_err(&priv->udev->dev,
4764 "%s: dma_agg_pages=%i larger than limit %i\n",
4765 __func__, rtl8xxxu_dma_agg_pages, page_thresh);
4766 }
4767 rtl8xxxu_write8(priv, REG_RXDMA_AGG_PG_TH, page_thresh);
4768 /*
4769 * REG_RXDMA_AGG_PG_TH + 1 seems to be the timeout register on
4770 * gen2 chips and rtl8188eu. The rtl8723au seems unhappy if we
4771 * don't set it, so better set both.
4772 */
4773 timeout = 4;
4774
4775 if (rtl8xxxu_dma_agg_timeout >= 0) {
4776 if (rtl8xxxu_dma_agg_timeout <= 127)
4777 timeout = rtl8xxxu_dma_agg_timeout;
4778 else
4779 dev_err(&priv->udev->dev,
4780 "%s: Invalid dma_agg_timeout: %i\n",
4781 __func__, rtl8xxxu_dma_agg_timeout);
4782 }
4783
4784 rtl8xxxu_write8(priv, REG_RXDMA_AGG_PG_TH + 1, timeout);
4785 rtl8xxxu_write8(priv, REG_USB_DMA_AGG_TO, timeout);
4786 priv->rx_buf_aggregation = 1;
4787 }
4788
4789 static const struct ieee80211_rate rtl8xxxu_legacy_ratetable[] = {
4790 {.bitrate = 10, .hw_value = 0x00,},
4791 {.bitrate = 20, .hw_value = 0x01,},
4792 {.bitrate = 55, .hw_value = 0x02,},
4793 {.bitrate = 110, .hw_value = 0x03,},
4794 {.bitrate = 60, .hw_value = 0x04,},
4795 {.bitrate = 90, .hw_value = 0x05,},
4796 {.bitrate = 120, .hw_value = 0x06,},
4797 {.bitrate = 180, .hw_value = 0x07,},
4798 {.bitrate = 240, .hw_value = 0x08,},
4799 {.bitrate = 360, .hw_value = 0x09,},
4800 {.bitrate = 480, .hw_value = 0x0a,},
4801 {.bitrate = 540, .hw_value = 0x0b,},
4802 };
4803
rtl8xxxu_desc_to_mcsrate(u16 rate,u8 * mcs,u8 * nss)4804 static void rtl8xxxu_desc_to_mcsrate(u16 rate, u8 *mcs, u8 *nss)
4805 {
4806 if (rate <= DESC_RATE_54M)
4807 return;
4808
4809 if (rate >= DESC_RATE_MCS0 && rate <= DESC_RATE_MCS15) {
4810 if (rate < DESC_RATE_MCS8)
4811 *nss = 1;
4812 else
4813 *nss = 2;
4814 *mcs = rate - DESC_RATE_MCS0;
4815 }
4816 }
4817
rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv * priv,u32 rate_cfg)4818 static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg)
4819 {
4820 struct ieee80211_hw *hw = priv->hw;
4821 u32 val32;
4822 u8 rate_idx = 0;
4823
4824 rate_cfg &= RESPONSE_RATE_BITMAP_ALL;
4825
4826 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4827 if (hw->conf.chandef.chan->band == NL80211_BAND_5GHZ)
4828 val32 &= RESPONSE_RATE_RRSR_INIT_5G;
4829 else
4830 val32 &= RESPONSE_RATE_RRSR_INIT_2G;
4831 val32 |= rate_cfg;
4832 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4833
4834 dev_dbg(&priv->udev->dev, "%s: rates %08x\n", __func__, rate_cfg);
4835
4836 if (rate_cfg)
4837 rate_idx = __fls(rate_cfg);
4838
4839 rtl8xxxu_write8(priv, REG_INIRTS_RATE_SEL, rate_idx);
4840 }
4841
4842 static u16
rtl8xxxu_wireless_mode(struct ieee80211_hw * hw,struct ieee80211_sta * sta)4843 rtl8xxxu_wireless_mode(struct ieee80211_hw *hw, struct ieee80211_sta *sta)
4844 {
4845 u16 network_type = WIRELESS_MODE_UNKNOWN;
4846
4847 if (hw->conf.chandef.chan->band == NL80211_BAND_5GHZ) {
4848 if (sta->deflink.vht_cap.vht_supported)
4849 network_type = WIRELESS_MODE_AC;
4850 else if (sta->deflink.ht_cap.ht_supported)
4851 network_type = WIRELESS_MODE_N_5G;
4852
4853 network_type |= WIRELESS_MODE_A;
4854 } else {
4855 if (sta->deflink.vht_cap.vht_supported)
4856 network_type = WIRELESS_MODE_AC;
4857 else if (sta->deflink.ht_cap.ht_supported)
4858 network_type = WIRELESS_MODE_N_24G;
4859
4860 if (sta->deflink.supp_rates[0] <= 0xf)
4861 network_type |= WIRELESS_MODE_B;
4862 else if (sta->deflink.supp_rates[0] & 0xf)
4863 network_type |= (WIRELESS_MODE_B | WIRELESS_MODE_G);
4864 else
4865 network_type |= WIRELESS_MODE_G;
4866 }
4867
4868 return network_type;
4869 }
4870
rtl8xxxu_set_aifs(struct rtl8xxxu_priv * priv,u8 slot_time)4871 static void rtl8xxxu_set_aifs(struct rtl8xxxu_priv *priv, u8 slot_time)
4872 {
4873 u32 reg_edca_param[IEEE80211_NUM_ACS] = {
4874 [IEEE80211_AC_VO] = REG_EDCA_VO_PARAM,
4875 [IEEE80211_AC_VI] = REG_EDCA_VI_PARAM,
4876 [IEEE80211_AC_BE] = REG_EDCA_BE_PARAM,
4877 [IEEE80211_AC_BK] = REG_EDCA_BK_PARAM,
4878 };
4879 u32 val32;
4880 u16 wireless_mode = 0;
4881 u8 aifs, aifsn, sifs;
4882 int i;
4883
4884 for (i = 0; i < ARRAY_SIZE(priv->vifs); i++) {
4885 struct ieee80211_sta *sta;
4886
4887 if (!priv->vifs[i])
4888 continue;
4889
4890 rcu_read_lock();
4891 sta = ieee80211_find_sta(priv->vifs[i], priv->vifs[i]->bss_conf.bssid);
4892 if (sta)
4893 wireless_mode = rtl8xxxu_wireless_mode(priv->hw, sta);
4894 rcu_read_unlock();
4895
4896 if (wireless_mode)
4897 break;
4898 }
4899
4900 if (priv->hw->conf.chandef.chan->band == NL80211_BAND_5GHZ ||
4901 (wireless_mode & WIRELESS_MODE_N_24G))
4902 sifs = 16;
4903 else
4904 sifs = 10;
4905
4906 for (i = 0; i < IEEE80211_NUM_ACS; i++) {
4907 val32 = rtl8xxxu_read32(priv, reg_edca_param[i]);
4908
4909 /* It was set in conf_tx. */
4910 aifsn = val32 & 0xff;
4911
4912 /* aifsn not set yet or already fixed */
4913 if (aifsn < 2 || aifsn > 15)
4914 continue;
4915
4916 aifs = aifsn * slot_time + sifs;
4917
4918 val32 &= ~0xff;
4919 val32 |= aifs;
4920 rtl8xxxu_write32(priv, reg_edca_param[i], val32);
4921 }
4922 }
4923
rtl8xxxu_update_ra_report(struct rtl8xxxu_ra_report * rarpt,u8 rate,u8 sgi,u8 bw)4924 void rtl8xxxu_update_ra_report(struct rtl8xxxu_ra_report *rarpt,
4925 u8 rate, u8 sgi, u8 bw)
4926 {
4927 u8 mcs, nss;
4928
4929 rarpt->txrate.flags = 0;
4930
4931 if (rate <= DESC_RATE_54M) {
4932 rarpt->txrate.legacy = rtl8xxxu_legacy_ratetable[rate].bitrate;
4933 } else {
4934 rtl8xxxu_desc_to_mcsrate(rate, &mcs, &nss);
4935 rarpt->txrate.flags |= RATE_INFO_FLAGS_MCS;
4936
4937 rarpt->txrate.mcs = mcs;
4938 rarpt->txrate.nss = nss;
4939
4940 if (sgi)
4941 rarpt->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
4942
4943 rarpt->txrate.bw = bw;
4944 }
4945
4946 rarpt->bit_rate = cfg80211_calculate_bitrate(&rarpt->txrate);
4947 rarpt->desc_rate = rate;
4948 }
4949
4950 static void
rtl8xxxu_bss_info_changed(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_bss_conf * bss_conf,u64 changed)4951 rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4952 struct ieee80211_bss_conf *bss_conf, u64 changed)
4953 {
4954 struct rtl8xxxu_vif *rtlvif = (struct rtl8xxxu_vif *)vif->drv_priv;
4955 struct rtl8xxxu_priv *priv = hw->priv;
4956 struct device *dev = &priv->udev->dev;
4957 struct rtl8xxxu_sta_info *sta_info;
4958 struct ieee80211_sta *sta;
4959 struct rtl8xxxu_ra_report *rarpt;
4960 u8 val8, macid;
4961 u32 val32;
4962
4963 rarpt = &priv->ra_report;
4964
4965 if (changed & BSS_CHANGED_ASSOC) {
4966 dev_dbg(dev, "Changed ASSOC: %i!\n", vif->cfg.assoc);
4967
4968 rtl8xxxu_set_linktype(priv, vif->type, rtlvif->port_num);
4969
4970 if (vif->cfg.assoc) {
4971 u32 ramask;
4972 int sgi = 0;
4973 u8 highest_rate;
4974 u8 bw;
4975
4976 rcu_read_lock();
4977 sta = ieee80211_find_sta(vif, bss_conf->bssid);
4978 if (!sta) {
4979 dev_info(dev, "%s: ASSOC no sta found\n",
4980 __func__);
4981 rcu_read_unlock();
4982 goto error;
4983 }
4984 macid = rtl8xxxu_get_macid(priv, sta);
4985
4986 if (sta->deflink.ht_cap.ht_supported)
4987 dev_info(dev, "%s: HT supported\n", __func__);
4988 if (sta->deflink.vht_cap.vht_supported)
4989 dev_info(dev, "%s: VHT supported\n", __func__);
4990
4991 /* TODO: Set bits 28-31 for rate adaptive id */
4992 ramask = (sta->deflink.supp_rates[0] & 0xfff) |
4993 sta->deflink.ht_cap.mcs.rx_mask[0] << 12 |
4994 sta->deflink.ht_cap.mcs.rx_mask[1] << 20;
4995 if (sta->deflink.ht_cap.cap &
4996 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))
4997 sgi = 1;
4998
4999 highest_rate = fls(ramask) - 1;
5000 if (rtl8xxxu_ht40_2g &&
5001 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40))
5002 bw = RATE_INFO_BW_40;
5003 else
5004 bw = RATE_INFO_BW_20;
5005
5006 sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv;
5007 sta_info->rssi_level = RTL8XXXU_RATR_STA_INIT;
5008 rcu_read_unlock();
5009
5010 rtl8xxxu_update_ra_report(rarpt, highest_rate, sgi, bw);
5011
5012 priv->fops->update_rate_mask(priv, ramask, 0, sgi,
5013 bw == RATE_INFO_BW_40, macid);
5014
5015 rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff);
5016
5017 if (rtlvif->port_num == 0)
5018 rtl8xxxu_stop_tx_beacon(priv);
5019
5020 /* joinbss sequence */
5021 rtl8xxxu_write16(priv, REG_BCN_PSR_RPT,
5022 0xc000 | vif->cfg.aid);
5023
5024 priv->fops->report_connect(priv, 0, H2C_MACID_ROLE_AP, true);
5025 } else {
5026 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
5027 val8 |= BEACON_DISABLE_TSF_UPDATE;
5028 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
5029
5030 priv->fops->report_connect(priv, 0, H2C_MACID_ROLE_AP, false);
5031 }
5032 }
5033
5034 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
5035 dev_dbg(dev, "Changed ERP_PREAMBLE: Use short preamble %i\n",
5036 bss_conf->use_short_preamble);
5037 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
5038 if (bss_conf->use_short_preamble)
5039 val32 |= RSR_ACK_SHORT_PREAMBLE;
5040 else
5041 val32 &= ~RSR_ACK_SHORT_PREAMBLE;
5042 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
5043 }
5044
5045 if (changed & BSS_CHANGED_ERP_SLOT) {
5046 dev_dbg(dev, "Changed ERP_SLOT: short_slot_time %i\n",
5047 bss_conf->use_short_slot);
5048
5049 if (bss_conf->use_short_slot)
5050 val8 = 9;
5051 else
5052 val8 = 20;
5053 rtl8xxxu_write8(priv, REG_SLOT, val8);
5054
5055 rtl8xxxu_set_aifs(priv, val8);
5056 }
5057
5058 if (changed & BSS_CHANGED_BSSID) {
5059 dev_dbg(dev, "Changed BSSID!\n");
5060 rtl8xxxu_set_bssid(priv, bss_conf->bssid, rtlvif->port_num);
5061 }
5062
5063 if (changed & BSS_CHANGED_BASIC_RATES) {
5064 dev_dbg(dev, "Changed BASIC_RATES!\n");
5065 rtl8xxxu_set_basic_rates(priv, bss_conf->basic_rates);
5066 }
5067
5068 if (changed & BSS_CHANGED_BEACON_ENABLED) {
5069 if (bss_conf->enable_beacon) {
5070 rtl8xxxu_start_tx_beacon(priv);
5071 schedule_delayed_work(&priv->update_beacon_work, 0);
5072 } else {
5073 rtl8xxxu_stop_tx_beacon(priv);
5074 }
5075 }
5076
5077 if (changed & BSS_CHANGED_BEACON)
5078 schedule_delayed_work(&priv->update_beacon_work, 0);
5079
5080 error:
5081 return;
5082 }
5083
rtl8xxxu_start_ap(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_bss_conf * link_conf)5084 static int rtl8xxxu_start_ap(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5085 struct ieee80211_bss_conf *link_conf)
5086 {
5087 struct rtl8xxxu_vif *rtlvif = (struct rtl8xxxu_vif *)vif->drv_priv;
5088 struct rtl8xxxu_priv *priv = hw->priv;
5089 struct device *dev = &priv->udev->dev;
5090
5091 dev_dbg(dev, "Start AP mode\n");
5092 rtl8xxxu_set_bssid(priv, vif->bss_conf.bssid, rtlvif->port_num);
5093 rtl8xxxu_write16(priv, REG_BCN_INTERVAL, vif->bss_conf.beacon_int);
5094 priv->fops->report_connect(priv, RTL8XXXU_BC_MC_MACID, 0, true);
5095
5096 return 0;
5097 }
5098
rtl8xxxu_80211_to_rtl_queue(u32 queue)5099 static u32 rtl8xxxu_80211_to_rtl_queue(u32 queue)
5100 {
5101 u32 rtlqueue;
5102
5103 switch (queue) {
5104 case IEEE80211_AC_VO:
5105 rtlqueue = TXDESC_QUEUE_VO;
5106 break;
5107 case IEEE80211_AC_VI:
5108 rtlqueue = TXDESC_QUEUE_VI;
5109 break;
5110 case IEEE80211_AC_BE:
5111 rtlqueue = TXDESC_QUEUE_BE;
5112 break;
5113 case IEEE80211_AC_BK:
5114 rtlqueue = TXDESC_QUEUE_BK;
5115 break;
5116 default:
5117 rtlqueue = TXDESC_QUEUE_BE;
5118 }
5119
5120 return rtlqueue;
5121 }
5122
rtl8xxxu_queue_select(struct ieee80211_hdr * hdr,struct sk_buff * skb)5123 static u32 rtl8xxxu_queue_select(struct ieee80211_hdr *hdr, struct sk_buff *skb)
5124 {
5125 u32 queue;
5126
5127 if (unlikely(ieee80211_is_beacon(hdr->frame_control)))
5128 queue = TXDESC_QUEUE_BEACON;
5129 else if (ieee80211_is_mgmt(hdr->frame_control))
5130 queue = TXDESC_QUEUE_MGNT;
5131 else
5132 queue = rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb));
5133
5134 return queue;
5135 }
5136
5137 /*
5138 * Despite newer chips 8723b/8812/8821 having a larger TX descriptor
5139 * format. The descriptor checksum is still only calculated over the
5140 * initial 32 bytes of the descriptor!
5141 */
rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_txdesc32 * tx_desc)5142 static void rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_txdesc32 *tx_desc)
5143 {
5144 __le16 *ptr = (__le16 *)tx_desc;
5145 u16 csum = 0;
5146 int i;
5147
5148 /*
5149 * Clear csum field before calculation, as the csum field is
5150 * in the middle of the struct.
5151 */
5152 tx_desc->csum = cpu_to_le16(0);
5153
5154 for (i = 0; i < (sizeof(struct rtl8xxxu_txdesc32) / sizeof(u16)); i++)
5155 csum = csum ^ le16_to_cpu(ptr[i]);
5156
5157 tx_desc->csum |= cpu_to_le16(csum);
5158 }
5159
rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv * priv)5160 static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv *priv)
5161 {
5162 struct rtl8xxxu_tx_urb *tx_urb, *tmp;
5163 unsigned long flags;
5164
5165 spin_lock_irqsave(&priv->tx_urb_lock, flags);
5166 list_for_each_entry_safe(tx_urb, tmp, &priv->tx_urb_free_list, list) {
5167 list_del(&tx_urb->list);
5168 priv->tx_urb_free_count--;
5169 usb_free_urb(&tx_urb->urb);
5170 }
5171 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
5172 }
5173
5174 static struct rtl8xxxu_tx_urb *
rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv * priv)5175 rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv *priv)
5176 {
5177 struct rtl8xxxu_tx_urb *tx_urb;
5178 unsigned long flags;
5179
5180 spin_lock_irqsave(&priv->tx_urb_lock, flags);
5181 tx_urb = list_first_entry_or_null(&priv->tx_urb_free_list,
5182 struct rtl8xxxu_tx_urb, list);
5183 if (tx_urb) {
5184 list_del(&tx_urb->list);
5185 priv->tx_urb_free_count--;
5186 if (priv->tx_urb_free_count < RTL8XXXU_TX_URB_LOW_WATER &&
5187 !priv->tx_stopped) {
5188 priv->tx_stopped = true;
5189 ieee80211_stop_queues(priv->hw);
5190 }
5191 }
5192
5193 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
5194
5195 return tx_urb;
5196 }
5197
rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv * priv,struct rtl8xxxu_tx_urb * tx_urb)5198 static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv *priv,
5199 struct rtl8xxxu_tx_urb *tx_urb)
5200 {
5201 unsigned long flags;
5202
5203 INIT_LIST_HEAD(&tx_urb->list);
5204
5205 spin_lock_irqsave(&priv->tx_urb_lock, flags);
5206
5207 list_add(&tx_urb->list, &priv->tx_urb_free_list);
5208 priv->tx_urb_free_count++;
5209 if (priv->tx_urb_free_count > RTL8XXXU_TX_URB_HIGH_WATER &&
5210 priv->tx_stopped) {
5211 priv->tx_stopped = false;
5212 ieee80211_wake_queues(priv->hw);
5213 }
5214
5215 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
5216 }
5217
rtl8xxxu_tx_complete(struct urb * urb)5218 static void rtl8xxxu_tx_complete(struct urb *urb)
5219 {
5220 struct sk_buff *skb = (struct sk_buff *)urb->context;
5221 struct ieee80211_tx_info *tx_info;
5222 struct ieee80211_hw *hw;
5223 struct rtl8xxxu_priv *priv;
5224 struct rtl8xxxu_tx_urb *tx_urb =
5225 container_of(urb, struct rtl8xxxu_tx_urb, urb);
5226
5227 tx_info = IEEE80211_SKB_CB(skb);
5228 hw = tx_info->rate_driver_data[0];
5229 priv = hw->priv;
5230
5231 skb_pull(skb, priv->fops->tx_desc_size);
5232
5233 ieee80211_tx_info_clear_status(tx_info);
5234 tx_info->status.rates[0].idx = -1;
5235 tx_info->status.rates[0].count = 0;
5236
5237 if (!urb->status)
5238 tx_info->flags |= IEEE80211_TX_STAT_ACK;
5239
5240 ieee80211_tx_status_irqsafe(hw, skb);
5241
5242 rtl8xxxu_free_tx_urb(priv, tx_urb);
5243 }
5244
rtl8xxxu_dump_action(struct device * dev,struct ieee80211_hdr * hdr)5245 static void rtl8xxxu_dump_action(struct device *dev,
5246 struct ieee80211_hdr *hdr)
5247 {
5248 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr;
5249 u16 cap, timeout;
5250
5251 if (!(rtl8xxxu_debug & RTL8XXXU_DEBUG_ACTION))
5252 return;
5253
5254 switch (mgmt->u.action.u.addba_resp.action_code) {
5255 case WLAN_ACTION_ADDBA_RESP:
5256 cap = le16_to_cpu(mgmt->u.action.u.addba_resp.capab);
5257 timeout = le16_to_cpu(mgmt->u.action.u.addba_resp.timeout);
5258 dev_info(dev, "WLAN_ACTION_ADDBA_RESP: "
5259 "timeout %i, tid %02x, buf_size %02x, policy %02x, "
5260 "status %02x\n",
5261 timeout,
5262 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
5263 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
5264 (cap >> 1) & 0x1,
5265 le16_to_cpu(mgmt->u.action.u.addba_resp.status));
5266 break;
5267 case WLAN_ACTION_ADDBA_REQ:
5268 cap = le16_to_cpu(mgmt->u.action.u.addba_req.capab);
5269 timeout = le16_to_cpu(mgmt->u.action.u.addba_req.timeout);
5270 dev_info(dev, "WLAN_ACTION_ADDBA_REQ: "
5271 "timeout %i, tid %02x, buf_size %02x, policy %02x\n",
5272 timeout,
5273 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
5274 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
5275 (cap >> 1) & 0x1);
5276 break;
5277 default:
5278 dev_info(dev, "action frame %02x\n",
5279 mgmt->u.action.u.addba_resp.action_code);
5280 break;
5281 }
5282 }
5283
5284 /*
5285 * Fill in v1 (gen1) specific TX descriptor bits.
5286 * This format is used on 8188cu/8192cu/8723au
5287 */
5288 void
rtl8xxxu_fill_txdesc_v1(struct ieee80211_hw * hw,struct ieee80211_hdr * hdr,struct ieee80211_tx_info * tx_info,struct rtl8xxxu_txdesc32 * tx_desc,bool sgi,bool short_preamble,bool ampdu_enable,u32 rts_rate,u8 macid)5289 rtl8xxxu_fill_txdesc_v1(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr,
5290 struct ieee80211_tx_info *tx_info,
5291 struct rtl8xxxu_txdesc32 *tx_desc, bool sgi,
5292 bool short_preamble, bool ampdu_enable, u32 rts_rate,
5293 u8 macid)
5294 {
5295 struct rtl8xxxu_priv *priv = hw->priv;
5296 struct device *dev = &priv->udev->dev;
5297 u8 *qc = ieee80211_get_qos_ctl(hdr);
5298 u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
5299 u32 rate = 0;
5300 u16 seq_number;
5301
5302 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)
5303 dev_info(dev, "%s: TX rate: %d, pkt size %u\n",
5304 __func__, rate, le16_to_cpu(tx_desc->pkt_size));
5305
5306 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
5307
5308 tx_desc->txdw5 = cpu_to_le32(rate);
5309
5310 if (ieee80211_is_data(hdr->frame_control))
5311 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00);
5312
5313 tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC32_SEQ_SHIFT);
5314
5315 if (ampdu_enable && test_bit(tid, priv->tid_tx_operational))
5316 tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_ENABLE);
5317 else
5318 tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_BREAK);
5319
5320 if (ieee80211_is_mgmt(hdr->frame_control)) {
5321 tx_desc->txdw5 = cpu_to_le32(rate);
5322 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_USE_DRIVER_RATE);
5323 tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC32_RETRY_LIMIT_SHIFT);
5324 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_RETRY_LIMIT_ENABLE);
5325 }
5326
5327 if (ieee80211_is_data_qos(hdr->frame_control))
5328 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_QOS);
5329
5330 if (short_preamble)
5331 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_SHORT_PREAMBLE);
5332
5333 if (sgi)
5334 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_SHORT_GI);
5335
5336 /*
5337 * rts_rate is zero if RTS/CTS or CTS to SELF are not enabled
5338 */
5339 tx_desc->txdw4 |= cpu_to_le32(rts_rate << TXDESC32_RTS_RATE_SHIFT);
5340 if (ampdu_enable || tx_info->control.use_rts) {
5341 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_RTS_CTS_ENABLE);
5342 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE);
5343 } else if (tx_info->control.use_cts_prot) {
5344 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_CTS_SELF_ENABLE);
5345 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE);
5346 }
5347 }
5348
5349 /*
5350 * Fill in v2 (gen2) specific TX descriptor bits.
5351 * This format is used on 8192eu/8723bu
5352 */
5353 void
rtl8xxxu_fill_txdesc_v2(struct ieee80211_hw * hw,struct ieee80211_hdr * hdr,struct ieee80211_tx_info * tx_info,struct rtl8xxxu_txdesc32 * tx_desc32,bool sgi,bool short_preamble,bool ampdu_enable,u32 rts_rate,u8 macid)5354 rtl8xxxu_fill_txdesc_v2(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr,
5355 struct ieee80211_tx_info *tx_info,
5356 struct rtl8xxxu_txdesc32 *tx_desc32, bool sgi,
5357 bool short_preamble, bool ampdu_enable, u32 rts_rate,
5358 u8 macid)
5359 {
5360 struct rtl8xxxu_priv *priv = hw->priv;
5361 struct device *dev = &priv->udev->dev;
5362 struct rtl8xxxu_txdesc40 *tx_desc40;
5363 u8 *qc = ieee80211_get_qos_ctl(hdr);
5364 u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
5365 u32 rate = 0;
5366 u16 seq_number;
5367
5368 tx_desc40 = (struct rtl8xxxu_txdesc40 *)tx_desc32;
5369
5370 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)
5371 dev_info(dev, "%s: TX rate: %d, pkt size %u\n",
5372 __func__, rate, le16_to_cpu(tx_desc40->pkt_size));
5373
5374 tx_desc40->txdw1 |= cpu_to_le32(macid << TXDESC40_MACID_SHIFT);
5375
5376 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
5377
5378 tx_desc40->txdw4 = cpu_to_le32(rate);
5379 if (ieee80211_is_data(hdr->frame_control)) {
5380 tx_desc40->txdw4 |= cpu_to_le32(0x1f <<
5381 TXDESC40_DATA_RATE_FB_SHIFT);
5382 }
5383
5384 tx_desc40->txdw9 = cpu_to_le32((u32)seq_number << TXDESC40_SEQ_SHIFT);
5385
5386 if (ampdu_enable && test_bit(tid, priv->tid_tx_operational))
5387 tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_ENABLE);
5388 else
5389 tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_BREAK);
5390
5391 if (ieee80211_is_mgmt(hdr->frame_control)) {
5392 tx_desc40->txdw4 = cpu_to_le32(rate);
5393 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_USE_DRIVER_RATE);
5394 tx_desc40->txdw4 |=
5395 cpu_to_le32(6 << TXDESC40_RETRY_LIMIT_SHIFT);
5396 tx_desc40->txdw4 |= cpu_to_le32(TXDESC40_RETRY_LIMIT_ENABLE);
5397 }
5398
5399 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ)
5400 tx_desc40->txdw8 |= cpu_to_le32(TXDESC40_HW_SEQ_ENABLE);
5401
5402 if (short_preamble)
5403 tx_desc40->txdw5 |= cpu_to_le32(TXDESC40_SHORT_PREAMBLE);
5404
5405 tx_desc40->txdw4 |= cpu_to_le32(rts_rate << TXDESC40_RTS_RATE_SHIFT);
5406
5407 /*
5408 * rts_rate is zero if RTS/CTS or CTS to SELF are not enabled
5409 */
5410 if (ampdu_enable || tx_info->control.use_rts) {
5411 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_RTS_CTS_ENABLE);
5412 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_HW_RTS_ENABLE);
5413 } else if (tx_info->control.use_cts_prot) {
5414 /*
5415 * For some reason the vendor driver doesn't set
5416 * TXDESC40_HW_RTS_ENABLE for CTS to SELF
5417 */
5418 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_CTS_SELF_ENABLE);
5419 }
5420 }
5421
5422 /*
5423 * Fill in v3 (gen1) specific TX descriptor bits.
5424 * This format is a hybrid between the v1 and v2 formats, only seen
5425 * on 8188eu devices so far.
5426 */
5427 void
rtl8xxxu_fill_txdesc_v3(struct ieee80211_hw * hw,struct ieee80211_hdr * hdr,struct ieee80211_tx_info * tx_info,struct rtl8xxxu_txdesc32 * tx_desc,bool sgi,bool short_preamble,bool ampdu_enable,u32 rts_rate,u8 macid)5428 rtl8xxxu_fill_txdesc_v3(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr,
5429 struct ieee80211_tx_info *tx_info,
5430 struct rtl8xxxu_txdesc32 *tx_desc, bool sgi,
5431 bool short_preamble, bool ampdu_enable, u32 rts_rate,
5432 u8 macid)
5433 {
5434 struct rtl8xxxu_priv *priv = hw->priv;
5435 struct device *dev = &priv->udev->dev;
5436 struct rtl8xxxu_ra_info *ra = &priv->ra_info;
5437 u8 *qc = ieee80211_get_qos_ctl(hdr);
5438 u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
5439 u32 rate = 0;
5440 u16 seq_number;
5441
5442 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
5443
5444 if (ieee80211_is_data(hdr->frame_control)) {
5445 rate = ra->decision_rate;
5446 tx_desc->txdw5 = cpu_to_le32(rate);
5447 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_USE_DRIVER_RATE);
5448 tx_desc->txdw4 |= le32_encode_bits(ra->pt_stage, TXDESC32_PT_STAGE_MASK);
5449 /* Data/RTS rate FB limit */
5450 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00);
5451 }
5452
5453 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)
5454 dev_info(dev, "%s: TX rate: %d, pkt size %d\n",
5455 __func__, rate, le16_to_cpu(tx_desc->pkt_size));
5456
5457 tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC32_SEQ_SHIFT);
5458
5459 if (ampdu_enable && test_bit(tid, priv->tid_tx_operational))
5460 tx_desc->txdw2 |= cpu_to_le32(TXDESC40_AGG_ENABLE);
5461 else
5462 tx_desc->txdw2 |= cpu_to_le32(TXDESC40_AGG_BREAK);
5463
5464 if (ieee80211_is_mgmt(hdr->frame_control)) {
5465 tx_desc->txdw5 = cpu_to_le32(rate);
5466 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_USE_DRIVER_RATE);
5467 tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC32_RETRY_LIMIT_SHIFT);
5468 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_RETRY_LIMIT_ENABLE);
5469 }
5470
5471 if (ieee80211_is_data_qos(hdr->frame_control)) {
5472 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_QOS);
5473
5474 if (conf_is_ht40(&hw->conf)) {
5475 tx_desc->txdw4 |= cpu_to_le32(TXDESC_DATA_BW);
5476
5477 if (conf_is_ht40_minus(&hw->conf))
5478 tx_desc->txdw4 |= cpu_to_le32(TXDESC_PRIME_CH_OFF_UPPER);
5479 else
5480 tx_desc->txdw4 |= cpu_to_le32(TXDESC_PRIME_CH_OFF_LOWER);
5481 }
5482 }
5483
5484 if (short_preamble)
5485 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_SHORT_PREAMBLE);
5486
5487 if (sgi && ra->rate_sgi)
5488 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_SHORT_GI);
5489
5490 /*
5491 * rts_rate is zero if RTS/CTS or CTS to SELF are not enabled
5492 */
5493 tx_desc->txdw4 |= cpu_to_le32(rts_rate << TXDESC32_RTS_RATE_SHIFT);
5494 if (ampdu_enable || tx_info->control.use_rts) {
5495 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_RTS_CTS_ENABLE);
5496 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE);
5497 } else if (tx_info->control.use_cts_prot) {
5498 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_CTS_SELF_ENABLE);
5499 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE);
5500 }
5501
5502 tx_desc->txdw2 |= cpu_to_le32(TXDESC_ANTENNA_SELECT_A |
5503 TXDESC_ANTENNA_SELECT_B);
5504 tx_desc->txdw7 |= cpu_to_le16(TXDESC_ANTENNA_SELECT_C >> 16);
5505 }
5506
rtl8xxxu_tx(struct ieee80211_hw * hw,struct ieee80211_tx_control * control,struct sk_buff * skb)5507 static void rtl8xxxu_tx(struct ieee80211_hw *hw,
5508 struct ieee80211_tx_control *control,
5509 struct sk_buff *skb)
5510 {
5511 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
5512 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
5513 struct rtl8xxxu_priv *priv = hw->priv;
5514 struct rtl8xxxu_txdesc32 *tx_desc;
5515 struct rtl8xxxu_tx_urb *tx_urb;
5516 struct ieee80211_sta *sta = NULL;
5517 struct ieee80211_vif *vif = tx_info->control.vif;
5518 struct rtl8xxxu_vif *rtlvif = vif ? (struct rtl8xxxu_vif *)vif->drv_priv : NULL;
5519 struct device *dev = &priv->udev->dev;
5520 u32 queue, rts_rate;
5521 u16 pktlen = skb->len;
5522 int tx_desc_size = priv->fops->tx_desc_size;
5523 u8 macid;
5524 int ret;
5525 bool ampdu_enable, sgi = false, short_preamble = false, bmc = false;
5526
5527 if (skb_headroom(skb) < tx_desc_size) {
5528 dev_warn(dev,
5529 "%s: Not enough headroom (%i) for tx descriptor\n",
5530 __func__, skb_headroom(skb));
5531 goto error;
5532 }
5533
5534 if (unlikely(skb->len > (65535 - tx_desc_size))) {
5535 dev_warn(dev, "%s: Trying to send over-sized skb (%i)\n",
5536 __func__, skb->len);
5537 goto error;
5538 }
5539
5540 tx_urb = rtl8xxxu_alloc_tx_urb(priv);
5541 if (!tx_urb) {
5542 dev_warn(dev, "%s: Unable to allocate tx urb\n", __func__);
5543 goto error;
5544 }
5545
5546 if (ieee80211_is_action(hdr->frame_control))
5547 rtl8xxxu_dump_action(dev, hdr);
5548
5549 tx_info->rate_driver_data[0] = hw;
5550
5551 if (control && control->sta)
5552 sta = control->sta;
5553
5554 queue = rtl8xxxu_queue_select(hdr, skb);
5555
5556 tx_desc = skb_push(skb, tx_desc_size);
5557
5558 memset(tx_desc, 0, tx_desc_size);
5559 tx_desc->pkt_size = cpu_to_le16(pktlen);
5560 tx_desc->pkt_offset = tx_desc_size;
5561
5562 /* These bits mean different things to the RTL8192F. */
5563 if (priv->rtl_chip != RTL8192F)
5564 tx_desc->txdw0 =
5565 TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT;
5566 if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
5567 is_broadcast_ether_addr(ieee80211_get_DA(hdr))) {
5568 tx_desc->txdw0 |= TXDESC_BROADMULTICAST;
5569 bmc = true;
5570 }
5571
5572
5573 tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT);
5574 macid = rtl8xxxu_get_macid(priv, sta);
5575
5576 if (tx_info->control.hw_key) {
5577 switch (tx_info->control.hw_key->cipher) {
5578 case WLAN_CIPHER_SUITE_WEP40:
5579 case WLAN_CIPHER_SUITE_WEP104:
5580 case WLAN_CIPHER_SUITE_TKIP:
5581 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_RC4);
5582 break;
5583 case WLAN_CIPHER_SUITE_CCMP:
5584 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_AES);
5585 break;
5586 default:
5587 break;
5588 }
5589 if (bmc && rtlvif && rtlvif->hw_key_idx != 0xff) {
5590 tx_desc->txdw1 |= cpu_to_le32(TXDESC_EN_DESC_ID);
5591 macid = rtlvif->hw_key_idx;
5592 }
5593 }
5594
5595 /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */
5596 ampdu_enable = false;
5597 if (ieee80211_is_data_qos(hdr->frame_control) && sta) {
5598 if (sta->deflink.ht_cap.ht_supported) {
5599 u32 ampdu, val32;
5600 u8 *qc = ieee80211_get_qos_ctl(hdr);
5601 u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
5602
5603 ampdu = (u32)sta->deflink.ht_cap.ampdu_density;
5604 val32 = ampdu << TXDESC_AMPDU_DENSITY_SHIFT;
5605 tx_desc->txdw2 |= cpu_to_le32(val32);
5606
5607 ampdu_enable = true;
5608
5609 if (!test_bit(tid, priv->tx_aggr_started) &&
5610 !(skb->protocol == cpu_to_be16(ETH_P_PAE)))
5611 if (!ieee80211_start_tx_ba_session(sta, tid, 0))
5612 set_bit(tid, priv->tx_aggr_started);
5613 }
5614 }
5615
5616 if (ieee80211_is_data_qos(hdr->frame_control) &&
5617 sta && sta->deflink.ht_cap.cap &
5618 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))
5619 sgi = true;
5620
5621 if (sta && vif && vif->bss_conf.use_short_preamble)
5622 short_preamble = true;
5623
5624 if (skb->len > hw->wiphy->rts_threshold)
5625 tx_info->control.use_rts = true;
5626
5627 if (sta && vif && vif->bss_conf.use_cts_prot)
5628 tx_info->control.use_cts_prot = true;
5629
5630 if (ampdu_enable || tx_info->control.use_rts ||
5631 tx_info->control.use_cts_prot)
5632 rts_rate = DESC_RATE_24M;
5633 else
5634 rts_rate = 0;
5635
5636 priv->fops->fill_txdesc(hw, hdr, tx_info, tx_desc, sgi, short_preamble,
5637 ampdu_enable, rts_rate, macid);
5638
5639 rtl8xxxu_calc_tx_desc_csum(tx_desc);
5640
5641 /* avoid zero checksum make tx hang */
5642 if (priv->rtl_chip == RTL8710B || priv->rtl_chip == RTL8192F)
5643 tx_desc->csum = ~tx_desc->csum;
5644
5645 usb_fill_bulk_urb(&tx_urb->urb, priv->udev, priv->pipe_out[queue],
5646 skb->data, skb->len, rtl8xxxu_tx_complete, skb);
5647
5648 usb_anchor_urb(&tx_urb->urb, &priv->tx_anchor);
5649 ret = usb_submit_urb(&tx_urb->urb, GFP_ATOMIC);
5650 if (ret) {
5651 usb_unanchor_urb(&tx_urb->urb);
5652 rtl8xxxu_free_tx_urb(priv, tx_urb);
5653 goto error;
5654 }
5655 return;
5656 error:
5657 dev_kfree_skb(skb);
5658 }
5659
rtl8xxxu_send_beacon_frame(struct ieee80211_hw * hw,struct ieee80211_vif * vif)5660 static void rtl8xxxu_send_beacon_frame(struct ieee80211_hw *hw,
5661 struct ieee80211_vif *vif)
5662 {
5663 struct rtl8xxxu_priv *priv = hw->priv;
5664 struct sk_buff *skb = ieee80211_beacon_get(hw, vif, 0);
5665 struct device *dev = &priv->udev->dev;
5666 int retry;
5667 u8 val8;
5668
5669 /* BCN_VALID, write 1 to clear, cleared by SW */
5670 val8 = rtl8xxxu_read8(priv, REG_TDECTRL + 2);
5671 val8 |= BIT_BCN_VALID >> 16;
5672 rtl8xxxu_write8(priv, REG_TDECTRL + 2, val8);
5673
5674 /* SW_BCN_SEL - Port0 */
5675 val8 = rtl8xxxu_read8(priv, REG_DWBCN1_CTRL_8723B + 2);
5676 val8 &= ~(BIT_SW_BCN_SEL >> 16);
5677 rtl8xxxu_write8(priv, REG_DWBCN1_CTRL_8723B + 2, val8);
5678
5679 if (skb)
5680 rtl8xxxu_tx(hw, NULL, skb);
5681
5682 retry = 100;
5683 do {
5684 val8 = rtl8xxxu_read8(priv, REG_TDECTRL + 2);
5685 if (val8 & (BIT_BCN_VALID >> 16))
5686 break;
5687 usleep_range(10, 20);
5688 } while (--retry);
5689
5690 if (!retry)
5691 dev_err(dev, "%s: Failed to read beacon valid bit\n", __func__);
5692 }
5693
rtl8xxxu_update_beacon_work_callback(struct work_struct * work)5694 static void rtl8xxxu_update_beacon_work_callback(struct work_struct *work)
5695 {
5696 struct rtl8xxxu_priv *priv =
5697 container_of(work, struct rtl8xxxu_priv, update_beacon_work.work);
5698 struct ieee80211_hw *hw = priv->hw;
5699 struct ieee80211_vif *vif = priv->vifs[0];
5700
5701 if (!vif) {
5702 WARN_ONCE(true, "no vif to update beacon\n");
5703 return;
5704 }
5705
5706 if (vif->bss_conf.csa_active) {
5707 if (ieee80211_beacon_cntdwn_is_complete(vif, 0)) {
5708 ieee80211_csa_finish(vif, 0);
5709 return;
5710 }
5711 schedule_delayed_work(&priv->update_beacon_work,
5712 msecs_to_jiffies(vif->bss_conf.beacon_int));
5713 }
5714 rtl8xxxu_send_beacon_frame(hw, vif);
5715 }
5716
rtl8xxxu_is_packet_match_bssid(struct rtl8xxxu_priv * priv,struct ieee80211_hdr * hdr,int port_num)5717 static inline bool rtl8xxxu_is_packet_match_bssid(struct rtl8xxxu_priv *priv,
5718 struct ieee80211_hdr *hdr,
5719 int port_num)
5720 {
5721 return priv->vifs[port_num] &&
5722 priv->vifs[port_num]->type == NL80211_IFTYPE_STATION &&
5723 priv->vifs[port_num]->cfg.assoc &&
5724 ether_addr_equal(priv->vifs[port_num]->bss_conf.bssid, hdr->addr2);
5725 }
5726
rtl8xxxu_is_sta_sta(struct rtl8xxxu_priv * priv)5727 static inline bool rtl8xxxu_is_sta_sta(struct rtl8xxxu_priv *priv)
5728 {
5729 return (priv->vifs[0] && priv->vifs[0]->cfg.assoc &&
5730 priv->vifs[0]->type == NL80211_IFTYPE_STATION) &&
5731 (priv->vifs[1] && priv->vifs[1]->cfg.assoc &&
5732 priv->vifs[1]->type == NL80211_IFTYPE_STATION);
5733 }
5734
rtl8723au_rx_parse_phystats(struct rtl8xxxu_priv * priv,struct ieee80211_rx_status * rx_status,struct rtl8723au_phy_stats * phy_stats,u32 rxmcs,struct ieee80211_hdr * hdr,bool crc_icv_err)5735 void rtl8723au_rx_parse_phystats(struct rtl8xxxu_priv *priv,
5736 struct ieee80211_rx_status *rx_status,
5737 struct rtl8723au_phy_stats *phy_stats,
5738 u32 rxmcs, struct ieee80211_hdr *hdr,
5739 bool crc_icv_err)
5740 {
5741 if (phy_stats->sgi_en)
5742 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
5743
5744 if (rxmcs < DESC_RATE_6M) {
5745 /*
5746 * Handle PHY stats for CCK rates
5747 */
5748 rx_status->signal = priv->fops->cck_rssi(priv, phy_stats);
5749 } else {
5750 bool parse_cfo = priv->fops->set_crystal_cap &&
5751 !crc_icv_err &&
5752 !ieee80211_is_ctl(hdr->frame_control) &&
5753 !rtl8xxxu_is_sta_sta(priv) &&
5754 (rtl8xxxu_is_packet_match_bssid(priv, hdr, 0) ||
5755 rtl8xxxu_is_packet_match_bssid(priv, hdr, 1));
5756
5757 if (parse_cfo) {
5758 priv->cfo_tracking.cfo_tail[0] = phy_stats->path_cfotail[0];
5759 priv->cfo_tracking.cfo_tail[1] = phy_stats->path_cfotail[1];
5760
5761 priv->cfo_tracking.packet_count++;
5762 }
5763
5764 rx_status->signal =
5765 (phy_stats->cck_sig_qual_ofdm_pwdb_all >> 1) - 110;
5766 }
5767 }
5768
jaguar2_rx_parse_phystats_type0(struct rtl8xxxu_priv * priv,struct ieee80211_rx_status * rx_status,struct jaguar2_phy_stats_type0 * phy_stats0,u32 rxmcs,struct ieee80211_hdr * hdr,bool crc_icv_err)5769 static void jaguar2_rx_parse_phystats_type0(struct rtl8xxxu_priv *priv,
5770 struct ieee80211_rx_status *rx_status,
5771 struct jaguar2_phy_stats_type0 *phy_stats0,
5772 u32 rxmcs, struct ieee80211_hdr *hdr,
5773 bool crc_icv_err)
5774 {
5775 s8 rx_power = phy_stats0->pwdb - 110;
5776
5777 if (!priv->cck_new_agc)
5778 rx_power = priv->fops->cck_rssi(priv, (struct rtl8723au_phy_stats *)phy_stats0);
5779
5780 rx_status->signal = rx_power;
5781 }
5782
jaguar2_rx_parse_phystats_type1(struct rtl8xxxu_priv * priv,struct ieee80211_rx_status * rx_status,struct jaguar2_phy_stats_type1 * phy_stats1,u32 rxmcs,struct ieee80211_hdr * hdr,bool crc_icv_err)5783 static void jaguar2_rx_parse_phystats_type1(struct rtl8xxxu_priv *priv,
5784 struct ieee80211_rx_status *rx_status,
5785 struct jaguar2_phy_stats_type1 *phy_stats1,
5786 u32 rxmcs, struct ieee80211_hdr *hdr,
5787 bool crc_icv_err)
5788 {
5789 bool parse_cfo = priv->fops->set_crystal_cap &&
5790 !crc_icv_err &&
5791 !ieee80211_is_ctl(hdr->frame_control) &&
5792 !rtl8xxxu_is_sta_sta(priv) &&
5793 (rtl8xxxu_is_packet_match_bssid(priv, hdr, 0) ||
5794 rtl8xxxu_is_packet_match_bssid(priv, hdr, 1));
5795 u8 pwdb_max = 0;
5796 int rx_path;
5797
5798 if (parse_cfo) {
5799 /* Only path-A and path-B have CFO tail and short CFO */
5800 priv->cfo_tracking.cfo_tail[RF_A] = phy_stats1->cfo_tail[RF_A];
5801 priv->cfo_tracking.cfo_tail[RF_B] = phy_stats1->cfo_tail[RF_B];
5802
5803 priv->cfo_tracking.packet_count++;
5804 }
5805
5806 for (rx_path = 0; rx_path < priv->rx_paths; rx_path++)
5807 pwdb_max = max(pwdb_max, phy_stats1->pwdb[rx_path]);
5808
5809 rx_status->signal = pwdb_max - 110;
5810 }
5811
jaguar2_rx_parse_phystats_type2(struct rtl8xxxu_priv * priv,struct ieee80211_rx_status * rx_status,struct jaguar2_phy_stats_type2 * phy_stats2,u32 rxmcs,struct ieee80211_hdr * hdr,bool crc_icv_err)5812 static void jaguar2_rx_parse_phystats_type2(struct rtl8xxxu_priv *priv,
5813 struct ieee80211_rx_status *rx_status,
5814 struct jaguar2_phy_stats_type2 *phy_stats2,
5815 u32 rxmcs, struct ieee80211_hdr *hdr,
5816 bool crc_icv_err)
5817 {
5818 u8 pwdb_max = 0;
5819 int rx_path;
5820
5821 for (rx_path = 0; rx_path < priv->rx_paths; rx_path++)
5822 pwdb_max = max(pwdb_max, phy_stats2->pwdb[rx_path]);
5823
5824 rx_status->signal = pwdb_max - 110;
5825 }
5826
jaguar2_rx_parse_phystats(struct rtl8xxxu_priv * priv,struct ieee80211_rx_status * rx_status,struct rtl8723au_phy_stats * phy_stats,u32 rxmcs,struct ieee80211_hdr * hdr,bool crc_icv_err)5827 void jaguar2_rx_parse_phystats(struct rtl8xxxu_priv *priv,
5828 struct ieee80211_rx_status *rx_status,
5829 struct rtl8723au_phy_stats *phy_stats,
5830 u32 rxmcs, struct ieee80211_hdr *hdr,
5831 bool crc_icv_err)
5832 {
5833 struct jaguar2_phy_stats_type0 *phy_stats0 = (struct jaguar2_phy_stats_type0 *)phy_stats;
5834 struct jaguar2_phy_stats_type1 *phy_stats1 = (struct jaguar2_phy_stats_type1 *)phy_stats;
5835 struct jaguar2_phy_stats_type2 *phy_stats2 = (struct jaguar2_phy_stats_type2 *)phy_stats;
5836
5837 switch (phy_stats0->page_num) {
5838 case 0:
5839 /* CCK */
5840 jaguar2_rx_parse_phystats_type0(priv, rx_status, phy_stats0,
5841 rxmcs, hdr, crc_icv_err);
5842 break;
5843 case 1:
5844 /* OFDM */
5845 jaguar2_rx_parse_phystats_type1(priv, rx_status, phy_stats1,
5846 rxmcs, hdr, crc_icv_err);
5847 break;
5848 case 2:
5849 /* Also OFDM but different (how?) */
5850 jaguar2_rx_parse_phystats_type2(priv, rx_status, phy_stats2,
5851 rxmcs, hdr, crc_icv_err);
5852 break;
5853 default:
5854 return;
5855 }
5856 }
5857
rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv * priv)5858 static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv *priv)
5859 {
5860 struct rtl8xxxu_rx_urb *rx_urb, *tmp;
5861 unsigned long flags;
5862
5863 spin_lock_irqsave(&priv->rx_urb_lock, flags);
5864
5865 list_for_each_entry_safe(rx_urb, tmp,
5866 &priv->rx_urb_pending_list, list) {
5867 list_del(&rx_urb->list);
5868 priv->rx_urb_pending_count--;
5869 usb_free_urb(&rx_urb->urb);
5870 }
5871
5872 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5873 }
5874
rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv * priv,struct rtl8xxxu_rx_urb * rx_urb)5875 static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv,
5876 struct rtl8xxxu_rx_urb *rx_urb)
5877 {
5878 struct sk_buff *skb;
5879 unsigned long flags;
5880 int pending = 0;
5881
5882 spin_lock_irqsave(&priv->rx_urb_lock, flags);
5883
5884 if (!priv->shutdown) {
5885 list_add_tail(&rx_urb->list, &priv->rx_urb_pending_list);
5886 priv->rx_urb_pending_count++;
5887 pending = priv->rx_urb_pending_count;
5888 } else {
5889 skb = (struct sk_buff *)rx_urb->urb.context;
5890 dev_kfree_skb_irq(skb);
5891 usb_free_urb(&rx_urb->urb);
5892 }
5893
5894 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5895
5896 if (pending > RTL8XXXU_RX_URB_PENDING_WATER)
5897 schedule_work(&priv->rx_urb_wq);
5898 }
5899
rtl8xxxu_rx_urb_work(struct work_struct * work)5900 static void rtl8xxxu_rx_urb_work(struct work_struct *work)
5901 {
5902 struct rtl8xxxu_priv *priv;
5903 struct rtl8xxxu_rx_urb *rx_urb, *tmp;
5904 struct list_head local;
5905 struct sk_buff *skb;
5906 unsigned long flags;
5907 int ret;
5908
5909 priv = container_of(work, struct rtl8xxxu_priv, rx_urb_wq);
5910 INIT_LIST_HEAD(&local);
5911
5912 spin_lock_irqsave(&priv->rx_urb_lock, flags);
5913
5914 list_splice_init(&priv->rx_urb_pending_list, &local);
5915 priv->rx_urb_pending_count = 0;
5916
5917 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5918
5919 list_for_each_entry_safe(rx_urb, tmp, &local, list) {
5920 list_del_init(&rx_urb->list);
5921 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
5922 /*
5923 * If out of memory or temporary error, put it back on the
5924 * queue and try again. Otherwise the device is dead/gone
5925 * and we should drop it.
5926 */
5927 switch (ret) {
5928 case 0:
5929 break;
5930 case -ENOMEM:
5931 case -EAGAIN:
5932 rtl8xxxu_queue_rx_urb(priv, rx_urb);
5933 break;
5934 default:
5935 dev_warn(&priv->udev->dev,
5936 "failed to requeue urb with error %i\n", ret);
5937 skb = (struct sk_buff *)rx_urb->urb.context;
5938 dev_kfree_skb(skb);
5939 usb_free_urb(&rx_urb->urb);
5940 }
5941 }
5942 }
5943
5944 /*
5945 * The RTL8723BU/RTL8192EU vendor driver use coexistence table type
5946 * 0-7 to represent writing different combinations of register values
5947 * to REG_BT_COEX_TABLEs. It's for different kinds of coexistence use
5948 * cases which Realtek doesn't provide detail for these settings. Keep
5949 * this aligned with vendor driver for easier maintenance.
5950 */
5951 static
rtl8723bu_set_coex_with_type(struct rtl8xxxu_priv * priv,u8 type)5952 void rtl8723bu_set_coex_with_type(struct rtl8xxxu_priv *priv, u8 type)
5953 {
5954 switch (type) {
5955 case 0:
5956 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555);
5957 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x55555555);
5958 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);
5959 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);
5960 break;
5961 case 1:
5962 case 3:
5963 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555);
5964 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x5a5a5a5a);
5965 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);
5966 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);
5967 break;
5968 case 2:
5969 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x5a5a5a5a);
5970 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x5a5a5a5a);
5971 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);
5972 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);
5973 break;
5974 case 4:
5975 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x5a5a5a5a);
5976 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaaaa5a5a);
5977 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);
5978 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);
5979 break;
5980 case 5:
5981 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x5a5a5a5a);
5982 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaa5a5a5a);
5983 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);
5984 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);
5985 break;
5986 case 6:
5987 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555);
5988 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaaaaaaaa);
5989 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);
5990 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);
5991 break;
5992 case 7:
5993 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0xaaaaaaaa);
5994 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaaaaaaaa);
5995 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);
5996 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);
5997 break;
5998 default:
5999 break;
6000 }
6001 }
6002
6003 static
rtl8723bu_update_bt_link_info(struct rtl8xxxu_priv * priv,u8 bt_info)6004 void rtl8723bu_update_bt_link_info(struct rtl8xxxu_priv *priv, u8 bt_info)
6005 {
6006 struct rtl8xxxu_btcoex *btcoex = &priv->bt_coex;
6007
6008 if (bt_info & BT_INFO_8723B_1ANT_B_INQ_PAGE)
6009 btcoex->c2h_bt_inquiry = true;
6010 else
6011 btcoex->c2h_bt_inquiry = false;
6012
6013 if (!(bt_info & BT_INFO_8723B_1ANT_B_CONNECTION)) {
6014 btcoex->bt_status = BT_8723B_1ANT_STATUS_NON_CONNECTED_IDLE;
6015 btcoex->has_sco = false;
6016 btcoex->has_hid = false;
6017 btcoex->has_pan = false;
6018 btcoex->has_a2dp = false;
6019 } else {
6020 if ((bt_info & 0x1f) == BT_INFO_8723B_1ANT_B_CONNECTION)
6021 btcoex->bt_status = BT_8723B_1ANT_STATUS_CONNECTED_IDLE;
6022 else if ((bt_info & BT_INFO_8723B_1ANT_B_SCO_ESCO) ||
6023 (bt_info & BT_INFO_8723B_1ANT_B_SCO_BUSY))
6024 btcoex->bt_status = BT_8723B_1ANT_STATUS_SCO_BUSY;
6025 else if (bt_info & BT_INFO_8723B_1ANT_B_ACL_BUSY)
6026 btcoex->bt_status = BT_8723B_1ANT_STATUS_ACL_BUSY;
6027 else
6028 btcoex->bt_status = BT_8723B_1ANT_STATUS_MAX;
6029
6030 if (bt_info & BT_INFO_8723B_1ANT_B_FTP)
6031 btcoex->has_pan = true;
6032 else
6033 btcoex->has_pan = false;
6034
6035 if (bt_info & BT_INFO_8723B_1ANT_B_A2DP)
6036 btcoex->has_a2dp = true;
6037 else
6038 btcoex->has_a2dp = false;
6039
6040 if (bt_info & BT_INFO_8723B_1ANT_B_HID)
6041 btcoex->has_hid = true;
6042 else
6043 btcoex->has_hid = false;
6044
6045 if (bt_info & BT_INFO_8723B_1ANT_B_SCO_ESCO)
6046 btcoex->has_sco = true;
6047 else
6048 btcoex->has_sco = false;
6049 }
6050
6051 if (!btcoex->has_a2dp && !btcoex->has_sco &&
6052 !btcoex->has_pan && btcoex->has_hid)
6053 btcoex->hid_only = true;
6054 else
6055 btcoex->hid_only = false;
6056
6057 if (!btcoex->has_sco && !btcoex->has_pan &&
6058 !btcoex->has_hid && btcoex->has_a2dp)
6059 btcoex->has_a2dp = true;
6060 else
6061 btcoex->has_a2dp = false;
6062
6063 if (btcoex->bt_status == BT_8723B_1ANT_STATUS_SCO_BUSY ||
6064 btcoex->bt_status == BT_8723B_1ANT_STATUS_ACL_BUSY)
6065 btcoex->bt_busy = true;
6066 else
6067 btcoex->bt_busy = false;
6068 }
6069
rtl8xxxu_is_assoc(struct rtl8xxxu_priv * priv)6070 static inline bool rtl8xxxu_is_assoc(struct rtl8xxxu_priv *priv)
6071 {
6072 return (priv->vifs[0] && priv->vifs[0]->cfg.assoc) ||
6073 (priv->vifs[1] && priv->vifs[1]->cfg.assoc);
6074 }
6075
6076 static
rtl8723bu_handle_bt_inquiry(struct rtl8xxxu_priv * priv)6077 void rtl8723bu_handle_bt_inquiry(struct rtl8xxxu_priv *priv)
6078 {
6079 struct rtl8xxxu_btcoex *btcoex;
6080
6081 btcoex = &priv->bt_coex;
6082
6083 if (!rtl8xxxu_is_assoc(priv)) {
6084 rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0);
6085 rtl8723bu_set_coex_with_type(priv, 0);
6086 } else if (btcoex->has_sco || btcoex->has_hid || btcoex->has_a2dp) {
6087 rtl8723bu_set_ps_tdma(priv, 0x61, 0x35, 0x3, 0x11, 0x11);
6088 rtl8723bu_set_coex_with_type(priv, 4);
6089 } else if (btcoex->has_pan) {
6090 rtl8723bu_set_ps_tdma(priv, 0x61, 0x3f, 0x3, 0x11, 0x11);
6091 rtl8723bu_set_coex_with_type(priv, 4);
6092 } else {
6093 rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0);
6094 rtl8723bu_set_coex_with_type(priv, 7);
6095 }
6096 }
6097
6098 static
rtl8723bu_handle_bt_info(struct rtl8xxxu_priv * priv)6099 void rtl8723bu_handle_bt_info(struct rtl8xxxu_priv *priv)
6100 {
6101 struct rtl8xxxu_btcoex *btcoex;
6102
6103 btcoex = &priv->bt_coex;
6104
6105 if (rtl8xxxu_is_assoc(priv)) {
6106 u32 val32 = 0;
6107 u32 high_prio_tx = 0, high_prio_rx = 0;
6108
6109 val32 = rtl8xxxu_read32(priv, 0x770);
6110 high_prio_tx = val32 & 0x0000ffff;
6111 high_prio_rx = (val32 & 0xffff0000) >> 16;
6112
6113 if (btcoex->bt_busy) {
6114 if (btcoex->hid_only) {
6115 rtl8723bu_set_ps_tdma(priv, 0x61, 0x20,
6116 0x3, 0x11, 0x11);
6117 rtl8723bu_set_coex_with_type(priv, 5);
6118 } else if (btcoex->a2dp_only) {
6119 rtl8723bu_set_ps_tdma(priv, 0x61, 0x35,
6120 0x3, 0x11, 0x11);
6121 rtl8723bu_set_coex_with_type(priv, 4);
6122 } else if ((btcoex->has_a2dp && btcoex->has_pan) ||
6123 (btcoex->has_hid && btcoex->has_a2dp &&
6124 btcoex->has_pan)) {
6125 rtl8723bu_set_ps_tdma(priv, 0x51, 0x21,
6126 0x3, 0x10, 0x10);
6127 rtl8723bu_set_coex_with_type(priv, 4);
6128 } else if (btcoex->has_hid && btcoex->has_a2dp) {
6129 rtl8723bu_set_ps_tdma(priv, 0x51, 0x21,
6130 0x3, 0x10, 0x10);
6131 rtl8723bu_set_coex_with_type(priv, 3);
6132 } else {
6133 rtl8723bu_set_ps_tdma(priv, 0x61, 0x35,
6134 0x3, 0x11, 0x11);
6135 rtl8723bu_set_coex_with_type(priv, 4);
6136 }
6137 } else {
6138 rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0);
6139 if (high_prio_tx + high_prio_rx <= 60)
6140 rtl8723bu_set_coex_with_type(priv, 2);
6141 else
6142 rtl8723bu_set_coex_with_type(priv, 7);
6143 }
6144 } else {
6145 rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0);
6146 rtl8723bu_set_coex_with_type(priv, 0);
6147 }
6148 }
6149
rtl8xxxu_c2hcmd_callback(struct work_struct * work)6150 static void rtl8xxxu_c2hcmd_callback(struct work_struct *work)
6151 {
6152 struct rtl8xxxu_priv *priv;
6153 struct rtl8723bu_c2h *c2h;
6154 struct sk_buff *skb = NULL;
6155 u8 bt_info = 0;
6156 struct rtl8xxxu_btcoex *btcoex;
6157 struct rtl8xxxu_ra_report *rarpt;
6158 u8 bw;
6159
6160 priv = container_of(work, struct rtl8xxxu_priv, c2hcmd_work);
6161 btcoex = &priv->bt_coex;
6162 rarpt = &priv->ra_report;
6163
6164 while (!skb_queue_empty(&priv->c2hcmd_queue)) {
6165 skb = skb_dequeue(&priv->c2hcmd_queue);
6166
6167 c2h = (struct rtl8723bu_c2h *)skb->data;
6168
6169 switch (c2h->id) {
6170 case C2H_8723B_BT_INFO:
6171 bt_info = c2h->bt_info.bt_info;
6172
6173 rtl8723bu_update_bt_link_info(priv, bt_info);
6174 if (btcoex->c2h_bt_inquiry) {
6175 rtl8723bu_handle_bt_inquiry(priv);
6176 break;
6177 }
6178 rtl8723bu_handle_bt_info(priv);
6179 break;
6180 case C2H_8723B_RA_REPORT:
6181 bw = rarpt->txrate.bw;
6182
6183 if (skb->len >= offsetofend(typeof(*c2h), ra_report.bw)) {
6184 if (c2h->ra_report.bw == RTL8XXXU_CHANNEL_WIDTH_40)
6185 bw = RATE_INFO_BW_40;
6186 else
6187 bw = RATE_INFO_BW_20;
6188 }
6189
6190 rtl8xxxu_update_ra_report(rarpt, c2h->ra_report.rate,
6191 c2h->ra_report.sgi, bw);
6192 break;
6193 default:
6194 break;
6195 }
6196
6197 dev_kfree_skb(skb);
6198 }
6199 }
6200
rtl8723bu_handle_c2h(struct rtl8xxxu_priv * priv,struct sk_buff * skb)6201 static void rtl8723bu_handle_c2h(struct rtl8xxxu_priv *priv,
6202 struct sk_buff *skb)
6203 {
6204 struct rtl8723bu_c2h *c2h = (struct rtl8723bu_c2h *)skb->data;
6205 struct device *dev = &priv->udev->dev;
6206 int len;
6207
6208 len = skb->len - 2;
6209
6210 dev_dbg(dev, "C2H ID %02x seq %02x, len %02x source %02x\n",
6211 c2h->id, c2h->seq, len, c2h->bt_info.response_source);
6212
6213 switch(c2h->id) {
6214 case C2H_8723B_BT_INFO:
6215 if (c2h->bt_info.response_source >
6216 BT_INFO_SRC_8723B_BT_ACTIVE_SEND)
6217 dev_dbg(dev, "C2H_BT_INFO WiFi only firmware\n");
6218 else
6219 dev_dbg(dev, "C2H_BT_INFO BT/WiFi coexist firmware\n");
6220
6221 if (c2h->bt_info.bt_has_reset)
6222 dev_dbg(dev, "BT has been reset\n");
6223 if (c2h->bt_info.tx_rx_mask)
6224 dev_dbg(dev, "BT TRx mask\n");
6225
6226 break;
6227 case C2H_8723B_BT_MP_INFO:
6228 dev_dbg(dev, "C2H_MP_INFO ext ID %02x, status %02x\n",
6229 c2h->bt_mp_info.ext_id, c2h->bt_mp_info.status);
6230 break;
6231 case C2H_8723B_RA_REPORT:
6232 dev_dbg(dev,
6233 "C2H RA RPT: rate %02x, unk %i, macid %02x, noise %i\n",
6234 c2h->ra_report.rate, c2h->ra_report.sgi,
6235 c2h->ra_report.macid, c2h->ra_report.noisy_state);
6236 break;
6237 default:
6238 dev_info(dev, "Unhandled C2H event %02x seq %02x\n",
6239 c2h->id, c2h->seq);
6240 print_hex_dump(KERN_INFO, "C2H content: ", DUMP_PREFIX_NONE,
6241 16, 1, c2h->raw.payload, len, false);
6242 break;
6243 }
6244
6245 skb_queue_tail(&priv->c2hcmd_queue, skb);
6246
6247 schedule_work(&priv->c2hcmd_work);
6248 }
6249
rtl8188e_c2hcmd_callback(struct work_struct * work)6250 static void rtl8188e_c2hcmd_callback(struct work_struct *work)
6251 {
6252 struct rtl8xxxu_priv *priv = container_of(work, struct rtl8xxxu_priv, c2hcmd_work);
6253 struct device *dev = &priv->udev->dev;
6254 struct sk_buff *skb = NULL;
6255 struct rtl8xxxu_rxdesc16 *rx_desc;
6256
6257 while (!skb_queue_empty(&priv->c2hcmd_queue)) {
6258 skb = skb_dequeue(&priv->c2hcmd_queue);
6259
6260 rx_desc = (struct rtl8xxxu_rxdesc16 *)(skb->data - sizeof(struct rtl8xxxu_rxdesc16));
6261
6262 switch (rx_desc->rpt_sel) {
6263 case 1:
6264 dev_dbg(dev, "C2H TX report type 1\n");
6265
6266 break;
6267 case 2:
6268 dev_dbg(dev, "C2H TX report type 2\n");
6269
6270 rtl8188e_handle_ra_tx_report2(priv, skb);
6271
6272 break;
6273 case 3:
6274 dev_dbg(dev, "C2H USB interrupt report\n");
6275
6276 break;
6277 default:
6278 dev_warn(dev, "%s: rpt_sel should not be %d\n",
6279 __func__, rx_desc->rpt_sel);
6280
6281 break;
6282 }
6283
6284 dev_kfree_skb(skb);
6285 }
6286 }
6287
6288 #define rtl8xxxu_iterate_vifs_atomic(priv, iterator, data) \
6289 ieee80211_iterate_active_interfaces_atomic((priv)->hw, \
6290 IEEE80211_IFACE_ITER_NORMAL, iterator, data)
6291
6292 struct rtl8xxxu_rx_update_rssi_data {
6293 struct rtl8xxxu_priv *priv;
6294 struct ieee80211_hdr *hdr;
6295 struct ieee80211_rx_status *rx_status;
6296 u8 *bssid;
6297 };
6298
rtl8xxxu_rx_update_rssi_iter(void * data,u8 * mac,struct ieee80211_vif * vif)6299 static void rtl8xxxu_rx_update_rssi_iter(void *data, u8 *mac,
6300 struct ieee80211_vif *vif)
6301 {
6302 struct rtl8xxxu_rx_update_rssi_data *iter_data = data;
6303 struct ieee80211_sta *sta;
6304 struct ieee80211_hdr *hdr = iter_data->hdr;
6305 struct rtl8xxxu_priv *priv = iter_data->priv;
6306 struct rtl8xxxu_sta_info *sta_info;
6307 struct ieee80211_rx_status *rx_status = iter_data->rx_status;
6308 u8 *bssid = iter_data->bssid;
6309
6310 if (!ether_addr_equal(vif->bss_conf.bssid, bssid))
6311 return;
6312
6313 if (!(ether_addr_equal(vif->addr, hdr->addr1) ||
6314 ieee80211_is_beacon(hdr->frame_control)))
6315 return;
6316
6317 sta = ieee80211_find_sta_by_ifaddr(priv->hw, hdr->addr2,
6318 vif->addr);
6319 if (!sta)
6320 return;
6321
6322 sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv;
6323 ewma_rssi_add(&sta_info->avg_rssi, -rx_status->signal);
6324 }
6325
get_hdr_bssid(struct ieee80211_hdr * hdr)6326 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr)
6327 {
6328 __le16 fc = hdr->frame_control;
6329 u8 *bssid;
6330
6331 if (ieee80211_has_tods(fc))
6332 bssid = hdr->addr1;
6333 else if (ieee80211_has_fromds(fc))
6334 bssid = hdr->addr2;
6335 else
6336 bssid = hdr->addr3;
6337
6338 return bssid;
6339 }
6340
rtl8xxxu_rx_update_rssi(struct rtl8xxxu_priv * priv,struct ieee80211_rx_status * rx_status,struct ieee80211_hdr * hdr)6341 static void rtl8xxxu_rx_update_rssi(struct rtl8xxxu_priv *priv,
6342 struct ieee80211_rx_status *rx_status,
6343 struct ieee80211_hdr *hdr)
6344 {
6345 struct rtl8xxxu_rx_update_rssi_data data = {};
6346
6347 if (ieee80211_is_ctl(hdr->frame_control))
6348 return;
6349
6350 data.priv = priv;
6351 data.hdr = hdr;
6352 data.rx_status = rx_status;
6353 data.bssid = get_hdr_bssid(hdr);
6354
6355 rtl8xxxu_iterate_vifs_atomic(priv, rtl8xxxu_rx_update_rssi_iter, &data);
6356 }
6357
rtl8xxxu_parse_rxdesc16(struct rtl8xxxu_priv * priv,struct sk_buff * skb)6358 int rtl8xxxu_parse_rxdesc16(struct rtl8xxxu_priv *priv, struct sk_buff *skb)
6359 {
6360 struct ieee80211_hw *hw = priv->hw;
6361 struct ieee80211_rx_status *rx_status;
6362 struct rtl8xxxu_rxdesc16 *rx_desc;
6363 struct rtl8723au_phy_stats *phy_stats;
6364 struct sk_buff *next_skb = NULL;
6365 __le32 *_rx_desc_le;
6366 u32 *_rx_desc;
6367 int drvinfo_sz, desc_shift;
6368 int i, pkt_cnt, pkt_len, urb_len, pkt_offset;
6369
6370 urb_len = skb->len;
6371 pkt_cnt = 0;
6372
6373 if (urb_len < sizeof(struct rtl8xxxu_rxdesc16)) {
6374 kfree_skb(skb);
6375 return RX_TYPE_ERROR;
6376 }
6377
6378 do {
6379 rx_desc = (struct rtl8xxxu_rxdesc16 *)skb->data;
6380 _rx_desc_le = (__le32 *)skb->data;
6381 _rx_desc = (u32 *)skb->data;
6382
6383 for (i = 0;
6384 i < (sizeof(struct rtl8xxxu_rxdesc16) / sizeof(u32)); i++)
6385 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);
6386
6387 /*
6388 * Only read pkt_cnt from the header if we're parsing the
6389 * first packet
6390 */
6391 if (!pkt_cnt)
6392 pkt_cnt = rx_desc->pkt_cnt;
6393 pkt_len = rx_desc->pktlen;
6394
6395 drvinfo_sz = rx_desc->drvinfo_sz * 8;
6396 desc_shift = rx_desc->shift;
6397 pkt_offset = roundup(pkt_len + drvinfo_sz + desc_shift +
6398 sizeof(struct rtl8xxxu_rxdesc16), 128);
6399
6400 /*
6401 * Only clone the skb if there's enough data at the end to
6402 * at least cover the rx descriptor
6403 */
6404 if (pkt_cnt > 1 &&
6405 urb_len >= (pkt_offset + sizeof(struct rtl8xxxu_rxdesc16)))
6406 next_skb = skb_clone(skb, GFP_ATOMIC);
6407
6408 rx_status = IEEE80211_SKB_RXCB(skb);
6409 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
6410
6411 skb_pull(skb, sizeof(struct rtl8xxxu_rxdesc16));
6412
6413 if (rx_desc->rpt_sel) {
6414 skb_queue_tail(&priv->c2hcmd_queue, skb);
6415 schedule_work(&priv->c2hcmd_work);
6416 } else {
6417 struct ieee80211_hdr *hdr;
6418
6419 phy_stats = (struct rtl8723au_phy_stats *)skb->data;
6420
6421 skb_pull(skb, drvinfo_sz + desc_shift);
6422
6423 skb_trim(skb, pkt_len);
6424
6425 hdr = (struct ieee80211_hdr *)skb->data;
6426 if (rx_desc->phy_stats) {
6427 priv->fops->parse_phystats(
6428 priv, rx_status, phy_stats,
6429 rx_desc->rxmcs,
6430 hdr,
6431 rx_desc->crc32 || rx_desc->icverr);
6432 if (!rx_desc->crc32 && !rx_desc->icverr)
6433 rtl8xxxu_rx_update_rssi(priv,
6434 rx_status,
6435 hdr);
6436 }
6437
6438 rx_status->mactime = rx_desc->tsfl;
6439 rx_status->flag |= RX_FLAG_MACTIME_START;
6440
6441 if (!rx_desc->swdec &&
6442 rx_desc->security != RX_DESC_ENC_NONE)
6443 rx_status->flag |= RX_FLAG_DECRYPTED;
6444 if (rx_desc->crc32)
6445 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
6446 if (rx_desc->bw)
6447 rx_status->bw = RATE_INFO_BW_40;
6448
6449 if (rx_desc->rxht) {
6450 rx_status->encoding = RX_ENC_HT;
6451 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
6452 } else {
6453 rx_status->rate_idx = rx_desc->rxmcs;
6454 }
6455
6456 rx_status->freq = hw->conf.chandef.chan->center_freq;
6457 rx_status->band = hw->conf.chandef.chan->band;
6458
6459 ieee80211_rx_irqsafe(hw, skb);
6460 }
6461
6462 skb = next_skb;
6463 if (skb)
6464 skb_pull(next_skb, pkt_offset);
6465
6466 pkt_cnt--;
6467 urb_len -= pkt_offset;
6468 next_skb = NULL;
6469 } while (skb && pkt_cnt > 0 &&
6470 urb_len >= sizeof(struct rtl8xxxu_rxdesc16));
6471
6472 return RX_TYPE_DATA_PKT;
6473 }
6474
rtl8xxxu_parse_rxdesc24(struct rtl8xxxu_priv * priv,struct sk_buff * skb)6475 int rtl8xxxu_parse_rxdesc24(struct rtl8xxxu_priv *priv, struct sk_buff *skb)
6476 {
6477 struct ieee80211_hw *hw = priv->hw;
6478 struct ieee80211_rx_status *rx_status;
6479 struct rtl8xxxu_rxdesc24 *rx_desc;
6480 struct rtl8723au_phy_stats *phy_stats;
6481 struct sk_buff *next_skb = NULL;
6482 __le32 *_rx_desc_le;
6483 u32 *_rx_desc;
6484 int drvinfo_sz, desc_shift;
6485 int i, pkt_len, urb_len, pkt_offset;
6486
6487 urb_len = skb->len;
6488
6489 if (urb_len < sizeof(struct rtl8xxxu_rxdesc24)) {
6490 kfree_skb(skb);
6491 return RX_TYPE_ERROR;
6492 }
6493
6494 do {
6495 rx_desc = (struct rtl8xxxu_rxdesc24 *)skb->data;
6496 _rx_desc_le = (__le32 *)skb->data;
6497 _rx_desc = (u32 *)skb->data;
6498
6499 for (i = 0; i < (sizeof(struct rtl8xxxu_rxdesc24) / sizeof(u32)); i++)
6500 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);
6501
6502 pkt_len = rx_desc->pktlen;
6503
6504 drvinfo_sz = rx_desc->drvinfo_sz * 8;
6505 desc_shift = rx_desc->shift;
6506 pkt_offset = roundup(pkt_len + drvinfo_sz + desc_shift +
6507 sizeof(struct rtl8xxxu_rxdesc24), 8);
6508
6509 /*
6510 * Only clone the skb if there's enough data at the end to
6511 * at least cover the rx descriptor
6512 */
6513 if (urb_len >= (pkt_offset + sizeof(struct rtl8xxxu_rxdesc24)))
6514 next_skb = skb_clone(skb, GFP_ATOMIC);
6515
6516 rx_status = IEEE80211_SKB_RXCB(skb);
6517 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
6518
6519 skb_pull(skb, sizeof(struct rtl8xxxu_rxdesc24));
6520
6521 phy_stats = (struct rtl8723au_phy_stats *)skb->data;
6522
6523 skb_pull(skb, drvinfo_sz + desc_shift);
6524
6525 skb_trim(skb, pkt_len);
6526
6527 if (rx_desc->rpt_sel) {
6528 struct device *dev = &priv->udev->dev;
6529 dev_dbg(dev, "%s: C2H packet\n", __func__);
6530 rtl8723bu_handle_c2h(priv, skb);
6531 } else {
6532 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
6533
6534 if (rx_desc->phy_stats) {
6535 priv->fops->parse_phystats(priv, rx_status, phy_stats,
6536 rx_desc->rxmcs, hdr,
6537 rx_desc->crc32 || rx_desc->icverr);
6538 if (!rx_desc->crc32 && !rx_desc->icverr)
6539 rtl8xxxu_rx_update_rssi(priv,
6540 rx_status,
6541 hdr);
6542 }
6543
6544 rx_status->mactime = rx_desc->tsfl;
6545 rx_status->flag |= RX_FLAG_MACTIME_START;
6546
6547 if (!rx_desc->swdec &&
6548 rx_desc->security != RX_DESC_ENC_NONE)
6549 rx_status->flag |= RX_FLAG_DECRYPTED;
6550 if (rx_desc->crc32)
6551 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
6552 if (rx_desc->bw)
6553 rx_status->bw = RATE_INFO_BW_40;
6554
6555 if (rx_desc->rxmcs >= DESC_RATE_MCS0) {
6556 rx_status->encoding = RX_ENC_HT;
6557 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
6558 } else {
6559 rx_status->rate_idx = rx_desc->rxmcs;
6560 }
6561
6562 rx_status->freq = hw->conf.chandef.chan->center_freq;
6563 rx_status->band = hw->conf.chandef.chan->band;
6564
6565 ieee80211_rx_irqsafe(hw, skb);
6566 }
6567
6568 skb = next_skb;
6569 if (skb)
6570 skb_pull(next_skb, pkt_offset);
6571
6572 urb_len -= pkt_offset;
6573 next_skb = NULL;
6574 } while (skb && urb_len >= sizeof(struct rtl8xxxu_rxdesc24));
6575
6576 return RX_TYPE_DATA_PKT;
6577 }
6578
rtl8xxxu_rx_complete(struct urb * urb)6579 static void rtl8xxxu_rx_complete(struct urb *urb)
6580 {
6581 struct rtl8xxxu_rx_urb *rx_urb =
6582 container_of(urb, struct rtl8xxxu_rx_urb, urb);
6583 struct ieee80211_hw *hw = rx_urb->hw;
6584 struct rtl8xxxu_priv *priv = hw->priv;
6585 struct sk_buff *skb = (struct sk_buff *)urb->context;
6586 struct device *dev = &priv->udev->dev;
6587
6588 skb_put(skb, urb->actual_length);
6589
6590 if (urb->status == 0) {
6591 priv->fops->parse_rx_desc(priv, skb);
6592
6593 skb = NULL;
6594 rx_urb->urb.context = NULL;
6595 rtl8xxxu_queue_rx_urb(priv, rx_urb);
6596 } else {
6597 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
6598 goto cleanup;
6599 }
6600 return;
6601
6602 cleanup:
6603 usb_free_urb(urb);
6604 dev_kfree_skb(skb);
6605 }
6606
rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv * priv,struct rtl8xxxu_rx_urb * rx_urb)6607 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
6608 struct rtl8xxxu_rx_urb *rx_urb)
6609 {
6610 struct rtl8xxxu_fileops *fops = priv->fops;
6611 struct sk_buff *skb;
6612 int skb_size;
6613 int ret, rx_desc_sz;
6614
6615 rx_desc_sz = fops->rx_desc_size;
6616
6617 if (priv->rx_buf_aggregation && fops->rx_agg_buf_size) {
6618 skb_size = fops->rx_agg_buf_size;
6619 skb_size += (rx_desc_sz + sizeof(struct rtl8723au_phy_stats));
6620 } else {
6621 skb_size = IEEE80211_MAX_FRAME_LEN + rx_desc_sz;
6622 }
6623
6624 skb = __netdev_alloc_skb(NULL, skb_size, GFP_KERNEL);
6625 if (!skb)
6626 return -ENOMEM;
6627
6628 memset(skb->data, 0, rx_desc_sz);
6629 usb_fill_bulk_urb(&rx_urb->urb, priv->udev, priv->pipe_in, skb->data,
6630 skb_size, rtl8xxxu_rx_complete, skb);
6631 usb_anchor_urb(&rx_urb->urb, &priv->rx_anchor);
6632 ret = usb_submit_urb(&rx_urb->urb, GFP_ATOMIC);
6633 if (ret)
6634 usb_unanchor_urb(&rx_urb->urb);
6635 return ret;
6636 }
6637
rtl8xxxu_int_complete(struct urb * urb)6638 static void rtl8xxxu_int_complete(struct urb *urb)
6639 {
6640 struct rtl8xxxu_priv *priv = (struct rtl8xxxu_priv *)urb->context;
6641 struct device *dev = &priv->udev->dev;
6642 int ret;
6643
6644 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_INTERRUPT)
6645 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
6646 if (urb->status == 0) {
6647 usb_anchor_urb(urb, &priv->int_anchor);
6648 ret = usb_submit_urb(urb, GFP_ATOMIC);
6649 if (ret)
6650 usb_unanchor_urb(urb);
6651 } else {
6652 dev_dbg(dev, "%s: Error %i\n", __func__, urb->status);
6653 }
6654 }
6655
6656
rtl8xxxu_submit_int_urb(struct ieee80211_hw * hw)6657 static int rtl8xxxu_submit_int_urb(struct ieee80211_hw *hw)
6658 {
6659 struct rtl8xxxu_priv *priv = hw->priv;
6660 struct urb *urb;
6661 u32 val32;
6662 int ret;
6663
6664 urb = usb_alloc_urb(0, GFP_KERNEL);
6665 if (!urb)
6666 return -ENOMEM;
6667
6668 usb_fill_int_urb(urb, priv->udev, priv->pipe_interrupt,
6669 priv->int_buf, USB_INTR_CONTENT_LENGTH,
6670 rtl8xxxu_int_complete, priv, 1);
6671 usb_anchor_urb(urb, &priv->int_anchor);
6672 ret = usb_submit_urb(urb, GFP_KERNEL);
6673 if (ret) {
6674 usb_unanchor_urb(urb);
6675 goto error;
6676 }
6677
6678 val32 = rtl8xxxu_read32(priv, REG_USB_HIMR);
6679 val32 |= USB_HIMR_CPWM;
6680 rtl8xxxu_write32(priv, REG_USB_HIMR, val32);
6681
6682 error:
6683 usb_free_urb(urb);
6684 return ret;
6685 }
6686
rtl8xxxu_switch_ports(struct rtl8xxxu_priv * priv)6687 static void rtl8xxxu_switch_ports(struct rtl8xxxu_priv *priv)
6688 {
6689 u8 macid[ETH_ALEN], bssid[ETH_ALEN], macid_1[ETH_ALEN], bssid_1[ETH_ALEN];
6690 u8 msr, bcn_ctrl, bcn_ctrl_1, atimwnd[2], atimwnd_1[2];
6691 struct rtl8xxxu_vif *rtlvif;
6692 u8 tsftr[8], tsftr_1[8];
6693 int i;
6694
6695 msr = rtl8xxxu_read8(priv, REG_MSR);
6696 bcn_ctrl = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
6697 bcn_ctrl_1 = rtl8xxxu_read8(priv, REG_BEACON_CTRL_1);
6698
6699 for (i = 0; i < ARRAY_SIZE(atimwnd); i++)
6700 atimwnd[i] = rtl8xxxu_read8(priv, REG_ATIMWND + i);
6701 for (i = 0; i < ARRAY_SIZE(atimwnd_1); i++)
6702 atimwnd_1[i] = rtl8xxxu_read8(priv, REG_ATIMWND_1 + i);
6703
6704 for (i = 0; i < ARRAY_SIZE(tsftr); i++)
6705 tsftr[i] = rtl8xxxu_read8(priv, REG_TSFTR + i);
6706 for (i = 0; i < ARRAY_SIZE(tsftr); i++)
6707 tsftr_1[i] = rtl8xxxu_read8(priv, REG_TSFTR1 + i);
6708
6709 for (i = 0; i < ARRAY_SIZE(macid); i++)
6710 macid[i] = rtl8xxxu_read8(priv, REG_MACID + i);
6711
6712 for (i = 0; i < ARRAY_SIZE(bssid); i++)
6713 bssid[i] = rtl8xxxu_read8(priv, REG_BSSID + i);
6714
6715 for (i = 0; i < ARRAY_SIZE(macid_1); i++)
6716 macid_1[i] = rtl8xxxu_read8(priv, REG_MACID1 + i);
6717
6718 for (i = 0; i < ARRAY_SIZE(bssid_1); i++)
6719 bssid_1[i] = rtl8xxxu_read8(priv, REG_BSSID1 + i);
6720
6721 /* disable bcn function, disable update TSF */
6722 rtl8xxxu_write8(priv, REG_BEACON_CTRL, (bcn_ctrl &
6723 (~BEACON_FUNCTION_ENABLE)) | BEACON_DISABLE_TSF_UPDATE);
6724 rtl8xxxu_write8(priv, REG_BEACON_CTRL_1, (bcn_ctrl_1 &
6725 (~BEACON_FUNCTION_ENABLE)) | BEACON_DISABLE_TSF_UPDATE);
6726
6727 /* switch msr */
6728 msr = (msr & 0xf0) | ((msr & 0x03) << 2) | ((msr & 0x0c) >> 2);
6729 rtl8xxxu_write8(priv, REG_MSR, msr);
6730
6731 /* write port0 */
6732 rtl8xxxu_write8(priv, REG_BEACON_CTRL, bcn_ctrl_1 & ~BEACON_FUNCTION_ENABLE);
6733 for (i = 0; i < ARRAY_SIZE(atimwnd_1); i++)
6734 rtl8xxxu_write8(priv, REG_ATIMWND + i, atimwnd_1[i]);
6735 for (i = 0; i < ARRAY_SIZE(tsftr_1); i++)
6736 rtl8xxxu_write8(priv, REG_TSFTR + i, tsftr_1[i]);
6737 for (i = 0; i < ARRAY_SIZE(macid_1); i++)
6738 rtl8xxxu_write8(priv, REG_MACID + i, macid_1[i]);
6739 for (i = 0; i < ARRAY_SIZE(bssid_1); i++)
6740 rtl8xxxu_write8(priv, REG_BSSID + i, bssid_1[i]);
6741
6742 /* write port1 */
6743 rtl8xxxu_write8(priv, REG_BEACON_CTRL_1, bcn_ctrl & ~BEACON_FUNCTION_ENABLE);
6744 for (i = 0; i < ARRAY_SIZE(atimwnd); i++)
6745 rtl8xxxu_write8(priv, REG_ATIMWND_1 + i, atimwnd[i]);
6746 for (i = 0; i < ARRAY_SIZE(tsftr); i++)
6747 rtl8xxxu_write8(priv, REG_TSFTR1 + i, tsftr[i]);
6748 for (i = 0; i < ARRAY_SIZE(macid); i++)
6749 rtl8xxxu_write8(priv, REG_MACID1 + i, macid[i]);
6750 for (i = 0; i < ARRAY_SIZE(bssid); i++)
6751 rtl8xxxu_write8(priv, REG_BSSID1 + i, bssid[i]);
6752
6753 /* write bcn ctl */
6754 rtl8xxxu_write8(priv, REG_BEACON_CTRL, bcn_ctrl_1);
6755 rtl8xxxu_write8(priv, REG_BEACON_CTRL_1, bcn_ctrl);
6756 swap(priv->vifs[0], priv->vifs[1]);
6757
6758 /* priv->vifs[0] is NULL here, based on how this function is currently
6759 * called from rtl8xxxu_add_interface().
6760 * When this function will be used in the future for a different
6761 * scenario, please check whether vifs[0] or vifs[1] can be NULL and if
6762 * necessary add code to set port_num = 1.
6763 */
6764 rtlvif = (struct rtl8xxxu_vif *)priv->vifs[1]->drv_priv;
6765 rtlvif->port_num = 1;
6766 }
6767
rtl8xxxu_add_interface(struct ieee80211_hw * hw,struct ieee80211_vif * vif)6768 static int rtl8xxxu_add_interface(struct ieee80211_hw *hw,
6769 struct ieee80211_vif *vif)
6770 {
6771 struct rtl8xxxu_vif *rtlvif = (struct rtl8xxxu_vif *)vif->drv_priv;
6772 struct rtl8xxxu_priv *priv = hw->priv;
6773 int port_num;
6774 u8 val8;
6775
6776 if (!priv->vifs[0])
6777 port_num = 0;
6778 else if (!priv->vifs[1])
6779 port_num = 1;
6780 else
6781 return -EOPNOTSUPP;
6782
6783 switch (vif->type) {
6784 case NL80211_IFTYPE_STATION:
6785 if (port_num == 0) {
6786 rtl8xxxu_stop_tx_beacon(priv);
6787
6788 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
6789 val8 |= BEACON_ATIM | BEACON_FUNCTION_ENABLE |
6790 BEACON_DISABLE_TSF_UPDATE;
6791 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
6792 }
6793 break;
6794 case NL80211_IFTYPE_AP:
6795 if (port_num == 1) {
6796 rtl8xxxu_switch_ports(priv);
6797 port_num = 0;
6798 }
6799
6800 rtl8xxxu_write8(priv, REG_BEACON_CTRL,
6801 BEACON_DISABLE_TSF_UPDATE | BEACON_CTRL_MBSSID);
6802 rtl8xxxu_write8(priv, REG_ATIMWND, 0x0c); /* 12ms */
6803 rtl8xxxu_write16(priv, REG_TSFTR_SYN_OFFSET, 0x7fff); /* ~32ms */
6804 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, DUAL_TSF_RESET_TSF0);
6805
6806 /* enable BCN0 function */
6807 rtl8xxxu_write8(priv, REG_BEACON_CTRL,
6808 BEACON_DISABLE_TSF_UPDATE |
6809 BEACON_FUNCTION_ENABLE | BEACON_CTRL_MBSSID |
6810 BEACON_CTRL_TX_BEACON_RPT);
6811
6812 /* select BCN on port 0 */
6813 val8 = rtl8xxxu_read8(priv, REG_CCK_CHECK);
6814 val8 &= ~BIT_BCN_PORT_SEL;
6815 rtl8xxxu_write8(priv, REG_CCK_CHECK, val8);
6816 break;
6817 default:
6818 return -EOPNOTSUPP;
6819 }
6820
6821 priv->vifs[port_num] = vif;
6822 rtlvif->port_num = port_num;
6823 rtlvif->hw_key_idx = 0xff;
6824
6825 rtl8xxxu_set_linktype(priv, vif->type, port_num);
6826 ether_addr_copy(priv->mac_addr, vif->addr);
6827 rtl8xxxu_set_mac(priv, port_num);
6828
6829 return 0;
6830 }
6831
rtl8xxxu_remove_interface(struct ieee80211_hw * hw,struct ieee80211_vif * vif)6832 static void rtl8xxxu_remove_interface(struct ieee80211_hw *hw,
6833 struct ieee80211_vif *vif)
6834 {
6835 struct rtl8xxxu_vif *rtlvif = (struct rtl8xxxu_vif *)vif->drv_priv;
6836 struct rtl8xxxu_priv *priv = hw->priv;
6837
6838 dev_dbg(&priv->udev->dev, "%s\n", __func__);
6839
6840 priv->vifs[rtlvif->port_num] = NULL;
6841 }
6842
rtl8xxxu_config(struct ieee80211_hw * hw,int radio_idx,u32 changed)6843 static int rtl8xxxu_config(struct ieee80211_hw *hw, int radio_idx, u32 changed)
6844 {
6845 struct rtl8xxxu_priv *priv = hw->priv;
6846 struct device *dev = &priv->udev->dev;
6847 int ret = 0, channel;
6848 bool ht40;
6849
6850 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
6851 dev_info(dev,
6852 "%s: channel: %i (changed %08x chandef.width %02x)\n",
6853 __func__, hw->conf.chandef.chan->hw_value,
6854 changed, hw->conf.chandef.width);
6855
6856 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
6857 switch (hw->conf.chandef.width) {
6858 case NL80211_CHAN_WIDTH_20_NOHT:
6859 case NL80211_CHAN_WIDTH_20:
6860 ht40 = false;
6861 break;
6862 case NL80211_CHAN_WIDTH_40:
6863 ht40 = true;
6864 break;
6865 default:
6866 ret = -ENOTSUPP;
6867 goto exit;
6868 }
6869
6870 channel = hw->conf.chandef.chan->hw_value;
6871
6872 priv->fops->set_tx_power(priv, channel, ht40);
6873
6874 priv->fops->config_channel(hw);
6875 }
6876
6877 exit:
6878 return ret;
6879 }
6880
rtl8xxxu_conf_tx(struct ieee80211_hw * hw,struct ieee80211_vif * vif,unsigned int link_id,u16 queue,const struct ieee80211_tx_queue_params * param)6881 static int rtl8xxxu_conf_tx(struct ieee80211_hw *hw,
6882 struct ieee80211_vif *vif,
6883 unsigned int link_id, u16 queue,
6884 const struct ieee80211_tx_queue_params *param)
6885 {
6886 struct rtl8xxxu_priv *priv = hw->priv;
6887 struct device *dev = &priv->udev->dev;
6888 u32 val32;
6889 u8 aifs, acm_ctrl, acm_bit;
6890
6891 aifs = param->aifs;
6892
6893 val32 = aifs |
6894 fls(param->cw_min) << EDCA_PARAM_ECW_MIN_SHIFT |
6895 fls(param->cw_max) << EDCA_PARAM_ECW_MAX_SHIFT |
6896 (u32)param->txop << EDCA_PARAM_TXOP_SHIFT;
6897
6898 acm_ctrl = rtl8xxxu_read8(priv, REG_ACM_HW_CTRL);
6899 dev_dbg(dev,
6900 "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n",
6901 __func__, queue, val32, param->acm, acm_ctrl);
6902
6903 switch (queue) {
6904 case IEEE80211_AC_VO:
6905 acm_bit = ACM_HW_CTRL_VO;
6906 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32);
6907 break;
6908 case IEEE80211_AC_VI:
6909 acm_bit = ACM_HW_CTRL_VI;
6910 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32);
6911 break;
6912 case IEEE80211_AC_BE:
6913 acm_bit = ACM_HW_CTRL_BE;
6914 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32);
6915 break;
6916 case IEEE80211_AC_BK:
6917 acm_bit = ACM_HW_CTRL_BK;
6918 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32);
6919 break;
6920 default:
6921 acm_bit = 0;
6922 break;
6923 }
6924
6925 if (param->acm)
6926 acm_ctrl |= acm_bit;
6927 else
6928 acm_ctrl &= ~acm_bit;
6929 rtl8xxxu_write8(priv, REG_ACM_HW_CTRL, acm_ctrl);
6930
6931 return 0;
6932 }
6933
rtl8xxxu_configure_filter(struct ieee80211_hw * hw,unsigned int changed_flags,unsigned int * total_flags,u64 multicast)6934 static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw,
6935 unsigned int changed_flags,
6936 unsigned int *total_flags, u64 multicast)
6937 {
6938 struct rtl8xxxu_priv *priv = hw->priv;
6939 u32 rcr = priv->regrcr;
6940
6941 dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n",
6942 __func__, changed_flags, *total_flags);
6943
6944 /*
6945 * FIF_ALLMULTI ignored as all multicast frames are accepted (REG_MAR)
6946 */
6947
6948 if (*total_flags & FIF_FCSFAIL)
6949 rcr |= RCR_ACCEPT_CRC32;
6950 else
6951 rcr &= ~RCR_ACCEPT_CRC32;
6952
6953 /*
6954 * FIF_PLCPFAIL not supported?
6955 */
6956
6957 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
6958 rcr &= ~(RCR_CHECK_BSSID_BEACON | RCR_CHECK_BSSID_MATCH);
6959 else
6960 rcr |= RCR_CHECK_BSSID_BEACON | RCR_CHECK_BSSID_MATCH;
6961
6962 if (priv->vifs[0] && priv->vifs[0]->type == NL80211_IFTYPE_AP)
6963 rcr &= ~(RCR_CHECK_BSSID_MATCH | RCR_CHECK_BSSID_BEACON);
6964
6965 if (*total_flags & FIF_CONTROL)
6966 rcr |= RCR_ACCEPT_CTRL_FRAME;
6967 else
6968 rcr &= ~RCR_ACCEPT_CTRL_FRAME;
6969
6970 if (*total_flags & FIF_OTHER_BSS)
6971 rcr |= RCR_ACCEPT_AP;
6972 else
6973 rcr &= ~RCR_ACCEPT_AP;
6974
6975 if (*total_flags & FIF_PSPOLL)
6976 rcr |= RCR_ACCEPT_PM;
6977 else
6978 rcr &= ~RCR_ACCEPT_PM;
6979
6980 /*
6981 * FIF_PROBE_REQ ignored as probe requests always seem to be accepted
6982 */
6983
6984 rtl8xxxu_write32(priv, REG_RCR, rcr);
6985 priv->regrcr = rcr;
6986
6987 *total_flags &= (FIF_ALLMULTI | FIF_FCSFAIL | FIF_BCN_PRBRESP_PROMISC |
6988 FIF_CONTROL | FIF_OTHER_BSS | FIF_PSPOLL |
6989 FIF_PROBE_REQ);
6990 }
6991
rtl8xxxu_set_rts_threshold(struct ieee80211_hw * hw,int radio_idx,u32 rts)6992 static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw *hw, int radio_idx,
6993 u32 rts)
6994 {
6995 if (rts > 2347 && rts != (u32)-1)
6996 return -EINVAL;
6997
6998 return 0;
6999 }
7000
rtl8xxxu_get_free_sec_cam(struct ieee80211_hw * hw)7001 static int rtl8xxxu_get_free_sec_cam(struct ieee80211_hw *hw)
7002 {
7003 struct rtl8xxxu_priv *priv = hw->priv;
7004
7005 return find_first_zero_bit(priv->cam_map, priv->fops->max_sec_cam_num);
7006 }
7007
rtl8xxxu_set_key(struct ieee80211_hw * hw,enum set_key_cmd cmd,struct ieee80211_vif * vif,struct ieee80211_sta * sta,struct ieee80211_key_conf * key)7008 static int rtl8xxxu_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
7009 struct ieee80211_vif *vif,
7010 struct ieee80211_sta *sta,
7011 struct ieee80211_key_conf *key)
7012 {
7013 struct rtl8xxxu_vif *rtlvif = (struct rtl8xxxu_vif *)vif->drv_priv;
7014 struct rtl8xxxu_priv *priv = hw->priv;
7015 struct device *dev = &priv->udev->dev;
7016 u8 mac_addr[ETH_ALEN];
7017 u8 val8;
7018 u16 val16;
7019 u32 val32;
7020 int retval = -EOPNOTSUPP;
7021
7022 dev_dbg(dev, "%s: cmd %02x, cipher %08x, index %i\n",
7023 __func__, cmd, key->cipher, key->keyidx);
7024
7025 if (key->keyidx > 3)
7026 return -EOPNOTSUPP;
7027
7028 switch (key->cipher) {
7029 case WLAN_CIPHER_SUITE_WEP40:
7030 case WLAN_CIPHER_SUITE_WEP104:
7031
7032 break;
7033 case WLAN_CIPHER_SUITE_CCMP:
7034 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
7035 break;
7036 case WLAN_CIPHER_SUITE_TKIP:
7037 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
7038 break;
7039 default:
7040 return -EOPNOTSUPP;
7041 }
7042
7043 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
7044 dev_dbg(dev, "%s: pairwise key\n", __func__);
7045 ether_addr_copy(mac_addr, sta->addr);
7046 } else {
7047 dev_dbg(dev, "%s: group key\n", __func__);
7048 ether_addr_copy(mac_addr, vif->bss_conf.bssid);
7049 }
7050
7051 val16 = rtl8xxxu_read16(priv, REG_CR);
7052 val16 |= CR_SECURITY_ENABLE;
7053 rtl8xxxu_write16(priv, REG_CR, val16);
7054
7055 val8 = SEC_CFG_TX_SEC_ENABLE | SEC_CFG_TXBC_USE_DEFKEY |
7056 SEC_CFG_RX_SEC_ENABLE | SEC_CFG_RXBC_USE_DEFKEY;
7057 val8 |= SEC_CFG_TX_USE_DEFKEY | SEC_CFG_RX_USE_DEFKEY;
7058 rtl8xxxu_write8(priv, REG_SECURITY_CFG, val8);
7059
7060 switch (cmd) {
7061 case SET_KEY:
7062
7063 retval = rtl8xxxu_get_free_sec_cam(hw);
7064 if (retval < 0)
7065 return -EOPNOTSUPP;
7066
7067 key->hw_key_idx = retval;
7068
7069 if (vif->type == NL80211_IFTYPE_AP && !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
7070 rtlvif->hw_key_idx = key->hw_key_idx;
7071
7072 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
7073 rtl8xxxu_cam_write(priv, key, mac_addr);
7074 set_bit(key->hw_key_idx, priv->cam_map);
7075 retval = 0;
7076 break;
7077 case DISABLE_KEY:
7078 rtl8xxxu_write32(priv, REG_CAM_WRITE, 0x00000000);
7079 val32 = CAM_CMD_POLLING | CAM_CMD_WRITE |
7080 key->hw_key_idx << CAM_CMD_KEY_SHIFT;
7081 rtl8xxxu_write32(priv, REG_CAM_CMD, val32);
7082 rtlvif->hw_key_idx = 0xff;
7083 clear_bit(key->hw_key_idx, priv->cam_map);
7084 retval = 0;
7085 break;
7086 default:
7087 dev_warn(dev, "%s: Unsupported command %02x\n", __func__, cmd);
7088 }
7089
7090 return retval;
7091 }
7092
7093 static int
rtl8xxxu_ampdu_action(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_ampdu_params * params)7094 rtl8xxxu_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
7095 struct ieee80211_ampdu_params *params)
7096 {
7097 struct rtl8xxxu_priv *priv = hw->priv;
7098 struct device *dev = &priv->udev->dev;
7099 u8 ampdu_factor, ampdu_density;
7100 struct ieee80211_sta *sta = params->sta;
7101 u16 tid = params->tid;
7102 enum ieee80211_ampdu_mlme_action action = params->action;
7103
7104 switch (action) {
7105 case IEEE80211_AMPDU_TX_START:
7106 dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_START\n", __func__);
7107 ampdu_factor = sta->deflink.ht_cap.ampdu_factor;
7108 ampdu_density = sta->deflink.ht_cap.ampdu_density;
7109 rtl8xxxu_set_ampdu_factor(priv, ampdu_factor);
7110 rtl8xxxu_set_ampdu_min_space(priv, ampdu_density);
7111 dev_dbg(dev,
7112 "Changed HT: ampdu_factor %02x, ampdu_density %02x\n",
7113 ampdu_factor, ampdu_density);
7114 return IEEE80211_AMPDU_TX_START_IMMEDIATE;
7115 case IEEE80211_AMPDU_TX_STOP_CONT:
7116 case IEEE80211_AMPDU_TX_STOP_FLUSH:
7117 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
7118 dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_STOP\n", __func__);
7119 rtl8xxxu_set_ampdu_factor(priv, 0);
7120 rtl8xxxu_set_ampdu_min_space(priv, 0);
7121 clear_bit(tid, priv->tx_aggr_started);
7122 clear_bit(tid, priv->tid_tx_operational);
7123 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
7124 break;
7125 case IEEE80211_AMPDU_TX_OPERATIONAL:
7126 dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_OPERATIONAL\n", __func__);
7127 set_bit(tid, priv->tid_tx_operational);
7128 break;
7129 case IEEE80211_AMPDU_RX_START:
7130 dev_dbg(dev, "%s: IEEE80211_AMPDU_RX_START\n", __func__);
7131 break;
7132 case IEEE80211_AMPDU_RX_STOP:
7133 dev_dbg(dev, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__);
7134 break;
7135 default:
7136 break;
7137 }
7138 return 0;
7139 }
7140
7141 static void
rtl8xxxu_sta_statistics(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_sta * sta,struct station_info * sinfo)7142 rtl8xxxu_sta_statistics(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
7143 struct ieee80211_sta *sta, struct station_info *sinfo)
7144 {
7145 struct rtl8xxxu_priv *priv = hw->priv;
7146
7147 sinfo->txrate = priv->ra_report.txrate;
7148 sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BITRATE);
7149 }
7150
rtl8xxxu_signal_to_snr(int signal)7151 static u8 rtl8xxxu_signal_to_snr(int signal)
7152 {
7153 if (signal < RTL8XXXU_NOISE_FLOOR_MIN)
7154 signal = RTL8XXXU_NOISE_FLOOR_MIN;
7155 else if (signal > 0)
7156 signal = 0;
7157 return (u8)(signal - RTL8XXXU_NOISE_FLOOR_MIN);
7158 }
7159
rtl8xxxu_refresh_rate_mask(struct rtl8xxxu_priv * priv,int signal,struct ieee80211_sta * sta,bool force)7160 static void rtl8xxxu_refresh_rate_mask(struct rtl8xxxu_priv *priv,
7161 int signal, struct ieee80211_sta *sta,
7162 bool force)
7163 {
7164 struct rtl8xxxu_sta_info *sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv;
7165 struct ieee80211_hw *hw = priv->hw;
7166 u16 wireless_mode;
7167 u8 rssi_level, ratr_idx;
7168 u8 txbw_40mhz;
7169 u8 snr, snr_thresh_high, snr_thresh_low;
7170 u8 go_up_gap = 5;
7171 u8 macid = rtl8xxxu_get_macid(priv, sta);
7172
7173 rssi_level = sta_info->rssi_level;
7174 snr = rtl8xxxu_signal_to_snr(signal);
7175 snr_thresh_high = RTL8XXXU_SNR_THRESH_HIGH;
7176 snr_thresh_low = RTL8XXXU_SNR_THRESH_LOW;
7177 txbw_40mhz = (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) ? 1 : 0;
7178
7179 switch (rssi_level) {
7180 case RTL8XXXU_RATR_STA_MID:
7181 snr_thresh_high += go_up_gap;
7182 break;
7183 case RTL8XXXU_RATR_STA_LOW:
7184 snr_thresh_high += go_up_gap;
7185 snr_thresh_low += go_up_gap;
7186 break;
7187 default:
7188 break;
7189 }
7190
7191 if (snr > snr_thresh_high)
7192 rssi_level = RTL8XXXU_RATR_STA_HIGH;
7193 else if (snr > snr_thresh_low)
7194 rssi_level = RTL8XXXU_RATR_STA_MID;
7195 else
7196 rssi_level = RTL8XXXU_RATR_STA_LOW;
7197
7198 if (rssi_level != sta_info->rssi_level || force) {
7199 int sgi = 0;
7200 u32 rate_bitmap = 0;
7201
7202 rate_bitmap = (sta->deflink.supp_rates[0] & 0xfff) |
7203 (sta->deflink.ht_cap.mcs.rx_mask[0] << 12) |
7204 (sta->deflink.ht_cap.mcs.rx_mask[1] << 20);
7205 if (sta->deflink.ht_cap.cap &
7206 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))
7207 sgi = 1;
7208
7209 wireless_mode = rtl8xxxu_wireless_mode(hw, sta);
7210 switch (wireless_mode) {
7211 case WIRELESS_MODE_B:
7212 ratr_idx = RATEID_IDX_B;
7213 if (rate_bitmap & 0x0000000c)
7214 rate_bitmap &= 0x0000000d;
7215 else
7216 rate_bitmap &= 0x0000000f;
7217 break;
7218 case WIRELESS_MODE_A:
7219 case WIRELESS_MODE_G:
7220 ratr_idx = RATEID_IDX_G;
7221 if (rssi_level == RTL8XXXU_RATR_STA_HIGH)
7222 rate_bitmap &= 0x00000f00;
7223 else
7224 rate_bitmap &= 0x00000ff0;
7225 break;
7226 case (WIRELESS_MODE_B | WIRELESS_MODE_G):
7227 ratr_idx = RATEID_IDX_BG;
7228 if (rssi_level == RTL8XXXU_RATR_STA_HIGH)
7229 rate_bitmap &= 0x00000f00;
7230 else if (rssi_level == RTL8XXXU_RATR_STA_MID)
7231 rate_bitmap &= 0x00000ff0;
7232 else
7233 rate_bitmap &= 0x00000ff5;
7234 break;
7235 case WIRELESS_MODE_N_24G:
7236 case WIRELESS_MODE_N_5G:
7237 case (WIRELESS_MODE_G | WIRELESS_MODE_N_24G):
7238 case (WIRELESS_MODE_A | WIRELESS_MODE_N_5G):
7239 if (priv->tx_paths == 2 && priv->rx_paths == 2)
7240 ratr_idx = RATEID_IDX_GN_N2SS;
7241 else
7242 ratr_idx = RATEID_IDX_GN_N1SS;
7243 break;
7244 case (WIRELESS_MODE_B | WIRELESS_MODE_G | WIRELESS_MODE_N_24G):
7245 case (WIRELESS_MODE_B | WIRELESS_MODE_N_24G):
7246 if (txbw_40mhz) {
7247 if (priv->tx_paths == 2 && priv->rx_paths == 2)
7248 ratr_idx = RATEID_IDX_BGN_40M_2SS;
7249 else
7250 ratr_idx = RATEID_IDX_BGN_40M_1SS;
7251 } else {
7252 if (priv->tx_paths == 2 && priv->rx_paths == 2)
7253 ratr_idx = RATEID_IDX_BGN_20M_2SS_BN;
7254 else
7255 ratr_idx = RATEID_IDX_BGN_20M_1SS_BN;
7256 }
7257
7258 if (priv->tx_paths == 2 && priv->rx_paths == 2) {
7259 if (rssi_level == RTL8XXXU_RATR_STA_HIGH) {
7260 rate_bitmap &= 0x0f8f0000;
7261 } else if (rssi_level == RTL8XXXU_RATR_STA_MID) {
7262 rate_bitmap &= 0x0f8ff000;
7263 } else {
7264 if (txbw_40mhz)
7265 rate_bitmap &= 0x0f8ff015;
7266 else
7267 rate_bitmap &= 0x0f8ff005;
7268 }
7269 } else {
7270 if (rssi_level == RTL8XXXU_RATR_STA_HIGH) {
7271 rate_bitmap &= 0x000f0000;
7272 } else if (rssi_level == RTL8XXXU_RATR_STA_MID) {
7273 rate_bitmap &= 0x000ff000;
7274 } else {
7275 if (txbw_40mhz)
7276 rate_bitmap &= 0x000ff015;
7277 else
7278 rate_bitmap &= 0x000ff005;
7279 }
7280 }
7281 break;
7282 default:
7283 ratr_idx = RATEID_IDX_BGN_40M_2SS;
7284 rate_bitmap &= 0x0fffffff;
7285 break;
7286 }
7287
7288 sta_info->rssi_level = rssi_level;
7289 priv->fops->update_rate_mask(priv, rate_bitmap, ratr_idx, sgi, txbw_40mhz, macid);
7290 }
7291 }
7292
rtl8xxxu_set_atc_status(struct rtl8xxxu_priv * priv,bool atc_status)7293 static void rtl8xxxu_set_atc_status(struct rtl8xxxu_priv *priv, bool atc_status)
7294 {
7295 struct rtl8xxxu_cfo_tracking *cfo = &priv->cfo_tracking;
7296 u32 val32;
7297
7298 if (atc_status == cfo->atc_status)
7299 return;
7300
7301 cfo->atc_status = atc_status;
7302
7303 val32 = rtl8xxxu_read32(priv, REG_OFDM1_CFO_TRACKING);
7304 if (atc_status)
7305 val32 |= CFO_TRACKING_ATC_STATUS;
7306 else
7307 val32 &= ~CFO_TRACKING_ATC_STATUS;
7308 rtl8xxxu_write32(priv, REG_OFDM1_CFO_TRACKING, val32);
7309 }
7310
7311 /* Central frequency offset correction */
rtl8xxxu_track_cfo(struct rtl8xxxu_priv * priv)7312 static void rtl8xxxu_track_cfo(struct rtl8xxxu_priv *priv)
7313 {
7314 struct rtl8xxxu_cfo_tracking *cfo = &priv->cfo_tracking;
7315 int cfo_khz_a, cfo_khz_b, cfo_average;
7316 int crystal_cap;
7317
7318 if (!rtl8xxxu_is_assoc(priv)) {
7319 /* Reset */
7320 cfo->adjust = true;
7321
7322 if (cfo->crystal_cap > priv->default_crystal_cap)
7323 priv->fops->set_crystal_cap(priv, cfo->crystal_cap - 1);
7324 else if (cfo->crystal_cap < priv->default_crystal_cap)
7325 priv->fops->set_crystal_cap(priv, cfo->crystal_cap + 1);
7326
7327 rtl8xxxu_set_atc_status(priv, true);
7328
7329 return;
7330 }
7331
7332 if (cfo->packet_count == cfo->packet_count_pre)
7333 /* No new information. */
7334 return;
7335
7336 cfo->packet_count_pre = cfo->packet_count;
7337
7338 /* CFO_tail[1:0] is S(8,7), (num_subcarrier>>7) x 312.5K = CFO value(K Hz) */
7339 cfo_khz_a = (int)((cfo->cfo_tail[0] * 3125) / 10) >> 7;
7340 cfo_khz_b = (int)((cfo->cfo_tail[1] * 3125) / 10) >> 7;
7341
7342 if (priv->tx_paths == 1)
7343 cfo_average = cfo_khz_a;
7344 else
7345 cfo_average = (cfo_khz_a + cfo_khz_b) / 2;
7346
7347 dev_dbg(&priv->udev->dev, "cfo_average: %d\n", cfo_average);
7348
7349 if (cfo->adjust) {
7350 if (abs(cfo_average) < CFO_TH_XTAL_LOW)
7351 cfo->adjust = false;
7352 } else {
7353 if (abs(cfo_average) > CFO_TH_XTAL_HIGH)
7354 cfo->adjust = true;
7355 }
7356
7357 /*
7358 * TODO: We should return here only if bluetooth is enabled.
7359 * See the vendor drivers for how to determine that.
7360 */
7361 if (priv->has_bluetooth)
7362 return;
7363
7364 if (!cfo->adjust)
7365 return;
7366
7367 crystal_cap = cfo->crystal_cap;
7368
7369 if (cfo_average > CFO_TH_XTAL_LOW)
7370 crystal_cap++;
7371 else if (cfo_average < -CFO_TH_XTAL_LOW)
7372 crystal_cap--;
7373
7374 crystal_cap = clamp(crystal_cap, 0, 0x3f);
7375
7376 priv->fops->set_crystal_cap(priv, crystal_cap);
7377
7378 rtl8xxxu_set_atc_status(priv, abs(cfo_average) >= CFO_TH_ATC);
7379 }
7380
rtl8xxxu_ra_iter(void * data,struct ieee80211_sta * sta)7381 static void rtl8xxxu_ra_iter(void *data, struct ieee80211_sta *sta)
7382 {
7383 struct rtl8xxxu_sta_info *sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv;
7384 struct rtl8xxxu_priv *priv = data;
7385 int signal = -ewma_rssi_read(&sta_info->avg_rssi);
7386
7387 priv->fops->report_rssi(priv, rtl8xxxu_get_macid(priv, sta),
7388 rtl8xxxu_signal_to_snr(signal));
7389 rtl8xxxu_refresh_rate_mask(priv, signal, sta, false);
7390 }
7391
7392 struct rtl8xxxu_stas_entry {
7393 struct list_head list;
7394 struct ieee80211_sta *sta;
7395 };
7396
7397 struct rtl8xxxu_iter_stas_data {
7398 struct rtl8xxxu_priv *priv;
7399 struct list_head list;
7400 };
7401
rtl8xxxu_collect_sta_iter(void * data,struct ieee80211_sta * sta)7402 static void rtl8xxxu_collect_sta_iter(void *data, struct ieee80211_sta *sta)
7403 {
7404 struct rtl8xxxu_iter_stas_data *iter_stas = data;
7405 struct rtl8xxxu_stas_entry *stas_entry;
7406
7407 stas_entry = kmalloc(sizeof(*stas_entry), GFP_ATOMIC);
7408 if (!stas_entry)
7409 return;
7410
7411 stas_entry->sta = sta;
7412 list_add_tail(&stas_entry->list, &iter_stas->list);
7413 }
7414
rtl8xxxu_watchdog_callback(struct work_struct * work)7415 static void rtl8xxxu_watchdog_callback(struct work_struct *work)
7416 {
7417
7418 struct rtl8xxxu_iter_stas_data iter_data;
7419 struct rtl8xxxu_stas_entry *sta_entry, *tmp;
7420 struct rtl8xxxu_priv *priv;
7421
7422 priv = container_of(work, struct rtl8xxxu_priv, ra_watchdog.work);
7423 iter_data.priv = priv;
7424 INIT_LIST_HEAD(&iter_data.list);
7425
7426 mutex_lock(&priv->sta_mutex);
7427 ieee80211_iterate_stations_atomic(priv->hw, rtl8xxxu_collect_sta_iter,
7428 &iter_data);
7429 list_for_each_entry_safe(sta_entry, tmp, &iter_data.list, list) {
7430 list_del_init(&sta_entry->list);
7431 rtl8xxxu_ra_iter(priv, sta_entry->sta);
7432 kfree(sta_entry);
7433 }
7434 mutex_unlock(&priv->sta_mutex);
7435
7436 if (priv->fops->set_crystal_cap)
7437 rtl8xxxu_track_cfo(priv);
7438
7439 schedule_delayed_work(&priv->ra_watchdog, 2 * HZ);
7440 }
7441
rtl8xxxu_start(struct ieee80211_hw * hw)7442 static int rtl8xxxu_start(struct ieee80211_hw *hw)
7443 {
7444 struct rtl8xxxu_priv *priv = hw->priv;
7445 struct rtl8xxxu_rx_urb *rx_urb;
7446 struct rtl8xxxu_tx_urb *tx_urb;
7447 struct sk_buff *skb;
7448 unsigned long flags;
7449 int ret, i;
7450
7451 ret = 0;
7452
7453 init_usb_anchor(&priv->rx_anchor);
7454 init_usb_anchor(&priv->tx_anchor);
7455 init_usb_anchor(&priv->int_anchor);
7456
7457 priv->fops->enable_rf(priv);
7458 if (priv->usb_interrupts) {
7459 ret = rtl8xxxu_submit_int_urb(hw);
7460 if (ret)
7461 goto exit;
7462 }
7463
7464 for (i = 0; i < RTL8XXXU_TX_URBS; i++) {
7465 tx_urb = kmalloc(sizeof(struct rtl8xxxu_tx_urb), GFP_KERNEL);
7466 if (!tx_urb) {
7467 if (!i)
7468 ret = -ENOMEM;
7469
7470 goto error_out;
7471 }
7472 usb_init_urb(&tx_urb->urb);
7473 INIT_LIST_HEAD(&tx_urb->list);
7474 tx_urb->hw = hw;
7475 list_add(&tx_urb->list, &priv->tx_urb_free_list);
7476 priv->tx_urb_free_count++;
7477 }
7478
7479 priv->tx_stopped = false;
7480
7481 spin_lock_irqsave(&priv->rx_urb_lock, flags);
7482 priv->shutdown = false;
7483 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7484
7485 for (i = 0; i < RTL8XXXU_RX_URBS; i++) {
7486 rx_urb = kmalloc(sizeof(struct rtl8xxxu_rx_urb), GFP_KERNEL);
7487 if (!rx_urb) {
7488 if (!i)
7489 ret = -ENOMEM;
7490
7491 goto error_out;
7492 }
7493 usb_init_urb(&rx_urb->urb);
7494 INIT_LIST_HEAD(&rx_urb->list);
7495 rx_urb->hw = hw;
7496
7497 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
7498 if (ret) {
7499 if (ret != -ENOMEM) {
7500 skb = (struct sk_buff *)rx_urb->urb.context;
7501 dev_kfree_skb(skb);
7502 }
7503 rtl8xxxu_queue_rx_urb(priv, rx_urb);
7504 }
7505 }
7506
7507 schedule_delayed_work(&priv->ra_watchdog, 2 * HZ);
7508 exit:
7509 /*
7510 * Accept all data and mgmt frames
7511 */
7512 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff);
7513 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff);
7514
7515 rtl8xxxu_write32_mask(priv, REG_OFDM0_XA_AGC_CORE1,
7516 OFDM0_X_AGC_CORE1_IGI_MASK, 0x1e);
7517
7518 return ret;
7519
7520 error_out:
7521 rtl8xxxu_free_tx_resources(priv);
7522 /*
7523 * Disable all data and mgmt frames
7524 */
7525 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
7526 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
7527
7528 return ret;
7529 }
7530
rtl8xxxu_stop(struct ieee80211_hw * hw,bool suspend)7531 static void rtl8xxxu_stop(struct ieee80211_hw *hw, bool suspend)
7532 {
7533 struct rtl8xxxu_priv *priv = hw->priv;
7534 unsigned long flags;
7535
7536 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
7537
7538 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
7539 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
7540
7541 spin_lock_irqsave(&priv->rx_urb_lock, flags);
7542 priv->shutdown = true;
7543 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7544
7545 usb_kill_anchored_urbs(&priv->rx_anchor);
7546 usb_kill_anchored_urbs(&priv->tx_anchor);
7547 if (priv->usb_interrupts)
7548 usb_kill_anchored_urbs(&priv->int_anchor);
7549
7550 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
7551
7552 priv->fops->disable_rf(priv);
7553
7554 /*
7555 * Disable interrupts
7556 */
7557 if (priv->usb_interrupts)
7558 rtl8xxxu_write32(priv, REG_USB_HIMR, 0);
7559
7560 cancel_work_sync(&priv->c2hcmd_work);
7561 cancel_delayed_work_sync(&priv->ra_watchdog);
7562 cancel_delayed_work_sync(&priv->update_beacon_work);
7563
7564 rtl8xxxu_free_rx_resources(priv);
7565 rtl8xxxu_free_tx_resources(priv);
7566 }
7567
rtl8xxxu_sta_add(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_sta * sta)7568 static int rtl8xxxu_sta_add(struct ieee80211_hw *hw,
7569 struct ieee80211_vif *vif,
7570 struct ieee80211_sta *sta)
7571 {
7572 struct rtl8xxxu_sta_info *sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv;
7573 struct rtl8xxxu_vif *rtlvif = (struct rtl8xxxu_vif *)vif->drv_priv;
7574 struct rtl8xxxu_priv *priv = hw->priv;
7575
7576 mutex_lock(&priv->sta_mutex);
7577 ewma_rssi_init(&sta_info->avg_rssi);
7578 if (vif->type == NL80211_IFTYPE_AP) {
7579 sta_info->rssi_level = RTL8XXXU_RATR_STA_INIT;
7580 sta_info->macid = rtl8xxxu_acquire_macid(priv);
7581 if (sta_info->macid >= RTL8XXXU_MAX_MAC_ID_NUM) {
7582 mutex_unlock(&priv->sta_mutex);
7583 return -ENOSPC;
7584 }
7585
7586 rtl8xxxu_refresh_rate_mask(priv, 0, sta, true);
7587 priv->fops->report_connect(priv, sta_info->macid, H2C_MACID_ROLE_STA, true);
7588 } else {
7589 switch (rtlvif->port_num) {
7590 case 0:
7591 sta_info->macid = RTL8XXXU_BC_MC_MACID;
7592 break;
7593 case 1:
7594 sta_info->macid = RTL8XXXU_BC_MC_MACID1;
7595 break;
7596 default:
7597 break;
7598 }
7599 }
7600 mutex_unlock(&priv->sta_mutex);
7601
7602 return 0;
7603 }
7604
rtl8xxxu_sta_remove(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_sta * sta)7605 static int rtl8xxxu_sta_remove(struct ieee80211_hw *hw,
7606 struct ieee80211_vif *vif,
7607 struct ieee80211_sta *sta)
7608 {
7609 struct rtl8xxxu_sta_info *sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv;
7610 struct rtl8xxxu_priv *priv = hw->priv;
7611
7612 mutex_lock(&priv->sta_mutex);
7613 if (vif->type == NL80211_IFTYPE_AP)
7614 rtl8xxxu_release_macid(priv, sta_info->macid);
7615 mutex_unlock(&priv->sta_mutex);
7616
7617 return 0;
7618 }
7619
7620 static const struct ieee80211_ops rtl8xxxu_ops = {
7621 .add_chanctx = ieee80211_emulate_add_chanctx,
7622 .remove_chanctx = ieee80211_emulate_remove_chanctx,
7623 .change_chanctx = ieee80211_emulate_change_chanctx,
7624 .switch_vif_chanctx = ieee80211_emulate_switch_vif_chanctx,
7625 .tx = rtl8xxxu_tx,
7626 .wake_tx_queue = ieee80211_handle_wake_tx_queue,
7627 .add_interface = rtl8xxxu_add_interface,
7628 .remove_interface = rtl8xxxu_remove_interface,
7629 .config = rtl8xxxu_config,
7630 .conf_tx = rtl8xxxu_conf_tx,
7631 .bss_info_changed = rtl8xxxu_bss_info_changed,
7632 .start_ap = rtl8xxxu_start_ap,
7633 .configure_filter = rtl8xxxu_configure_filter,
7634 .set_rts_threshold = rtl8xxxu_set_rts_threshold,
7635 .start = rtl8xxxu_start,
7636 .stop = rtl8xxxu_stop,
7637 .sw_scan_start = rtl8xxxu_sw_scan_start,
7638 .sw_scan_complete = rtl8xxxu_sw_scan_complete,
7639 .set_key = rtl8xxxu_set_key,
7640 .ampdu_action = rtl8xxxu_ampdu_action,
7641 .sta_statistics = rtl8xxxu_sta_statistics,
7642 .get_antenna = rtl8xxxu_get_antenna,
7643 .set_tim = rtl8xxxu_set_tim,
7644 .sta_add = rtl8xxxu_sta_add,
7645 .sta_remove = rtl8xxxu_sta_remove,
7646 };
7647
rtl8xxxu_parse_usb(struct rtl8xxxu_priv * priv,struct usb_interface * interface)7648 static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv *priv,
7649 struct usb_interface *interface)
7650 {
7651 struct usb_interface_descriptor *interface_desc;
7652 struct usb_host_interface *host_interface;
7653 struct usb_endpoint_descriptor *endpoint;
7654 struct device *dev = &priv->udev->dev;
7655 int i, j = 0, endpoints;
7656 u8 dir, xtype, num;
7657 int ret = 0;
7658
7659 host_interface = interface->cur_altsetting;
7660 interface_desc = &host_interface->desc;
7661 endpoints = interface_desc->bNumEndpoints;
7662
7663 for (i = 0; i < endpoints; i++) {
7664 endpoint = &host_interface->endpoint[i].desc;
7665
7666 dir = endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK;
7667 num = usb_endpoint_num(endpoint);
7668 xtype = usb_endpoint_type(endpoint);
7669 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
7670 dev_dbg(dev,
7671 "%s: endpoint: dir %02x, # %02x, type %02x\n",
7672 __func__, dir, num, xtype);
7673 if (usb_endpoint_dir_in(endpoint) &&
7674 usb_endpoint_xfer_bulk(endpoint)) {
7675 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
7676 dev_dbg(dev, "%s: in endpoint num %i\n",
7677 __func__, num);
7678
7679 if (priv->pipe_in) {
7680 dev_warn(dev,
7681 "%s: Too many IN pipes\n", __func__);
7682 ret = -EINVAL;
7683 goto exit;
7684 }
7685
7686 priv->pipe_in = usb_rcvbulkpipe(priv->udev, num);
7687 }
7688
7689 if (usb_endpoint_dir_in(endpoint) &&
7690 usb_endpoint_xfer_int(endpoint)) {
7691 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
7692 dev_dbg(dev, "%s: interrupt endpoint num %i\n",
7693 __func__, num);
7694
7695 if (priv->pipe_interrupt) {
7696 dev_warn(dev, "%s: Too many INTERRUPT pipes\n",
7697 __func__);
7698 ret = -EINVAL;
7699 goto exit;
7700 }
7701
7702 priv->pipe_interrupt = usb_rcvintpipe(priv->udev, num);
7703 }
7704
7705 if (usb_endpoint_dir_out(endpoint) &&
7706 usb_endpoint_xfer_bulk(endpoint)) {
7707 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
7708 dev_dbg(dev, "%s: out endpoint num %i\n",
7709 __func__, num);
7710 if (j >= RTL8XXXU_OUT_ENDPOINTS) {
7711 dev_warn(dev,
7712 "%s: Too many OUT pipes\n", __func__);
7713 ret = -EINVAL;
7714 goto exit;
7715 }
7716 priv->out_ep[j++] = num;
7717 }
7718 }
7719 exit:
7720 priv->nr_out_eps = j;
7721 return ret;
7722 }
7723
rtl8xxxu_init_led(struct rtl8xxxu_priv * priv)7724 static void rtl8xxxu_init_led(struct rtl8xxxu_priv *priv)
7725 {
7726 struct led_classdev *led = &priv->led_cdev;
7727
7728 if (!priv->fops->led_classdev_brightness_set)
7729 return;
7730
7731 led->brightness_set_blocking = priv->fops->led_classdev_brightness_set;
7732
7733 snprintf(priv->led_name, sizeof(priv->led_name),
7734 "rtl8xxxu-usb%s", dev_name(&priv->udev->dev));
7735 led->name = priv->led_name;
7736 led->max_brightness = RTL8XXXU_HW_LED_CONTROL;
7737
7738 if (led_classdev_register(&priv->udev->dev, led))
7739 return;
7740
7741 priv->led_registered = true;
7742
7743 led->brightness = led->max_brightness;
7744 priv->fops->led_classdev_brightness_set(led, led->brightness);
7745 }
7746
rtl8xxxu_deinit_led(struct rtl8xxxu_priv * priv)7747 static void rtl8xxxu_deinit_led(struct rtl8xxxu_priv *priv)
7748 {
7749 struct led_classdev *led = &priv->led_cdev;
7750
7751 if (!priv->led_registered)
7752 return;
7753
7754 priv->fops->led_classdev_brightness_set(led, LED_OFF);
7755 led_classdev_unregister(led);
7756 }
7757
7758 static const struct ieee80211_iface_limit rtl8xxxu_limits[] = {
7759 { .max = 2, .types = BIT(NL80211_IFTYPE_STATION), },
7760 { .max = 1, .types = BIT(NL80211_IFTYPE_AP), },
7761 };
7762
7763 static const struct ieee80211_iface_combination rtl8xxxu_combinations[] = {
7764 {
7765 .limits = rtl8xxxu_limits,
7766 .n_limits = ARRAY_SIZE(rtl8xxxu_limits),
7767 .max_interfaces = 2,
7768 .num_different_channels = 1,
7769 },
7770 };
7771
rtl8xxxu_probe(struct usb_interface * interface,const struct usb_device_id * id)7772 static int rtl8xxxu_probe(struct usb_interface *interface,
7773 const struct usb_device_id *id)
7774 {
7775 struct rtl8xxxu_priv *priv;
7776 struct ieee80211_hw *hw;
7777 struct usb_device *udev;
7778 struct ieee80211_supported_band *sband;
7779 int ret;
7780 int untested = 1;
7781
7782 udev = usb_get_dev(interface_to_usbdev(interface));
7783
7784 switch (id->idVendor) {
7785 case USB_VENDOR_ID_REALTEK:
7786 switch(id->idProduct) {
7787 case 0x1724:
7788 case 0x8176:
7789 case 0x8178:
7790 case 0x817f:
7791 case 0x818b:
7792 case 0xf179:
7793 case 0x8179:
7794 case 0xb711:
7795 case 0xf192:
7796 case 0x2005:
7797 untested = 0;
7798 break;
7799 }
7800 break;
7801 case 0x7392:
7802 if (id->idProduct == 0x7811 || id->idProduct == 0xa611 || id->idProduct == 0xb811)
7803 untested = 0;
7804 break;
7805 case 0x050d:
7806 if (id->idProduct == 0x1004)
7807 untested = 0;
7808 break;
7809 case 0x20f4:
7810 if (id->idProduct == 0x648b)
7811 untested = 0;
7812 break;
7813 case 0x2001:
7814 if (id->idProduct == 0x3308)
7815 untested = 0;
7816 break;
7817 case 0x2357:
7818 if (id->idProduct == 0x0109 || id->idProduct == 0x0135)
7819 untested = 0;
7820 break;
7821 case 0x0b05:
7822 if (id->idProduct == 0x18f1)
7823 untested = 0;
7824 break;
7825 default:
7826 break;
7827 }
7828
7829 if (untested) {
7830 rtl8xxxu_debug |= RTL8XXXU_DEBUG_EFUSE;
7831 dev_info(&udev->dev,
7832 "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n",
7833 id->idVendor, id->idProduct);
7834 dev_info(&udev->dev,
7835 "Please report results to Jes.Sorensen@gmail.com\n");
7836 }
7837
7838 hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops);
7839 if (!hw) {
7840 ret = -ENOMEM;
7841 goto err_put_dev;
7842 }
7843
7844 priv = hw->priv;
7845 priv->hw = hw;
7846 priv->udev = udev;
7847 priv->fops = (struct rtl8xxxu_fileops *)id->driver_info;
7848 mutex_init(&priv->usb_buf_mutex);
7849 mutex_init(&priv->syson_indirect_access_mutex);
7850 mutex_init(&priv->h2c_mutex);
7851 mutex_init(&priv->sta_mutex);
7852 INIT_LIST_HEAD(&priv->tx_urb_free_list);
7853 spin_lock_init(&priv->tx_urb_lock);
7854 INIT_LIST_HEAD(&priv->rx_urb_pending_list);
7855 spin_lock_init(&priv->rx_urb_lock);
7856 INIT_WORK(&priv->rx_urb_wq, rtl8xxxu_rx_urb_work);
7857 INIT_DELAYED_WORK(&priv->ra_watchdog, rtl8xxxu_watchdog_callback);
7858 INIT_DELAYED_WORK(&priv->update_beacon_work, rtl8xxxu_update_beacon_work_callback);
7859 skb_queue_head_init(&priv->c2hcmd_queue);
7860
7861 usb_set_intfdata(interface, hw);
7862
7863 ret = rtl8xxxu_parse_usb(priv, interface);
7864 if (ret)
7865 goto err_set_intfdata;
7866
7867 ret = priv->fops->identify_chip(priv);
7868 if (ret) {
7869 dev_err(&udev->dev, "Fatal - failed to identify chip\n");
7870 goto err_set_intfdata;
7871 }
7872
7873 hw->wiphy->available_antennas_tx = BIT(priv->tx_paths) - 1;
7874 hw->wiphy->available_antennas_rx = BIT(priv->rx_paths) - 1;
7875
7876 if (priv->rtl_chip == RTL8188E)
7877 INIT_WORK(&priv->c2hcmd_work, rtl8188e_c2hcmd_callback);
7878 else
7879 INIT_WORK(&priv->c2hcmd_work, rtl8xxxu_c2hcmd_callback);
7880
7881 ret = priv->fops->read_efuse(priv);
7882 if (ret) {
7883 dev_err(&udev->dev, "Fatal - failed to read EFuse\n");
7884 goto err_set_intfdata;
7885 }
7886
7887 ret = priv->fops->parse_efuse(priv);
7888 if (ret) {
7889 dev_err(&udev->dev, "Fatal - failed to parse EFuse\n");
7890 goto err_set_intfdata;
7891 }
7892
7893 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE)
7894 rtl8xxxu_dump_efuse(priv);
7895
7896 rtl8xxxu_print_chipinfo(priv);
7897
7898 ret = priv->fops->load_firmware(priv);
7899 if (ret) {
7900 dev_err(&udev->dev, "Fatal - failed to load firmware\n");
7901 goto err_set_intfdata;
7902 }
7903
7904 ret = rtl8xxxu_init_device(hw);
7905 if (ret)
7906 goto err_set_intfdata;
7907
7908 hw->vif_data_size = sizeof(struct rtl8xxxu_vif);
7909
7910 hw->wiphy->max_scan_ssids = 1;
7911 hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
7912 if (priv->fops->max_macid_num)
7913 hw->wiphy->max_ap_assoc_sta = priv->fops->max_macid_num - 1;
7914 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
7915 if (priv->fops->supports_ap)
7916 hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_AP);
7917 hw->queues = 4;
7918
7919 hw->wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH;
7920
7921 if (priv->fops->supports_concurrent) {
7922 hw->wiphy->iface_combinations = rtl8xxxu_combinations;
7923 hw->wiphy->n_iface_combinations = ARRAY_SIZE(rtl8xxxu_combinations);
7924 }
7925
7926 sband = &rtl8xxxu_supported_band;
7927 sband->ht_cap.ht_supported = true;
7928 sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
7929 sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
7930 sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40;
7931 memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs));
7932 sband->ht_cap.mcs.rx_mask[0] = 0xff;
7933 sband->ht_cap.mcs.rx_mask[4] = 0x01;
7934 if (priv->rf_paths > 1) {
7935 sband->ht_cap.mcs.rx_mask[1] = 0xff;
7936 sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
7937 }
7938 sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
7939 /*
7940 * Some APs will negotiate HT20_40 in a noisy environment leading
7941 * to miserable performance. Rather than defaulting to this, only
7942 * enable it if explicitly requested at module load time.
7943 */
7944 if (rtl8xxxu_ht40_2g) {
7945 dev_info(&udev->dev, "Enabling HT_20_40 on the 2.4GHz band\n");
7946 sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
7947 }
7948 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband;
7949
7950 hw->wiphy->rts_threshold = 2347;
7951
7952 SET_IEEE80211_DEV(priv->hw, &interface->dev);
7953 SET_IEEE80211_PERM_ADDR(hw, priv->mac_addr);
7954
7955 hw->extra_tx_headroom = priv->fops->tx_desc_size;
7956 ieee80211_hw_set(hw, SIGNAL_DBM);
7957
7958 /*
7959 * The firmware handles rate control, except for RTL8188EU,
7960 * where we handle the rate control in the driver.
7961 */
7962 ieee80211_hw_set(hw, HAS_RATE_CONTROL);
7963 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT);
7964 ieee80211_hw_set(hw, AMPDU_AGGREGATION);
7965 ieee80211_hw_set(hw, MFP_CAPABLE);
7966
7967 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST);
7968
7969 ret = ieee80211_register_hw(priv->hw);
7970 if (ret) {
7971 dev_err(&udev->dev, "%s: Failed to register: %i\n",
7972 __func__, ret);
7973 goto err_set_intfdata;
7974 }
7975
7976 rtl8xxxu_init_led(priv);
7977
7978 return 0;
7979
7980 err_set_intfdata:
7981 usb_set_intfdata(interface, NULL);
7982
7983 kfree(priv->fw_data);
7984 mutex_destroy(&priv->usb_buf_mutex);
7985 mutex_destroy(&priv->syson_indirect_access_mutex);
7986 mutex_destroy(&priv->h2c_mutex);
7987
7988 ieee80211_free_hw(hw);
7989 err_put_dev:
7990 usb_put_dev(udev);
7991
7992 return ret;
7993 }
7994
rtl8xxxu_disconnect(struct usb_interface * interface)7995 static void rtl8xxxu_disconnect(struct usb_interface *interface)
7996 {
7997 struct rtl8xxxu_priv *priv;
7998 struct ieee80211_hw *hw;
7999
8000 hw = usb_get_intfdata(interface);
8001 priv = hw->priv;
8002
8003 rtl8xxxu_deinit_led(priv);
8004
8005 ieee80211_unregister_hw(hw);
8006
8007 priv->fops->power_off(priv);
8008
8009 usb_set_intfdata(interface, NULL);
8010
8011 dev_info(&priv->udev->dev, "disconnecting\n");
8012
8013 kfree(priv->fw_data);
8014 mutex_destroy(&priv->usb_buf_mutex);
8015 mutex_destroy(&priv->syson_indirect_access_mutex);
8016 mutex_destroy(&priv->h2c_mutex);
8017
8018 if (priv->udev->state != USB_STATE_NOTATTACHED) {
8019 dev_info(&priv->udev->dev,
8020 "Device still attached, trying to reset\n");
8021 usb_reset_device(priv->udev);
8022 }
8023 usb_put_dev(priv->udev);
8024 ieee80211_free_hw(hw);
8025 }
8026
8027 static const struct usb_device_id dev_table[] = {
8028 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8724, 0xff, 0xff, 0xff),
8029 .driver_info = (unsigned long)&rtl8723au_fops},
8030 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1724, 0xff, 0xff, 0xff),
8031 .driver_info = (unsigned long)&rtl8723au_fops},
8032 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0724, 0xff, 0xff, 0xff),
8033 .driver_info = (unsigned long)&rtl8723au_fops},
8034 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818b, 0xff, 0xff, 0xff),
8035 .driver_info = (unsigned long)&rtl8192eu_fops},
8036 /* TP-Link TL-WN822N v4 */
8037 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0108, 0xff, 0xff, 0xff),
8038 .driver_info = (unsigned long)&rtl8192eu_fops},
8039 /* D-Link DWA-131 rev E1, tested by David Patiño */
8040 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3319, 0xff, 0xff, 0xff),
8041 .driver_info = (unsigned long)&rtl8192eu_fops},
8042 /* Tested by Myckel Habets */
8043 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0109, 0xff, 0xff, 0xff),
8044 .driver_info = (unsigned long)&rtl8192eu_fops},
8045 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb720, 0xff, 0xff, 0xff),
8046 .driver_info = (unsigned long)&rtl8723bu_fops},
8047 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0xa611, 0xff, 0xff, 0xff),
8048 .driver_info = (unsigned long)&rtl8723bu_fops},
8049 /* RTL8188FU */
8050 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xf179, 0xff, 0xff, 0xff),
8051 .driver_info = (unsigned long)&rtl8188fu_fops},
8052 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8179, 0xff, 0xff, 0xff),
8053 .driver_info = (unsigned long)&rtl8188eu_fops},
8054 /* Tested by Hans de Goede - rtl8188etv */
8055 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0179, 0xff, 0xff, 0xff),
8056 .driver_info = (unsigned long)&rtl8188eu_fops},
8057 /* Sitecom rtl8188eus */
8058 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0076, 0xff, 0xff, 0xff),
8059 .driver_info = (unsigned long)&rtl8188eu_fops},
8060 /* D-Link USB-GO-N150 */
8061 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3311, 0xff, 0xff, 0xff),
8062 .driver_info = (unsigned long)&rtl8188eu_fops},
8063 /* D-Link DWA-125 REV D1 */
8064 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330f, 0xff, 0xff, 0xff),
8065 .driver_info = (unsigned long)&rtl8188eu_fops},
8066 /* D-Link DWA-123 REV D1 */
8067 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3310, 0xff, 0xff, 0xff),
8068 .driver_info = (unsigned long)&rtl8188eu_fops},
8069 /* D-Link DWA-121 rev B1 */
8070 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x331b, 0xff, 0xff, 0xff),
8071 .driver_info = (unsigned long)&rtl8188eu_fops},
8072 /* Abocom - Abocom */
8073 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8179, 0xff, 0xff, 0xff),
8074 .driver_info = (unsigned long)&rtl8188eu_fops},
8075 /* Elecom WDC-150SU2M */
8076 {USB_DEVICE_AND_INTERFACE_INFO(0x056e, 0x4008, 0xff, 0xff, 0xff),
8077 .driver_info = (unsigned long)&rtl8188eu_fops},
8078 /* TP-Link TL-WN722N v2 */
8079 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x010c, 0xff, 0xff, 0xff),
8080 .driver_info = (unsigned long)&rtl8188eu_fops},
8081 /* TP-Link TL-WN727N v5.21 */
8082 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0111, 0xff, 0xff, 0xff),
8083 .driver_info = (unsigned long)&rtl8188eu_fops},
8084 /* MERCUSYS MW150US v2 */
8085 {USB_DEVICE_AND_INTERFACE_INFO(0x2c4e, 0x0102, 0xff, 0xff, 0xff),
8086 .driver_info = (unsigned long)&rtl8188eu_fops},
8087 /* ASUS USB-N10 Nano B1 */
8088 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x18f0, 0xff, 0xff, 0xff),
8089 .driver_info = (unsigned long)&rtl8188eu_fops},
8090 /* Edimax EW-7811Un V2 */
8091 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0xb811, 0xff, 0xff, 0xff),
8092 .driver_info = (unsigned long)&rtl8188eu_fops},
8093 /* Rosewill USB-N150 Nano */
8094 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xffef, 0xff, 0xff, 0xff),
8095 .driver_info = (unsigned long)&rtl8188eu_fops},
8096 /* RTL8710BU aka RTL8188GU (not to be confused with RTL8188GTVU) */
8097 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb711, 0xff, 0xff, 0xff),
8098 .driver_info = (unsigned long)&rtl8710bu_fops},
8099 /* TOTOLINK N150UA V5 / N150UA-B */
8100 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2005, 0xff, 0xff, 0xff),
8101 .driver_info = (unsigned long)&rtl8710bu_fops},
8102 /* Comfast CF-826F */
8103 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xf192, 0xff, 0xff, 0xff),
8104 .driver_info = (unsigned long)&rtl8192fu_fops},
8105 /* Asus USB-N13 rev C1 */
8106 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x18f1, 0xff, 0xff, 0xff),
8107 .driver_info = (unsigned long)&rtl8192fu_fops},
8108 /* EDIMAX EW-7722UTn V3 */
8109 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0xb722, 0xff, 0xff, 0xff),
8110 .driver_info = (unsigned long)&rtl8192fu_fops},
8111 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x318b, 0xff, 0xff, 0xff),
8112 .driver_info = (unsigned long)&rtl8192fu_fops},
8113 /* TP-Link TL-WN823N V2 */
8114 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0135, 0xff, 0xff, 0xff),
8115 .driver_info = (unsigned long)&rtl8192fu_fops},
8116 #ifdef CONFIG_RTL8XXXU_UNTESTED
8117 /* Still supported by rtlwifi */
8118 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff),
8119 .driver_info = (unsigned long)&rtl8192cu_fops},
8120 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8178, 0xff, 0xff, 0xff),
8121 .driver_info = (unsigned long)&rtl8192cu_fops},
8122 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817f, 0xff, 0xff, 0xff),
8123 .driver_info = (unsigned long)&rtl8192cu_fops},
8124 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x819a, 0xff, 0xff, 0xff),
8125 .driver_info = (unsigned long)&rtl8192cu_fops},
8126 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8754, 0xff, 0xff, 0xff),
8127 .driver_info = (unsigned long)&rtl8192cu_fops},
8128 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817c, 0xff, 0xff, 0xff),
8129 .driver_info = (unsigned long)&rtl8192cu_fops},
8130 /* Tested by Larry Finger */
8131 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff),
8132 .driver_info = (unsigned long)&rtl8192cu_fops},
8133 /* Tested by Andrea Merello */
8134 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff),
8135 .driver_info = (unsigned long)&rtl8192cu_fops},
8136 /* Tested by Jocelyn Mayer */
8137 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff),
8138 .driver_info = (unsigned long)&rtl8192cu_fops},
8139 /* Tested by Stefano Bravi */
8140 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff),
8141 .driver_info = (unsigned long)&rtl8192cu_fops},
8142 /* Currently untested 8188 series devices */
8143 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x018a, 0xff, 0xff, 0xff),
8144 .driver_info = (unsigned long)&rtl8192cu_fops},
8145 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8191, 0xff, 0xff, 0xff),
8146 .driver_info = (unsigned long)&rtl8192cu_fops},
8147 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8170, 0xff, 0xff, 0xff),
8148 .driver_info = (unsigned long)&rtl8192cu_fops},
8149 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8177, 0xff, 0xff, 0xff),
8150 .driver_info = (unsigned long)&rtl8192cu_fops},
8151 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817a, 0xff, 0xff, 0xff),
8152 .driver_info = (unsigned long)&rtl8192cu_fops},
8153 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817b, 0xff, 0xff, 0xff),
8154 .driver_info = (unsigned long)&rtl8192cu_fops},
8155 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817d, 0xff, 0xff, 0xff),
8156 .driver_info = (unsigned long)&rtl8192cu_fops},
8157 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817e, 0xff, 0xff, 0xff),
8158 .driver_info = (unsigned long)&rtl8192cu_fops},
8159 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8186, 0xff, 0xff, 0xff),
8160 .driver_info = (unsigned long)&rtl8192cu_fops},
8161 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818a, 0xff, 0xff, 0xff),
8162 .driver_info = (unsigned long)&rtl8192cu_fops},
8163 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff),
8164 .driver_info = (unsigned long)&rtl8192cu_fops},
8165 {USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff),
8166 .driver_info = (unsigned long)&rtl8192cu_fops},
8167 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff),
8168 .driver_info = (unsigned long)&rtl8192cu_fops},
8169 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff),
8170 .driver_info = (unsigned long)&rtl8192cu_fops},
8171 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x11f2, 0xff, 0xff, 0xff),
8172 .driver_info = (unsigned long)&rtl8192cu_fops},
8173 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff),
8174 .driver_info = (unsigned long)&rtl8192cu_fops},
8175 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8188, 0xff, 0xff, 0xff),
8176 .driver_info = (unsigned long)&rtl8192cu_fops},
8177 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff),
8178 .driver_info = (unsigned long)&rtl8192cu_fops},
8179 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff),
8180 .driver_info = (unsigned long)&rtl8192cu_fops},
8181 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9043, 0xff, 0xff, 0xff),
8182 .driver_info = (unsigned long)&rtl8192cu_fops},
8183 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff),
8184 .driver_info = (unsigned long)&rtl8192cu_fops},
8185 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1e1e, 0xff, 0xff, 0xff),
8186 .driver_info = (unsigned long)&rtl8192cu_fops},
8187 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x5088, 0xff, 0xff, 0xff),
8188 .driver_info = (unsigned long)&rtl8192cu_fops},
8189 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff),
8190 .driver_info = (unsigned long)&rtl8192cu_fops},
8191 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff),
8192 .driver_info = (unsigned long)&rtl8192cu_fops},
8193 {USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff),
8194 .driver_info = (unsigned long)&rtl8192cu_fops},
8195 {USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff),
8196 .driver_info = (unsigned long)&rtl8192cu_fops},
8197 {USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff),
8198 .driver_info = (unsigned long)&rtl8192cu_fops},
8199 {USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3358, 0xff, 0xff, 0xff),
8200 .driver_info = (unsigned long)&rtl8192cu_fops},
8201 {USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3359, 0xff, 0xff, 0xff),
8202 .driver_info = (unsigned long)&rtl8192cu_fops},
8203 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff),
8204 .driver_info = (unsigned long)&rtl8192cu_fops},
8205 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff),
8206 .driver_info = (unsigned long)&rtl8192cu_fops},
8207 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff),
8208 .driver_info = (unsigned long)&rtl8192cu_fops},
8209 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff),
8210 .driver_info = (unsigned long)&rtl8192cu_fops},
8211 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff),
8212 .driver_info = (unsigned long)&rtl8192cu_fops},
8213 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff),
8214 .driver_info = (unsigned long)&rtl8192cu_fops},
8215 {USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff),
8216 .driver_info = (unsigned long)&rtl8192cu_fops},
8217 {USB_DEVICE_AND_INTERFACE_INFO(0x9846, 0x9041, 0xff, 0xff, 0xff),
8218 .driver_info = (unsigned long)&rtl8192cu_fops},
8219 {USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff),
8220 .driver_info = (unsigned long)&rtl8192cu_fops},
8221 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff),
8222 .driver_info = (unsigned long)&rtl8192cu_fops},
8223 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff),
8224 .driver_info = (unsigned long)&rtl8192cu_fops},
8225 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff),
8226 .driver_info = (unsigned long)&rtl8192cu_fops},
8227 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff),
8228 .driver_info = (unsigned long)&rtl8192cu_fops},
8229 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff),
8230 .driver_info = (unsigned long)&rtl8192cu_fops},
8231 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff),
8232 .driver_info = (unsigned long)&rtl8192cu_fops},
8233 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff),
8234 .driver_info = (unsigned long)&rtl8192cu_fops},
8235 /* Currently untested 8192 series devices */
8236 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff),
8237 .driver_info = (unsigned long)&rtl8192cu_fops},
8238 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff),
8239 .driver_info = (unsigned long)&rtl8192cu_fops},
8240 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff),
8241 .driver_info = (unsigned long)&rtl8192cu_fops},
8242 {USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff),
8243 .driver_info = (unsigned long)&rtl8192cu_fops},
8244 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff),
8245 .driver_info = (unsigned long)&rtl8192cu_fops},
8246 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff),
8247 .driver_info = (unsigned long)&rtl8192cu_fops},
8248 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff),
8249 .driver_info = (unsigned long)&rtl8192cu_fops},
8250 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff),
8251 .driver_info = (unsigned long)&rtl8192cu_fops},
8252 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff),
8253 .driver_info = (unsigned long)&rtl8192cu_fops},
8254 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0077, 0xff, 0xff, 0xff),
8255 .driver_info = (unsigned long)&rtl8192cu_fops},
8256 {USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff),
8257 .driver_info = (unsigned long)&rtl8192cu_fops},
8258 {USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff),
8259 .driver_info = (unsigned long)&rtl8192cu_fops},
8260 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff),
8261 .driver_info = (unsigned long)&rtl8192cu_fops},
8262 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff),
8263 .driver_info = (unsigned long)&rtl8192cu_fops},
8264 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff),
8265 .driver_info = (unsigned long)&rtl8192cu_fops},
8266 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2e2e, 0xff, 0xff, 0xff),
8267 .driver_info = (unsigned long)&rtl8192cu_fops},
8268 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff),
8269 .driver_info = (unsigned long)&rtl8192cu_fops},
8270 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff),
8271 .driver_info = (unsigned long)&rtl8192cu_fops},
8272 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff),
8273 .driver_info = (unsigned long)&rtl8192cu_fops},
8274 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff),
8275 .driver_info = (unsigned long)&rtl8192cu_fops},
8276 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff),
8277 .driver_info = (unsigned long)&rtl8192cu_fops},
8278 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330d, 0xff, 0xff, 0xff),
8279 .driver_info = (unsigned long)&rtl8192cu_fops},
8280 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff),
8281 .driver_info = (unsigned long)&rtl8192cu_fops},
8282 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff),
8283 .driver_info = (unsigned long)&rtl8192cu_fops},
8284 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff),
8285 .driver_info = (unsigned long)&rtl8192cu_fops},
8286 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff),
8287 .driver_info = (unsigned long)&rtl8192cu_fops},
8288 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff),
8289 .driver_info = (unsigned long)&rtl8192cu_fops},
8290 /* found in rtl8192eu vendor driver */
8291 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0107, 0xff, 0xff, 0xff),
8292 .driver_info = (unsigned long)&rtl8192eu_fops},
8293 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab33, 0xff, 0xff, 0xff),
8294 .driver_info = (unsigned long)&rtl8192eu_fops},
8295 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818c, 0xff, 0xff, 0xff),
8296 .driver_info = (unsigned long)&rtl8192eu_fops},
8297 /* D-Link DWA-131 rev C1 */
8298 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3312, 0xff, 0xff, 0xff),
8299 .driver_info = (unsigned long)&rtl8192eu_fops},
8300 /* TP-Link TL-WN8200ND V2 */
8301 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0126, 0xff, 0xff, 0xff),
8302 .driver_info = (unsigned long)&rtl8192eu_fops},
8303 /* Mercusys MW300UM */
8304 {USB_DEVICE_AND_INTERFACE_INFO(0x2c4e, 0x0100, 0xff, 0xff, 0xff),
8305 .driver_info = (unsigned long)&rtl8192eu_fops},
8306 /* Mercusys MW300UH */
8307 {USB_DEVICE_AND_INTERFACE_INFO(0x2c4e, 0x0104, 0xff, 0xff, 0xff),
8308 .driver_info = (unsigned long)&rtl8192eu_fops},
8309 #endif
8310 { }
8311 };
8312
8313 static struct usb_driver rtl8xxxu_driver = {
8314 .name = DRIVER_NAME,
8315 .probe = rtl8xxxu_probe,
8316 .disconnect = rtl8xxxu_disconnect,
8317 .id_table = dev_table,
8318 .no_dynamic_id = 1,
8319 .disable_hub_initiated_lpm = 1,
8320 };
8321
8322 MODULE_DEVICE_TABLE(usb, dev_table);
8323
8324 module_usb_driver(rtl8xxxu_driver);
8325