1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * RTL8XXXU mac80211 USB driver - 8723a specific subdriver
4 *
5 * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com>
6 *
7 * Portions, notably calibration code:
8 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
9 *
10 * This driver was written as a replacement for the vendor provided
11 * rtl8723au driver. As the Realtek 8xxx chips are very similar in
12 * their programming interface, I have started adding support for
13 * additional 8xxx chips like the 8192cu, 8188cus, etc.
14 */
15
16 #include "regs.h"
17 #include "rtl8xxxu.h"
18
19 static struct rtl8xxxu_power_base rtl8723a_power_base = {
20 .reg_0e00 = 0x0a0c0c0c,
21 .reg_0e04 = 0x02040608,
22 .reg_0e08 = 0x00000000,
23 .reg_086c = 0x00000000,
24
25 .reg_0e10 = 0x0a0c0d0e,
26 .reg_0e14 = 0x02040608,
27 .reg_0e18 = 0x0a0c0d0e,
28 .reg_0e1c = 0x02040608,
29
30 .reg_0830 = 0x0a0c0c0c,
31 .reg_0834 = 0x02040608,
32 .reg_0838 = 0x00000000,
33 .reg_086c_2 = 0x00000000,
34
35 .reg_083c = 0x0a0c0d0e,
36 .reg_0848 = 0x02040608,
37 .reg_084c = 0x0a0c0d0e,
38 .reg_0868 = 0x02040608,
39 };
40
41 static const struct rtl8xxxu_reg8val rtl8723au_mac_init_table[] = {
42 {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00},
43 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
44 {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00},
45 {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05},
46 {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01},
47 {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f},
48 {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72},
49 {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08},
50 {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
51 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
52 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
53 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
54 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
55 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
56 {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16},
57 {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00},
58 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02},
59 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
60 {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
61 {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
62 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
63 {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff},
64 };
65
66 static const struct rtl8xxxu_rfregval rtl8723au_radioa_1t_init_table[] = {
67 {0x00, 0x00030159}, {0x01, 0x00031284},
68 {0x02, 0x00098000}, {0x03, 0x00039c63},
69 {0x04, 0x000210e7}, {0x09, 0x0002044f},
70 {0x0a, 0x0001a3f1}, {0x0b, 0x00014787},
71 {0x0c, 0x000896fe}, {0x0d, 0x0000e02c},
72 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
73 {0x19, 0x00000000}, {0x1a, 0x00030355},
74 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
75 {0x1d, 0x000a1250}, {0x1e, 0x0000024f},
76 {0x1f, 0x00000000}, {0x20, 0x0000b614},
77 {0x21, 0x0006c000}, {0x22, 0x00000000},
78 {0x23, 0x00001558}, {0x24, 0x00000060},
79 {0x25, 0x00000483}, {0x26, 0x0004f000},
80 {0x27, 0x000ec7d9}, {0x28, 0x00057730},
81 {0x29, 0x00004783}, {0x2a, 0x00000001},
82 {0x2b, 0x00021334}, {0x2a, 0x00000000},
83 {0x2b, 0x00000054}, {0x2a, 0x00000001},
84 {0x2b, 0x00000808}, {0x2b, 0x00053333},
85 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
86 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
87 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
88 {0x2b, 0x00000808}, {0x2b, 0x00063333},
89 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
90 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
91 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
92 {0x2b, 0x00000808}, {0x2b, 0x00073333},
93 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
94 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
95 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
96 {0x2b, 0x00000709}, {0x2b, 0x00063333},
97 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
98 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
99 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
100 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
101 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
102 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
103 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
104 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
105 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
106 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
107 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
108 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
109 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
110 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
111 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
112 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
113 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
114 {0x10, 0x0002000f}, {0x11, 0x000203f9},
115 {0x10, 0x0003000f}, {0x11, 0x000ff500},
116 {0x10, 0x00000000}, {0x11, 0x00000000},
117 {0x10, 0x0008000f}, {0x11, 0x0003f100},
118 {0x10, 0x0009000f}, {0x11, 0x00023100},
119 {0x12, 0x00032000}, {0x12, 0x00071000},
120 {0x12, 0x000b0000}, {0x12, 0x000fc000},
121 {0x13, 0x000287b3}, {0x13, 0x000244b7},
122 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
123 {0x13, 0x00018493}, {0x13, 0x0001429b},
124 {0x13, 0x00010299}, {0x13, 0x0000c29c},
125 {0x13, 0x000081a0}, {0x13, 0x000040ac},
126 {0x13, 0x00000020}, {0x14, 0x0001944c},
127 {0x14, 0x00059444}, {0x14, 0x0009944c},
128 {0x14, 0x000d9444}, {0x15, 0x0000f474},
129 {0x15, 0x0004f477}, {0x15, 0x0008f455},
130 {0x15, 0x000cf455}, {0x16, 0x00000339},
131 {0x16, 0x00040339}, {0x16, 0x00080339},
132 {0x16, 0x000c0366}, {0x00, 0x00010159},
133 {0x18, 0x0000f401}, {0xfe, 0x00000000},
134 {0xfe, 0x00000000}, {0x1f, 0x00000003},
135 {0xfe, 0x00000000}, {0xfe, 0x00000000},
136 {0x1e, 0x00000247}, {0x1f, 0x00000000},
137 {0x00, 0x00030159},
138 {0xff, 0xffffffff}
139 };
140
rtl8723au_identify_chip(struct rtl8xxxu_priv * priv)141 static int rtl8723au_identify_chip(struct rtl8xxxu_priv *priv)
142 {
143 struct device *dev = &priv->udev->dev;
144 u32 val32, sys_cfg, vendor;
145 int ret = 0;
146
147 sys_cfg = rtl8xxxu_read32(priv, REG_SYS_CFG);
148 priv->chip_cut = u32_get_bits(sys_cfg, SYS_CFG_CHIP_VERSION_MASK);
149 if (sys_cfg & SYS_CFG_TRP_VAUX_EN) {
150 dev_info(dev, "Unsupported test chip\n");
151 ret = -ENOTSUPP;
152 goto out;
153 }
154
155 strscpy(priv->chip_name, "8723AU", sizeof(priv->chip_name));
156 priv->usb_interrupts = 1;
157 priv->rtl_chip = RTL8723A;
158
159 priv->rf_paths = 1;
160 priv->rx_paths = 1;
161 priv->tx_paths = 1;
162
163 val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL);
164 if (val32 & MULTI_WIFI_FUNC_EN)
165 priv->has_wifi = 1;
166 if (val32 & MULTI_BT_FUNC_EN)
167 priv->has_bluetooth = 1;
168 if (val32 & MULTI_GPS_FUNC_EN)
169 priv->has_gps = 1;
170 priv->is_multi_func = 1;
171
172 vendor = sys_cfg & SYS_CFG_VENDOR_ID;
173 rtl8xxxu_identify_vendor_1bit(priv, vendor);
174
175 val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS);
176 priv->rom_rev = u32_get_bits(val32, GPIO_RF_RL_ID);
177
178 rtl8xxxu_config_endpoints_sie(priv);
179
180 /*
181 * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX
182 */
183 if (!priv->ep_tx_count)
184 ret = rtl8xxxu_config_endpoints_no_sie(priv);
185
186 out:
187 return ret;
188 }
189
rtl8723au_parse_efuse(struct rtl8xxxu_priv * priv)190 static int rtl8723au_parse_efuse(struct rtl8xxxu_priv *priv)
191 {
192 struct rtl8723au_efuse *efuse = &priv->efuse_wifi.efuse8723;
193
194 if (efuse->rtl_id != cpu_to_le16(0x8129))
195 return -EINVAL;
196
197 ether_addr_copy(priv->mac_addr, efuse->mac_addr);
198
199 memcpy(priv->cck_tx_power_index_A,
200 efuse->cck_tx_power_index_A,
201 sizeof(efuse->cck_tx_power_index_A));
202 memcpy(priv->cck_tx_power_index_B,
203 efuse->cck_tx_power_index_B,
204 sizeof(efuse->cck_tx_power_index_B));
205
206 memcpy(priv->ht40_1s_tx_power_index_A,
207 efuse->ht40_1s_tx_power_index_A,
208 sizeof(efuse->ht40_1s_tx_power_index_A));
209 memcpy(priv->ht40_1s_tx_power_index_B,
210 efuse->ht40_1s_tx_power_index_B,
211 sizeof(efuse->ht40_1s_tx_power_index_B));
212
213 memcpy(priv->ht20_tx_power_index_diff,
214 efuse->ht20_tx_power_index_diff,
215 sizeof(efuse->ht20_tx_power_index_diff));
216 memcpy(priv->ofdm_tx_power_index_diff,
217 efuse->ofdm_tx_power_index_diff,
218 sizeof(efuse->ofdm_tx_power_index_diff));
219
220 memcpy(priv->ht40_max_power_offset,
221 efuse->ht40_max_power_offset,
222 sizeof(efuse->ht40_max_power_offset));
223 memcpy(priv->ht20_max_power_offset,
224 efuse->ht20_max_power_offset,
225 sizeof(efuse->ht20_max_power_offset));
226
227 if (priv->efuse_wifi.efuse8723.version >= 0x01)
228 priv->default_crystal_cap = priv->efuse_wifi.efuse8723.xtal_k & 0x3f;
229 else
230 priv->fops->set_crystal_cap = NULL;
231
232 priv->power_base = &rtl8723a_power_base;
233
234 return 0;
235 }
236
rtl8723au_load_firmware(struct rtl8xxxu_priv * priv)237 static int rtl8723au_load_firmware(struct rtl8xxxu_priv *priv)
238 {
239 const char *fw_name;
240 int ret;
241
242 switch (priv->chip_cut) {
243 case 0:
244 fw_name = "rtlwifi/rtl8723aufw_A.bin";
245 break;
246 case 1:
247 if (priv->enable_bluetooth)
248 fw_name = "rtlwifi/rtl8723aufw_B.bin";
249 else
250 fw_name = "rtlwifi/rtl8723aufw_B_NoBT.bin";
251
252 break;
253 default:
254 return -EINVAL;
255 }
256
257 ret = rtl8xxxu_load_firmware(priv, fw_name);
258 return ret;
259 }
260
rtl8723au_init_phy_rf(struct rtl8xxxu_priv * priv)261 static int rtl8723au_init_phy_rf(struct rtl8xxxu_priv *priv)
262 {
263 int ret;
264
265 ret = rtl8xxxu_init_phy_rf(priv, rtl8723au_radioa_1t_init_table, RF_A);
266
267 /* Reduce 80M spur */
268 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x0381808d);
269 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
270 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff82);
271 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
272
273 return ret;
274 }
275
rtl8723a_emu_to_active(struct rtl8xxxu_priv * priv)276 static int rtl8723a_emu_to_active(struct rtl8xxxu_priv *priv)
277 {
278 u8 val8;
279 u32 val32;
280 int count, ret = 0;
281
282 /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface*/
283 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
284 val8 |= LDOA15_ENABLE;
285 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
286
287 /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
288 val8 = rtl8xxxu_read8(priv, 0x0067);
289 val8 &= ~BIT(4);
290 rtl8xxxu_write8(priv, 0x0067, val8);
291
292 mdelay(1);
293
294 /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
295 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
296 val8 &= ~SYS_ISO_ANALOG_IPS;
297 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
298
299 /* disable SW LPS 0x04[10]= 0 */
300 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
301 val8 &= ~BIT(2);
302 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
303
304 /* wait till 0x04[17] = 1 power ready*/
305 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
306 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
307 if (val32 & BIT(17))
308 break;
309
310 udelay(10);
311 }
312
313 if (!count) {
314 ret = -EBUSY;
315 goto exit;
316 }
317
318 /* We should be able to optimize the following three entries into one */
319
320 /* release WLON reset 0x04[16]= 1*/
321 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
322 val8 |= BIT(0);
323 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
324
325 /* disable HWPDN 0x04[15]= 0*/
326 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
327 val8 &= ~BIT(7);
328 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
329
330 /* disable WL suspend*/
331 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
332 val8 &= ~(BIT(3) | BIT(4));
333 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
334
335 /* set, then poll until 0 */
336 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
337 val32 |= APS_FSMCO_MAC_ENABLE;
338 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
339
340 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
341 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
342 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
343 ret = 0;
344 break;
345 }
346 udelay(10);
347 }
348
349 if (!count) {
350 ret = -EBUSY;
351 goto exit;
352 }
353
354 /* 0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */
355 /*
356 * Note: Vendor driver actually clears this bit, despite the
357 * documentation claims it's being set!
358 */
359 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
360 val8 |= LEDCFG2_DPDT_SELECT;
361 val8 &= ~LEDCFG2_DPDT_SELECT;
362 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
363
364 exit:
365 return ret;
366 }
367
rtl8723au_power_on(struct rtl8xxxu_priv * priv)368 static int rtl8723au_power_on(struct rtl8xxxu_priv *priv)
369 {
370 u8 val8;
371 u16 val16;
372 u32 val32;
373 int ret;
374
375 /*
376 * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
377 */
378 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
379
380 rtl8xxxu_disabled_to_emu(priv);
381
382 ret = rtl8723a_emu_to_active(priv);
383 if (ret)
384 goto exit;
385
386 /*
387 * 0x0004[19] = 1, reset 8051
388 */
389 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
390 val8 |= BIT(3);
391 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
392
393 /*
394 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
395 * Set CR bit10 to enable 32k calibration.
396 */
397 val16 = rtl8xxxu_read16(priv, REG_CR);
398 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
399 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
400 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
401 CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
402 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
403 rtl8xxxu_write16(priv, REG_CR, val16);
404
405 /* For EFuse PG */
406 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
407 val32 &= ~(BIT(28) | BIT(29) | BIT(30));
408 val32 |= (0x06 << 28);
409 rtl8xxxu_write32(priv, REG_EFUSE_CTRL, val32);
410 exit:
411 return ret;
412 }
413
414 #define XTAL1 GENMASK(23, 18)
415 #define XTAL0 GENMASK(17, 12)
416
rtl8723a_set_crystal_cap(struct rtl8xxxu_priv * priv,u8 crystal_cap)417 void rtl8723a_set_crystal_cap(struct rtl8xxxu_priv *priv, u8 crystal_cap)
418 {
419 struct rtl8xxxu_cfo_tracking *cfo = &priv->cfo_tracking;
420 u32 val32;
421
422 if (crystal_cap == cfo->crystal_cap)
423 return;
424
425 val32 = rtl8xxxu_read32(priv, REG_MAC_PHY_CTRL);
426
427 dev_dbg(&priv->udev->dev,
428 "%s: Adjusting crystal cap from 0x%x (actually 0x%lx 0x%lx) to 0x%x\n",
429 __func__,
430 cfo->crystal_cap,
431 FIELD_GET(XTAL1, val32),
432 FIELD_GET(XTAL0, val32),
433 crystal_cap);
434
435 val32 &= ~(XTAL1 | XTAL0);
436 val32 |= FIELD_PREP(XTAL1, crystal_cap) |
437 FIELD_PREP(XTAL0, crystal_cap);
438 rtl8xxxu_write32(priv, REG_MAC_PHY_CTRL, val32);
439
440 cfo->crystal_cap = crystal_cap;
441 }
442
rtl8723a_cck_rssi(struct rtl8xxxu_priv * priv,struct rtl8723au_phy_stats * phy_stats)443 s8 rtl8723a_cck_rssi(struct rtl8xxxu_priv *priv, struct rtl8723au_phy_stats *phy_stats)
444 {
445 u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a;
446 s8 rx_pwr_all = 0x00;
447
448 switch (cck_agc_rpt & 0xc0) {
449 case 0xc0:
450 rx_pwr_all = -46 - (cck_agc_rpt & 0x3e);
451 break;
452 case 0x80:
453 rx_pwr_all = -26 - (cck_agc_rpt & 0x3e);
454 break;
455 case 0x40:
456 rx_pwr_all = -12 - (cck_agc_rpt & 0x3e);
457 break;
458 case 0x00:
459 rx_pwr_all = 16 - (cck_agc_rpt & 0x3e);
460 break;
461 }
462
463 return rx_pwr_all;
464 }
465
rtl8723au_led_brightness_set(struct led_classdev * led_cdev,enum led_brightness brightness)466 static int rtl8723au_led_brightness_set(struct led_classdev *led_cdev,
467 enum led_brightness brightness)
468 {
469 struct rtl8xxxu_priv *priv = container_of(led_cdev,
470 struct rtl8xxxu_priv,
471 led_cdev);
472 u8 ledcfg = rtl8xxxu_read8(priv, REG_LEDCFG2);
473
474 if (brightness == LED_OFF) {
475 ledcfg &= ~LEDCFG2_HW_LED_CONTROL;
476 ledcfg |= LEDCFG2_SW_LED_CONTROL | LEDCFG2_SW_LED_DISABLE;
477 } else if (brightness == LED_ON) {
478 ledcfg &= ~(LEDCFG2_HW_LED_CONTROL | LEDCFG2_SW_LED_DISABLE);
479 ledcfg |= LEDCFG2_SW_LED_CONTROL;
480 } else if (brightness == RTL8XXXU_HW_LED_CONTROL) {
481 ledcfg &= ~LEDCFG2_SW_LED_DISABLE;
482 ledcfg |= LEDCFG2_HW_LED_CONTROL | LEDCFG2_HW_LED_ENABLE;
483 }
484
485 rtl8xxxu_write8(priv, REG_LEDCFG2, ledcfg);
486
487 return 0;
488 }
489
490 struct rtl8xxxu_fileops rtl8723au_fops = {
491 .identify_chip = rtl8723au_identify_chip,
492 .parse_efuse = rtl8723au_parse_efuse,
493 .load_firmware = rtl8723au_load_firmware,
494 .power_on = rtl8723au_power_on,
495 .power_off = rtl8xxxu_power_off,
496 .read_efuse = rtl8xxxu_read_efuse,
497 .reset_8051 = rtl8xxxu_reset_8051,
498 .llt_init = rtl8xxxu_init_llt_table,
499 .init_phy_bb = rtl8xxxu_gen1_init_phy_bb,
500 .init_phy_rf = rtl8723au_init_phy_rf,
501 .phy_lc_calibrate = rtl8723a_phy_lc_calibrate,
502 .phy_iq_calibrate = rtl8xxxu_gen1_phy_iq_calibrate,
503 .config_channel = rtl8xxxu_gen1_config_channel,
504 .parse_rx_desc = rtl8xxxu_parse_rxdesc16,
505 .parse_phystats = rtl8723au_rx_parse_phystats,
506 .init_aggregation = rtl8xxxu_gen1_init_aggregation,
507 .enable_rf = rtl8xxxu_gen1_enable_rf,
508 .disable_rf = rtl8xxxu_gen1_disable_rf,
509 .usb_quirks = rtl8xxxu_gen1_usb_quirks,
510 .set_tx_power = rtl8xxxu_gen1_set_tx_power,
511 .update_rate_mask = rtl8xxxu_update_rate_mask,
512 .report_connect = rtl8xxxu_gen1_report_connect,
513 .report_rssi = rtl8xxxu_gen1_report_rssi,
514 .fill_txdesc = rtl8xxxu_fill_txdesc_v1,
515 .set_crystal_cap = rtl8723a_set_crystal_cap,
516 .cck_rssi = rtl8723a_cck_rssi,
517 .led_classdev_brightness_set = rtl8723au_led_brightness_set,
518 .writeN_block_size = 1024,
519 .rx_agg_buf_size = 16000,
520 .tx_desc_size = sizeof(struct rtl8xxxu_txdesc32),
521 .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc16),
522 .max_sec_cam_num = 32,
523 .adda_1t_init = 0x0b1b25a0,
524 .adda_1t_path_on = 0x0bdb25a0,
525 .adda_2t_path_on_a = 0x04db25a4,
526 .adda_2t_path_on_b = 0x0b1b25a4,
527 .trxff_boundary = 0x27ff,
528 .pbp_rx = PBP_PAGE_SIZE_128,
529 .pbp_tx = PBP_PAGE_SIZE_128,
530 .mactable = rtl8723au_mac_init_table,
531 .total_page_num = TX_TOTAL_PAGE_NUM,
532 .page_num_hi = TX_PAGE_NUM_HI_PQ,
533 .page_num_lo = TX_PAGE_NUM_LO_PQ,
534 .page_num_norm = TX_PAGE_NUM_NORM_PQ,
535 };
536