xref: /linux/drivers/net/dsa/realtek/rtl8366rb.c (revision 1e15510b71c99c6e49134d756df91069f7d18141)
1 // SPDX-License-Identifier: GPL-2.0
2 /* Realtek SMI subdriver for the Realtek RTL8366RB ethernet switch
3  *
4  * This is a sparsely documented chip, the only viable documentation seems
5  * to be a patched up code drop from the vendor that appear in various
6  * GPL source trees.
7  *
8  * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
9  * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
10  * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
11  * Copyright (C) 2010 Roman Yeryomin <roman@advem.lv>
12  * Copyright (C) 2011 Colin Leitner <colin.leitner@googlemail.com>
13  */
14 
15 #include <linux/bitops.h>
16 #include <linux/etherdevice.h>
17 #include <linux/if_bridge.h>
18 #include <linux/if_vlan.h>
19 #include <linux/interrupt.h>
20 #include <linux/irqdomain.h>
21 #include <linux/irqchip/chained_irq.h>
22 #include <linux/of_irq.h>
23 #include <linux/regmap.h>
24 #include <linux/string_choices.h>
25 
26 #include "realtek.h"
27 #include "realtek-smi.h"
28 #include "realtek-mdio.h"
29 #include "rtl83xx.h"
30 #include "rtl8366rb.h"
31 
32 /* Switch Global Configuration register */
33 #define RTL8366RB_SGCR				0x0000
34 #define RTL8366RB_SGCR_EN_BC_STORM_CTRL		BIT(0)
35 #define RTL8366RB_SGCR_MAX_LENGTH(a)		((a) << 4)
36 #define RTL8366RB_SGCR_MAX_LENGTH_MASK		RTL8366RB_SGCR_MAX_LENGTH(0x3)
37 #define RTL8366RB_SGCR_MAX_LENGTH_1522		RTL8366RB_SGCR_MAX_LENGTH(0x0)
38 #define RTL8366RB_SGCR_MAX_LENGTH_1536		RTL8366RB_SGCR_MAX_LENGTH(0x1)
39 #define RTL8366RB_SGCR_MAX_LENGTH_1552		RTL8366RB_SGCR_MAX_LENGTH(0x2)
40 #define RTL8366RB_SGCR_MAX_LENGTH_16000		RTL8366RB_SGCR_MAX_LENGTH(0x3)
41 #define RTL8366RB_SGCR_EN_VLAN			BIT(13)
42 #define RTL8366RB_SGCR_EN_VLAN_4KTB		BIT(14)
43 
44 /* Port Enable Control register */
45 #define RTL8366RB_PECR				0x0001
46 
47 /* Switch per-port learning disablement register */
48 #define RTL8366RB_PORT_LEARNDIS_CTRL		0x0002
49 
50 /* Security control, actually aging register */
51 #define RTL8366RB_SECURITY_CTRL			0x0003
52 
53 #define RTL8366RB_SSCR2				0x0004
54 #define RTL8366RB_SSCR2_DROP_UNKNOWN_DA		BIT(0)
55 
56 /* Port Mode Control registers */
57 #define RTL8366RB_PMC0				0x0005
58 #define RTL8366RB_PMC0_SPI			BIT(0)
59 #define RTL8366RB_PMC0_EN_AUTOLOAD		BIT(1)
60 #define RTL8366RB_PMC0_PROBE			BIT(2)
61 #define RTL8366RB_PMC0_DIS_BISR			BIT(3)
62 #define RTL8366RB_PMC0_ADCTEST			BIT(4)
63 #define RTL8366RB_PMC0_SRAM_DIAG		BIT(5)
64 #define RTL8366RB_PMC0_EN_SCAN			BIT(6)
65 #define RTL8366RB_PMC0_P4_IOMODE_SHIFT		7
66 #define RTL8366RB_PMC0_P4_IOMODE_MASK		GENMASK(9, 7)
67 #define RTL8366RB_PMC0_P5_IOMODE_SHIFT		10
68 #define RTL8366RB_PMC0_P5_IOMODE_MASK		GENMASK(12, 10)
69 #define RTL8366RB_PMC0_SDSMODE_SHIFT		13
70 #define RTL8366RB_PMC0_SDSMODE_MASK		GENMASK(15, 13)
71 #define RTL8366RB_PMC1				0x0006
72 
73 /* Port Mirror Control Register */
74 #define RTL8366RB_PMCR				0x0007
75 #define RTL8366RB_PMCR_SOURCE_PORT(a)		(a)
76 #define RTL8366RB_PMCR_SOURCE_PORT_MASK		0x000f
77 #define RTL8366RB_PMCR_MONITOR_PORT(a)		((a) << 4)
78 #define RTL8366RB_PMCR_MONITOR_PORT_MASK	0x00f0
79 #define RTL8366RB_PMCR_MIRROR_RX		BIT(8)
80 #define RTL8366RB_PMCR_MIRROR_TX		BIT(9)
81 #define RTL8366RB_PMCR_MIRROR_SPC		BIT(10)
82 #define RTL8366RB_PMCR_MIRROR_ISO		BIT(11)
83 
84 /* bits 0..7 = port 0, bits 8..15 = port 1 */
85 #define RTL8366RB_PAACR0		0x0010
86 /* bits 0..7 = port 2, bits 8..15 = port 3 */
87 #define RTL8366RB_PAACR1		0x0011
88 /* bits 0..7 = port 4, bits 8..15 = port 5 */
89 #define RTL8366RB_PAACR2		0x0012
90 #define RTL8366RB_PAACR_SPEED_10M	0
91 #define RTL8366RB_PAACR_SPEED_100M	1
92 #define RTL8366RB_PAACR_SPEED_1000M	2
93 #define RTL8366RB_PAACR_FULL_DUPLEX	BIT(2)
94 #define RTL8366RB_PAACR_LINK_UP		BIT(4)
95 #define RTL8366RB_PAACR_TX_PAUSE	BIT(5)
96 #define RTL8366RB_PAACR_RX_PAUSE	BIT(6)
97 #define RTL8366RB_PAACR_AN		BIT(7)
98 
99 /* bits 0..7 = port 0, bits 8..15 = port 1 */
100 #define RTL8366RB_PSTAT0		0x0014
101 /* bits 0..7 = port 2, bits 8..15 = port 3 */
102 #define RTL8366RB_PSTAT1		0x0015
103 /* bits 0..7 = port 4, bits 8..15 = port 5 */
104 #define RTL8366RB_PSTAT2		0x0016
105 
106 #define RTL8366RB_POWER_SAVING_REG	0x0021
107 
108 /* Spanning tree status (STP) control, two bits per port per FID */
109 #define RTL8366RB_STP_STATE_BASE	0x0050 /* 0x0050..0x0057 */
110 #define RTL8366RB_STP_STATE_DISABLED	0x0
111 #define RTL8366RB_STP_STATE_BLOCKING	0x1
112 #define RTL8366RB_STP_STATE_LEARNING	0x2
113 #define RTL8366RB_STP_STATE_FORWARDING	0x3
114 #define RTL8366RB_STP_MASK		GENMASK(1, 0)
115 #define RTL8366RB_STP_STATE(port, state) \
116 	((state) << ((port) * 2))
117 #define RTL8366RB_STP_STATE_MASK(port) \
118 	RTL8366RB_STP_STATE((port), RTL8366RB_STP_MASK)
119 
120 /* CPU port control reg */
121 #define RTL8366RB_CPU_CTRL_REG		0x0061
122 #define RTL8366RB_CPU_PORTS_MSK		0x00FF
123 /* Disables inserting custom tag length/type 0x8899 */
124 #define RTL8366RB_CPU_NO_TAG		BIT(15)
125 #define RTL8366RB_CPU_TAG_SIZE		4
126 
127 #define RTL8366RB_SMAR0			0x0070 /* bits 0..15 */
128 #define RTL8366RB_SMAR1			0x0071 /* bits 16..31 */
129 #define RTL8366RB_SMAR2			0x0072 /* bits 32..47 */
130 
131 #define RTL8366RB_RESET_CTRL_REG		0x0100
132 #define RTL8366RB_CHIP_CTRL_RESET_HW		BIT(0)
133 #define RTL8366RB_CHIP_CTRL_RESET_SW		BIT(1)
134 
135 #define RTL8366RB_CHIP_ID_REG			0x0509
136 #define RTL8366RB_CHIP_ID_8366			0x5937
137 #define RTL8366RB_CHIP_VERSION_CTRL_REG		0x050A
138 #define RTL8366RB_CHIP_VERSION_MASK		0xf
139 
140 /* PHY registers control */
141 #define RTL8366RB_PHY_ACCESS_CTRL_REG		0x8000
142 #define RTL8366RB_PHY_CTRL_READ			BIT(0)
143 #define RTL8366RB_PHY_CTRL_WRITE		0
144 #define RTL8366RB_PHY_ACCESS_BUSY_REG		0x8001
145 #define RTL8366RB_PHY_INT_BUSY			BIT(0)
146 #define RTL8366RB_PHY_EXT_BUSY			BIT(4)
147 #define RTL8366RB_PHY_ACCESS_DATA_REG		0x8002
148 #define RTL8366RB_PHY_EXT_CTRL_REG		0x8010
149 #define RTL8366RB_PHY_EXT_WRDATA_REG		0x8011
150 #define RTL8366RB_PHY_EXT_RDDATA_REG		0x8012
151 
152 #define RTL8366RB_PHY_REG_MASK			0x1f
153 #define RTL8366RB_PHY_PAGE_OFFSET		5
154 #define RTL8366RB_PHY_PAGE_MASK			(0xf << 5)
155 #define RTL8366RB_PHY_NO_OFFSET			9
156 #define RTL8366RB_PHY_NO_MASK			(0x1f << 9)
157 
158 /* VLAN Ingress Control Register 1, one bit per port.
159  * bit 0 .. 5 will make the switch drop ingress frames without
160  * VID such as untagged or priority-tagged frames for respective
161  * port.
162  * bit 6 .. 11 will make the switch drop ingress frames carrying
163  * a C-tag with VID != 0 for respective port.
164  */
165 #define RTL8366RB_VLAN_INGRESS_CTRL1_REG	0x037E
166 #define RTL8366RB_VLAN_INGRESS_CTRL1_DROP(port)	(BIT((port)) | BIT((port) + 6))
167 
168 /* VLAN Ingress Control Register 2, one bit per port.
169  * bit0 .. bit5 will make the switch drop all ingress frames with
170  * a VLAN classification that does not include the port is in its
171  * member set.
172  */
173 #define RTL8366RB_VLAN_INGRESS_CTRL2_REG	0x037f
174 
175 #define RTL8366RB_MIB_COUNT			33
176 #define RTL8366RB_GLOBAL_MIB_COUNT		1
177 #define RTL8366RB_MIB_COUNTER_PORT_OFFSET	0x0050
178 #define RTL8366RB_MIB_COUNTER_BASE		0x1000
179 #define RTL8366RB_MIB_CTRL_REG			0x13F0
180 #define RTL8366RB_MIB_CTRL_USER_MASK		0x0FFC
181 #define RTL8366RB_MIB_CTRL_BUSY_MASK		BIT(0)
182 #define RTL8366RB_MIB_CTRL_RESET_MASK		BIT(1)
183 #define RTL8366RB_MIB_CTRL_PORT_RESET(_p)	BIT(2 + (_p))
184 #define RTL8366RB_MIB_CTRL_GLOBAL_RESET		BIT(11)
185 
186 #define RTL8366RB_PORT_VLAN_CTRL_BASE		0x0063
187 #define RTL8366RB_PORT_VLAN_CTRL_REG(_p)  \
188 		(RTL8366RB_PORT_VLAN_CTRL_BASE + (_p) / 4)
189 #define RTL8366RB_PORT_VLAN_CTRL_MASK		0xf
190 #define RTL8366RB_PORT_VLAN_CTRL_SHIFT(_p)	(4 * ((_p) % 4))
191 
192 #define RTL8366RB_VLAN_TABLE_READ_BASE		0x018C
193 #define RTL8366RB_VLAN_TABLE_WRITE_BASE		0x0185
194 
195 #define RTL8366RB_TABLE_ACCESS_CTRL_REG		0x0180
196 #define RTL8366RB_TABLE_VLAN_READ_CTRL		0x0E01
197 #define RTL8366RB_TABLE_VLAN_WRITE_CTRL		0x0F01
198 
199 #define RTL8366RB_VLAN_MC_BASE(_x)		(0x0020 + (_x) * 3)
200 
201 #define RTL8366RB_PORT_LINK_STATUS_BASE		0x0014
202 #define RTL8366RB_PORT_STATUS_SPEED_MASK	0x0003
203 #define RTL8366RB_PORT_STATUS_DUPLEX_MASK	0x0004
204 #define RTL8366RB_PORT_STATUS_LINK_MASK		0x0010
205 #define RTL8366RB_PORT_STATUS_TXPAUSE_MASK	0x0020
206 #define RTL8366RB_PORT_STATUS_RXPAUSE_MASK	0x0040
207 #define RTL8366RB_PORT_STATUS_AN_MASK		0x0080
208 
209 #define RTL8366RB_NUM_VLANS		16
210 #define RTL8366RB_NUM_VIDS		4096
211 #define RTL8366RB_PRIORITYMAX		7
212 #define RTL8366RB_NUM_FIDS		8
213 #define RTL8366RB_FIDMAX		7
214 
215 #define RTL8366RB_PORT_1		BIT(0) /* In userspace port 0 */
216 #define RTL8366RB_PORT_2		BIT(1) /* In userspace port 1 */
217 #define RTL8366RB_PORT_3		BIT(2) /* In userspace port 2 */
218 #define RTL8366RB_PORT_4		BIT(3) /* In userspace port 3 */
219 #define RTL8366RB_PORT_5		BIT(4) /* In userspace port 4 */
220 
221 #define RTL8366RB_PORT_CPU		BIT(5) /* CPU port */
222 
223 #define RTL8366RB_PORT_ALL		(RTL8366RB_PORT_1 |	\
224 					 RTL8366RB_PORT_2 |	\
225 					 RTL8366RB_PORT_3 |	\
226 					 RTL8366RB_PORT_4 |	\
227 					 RTL8366RB_PORT_5 |	\
228 					 RTL8366RB_PORT_CPU)
229 
230 #define RTL8366RB_PORT_ALL_BUT_CPU	(RTL8366RB_PORT_1 |	\
231 					 RTL8366RB_PORT_2 |	\
232 					 RTL8366RB_PORT_3 |	\
233 					 RTL8366RB_PORT_4 |	\
234 					 RTL8366RB_PORT_5)
235 
236 #define RTL8366RB_PORT_ALL_EXTERNAL	(RTL8366RB_PORT_1 |	\
237 					 RTL8366RB_PORT_2 |	\
238 					 RTL8366RB_PORT_3 |	\
239 					 RTL8366RB_PORT_4)
240 
241 #define RTL8366RB_PORT_ALL_INTERNAL	 RTL8366RB_PORT_CPU
242 
243 /* First configuration word per member config, VID and prio */
244 #define RTL8366RB_VLAN_VID_MASK		0xfff
245 #define RTL8366RB_VLAN_PRIORITY_SHIFT	12
246 #define RTL8366RB_VLAN_PRIORITY_MASK	0x7
247 /* Second configuration word per member config, member and untagged */
248 #define RTL8366RB_VLAN_UNTAG_SHIFT	8
249 #define RTL8366RB_VLAN_UNTAG_MASK	0xff
250 #define RTL8366RB_VLAN_MEMBER_MASK	0xff
251 /* Third config word per member config, STAG currently unused */
252 #define RTL8366RB_VLAN_STAG_MBR_MASK	0xff
253 #define RTL8366RB_VLAN_STAG_MBR_SHIFT	8
254 #define RTL8366RB_VLAN_STAG_IDX_MASK	0x7
255 #define RTL8366RB_VLAN_STAG_IDX_SHIFT	5
256 #define RTL8366RB_VLAN_FID_MASK		0x7
257 
258 /* Port ingress bandwidth control */
259 #define RTL8366RB_IB_BASE		0x0200
260 #define RTL8366RB_IB_REG(pnum)		(RTL8366RB_IB_BASE + (pnum))
261 #define RTL8366RB_IB_BDTH_MASK		0x3fff
262 #define RTL8366RB_IB_PREIFG		BIT(14)
263 
264 /* Port egress bandwidth control */
265 #define RTL8366RB_EB_BASE		0x02d1
266 #define RTL8366RB_EB_REG(pnum)		(RTL8366RB_EB_BASE + (pnum))
267 #define RTL8366RB_EB_BDTH_MASK		0x3fff
268 #define RTL8366RB_EB_PREIFG_REG		0x02f8
269 #define RTL8366RB_EB_PREIFG		BIT(9)
270 
271 #define RTL8366RB_BDTH_SW_MAX		1048512 /* 1048576? */
272 #define RTL8366RB_BDTH_UNIT		64
273 #define RTL8366RB_BDTH_REG_DEFAULT	16383
274 
275 /* QOS */
276 #define RTL8366RB_QOS			BIT(15)
277 /* Include/Exclude Preamble and IFG (20 bytes). 0:Exclude, 1:Include. */
278 #define RTL8366RB_QOS_DEFAULT_PREIFG	1
279 
280 /* Interrupt handling */
281 #define RTL8366RB_INTERRUPT_CONTROL_REG	0x0440
282 #define RTL8366RB_INTERRUPT_POLARITY	BIT(0)
283 #define RTL8366RB_P4_RGMII_LED		BIT(2)
284 #define RTL8366RB_INTERRUPT_MASK_REG	0x0441
285 #define RTL8366RB_INTERRUPT_LINK_CHGALL	GENMASK(11, 0)
286 #define RTL8366RB_INTERRUPT_ACLEXCEED	BIT(8)
287 #define RTL8366RB_INTERRUPT_STORMEXCEED	BIT(9)
288 #define RTL8366RB_INTERRUPT_P4_FIBER	BIT(12)
289 #define RTL8366RB_INTERRUPT_P4_UTP	BIT(13)
290 #define RTL8366RB_INTERRUPT_VALID	(RTL8366RB_INTERRUPT_LINK_CHGALL | \
291 					 RTL8366RB_INTERRUPT_ACLEXCEED | \
292 					 RTL8366RB_INTERRUPT_STORMEXCEED | \
293 					 RTL8366RB_INTERRUPT_P4_FIBER | \
294 					 RTL8366RB_INTERRUPT_P4_UTP)
295 #define RTL8366RB_INTERRUPT_STATUS_REG	0x0442
296 #define RTL8366RB_NUM_INTERRUPT		14 /* 0..13 */
297 
298 /* Port isolation registers */
299 #define RTL8366RB_PORT_ISO_BASE		0x0F08
300 #define RTL8366RB_PORT_ISO(pnum)	(RTL8366RB_PORT_ISO_BASE + (pnum))
301 #define RTL8366RB_PORT_ISO_EN		BIT(0)
302 #define RTL8366RB_PORT_ISO_PORTS_MASK	GENMASK(7, 1)
303 #define RTL8366RB_PORT_ISO_PORTS(pmask)	((pmask) << 1)
304 
305 /* bits 0..5 enable force when cleared */
306 #define RTL8366RB_MAC_FORCE_CTRL_REG	0x0F11
307 
308 #define RTL8366RB_OAM_PARSER_REG	0x0F14
309 #define RTL8366RB_OAM_MULTIPLEXER_REG	0x0F15
310 
311 #define RTL8366RB_GREEN_FEATURE_REG	0x0F51
312 #define RTL8366RB_GREEN_FEATURE_MSK	0x0007
313 #define RTL8366RB_GREEN_FEATURE_TX	BIT(0)
314 #define RTL8366RB_GREEN_FEATURE_RX	BIT(2)
315 
316 static struct rtl8366_mib_counter rtl8366rb_mib_counters[] = {
317 	{ 0,  0, 4, "IfInOctets"				},
318 	{ 0,  4, 4, "EtherStatsOctets"				},
319 	{ 0,  8, 2, "EtherStatsUnderSizePkts"			},
320 	{ 0, 10, 2, "EtherFragments"				},
321 	{ 0, 12, 2, "EtherStatsPkts64Octets"			},
322 	{ 0, 14, 2, "EtherStatsPkts65to127Octets"		},
323 	{ 0, 16, 2, "EtherStatsPkts128to255Octets"		},
324 	{ 0, 18, 2, "EtherStatsPkts256to511Octets"		},
325 	{ 0, 20, 2, "EtherStatsPkts512to1023Octets"		},
326 	{ 0, 22, 2, "EtherStatsPkts1024to1518Octets"		},
327 	{ 0, 24, 2, "EtherOversizeStats"			},
328 	{ 0, 26, 2, "EtherStatsJabbers"				},
329 	{ 0, 28, 2, "IfInUcastPkts"				},
330 	{ 0, 30, 2, "EtherStatsMulticastPkts"			},
331 	{ 0, 32, 2, "EtherStatsBroadcastPkts"			},
332 	{ 0, 34, 2, "EtherStatsDropEvents"			},
333 	{ 0, 36, 2, "Dot3StatsFCSErrors"			},
334 	{ 0, 38, 2, "Dot3StatsSymbolErrors"			},
335 	{ 0, 40, 2, "Dot3InPauseFrames"				},
336 	{ 0, 42, 2, "Dot3ControlInUnknownOpcodes"		},
337 	{ 0, 44, 4, "IfOutOctets"				},
338 	{ 0, 48, 2, "Dot3StatsSingleCollisionFrames"		},
339 	{ 0, 50, 2, "Dot3StatMultipleCollisionFrames"		},
340 	{ 0, 52, 2, "Dot3sDeferredTransmissions"		},
341 	{ 0, 54, 2, "Dot3StatsLateCollisions"			},
342 	{ 0, 56, 2, "EtherStatsCollisions"			},
343 	{ 0, 58, 2, "Dot3StatsExcessiveCollisions"		},
344 	{ 0, 60, 2, "Dot3OutPauseFrames"			},
345 	{ 0, 62, 2, "Dot1dBasePortDelayExceededDiscards"	},
346 	{ 0, 64, 2, "Dot1dTpPortInDiscards"			},
347 	{ 0, 66, 2, "IfOutUcastPkts"				},
348 	{ 0, 68, 2, "IfOutMulticastPkts"			},
349 	{ 0, 70, 2, "IfOutBroadcastPkts"			},
350 };
351 
rtl8366rb_get_mib_counter(struct realtek_priv * priv,int port,struct rtl8366_mib_counter * mib,u64 * mibvalue)352 static int rtl8366rb_get_mib_counter(struct realtek_priv *priv,
353 				     int port,
354 				     struct rtl8366_mib_counter *mib,
355 				     u64 *mibvalue)
356 {
357 	u32 addr, val;
358 	int ret;
359 	int i;
360 
361 	addr = RTL8366RB_MIB_COUNTER_BASE +
362 		RTL8366RB_MIB_COUNTER_PORT_OFFSET * (port) +
363 		mib->offset;
364 
365 	/* Writing access counter address first
366 	 * then ASIC will prepare 64bits counter wait for being retrived
367 	 */
368 	ret = regmap_write(priv->map, addr, 0); /* Write whatever */
369 	if (ret)
370 		return ret;
371 
372 	/* Read MIB control register */
373 	ret = regmap_read(priv->map, RTL8366RB_MIB_CTRL_REG, &val);
374 	if (ret)
375 		return -EIO;
376 
377 	if (val & RTL8366RB_MIB_CTRL_BUSY_MASK)
378 		return -EBUSY;
379 
380 	if (val & RTL8366RB_MIB_CTRL_RESET_MASK)
381 		return -EIO;
382 
383 	/* Read each individual MIB 16 bits at the time */
384 	*mibvalue = 0;
385 	for (i = mib->length; i > 0; i--) {
386 		ret = regmap_read(priv->map, addr + (i - 1), &val);
387 		if (ret)
388 			return ret;
389 		*mibvalue = (*mibvalue << 16) | (val & 0xFFFF);
390 	}
391 	return 0;
392 }
393 
rtl8366rb_get_irqmask(struct irq_data * d)394 static u32 rtl8366rb_get_irqmask(struct irq_data *d)
395 {
396 	int line = irqd_to_hwirq(d);
397 	u32 val;
398 
399 	/* For line interrupts we combine link down in bits
400 	 * 6..11 with link up in bits 0..5 into one interrupt.
401 	 */
402 	if (line < 12)
403 		val = BIT(line) | BIT(line + 6);
404 	else
405 		val = BIT(line);
406 	return val;
407 }
408 
rtl8366rb_mask_irq(struct irq_data * d)409 static void rtl8366rb_mask_irq(struct irq_data *d)
410 {
411 	struct realtek_priv *priv = irq_data_get_irq_chip_data(d);
412 	int ret;
413 
414 	ret = regmap_update_bits(priv->map, RTL8366RB_INTERRUPT_MASK_REG,
415 				 rtl8366rb_get_irqmask(d), 0);
416 	if (ret)
417 		dev_err(priv->dev, "could not mask IRQ\n");
418 }
419 
rtl8366rb_unmask_irq(struct irq_data * d)420 static void rtl8366rb_unmask_irq(struct irq_data *d)
421 {
422 	struct realtek_priv *priv = irq_data_get_irq_chip_data(d);
423 	int ret;
424 
425 	ret = regmap_update_bits(priv->map, RTL8366RB_INTERRUPT_MASK_REG,
426 				 rtl8366rb_get_irqmask(d),
427 				 rtl8366rb_get_irqmask(d));
428 	if (ret)
429 		dev_err(priv->dev, "could not unmask IRQ\n");
430 }
431 
rtl8366rb_irq(int irq,void * data)432 static irqreturn_t rtl8366rb_irq(int irq, void *data)
433 {
434 	struct realtek_priv *priv = data;
435 	u32 stat;
436 	int ret;
437 
438 	/* This clears the IRQ status register */
439 	ret = regmap_read(priv->map, RTL8366RB_INTERRUPT_STATUS_REG,
440 			  &stat);
441 	if (ret) {
442 		dev_err(priv->dev, "can't read interrupt status\n");
443 		return IRQ_NONE;
444 	}
445 	stat &= RTL8366RB_INTERRUPT_VALID;
446 	if (!stat)
447 		return IRQ_NONE;
448 	while (stat) {
449 		int line = __ffs(stat);
450 		int child_irq;
451 
452 		stat &= ~BIT(line);
453 		/* For line interrupts we combine link down in bits
454 		 * 6..11 with link up in bits 0..5 into one interrupt.
455 		 */
456 		if (line < 12 && line > 5)
457 			line -= 5;
458 		child_irq = irq_find_mapping(priv->irqdomain, line);
459 		handle_nested_irq(child_irq);
460 	}
461 	return IRQ_HANDLED;
462 }
463 
464 static struct irq_chip rtl8366rb_irq_chip = {
465 	.name = "RTL8366RB",
466 	.irq_mask = rtl8366rb_mask_irq,
467 	.irq_unmask = rtl8366rb_unmask_irq,
468 };
469 
rtl8366rb_irq_map(struct irq_domain * domain,unsigned int irq,irq_hw_number_t hwirq)470 static int rtl8366rb_irq_map(struct irq_domain *domain, unsigned int irq,
471 			     irq_hw_number_t hwirq)
472 {
473 	irq_set_chip_data(irq, domain->host_data);
474 	irq_set_chip_and_handler(irq, &rtl8366rb_irq_chip, handle_simple_irq);
475 	irq_set_nested_thread(irq, 1);
476 	irq_set_noprobe(irq);
477 
478 	return 0;
479 }
480 
rtl8366rb_irq_unmap(struct irq_domain * d,unsigned int irq)481 static void rtl8366rb_irq_unmap(struct irq_domain *d, unsigned int irq)
482 {
483 	irq_set_nested_thread(irq, 0);
484 	irq_set_chip_and_handler(irq, NULL, NULL);
485 	irq_set_chip_data(irq, NULL);
486 }
487 
488 static const struct irq_domain_ops rtl8366rb_irqdomain_ops = {
489 	.map = rtl8366rb_irq_map,
490 	.unmap = rtl8366rb_irq_unmap,
491 	.xlate  = irq_domain_xlate_onecell,
492 };
493 
rtl8366rb_setup_cascaded_irq(struct realtek_priv * priv)494 static int rtl8366rb_setup_cascaded_irq(struct realtek_priv *priv)
495 {
496 	struct device_node *intc;
497 	unsigned long irq_trig;
498 	int irq;
499 	int ret;
500 	u32 val;
501 	int i;
502 
503 	intc = of_get_child_by_name(priv->dev->of_node, "interrupt-controller");
504 	if (!intc) {
505 		dev_err(priv->dev, "missing child interrupt-controller node\n");
506 		return -EINVAL;
507 	}
508 	/* RB8366RB IRQs cascade off this one */
509 	irq = of_irq_get(intc, 0);
510 	if (irq <= 0) {
511 		dev_err(priv->dev, "failed to get parent IRQ\n");
512 		ret = irq ? irq : -EINVAL;
513 		goto out_put_node;
514 	}
515 
516 	/* This clears the IRQ status register */
517 	ret = regmap_read(priv->map, RTL8366RB_INTERRUPT_STATUS_REG,
518 			  &val);
519 	if (ret) {
520 		dev_err(priv->dev, "can't read interrupt status\n");
521 		goto out_put_node;
522 	}
523 
524 	/* Fetch IRQ edge information from the descriptor */
525 	irq_trig = irq_get_trigger_type(irq);
526 	switch (irq_trig) {
527 	case IRQF_TRIGGER_RISING:
528 	case IRQF_TRIGGER_HIGH:
529 		dev_info(priv->dev, "active high/rising IRQ\n");
530 		val = 0;
531 		break;
532 	case IRQF_TRIGGER_FALLING:
533 	case IRQF_TRIGGER_LOW:
534 		dev_info(priv->dev, "active low/falling IRQ\n");
535 		val = RTL8366RB_INTERRUPT_POLARITY;
536 		break;
537 	}
538 	ret = regmap_update_bits(priv->map, RTL8366RB_INTERRUPT_CONTROL_REG,
539 				 RTL8366RB_INTERRUPT_POLARITY,
540 				 val);
541 	if (ret) {
542 		dev_err(priv->dev, "could not configure IRQ polarity\n");
543 		goto out_put_node;
544 	}
545 
546 	ret = devm_request_threaded_irq(priv->dev, irq, NULL,
547 					rtl8366rb_irq, IRQF_ONESHOT,
548 					"RTL8366RB", priv);
549 	if (ret) {
550 		dev_err(priv->dev, "unable to request irq: %d\n", ret);
551 		goto out_put_node;
552 	}
553 	priv->irqdomain = irq_domain_add_linear(intc,
554 						RTL8366RB_NUM_INTERRUPT,
555 						&rtl8366rb_irqdomain_ops,
556 						priv);
557 	if (!priv->irqdomain) {
558 		dev_err(priv->dev, "failed to create IRQ domain\n");
559 		ret = -EINVAL;
560 		goto out_put_node;
561 	}
562 	for (i = 0; i < priv->num_ports; i++)
563 		irq_set_parent(irq_create_mapping(priv->irqdomain, i), irq);
564 
565 out_put_node:
566 	of_node_put(intc);
567 	return ret;
568 }
569 
rtl8366rb_set_addr(struct realtek_priv * priv)570 static int rtl8366rb_set_addr(struct realtek_priv *priv)
571 {
572 	u8 addr[ETH_ALEN];
573 	u16 val;
574 	int ret;
575 
576 	eth_random_addr(addr);
577 
578 	dev_info(priv->dev, "set MAC: %02X:%02X:%02X:%02X:%02X:%02X\n",
579 		 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
580 	val = addr[0] << 8 | addr[1];
581 	ret = regmap_write(priv->map, RTL8366RB_SMAR0, val);
582 	if (ret)
583 		return ret;
584 	val = addr[2] << 8 | addr[3];
585 	ret = regmap_write(priv->map, RTL8366RB_SMAR1, val);
586 	if (ret)
587 		return ret;
588 	val = addr[4] << 8 | addr[5];
589 	ret = regmap_write(priv->map, RTL8366RB_SMAR2, val);
590 	if (ret)
591 		return ret;
592 
593 	return 0;
594 }
595 
596 /* Found in a vendor driver */
597 
598 /* Struct for handling the jam tables' entries */
599 struct rtl8366rb_jam_tbl_entry {
600 	u16 reg;
601 	u16 val;
602 };
603 
604 /* For the "version 0" early silicon, appear in most source releases */
605 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_ver_0[] = {
606 	{0x000B, 0x0001}, {0x03A6, 0x0100}, {0x03A7, 0x0001}, {0x02D1, 0x3FFF},
607 	{0x02D2, 0x3FFF}, {0x02D3, 0x3FFF}, {0x02D4, 0x3FFF}, {0x02D5, 0x3FFF},
608 	{0x02D6, 0x3FFF}, {0x02D7, 0x3FFF}, {0x02D8, 0x3FFF}, {0x022B, 0x0688},
609 	{0x022C, 0x0FAC}, {0x03D0, 0x4688}, {0x03D1, 0x01F5}, {0x0000, 0x0830},
610 	{0x02F9, 0x0200}, {0x02F7, 0x7FFF}, {0x02F8, 0x03FF}, {0x0080, 0x03E8},
611 	{0x0081, 0x00CE}, {0x0082, 0x00DA}, {0x0083, 0x0230}, {0xBE0F, 0x2000},
612 	{0x0231, 0x422A}, {0x0232, 0x422A}, {0x0233, 0x422A}, {0x0234, 0x422A},
613 	{0x0235, 0x422A}, {0x0236, 0x422A}, {0x0237, 0x422A}, {0x0238, 0x422A},
614 	{0x0239, 0x422A}, {0x023A, 0x422A}, {0x023B, 0x422A}, {0x023C, 0x422A},
615 	{0x023D, 0x422A}, {0x023E, 0x422A}, {0x023F, 0x422A}, {0x0240, 0x422A},
616 	{0x0241, 0x422A}, {0x0242, 0x422A}, {0x0243, 0x422A}, {0x0244, 0x422A},
617 	{0x0245, 0x422A}, {0x0246, 0x422A}, {0x0247, 0x422A}, {0x0248, 0x422A},
618 	{0x0249, 0x0146}, {0x024A, 0x0146}, {0x024B, 0x0146}, {0xBE03, 0xC961},
619 	{0x024D, 0x0146}, {0x024E, 0x0146}, {0x024F, 0x0146}, {0x0250, 0x0146},
620 	{0xBE64, 0x0226}, {0x0252, 0x0146}, {0x0253, 0x0146}, {0x024C, 0x0146},
621 	{0x0251, 0x0146}, {0x0254, 0x0146}, {0xBE62, 0x3FD0}, {0x0084, 0x0320},
622 	{0x0255, 0x0146}, {0x0256, 0x0146}, {0x0257, 0x0146}, {0x0258, 0x0146},
623 	{0x0259, 0x0146}, {0x025A, 0x0146}, {0x025B, 0x0146}, {0x025C, 0x0146},
624 	{0x025D, 0x0146}, {0x025E, 0x0146}, {0x025F, 0x0146}, {0x0260, 0x0146},
625 	{0x0261, 0xA23F}, {0x0262, 0x0294}, {0x0263, 0xA23F}, {0x0264, 0x0294},
626 	{0x0265, 0xA23F}, {0x0266, 0x0294}, {0x0267, 0xA23F}, {0x0268, 0x0294},
627 	{0x0269, 0xA23F}, {0x026A, 0x0294}, {0x026B, 0xA23F}, {0x026C, 0x0294},
628 	{0x026D, 0xA23F}, {0x026E, 0x0294}, {0x026F, 0xA23F}, {0x0270, 0x0294},
629 	{0x02F5, 0x0048}, {0xBE09, 0x0E00}, {0xBE1E, 0x0FA0}, {0xBE14, 0x8448},
630 	{0xBE15, 0x1007}, {0xBE4A, 0xA284}, {0xC454, 0x3F0B}, {0xC474, 0x3F0B},
631 	{0xBE48, 0x3672}, {0xBE4B, 0x17A7}, {0xBE4C, 0x0B15}, {0xBE52, 0x0EDD},
632 	{0xBE49, 0x8C00}, {0xBE5B, 0x785C}, {0xBE5C, 0x785C}, {0xBE5D, 0x785C},
633 	{0xBE61, 0x368A}, {0xBE63, 0x9B84}, {0xC456, 0xCC13}, {0xC476, 0xCC13},
634 	{0xBE65, 0x307D}, {0xBE6D, 0x0005}, {0xBE6E, 0xE120}, {0xBE2E, 0x7BAF},
635 };
636 
637 /* This v1 init sequence is from Belkin F5D8235 U-Boot release */
638 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_ver_1[] = {
639 	{0x0000, 0x0830}, {0x0001, 0x8000}, {0x0400, 0x8130}, {0xBE78, 0x3C3C},
640 	{0x0431, 0x5432}, {0xBE37, 0x0CE4}, {0x02FA, 0xFFDF}, {0x02FB, 0xFFE0},
641 	{0xC44C, 0x1585}, {0xC44C, 0x1185}, {0xC44C, 0x1585}, {0xC46C, 0x1585},
642 	{0xC46C, 0x1185}, {0xC46C, 0x1585}, {0xC451, 0x2135}, {0xC471, 0x2135},
643 	{0xBE10, 0x8140}, {0xBE15, 0x0007}, {0xBE6E, 0xE120}, {0xBE69, 0xD20F},
644 	{0xBE6B, 0x0320}, {0xBE24, 0xB000}, {0xBE23, 0xFF51}, {0xBE22, 0xDF20},
645 	{0xBE21, 0x0140}, {0xBE20, 0x00BB}, {0xBE24, 0xB800}, {0xBE24, 0x0000},
646 	{0xBE24, 0x7000}, {0xBE23, 0xFF51}, {0xBE22, 0xDF60}, {0xBE21, 0x0140},
647 	{0xBE20, 0x0077}, {0xBE24, 0x7800}, {0xBE24, 0x0000}, {0xBE2E, 0x7B7A},
648 	{0xBE36, 0x0CE4}, {0x02F5, 0x0048}, {0xBE77, 0x2940}, {0x000A, 0x83E0},
649 	{0xBE79, 0x3C3C}, {0xBE00, 0x1340},
650 };
651 
652 /* This v2 init sequence is from Belkin F5D8235 U-Boot release */
653 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_ver_2[] = {
654 	{0x0450, 0x0000}, {0x0400, 0x8130}, {0x000A, 0x83ED}, {0x0431, 0x5432},
655 	{0xC44F, 0x6250}, {0xC46F, 0x6250}, {0xC456, 0x0C14}, {0xC476, 0x0C14},
656 	{0xC44C, 0x1C85}, {0xC44C, 0x1885}, {0xC44C, 0x1C85}, {0xC46C, 0x1C85},
657 	{0xC46C, 0x1885}, {0xC46C, 0x1C85}, {0xC44C, 0x0885}, {0xC44C, 0x0881},
658 	{0xC44C, 0x0885}, {0xC46C, 0x0885}, {0xC46C, 0x0881}, {0xC46C, 0x0885},
659 	{0xBE2E, 0x7BA7}, {0xBE36, 0x1000}, {0xBE37, 0x1000}, {0x8000, 0x0001},
660 	{0xBE69, 0xD50F}, {0x8000, 0x0000}, {0xBE69, 0xD50F}, {0xBE6E, 0x0320},
661 	{0xBE77, 0x2940}, {0xBE78, 0x3C3C}, {0xBE79, 0x3C3C}, {0xBE6E, 0xE120},
662 	{0x8000, 0x0001}, {0xBE15, 0x1007}, {0x8000, 0x0000}, {0xBE15, 0x1007},
663 	{0xBE14, 0x0448}, {0xBE1E, 0x00A0}, {0xBE10, 0x8160}, {0xBE10, 0x8140},
664 	{0xBE00, 0x1340}, {0x0F51, 0x0010},
665 };
666 
667 /* Appears in a DDWRT code dump */
668 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_ver_3[] = {
669 	{0x0000, 0x0830}, {0x0400, 0x8130}, {0x000A, 0x83ED}, {0x0431, 0x5432},
670 	{0x0F51, 0x0017}, {0x02F5, 0x0048}, {0x02FA, 0xFFDF}, {0x02FB, 0xFFE0},
671 	{0xC456, 0x0C14}, {0xC476, 0x0C14}, {0xC454, 0x3F8B}, {0xC474, 0x3F8B},
672 	{0xC450, 0x2071}, {0xC470, 0x2071}, {0xC451, 0x226B}, {0xC471, 0x226B},
673 	{0xC452, 0xA293}, {0xC472, 0xA293}, {0xC44C, 0x1585}, {0xC44C, 0x1185},
674 	{0xC44C, 0x1585}, {0xC46C, 0x1585}, {0xC46C, 0x1185}, {0xC46C, 0x1585},
675 	{0xC44C, 0x0185}, {0xC44C, 0x0181}, {0xC44C, 0x0185}, {0xC46C, 0x0185},
676 	{0xC46C, 0x0181}, {0xC46C, 0x0185}, {0xBE24, 0xB000}, {0xBE23, 0xFF51},
677 	{0xBE22, 0xDF20}, {0xBE21, 0x0140}, {0xBE20, 0x00BB}, {0xBE24, 0xB800},
678 	{0xBE24, 0x0000}, {0xBE24, 0x7000}, {0xBE23, 0xFF51}, {0xBE22, 0xDF60},
679 	{0xBE21, 0x0140}, {0xBE20, 0x0077}, {0xBE24, 0x7800}, {0xBE24, 0x0000},
680 	{0xBE2E, 0x7BA7}, {0xBE36, 0x1000}, {0xBE37, 0x1000}, {0x8000, 0x0001},
681 	{0xBE69, 0xD50F}, {0x8000, 0x0000}, {0xBE69, 0xD50F}, {0xBE6B, 0x0320},
682 	{0xBE77, 0x2800}, {0xBE78, 0x3C3C}, {0xBE79, 0x3C3C}, {0xBE6E, 0xE120},
683 	{0x8000, 0x0001}, {0xBE10, 0x8140}, {0x8000, 0x0000}, {0xBE10, 0x8140},
684 	{0xBE15, 0x1007}, {0xBE14, 0x0448}, {0xBE1E, 0x00A0}, {0xBE10, 0x8160},
685 	{0xBE10, 0x8140}, {0xBE00, 0x1340}, {0x0450, 0x0000}, {0x0401, 0x0000},
686 };
687 
688 /* Belkin F5D8235 v1, "belkin,f5d8235-v1" */
689 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_f5d8235[] = {
690 	{0x0242, 0x02BF}, {0x0245, 0x02BF}, {0x0248, 0x02BF}, {0x024B, 0x02BF},
691 	{0x024E, 0x02BF}, {0x0251, 0x02BF}, {0x0254, 0x0A3F}, {0x0256, 0x0A3F},
692 	{0x0258, 0x0A3F}, {0x025A, 0x0A3F}, {0x025C, 0x0A3F}, {0x025E, 0x0A3F},
693 	{0x0263, 0x007C}, {0x0100, 0x0004}, {0xBE5B, 0x3500}, {0x800E, 0x200F},
694 	{0xBE1D, 0x0F00}, {0x8001, 0x5011}, {0x800A, 0xA2F4}, {0x800B, 0x17A3},
695 	{0xBE4B, 0x17A3}, {0xBE41, 0x5011}, {0xBE17, 0x2100}, {0x8000, 0x8304},
696 	{0xBE40, 0x8304}, {0xBE4A, 0xA2F4}, {0x800C, 0xA8D5}, {0x8014, 0x5500},
697 	{0x8015, 0x0004}, {0xBE4C, 0xA8D5}, {0xBE59, 0x0008}, {0xBE09, 0x0E00},
698 	{0xBE36, 0x1036}, {0xBE37, 0x1036}, {0x800D, 0x00FF}, {0xBE4D, 0x00FF},
699 };
700 
701 /* DGN3500, "netgear,dgn3500", "netgear,dgn3500b" */
702 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_dgn3500[] = {
703 	{0x0000, 0x0830}, {0x0400, 0x8130}, {0x000A, 0x83ED}, {0x0F51, 0x0017},
704 	{0x02F5, 0x0048}, {0x02FA, 0xFFDF}, {0x02FB, 0xFFE0}, {0x0450, 0x0000},
705 	{0x0401, 0x0000}, {0x0431, 0x0960},
706 };
707 
708 /* This jam table activates "green ethernet", which means low power mode
709  * and is claimed to detect the cable length and not use more power than
710  * necessary, and the ports should enter power saving mode 10 seconds after
711  * a cable is disconnected. Seems to always be the same.
712  */
713 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_green_jam[] = {
714 	{0xBE78, 0x323C}, {0xBE77, 0x5000}, {0xBE2E, 0x7BA7},
715 	{0xBE59, 0x3459}, {0xBE5A, 0x745A}, {0xBE5B, 0x785C},
716 	{0xBE5C, 0x785C}, {0xBE6E, 0xE120}, {0xBE79, 0x323C},
717 };
718 
719 /* Function that jams the tables in the proper registers */
rtl8366rb_jam_table(const struct rtl8366rb_jam_tbl_entry * jam_table,int jam_size,struct realtek_priv * priv,bool write_dbg)720 static int rtl8366rb_jam_table(const struct rtl8366rb_jam_tbl_entry *jam_table,
721 			       int jam_size, struct realtek_priv *priv,
722 			       bool write_dbg)
723 {
724 	u32 val;
725 	int ret;
726 	int i;
727 
728 	for (i = 0; i < jam_size; i++) {
729 		if ((jam_table[i].reg & 0xBE00) == 0xBE00) {
730 			ret = regmap_read(priv->map,
731 					  RTL8366RB_PHY_ACCESS_BUSY_REG,
732 					  &val);
733 			if (ret)
734 				return ret;
735 			if (!(val & RTL8366RB_PHY_INT_BUSY)) {
736 				ret = regmap_write(priv->map,
737 						   RTL8366RB_PHY_ACCESS_CTRL_REG,
738 						   RTL8366RB_PHY_CTRL_WRITE);
739 				if (ret)
740 					return ret;
741 			}
742 		}
743 		if (write_dbg)
744 			dev_dbg(priv->dev, "jam %04x into register %04x\n",
745 				jam_table[i].val,
746 				jam_table[i].reg);
747 		ret = regmap_write(priv->map,
748 				   jam_table[i].reg,
749 				   jam_table[i].val);
750 		if (ret)
751 			return ret;
752 	}
753 	return 0;
754 }
755 
756 /* This code is used also with LEDs disabled */
rb8366rb_set_ledgroup_mode(struct realtek_priv * priv,u8 led_group,enum rtl8366_ledgroup_mode mode)757 int rb8366rb_set_ledgroup_mode(struct realtek_priv *priv,
758 			       u8 led_group,
759 			       enum rtl8366_ledgroup_mode mode)
760 {
761 	int ret;
762 	u32 val;
763 
764 	val = mode << RTL8366RB_LED_CTRL_OFFSET(led_group);
765 
766 	ret = regmap_update_bits(priv->map,
767 				 RTL8366RB_LED_CTRL_REG,
768 				 RTL8366RB_LED_CTRL_MASK(led_group),
769 				 val);
770 	if (ret)
771 		return ret;
772 
773 	return 0;
774 }
775 
776 /* This code is used also with LEDs disabled */
rtl8366rb_setup_all_leds_off(struct realtek_priv * priv)777 static int rtl8366rb_setup_all_leds_off(struct realtek_priv *priv)
778 {
779 	int ret = 0;
780 	int i;
781 
782 	regmap_update_bits(priv->map,
783 			   RTL8366RB_INTERRUPT_CONTROL_REG,
784 			   RTL8366RB_P4_RGMII_LED,
785 			   0);
786 
787 	for (i = 0; i < RTL8366RB_NUM_LEDGROUPS; i++) {
788 		ret = rb8366rb_set_ledgroup_mode(priv, i,
789 						 RTL8366RB_LEDGROUP_OFF);
790 		if (ret)
791 			return ret;
792 	}
793 
794 	return ret;
795 }
796 
rtl8366rb_setup(struct dsa_switch * ds)797 static int rtl8366rb_setup(struct dsa_switch *ds)
798 {
799 	struct realtek_priv *priv = ds->priv;
800 	const struct rtl8366rb_jam_tbl_entry *jam_table;
801 	struct rtl8366rb *rb;
802 	u32 chip_ver = 0;
803 	u32 chip_id = 0;
804 	int jam_size;
805 	int ret;
806 	int i;
807 
808 	rb = priv->chip_data;
809 
810 	ret = regmap_read(priv->map, RTL8366RB_CHIP_ID_REG, &chip_id);
811 	if (ret) {
812 		dev_err(priv->dev, "unable to read chip id\n");
813 		return ret;
814 	}
815 
816 	switch (chip_id) {
817 	case RTL8366RB_CHIP_ID_8366:
818 		break;
819 	default:
820 		dev_err(priv->dev, "unknown chip id (%04x)\n", chip_id);
821 		return -ENODEV;
822 	}
823 
824 	ret = regmap_read(priv->map, RTL8366RB_CHIP_VERSION_CTRL_REG,
825 			  &chip_ver);
826 	if (ret) {
827 		dev_err(priv->dev, "unable to read chip version\n");
828 		return ret;
829 	}
830 
831 	dev_info(priv->dev, "RTL%04x ver %u chip found\n",
832 		 chip_id, chip_ver & RTL8366RB_CHIP_VERSION_MASK);
833 
834 	/* Do the init dance using the right jam table */
835 	switch (chip_ver) {
836 	case 0:
837 		jam_table = rtl8366rb_init_jam_ver_0;
838 		jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_0);
839 		break;
840 	case 1:
841 		jam_table = rtl8366rb_init_jam_ver_1;
842 		jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_1);
843 		break;
844 	case 2:
845 		jam_table = rtl8366rb_init_jam_ver_2;
846 		jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_2);
847 		break;
848 	default:
849 		jam_table = rtl8366rb_init_jam_ver_3;
850 		jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_3);
851 		break;
852 	}
853 
854 	/* Special jam tables for special routers
855 	 * TODO: are these necessary? Maintainers, please test
856 	 * without them, using just the off-the-shelf tables.
857 	 */
858 	if (of_machine_is_compatible("belkin,f5d8235-v1")) {
859 		jam_table = rtl8366rb_init_jam_f5d8235;
860 		jam_size = ARRAY_SIZE(rtl8366rb_init_jam_f5d8235);
861 	}
862 	if (of_machine_is_compatible("netgear,dgn3500") ||
863 	    of_machine_is_compatible("netgear,dgn3500b")) {
864 		jam_table = rtl8366rb_init_jam_dgn3500;
865 		jam_size = ARRAY_SIZE(rtl8366rb_init_jam_dgn3500);
866 	}
867 
868 	ret = rtl8366rb_jam_table(jam_table, jam_size, priv, true);
869 	if (ret)
870 		return ret;
871 
872 	/* Isolate all user ports so they can only send packets to itself and the CPU port */
873 	for (i = 0; i < RTL8366RB_PORT_NUM_CPU; i++) {
874 		ret = regmap_write(priv->map, RTL8366RB_PORT_ISO(i),
875 				   RTL8366RB_PORT_ISO_PORTS(BIT(RTL8366RB_PORT_NUM_CPU)) |
876 				   RTL8366RB_PORT_ISO_EN);
877 		if (ret)
878 			return ret;
879 	}
880 	/* CPU port can send packets to all ports */
881 	ret = regmap_write(priv->map, RTL8366RB_PORT_ISO(RTL8366RB_PORT_NUM_CPU),
882 			   RTL8366RB_PORT_ISO_PORTS(dsa_user_ports(ds)) |
883 			   RTL8366RB_PORT_ISO_EN);
884 	if (ret)
885 		return ret;
886 
887 	/* Set up the "green ethernet" feature */
888 	ret = rtl8366rb_jam_table(rtl8366rb_green_jam,
889 				  ARRAY_SIZE(rtl8366rb_green_jam), priv, false);
890 	if (ret)
891 		return ret;
892 
893 	ret = regmap_write(priv->map,
894 			   RTL8366RB_GREEN_FEATURE_REG,
895 			   (chip_ver == 1) ? 0x0007 : 0x0003);
896 	if (ret)
897 		return ret;
898 
899 	/* Vendor driver sets 0x240 in registers 0xc and 0xd (undocumented) */
900 	ret = regmap_write(priv->map, 0x0c, 0x240);
901 	if (ret)
902 		return ret;
903 	ret = regmap_write(priv->map, 0x0d, 0x240);
904 	if (ret)
905 		return ret;
906 
907 	/* Set some random MAC address */
908 	ret = rtl8366rb_set_addr(priv);
909 	if (ret)
910 		return ret;
911 
912 	/* Enable CPU port with custom DSA tag 8899.
913 	 *
914 	 * If you set RTL8366RB_CPU_NO_TAG (bit 15) in this register
915 	 * the custom tag is turned off.
916 	 */
917 	ret = regmap_update_bits(priv->map, RTL8366RB_CPU_CTRL_REG,
918 				 0xFFFF,
919 				 BIT(priv->cpu_port));
920 	if (ret)
921 		return ret;
922 
923 	/* Make sure we default-enable the fixed CPU port */
924 	ret = regmap_update_bits(priv->map, RTL8366RB_PECR,
925 				 BIT(priv->cpu_port),
926 				 0);
927 	if (ret)
928 		return ret;
929 
930 	/* Set default maximum packet length to 1536 bytes */
931 	ret = regmap_update_bits(priv->map, RTL8366RB_SGCR,
932 				 RTL8366RB_SGCR_MAX_LENGTH_MASK,
933 				 RTL8366RB_SGCR_MAX_LENGTH_1536);
934 	if (ret)
935 		return ret;
936 	for (i = 0; i < RTL8366RB_NUM_PORTS; i++) {
937 		if (i == priv->cpu_port)
938 			/* CPU port need to also accept the tag */
939 			rb->max_mtu[i] = ETH_DATA_LEN + RTL8366RB_CPU_TAG_SIZE;
940 		else
941 			rb->max_mtu[i] = ETH_DATA_LEN;
942 	}
943 
944 	/* Disable learning for all ports */
945 	ret = regmap_write(priv->map, RTL8366RB_PORT_LEARNDIS_CTRL,
946 			   RTL8366RB_PORT_ALL);
947 	if (ret)
948 		return ret;
949 
950 	/* Enable auto ageing for all ports */
951 	ret = regmap_write(priv->map, RTL8366RB_SECURITY_CTRL, 0);
952 	if (ret)
953 		return ret;
954 
955 	/* Port 4 setup: this enables Port 4, usually the WAN port,
956 	 * common PHY IO mode is apparently mode 0, and this is not what
957 	 * the port is initialized to. There is no explanation of the
958 	 * IO modes in the Realtek source code, if your WAN port is
959 	 * connected to something exotic such as fiber, then this might
960 	 * be worth experimenting with.
961 	 */
962 	ret = regmap_update_bits(priv->map, RTL8366RB_PMC0,
963 				 RTL8366RB_PMC0_P4_IOMODE_MASK,
964 				 0 << RTL8366RB_PMC0_P4_IOMODE_SHIFT);
965 	if (ret)
966 		return ret;
967 
968 	/* Accept all packets by default, we enable filtering on-demand */
969 	ret = regmap_write(priv->map, RTL8366RB_VLAN_INGRESS_CTRL1_REG,
970 			   0);
971 	if (ret)
972 		return ret;
973 	ret = regmap_write(priv->map, RTL8366RB_VLAN_INGRESS_CTRL2_REG,
974 			   0);
975 	if (ret)
976 		return ret;
977 
978 	/* Don't drop packets whose DA has not been learned */
979 	ret = regmap_update_bits(priv->map, RTL8366RB_SSCR2,
980 				 RTL8366RB_SSCR2_DROP_UNKNOWN_DA, 0);
981 	if (ret)
982 		return ret;
983 
984 	/* Set blinking, used by all LED groups using HW triggers.
985 	 * TODO: make this configurable
986 	 */
987 	ret = regmap_update_bits(priv->map, RTL8366RB_LED_BLINKRATE_REG,
988 				 RTL8366RB_LED_BLINKRATE_MASK,
989 				 RTL8366RB_LED_BLINKRATE_56MS);
990 	if (ret)
991 		return ret;
992 
993 	/* Set up LED activity:
994 	 * Each port has 4 LEDs on fixed groups. Each group shares the same
995 	 * hardware trigger across all ports. LEDs can only be indiviually
996 	 * controlled setting the LED group to fixed mode and using the driver
997 	 * to toggle them LEDs on/off.
998 	 */
999 	if (priv->leds_disabled) {
1000 		ret = rtl8366rb_setup_all_leds_off(priv);
1001 		if (ret)
1002 			return ret;
1003 	} else {
1004 		ret = rtl8366rb_setup_leds(priv);
1005 		if (ret)
1006 			return ret;
1007 	}
1008 
1009 	ret = rtl8366_reset_vlan(priv);
1010 	if (ret)
1011 		return ret;
1012 
1013 	ret = rtl8366rb_setup_cascaded_irq(priv);
1014 	if (ret)
1015 		dev_info(priv->dev, "no interrupt support\n");
1016 
1017 	ret = rtl83xx_setup_user_mdio(ds);
1018 	if (ret) {
1019 		dev_err(priv->dev, "could not set up MDIO bus\n");
1020 		return -ENODEV;
1021 	}
1022 
1023 	return 0;
1024 }
1025 
rtl8366_get_tag_protocol(struct dsa_switch * ds,int port,enum dsa_tag_protocol mp)1026 static enum dsa_tag_protocol rtl8366_get_tag_protocol(struct dsa_switch *ds,
1027 						      int port,
1028 						      enum dsa_tag_protocol mp)
1029 {
1030 	/* This switch uses the 4 byte protocol A Realtek DSA tag */
1031 	return DSA_TAG_PROTO_RTL4_A;
1032 }
1033 
rtl8366rb_phylink_get_caps(struct dsa_switch * ds,int port,struct phylink_config * config)1034 static void rtl8366rb_phylink_get_caps(struct dsa_switch *ds, int port,
1035 				       struct phylink_config *config)
1036 {
1037 	unsigned long *interfaces = config->supported_interfaces;
1038 	struct realtek_priv *priv = ds->priv;
1039 
1040 	if (port == priv->cpu_port) {
1041 		__set_bit(PHY_INTERFACE_MODE_MII, interfaces);
1042 		__set_bit(PHY_INTERFACE_MODE_GMII, interfaces);
1043 		/* REVMII only supports 100M FD */
1044 		__set_bit(PHY_INTERFACE_MODE_REVMII, interfaces);
1045 		/* RGMII only supports 1G FD */
1046 		phy_interface_set_rgmii(interfaces);
1047 
1048 		config->mac_capabilities = MAC_1000 | MAC_100 |
1049 					   MAC_SYM_PAUSE;
1050 	} else {
1051 		/* RSGMII port, but we don't have that, and we don't
1052 		 * specify in DT, so phylib uses the default of GMII
1053 		 */
1054 		__set_bit(PHY_INTERFACE_MODE_GMII, interfaces);
1055 		config->mac_capabilities = MAC_1000 | MAC_100 | MAC_10 |
1056 					   MAC_SYM_PAUSE | MAC_ASYM_PAUSE;
1057 	}
1058 }
1059 
1060 static void
rtl8366rb_mac_config(struct phylink_config * config,unsigned int mode,const struct phylink_link_state * state)1061 rtl8366rb_mac_config(struct phylink_config *config, unsigned int mode,
1062 		     const struct phylink_link_state *state)
1063 {
1064 }
1065 
1066 static void
rtl8366rb_mac_link_up(struct phylink_config * config,struct phy_device * phydev,unsigned int mode,phy_interface_t interface,int speed,int duplex,bool tx_pause,bool rx_pause)1067 rtl8366rb_mac_link_up(struct phylink_config *config, struct phy_device *phydev,
1068 		      unsigned int mode, phy_interface_t interface,
1069 		      int speed, int duplex, bool tx_pause, bool rx_pause)
1070 {
1071 	struct dsa_port *dp = dsa_phylink_to_port(config);
1072 	struct realtek_priv *priv = dp->ds->priv;
1073 	int port = dp->index;
1074 	unsigned int val;
1075 	int ret;
1076 
1077 	/* Allow forcing the mode on the fixed CPU port, no autonegotiation.
1078 	 * We assume autonegotiation works on the PHY-facing ports.
1079 	 */
1080 	if (port != priv->cpu_port)
1081 		return;
1082 
1083 	dev_dbg(priv->dev, "MAC link up on CPU port (%d)\n", port);
1084 
1085 	ret = regmap_update_bits(priv->map, RTL8366RB_MAC_FORCE_CTRL_REG,
1086 				 BIT(port), BIT(port));
1087 	if (ret) {
1088 		dev_err(priv->dev, "failed to force CPU port\n");
1089 		return;
1090 	}
1091 
1092 	/* Conjure port config */
1093 	switch (speed) {
1094 	case SPEED_10:
1095 		val = RTL8366RB_PAACR_SPEED_10M;
1096 		break;
1097 	case SPEED_100:
1098 		val = RTL8366RB_PAACR_SPEED_100M;
1099 		break;
1100 	case SPEED_1000:
1101 		val = RTL8366RB_PAACR_SPEED_1000M;
1102 		break;
1103 	default:
1104 		val = RTL8366RB_PAACR_SPEED_1000M;
1105 		break;
1106 	}
1107 
1108 	if (duplex == DUPLEX_FULL)
1109 		val |= RTL8366RB_PAACR_FULL_DUPLEX;
1110 
1111 	if (tx_pause)
1112 		val |=  RTL8366RB_PAACR_TX_PAUSE;
1113 
1114 	if (rx_pause)
1115 		val |= RTL8366RB_PAACR_RX_PAUSE;
1116 
1117 	val |= RTL8366RB_PAACR_LINK_UP;
1118 
1119 	ret = regmap_update_bits(priv->map, RTL8366RB_PAACR2,
1120 				 0xFF00U,
1121 				 val << 8);
1122 	if (ret) {
1123 		dev_err(priv->dev, "failed to set PAACR on CPU port\n");
1124 		return;
1125 	}
1126 
1127 	dev_dbg(priv->dev, "set PAACR to %04x\n", val);
1128 
1129 	/* Enable the CPU port */
1130 	ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port),
1131 				 0);
1132 	if (ret) {
1133 		dev_err(priv->dev, "failed to enable the CPU port\n");
1134 		return;
1135 	}
1136 }
1137 
1138 static void
rtl8366rb_mac_link_down(struct phylink_config * config,unsigned int mode,phy_interface_t interface)1139 rtl8366rb_mac_link_down(struct phylink_config *config, unsigned int mode,
1140 			phy_interface_t interface)
1141 {
1142 	struct dsa_port *dp = dsa_phylink_to_port(config);
1143 	struct realtek_priv *priv = dp->ds->priv;
1144 	int port = dp->index;
1145 	int ret;
1146 
1147 	if (port != priv->cpu_port)
1148 		return;
1149 
1150 	dev_dbg(priv->dev, "MAC link down on CPU port (%d)\n", port);
1151 
1152 	/* Disable the CPU port */
1153 	ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port),
1154 				 BIT(port));
1155 	if (ret) {
1156 		dev_err(priv->dev, "failed to disable the CPU port\n");
1157 		return;
1158 	}
1159 }
1160 
1161 static int
rtl8366rb_port_enable(struct dsa_switch * ds,int port,struct phy_device * phy)1162 rtl8366rb_port_enable(struct dsa_switch *ds, int port,
1163 		      struct phy_device *phy)
1164 {
1165 	struct realtek_priv *priv = ds->priv;
1166 	int ret;
1167 
1168 	dev_dbg(priv->dev, "enable port %d\n", port);
1169 	ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port),
1170 				 0);
1171 	if (ret)
1172 		return ret;
1173 
1174 	return 0;
1175 }
1176 
1177 static void
rtl8366rb_port_disable(struct dsa_switch * ds,int port)1178 rtl8366rb_port_disable(struct dsa_switch *ds, int port)
1179 {
1180 	struct realtek_priv *priv = ds->priv;
1181 	int ret;
1182 
1183 	dev_dbg(priv->dev, "disable port %d\n", port);
1184 	ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port),
1185 				 BIT(port));
1186 	if (ret)
1187 		return;
1188 }
1189 
1190 static int
rtl8366rb_port_bridge_join(struct dsa_switch * ds,int port,struct dsa_bridge bridge,bool * tx_fwd_offload,struct netlink_ext_ack * extack)1191 rtl8366rb_port_bridge_join(struct dsa_switch *ds, int port,
1192 			   struct dsa_bridge bridge,
1193 			   bool *tx_fwd_offload,
1194 			   struct netlink_ext_ack *extack)
1195 {
1196 	struct realtek_priv *priv = ds->priv;
1197 	unsigned int port_bitmap = 0;
1198 	int ret, i;
1199 
1200 	/* Loop over all other ports than the current one */
1201 	for (i = 0; i < RTL8366RB_PORT_NUM_CPU; i++) {
1202 		/* Current port handled last */
1203 		if (i == port)
1204 			continue;
1205 		/* Not on this bridge */
1206 		if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))
1207 			continue;
1208 		/* Join this port to each other port on the bridge */
1209 		ret = regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(i),
1210 					 RTL8366RB_PORT_ISO_PORTS(BIT(port)),
1211 					 RTL8366RB_PORT_ISO_PORTS(BIT(port)));
1212 		if (ret)
1213 			dev_err(priv->dev, "failed to join port %d\n", port);
1214 
1215 		port_bitmap |= BIT(i);
1216 	}
1217 
1218 	/* Set the bits for the ports we can access */
1219 	return regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(port),
1220 				  RTL8366RB_PORT_ISO_PORTS(port_bitmap),
1221 				  RTL8366RB_PORT_ISO_PORTS(port_bitmap));
1222 }
1223 
1224 static void
rtl8366rb_port_bridge_leave(struct dsa_switch * ds,int port,struct dsa_bridge bridge)1225 rtl8366rb_port_bridge_leave(struct dsa_switch *ds, int port,
1226 			    struct dsa_bridge bridge)
1227 {
1228 	struct realtek_priv *priv = ds->priv;
1229 	unsigned int port_bitmap = 0;
1230 	int ret, i;
1231 
1232 	/* Loop over all other ports than this one */
1233 	for (i = 0; i < RTL8366RB_PORT_NUM_CPU; i++) {
1234 		/* Current port handled last */
1235 		if (i == port)
1236 			continue;
1237 		/* Not on this bridge */
1238 		if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))
1239 			continue;
1240 		/* Remove this port from any other port on the bridge */
1241 		ret = regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(i),
1242 					 RTL8366RB_PORT_ISO_PORTS(BIT(port)), 0);
1243 		if (ret)
1244 			dev_err(priv->dev, "failed to leave port %d\n", port);
1245 
1246 		port_bitmap |= BIT(i);
1247 	}
1248 
1249 	/* Clear the bits for the ports we can not access, leave ourselves */
1250 	regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(port),
1251 			   RTL8366RB_PORT_ISO_PORTS(port_bitmap), 0);
1252 }
1253 
1254 /**
1255  * rtl8366rb_drop_untagged() - make the switch drop untagged and C-tagged frames
1256  * @priv: SMI state container
1257  * @port: the port to drop untagged and C-tagged frames on
1258  * @drop: whether to drop or pass untagged and C-tagged frames
1259  *
1260  * Return: zero for success, a negative number on error.
1261  */
rtl8366rb_drop_untagged(struct realtek_priv * priv,int port,bool drop)1262 static int rtl8366rb_drop_untagged(struct realtek_priv *priv, int port, bool drop)
1263 {
1264 	return regmap_update_bits(priv->map, RTL8366RB_VLAN_INGRESS_CTRL1_REG,
1265 				  RTL8366RB_VLAN_INGRESS_CTRL1_DROP(port),
1266 				  drop ? RTL8366RB_VLAN_INGRESS_CTRL1_DROP(port) : 0);
1267 }
1268 
rtl8366rb_vlan_filtering(struct dsa_switch * ds,int port,bool vlan_filtering,struct netlink_ext_ack * extack)1269 static int rtl8366rb_vlan_filtering(struct dsa_switch *ds, int port,
1270 				    bool vlan_filtering,
1271 				    struct netlink_ext_ack *extack)
1272 {
1273 	struct realtek_priv *priv = ds->priv;
1274 	struct rtl8366rb *rb;
1275 	int ret;
1276 
1277 	rb = priv->chip_data;
1278 
1279 	dev_dbg(priv->dev, "port %d: %s VLAN filtering\n", port,
1280 		str_enable_disable(vlan_filtering));
1281 
1282 	/* If the port is not in the member set, the frame will be dropped */
1283 	ret = regmap_update_bits(priv->map, RTL8366RB_VLAN_INGRESS_CTRL2_REG,
1284 				 BIT(port), vlan_filtering ? BIT(port) : 0);
1285 	if (ret)
1286 		return ret;
1287 
1288 	/* If VLAN filtering is enabled and PVID is also enabled, we must
1289 	 * not drop any untagged or C-tagged frames. If we turn off VLAN
1290 	 * filtering on a port, we need to accept any frames.
1291 	 */
1292 	if (vlan_filtering)
1293 		ret = rtl8366rb_drop_untagged(priv, port, !rb->pvid_enabled[port]);
1294 	else
1295 		ret = rtl8366rb_drop_untagged(priv, port, false);
1296 
1297 	return ret;
1298 }
1299 
1300 static int
rtl8366rb_port_pre_bridge_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)1301 rtl8366rb_port_pre_bridge_flags(struct dsa_switch *ds, int port,
1302 				struct switchdev_brport_flags flags,
1303 				struct netlink_ext_ack *extack)
1304 {
1305 	/* We support enabling/disabling learning */
1306 	if (flags.mask & ~(BR_LEARNING))
1307 		return -EINVAL;
1308 
1309 	return 0;
1310 }
1311 
1312 static int
rtl8366rb_port_bridge_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)1313 rtl8366rb_port_bridge_flags(struct dsa_switch *ds, int port,
1314 			    struct switchdev_brport_flags flags,
1315 			    struct netlink_ext_ack *extack)
1316 {
1317 	struct realtek_priv *priv = ds->priv;
1318 	int ret;
1319 
1320 	if (flags.mask & BR_LEARNING) {
1321 		ret = regmap_update_bits(priv->map, RTL8366RB_PORT_LEARNDIS_CTRL,
1322 					 BIT(port),
1323 					 (flags.val & BR_LEARNING) ? 0 : BIT(port));
1324 		if (ret)
1325 			return ret;
1326 	}
1327 
1328 	return 0;
1329 }
1330 
1331 static void
rtl8366rb_port_stp_state_set(struct dsa_switch * ds,int port,u8 state)1332 rtl8366rb_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1333 {
1334 	struct realtek_priv *priv = ds->priv;
1335 	u32 val;
1336 	int i;
1337 
1338 	switch (state) {
1339 	case BR_STATE_DISABLED:
1340 		val = RTL8366RB_STP_STATE_DISABLED;
1341 		break;
1342 	case BR_STATE_BLOCKING:
1343 	case BR_STATE_LISTENING:
1344 		val = RTL8366RB_STP_STATE_BLOCKING;
1345 		break;
1346 	case BR_STATE_LEARNING:
1347 		val = RTL8366RB_STP_STATE_LEARNING;
1348 		break;
1349 	case BR_STATE_FORWARDING:
1350 		val = RTL8366RB_STP_STATE_FORWARDING;
1351 		break;
1352 	default:
1353 		dev_err(priv->dev, "unknown bridge state requested\n");
1354 		return;
1355 	}
1356 
1357 	/* Set the same status for the port on all the FIDs */
1358 	for (i = 0; i < RTL8366RB_NUM_FIDS; i++) {
1359 		regmap_update_bits(priv->map, RTL8366RB_STP_STATE_BASE + i,
1360 				   RTL8366RB_STP_STATE_MASK(port),
1361 				   RTL8366RB_STP_STATE(port, val));
1362 	}
1363 }
1364 
1365 static void
rtl8366rb_port_fast_age(struct dsa_switch * ds,int port)1366 rtl8366rb_port_fast_age(struct dsa_switch *ds, int port)
1367 {
1368 	struct realtek_priv *priv = ds->priv;
1369 
1370 	/* This will age out any learned L2 entries */
1371 	regmap_update_bits(priv->map, RTL8366RB_SECURITY_CTRL,
1372 			   BIT(port), BIT(port));
1373 	/* Restore the normal state of things */
1374 	regmap_update_bits(priv->map, RTL8366RB_SECURITY_CTRL,
1375 			   BIT(port), 0);
1376 }
1377 
rtl8366rb_change_mtu(struct dsa_switch * ds,int port,int new_mtu)1378 static int rtl8366rb_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
1379 {
1380 	struct realtek_priv *priv = ds->priv;
1381 	struct rtl8366rb *rb;
1382 	unsigned int max_mtu;
1383 	u32 len;
1384 	int i;
1385 
1386 	/* Cache the per-port MTU setting */
1387 	rb = priv->chip_data;
1388 	rb->max_mtu[port] = new_mtu;
1389 
1390 	/* Roof out the MTU for the entire switch to the greatest
1391 	 * common denominator: the biggest set for any one port will
1392 	 * be the biggest MTU for the switch.
1393 	 */
1394 	max_mtu = ETH_DATA_LEN;
1395 	for (i = 0; i < RTL8366RB_NUM_PORTS; i++) {
1396 		if (rb->max_mtu[i] > max_mtu)
1397 			max_mtu = rb->max_mtu[i];
1398 	}
1399 
1400 	/* Translate to layer 2 size.
1401 	 * Add ethernet and (possible) VLAN headers, and checksum to the size.
1402 	 * For ETH_DATA_LEN (1500 bytes) this will add up to 1522 bytes.
1403 	 */
1404 	max_mtu += VLAN_ETH_HLEN;
1405 	max_mtu += ETH_FCS_LEN;
1406 
1407 	if (max_mtu <= 1522)
1408 		len = RTL8366RB_SGCR_MAX_LENGTH_1522;
1409 	else if (max_mtu > 1522 && max_mtu <= 1536)
1410 		/* This will be the most common default if using VLAN and
1411 		 * CPU tagging on a port as both VLAN and CPU tag will
1412 		 * result in 1518 + 4 + 4 = 1526 bytes.
1413 		 */
1414 		len = RTL8366RB_SGCR_MAX_LENGTH_1536;
1415 	else if (max_mtu > 1536 && max_mtu <= 1552)
1416 		len = RTL8366RB_SGCR_MAX_LENGTH_1552;
1417 	else
1418 		len = RTL8366RB_SGCR_MAX_LENGTH_16000;
1419 
1420 	return regmap_update_bits(priv->map, RTL8366RB_SGCR,
1421 				  RTL8366RB_SGCR_MAX_LENGTH_MASK,
1422 				  len);
1423 }
1424 
rtl8366rb_max_mtu(struct dsa_switch * ds,int port)1425 static int rtl8366rb_max_mtu(struct dsa_switch *ds, int port)
1426 {
1427 	/* The max MTU is 16000 bytes, so we subtract the ethernet
1428 	 * headers with VLAN and checksum and arrive at
1429 	 * 16000 - 18 - 4 = 15978. This does not include the CPU tag
1430 	 * since that is added to the requested MTU by the DSA framework.
1431 	 */
1432 	return 16000 - VLAN_ETH_HLEN - ETH_FCS_LEN;
1433 }
1434 
rtl8366rb_get_vlan_4k(struct realtek_priv * priv,u32 vid,struct rtl8366_vlan_4k * vlan4k)1435 static int rtl8366rb_get_vlan_4k(struct realtek_priv *priv, u32 vid,
1436 				 struct rtl8366_vlan_4k *vlan4k)
1437 {
1438 	u32 data[3];
1439 	int ret;
1440 	int i;
1441 
1442 	memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
1443 
1444 	if (vid >= RTL8366RB_NUM_VIDS)
1445 		return -EINVAL;
1446 
1447 	/* write VID */
1448 	ret = regmap_write(priv->map, RTL8366RB_VLAN_TABLE_WRITE_BASE,
1449 			   vid & RTL8366RB_VLAN_VID_MASK);
1450 	if (ret)
1451 		return ret;
1452 
1453 	/* write table access control word */
1454 	ret = regmap_write(priv->map, RTL8366RB_TABLE_ACCESS_CTRL_REG,
1455 			   RTL8366RB_TABLE_VLAN_READ_CTRL);
1456 	if (ret)
1457 		return ret;
1458 
1459 	for (i = 0; i < 3; i++) {
1460 		ret = regmap_read(priv->map,
1461 				  RTL8366RB_VLAN_TABLE_READ_BASE + i,
1462 				  &data[i]);
1463 		if (ret)
1464 			return ret;
1465 	}
1466 
1467 	vlan4k->vid = vid;
1468 	vlan4k->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
1469 			RTL8366RB_VLAN_UNTAG_MASK;
1470 	vlan4k->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
1471 	vlan4k->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
1472 
1473 	return 0;
1474 }
1475 
rtl8366rb_set_vlan_4k(struct realtek_priv * priv,const struct rtl8366_vlan_4k * vlan4k)1476 static int rtl8366rb_set_vlan_4k(struct realtek_priv *priv,
1477 				 const struct rtl8366_vlan_4k *vlan4k)
1478 {
1479 	u32 data[3];
1480 	int ret;
1481 	int i;
1482 
1483 	if (vlan4k->vid >= RTL8366RB_NUM_VIDS ||
1484 	    vlan4k->member > RTL8366RB_VLAN_MEMBER_MASK ||
1485 	    vlan4k->untag > RTL8366RB_VLAN_UNTAG_MASK ||
1486 	    vlan4k->fid > RTL8366RB_FIDMAX)
1487 		return -EINVAL;
1488 
1489 	data[0] = vlan4k->vid & RTL8366RB_VLAN_VID_MASK;
1490 	data[1] = (vlan4k->member & RTL8366RB_VLAN_MEMBER_MASK) |
1491 		  ((vlan4k->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
1492 			RTL8366RB_VLAN_UNTAG_SHIFT);
1493 	data[2] = vlan4k->fid & RTL8366RB_VLAN_FID_MASK;
1494 
1495 	for (i = 0; i < 3; i++) {
1496 		ret = regmap_write(priv->map,
1497 				   RTL8366RB_VLAN_TABLE_WRITE_BASE + i,
1498 				   data[i]);
1499 		if (ret)
1500 			return ret;
1501 	}
1502 
1503 	/* write table access control word */
1504 	ret = regmap_write(priv->map, RTL8366RB_TABLE_ACCESS_CTRL_REG,
1505 			   RTL8366RB_TABLE_VLAN_WRITE_CTRL);
1506 
1507 	return ret;
1508 }
1509 
rtl8366rb_get_vlan_mc(struct realtek_priv * priv,u32 index,struct rtl8366_vlan_mc * vlanmc)1510 static int rtl8366rb_get_vlan_mc(struct realtek_priv *priv, u32 index,
1511 				 struct rtl8366_vlan_mc *vlanmc)
1512 {
1513 	u32 data[3];
1514 	int ret;
1515 	int i;
1516 
1517 	memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
1518 
1519 	if (index >= RTL8366RB_NUM_VLANS)
1520 		return -EINVAL;
1521 
1522 	for (i = 0; i < 3; i++) {
1523 		ret = regmap_read(priv->map,
1524 				  RTL8366RB_VLAN_MC_BASE(index) + i,
1525 				  &data[i]);
1526 		if (ret)
1527 			return ret;
1528 	}
1529 
1530 	vlanmc->vid = data[0] & RTL8366RB_VLAN_VID_MASK;
1531 	vlanmc->priority = (data[0] >> RTL8366RB_VLAN_PRIORITY_SHIFT) &
1532 		RTL8366RB_VLAN_PRIORITY_MASK;
1533 	vlanmc->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
1534 		RTL8366RB_VLAN_UNTAG_MASK;
1535 	vlanmc->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
1536 	vlanmc->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
1537 
1538 	return 0;
1539 }
1540 
rtl8366rb_set_vlan_mc(struct realtek_priv * priv,u32 index,const struct rtl8366_vlan_mc * vlanmc)1541 static int rtl8366rb_set_vlan_mc(struct realtek_priv *priv, u32 index,
1542 				 const struct rtl8366_vlan_mc *vlanmc)
1543 {
1544 	u32 data[3];
1545 	int ret;
1546 	int i;
1547 
1548 	if (index >= RTL8366RB_NUM_VLANS ||
1549 	    vlanmc->vid >= RTL8366RB_NUM_VIDS ||
1550 	    vlanmc->priority > RTL8366RB_PRIORITYMAX ||
1551 	    vlanmc->member > RTL8366RB_VLAN_MEMBER_MASK ||
1552 	    vlanmc->untag > RTL8366RB_VLAN_UNTAG_MASK ||
1553 	    vlanmc->fid > RTL8366RB_FIDMAX)
1554 		return -EINVAL;
1555 
1556 	data[0] = (vlanmc->vid & RTL8366RB_VLAN_VID_MASK) |
1557 		  ((vlanmc->priority & RTL8366RB_VLAN_PRIORITY_MASK) <<
1558 			RTL8366RB_VLAN_PRIORITY_SHIFT);
1559 	data[1] = (vlanmc->member & RTL8366RB_VLAN_MEMBER_MASK) |
1560 		  ((vlanmc->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
1561 			RTL8366RB_VLAN_UNTAG_SHIFT);
1562 	data[2] = vlanmc->fid & RTL8366RB_VLAN_FID_MASK;
1563 
1564 	for (i = 0; i < 3; i++) {
1565 		ret = regmap_write(priv->map,
1566 				   RTL8366RB_VLAN_MC_BASE(index) + i,
1567 				   data[i]);
1568 		if (ret)
1569 			return ret;
1570 	}
1571 
1572 	return 0;
1573 }
1574 
rtl8366rb_get_mc_index(struct realtek_priv * priv,int port,int * val)1575 static int rtl8366rb_get_mc_index(struct realtek_priv *priv, int port, int *val)
1576 {
1577 	u32 data;
1578 	int ret;
1579 
1580 	if (port >= priv->num_ports)
1581 		return -EINVAL;
1582 
1583 	ret = regmap_read(priv->map, RTL8366RB_PORT_VLAN_CTRL_REG(port),
1584 			  &data);
1585 	if (ret)
1586 		return ret;
1587 
1588 	*val = (data >> RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)) &
1589 		RTL8366RB_PORT_VLAN_CTRL_MASK;
1590 
1591 	return 0;
1592 }
1593 
rtl8366rb_set_mc_index(struct realtek_priv * priv,int port,int index)1594 static int rtl8366rb_set_mc_index(struct realtek_priv *priv, int port, int index)
1595 {
1596 	struct dsa_switch *ds = &priv->ds;
1597 	struct rtl8366rb *rb;
1598 	bool pvid_enabled;
1599 	int ret;
1600 
1601 	rb = priv->chip_data;
1602 	pvid_enabled = !!index;
1603 
1604 	if (port >= priv->num_ports || index >= RTL8366RB_NUM_VLANS)
1605 		return -EINVAL;
1606 
1607 	ret = regmap_update_bits(priv->map, RTL8366RB_PORT_VLAN_CTRL_REG(port),
1608 				 RTL8366RB_PORT_VLAN_CTRL_MASK <<
1609 					RTL8366RB_PORT_VLAN_CTRL_SHIFT(port),
1610 				 (index & RTL8366RB_PORT_VLAN_CTRL_MASK) <<
1611 					RTL8366RB_PORT_VLAN_CTRL_SHIFT(port));
1612 	if (ret)
1613 		return ret;
1614 
1615 	rb->pvid_enabled[port] = pvid_enabled;
1616 
1617 	/* If VLAN filtering is enabled and PVID is also enabled, we must
1618 	 * not drop any untagged or C-tagged frames. Make sure to update the
1619 	 * filtering setting.
1620 	 */
1621 	if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))
1622 		ret = rtl8366rb_drop_untagged(priv, port, !pvid_enabled);
1623 
1624 	return ret;
1625 }
1626 
rtl8366rb_is_vlan_valid(struct realtek_priv * priv,unsigned int vlan)1627 static bool rtl8366rb_is_vlan_valid(struct realtek_priv *priv, unsigned int vlan)
1628 {
1629 	unsigned int max = RTL8366RB_NUM_VLANS - 1;
1630 
1631 	if (priv->vlan4k_enabled)
1632 		max = RTL8366RB_NUM_VIDS - 1;
1633 
1634 	if (vlan > max)
1635 		return false;
1636 
1637 	return true;
1638 }
1639 
rtl8366rb_enable_vlan(struct realtek_priv * priv,bool enable)1640 static int rtl8366rb_enable_vlan(struct realtek_priv *priv, bool enable)
1641 {
1642 	dev_dbg(priv->dev, "%s VLAN\n", str_enable_disable(enable));
1643 	return regmap_update_bits(priv->map,
1644 				  RTL8366RB_SGCR, RTL8366RB_SGCR_EN_VLAN,
1645 				  enable ? RTL8366RB_SGCR_EN_VLAN : 0);
1646 }
1647 
rtl8366rb_enable_vlan4k(struct realtek_priv * priv,bool enable)1648 static int rtl8366rb_enable_vlan4k(struct realtek_priv *priv, bool enable)
1649 {
1650 	dev_dbg(priv->dev, "%s VLAN 4k\n", str_enable_disable(enable));
1651 	return regmap_update_bits(priv->map, RTL8366RB_SGCR,
1652 				  RTL8366RB_SGCR_EN_VLAN_4KTB,
1653 				  enable ? RTL8366RB_SGCR_EN_VLAN_4KTB : 0);
1654 }
1655 
rtl8366rb_phy_read(struct realtek_priv * priv,int phy,int regnum)1656 static int rtl8366rb_phy_read(struct realtek_priv *priv, int phy, int regnum)
1657 {
1658 	u32 val;
1659 	u32 reg;
1660 	int ret;
1661 
1662 	if (phy > RTL8366RB_PHY_NO_MAX)
1663 		return -EINVAL;
1664 
1665 	rtl83xx_lock(priv);
1666 
1667 	ret = regmap_write(priv->map_nolock, RTL8366RB_PHY_ACCESS_CTRL_REG,
1668 			   RTL8366RB_PHY_CTRL_READ);
1669 	if (ret)
1670 		goto out;
1671 
1672 	reg = 0x8000 | (1 << (phy + RTL8366RB_PHY_NO_OFFSET)) | regnum;
1673 
1674 	ret = regmap_write(priv->map_nolock, reg, 0);
1675 	if (ret) {
1676 		dev_err(priv->dev,
1677 			"failed to write PHY%d reg %04x @ %04x, ret %d\n",
1678 			phy, regnum, reg, ret);
1679 		goto out;
1680 	}
1681 
1682 	ret = regmap_read(priv->map_nolock, RTL8366RB_PHY_ACCESS_DATA_REG,
1683 			  &val);
1684 	if (ret)
1685 		goto out;
1686 
1687 	ret = val;
1688 
1689 	dev_dbg(priv->dev, "read PHY%d register 0x%04x @ %08x, val <- %04x\n",
1690 		phy, regnum, reg, val);
1691 
1692 out:
1693 	rtl83xx_unlock(priv);
1694 
1695 	return ret;
1696 }
1697 
rtl8366rb_phy_write(struct realtek_priv * priv,int phy,int regnum,u16 val)1698 static int rtl8366rb_phy_write(struct realtek_priv *priv, int phy, int regnum,
1699 			       u16 val)
1700 {
1701 	u32 reg;
1702 	int ret;
1703 
1704 	if (phy > RTL8366RB_PHY_NO_MAX)
1705 		return -EINVAL;
1706 
1707 	rtl83xx_lock(priv);
1708 
1709 	ret = regmap_write(priv->map_nolock, RTL8366RB_PHY_ACCESS_CTRL_REG,
1710 			   RTL8366RB_PHY_CTRL_WRITE);
1711 	if (ret)
1712 		goto out;
1713 
1714 	reg = 0x8000 | (1 << (phy + RTL8366RB_PHY_NO_OFFSET)) | regnum;
1715 
1716 	dev_dbg(priv->dev, "write PHY%d register 0x%04x @ %04x, val -> %04x\n",
1717 		phy, regnum, reg, val);
1718 
1719 	ret = regmap_write(priv->map_nolock, reg, val);
1720 	if (ret)
1721 		goto out;
1722 
1723 out:
1724 	rtl83xx_unlock(priv);
1725 
1726 	return ret;
1727 }
1728 
rtl8366rb_reset_chip(struct realtek_priv * priv)1729 static int rtl8366rb_reset_chip(struct realtek_priv *priv)
1730 {
1731 	int timeout = 10;
1732 	u32 val;
1733 	int ret;
1734 
1735 	priv->write_reg_noack(priv, RTL8366RB_RESET_CTRL_REG,
1736 			      RTL8366RB_CHIP_CTRL_RESET_HW);
1737 	do {
1738 		usleep_range(20000, 25000);
1739 		ret = regmap_read(priv->map, RTL8366RB_RESET_CTRL_REG, &val);
1740 		if (ret)
1741 			return ret;
1742 
1743 		if (!(val & RTL8366RB_CHIP_CTRL_RESET_HW))
1744 			break;
1745 	} while (--timeout);
1746 
1747 	if (!timeout) {
1748 		dev_err(priv->dev, "timeout waiting for the switch to reset\n");
1749 		return -EIO;
1750 	}
1751 
1752 	return 0;
1753 }
1754 
rtl8366rb_detect(struct realtek_priv * priv)1755 static int rtl8366rb_detect(struct realtek_priv *priv)
1756 {
1757 	struct device *dev = priv->dev;
1758 	int ret;
1759 	u32 val;
1760 
1761 	/* Detect device */
1762 	ret = regmap_read(priv->map, 0x5c, &val);
1763 	if (ret) {
1764 		dev_err(dev, "can't get chip ID (%d)\n", ret);
1765 		return ret;
1766 	}
1767 
1768 	switch (val) {
1769 	case 0x6027:
1770 		dev_info(dev, "found an RTL8366S switch\n");
1771 		dev_err(dev, "this switch is not yet supported, submit patches!\n");
1772 		return -ENODEV;
1773 	case 0x5937:
1774 		dev_info(dev, "found an RTL8366RB switch\n");
1775 		priv->cpu_port = RTL8366RB_PORT_NUM_CPU;
1776 		priv->num_ports = RTL8366RB_NUM_PORTS;
1777 		priv->num_vlan_mc = RTL8366RB_NUM_VLANS;
1778 		priv->mib_counters = rtl8366rb_mib_counters;
1779 		priv->num_mib_counters = ARRAY_SIZE(rtl8366rb_mib_counters);
1780 		break;
1781 	default:
1782 		dev_info(dev, "found an Unknown Realtek switch (id=0x%04x)\n",
1783 			 val);
1784 		break;
1785 	}
1786 
1787 	ret = rtl8366rb_reset_chip(priv);
1788 	if (ret)
1789 		return ret;
1790 
1791 	return 0;
1792 }
1793 
1794 static const struct phylink_mac_ops rtl8366rb_phylink_mac_ops = {
1795 	.mac_config = rtl8366rb_mac_config,
1796 	.mac_link_down = rtl8366rb_mac_link_down,
1797 	.mac_link_up = rtl8366rb_mac_link_up,
1798 };
1799 
1800 static const struct dsa_switch_ops rtl8366rb_switch_ops = {
1801 	.get_tag_protocol = rtl8366_get_tag_protocol,
1802 	.setup = rtl8366rb_setup,
1803 	.phylink_get_caps = rtl8366rb_phylink_get_caps,
1804 	.get_strings = rtl8366_get_strings,
1805 	.get_ethtool_stats = rtl8366_get_ethtool_stats,
1806 	.get_sset_count = rtl8366_get_sset_count,
1807 	.port_bridge_join = rtl8366rb_port_bridge_join,
1808 	.port_bridge_leave = rtl8366rb_port_bridge_leave,
1809 	.port_vlan_filtering = rtl8366rb_vlan_filtering,
1810 	.port_vlan_add = rtl8366_vlan_add,
1811 	.port_vlan_del = rtl8366_vlan_del,
1812 	.port_enable = rtl8366rb_port_enable,
1813 	.port_disable = rtl8366rb_port_disable,
1814 	.port_pre_bridge_flags = rtl8366rb_port_pre_bridge_flags,
1815 	.port_bridge_flags = rtl8366rb_port_bridge_flags,
1816 	.port_stp_state_set = rtl8366rb_port_stp_state_set,
1817 	.port_fast_age = rtl8366rb_port_fast_age,
1818 	.port_change_mtu = rtl8366rb_change_mtu,
1819 	.port_max_mtu = rtl8366rb_max_mtu,
1820 };
1821 
1822 static const struct realtek_ops rtl8366rb_ops = {
1823 	.detect		= rtl8366rb_detect,
1824 	.get_vlan_mc	= rtl8366rb_get_vlan_mc,
1825 	.set_vlan_mc	= rtl8366rb_set_vlan_mc,
1826 	.get_vlan_4k	= rtl8366rb_get_vlan_4k,
1827 	.set_vlan_4k	= rtl8366rb_set_vlan_4k,
1828 	.get_mc_index	= rtl8366rb_get_mc_index,
1829 	.set_mc_index	= rtl8366rb_set_mc_index,
1830 	.get_mib_counter = rtl8366rb_get_mib_counter,
1831 	.is_vlan_valid	= rtl8366rb_is_vlan_valid,
1832 	.enable_vlan	= rtl8366rb_enable_vlan,
1833 	.enable_vlan4k	= rtl8366rb_enable_vlan4k,
1834 	.phy_read	= rtl8366rb_phy_read,
1835 	.phy_write	= rtl8366rb_phy_write,
1836 };
1837 
1838 const struct realtek_variant rtl8366rb_variant = {
1839 	.ds_ops = &rtl8366rb_switch_ops,
1840 	.ops = &rtl8366rb_ops,
1841 	.phylink_mac_ops = &rtl8366rb_phylink_mac_ops,
1842 	.clk_delay = 10,
1843 	.cmd_read = 0xa9,
1844 	.cmd_write = 0xa8,
1845 	.chip_data_sz = sizeof(struct rtl8366rb),
1846 };
1847 
1848 static const struct of_device_id rtl8366rb_of_match[] = {
1849 	{ .compatible = "realtek,rtl8366rb", .data = &rtl8366rb_variant, },
1850 	{ /* sentinel */ },
1851 };
1852 MODULE_DEVICE_TABLE(of, rtl8366rb_of_match);
1853 
1854 static struct platform_driver rtl8366rb_smi_driver = {
1855 	.driver = {
1856 		.name = "rtl8366rb-smi",
1857 		.of_match_table = rtl8366rb_of_match,
1858 	},
1859 	.probe  = realtek_smi_probe,
1860 	.remove = realtek_smi_remove,
1861 	.shutdown = realtek_smi_shutdown,
1862 };
1863 
1864 static struct mdio_driver rtl8366rb_mdio_driver = {
1865 	.mdiodrv.driver = {
1866 		.name = "rtl8366rb-mdio",
1867 		.of_match_table = rtl8366rb_of_match,
1868 	},
1869 	.probe  = realtek_mdio_probe,
1870 	.remove = realtek_mdio_remove,
1871 	.shutdown = realtek_mdio_shutdown,
1872 };
1873 
rtl8366rb_init(void)1874 static int rtl8366rb_init(void)
1875 {
1876 	int ret;
1877 
1878 	ret = realtek_mdio_driver_register(&rtl8366rb_mdio_driver);
1879 	if (ret)
1880 		return ret;
1881 
1882 	ret = realtek_smi_driver_register(&rtl8366rb_smi_driver);
1883 	if (ret) {
1884 		realtek_mdio_driver_unregister(&rtl8366rb_mdio_driver);
1885 		return ret;
1886 	}
1887 
1888 	return 0;
1889 }
1890 module_init(rtl8366rb_init);
1891 
rtl8366rb_exit(void)1892 static void __exit rtl8366rb_exit(void)
1893 {
1894 	realtek_smi_driver_unregister(&rtl8366rb_smi_driver);
1895 	realtek_mdio_driver_unregister(&rtl8366rb_mdio_driver);
1896 }
1897 module_exit(rtl8366rb_exit);
1898 
1899 MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
1900 MODULE_DESCRIPTION("Driver for RTL8366RB ethernet switch");
1901 MODULE_LICENSE("GPL");
1902 MODULE_IMPORT_NS("REALTEK_DSA");
1903