xref: /linux/drivers/rtc/rtc-snvs.c (revision 7ae9fb1b7ecbb5d85d07857943f677fd1a559b18)
1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // Copyright (C) 2011-2012 Freescale Semiconductor, Inc.
4 
5 #include <linux/init.h>
6 #include <linux/io.h>
7 #include <linux/kernel.h>
8 #include <linux/module.h>
9 #include <linux/of.h>
10 #include <linux/platform_device.h>
11 #include <linux/pm_wakeirq.h>
12 #include <linux/rtc.h>
13 #include <linux/clk.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/regmap.h>
16 
17 #define SNVS_LPREGISTER_OFFSET	0x34
18 
19 /* These register offsets are relative to LP (Low Power) range */
20 #define SNVS_LPCR		0x04
21 #define SNVS_LPSR		0x18
22 #define SNVS_LPSRTCMR		0x1c
23 #define SNVS_LPSRTCLR		0x20
24 #define SNVS_LPTAR		0x24
25 #define SNVS_LPPGDR		0x30
26 
27 #define SNVS_LPCR_SRTC_ENV	(1 << 0)
28 #define SNVS_LPCR_LPTA_EN	(1 << 1)
29 #define SNVS_LPCR_LPWUI_EN	(1 << 3)
30 #define SNVS_LPSR_LPTA		(1 << 0)
31 
32 #define SNVS_LPPGDR_INIT	0x41736166
33 #define CNTR_TO_SECS_SH		15
34 
35 /* The maximum RTC clock cycles that are allowed to pass between two
36  * consecutive clock counter register reads. If the values are corrupted a
37  * bigger difference is expected. The RTC frequency is 32kHz. With 320 cycles
38  * we end at 10ms which should be enough for most cases. If it once takes
39  * longer than expected we do a retry.
40  */
41 #define MAX_RTC_READ_DIFF_CYCLES	320
42 
43 struct snvs_rtc_data {
44 	struct rtc_device *rtc;
45 	struct regmap *regmap;
46 	int offset;
47 	int irq;
48 	struct clk *clk;
49 };
50 
51 /* Read 64 bit timer register, which could be in inconsistent state */
rtc_read_lpsrt(struct snvs_rtc_data * data)52 static u64 rtc_read_lpsrt(struct snvs_rtc_data *data)
53 {
54 	u32 msb, lsb;
55 
56 	regmap_read(data->regmap, data->offset + SNVS_LPSRTCMR, &msb);
57 	regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &lsb);
58 	return (u64)msb << 32 | lsb;
59 }
60 
61 /* Read the secure real time counter, taking care to deal with the cases of the
62  * counter updating while being read.
63  */
rtc_read_lp_counter(struct snvs_rtc_data * data)64 static u32 rtc_read_lp_counter(struct snvs_rtc_data *data)
65 {
66 	u64 read1, read2;
67 	s64 diff;
68 	unsigned int timeout = 100;
69 
70 	/* As expected, the registers might update between the read of the LSB
71 	 * reg and the MSB reg.  It's also possible that one register might be
72 	 * in partially modified state as well.
73 	 */
74 	read1 = rtc_read_lpsrt(data);
75 	do {
76 		read2 = read1;
77 		read1 = rtc_read_lpsrt(data);
78 		diff = read1 - read2;
79 	} while (((diff < 0) || (diff > MAX_RTC_READ_DIFF_CYCLES)) && --timeout);
80 	if (!timeout)
81 		dev_err(&data->rtc->dev, "Timeout trying to get valid LPSRT Counter read\n");
82 
83 	/* Convert 47-bit counter to 32-bit raw second count */
84 	return (u32) (read1 >> CNTR_TO_SECS_SH);
85 }
86 
87 /* Just read the lsb from the counter, dealing with inconsistent state */
rtc_read_lp_counter_lsb(struct snvs_rtc_data * data,u32 * lsb)88 static int rtc_read_lp_counter_lsb(struct snvs_rtc_data *data, u32 *lsb)
89 {
90 	u32 count1, count2;
91 	s32 diff;
92 	unsigned int timeout = 100;
93 
94 	regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1);
95 	do {
96 		count2 = count1;
97 		regmap_read(data->regmap, data->offset + SNVS_LPSRTCLR, &count1);
98 		diff = count1 - count2;
99 	} while (((diff < 0) || (diff > MAX_RTC_READ_DIFF_CYCLES)) && --timeout);
100 	if (!timeout) {
101 		dev_err(&data->rtc->dev, "Timeout trying to get valid LPSRT Counter read\n");
102 		return -ETIMEDOUT;
103 	}
104 
105 	*lsb = count1;
106 	return 0;
107 }
108 
rtc_write_sync_lp(struct snvs_rtc_data * data)109 static int rtc_write_sync_lp(struct snvs_rtc_data *data)
110 {
111 	u32 count1, count2;
112 	u32 elapsed;
113 	unsigned int timeout = 1000;
114 	int ret;
115 
116 	ret = rtc_read_lp_counter_lsb(data, &count1);
117 	if (ret)
118 		return ret;
119 
120 	/* Wait for 3 CKIL cycles, about 61.0-91.5 µs */
121 	do {
122 		ret = rtc_read_lp_counter_lsb(data, &count2);
123 		if (ret)
124 			return ret;
125 		elapsed = count2 - count1; /* wrap around _is_ handled! */
126 	} while (elapsed < 3 && --timeout);
127 	if (!timeout) {
128 		dev_err(&data->rtc->dev, "Timeout waiting for LPSRT Counter to change\n");
129 		return -ETIMEDOUT;
130 	}
131 	return 0;
132 }
133 
snvs_rtc_enable(struct snvs_rtc_data * data,bool enable)134 static int snvs_rtc_enable(struct snvs_rtc_data *data, bool enable)
135 {
136 	int timeout = 1000;
137 	u32 lpcr;
138 
139 	regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_SRTC_ENV,
140 			   enable ? SNVS_LPCR_SRTC_ENV : 0);
141 
142 	while (--timeout) {
143 		regmap_read(data->regmap, data->offset + SNVS_LPCR, &lpcr);
144 
145 		if (enable) {
146 			if (lpcr & SNVS_LPCR_SRTC_ENV)
147 				break;
148 		} else {
149 			if (!(lpcr & SNVS_LPCR_SRTC_ENV))
150 				break;
151 		}
152 	}
153 
154 	if (!timeout)
155 		return -ETIMEDOUT;
156 
157 	return 0;
158 }
159 
snvs_rtc_read_time(struct device * dev,struct rtc_time * tm)160 static int snvs_rtc_read_time(struct device *dev, struct rtc_time *tm)
161 {
162 	struct snvs_rtc_data *data = dev_get_drvdata(dev);
163 	unsigned long time;
164 	int ret;
165 
166 	ret = clk_enable(data->clk);
167 	if (ret)
168 		return ret;
169 
170 	time = rtc_read_lp_counter(data);
171 	rtc_time64_to_tm(time, tm);
172 
173 	clk_disable(data->clk);
174 
175 	return 0;
176 }
177 
snvs_rtc_set_time(struct device * dev,struct rtc_time * tm)178 static int snvs_rtc_set_time(struct device *dev, struct rtc_time *tm)
179 {
180 	struct snvs_rtc_data *data = dev_get_drvdata(dev);
181 	unsigned long time = rtc_tm_to_time64(tm);
182 	int ret;
183 
184 	ret = clk_enable(data->clk);
185 	if (ret)
186 		return ret;
187 
188 	/* Disable RTC first */
189 	ret = snvs_rtc_enable(data, false);
190 	if (ret)
191 		return ret;
192 
193 	/* Write 32-bit time to 47-bit timer, leaving 15 LSBs blank */
194 	regmap_write(data->regmap, data->offset + SNVS_LPSRTCLR, time << CNTR_TO_SECS_SH);
195 	regmap_write(data->regmap, data->offset + SNVS_LPSRTCMR, time >> (32 - CNTR_TO_SECS_SH));
196 
197 	/* Enable RTC again */
198 	ret = snvs_rtc_enable(data, true);
199 
200 	clk_disable(data->clk);
201 
202 	return ret;
203 }
204 
snvs_rtc_read_alarm(struct device * dev,struct rtc_wkalrm * alrm)205 static int snvs_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
206 {
207 	struct snvs_rtc_data *data = dev_get_drvdata(dev);
208 	u32 lptar, lpsr;
209 	int ret;
210 
211 	ret = clk_enable(data->clk);
212 	if (ret)
213 		return ret;
214 
215 	regmap_read(data->regmap, data->offset + SNVS_LPTAR, &lptar);
216 	rtc_time64_to_tm(lptar, &alrm->time);
217 
218 	regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr);
219 	alrm->pending = (lpsr & SNVS_LPSR_LPTA) ? 1 : 0;
220 
221 	clk_disable(data->clk);
222 
223 	return 0;
224 }
225 
snvs_rtc_alarm_irq_enable(struct device * dev,unsigned int enable)226 static int snvs_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
227 {
228 	struct snvs_rtc_data *data = dev_get_drvdata(dev);
229 	int ret;
230 
231 	ret = clk_enable(data->clk);
232 	if (ret)
233 		return ret;
234 
235 	regmap_update_bits(data->regmap, data->offset + SNVS_LPCR,
236 			   (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN),
237 			   enable ? (SNVS_LPCR_LPTA_EN | SNVS_LPCR_LPWUI_EN) : 0);
238 
239 	ret = rtc_write_sync_lp(data);
240 
241 	clk_disable(data->clk);
242 
243 	return ret;
244 }
245 
snvs_rtc_set_alarm(struct device * dev,struct rtc_wkalrm * alrm)246 static int snvs_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
247 {
248 	struct snvs_rtc_data *data = dev_get_drvdata(dev);
249 	unsigned long time = rtc_tm_to_time64(&alrm->time);
250 	int ret;
251 
252 	ret = clk_enable(data->clk);
253 	if (ret)
254 		return ret;
255 
256 	regmap_update_bits(data->regmap, data->offset + SNVS_LPCR, SNVS_LPCR_LPTA_EN, 0);
257 	ret = rtc_write_sync_lp(data);
258 	if (ret)
259 		return ret;
260 	regmap_write(data->regmap, data->offset + SNVS_LPTAR, time);
261 
262 	/* Clear alarm interrupt status bit */
263 	regmap_write(data->regmap, data->offset + SNVS_LPSR, SNVS_LPSR_LPTA);
264 
265 	clk_disable(data->clk);
266 
267 	return snvs_rtc_alarm_irq_enable(dev, alrm->enabled);
268 }
269 
270 static const struct rtc_class_ops snvs_rtc_ops = {
271 	.read_time = snvs_rtc_read_time,
272 	.set_time = snvs_rtc_set_time,
273 	.read_alarm = snvs_rtc_read_alarm,
274 	.set_alarm = snvs_rtc_set_alarm,
275 	.alarm_irq_enable = snvs_rtc_alarm_irq_enable,
276 };
277 
snvs_rtc_irq_handler(int irq,void * dev_id)278 static irqreturn_t snvs_rtc_irq_handler(int irq, void *dev_id)
279 {
280 	struct device *dev = dev_id;
281 	struct snvs_rtc_data *data = dev_get_drvdata(dev);
282 	u32 lpsr;
283 	u32 events = 0;
284 
285 	clk_enable(data->clk);
286 
287 	regmap_read(data->regmap, data->offset + SNVS_LPSR, &lpsr);
288 
289 	if (lpsr & SNVS_LPSR_LPTA) {
290 		events |= (RTC_AF | RTC_IRQF);
291 
292 		/* RTC alarm should be one-shot */
293 		snvs_rtc_alarm_irq_enable(dev, 0);
294 
295 		rtc_update_irq(data->rtc, 1, events);
296 	}
297 
298 	/* clear interrupt status */
299 	regmap_write(data->regmap, data->offset + SNVS_LPSR, lpsr);
300 
301 	clk_disable(data->clk);
302 
303 	return events ? IRQ_HANDLED : IRQ_NONE;
304 }
305 
306 static const struct regmap_config snvs_rtc_config = {
307 	.reg_bits = 32,
308 	.val_bits = 32,
309 	.reg_stride = 4,
310 };
311 
snvs_rtc_action(void * data)312 static void snvs_rtc_action(void *data)
313 {
314 	clk_disable_unprepare(data);
315 }
316 
snvs_rtc_probe(struct platform_device * pdev)317 static int snvs_rtc_probe(struct platform_device *pdev)
318 {
319 	struct snvs_rtc_data *data;
320 	int ret;
321 	void __iomem *mmio;
322 
323 	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
324 	if (!data)
325 		return -ENOMEM;
326 
327 	data->rtc = devm_rtc_allocate_device(&pdev->dev);
328 	if (IS_ERR(data->rtc))
329 		return PTR_ERR(data->rtc);
330 
331 	data->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "regmap");
332 
333 	if (IS_ERR(data->regmap)) {
334 		dev_warn(&pdev->dev, "snvs rtc: you use old dts file, please update it\n");
335 
336 		mmio = devm_platform_ioremap_resource(pdev, 0);
337 		if (IS_ERR(mmio))
338 			return PTR_ERR(mmio);
339 
340 		data->regmap = devm_regmap_init_mmio(&pdev->dev, mmio, &snvs_rtc_config);
341 	} else {
342 		data->offset = SNVS_LPREGISTER_OFFSET;
343 		of_property_read_u32(pdev->dev.of_node, "offset", &data->offset);
344 	}
345 
346 	if (IS_ERR(data->regmap)) {
347 		dev_err(&pdev->dev, "Can't find snvs syscon\n");
348 		return -ENODEV;
349 	}
350 
351 	data->irq = platform_get_irq(pdev, 0);
352 	if (data->irq < 0)
353 		return data->irq;
354 
355 	data->clk = devm_clk_get(&pdev->dev, "snvs-rtc");
356 	if (IS_ERR(data->clk)) {
357 		data->clk = NULL;
358 	} else {
359 		ret = clk_prepare_enable(data->clk);
360 		if (ret) {
361 			dev_err(&pdev->dev,
362 				"Could not prepare or enable the snvs clock\n");
363 			return ret;
364 		}
365 	}
366 
367 	ret = devm_add_action_or_reset(&pdev->dev, snvs_rtc_action, data->clk);
368 	if (ret)
369 		return ret;
370 
371 	platform_set_drvdata(pdev, data);
372 
373 	/* Initialize glitch detect */
374 	regmap_write(data->regmap, data->offset + SNVS_LPPGDR, SNVS_LPPGDR_INIT);
375 
376 	/* Clear interrupt status */
377 	regmap_write(data->regmap, data->offset + SNVS_LPSR, 0xffffffff);
378 
379 	/* Enable RTC */
380 	ret = snvs_rtc_enable(data, true);
381 	if (ret) {
382 		dev_err(&pdev->dev, "failed to enable rtc %d\n", ret);
383 		return ret;
384 	}
385 
386 	device_init_wakeup(&pdev->dev, true);
387 	ret = dev_pm_set_wake_irq(&pdev->dev, data->irq);
388 	if (ret)
389 		dev_err(&pdev->dev, "failed to enable irq wake\n");
390 
391 	ret = devm_request_irq(&pdev->dev, data->irq, snvs_rtc_irq_handler,
392 			       IRQF_SHARED, "rtc alarm", &pdev->dev);
393 	if (ret) {
394 		dev_err(&pdev->dev, "failed to request irq %d: %d\n",
395 			data->irq, ret);
396 		return ret;
397 	}
398 
399 	data->rtc->ops = &snvs_rtc_ops;
400 	data->rtc->range_max = U32_MAX;
401 
402 	return devm_rtc_register_device(data->rtc);
403 }
404 
snvs_rtc_suspend_noirq(struct device * dev)405 static int __maybe_unused snvs_rtc_suspend_noirq(struct device *dev)
406 {
407 	struct snvs_rtc_data *data = dev_get_drvdata(dev);
408 
409 	clk_disable(data->clk);
410 
411 	return 0;
412 }
413 
snvs_rtc_resume_noirq(struct device * dev)414 static int __maybe_unused snvs_rtc_resume_noirq(struct device *dev)
415 {
416 	struct snvs_rtc_data *data = dev_get_drvdata(dev);
417 
418 	if (data->clk)
419 		return clk_enable(data->clk);
420 
421 	return 0;
422 }
423 
424 static const struct dev_pm_ops snvs_rtc_pm_ops = {
425 	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(snvs_rtc_suspend_noirq, snvs_rtc_resume_noirq)
426 };
427 
428 static const struct of_device_id snvs_dt_ids[] = {
429 	{ .compatible = "fsl,sec-v4.0-mon-rtc-lp", },
430 	{ /* sentinel */ }
431 };
432 MODULE_DEVICE_TABLE(of, snvs_dt_ids);
433 
434 static struct platform_driver snvs_rtc_driver = {
435 	.driver = {
436 		.name	= "snvs_rtc",
437 		.pm	= &snvs_rtc_pm_ops,
438 		.of_match_table = snvs_dt_ids,
439 	},
440 	.probe		= snvs_rtc_probe,
441 };
442 module_platform_driver(snvs_rtc_driver);
443 
444 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
445 MODULE_DESCRIPTION("Freescale SNVS RTC Driver");
446 MODULE_LICENSE("GPL");
447