1 // SPDX-License-Identifier: GPL-2.0-only
2 //
3 // rt722-sdca.c -- rt722 SDCA ALSA SoC audio driver
4 //
5 // Copyright(c) 2023 Realtek Semiconductor Corp.
6 //
7 //
8
9 #include <linux/bitops.h>
10 #include <sound/core.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <sound/initval.h>
14 #include <sound/jack.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/moduleparam.h>
18 #include <sound/pcm.h>
19 #include <linux/pm_runtime.h>
20 #include <sound/pcm_params.h>
21 #include <linux/soundwire/sdw_registers.h>
22 #include <linux/slab.h>
23 #include <sound/soc-dapm.h>
24 #include <sound/tlv.h>
25
26 #include "rt722-sdca.h"
27
28 #define RT722_NID_ADDR(nid, reg) ((nid) << 20 | (reg))
29
rt722_sdca_index_write(struct rt722_sdca_priv * rt722,unsigned int nid,unsigned int reg,unsigned int value)30 int rt722_sdca_index_write(struct rt722_sdca_priv *rt722,
31 unsigned int nid, unsigned int reg, unsigned int value)
32 {
33 struct regmap *regmap = rt722->regmap;
34 unsigned int addr = RT722_NID_ADDR(nid, reg);
35 int ret;
36
37 ret = regmap_write(regmap, addr, value);
38 if (ret < 0)
39 dev_err(&rt722->slave->dev,
40 "%s: Failed to set private value: %06x <= %04x ret=%d\n",
41 __func__, addr, value, ret);
42
43 return ret;
44 }
45
rt722_sdca_index_read(struct rt722_sdca_priv * rt722,unsigned int nid,unsigned int reg,unsigned int * value)46 int rt722_sdca_index_read(struct rt722_sdca_priv *rt722,
47 unsigned int nid, unsigned int reg, unsigned int *value)
48 {
49 int ret;
50 struct regmap *regmap = rt722->regmap;
51 unsigned int addr = RT722_NID_ADDR(nid, reg);
52
53 ret = regmap_read(regmap, addr, value);
54 if (ret < 0)
55 dev_err(&rt722->slave->dev,
56 "%s: Failed to get private value: %06x => %04x ret=%d\n",
57 __func__, addr, *value, ret);
58
59 return ret;
60 }
61
rt722_sdca_index_update_bits(struct rt722_sdca_priv * rt722,unsigned int nid,unsigned int reg,unsigned int mask,unsigned int val)62 static int rt722_sdca_index_update_bits(struct rt722_sdca_priv *rt722,
63 unsigned int nid, unsigned int reg, unsigned int mask, unsigned int val)
64 {
65 unsigned int tmp;
66 int ret;
67
68 ret = rt722_sdca_index_read(rt722, nid, reg, &tmp);
69 if (ret < 0)
70 return ret;
71
72 set_mask_bits(&tmp, mask, val);
73 return rt722_sdca_index_write(rt722, nid, reg, tmp);
74 }
75
rt722_sdca_btn_type(unsigned char * buffer)76 static int rt722_sdca_btn_type(unsigned char *buffer)
77 {
78 if ((*buffer & 0xf0) == 0x10 || (*buffer & 0x0f) == 0x01 || (*(buffer + 1) == 0x01) ||
79 (*(buffer + 1) == 0x10))
80 return SND_JACK_BTN_2;
81 else if ((*buffer & 0xf0) == 0x20 || (*buffer & 0x0f) == 0x02 || (*(buffer + 1) == 0x02) ||
82 (*(buffer + 1) == 0x20))
83 return SND_JACK_BTN_3;
84 else if ((*buffer & 0xf0) == 0x40 || (*buffer & 0x0f) == 0x04 || (*(buffer + 1) == 0x04) ||
85 (*(buffer + 1) == 0x40))
86 return SND_JACK_BTN_0;
87 else if ((*buffer & 0xf0) == 0x80 || (*buffer & 0x0f) == 0x08 || (*(buffer + 1) == 0x08) ||
88 (*(buffer + 1) == 0x80))
89 return SND_JACK_BTN_1;
90
91 return 0;
92 }
93
rt722_sdca_button_detect(struct rt722_sdca_priv * rt722)94 static unsigned int rt722_sdca_button_detect(struct rt722_sdca_priv *rt722)
95 {
96 unsigned int btn_type = 0, offset, idx, val, owner;
97 int ret;
98 unsigned char buf[3];
99
100 /* get current UMP message owner */
101 ret = regmap_read(rt722->regmap,
102 SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01,
103 RT722_SDCA_CTL_HIDTX_CURRENT_OWNER, 0), &owner);
104 if (ret < 0)
105 return 0;
106
107 /* if owner is device then there is no button event from device */
108 if (owner == 1)
109 return 0;
110
111 /* read UMP message offset */
112 ret = regmap_read(rt722->regmap,
113 SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01,
114 RT722_SDCA_CTL_HIDTX_MESSAGE_OFFSET, 0), &offset);
115 if (ret < 0)
116 goto _end_btn_det_;
117
118 for (idx = 0; idx < sizeof(buf); idx++) {
119 ret = regmap_read(rt722->regmap,
120 RT722_BUF_ADDR_HID1 + offset + idx, &val);
121 if (ret < 0)
122 goto _end_btn_det_;
123 buf[idx] = val & 0xff;
124 }
125
126 if (buf[0] == 0x11)
127 btn_type = rt722_sdca_btn_type(&buf[1]);
128
129 _end_btn_det_:
130 /* Host is owner, so set back to device */
131 if (owner == 0)
132 /* set owner to device */
133 regmap_write(rt722->regmap,
134 SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01,
135 RT722_SDCA_CTL_HIDTX_CURRENT_OWNER, 0), 0x01);
136
137 return btn_type;
138 }
139
rt722_sdca_headset_detect(struct rt722_sdca_priv * rt722)140 static int rt722_sdca_headset_detect(struct rt722_sdca_priv *rt722)
141 {
142 unsigned int det_mode;
143 int ret;
144
145 /* get detected_mode */
146 ret = regmap_read(rt722->regmap,
147 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_GE49,
148 RT722_SDCA_CTL_DETECTED_MODE, 0), &det_mode);
149 if (ret < 0)
150 goto io_error;
151
152 switch (det_mode) {
153 case 0x00:
154 rt722->jack_type = 0;
155 break;
156 case 0x03:
157 rt722->jack_type = SND_JACK_HEADPHONE;
158 break;
159 case 0x05:
160 rt722->jack_type = SND_JACK_HEADSET;
161 break;
162 }
163
164 /* write selected_mode */
165 if (det_mode) {
166 ret = regmap_write(rt722->regmap,
167 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_GE49,
168 RT722_SDCA_CTL_SELECTED_MODE, 0), det_mode);
169 if (ret < 0)
170 goto io_error;
171 }
172
173 dev_dbg(&rt722->slave->dev,
174 "%s, detected_mode=0x%x\n", __func__, det_mode);
175
176 return 0;
177
178 io_error:
179 pr_err_ratelimited("IO error in %s, ret %d\n", __func__, ret);
180 return ret;
181 }
182
rt722_sdca_jack_detect_handler(struct work_struct * work)183 static void rt722_sdca_jack_detect_handler(struct work_struct *work)
184 {
185 struct rt722_sdca_priv *rt722 =
186 container_of(work, struct rt722_sdca_priv, jack_detect_work.work);
187 int btn_type = 0, ret;
188
189 if (!rt722->hs_jack)
190 return;
191
192 if (!rt722->component->card || !rt722->component->card->instantiated)
193 return;
194
195 /* SDW_SCP_SDCA_INT_SDCA_0 is used for jack detection */
196 if (rt722->scp_sdca_stat1 & SDW_SCP_SDCA_INT_SDCA_0) {
197 ret = rt722_sdca_headset_detect(rt722);
198 if (ret < 0)
199 return;
200 }
201
202 /* SDW_SCP_SDCA_INT_SDCA_8 is used for button detection */
203 if (rt722->scp_sdca_stat2 & SDW_SCP_SDCA_INT_SDCA_8)
204 btn_type = rt722_sdca_button_detect(rt722);
205
206 if (rt722->jack_type == 0)
207 btn_type = 0;
208
209 dev_dbg(&rt722->slave->dev,
210 "in %s, jack_type=%d\n", __func__, rt722->jack_type);
211 dev_dbg(&rt722->slave->dev,
212 "in %s, btn_type=0x%x\n", __func__, btn_type);
213 dev_dbg(&rt722->slave->dev,
214 "in %s, scp_sdca_stat1=0x%x, scp_sdca_stat2=0x%x\n", __func__,
215 rt722->scp_sdca_stat1, rt722->scp_sdca_stat2);
216
217 snd_soc_jack_report(rt722->hs_jack, rt722->jack_type | btn_type,
218 SND_JACK_HEADSET |
219 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
220 SND_JACK_BTN_2 | SND_JACK_BTN_3);
221
222 if (btn_type) {
223 /* button released */
224 snd_soc_jack_report(rt722->hs_jack, rt722->jack_type,
225 SND_JACK_HEADSET |
226 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
227 SND_JACK_BTN_2 | SND_JACK_BTN_3);
228
229 mod_delayed_work(system_power_efficient_wq,
230 &rt722->jack_btn_check_work, msecs_to_jiffies(200));
231 }
232 }
233
rt722_sdca_btn_check_handler(struct work_struct * work)234 static void rt722_sdca_btn_check_handler(struct work_struct *work)
235 {
236 struct rt722_sdca_priv *rt722 =
237 container_of(work, struct rt722_sdca_priv, jack_btn_check_work.work);
238 int btn_type = 0, ret, idx;
239 unsigned int det_mode, offset, val;
240 unsigned char buf[3];
241
242 ret = regmap_read(rt722->regmap,
243 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_GE49,
244 RT722_SDCA_CTL_DETECTED_MODE, 0), &det_mode);
245 if (ret < 0)
246 goto io_error;
247
248 /* pin attached */
249 if (det_mode) {
250 /* read UMP message offset */
251 ret = regmap_read(rt722->regmap,
252 SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01,
253 RT722_SDCA_CTL_HIDTX_MESSAGE_OFFSET, 0), &offset);
254 if (ret < 0)
255 goto io_error;
256
257 for (idx = 0; idx < sizeof(buf); idx++) {
258 ret = regmap_read(rt722->regmap,
259 RT722_BUF_ADDR_HID1 + offset + idx, &val);
260 if (ret < 0)
261 goto io_error;
262 buf[idx] = val & 0xff;
263 }
264
265 if (buf[0] == 0x11)
266 btn_type = rt722_sdca_btn_type(&buf[1]);
267 } else
268 rt722->jack_type = 0;
269
270 dev_dbg(&rt722->slave->dev, "%s, btn_type=0x%x\n", __func__, btn_type);
271 snd_soc_jack_report(rt722->hs_jack, rt722->jack_type | btn_type,
272 SND_JACK_HEADSET |
273 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
274 SND_JACK_BTN_2 | SND_JACK_BTN_3);
275
276 if (btn_type) {
277 /* button released */
278 snd_soc_jack_report(rt722->hs_jack, rt722->jack_type,
279 SND_JACK_HEADSET |
280 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
281 SND_JACK_BTN_2 | SND_JACK_BTN_3);
282
283 mod_delayed_work(system_power_efficient_wq,
284 &rt722->jack_btn_check_work, msecs_to_jiffies(200));
285 }
286
287 return;
288
289 io_error:
290 pr_err_ratelimited("IO error in %s, ret %d\n", __func__, ret);
291 }
292
rt722_sdca_jack_init(struct rt722_sdca_priv * rt722)293 static void rt722_sdca_jack_init(struct rt722_sdca_priv *rt722)
294 {
295 mutex_lock(&rt722->calibrate_mutex);
296 if (rt722->hs_jack) {
297 /* set SCP_SDCA_IntMask1[0]=1 */
298 sdw_write_no_pm(rt722->slave, SDW_SCP_SDCA_INTMASK1,
299 SDW_SCP_SDCA_INTMASK_SDCA_0);
300 /* set SCP_SDCA_IntMask2[0]=1 */
301 sdw_write_no_pm(rt722->slave, SDW_SCP_SDCA_INTMASK2,
302 SDW_SCP_SDCA_INTMASK_SDCA_8);
303 dev_dbg(&rt722->slave->dev, "in %s enable\n", __func__);
304 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL,
305 RT722_HDA_LEGACY_UNSOL_CTL, 0x016E);
306 /* set XU(et03h) & XU(et0Dh) to Not bypassed */
307 regmap_write(rt722->regmap,
308 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_XU03,
309 RT722_SDCA_CTL_SELECTED_MODE, 0), 0);
310 regmap_write(rt722->regmap,
311 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_XU0D,
312 RT722_SDCA_CTL_SELECTED_MODE, 0), 0);
313 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_GE_RELATED_CTL1, 0x0000);
314 /* trigger GE interrupt */
315 rt722_sdca_index_update_bits(rt722, RT722_VENDOR_HDA_CTL,
316 RT722_GE_RELATED_CTL2, 0x4000, 0x4000);
317 }
318 mutex_unlock(&rt722->calibrate_mutex);
319 }
320
rt722_sdca_set_jack_detect(struct snd_soc_component * component,struct snd_soc_jack * hs_jack,void * data)321 static int rt722_sdca_set_jack_detect(struct snd_soc_component *component,
322 struct snd_soc_jack *hs_jack, void *data)
323 {
324 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
325 int ret;
326
327 rt722->hs_jack = hs_jack;
328
329 ret = pm_runtime_resume_and_get(component->dev);
330 if (ret < 0) {
331 if (ret != -EACCES) {
332 dev_err(component->dev, "%s: failed to resume %d\n", __func__, ret);
333 return ret;
334 }
335 /* pm_runtime not enabled yet */
336 dev_dbg(component->dev, "%s: skipping jack init for now\n", __func__);
337 return 0;
338 }
339
340 rt722_sdca_jack_init(rt722);
341
342 pm_runtime_mark_last_busy(component->dev);
343 pm_runtime_put_autosuspend(component->dev);
344
345 return 0;
346 }
347
348 /* For SDCA control DAC/ADC Gain */
rt722_sdca_set_gain_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)349 static int rt722_sdca_set_gain_put(struct snd_kcontrol *kcontrol,
350 struct snd_ctl_elem_value *ucontrol)
351 {
352 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
353 struct soc_mixer_control *mc =
354 (struct soc_mixer_control *)kcontrol->private_value;
355 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
356 unsigned int read_l, read_r, gain_l_val, gain_r_val;
357 unsigned int adc_vol_flag = 0, changed = 0;
358 unsigned int lvalue, rvalue;
359 const unsigned int interval_offset = 0xc0;
360 const unsigned int tendB = 0xa00;
361
362 if (strstr(ucontrol->id.name, "FU1E Capture Volume") ||
363 strstr(ucontrol->id.name, "FU0F Capture Volume"))
364 adc_vol_flag = 1;
365
366 regmap_read(rt722->regmap, mc->reg, &lvalue);
367 regmap_read(rt722->regmap, mc->rreg, &rvalue);
368
369 /* L Channel */
370 gain_l_val = ucontrol->value.integer.value[0];
371 if (gain_l_val > mc->max)
372 gain_l_val = mc->max;
373
374 if (mc->shift == 8) /* boost gain */
375 gain_l_val = gain_l_val * tendB;
376 else {
377 /* ADC/DAC gain */
378 if (adc_vol_flag)
379 gain_l_val = 0x1e00 - ((mc->max - gain_l_val) * interval_offset);
380 else
381 gain_l_val = 0 - ((mc->max - gain_l_val) * interval_offset);
382 gain_l_val &= 0xffff;
383 }
384
385 /* R Channel */
386 gain_r_val = ucontrol->value.integer.value[1];
387 if (gain_r_val > mc->max)
388 gain_r_val = mc->max;
389
390 if (mc->shift == 8) /* boost gain */
391 gain_r_val = gain_r_val * tendB;
392 else {
393 /* ADC/DAC gain */
394 if (adc_vol_flag)
395 gain_r_val = 0x1e00 - ((mc->max - gain_r_val) * interval_offset);
396 else
397 gain_r_val = 0 - ((mc->max - gain_r_val) * interval_offset);
398 gain_r_val &= 0xffff;
399 }
400
401 if (lvalue != gain_l_val || rvalue != gain_r_val)
402 changed = 1;
403 else
404 return 0;
405
406 /* Lch*/
407 regmap_write(rt722->regmap, mc->reg, gain_l_val);
408
409 /* Rch */
410 regmap_write(rt722->regmap, mc->rreg, gain_r_val);
411
412 regmap_read(rt722->regmap, mc->reg, &read_l);
413 regmap_read(rt722->regmap, mc->rreg, &read_r);
414 if (read_r == gain_r_val && read_l == gain_l_val)
415 return changed;
416
417 return -EIO;
418 }
419
rt722_sdca_set_gain_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)420 static int rt722_sdca_set_gain_get(struct snd_kcontrol *kcontrol,
421 struct snd_ctl_elem_value *ucontrol)
422 {
423 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
424 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
425 struct soc_mixer_control *mc =
426 (struct soc_mixer_control *)kcontrol->private_value;
427 unsigned int read_l, read_r, ctl_l = 0, ctl_r = 0;
428 unsigned int adc_vol_flag = 0;
429 const unsigned int interval_offset = 0xc0;
430 const unsigned int tendB = 0xa00;
431
432 if (strstr(ucontrol->id.name, "FU1E Capture Volume") ||
433 strstr(ucontrol->id.name, "FU0F Capture Volume"))
434 adc_vol_flag = 1;
435
436 regmap_read(rt722->regmap, mc->reg, &read_l);
437 regmap_read(rt722->regmap, mc->rreg, &read_r);
438
439 if (mc->shift == 8) /* boost gain */
440 ctl_l = read_l / tendB;
441 else {
442 if (adc_vol_flag)
443 ctl_l = mc->max - (((0x1e00 - read_l) & 0xffff) / interval_offset);
444 else
445 ctl_l = mc->max - (((0 - read_l) & 0xffff) / interval_offset);
446 }
447
448 if (read_l != read_r) {
449 if (mc->shift == 8) /* boost gain */
450 ctl_r = read_r / tendB;
451 else { /* ADC/DAC gain */
452 if (adc_vol_flag)
453 ctl_r = mc->max - (((0x1e00 - read_r) & 0xffff) / interval_offset);
454 else
455 ctl_r = mc->max - (((0 - read_r) & 0xffff) / interval_offset);
456 }
457 } else {
458 ctl_r = ctl_l;
459 }
460
461 ucontrol->value.integer.value[0] = ctl_l;
462 ucontrol->value.integer.value[1] = ctl_r;
463
464 return 0;
465 }
466
rt722_sdca_set_fu1e_capture_ctl(struct rt722_sdca_priv * rt722)467 static int rt722_sdca_set_fu1e_capture_ctl(struct rt722_sdca_priv *rt722)
468 {
469 int err, i;
470 unsigned int ch_mute;
471
472 for (i = 0; i < ARRAY_SIZE(rt722->fu1e_mixer_mute); i++) {
473 ch_mute = rt722->fu1e_dapm_mute || rt722->fu1e_mixer_mute[i];
474 err = regmap_write(rt722->regmap,
475 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E,
476 RT722_SDCA_CTL_FU_MUTE, CH_01) + i, ch_mute);
477 if (err < 0)
478 return err;
479 }
480
481 return 0;
482 }
483
rt722_sdca_fu1e_capture_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)484 static int rt722_sdca_fu1e_capture_get(struct snd_kcontrol *kcontrol,
485 struct snd_ctl_elem_value *ucontrol)
486 {
487 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
488 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
489 struct rt722_sdca_dmic_kctrl_priv *p =
490 (struct rt722_sdca_dmic_kctrl_priv *)kcontrol->private_value;
491 unsigned int i;
492
493 for (i = 0; i < p->count; i++)
494 ucontrol->value.integer.value[i] = !rt722->fu1e_mixer_mute[i];
495
496 return 0;
497 }
498
rt722_sdca_fu1e_capture_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)499 static int rt722_sdca_fu1e_capture_put(struct snd_kcontrol *kcontrol,
500 struct snd_ctl_elem_value *ucontrol)
501 {
502 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
503 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
504 struct rt722_sdca_dmic_kctrl_priv *p =
505 (struct rt722_sdca_dmic_kctrl_priv *)kcontrol->private_value;
506 int err, changed = 0, i;
507
508 for (i = 0; i < p->count; i++) {
509 if (rt722->fu1e_mixer_mute[i] != !ucontrol->value.integer.value[i])
510 changed = 1;
511 rt722->fu1e_mixer_mute[i] = !ucontrol->value.integer.value[i];
512 }
513
514 err = rt722_sdca_set_fu1e_capture_ctl(rt722);
515 if (err < 0)
516 return err;
517
518 return changed;
519 }
520
rt722_sdca_set_fu0f_capture_ctl(struct rt722_sdca_priv * rt722)521 static int rt722_sdca_set_fu0f_capture_ctl(struct rt722_sdca_priv *rt722)
522 {
523 int err;
524 unsigned int ch_l, ch_r;
525
526 ch_l = (rt722->fu0f_dapm_mute || rt722->fu0f_mixer_l_mute) ? 0x01 : 0x00;
527 ch_r = (rt722->fu0f_dapm_mute || rt722->fu0f_mixer_r_mute) ? 0x01 : 0x00;
528
529 err = regmap_write(rt722->regmap,
530 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F,
531 RT722_SDCA_CTL_FU_MUTE, CH_L), ch_l);
532 if (err < 0)
533 return err;
534
535 err = regmap_write(rt722->regmap,
536 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F,
537 RT722_SDCA_CTL_FU_MUTE, CH_R), ch_r);
538 if (err < 0)
539 return err;
540
541 return 0;
542 }
543
rt722_sdca_fu0f_capture_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)544 static int rt722_sdca_fu0f_capture_get(struct snd_kcontrol *kcontrol,
545 struct snd_ctl_elem_value *ucontrol)
546 {
547 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
548 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
549
550 ucontrol->value.integer.value[0] = !rt722->fu0f_mixer_l_mute;
551 ucontrol->value.integer.value[1] = !rt722->fu0f_mixer_r_mute;
552 return 0;
553 }
554
rt722_sdca_fu0f_capture_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)555 static int rt722_sdca_fu0f_capture_put(struct snd_kcontrol *kcontrol,
556 struct snd_ctl_elem_value *ucontrol)
557 {
558 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
559 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
560 int err, changed = 0;
561
562 if (rt722->fu0f_mixer_l_mute != !ucontrol->value.integer.value[0] ||
563 rt722->fu0f_mixer_r_mute != !ucontrol->value.integer.value[1])
564 changed = 1;
565
566 rt722->fu0f_mixer_l_mute = !ucontrol->value.integer.value[0];
567 rt722->fu0f_mixer_r_mute = !ucontrol->value.integer.value[1];
568 err = rt722_sdca_set_fu0f_capture_ctl(rt722);
569 if (err < 0)
570 return err;
571
572 return changed;
573 }
574
rt722_sdca_fu_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)575 static int rt722_sdca_fu_info(struct snd_kcontrol *kcontrol,
576 struct snd_ctl_elem_info *uinfo)
577 {
578 struct rt722_sdca_dmic_kctrl_priv *p =
579 (struct rt722_sdca_dmic_kctrl_priv *)kcontrol->private_value;
580
581 if (p->max == 1)
582 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
583 else
584 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
585 uinfo->count = p->count;
586 uinfo->value.integer.min = 0;
587 uinfo->value.integer.max = p->max;
588 return 0;
589 }
590
rt722_sdca_dmic_set_gain_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)591 static int rt722_sdca_dmic_set_gain_get(struct snd_kcontrol *kcontrol,
592 struct snd_ctl_elem_value *ucontrol)
593 {
594 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
595 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
596 struct rt722_sdca_dmic_kctrl_priv *p =
597 (struct rt722_sdca_dmic_kctrl_priv *)kcontrol->private_value;
598 unsigned int boost_step = 0x0a00;
599 unsigned int vol_max = 0x1e00;
600 unsigned int regvalue, ctl, i;
601 unsigned int adc_vol_flag = 0;
602 const unsigned int interval_offset = 0xc0;
603
604 if (strstr(ucontrol->id.name, "FU1E Capture Volume"))
605 adc_vol_flag = 1;
606
607 /* check all channels */
608 for (i = 0; i < p->count; i++) {
609 regmap_read(rt722->regmap, p->reg_base + i, ®value);
610
611 if (!adc_vol_flag) /* boost gain */
612 ctl = regvalue / boost_step;
613 else /* ADC gain */
614 ctl = p->max - (((vol_max - regvalue) & 0xffff) / interval_offset);
615
616 ucontrol->value.integer.value[i] = ctl;
617 }
618
619 return 0;
620 }
621
rt722_sdca_dmic_set_gain_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)622 static int rt722_sdca_dmic_set_gain_put(struct snd_kcontrol *kcontrol,
623 struct snd_ctl_elem_value *ucontrol)
624 {
625 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
626 struct rt722_sdca_dmic_kctrl_priv *p =
627 (struct rt722_sdca_dmic_kctrl_priv *)kcontrol->private_value;
628 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
629 unsigned int boost_step = 0x0a00;
630 unsigned int vol_max = 0x1e00;
631 unsigned int gain_val[4];
632 unsigned int i, adc_vol_flag = 0, changed = 0;
633 unsigned int regvalue[4];
634 const unsigned int interval_offset = 0xc0;
635 int err;
636
637 if (strstr(ucontrol->id.name, "FU1E Capture Volume"))
638 adc_vol_flag = 1;
639
640 /* check all channels */
641 for (i = 0; i < p->count; i++) {
642 regmap_read(rt722->regmap, p->reg_base + i, ®value[i]);
643
644 gain_val[i] = ucontrol->value.integer.value[i];
645 if (gain_val[i] > p->max)
646 gain_val[i] = p->max;
647
648 if (!adc_vol_flag) /* boost gain */
649 gain_val[i] = gain_val[i] * boost_step;
650 else { /* ADC gain */
651 gain_val[i] = vol_max - ((p->max - gain_val[i]) * interval_offset);
652 gain_val[i] &= 0xffff;
653 }
654
655 if (regvalue[i] != gain_val[i])
656 changed = 1;
657 }
658
659 if (!changed)
660 return 0;
661
662 for (i = 0; i < p->count; i++) {
663 err = regmap_write(rt722->regmap, p->reg_base + i, gain_val[i]);
664 if (err < 0)
665 dev_err(&rt722->slave->dev, "%s: %#08x can't be set\n",
666 __func__, p->reg_base + i);
667 }
668
669 return changed;
670 }
671
672 #define RT722_SDCA_PR_VALUE(xreg_base, xcount, xmax, xinvert) \
673 ((unsigned long)&(struct rt722_sdca_dmic_kctrl_priv) \
674 {.reg_base = xreg_base, .count = xcount, .max = xmax, \
675 .invert = xinvert})
676
677 #define RT722_SDCA_FU_CTRL(xname, reg_base, xmax, xinvert, xcount) \
678 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
679 .info = rt722_sdca_fu_info, \
680 .get = rt722_sdca_fu1e_capture_get, \
681 .put = rt722_sdca_fu1e_capture_put, \
682 .private_value = RT722_SDCA_PR_VALUE(reg_base, xcount, xmax, xinvert)}
683
684 #define RT722_SDCA_EXT_TLV(xname, reg_base, xhandler_get,\
685 xhandler_put, xcount, xmax, tlv_array) \
686 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
687 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
688 SNDRV_CTL_ELEM_ACCESS_READWRITE, \
689 .tlv.p = (tlv_array), \
690 .info = rt722_sdca_fu_info, \
691 .get = xhandler_get, .put = xhandler_put, \
692 .private_value = RT722_SDCA_PR_VALUE(reg_base, xcount, xmax, 0) }
693
694 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6525, 75, 0);
695 static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, -1725, 75, 0);
696 static const DECLARE_TLV_DB_SCALE(boost_vol_tlv, 0, 1000, 0);
697
698 static const struct snd_kcontrol_new rt722_sdca_controls[] = {
699 /* Headphone playback settings */
700 SOC_DOUBLE_R_EXT_TLV("FU05 Playback Volume",
701 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05,
702 RT722_SDCA_CTL_FU_VOLUME, CH_L),
703 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05,
704 RT722_SDCA_CTL_FU_VOLUME, CH_R), 0, 0x57, 0,
705 rt722_sdca_set_gain_get, rt722_sdca_set_gain_put, out_vol_tlv),
706 /* Headset mic capture settings */
707 SOC_DOUBLE_EXT("FU0F Capture Switch", SND_SOC_NOPM, 0, 1, 1, 0,
708 rt722_sdca_fu0f_capture_get, rt722_sdca_fu0f_capture_put),
709 SOC_DOUBLE_R_EXT_TLV("FU0F Capture Volume",
710 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F,
711 RT722_SDCA_CTL_FU_VOLUME, CH_L),
712 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F,
713 RT722_SDCA_CTL_FU_VOLUME, CH_R), 0, 0x3f, 0,
714 rt722_sdca_set_gain_get, rt722_sdca_set_gain_put, mic_vol_tlv),
715 SOC_DOUBLE_R_EXT_TLV("FU33 Boost Volume",
716 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PLATFORM_FU44,
717 RT722_SDCA_CTL_FU_CH_GAIN, CH_L),
718 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PLATFORM_FU44,
719 RT722_SDCA_CTL_FU_CH_GAIN, CH_R), 8, 3, 0,
720 rt722_sdca_set_gain_get, rt722_sdca_set_gain_put, boost_vol_tlv),
721 /* AMP playback settings */
722 SOC_DOUBLE_R_EXT_TLV("FU06 Playback Volume",
723 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06,
724 RT722_SDCA_CTL_FU_VOLUME, CH_L),
725 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06,
726 RT722_SDCA_CTL_FU_VOLUME, CH_R), 0, 0x57, 0,
727 rt722_sdca_set_gain_get, rt722_sdca_set_gain_put, out_vol_tlv),
728 /* DMIC capture settings */
729 RT722_SDCA_FU_CTRL("FU1E Capture Switch",
730 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E,
731 RT722_SDCA_CTL_FU_MUTE, CH_01), 1, 1, 4),
732 RT722_SDCA_EXT_TLV("FU1E Capture Volume",
733 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E,
734 RT722_SDCA_CTL_FU_VOLUME, CH_01),
735 rt722_sdca_dmic_set_gain_get, rt722_sdca_dmic_set_gain_put,
736 4, 0x3f, mic_vol_tlv),
737 RT722_SDCA_EXT_TLV("FU15 Boost Volume",
738 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_FU15,
739 RT722_SDCA_CTL_FU_CH_GAIN, CH_01),
740 rt722_sdca_dmic_set_gain_get, rt722_sdca_dmic_set_gain_put,
741 4, 3, boost_vol_tlv),
742 };
743
744 static const char * const adc22_mux_text[] = {
745 "MIC2",
746 "LINE1",
747 "LINE2",
748 };
749
750 static const char * const adc07_10_mux_text[] = {
751 "DMIC1",
752 "DMIC2",
753 };
754
755 static SOC_ENUM_SINGLE_DECL(rt722_adc22_enum,
756 RT722_NID_ADDR(RT722_VENDOR_HDA_CTL, RT722_HDA_LEGACY_MUX_CTL0),
757 12, adc22_mux_text);
758
759 static SOC_ENUM_SINGLE_DECL(rt722_adc24_enum,
760 RT722_NID_ADDR(RT722_VENDOR_HDA_CTL, RT722_HDA_LEGACY_MUX_CTL0),
761 4, adc07_10_mux_text);
762
763 static SOC_ENUM_SINGLE_DECL(rt722_adc25_enum,
764 RT722_NID_ADDR(RT722_VENDOR_HDA_CTL, RT722_HDA_LEGACY_MUX_CTL0),
765 0, adc07_10_mux_text);
766
767 static const struct snd_kcontrol_new rt722_sdca_adc22_mux =
768 SOC_DAPM_ENUM("ADC 22 Mux", rt722_adc22_enum);
769
770 static const struct snd_kcontrol_new rt722_sdca_adc24_mux =
771 SOC_DAPM_ENUM("ADC 24 Mux", rt722_adc24_enum);
772
773 static const struct snd_kcontrol_new rt722_sdca_adc25_mux =
774 SOC_DAPM_ENUM("ADC 25 Mux", rt722_adc25_enum);
775
rt722_sdca_fu42_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)776 static int rt722_sdca_fu42_event(struct snd_soc_dapm_widget *w,
777 struct snd_kcontrol *kcontrol, int event)
778 {
779 struct snd_soc_component *component =
780 snd_soc_dapm_to_component(w->dapm);
781 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
782 unsigned char unmute = 0x0, mute = 0x1;
783
784 switch (event) {
785 case SND_SOC_DAPM_POST_PMU:
786 regmap_write(rt722->regmap,
787 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05,
788 RT722_SDCA_CTL_FU_MUTE, CH_L), unmute);
789 regmap_write(rt722->regmap,
790 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05,
791 RT722_SDCA_CTL_FU_MUTE, CH_R), unmute);
792 break;
793 case SND_SOC_DAPM_PRE_PMD:
794 regmap_write(rt722->regmap,
795 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05,
796 RT722_SDCA_CTL_FU_MUTE, CH_L), mute);
797 regmap_write(rt722->regmap,
798 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05,
799 RT722_SDCA_CTL_FU_MUTE, CH_R), mute);
800 break;
801 }
802 return 0;
803 }
804
rt722_sdca_fu21_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)805 static int rt722_sdca_fu21_event(struct snd_soc_dapm_widget *w,
806 struct snd_kcontrol *kcontrol, int event)
807 {
808 struct snd_soc_component *component =
809 snd_soc_dapm_to_component(w->dapm);
810 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
811 unsigned char unmute = 0x0, mute = 0x1;
812
813 switch (event) {
814 case SND_SOC_DAPM_POST_PMU:
815 regmap_write(rt722->regmap,
816 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06,
817 RT722_SDCA_CTL_FU_MUTE, CH_L), unmute);
818 regmap_write(rt722->regmap,
819 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06,
820 RT722_SDCA_CTL_FU_MUTE, CH_R), unmute);
821 break;
822 case SND_SOC_DAPM_PRE_PMD:
823 regmap_write(rt722->regmap,
824 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06,
825 RT722_SDCA_CTL_FU_MUTE, CH_L), mute);
826 regmap_write(rt722->regmap,
827 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06,
828 RT722_SDCA_CTL_FU_MUTE, CH_R), mute);
829 break;
830 }
831 return 0;
832 }
833
rt722_sdca_fu113_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)834 static int rt722_sdca_fu113_event(struct snd_soc_dapm_widget *w,
835 struct snd_kcontrol *kcontrol, int event)
836 {
837 struct snd_soc_component *component =
838 snd_soc_dapm_to_component(w->dapm);
839 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
840
841 switch (event) {
842 case SND_SOC_DAPM_POST_PMU:
843 rt722->fu1e_dapm_mute = false;
844 rt722_sdca_set_fu1e_capture_ctl(rt722);
845 usleep_range(150000, 160000);
846 break;
847 case SND_SOC_DAPM_PRE_PMD:
848 rt722->fu1e_dapm_mute = true;
849 rt722_sdca_set_fu1e_capture_ctl(rt722);
850 break;
851 }
852 return 0;
853 }
854
rt722_sdca_fu36_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)855 static int rt722_sdca_fu36_event(struct snd_soc_dapm_widget *w,
856 struct snd_kcontrol *kcontrol, int event)
857 {
858 struct snd_soc_component *component =
859 snd_soc_dapm_to_component(w->dapm);
860 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
861
862 switch (event) {
863 case SND_SOC_DAPM_POST_PMU:
864 rt722->fu0f_dapm_mute = false;
865 rt722_sdca_set_fu0f_capture_ctl(rt722);
866 break;
867 case SND_SOC_DAPM_PRE_PMD:
868 rt722->fu0f_dapm_mute = true;
869 rt722_sdca_set_fu0f_capture_ctl(rt722);
870 break;
871 }
872 return 0;
873 }
874
rt722_pde_transition_delay(struct rt722_sdca_priv * rt722,unsigned char func,unsigned char entity,unsigned char ps)875 static void rt722_pde_transition_delay(struct rt722_sdca_priv *rt722, unsigned char func,
876 unsigned char entity, unsigned char ps)
877 {
878 unsigned int delay = 1000, val;
879
880 pm_runtime_mark_last_busy(&rt722->slave->dev);
881
882 /* waiting for Actual PDE becomes to PS0/PS3 */
883 while (delay) {
884 regmap_read(rt722->regmap,
885 SDW_SDCA_CTL(func, entity, RT722_SDCA_CTL_ACTUAL_POWER_STATE, 0), &val);
886 if (val == ps)
887 break;
888
889 usleep_range(1000, 1500);
890 delay--;
891 }
892 if (!delay) {
893 dev_warn(&rt722->slave->dev, "%s PDE to %s is NOT ready", __func__, ps?"PS3":"PS0");
894 }
895 }
896
rt722_sdca_pde47_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)897 static int rt722_sdca_pde47_event(struct snd_soc_dapm_widget *w,
898 struct snd_kcontrol *kcontrol, int event)
899 {
900 struct snd_soc_component *component =
901 snd_soc_dapm_to_component(w->dapm);
902 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
903 unsigned char ps0 = 0x0, ps3 = 0x3;
904
905 switch (event) {
906 case SND_SOC_DAPM_POST_PMU:
907 regmap_write(rt722->regmap,
908 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE40,
909 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps0);
910 rt722_pde_transition_delay(rt722, FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE40, ps0);
911 break;
912 case SND_SOC_DAPM_PRE_PMD:
913 regmap_write(rt722->regmap,
914 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE40,
915 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps3);
916 rt722_pde_transition_delay(rt722, FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE40, ps3);
917 break;
918 }
919 return 0;
920 }
921
rt722_sdca_pde23_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)922 static int rt722_sdca_pde23_event(struct snd_soc_dapm_widget *w,
923 struct snd_kcontrol *kcontrol, int event)
924 {
925 struct snd_soc_component *component =
926 snd_soc_dapm_to_component(w->dapm);
927 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
928 unsigned char ps0 = 0x0, ps3 = 0x3;
929
930 switch (event) {
931 case SND_SOC_DAPM_POST_PMU:
932 regmap_write(rt722->regmap,
933 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_PDE23,
934 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps0);
935 rt722_pde_transition_delay(rt722, FUNC_NUM_AMP, RT722_SDCA_ENT_PDE23, ps0);
936 break;
937 case SND_SOC_DAPM_PRE_PMD:
938 regmap_write(rt722->regmap,
939 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_PDE23,
940 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps3);
941 rt722_pde_transition_delay(rt722, FUNC_NUM_AMP, RT722_SDCA_ENT_PDE23, ps3);
942 break;
943 }
944 return 0;
945 }
946
rt722_sdca_pde11_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)947 static int rt722_sdca_pde11_event(struct snd_soc_dapm_widget *w,
948 struct snd_kcontrol *kcontrol, int event)
949 {
950 struct snd_soc_component *component =
951 snd_soc_dapm_to_component(w->dapm);
952 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
953 unsigned char ps0 = 0x0, ps3 = 0x3;
954
955 switch (event) {
956 case SND_SOC_DAPM_POST_PMU:
957 regmap_write(rt722->regmap,
958 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_PDE2A,
959 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps0);
960 rt722_pde_transition_delay(rt722, FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_PDE2A, ps0);
961 break;
962 case SND_SOC_DAPM_PRE_PMD:
963 regmap_write(rt722->regmap,
964 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_PDE2A,
965 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps3);
966 rt722_pde_transition_delay(rt722, FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_PDE2A, ps3);
967 break;
968 }
969 return 0;
970 }
971
rt722_sdca_pde12_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)972 static int rt722_sdca_pde12_event(struct snd_soc_dapm_widget *w,
973 struct snd_kcontrol *kcontrol, int event)
974 {
975 struct snd_soc_component *component =
976 snd_soc_dapm_to_component(w->dapm);
977 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
978 unsigned char ps0 = 0x0, ps3 = 0x3;
979
980 switch (event) {
981 case SND_SOC_DAPM_POST_PMU:
982 regmap_write(rt722->regmap,
983 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE12,
984 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps0);
985 rt722_pde_transition_delay(rt722, FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE12, ps0);
986 break;
987 case SND_SOC_DAPM_PRE_PMD:
988 regmap_write(rt722->regmap,
989 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE12,
990 RT722_SDCA_CTL_REQ_POWER_STATE, 0), ps3);
991 rt722_pde_transition_delay(rt722, FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE12, ps3);
992 break;
993 }
994 return 0;
995 }
996
997 static const struct snd_soc_dapm_widget rt722_sdca_dapm_widgets[] = {
998 SND_SOC_DAPM_OUTPUT("HP"),
999 SND_SOC_DAPM_OUTPUT("SPK"),
1000 SND_SOC_DAPM_INPUT("MIC2"),
1001 SND_SOC_DAPM_INPUT("LINE1"),
1002 SND_SOC_DAPM_INPUT("LINE2"),
1003 SND_SOC_DAPM_INPUT("DMIC1_2"),
1004 SND_SOC_DAPM_INPUT("DMIC3_4"),
1005
1006 SND_SOC_DAPM_SUPPLY("PDE 23", SND_SOC_NOPM, 0, 0,
1007 rt722_sdca_pde23_event,
1008 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1009 SND_SOC_DAPM_SUPPLY("PDE 47", SND_SOC_NOPM, 0, 0,
1010 rt722_sdca_pde47_event,
1011 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1012 SND_SOC_DAPM_SUPPLY("PDE 11", SND_SOC_NOPM, 0, 0,
1013 rt722_sdca_pde11_event,
1014 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1015 SND_SOC_DAPM_SUPPLY("PDE 12", SND_SOC_NOPM, 0, 0,
1016 rt722_sdca_pde12_event,
1017 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1018
1019 SND_SOC_DAPM_DAC_E("FU 21", NULL, SND_SOC_NOPM, 0, 0,
1020 rt722_sdca_fu21_event,
1021 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1022 SND_SOC_DAPM_DAC_E("FU 42", NULL, SND_SOC_NOPM, 0, 0,
1023 rt722_sdca_fu42_event,
1024 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1025 SND_SOC_DAPM_ADC_E("FU 36", NULL, SND_SOC_NOPM, 0, 0,
1026 rt722_sdca_fu36_event,
1027 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1028 SND_SOC_DAPM_ADC_E("FU 113", NULL, SND_SOC_NOPM, 0, 0,
1029 rt722_sdca_fu113_event,
1030 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1031 SND_SOC_DAPM_MUX("ADC 22 Mux", SND_SOC_NOPM, 0, 0,
1032 &rt722_sdca_adc22_mux),
1033 SND_SOC_DAPM_MUX("ADC 24 Mux", SND_SOC_NOPM, 0, 0,
1034 &rt722_sdca_adc24_mux),
1035 SND_SOC_DAPM_MUX("ADC 25 Mux", SND_SOC_NOPM, 0, 0,
1036 &rt722_sdca_adc25_mux),
1037
1038 SND_SOC_DAPM_AIF_IN("DP1RX", "DP1 Headphone Playback", 0, SND_SOC_NOPM, 0, 0),
1039 SND_SOC_DAPM_AIF_OUT("DP2TX", "DP2 Headset Capture", 0, SND_SOC_NOPM, 0, 0),
1040 SND_SOC_DAPM_AIF_IN("DP3RX", "DP3 Speaker Playback", 0, SND_SOC_NOPM, 0, 0),
1041 SND_SOC_DAPM_AIF_OUT("DP6TX", "DP6 DMic Capture", 0, SND_SOC_NOPM, 0, 0),
1042 };
1043
1044 static const struct snd_soc_dapm_route rt722_sdca_audio_map[] = {
1045 {"FU 42", NULL, "DP1RX"},
1046 {"FU 21", NULL, "DP3RX"},
1047
1048 {"ADC 22 Mux", "MIC2", "MIC2"},
1049 {"ADC 22 Mux", "LINE1", "LINE1"},
1050 {"ADC 22 Mux", "LINE2", "LINE2"},
1051 {"ADC 24 Mux", "DMIC1", "DMIC1_2"},
1052 {"ADC 24 Mux", "DMIC2", "DMIC3_4"},
1053 {"ADC 25 Mux", "DMIC1", "DMIC1_2"},
1054 {"ADC 25 Mux", "DMIC2", "DMIC3_4"},
1055 {"FU 36", NULL, "PDE 12"},
1056 {"FU 36", NULL, "ADC 22 Mux"},
1057 {"FU 113", NULL, "PDE 11"},
1058 {"FU 113", NULL, "ADC 24 Mux"},
1059 {"FU 113", NULL, "ADC 25 Mux"},
1060 {"DP2TX", NULL, "FU 36"},
1061 {"DP6TX", NULL, "FU 113"},
1062
1063 {"HP", NULL, "PDE 47"},
1064 {"HP", NULL, "FU 42"},
1065 {"SPK", NULL, "PDE 23"},
1066 {"SPK", NULL, "FU 21"},
1067 };
1068
rt722_sdca_parse_dt(struct rt722_sdca_priv * rt722,struct device * dev)1069 static int rt722_sdca_parse_dt(struct rt722_sdca_priv *rt722, struct device *dev)
1070 {
1071 device_property_read_u32(dev, "realtek,jd-src", &rt722->jd_src);
1072
1073 return 0;
1074 }
1075
rt722_sdca_probe(struct snd_soc_component * component)1076 static int rt722_sdca_probe(struct snd_soc_component *component)
1077 {
1078 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
1079 int ret;
1080
1081 rt722_sdca_parse_dt(rt722, &rt722->slave->dev);
1082 rt722->component = component;
1083
1084 ret = pm_runtime_resume(component->dev);
1085 if (ret < 0 && ret != -EACCES)
1086 return ret;
1087
1088 return 0;
1089 }
1090
1091 static const struct snd_soc_component_driver soc_sdca_dev_rt722 = {
1092 .probe = rt722_sdca_probe,
1093 .controls = rt722_sdca_controls,
1094 .num_controls = ARRAY_SIZE(rt722_sdca_controls),
1095 .dapm_widgets = rt722_sdca_dapm_widgets,
1096 .num_dapm_widgets = ARRAY_SIZE(rt722_sdca_dapm_widgets),
1097 .dapm_routes = rt722_sdca_audio_map,
1098 .num_dapm_routes = ARRAY_SIZE(rt722_sdca_audio_map),
1099 .set_jack = rt722_sdca_set_jack_detect,
1100 .endianness = 1,
1101 };
1102
rt722_sdca_set_sdw_stream(struct snd_soc_dai * dai,void * sdw_stream,int direction)1103 static int rt722_sdca_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream,
1104 int direction)
1105 {
1106 snd_soc_dai_dma_data_set(dai, direction, sdw_stream);
1107
1108 return 0;
1109 }
1110
rt722_sdca_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)1111 static void rt722_sdca_shutdown(struct snd_pcm_substream *substream,
1112 struct snd_soc_dai *dai)
1113 {
1114 snd_soc_dai_set_dma_data(dai, substream, NULL);
1115 }
1116
rt722_sdca_pcm_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)1117 static int rt722_sdca_pcm_hw_params(struct snd_pcm_substream *substream,
1118 struct snd_pcm_hw_params *params,
1119 struct snd_soc_dai *dai)
1120 {
1121 struct snd_soc_component *component = dai->component;
1122 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
1123 struct sdw_stream_config stream_config;
1124 struct sdw_port_config port_config;
1125 enum sdw_data_direction direction;
1126 struct sdw_stream_runtime *sdw_stream;
1127 int retval, port, num_channels;
1128 unsigned int sampling_rate;
1129
1130 dev_dbg(dai->dev, "%s %s", __func__, dai->name);
1131 sdw_stream = snd_soc_dai_get_dma_data(dai, substream);
1132
1133 if (!sdw_stream)
1134 return -EINVAL;
1135
1136 if (!rt722->slave)
1137 return -EINVAL;
1138
1139 /*
1140 * RT722_AIF1 with port = 1 for headphone playback
1141 * RT722_AIF1 with port = 2 for headset-mic capture
1142 * RT722_AIF2 with port = 3 for speaker playback
1143 * RT722_AIF3 with port = 6 for digital-mic capture
1144 */
1145 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1146 direction = SDW_DATA_DIR_RX;
1147 if (dai->id == RT722_AIF1)
1148 port = 1;
1149 else if (dai->id == RT722_AIF2)
1150 port = 3;
1151 else
1152 return -EINVAL;
1153 } else {
1154 direction = SDW_DATA_DIR_TX;
1155 if (dai->id == RT722_AIF1)
1156 port = 2;
1157 else if (dai->id == RT722_AIF3)
1158 port = 6;
1159 else
1160 return -EINVAL;
1161 }
1162 stream_config.frame_rate = params_rate(params);
1163 stream_config.ch_count = params_channels(params);
1164 stream_config.bps = snd_pcm_format_width(params_format(params));
1165 stream_config.direction = direction;
1166
1167 num_channels = params_channels(params);
1168 port_config.ch_mask = GENMASK(num_channels - 1, 0);
1169 port_config.num = port;
1170
1171 retval = sdw_stream_add_slave(rt722->slave, &stream_config,
1172 &port_config, 1, sdw_stream);
1173 if (retval) {
1174 dev_err(dai->dev, "%s: Unable to configure port\n", __func__);
1175 return retval;
1176 }
1177
1178 if (params_channels(params) > 16) {
1179 dev_err(component->dev, "%s: Unsupported channels %d\n",
1180 __func__, params_channels(params));
1181 return -EINVAL;
1182 }
1183
1184 /* sampling rate configuration */
1185 switch (params_rate(params)) {
1186 case 44100:
1187 sampling_rate = RT722_SDCA_RATE_44100HZ;
1188 break;
1189 case 48000:
1190 sampling_rate = RT722_SDCA_RATE_48000HZ;
1191 break;
1192 case 96000:
1193 sampling_rate = RT722_SDCA_RATE_96000HZ;
1194 break;
1195 case 192000:
1196 sampling_rate = RT722_SDCA_RATE_192000HZ;
1197 break;
1198 default:
1199 dev_err(component->dev, "%s: Rate %d is not supported\n",
1200 __func__, params_rate(params));
1201 return -EINVAL;
1202 }
1203
1204 /* set sampling frequency */
1205 if (dai->id == RT722_AIF1) {
1206 regmap_write(rt722->regmap,
1207 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_CS01,
1208 RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), sampling_rate);
1209 regmap_write(rt722->regmap,
1210 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_CS11,
1211 RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), sampling_rate);
1212 }
1213
1214 if (dai->id == RT722_AIF2)
1215 regmap_write(rt722->regmap,
1216 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_CS31,
1217 RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), sampling_rate);
1218
1219 if (dai->id == RT722_AIF3)
1220 regmap_write(rt722->regmap,
1221 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_CS1F,
1222 RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), sampling_rate);
1223
1224 return 0;
1225 }
1226
rt722_sdca_pcm_hw_free(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)1227 static int rt722_sdca_pcm_hw_free(struct snd_pcm_substream *substream,
1228 struct snd_soc_dai *dai)
1229 {
1230 struct snd_soc_component *component = dai->component;
1231 struct rt722_sdca_priv *rt722 = snd_soc_component_get_drvdata(component);
1232 struct sdw_stream_runtime *sdw_stream =
1233 snd_soc_dai_get_dma_data(dai, substream);
1234
1235 if (!rt722->slave)
1236 return -EINVAL;
1237
1238 sdw_stream_remove_slave(rt722->slave, sdw_stream);
1239 return 0;
1240 }
1241
1242 #define RT722_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \
1243 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
1244 #define RT722_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1245 SNDRV_PCM_FMTBIT_S24_LE)
1246
1247 static const struct snd_soc_dai_ops rt722_sdca_ops = {
1248 .hw_params = rt722_sdca_pcm_hw_params,
1249 .hw_free = rt722_sdca_pcm_hw_free,
1250 .set_stream = rt722_sdca_set_sdw_stream,
1251 .shutdown = rt722_sdca_shutdown,
1252 };
1253
1254 static struct snd_soc_dai_driver rt722_sdca_dai[] = {
1255 {
1256 .name = "rt722-sdca-aif1",
1257 .id = RT722_AIF1,
1258 .playback = {
1259 .stream_name = "DP1 Headphone Playback",
1260 .channels_min = 1,
1261 .channels_max = 2,
1262 .rates = RT722_STEREO_RATES,
1263 .formats = RT722_FORMATS,
1264 },
1265 .capture = {
1266 .stream_name = "DP2 Headset Capture",
1267 .channels_min = 1,
1268 .channels_max = 2,
1269 .rates = RT722_STEREO_RATES,
1270 .formats = RT722_FORMATS,
1271 },
1272 .ops = &rt722_sdca_ops,
1273 },
1274 {
1275 .name = "rt722-sdca-aif2",
1276 .id = RT722_AIF2,
1277 .playback = {
1278 .stream_name = "DP3 Speaker Playback",
1279 .channels_min = 1,
1280 .channels_max = 2,
1281 .rates = RT722_STEREO_RATES,
1282 .formats = RT722_FORMATS,
1283 },
1284 .ops = &rt722_sdca_ops,
1285 },
1286 {
1287 .name = "rt722-sdca-aif3",
1288 .id = RT722_AIF3,
1289 .capture = {
1290 .stream_name = "DP6 DMic Capture",
1291 .channels_min = 1,
1292 .channels_max = 4,
1293 .rates = RT722_STEREO_RATES,
1294 .formats = RT722_FORMATS,
1295 },
1296 .ops = &rt722_sdca_ops,
1297 }
1298 };
1299
rt722_sdca_init(struct device * dev,struct regmap * regmap,struct sdw_slave * slave)1300 int rt722_sdca_init(struct device *dev, struct regmap *regmap, struct sdw_slave *slave)
1301 {
1302 struct rt722_sdca_priv *rt722;
1303
1304 rt722 = devm_kzalloc(dev, sizeof(*rt722), GFP_KERNEL);
1305 if (!rt722)
1306 return -ENOMEM;
1307
1308 dev_set_drvdata(dev, rt722);
1309 rt722->slave = slave;
1310 rt722->regmap = regmap;
1311
1312 regcache_cache_only(rt722->regmap, true);
1313
1314 mutex_init(&rt722->calibrate_mutex);
1315 mutex_init(&rt722->disable_irq_lock);
1316
1317 INIT_DELAYED_WORK(&rt722->jack_detect_work, rt722_sdca_jack_detect_handler);
1318 INIT_DELAYED_WORK(&rt722->jack_btn_check_work, rt722_sdca_btn_check_handler);
1319
1320 /*
1321 * Mark hw_init to false
1322 * HW init will be performed when device reports present
1323 */
1324 rt722->hw_init = false;
1325 rt722->first_hw_init = false;
1326 rt722->fu1e_dapm_mute = true;
1327 rt722->fu0f_dapm_mute = true;
1328 rt722->fu0f_mixer_l_mute = rt722->fu0f_mixer_r_mute = true;
1329 rt722->fu1e_mixer_mute[0] = rt722->fu1e_mixer_mute[1] =
1330 rt722->fu1e_mixer_mute[2] = rt722->fu1e_mixer_mute[3] = true;
1331
1332 return devm_snd_soc_register_component(dev,
1333 &soc_sdca_dev_rt722, rt722_sdca_dai, ARRAY_SIZE(rt722_sdca_dai));
1334 }
1335
rt722_sdca_dmic_preset(struct rt722_sdca_priv * rt722)1336 static void rt722_sdca_dmic_preset(struct rt722_sdca_priv *rt722)
1337 {
1338 unsigned int mic_func_status;
1339 struct device *dev = &rt722->slave->dev;
1340
1341 regmap_read(rt722->regmap,
1342 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT0, RT722_SDCA_CTL_FUNC_STATUS, 0), &mic_func_status);
1343 dev_dbg(dev, "%s mic func_status=0x%x\n", __func__, mic_func_status);
1344
1345 if ((mic_func_status & FUNCTION_NEEDS_INITIALIZATION) || (!rt722->first_hw_init)) {
1346 /* Set AD07 power entity floating control */
1347 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL,
1348 RT722_ADC0A_08_PDE_FLOAT_CTL, 0x2a29);
1349 /* Set AD10 power entity floating control */
1350 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL,
1351 RT722_ADC10_PDE_FLOAT_CTL, 0x2a00);
1352 /* Set DMIC1/DMIC2 power entity floating control */
1353 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL,
1354 RT722_DMIC1_2_PDE_FLOAT_CTL, 0x2a2a);
1355 /* Set DMIC2 IT entity floating control */
1356 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL,
1357 RT722_DMIC_ENT_FLOAT_CTL, 0x2626);
1358 /* Set AD10 FU entity floating control */
1359 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL,
1360 RT722_ADC_ENT_FLOAT_CTL, 0x1e00);
1361 /* Set DMIC2 FU entity floating control */
1362 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL,
1363 RT722_DMIC_GAIN_ENT_FLOAT_CTL0, 0x1515);
1364 /* Set AD10 FU channel floating control */
1365 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL,
1366 RT722_ADC_VOL_CH_FLOAT_CTL, 0x0304);
1367 /* Set DMIC2 FU channel floating control */
1368 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL,
1369 RT722_DMIC_GAIN_ENT_FLOAT_CTL2, 0x0304);
1370 /* vf71f_r12_07_06 and vf71f_r13_07_06 = 2’b00 */
1371 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL,
1372 RT722_HDA_LEGACY_CONFIG_CTL0, 0x0000);
1373 /* Enable vf707_r12_05/vf707_r13_05 */
1374 regmap_write(rt722->regmap,
1375 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_IT26,
1376 RT722_SDCA_CTL_VENDOR_DEF, 0), 0x01);
1377 /* Fine tune PDE2A latency */
1378 regmap_write(rt722->regmap, 0x2f5c, 0x25);
1379 /* PHYtiming TDZ/TZD control */
1380 regmap_write(rt722->regmap, 0x2f03, 0x06);
1381
1382 /* clear flag */
1383 regmap_write(rt722->regmap,
1384 SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT0, RT722_SDCA_CTL_FUNC_STATUS, 0),
1385 FUNCTION_NEEDS_INITIALIZATION);
1386 }
1387 }
1388
rt722_sdca_amp_preset(struct rt722_sdca_priv * rt722)1389 static void rt722_sdca_amp_preset(struct rt722_sdca_priv *rt722)
1390 {
1391 unsigned int amp_func_status;
1392 struct device *dev = &rt722->slave->dev;
1393
1394 regmap_read(rt722->regmap,
1395 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT0, RT722_SDCA_CTL_FUNC_STATUS, 0), &_func_status);
1396 dev_dbg(dev, "%s amp func_status=0x%x\n", __func__, amp_func_status);
1397
1398 if ((amp_func_status & FUNCTION_NEEDS_INITIALIZATION) || (!rt722->first_hw_init)) {
1399 /* Set DVQ=01 */
1400 rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_CLSD_CTRL6,
1401 0xc215);
1402 /* Reset dc_cal_top */
1403 rt722_sdca_index_write(rt722, RT722_VENDOR_CALI, RT722_DC_CALIB_CTRL,
1404 0x702c);
1405 /* W1C Trigger Calibration */
1406 rt722_sdca_index_write(rt722, RT722_VENDOR_CALI, RT722_DC_CALIB_CTRL,
1407 0xf02d);
1408 /* Set DAC02/ClassD power entity floating control */
1409 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_AMP_PDE_FLOAT_CTL,
1410 0x2323);
1411 /* Set EAPD high */
1412 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_EAPD_CTL,
1413 0x0002);
1414 /* Enable vf707_r14 */
1415 regmap_write(rt722->regmap,
1416 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_OT23,
1417 RT722_SDCA_CTL_VENDOR_DEF, CH_08), 0x04);
1418
1419 /* clear flag */
1420 regmap_write(rt722->regmap,
1421 SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT0, RT722_SDCA_CTL_FUNC_STATUS, 0),
1422 FUNCTION_NEEDS_INITIALIZATION);
1423 }
1424 }
1425
rt722_sdca_jack_preset(struct rt722_sdca_priv * rt722)1426 static void rt722_sdca_jack_preset(struct rt722_sdca_priv *rt722)
1427 {
1428 int loop_check, chk_cnt = 100, ret;
1429 unsigned int calib_status = 0;
1430 unsigned int jack_func_status;
1431 struct device *dev = &rt722->slave->dev;
1432
1433 regmap_read(rt722->regmap,
1434 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT0, RT722_SDCA_CTL_FUNC_STATUS, 0), &jack_func_status);
1435 dev_dbg(dev, "%s jack func_status=0x%x\n", __func__, jack_func_status);
1436
1437 if ((jack_func_status & FUNCTION_NEEDS_INITIALIZATION) || (!rt722->first_hw_init)) {
1438 /* Config analog bias */
1439 rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_ANALOG_BIAS_CTL3,
1440 0xa081);
1441 /* GE related settings */
1442 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_GE_RELATED_CTL2,
1443 0xa009);
1444 /* Button A, B, C, D bypass mode */
1445 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_UMP_HID_CTL4,
1446 0xcf00);
1447 /* HID1 slot enable */
1448 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_UMP_HID_CTL5,
1449 0x000f);
1450 /* Report ID for HID1 */
1451 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_UMP_HID_CTL0,
1452 0x1100);
1453 /* OSC/OOC for slot 2, 3 */
1454 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_UMP_HID_CTL7,
1455 0x0c12);
1456 /* Set JD de-bounce clock control */
1457 rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_JD_CTRL1,
1458 0x7002);
1459 /* Set DVQ=01 */
1460 rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_CLSD_CTRL6,
1461 0xc215);
1462 /* FSM switch to calibration manual mode */
1463 rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_FSM_CTL,
1464 0x4100);
1465 /* W1C Trigger DC calibration (HP) */
1466 rt722_sdca_index_write(rt722, RT722_VENDOR_CALI, RT722_DAC_DC_CALI_CTL3,
1467 0x008d);
1468 /* check HP calibration FSM status */
1469 for (loop_check = 0; loop_check < chk_cnt; loop_check++) {
1470 usleep_range(10000, 11000);
1471 ret = rt722_sdca_index_read(rt722, RT722_VENDOR_CALI,
1472 RT722_DAC_DC_CALI_CTL3, &calib_status);
1473 if (ret < 0)
1474 dev_dbg(&rt722->slave->dev, "calibration failed!, ret=%d\n", ret);
1475 if ((calib_status & 0x0040) == 0x0)
1476 break;
1477 }
1478
1479 if (loop_check == chk_cnt)
1480 dev_dbg(&rt722->slave->dev, "%s, calibration time-out!\n", __func__);
1481
1482 /* Set ADC09 power entity floating control */
1483 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_ADC0A_08_PDE_FLOAT_CTL,
1484 0x2a12);
1485 /* Set MIC2 and LINE1 power entity floating control */
1486 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_MIC2_LINE2_PDE_FLOAT_CTL,
1487 0x3429);
1488 /* Set ET41h and LINE2 power entity floating control */
1489 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_ET41_LINE2_PDE_FLOAT_CTL,
1490 0x4112);
1491 /* Set DAC03 and HP power entity floating control */
1492 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_DAC03_HP_PDE_FLOAT_CTL,
1493 0x4040);
1494 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_ENT_FLOAT_CTRL_1,
1495 0x4141);
1496 rt722_sdca_index_write(rt722, RT722_VENDOR_HDA_CTL, RT722_FLOAT_CTRL_1,
1497 0x0101);
1498 /* Fine tune PDE40 latency */
1499 regmap_write(rt722->regmap, 0x2f58, 0x07);
1500 regmap_write(rt722->regmap, 0x2f03, 0x06);
1501 /* MIC VRefo */
1502 rt722_sdca_index_update_bits(rt722, RT722_VENDOR_REG,
1503 RT722_COMBO_JACK_AUTO_CTL1, 0x0200, 0x0200);
1504 rt722_sdca_index_update_bits(rt722, RT722_VENDOR_REG,
1505 RT722_VREFO_GAT, 0x4000, 0x4000);
1506 /* Release HP-JD, EN_CBJ_TIE_GL/R open, en_osw gating auto done bit */
1507 rt722_sdca_index_write(rt722, RT722_VENDOR_REG, RT722_DIGITAL_MISC_CTRL4,
1508 0x0010);
1509
1510 /* clear flag */
1511 regmap_write(rt722->regmap,
1512 SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT0, RT722_SDCA_CTL_FUNC_STATUS, 0),
1513 FUNCTION_NEEDS_INITIALIZATION);
1514 }
1515 }
1516
rt722_sdca_io_init(struct device * dev,struct sdw_slave * slave)1517 int rt722_sdca_io_init(struct device *dev, struct sdw_slave *slave)
1518 {
1519 struct rt722_sdca_priv *rt722 = dev_get_drvdata(dev);
1520
1521 rt722->disable_irq = false;
1522
1523 if (rt722->hw_init)
1524 return 0;
1525
1526 regcache_cache_only(rt722->regmap, false);
1527 if (rt722->first_hw_init) {
1528 regcache_cache_bypass(rt722->regmap, true);
1529 } else {
1530 /*
1531 * PM runtime is only enabled when a Slave reports as Attached
1532 */
1533
1534 /* set autosuspend parameters */
1535 pm_runtime_set_autosuspend_delay(&slave->dev, 3000);
1536 pm_runtime_use_autosuspend(&slave->dev);
1537
1538 /* update count of parent 'active' children */
1539 pm_runtime_set_active(&slave->dev);
1540
1541 /* make sure the device does not suspend immediately */
1542 pm_runtime_mark_last_busy(&slave->dev);
1543
1544 pm_runtime_enable(&slave->dev);
1545 }
1546
1547 pm_runtime_get_noresume(&slave->dev);
1548
1549 rt722_sdca_dmic_preset(rt722);
1550 rt722_sdca_amp_preset(rt722);
1551 rt722_sdca_jack_preset(rt722);
1552
1553 if (rt722->first_hw_init) {
1554 regcache_cache_bypass(rt722->regmap, false);
1555 regcache_mark_dirty(rt722->regmap);
1556 } else
1557 rt722->first_hw_init = true;
1558
1559 /* Mark Slave initialization complete */
1560 rt722->hw_init = true;
1561
1562 pm_runtime_mark_last_busy(&slave->dev);
1563 pm_runtime_put_autosuspend(&slave->dev);
1564
1565 dev_dbg(&slave->dev, "%s hw_init complete\n", __func__);
1566 return 0;
1567 }
1568
1569 MODULE_DESCRIPTION("ASoC RT722 SDCA SDW driver");
1570 MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>");
1571 MODULE_LICENSE("GPL");
1572