1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * rt715.c -- rt715 ALSA SoC audio driver 4 * 5 * Copyright(c) 2019 Realtek Semiconductor Corp. 6 * 7 * ALC715 ASoC Codec Driver based Intel Dummy SdW codec driver 8 * 9 */ 10 11 #include <linux/module.h> 12 #include <linux/kernel.h> 13 #include <linux/init.h> 14 #include <linux/delay.h> 15 #include <linux/i2c.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/pm.h> 18 #include <linux/soundwire/sdw.h> 19 #include <linux/regmap.h> 20 #include <linux/slab.h> 21 #include <linux/platform_device.h> 22 #include <linux/regulator/consumer.h> 23 #include <sound/core.h> 24 #include <sound/pcm.h> 25 #include <sound/pcm_params.h> 26 #include <sound/sdw.h> 27 #include <sound/soc.h> 28 #include <sound/soc-dapm.h> 29 #include <sound/initval.h> 30 #include <sound/tlv.h> 31 #include <sound/hda_verbs.h> 32 33 #include "rt715.h" 34 35 static int rt715_index_write(struct regmap *regmap, unsigned int reg, 36 unsigned int value) 37 { 38 int ret; 39 unsigned int addr = ((RT715_PRIV_INDEX_W_H) << 8) | reg; 40 41 ret = regmap_write(regmap, addr, value); 42 if (ret < 0) { 43 pr_err("%s: Failed to set private value: %08x <= %04x %d\n", 44 __func__, addr, value, ret); 45 } 46 47 return ret; 48 } 49 50 static int rt715_index_write_nid(struct regmap *regmap, 51 unsigned int nid, unsigned int reg, unsigned int value) 52 { 53 int ret; 54 unsigned int addr = ((RT715_PRIV_INDEX_W_H_2 | nid) << 8) | reg; 55 56 ret = regmap_write(regmap, addr, value); 57 if (ret < 0) 58 pr_err("%s: Failed to set private value: %06x <= %04x ret=%d\n", 59 __func__, addr, value, ret); 60 61 return ret; 62 } 63 64 static int rt715_index_read_nid(struct regmap *regmap, 65 unsigned int nid, unsigned int reg, unsigned int *value) 66 { 67 int ret; 68 unsigned int addr = ((RT715_PRIV_INDEX_W_H_2 | nid) << 8) | reg; 69 70 *value = 0; 71 ret = regmap_read(regmap, addr, value); 72 if (ret < 0) 73 pr_err("%s: Failed to get private value: %06x => %04x ret=%d\n", 74 __func__, addr, *value, ret); 75 76 return ret; 77 } 78 79 static int rt715_index_update_bits(struct regmap *regmap, unsigned int nid, 80 unsigned int reg, unsigned int mask, unsigned int val) 81 { 82 unsigned int tmp, orig; 83 int ret; 84 85 ret = rt715_index_read_nid(regmap, nid, reg, &orig); 86 if (ret < 0) 87 return ret; 88 89 tmp = orig & ~mask; 90 tmp |= val & mask; 91 92 return rt715_index_write_nid(regmap, nid, reg, tmp); 93 } 94 95 static void rt715_reset(struct regmap *regmap) 96 { 97 regmap_write(regmap, RT715_FUNC_RESET, 0); 98 rt715_index_update_bits(regmap, RT715_VENDOR_REGISTERS, 99 RT715_VD_CLEAR_CTRL, RT715_CLEAR_HIDDEN_REG, 100 RT715_CLEAR_HIDDEN_REG); 101 } 102 103 104 static void rt715_get_gain(struct rt715_priv *rt715, unsigned int addr_h, 105 unsigned int addr_l, unsigned int val_h, 106 unsigned int *r_val, unsigned int *l_val) 107 { 108 int ret; 109 /* R Channel */ 110 *r_val = val_h << 8; 111 ret = regmap_read(rt715->regmap, addr_l, r_val); 112 if (ret < 0) 113 pr_err("Failed to get R channel gain.\n"); 114 115 /* L Channel */ 116 val_h |= 0x20; 117 *l_val = val_h << 8; 118 ret = regmap_read(rt715->regmap, addr_h, l_val); 119 if (ret < 0) 120 pr_err("Failed to get L channel gain.\n"); 121 } 122 123 /* For Verb-Set Amplifier Gain (Verb ID = 3h) */ 124 static int rt715_set_amp_gain_put(struct snd_kcontrol *kcontrol, 125 struct snd_ctl_elem_value *ucontrol) 126 { 127 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 128 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 129 struct soc_mixer_control *mc = 130 (struct soc_mixer_control *)kcontrol->private_value; 131 struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component); 132 unsigned int addr_h, addr_l, val_h, val_ll, val_lr; 133 unsigned int read_ll, read_rl, i; 134 unsigned int k_vol_changed = 0; 135 136 for (i = 0; i < 2; i++) { 137 if (ucontrol->value.integer.value[i] != rt715->kctl_2ch_vol_ori[i]) { 138 k_vol_changed = 1; 139 break; 140 } 141 } 142 143 /* Can't use update bit function, so read the original value first */ 144 addr_h = mc->reg; 145 addr_l = mc->rreg; 146 147 if (mc->shift == RT715_DIR_OUT_SFT) /* output */ 148 val_h = 0x80; 149 else /* input */ 150 val_h = 0x0; 151 152 rt715_get_gain(rt715, addr_h, addr_l, val_h, &read_rl, &read_ll); 153 154 if (snd_soc_dapm_get_bias_level(dapm) <= SND_SOC_BIAS_STANDBY) 155 regmap_write(rt715->regmap, 156 RT715_SET_AUDIO_POWER_STATE, AC_PWRST_D0); 157 158 /* L Channel */ 159 rt715->kctl_2ch_vol_ori[0] = ucontrol->value.integer.value[0]; 160 /* for gain */ 161 val_ll = ((ucontrol->value.integer.value[0]) & 0x7f); 162 if (val_ll > mc->max) 163 val_ll = mc->max; 164 /* keep mute status */ 165 val_ll |= read_ll & 0x80; 166 167 /* R Channel */ 168 rt715->kctl_2ch_vol_ori[1] = ucontrol->value.integer.value[1]; 169 /* for gain */ 170 val_lr = ((ucontrol->value.integer.value[1]) & 0x7f); 171 if (val_lr > mc->max) 172 val_lr = mc->max; 173 /* keep mute status */ 174 val_lr |= read_rl & 0x80; 175 176 for (i = 0; i < 3; i++) { /* retry 3 times at most */ 177 178 if (val_ll == val_lr) { 179 /* Set both L/R channels at the same time */ 180 val_h = (1 << mc->shift) | (3 << 4); 181 regmap_write(rt715->regmap, addr_h, 182 (val_h << 8) | val_ll); 183 regmap_write(rt715->regmap, addr_l, 184 (val_h << 8) | val_ll); 185 } else { 186 /* Lch*/ 187 val_h = (1 << mc->shift) | (1 << 5); 188 regmap_write(rt715->regmap, addr_h, 189 (val_h << 8) | val_ll); 190 /* Rch */ 191 val_h = (1 << mc->shift) | (1 << 4); 192 regmap_write(rt715->regmap, addr_l, 193 (val_h << 8) | val_lr); 194 } 195 /* check result */ 196 if (mc->shift == RT715_DIR_OUT_SFT) /* output */ 197 val_h = 0x80; 198 else /* input */ 199 val_h = 0x0; 200 201 rt715_get_gain(rt715, addr_h, addr_l, val_h, 202 &read_rl, &read_ll); 203 if (read_rl == val_lr && read_ll == val_ll) 204 break; 205 } 206 207 /* D0:power on state, D3: power saving mode */ 208 if (snd_soc_dapm_get_bias_level(dapm) <= SND_SOC_BIAS_STANDBY) 209 regmap_write(rt715->regmap, 210 RT715_SET_AUDIO_POWER_STATE, AC_PWRST_D3); 211 return k_vol_changed; 212 } 213 214 static int rt715_set_amp_gain_get(struct snd_kcontrol *kcontrol, 215 struct snd_ctl_elem_value *ucontrol) 216 { 217 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 218 struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component); 219 struct soc_mixer_control *mc = 220 (struct soc_mixer_control *)kcontrol->private_value; 221 unsigned int addr_h, addr_l, val_h; 222 unsigned int read_ll, read_rl; 223 224 addr_h = mc->reg; 225 addr_l = mc->rreg; 226 if (mc->shift == RT715_DIR_OUT_SFT) /* output */ 227 val_h = 0x80; 228 else /* input */ 229 val_h = 0x0; 230 231 rt715_get_gain(rt715, addr_h, addr_l, val_h, &read_rl, &read_ll); 232 233 if (mc->invert) { 234 /* for mute status */ 235 read_ll = !(read_ll & 0x80); 236 read_rl = !(read_rl & 0x80); 237 } else { 238 /* for gain */ 239 read_ll = read_ll & 0x7f; 240 read_rl = read_rl & 0x7f; 241 } 242 ucontrol->value.integer.value[0] = read_ll; 243 ucontrol->value.integer.value[1] = read_rl; 244 245 return 0; 246 } 247 248 static int rt715_set_main_switch_put(struct snd_kcontrol *kcontrol, 249 struct snd_ctl_elem_value *ucontrol) 250 { 251 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 252 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 253 struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component); 254 static const unsigned int capture_reg_H[] = { 255 RT715_SET_GAIN_MIC_ADC_H, RT715_SET_GAIN_LINE_ADC_H, 256 RT715_SET_GAIN_MIX_ADC_H, RT715_SET_GAIN_MIX_ADC2_H }; 257 static const unsigned int capture_reg_L[] = { 258 RT715_SET_GAIN_MIC_ADC_L, RT715_SET_GAIN_LINE_ADC_L, 259 RT715_SET_GAIN_MIX_ADC_L, RT715_SET_GAIN_MIX_ADC2_L }; 260 unsigned int addr_h, addr_l, val_h = 0x0, val_ll, val_lr; 261 unsigned int k_shift = RT715_DIR_IN_SFT, k_changed = 0; 262 unsigned int read_ll, read_rl, i, j, loop_cnt = 4; 263 264 for (i = 0; i < 8; i++) { 265 if (ucontrol->value.integer.value[i] != rt715->kctl_8ch_switch_ori[i]) 266 k_changed = 1; 267 } 268 269 for (j = 0; j < loop_cnt; j++) { 270 /* Can't use update bit function, so read the original value first */ 271 addr_h = capture_reg_H[j]; 272 addr_l = capture_reg_L[j]; 273 rt715_get_gain(rt715, addr_h, addr_l, val_h, &read_rl, &read_ll); 274 275 if (snd_soc_dapm_get_bias_level(dapm) <= SND_SOC_BIAS_STANDBY) 276 regmap_write(rt715->regmap, 277 RT715_SET_AUDIO_POWER_STATE, AC_PWRST_D0); 278 279 /* L Channel */ 280 /* for mute */ 281 rt715->kctl_8ch_switch_ori[j * 2] = 282 ucontrol->value.integer.value[j * 2]; 283 val_ll = (!ucontrol->value.integer.value[j * 2]) << 7; 284 /* keep gain */ 285 val_ll |= read_ll & 0x7f; 286 287 /* R Channel */ 288 /* for mute */ 289 rt715->kctl_8ch_switch_ori[j * 2 + 1] = 290 ucontrol->value.integer.value[j * 2 + 1]; 291 val_lr = (!ucontrol->value.integer.value[j * 2 + 1]) << 7; 292 /* keep gain */ 293 val_lr |= read_rl & 0x7f; 294 295 for (i = 0; i < 3; i++) { /* retry 3 times at most */ 296 297 if (val_ll == val_lr) { 298 /* Set both L/R channels at the same time */ 299 val_h = (1 << k_shift) | (3 << 4); 300 regmap_write(rt715->regmap, addr_h, 301 (val_h << 8) | val_ll); 302 regmap_write(rt715->regmap, addr_l, 303 (val_h << 8) | val_ll); 304 } else { 305 /* Lch*/ 306 val_h = (1 << k_shift) | (1 << 5); 307 regmap_write(rt715->regmap, addr_h, 308 (val_h << 8) | val_ll); 309 /* Rch */ 310 val_h = (1 << k_shift) | (1 << 4); 311 regmap_write(rt715->regmap, addr_l, 312 (val_h << 8) | val_lr); 313 } 314 val_h = 0x0; 315 rt715_get_gain(rt715, addr_h, addr_l, val_h, 316 &read_rl, &read_ll); 317 if (read_rl == val_lr && read_ll == val_ll) 318 break; 319 } 320 } 321 322 /* D0:power on state, D3: power saving mode */ 323 if (snd_soc_dapm_get_bias_level(dapm) <= SND_SOC_BIAS_STANDBY) 324 regmap_write(rt715->regmap, 325 RT715_SET_AUDIO_POWER_STATE, AC_PWRST_D3); 326 return k_changed; 327 } 328 329 static int rt715_set_main_switch_get(struct snd_kcontrol *kcontrol, 330 struct snd_ctl_elem_value *ucontrol) 331 { 332 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 333 struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component); 334 static const unsigned int capture_reg_H[] = { 335 RT715_SET_GAIN_MIC_ADC_H, RT715_SET_GAIN_LINE_ADC_H, 336 RT715_SET_GAIN_MIX_ADC_H, RT715_SET_GAIN_MIX_ADC2_H }; 337 static const unsigned int capture_reg_L[] = { 338 RT715_SET_GAIN_MIC_ADC_L, RT715_SET_GAIN_LINE_ADC_L, 339 RT715_SET_GAIN_MIX_ADC_L, RT715_SET_GAIN_MIX_ADC2_L }; 340 unsigned int addr_h, addr_l, val_h = 0x0, i, loop_cnt = 4; 341 unsigned int read_ll, read_rl; 342 343 for (i = 0; i < loop_cnt; i++) { 344 addr_h = capture_reg_H[i]; 345 addr_l = capture_reg_L[i]; 346 rt715_get_gain(rt715, addr_h, addr_l, val_h, &read_rl, &read_ll); 347 348 ucontrol->value.integer.value[i * 2] = !(read_ll & 0x80); 349 ucontrol->value.integer.value[i * 2 + 1] = !(read_rl & 0x80); 350 } 351 352 return 0; 353 } 354 355 static int rt715_set_main_vol_put(struct snd_kcontrol *kcontrol, 356 struct snd_ctl_elem_value *ucontrol) 357 { 358 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 359 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 360 struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component); 361 static const unsigned int capture_reg_H[] = { 362 RT715_SET_GAIN_MIC_ADC_H, RT715_SET_GAIN_LINE_ADC_H, 363 RT715_SET_GAIN_MIX_ADC_H, RT715_SET_GAIN_MIX_ADC2_H }; 364 static const unsigned int capture_reg_L[] = { 365 RT715_SET_GAIN_MIC_ADC_L, RT715_SET_GAIN_LINE_ADC_L, 366 RT715_SET_GAIN_MIX_ADC_L, RT715_SET_GAIN_MIX_ADC2_L}; 367 unsigned int addr_h, addr_l, val_h = 0x0, val_ll, val_lr; 368 unsigned int read_ll, read_rl, i, j, loop_cnt = 4, k_changed = 0; 369 unsigned int k_shift = RT715_DIR_IN_SFT, k_max = 0x3f; 370 371 for (i = 0; i < 8; i++) { 372 if (ucontrol->value.integer.value[i] != rt715->kctl_8ch_vol_ori[i]) 373 k_changed = 1; 374 } 375 376 for (j = 0; j < loop_cnt; j++) { 377 addr_h = capture_reg_H[j]; 378 addr_l = capture_reg_L[j]; 379 rt715_get_gain(rt715, addr_h, addr_l, val_h, &read_rl, &read_ll); 380 381 if (snd_soc_dapm_get_bias_level(dapm) <= SND_SOC_BIAS_STANDBY) 382 regmap_write(rt715->regmap, 383 RT715_SET_AUDIO_POWER_STATE, AC_PWRST_D0); 384 385 /* L Channel */ 386 /* for gain */ 387 rt715->kctl_8ch_vol_ori[j * 2] = ucontrol->value.integer.value[j * 2]; 388 val_ll = ((ucontrol->value.integer.value[j * 2]) & 0x7f); 389 if (val_ll > k_max) 390 val_ll = k_max; 391 /* keep mute status */ 392 val_ll |= read_ll & 0x80; 393 394 /* R Channel */ 395 /* for gain */ 396 rt715->kctl_8ch_vol_ori[j * 2 + 1] = 397 ucontrol->value.integer.value[j * 2 + 1]; 398 val_lr = ((ucontrol->value.integer.value[j * 2 + 1]) & 0x7f); 399 if (val_lr > k_max) 400 val_lr = k_max; 401 /* keep mute status */ 402 val_lr |= read_rl & 0x80; 403 404 for (i = 0; i < 3; i++) { /* retry 3 times at most */ 405 if (val_ll == val_lr) { 406 /* Set both L/R channels at the same time */ 407 val_h = (1 << k_shift) | (3 << 4); 408 regmap_write(rt715->regmap, addr_h, 409 (val_h << 8) | val_ll); 410 regmap_write(rt715->regmap, addr_l, 411 (val_h << 8) | val_ll); 412 } else { 413 /* Lch*/ 414 val_h = (1 << k_shift) | (1 << 5); 415 regmap_write(rt715->regmap, addr_h, 416 (val_h << 8) | val_ll); 417 /* Rch */ 418 val_h = (1 << k_shift) | (1 << 4); 419 regmap_write(rt715->regmap, addr_l, 420 (val_h << 8) | val_lr); 421 } 422 val_h = 0x0; 423 rt715_get_gain(rt715, addr_h, addr_l, val_h, 424 &read_rl, &read_ll); 425 if (read_rl == val_lr && read_ll == val_ll) 426 break; 427 } 428 } 429 430 /* D0:power on state, D3: power saving mode */ 431 if (snd_soc_dapm_get_bias_level(dapm) <= SND_SOC_BIAS_STANDBY) 432 regmap_write(rt715->regmap, 433 RT715_SET_AUDIO_POWER_STATE, AC_PWRST_D3); 434 return k_changed; 435 } 436 437 static int rt715_set_main_vol_get(struct snd_kcontrol *kcontrol, 438 struct snd_ctl_elem_value *ucontrol) 439 { 440 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 441 struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component); 442 static const unsigned int capture_reg_H[] = { 443 RT715_SET_GAIN_MIC_ADC_H, RT715_SET_GAIN_LINE_ADC_H, 444 RT715_SET_GAIN_MIX_ADC_H, RT715_SET_GAIN_MIX_ADC2_H }; 445 static const unsigned int capture_reg_L[] = { 446 RT715_SET_GAIN_MIC_ADC_L, RT715_SET_GAIN_LINE_ADC_L, 447 RT715_SET_GAIN_MIX_ADC_L, RT715_SET_GAIN_MIX_ADC2_L }; 448 unsigned int addr_h, addr_l, val_h = 0x0, i, loop_cnt = 4; 449 unsigned int read_ll, read_rl; 450 451 for (i = 0; i < loop_cnt; i++) { 452 addr_h = capture_reg_H[i]; 453 addr_l = capture_reg_L[i]; 454 rt715_get_gain(rt715, addr_h, addr_l, val_h, &read_rl, &read_ll); 455 456 ucontrol->value.integer.value[i * 2] = read_ll & 0x7f; 457 ucontrol->value.integer.value[i * 2 + 1] = read_rl & 0x7f; 458 } 459 460 return 0; 461 } 462 463 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -1725, 75, 0); 464 static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0); 465 466 static int rt715_switch_info(struct snd_kcontrol *kcontrol, 467 struct snd_ctl_elem_info *uinfo) 468 { 469 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 470 uinfo->count = 8; 471 uinfo->value.integer.min = 0; 472 uinfo->value.integer.max = 1; 473 return 0; 474 } 475 476 static int rt715_vol_info(struct snd_kcontrol *kcontrol, 477 struct snd_ctl_elem_info *uinfo) 478 { 479 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 480 uinfo->count = 8; 481 uinfo->value.integer.min = 0; 482 uinfo->value.integer.max = 0x3f; 483 return 0; 484 } 485 486 #define RT715_MAIN_SWITCH_EXT(xname, xhandler_get, xhandler_put) \ 487 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ 488 .info = rt715_switch_info, \ 489 .get = xhandler_get, .put = xhandler_put, \ 490 } 491 492 #define RT715_MAIN_VOL_EXT_TLV(xname, xhandler_get, xhandler_put, tlv_array) \ 493 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ 494 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ 495 SNDRV_CTL_ELEM_ACCESS_READWRITE, \ 496 .tlv.p = (tlv_array), \ 497 .info = rt715_vol_info, \ 498 .get = xhandler_get, .put = xhandler_put, \ 499 } 500 501 static const struct snd_kcontrol_new rt715_snd_controls[] = { 502 /* Capture switch */ 503 RT715_MAIN_SWITCH_EXT("Capture Switch", 504 rt715_set_main_switch_get, rt715_set_main_switch_put), 505 /* Volume Control */ 506 RT715_MAIN_VOL_EXT_TLV("Capture Volume", 507 rt715_set_main_vol_get, rt715_set_main_vol_put, in_vol_tlv), 508 /* MIC Boost Control */ 509 SOC_DOUBLE_R_EXT_TLV("DMIC1 Boost", RT715_SET_GAIN_DMIC1_H, 510 RT715_SET_GAIN_DMIC1_L, RT715_DIR_IN_SFT, 3, 0, 511 rt715_set_amp_gain_get, rt715_set_amp_gain_put, 512 mic_vol_tlv), 513 SOC_DOUBLE_R_EXT_TLV("DMIC2 Boost", RT715_SET_GAIN_DMIC2_H, 514 RT715_SET_GAIN_DMIC2_L, RT715_DIR_IN_SFT, 3, 0, 515 rt715_set_amp_gain_get, rt715_set_amp_gain_put, 516 mic_vol_tlv), 517 SOC_DOUBLE_R_EXT_TLV("DMIC3 Boost", RT715_SET_GAIN_DMIC3_H, 518 RT715_SET_GAIN_DMIC3_L, RT715_DIR_IN_SFT, 3, 0, 519 rt715_set_amp_gain_get, rt715_set_amp_gain_put, 520 mic_vol_tlv), 521 SOC_DOUBLE_R_EXT_TLV("DMIC4 Boost", RT715_SET_GAIN_DMIC4_H, 522 RT715_SET_GAIN_DMIC4_L, RT715_DIR_IN_SFT, 3, 0, 523 rt715_set_amp_gain_get, rt715_set_amp_gain_put, 524 mic_vol_tlv), 525 SOC_DOUBLE_R_EXT_TLV("MIC1 Boost", RT715_SET_GAIN_MIC1_H, 526 RT715_SET_GAIN_MIC1_L, RT715_DIR_IN_SFT, 3, 0, 527 rt715_set_amp_gain_get, rt715_set_amp_gain_put, 528 mic_vol_tlv), 529 SOC_DOUBLE_R_EXT_TLV("MIC2 Boost", RT715_SET_GAIN_MIC2_H, 530 RT715_SET_GAIN_MIC2_L, RT715_DIR_IN_SFT, 3, 0, 531 rt715_set_amp_gain_get, rt715_set_amp_gain_put, 532 mic_vol_tlv), 533 SOC_DOUBLE_R_EXT_TLV("LINE1 Boost", RT715_SET_GAIN_LINE1_H, 534 RT715_SET_GAIN_LINE1_L, RT715_DIR_IN_SFT, 3, 0, 535 rt715_set_amp_gain_get, rt715_set_amp_gain_put, 536 mic_vol_tlv), 537 SOC_DOUBLE_R_EXT_TLV("LINE2 Boost", RT715_SET_GAIN_LINE2_H, 538 RT715_SET_GAIN_LINE2_L, RT715_DIR_IN_SFT, 3, 0, 539 rt715_set_amp_gain_get, rt715_set_amp_gain_put, 540 mic_vol_tlv), 541 }; 542 543 static int rt715_mux_get(struct snd_kcontrol *kcontrol, 544 struct snd_ctl_elem_value *ucontrol) 545 { 546 struct snd_soc_component *component = snd_soc_dapm_kcontrol_to_component(kcontrol); 547 struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component); 548 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 549 unsigned int reg, val; 550 int ret; 551 552 /* nid = e->reg, vid = 0xf01 */ 553 reg = RT715_VERB_SET_CONNECT_SEL | e->reg; 554 ret = regmap_read(rt715->regmap, reg, &val); 555 if (ret < 0) { 556 dev_err(component->dev, "%s: sdw read failed: %d\n", 557 __func__, ret); 558 return ret; 559 } 560 561 /* 562 * The first two indices of ADC Mux 24/25 are routed to the same 563 * hardware source. ie, ADC Mux 24 0/1 will both connect to MIC2. 564 * To have a unique set of inputs, we skip the index1 of the muxes. 565 */ 566 if ((e->reg == RT715_MUX_IN3 || e->reg == RT715_MUX_IN4) && (val > 0)) 567 val -= 1; 568 ucontrol->value.enumerated.item[0] = val; 569 570 return 0; 571 } 572 573 static int rt715_mux_put(struct snd_kcontrol *kcontrol, 574 struct snd_ctl_elem_value *ucontrol) 575 { 576 struct snd_soc_component *component = snd_soc_dapm_kcontrol_to_component(kcontrol); 577 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_to_dapm(kcontrol); 578 struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component); 579 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 580 unsigned int *item = ucontrol->value.enumerated.item; 581 unsigned int val, val2 = 0, change, reg; 582 int ret; 583 584 if (item[0] >= e->items) 585 return -EINVAL; 586 587 /* Verb ID = 0x701h, nid = e->reg */ 588 val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l; 589 590 reg = RT715_VERB_SET_CONNECT_SEL | e->reg; 591 ret = regmap_read(rt715->regmap, reg, &val2); 592 if (ret < 0) { 593 dev_err(component->dev, "%s: sdw read failed: %d\n", 594 __func__, ret); 595 return ret; 596 } 597 598 if (val == val2) 599 change = 0; 600 else 601 change = 1; 602 603 if (change) { 604 reg = RT715_VERB_SET_CONNECT_SEL | e->reg; 605 regmap_write(rt715->regmap, reg, val); 606 } 607 608 snd_soc_dapm_mux_update_power(dapm, kcontrol, 609 item[0], e, NULL); 610 611 return change; 612 } 613 614 static const char * const adc_22_23_mux_text[] = { 615 "MIC1", 616 "MIC2", 617 "LINE1", 618 "LINE2", 619 "DMIC1", 620 "DMIC2", 621 "DMIC3", 622 "DMIC4", 623 }; 624 625 /* 626 * Due to mux design for nid 24 (MUX_IN3)/25 (MUX_IN4), connection index 0 and 627 * 1 will be connected to the same dmic source, therefore we skip index 1 to 628 * avoid misunderstanding on usage of dapm routing. 629 */ 630 static const unsigned int rt715_adc_24_25_values[] = { 631 0, 632 2, 633 3, 634 4, 635 5, 636 }; 637 638 static const char * const adc_24_mux_text[] = { 639 "MIC2", 640 "DMIC1", 641 "DMIC2", 642 "DMIC3", 643 "DMIC4", 644 }; 645 646 static const char * const adc_25_mux_text[] = { 647 "MIC1", 648 "DMIC1", 649 "DMIC2", 650 "DMIC3", 651 "DMIC4", 652 }; 653 654 static SOC_ENUM_SINGLE_DECL( 655 rt715_adc22_enum, RT715_MUX_IN1, 0, adc_22_23_mux_text); 656 657 static SOC_ENUM_SINGLE_DECL( 658 rt715_adc23_enum, RT715_MUX_IN2, 0, adc_22_23_mux_text); 659 660 static SOC_VALUE_ENUM_SINGLE_DECL(rt715_adc24_enum, 661 RT715_MUX_IN3, 0, 0xf, 662 adc_24_mux_text, rt715_adc_24_25_values); 663 664 static SOC_VALUE_ENUM_SINGLE_DECL(rt715_adc25_enum, 665 RT715_MUX_IN4, 0, 0xf, 666 adc_25_mux_text, rt715_adc_24_25_values); 667 668 static const struct snd_kcontrol_new rt715_adc22_mux = 669 SOC_DAPM_ENUM_EXT("ADC 22 Mux", rt715_adc22_enum, 670 rt715_mux_get, rt715_mux_put); 671 672 static const struct snd_kcontrol_new rt715_adc23_mux = 673 SOC_DAPM_ENUM_EXT("ADC 23 Mux", rt715_adc23_enum, 674 rt715_mux_get, rt715_mux_put); 675 676 static const struct snd_kcontrol_new rt715_adc24_mux = 677 SOC_DAPM_ENUM_EXT("ADC 24 Mux", rt715_adc24_enum, 678 rt715_mux_get, rt715_mux_put); 679 680 static const struct snd_kcontrol_new rt715_adc25_mux = 681 SOC_DAPM_ENUM_EXT("ADC 25 Mux", rt715_adc25_enum, 682 rt715_mux_get, rt715_mux_put); 683 684 static const struct snd_soc_dapm_widget rt715_dapm_widgets[] = { 685 SND_SOC_DAPM_INPUT("DMIC1"), 686 SND_SOC_DAPM_INPUT("DMIC2"), 687 SND_SOC_DAPM_INPUT("DMIC3"), 688 SND_SOC_DAPM_INPUT("DMIC4"), 689 SND_SOC_DAPM_INPUT("MIC1"), 690 SND_SOC_DAPM_INPUT("MIC2"), 691 SND_SOC_DAPM_INPUT("LINE1"), 692 SND_SOC_DAPM_INPUT("LINE2"), 693 SND_SOC_DAPM_ADC("ADC 07", NULL, RT715_SET_STREAMID_MIC_ADC, 4, 0), 694 SND_SOC_DAPM_ADC("ADC 08", NULL, RT715_SET_STREAMID_LINE_ADC, 4, 0), 695 SND_SOC_DAPM_ADC("ADC 09", NULL, RT715_SET_STREAMID_MIX_ADC, 4, 0), 696 SND_SOC_DAPM_ADC("ADC 27", NULL, RT715_SET_STREAMID_MIX_ADC2, 4, 0), 697 SND_SOC_DAPM_MUX("ADC 22 Mux", SND_SOC_NOPM, 0, 0, 698 &rt715_adc22_mux), 699 SND_SOC_DAPM_MUX("ADC 23 Mux", SND_SOC_NOPM, 0, 0, 700 &rt715_adc23_mux), 701 SND_SOC_DAPM_MUX("ADC 24 Mux", SND_SOC_NOPM, 0, 0, 702 &rt715_adc24_mux), 703 SND_SOC_DAPM_MUX("ADC 25 Mux", SND_SOC_NOPM, 0, 0, 704 &rt715_adc25_mux), 705 SND_SOC_DAPM_AIF_OUT("DP4TX", "DP4 Capture", 0, SND_SOC_NOPM, 0, 0), 706 SND_SOC_DAPM_AIF_OUT("DP6TX", "DP6 Capture", 0, SND_SOC_NOPM, 0, 0), 707 }; 708 709 static const struct snd_soc_dapm_route rt715_audio_map[] = { 710 {"DP6TX", NULL, "ADC 09"}, 711 {"DP6TX", NULL, "ADC 08"}, 712 {"DP4TX", NULL, "ADC 07"}, 713 {"DP4TX", NULL, "ADC 27"}, 714 {"ADC 09", NULL, "ADC 22 Mux"}, 715 {"ADC 08", NULL, "ADC 23 Mux"}, 716 {"ADC 07", NULL, "ADC 24 Mux"}, 717 {"ADC 27", NULL, "ADC 25 Mux"}, 718 {"ADC 22 Mux", "MIC1", "MIC1"}, 719 {"ADC 22 Mux", "MIC2", "MIC2"}, 720 {"ADC 22 Mux", "LINE1", "LINE1"}, 721 {"ADC 22 Mux", "LINE2", "LINE2"}, 722 {"ADC 22 Mux", "DMIC1", "DMIC1"}, 723 {"ADC 22 Mux", "DMIC2", "DMIC2"}, 724 {"ADC 22 Mux", "DMIC3", "DMIC3"}, 725 {"ADC 22 Mux", "DMIC4", "DMIC4"}, 726 {"ADC 23 Mux", "MIC1", "MIC1"}, 727 {"ADC 23 Mux", "MIC2", "MIC2"}, 728 {"ADC 23 Mux", "LINE1", "LINE1"}, 729 {"ADC 23 Mux", "LINE2", "LINE2"}, 730 {"ADC 23 Mux", "DMIC1", "DMIC1"}, 731 {"ADC 23 Mux", "DMIC2", "DMIC2"}, 732 {"ADC 23 Mux", "DMIC3", "DMIC3"}, 733 {"ADC 23 Mux", "DMIC4", "DMIC4"}, 734 {"ADC 24 Mux", "MIC2", "MIC2"}, 735 {"ADC 24 Mux", "DMIC1", "DMIC1"}, 736 {"ADC 24 Mux", "DMIC2", "DMIC2"}, 737 {"ADC 24 Mux", "DMIC3", "DMIC3"}, 738 {"ADC 24 Mux", "DMIC4", "DMIC4"}, 739 {"ADC 25 Mux", "MIC1", "MIC1"}, 740 {"ADC 25 Mux", "DMIC1", "DMIC1"}, 741 {"ADC 25 Mux", "DMIC2", "DMIC2"}, 742 {"ADC 25 Mux", "DMIC3", "DMIC3"}, 743 {"ADC 25 Mux", "DMIC4", "DMIC4"}, 744 }; 745 746 static int rt715_set_bias_level(struct snd_soc_component *component, 747 enum snd_soc_bias_level level) 748 { 749 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 750 struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component); 751 752 switch (level) { 753 case SND_SOC_BIAS_PREPARE: 754 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_STANDBY) { 755 regmap_write(rt715->regmap, 756 RT715_SET_AUDIO_POWER_STATE, 757 AC_PWRST_D0); 758 msleep(RT715_POWER_UP_DELAY_MS); 759 } 760 break; 761 762 case SND_SOC_BIAS_STANDBY: 763 regmap_write(rt715->regmap, 764 RT715_SET_AUDIO_POWER_STATE, 765 AC_PWRST_D3); 766 break; 767 768 default: 769 break; 770 } 771 772 return 0; 773 } 774 775 static int rt715_probe(struct snd_soc_component *component) 776 { 777 struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component); 778 int ret; 779 780 if (!rt715->first_hw_init) 781 return 0; 782 783 ret = pm_runtime_resume(component->dev); 784 if (ret < 0 && ret != -EACCES) 785 return ret; 786 787 return 0; 788 } 789 790 static const struct snd_soc_component_driver soc_codec_dev_rt715 = { 791 .probe = rt715_probe, 792 .set_bias_level = rt715_set_bias_level, 793 .controls = rt715_snd_controls, 794 .num_controls = ARRAY_SIZE(rt715_snd_controls), 795 .dapm_widgets = rt715_dapm_widgets, 796 .num_dapm_widgets = ARRAY_SIZE(rt715_dapm_widgets), 797 .dapm_routes = rt715_audio_map, 798 .num_dapm_routes = ARRAY_SIZE(rt715_audio_map), 799 .endianness = 1, 800 }; 801 802 static int rt715_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream, 803 int direction) 804 { 805 806 snd_soc_dai_dma_data_set(dai, direction, sdw_stream); 807 808 return 0; 809 } 810 811 static void rt715_shutdown(struct snd_pcm_substream *substream, 812 struct snd_soc_dai *dai) 813 814 { 815 snd_soc_dai_set_dma_data(dai, substream, NULL); 816 } 817 818 static int rt715_pcm_hw_params(struct snd_pcm_substream *substream, 819 struct snd_pcm_hw_params *params, 820 struct snd_soc_dai *dai) 821 { 822 struct snd_soc_component *component = dai->component; 823 struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component); 824 struct sdw_stream_config stream_config = {0}; 825 struct sdw_port_config port_config = {0}; 826 struct sdw_stream_runtime *sdw_stream; 827 int retval; 828 unsigned int val = 0; 829 830 sdw_stream = snd_soc_dai_get_dma_data(dai, substream); 831 832 if (!sdw_stream) 833 return -EINVAL; 834 835 if (!rt715->slave) 836 return -EINVAL; 837 838 snd_sdw_params_to_config(substream, params, &stream_config, &port_config); 839 840 switch (dai->id) { 841 case RT715_AIF1: 842 port_config.num = 6; 843 rt715_index_write(rt715->regmap, RT715_SDW_INPUT_SEL, 0xa500); 844 break; 845 case RT715_AIF2: 846 port_config.num = 4; 847 rt715_index_write(rt715->regmap, RT715_SDW_INPUT_SEL, 0xa000); 848 break; 849 default: 850 dev_err(component->dev, "%s: Invalid DAI id %d\n", __func__, dai->id); 851 return -EINVAL; 852 } 853 854 retval = sdw_stream_add_slave(rt715->slave, &stream_config, 855 &port_config, 1, sdw_stream); 856 if (retval) { 857 dev_err(dai->dev, "%s: Unable to configure port\n", __func__); 858 return retval; 859 } 860 861 switch (params_rate(params)) { 862 /* bit 14 0:48K 1:44.1K */ 863 /* bit 15 Stream Type 0:PCM 1:Non-PCM, should always be PCM */ 864 case 44100: 865 val |= 0x40 << 8; 866 break; 867 case 48000: 868 val |= 0x0 << 8; 869 break; 870 default: 871 dev_err(component->dev, "%s: Unsupported sample rate %d\n", 872 __func__, params_rate(params)); 873 return -EINVAL; 874 } 875 876 if (params_channels(params) <= 16) { 877 /* bit 3:0 Number of Channel */ 878 val |= (params_channels(params) - 1); 879 } else { 880 dev_err(component->dev, "%s: Unsupported channels %d\n", 881 __func__, params_channels(params)); 882 return -EINVAL; 883 } 884 885 switch (params_width(params)) { 886 /* bit 6:4 Bits per Sample */ 887 case 8: 888 break; 889 case 16: 890 val |= (0x1 << 4); 891 break; 892 case 20: 893 val |= (0x2 << 4); 894 break; 895 case 24: 896 val |= (0x3 << 4); 897 break; 898 case 32: 899 val |= (0x4 << 4); 900 break; 901 default: 902 return -EINVAL; 903 } 904 905 regmap_write(rt715->regmap, RT715_MIC_ADC_FORMAT_H, val); 906 regmap_write(rt715->regmap, RT715_MIC_LINE_FORMAT_H, val); 907 regmap_write(rt715->regmap, RT715_MIX_ADC_FORMAT_H, val); 908 regmap_write(rt715->regmap, RT715_MIX_ADC2_FORMAT_H, val); 909 910 return retval; 911 } 912 913 static int rt715_pcm_hw_free(struct snd_pcm_substream *substream, 914 struct snd_soc_dai *dai) 915 { 916 struct snd_soc_component *component = dai->component; 917 struct rt715_priv *rt715 = snd_soc_component_get_drvdata(component); 918 struct sdw_stream_runtime *sdw_stream = 919 snd_soc_dai_get_dma_data(dai, substream); 920 921 if (!rt715->slave) 922 return -EINVAL; 923 924 sdw_stream_remove_slave(rt715->slave, sdw_stream); 925 return 0; 926 } 927 928 #define RT715_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) 929 #define RT715_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 930 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8) 931 932 static const struct snd_soc_dai_ops rt715_ops = { 933 .hw_params = rt715_pcm_hw_params, 934 .hw_free = rt715_pcm_hw_free, 935 .set_stream = rt715_set_sdw_stream, 936 .shutdown = rt715_shutdown, 937 }; 938 939 static struct snd_soc_dai_driver rt715_dai[] = { 940 { 941 .name = "rt715-aif1", 942 .id = RT715_AIF1, 943 .capture = { 944 .stream_name = "DP6 Capture", 945 .channels_min = 1, 946 .channels_max = 2, 947 .rates = RT715_STEREO_RATES, 948 .formats = RT715_FORMATS, 949 }, 950 .ops = &rt715_ops, 951 }, 952 { 953 .name = "rt715-aif2", 954 .id = RT715_AIF2, 955 .capture = { 956 .stream_name = "DP4 Capture", 957 .channels_min = 1, 958 .channels_max = 2, 959 .rates = RT715_STEREO_RATES, 960 .formats = RT715_FORMATS, 961 }, 962 .ops = &rt715_ops, 963 }, 964 }; 965 966 /* Bus clock frequency */ 967 #define RT715_CLK_FREQ_9600000HZ 9600000 968 #define RT715_CLK_FREQ_12000000HZ 12000000 969 #define RT715_CLK_FREQ_6000000HZ 6000000 970 #define RT715_CLK_FREQ_4800000HZ 4800000 971 #define RT715_CLK_FREQ_2400000HZ 2400000 972 #define RT715_CLK_FREQ_12288000HZ 12288000 973 974 int rt715_clock_config(struct device *dev) 975 { 976 struct rt715_priv *rt715 = dev_get_drvdata(dev); 977 unsigned int clk_freq, value; 978 979 clk_freq = (rt715->params.curr_dr_freq >> 1); 980 981 switch (clk_freq) { 982 case RT715_CLK_FREQ_12000000HZ: 983 value = 0x0; 984 break; 985 case RT715_CLK_FREQ_6000000HZ: 986 value = 0x1; 987 break; 988 case RT715_CLK_FREQ_9600000HZ: 989 value = 0x2; 990 break; 991 case RT715_CLK_FREQ_4800000HZ: 992 value = 0x3; 993 break; 994 case RT715_CLK_FREQ_2400000HZ: 995 value = 0x4; 996 break; 997 case RT715_CLK_FREQ_12288000HZ: 998 value = 0x5; 999 break; 1000 default: 1001 return -EINVAL; 1002 } 1003 1004 regmap_write(rt715->regmap, 0xe0, value); 1005 regmap_write(rt715->regmap, 0xf0, value); 1006 1007 return 0; 1008 } 1009 1010 int rt715_init(struct device *dev, struct regmap *sdw_regmap, 1011 struct regmap *regmap, struct sdw_slave *slave) 1012 { 1013 struct rt715_priv *rt715; 1014 int ret; 1015 1016 rt715 = devm_kzalloc(dev, sizeof(*rt715), GFP_KERNEL); 1017 if (!rt715) 1018 return -ENOMEM; 1019 1020 dev_set_drvdata(dev, rt715); 1021 rt715->slave = slave; 1022 rt715->regmap = regmap; 1023 rt715->sdw_regmap = sdw_regmap; 1024 1025 regcache_cache_only(rt715->regmap, true); 1026 1027 /* 1028 * Mark hw_init to false 1029 * HW init will be performed when device reports present 1030 */ 1031 rt715->hw_init = false; 1032 rt715->first_hw_init = false; 1033 1034 ret = devm_snd_soc_register_component(dev, 1035 &soc_codec_dev_rt715, 1036 rt715_dai, 1037 ARRAY_SIZE(rt715_dai)); 1038 if (ret < 0) 1039 return ret; 1040 1041 /* set autosuspend parameters */ 1042 pm_runtime_set_autosuspend_delay(dev, 3000); 1043 pm_runtime_use_autosuspend(dev); 1044 1045 /* make sure the device does not suspend immediately */ 1046 pm_runtime_mark_last_busy(dev); 1047 1048 pm_runtime_enable(dev); 1049 1050 /* important note: the device is NOT tagged as 'active' and will remain 1051 * 'suspended' until the hardware is enumerated/initialized. This is required 1052 * to make sure the ASoC framework use of pm_runtime_get_sync() does not silently 1053 * fail with -EACCESS because of race conditions between card creation and enumeration 1054 */ 1055 1056 return 0; 1057 } 1058 1059 int rt715_io_init(struct device *dev, struct sdw_slave *slave) 1060 { 1061 struct rt715_priv *rt715 = dev_get_drvdata(dev); 1062 1063 if (rt715->hw_init) 1064 return 0; 1065 1066 regcache_cache_only(rt715->regmap, false); 1067 1068 /* 1069 * PM runtime status is marked as 'active' only when a Slave reports as Attached 1070 */ 1071 if (!rt715->first_hw_init) 1072 /* update count of parent 'active' children */ 1073 pm_runtime_set_active(&slave->dev); 1074 1075 pm_runtime_get_noresume(&slave->dev); 1076 1077 rt715_reset(rt715->regmap); 1078 1079 /* Mute nid=08h/09h */ 1080 regmap_write(rt715->regmap, RT715_SET_GAIN_LINE_ADC_H, 0xb080); 1081 regmap_write(rt715->regmap, RT715_SET_GAIN_MIX_ADC_H, 0xb080); 1082 /* Mute nid=07h/27h */ 1083 regmap_write(rt715->regmap, RT715_SET_GAIN_MIC_ADC_H, 0xb080); 1084 regmap_write(rt715->regmap, RT715_SET_GAIN_MIX_ADC2_H, 0xb080); 1085 1086 /* Set Pin Widget */ 1087 regmap_write(rt715->regmap, RT715_SET_PIN_DMIC1, 0x20); 1088 regmap_write(rt715->regmap, RT715_SET_PIN_DMIC2, 0x20); 1089 regmap_write(rt715->regmap, RT715_SET_PIN_DMIC3, 0x20); 1090 regmap_write(rt715->regmap, RT715_SET_PIN_DMIC4, 0x20); 1091 /* Set Converter Stream */ 1092 regmap_write(rt715->regmap, RT715_SET_STREAMID_LINE_ADC, 0x10); 1093 regmap_write(rt715->regmap, RT715_SET_STREAMID_MIX_ADC, 0x10); 1094 regmap_write(rt715->regmap, RT715_SET_STREAMID_MIC_ADC, 0x10); 1095 regmap_write(rt715->regmap, RT715_SET_STREAMID_MIX_ADC2, 0x10); 1096 /* Set Configuration Default */ 1097 regmap_write(rt715->regmap, RT715_SET_DMIC1_CONFIG_DEFAULT1, 0xd0); 1098 regmap_write(rt715->regmap, RT715_SET_DMIC1_CONFIG_DEFAULT2, 0x11); 1099 regmap_write(rt715->regmap, RT715_SET_DMIC1_CONFIG_DEFAULT3, 0xa1); 1100 regmap_write(rt715->regmap, RT715_SET_DMIC1_CONFIG_DEFAULT4, 0x81); 1101 regmap_write(rt715->regmap, RT715_SET_DMIC2_CONFIG_DEFAULT1, 0xd1); 1102 regmap_write(rt715->regmap, RT715_SET_DMIC2_CONFIG_DEFAULT2, 0x11); 1103 regmap_write(rt715->regmap, RT715_SET_DMIC2_CONFIG_DEFAULT3, 0xa1); 1104 regmap_write(rt715->regmap, RT715_SET_DMIC2_CONFIG_DEFAULT4, 0x81); 1105 regmap_write(rt715->regmap, RT715_SET_DMIC3_CONFIG_DEFAULT1, 0xd0); 1106 regmap_write(rt715->regmap, RT715_SET_DMIC3_CONFIG_DEFAULT2, 0x11); 1107 regmap_write(rt715->regmap, RT715_SET_DMIC3_CONFIG_DEFAULT3, 0xa1); 1108 regmap_write(rt715->regmap, RT715_SET_DMIC3_CONFIG_DEFAULT4, 0x81); 1109 regmap_write(rt715->regmap, RT715_SET_DMIC4_CONFIG_DEFAULT1, 0xd1); 1110 regmap_write(rt715->regmap, RT715_SET_DMIC4_CONFIG_DEFAULT2, 0x11); 1111 regmap_write(rt715->regmap, RT715_SET_DMIC4_CONFIG_DEFAULT3, 0xa1); 1112 regmap_write(rt715->regmap, RT715_SET_DMIC4_CONFIG_DEFAULT4, 0x81); 1113 1114 /* Finish Initial Settings, set power to D3 */ 1115 regmap_write(rt715->regmap, RT715_SET_AUDIO_POWER_STATE, AC_PWRST_D3); 1116 1117 if (rt715->first_hw_init) 1118 regcache_mark_dirty(rt715->regmap); 1119 else 1120 rt715->first_hw_init = true; 1121 1122 /* Mark Slave initialization complete */ 1123 rt715->hw_init = true; 1124 1125 pm_runtime_put_autosuspend(&slave->dev); 1126 1127 return 0; 1128 } 1129 1130 MODULE_DESCRIPTION("ASoC rt715 driver"); 1131 MODULE_DESCRIPTION("ASoC rt715 driver SDW"); 1132 MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>"); 1133 MODULE_LICENSE("GPL v2"); 1134