1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * rt5665.c -- RT5665/RT5658 ALSA SoC audio codec driver
4 *
5 * Copyright 2016 Realtek Semiconductor Corp.
6 * Author: Bard Liao <bardliao@realtek.com>
7 */
8
9 #include <linux/module.h>
10 #include <linux/moduleparam.h>
11 #include <linux/init.h>
12 #include <linux/delay.h>
13 #include <linux/pm.h>
14 #include <linux/i2c.h>
15 #include <linux/platform_device.h>
16 #include <linux/spi/spi.h>
17 #include <linux/acpi.h>
18 #include <linux/gpio/consumer.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/mutex.h>
21 #include <sound/core.h>
22 #include <sound/pcm.h>
23 #include <sound/pcm_params.h>
24 #include <sound/jack.h>
25 #include <sound/soc.h>
26 #include <sound/soc-dapm.h>
27 #include <sound/initval.h>
28 #include <sound/tlv.h>
29 #include <sound/rt5665.h>
30
31 #include "rl6231.h"
32 #include "rt5665.h"
33
34 static const char * const rt5665_supply_names[] = {
35 "AVDD",
36 "MICVDD",
37 "VBAT",
38 };
39
40 struct rt5665_priv {
41 struct snd_soc_component *component;
42 struct rt5665_platform_data pdata;
43 struct regmap *regmap;
44 struct gpio_desc *gpiod_ldo1_en;
45 struct gpio_desc *gpiod_reset;
46 struct snd_soc_jack *hs_jack;
47 struct delayed_work jack_detect_work;
48 struct delayed_work calibrate_work;
49 struct delayed_work jd_check_work;
50 struct mutex calibrate_mutex;
51
52 int sysclk;
53 int sysclk_src;
54 int lrck[RT5665_AIFS];
55 int bclk[RT5665_AIFS];
56 int master[RT5665_AIFS];
57 int id;
58
59 int pll_src;
60 int pll_in;
61 int pll_out;
62
63 int jack_type;
64 int irq_work_delay_time;
65 unsigned int sar_adc_value;
66 bool calibration_done;
67 };
68
69 static const struct reg_default rt5665_reg[] = {
70 {0x0000, 0x0000},
71 {0x0001, 0xc8c8},
72 {0x0002, 0x8080},
73 {0x0003, 0x8000},
74 {0x0004, 0xc80a},
75 {0x0005, 0x0000},
76 {0x0006, 0x0000},
77 {0x0007, 0x0000},
78 {0x000a, 0x0000},
79 {0x000b, 0x0000},
80 {0x000c, 0x0000},
81 {0x000d, 0x0000},
82 {0x000f, 0x0808},
83 {0x0010, 0x4040},
84 {0x0011, 0x0000},
85 {0x0012, 0x1404},
86 {0x0013, 0x1000},
87 {0x0014, 0xa00a},
88 {0x0015, 0x0404},
89 {0x0016, 0x0404},
90 {0x0017, 0x0011},
91 {0x0018, 0xafaf},
92 {0x0019, 0xafaf},
93 {0x001a, 0xafaf},
94 {0x001b, 0x0011},
95 {0x001c, 0x2f2f},
96 {0x001d, 0x2f2f},
97 {0x001e, 0x2f2f},
98 {0x001f, 0x0000},
99 {0x0020, 0x0000},
100 {0x0021, 0x0000},
101 {0x0022, 0x5757},
102 {0x0023, 0x0039},
103 {0x0026, 0xc0c0},
104 {0x0027, 0xc0c0},
105 {0x0028, 0xc0c0},
106 {0x0029, 0x8080},
107 {0x002a, 0xaaaa},
108 {0x002b, 0xaaaa},
109 {0x002c, 0xaba8},
110 {0x002d, 0x0000},
111 {0x002e, 0x0000},
112 {0x002f, 0x0000},
113 {0x0030, 0x0000},
114 {0x0031, 0x5000},
115 {0x0032, 0x0000},
116 {0x0033, 0x0000},
117 {0x0034, 0x0000},
118 {0x0035, 0x0000},
119 {0x003a, 0x0000},
120 {0x003b, 0x0000},
121 {0x003c, 0x00ff},
122 {0x003d, 0x0000},
123 {0x003e, 0x00ff},
124 {0x003f, 0x0000},
125 {0x0040, 0x0000},
126 {0x0041, 0x00ff},
127 {0x0042, 0x0000},
128 {0x0043, 0x00ff},
129 {0x0044, 0x0c0c},
130 {0x0049, 0xc00b},
131 {0x004a, 0x0000},
132 {0x004b, 0x031f},
133 {0x004d, 0x0000},
134 {0x004e, 0x001f},
135 {0x004f, 0x0000},
136 {0x0050, 0x001f},
137 {0x0052, 0xf000},
138 {0x0061, 0x0000},
139 {0x0062, 0x0000},
140 {0x0063, 0x003e},
141 {0x0064, 0x0000},
142 {0x0065, 0x0000},
143 {0x0066, 0x003f},
144 {0x0067, 0x0000},
145 {0x006b, 0x0000},
146 {0x006d, 0xff00},
147 {0x006e, 0x2808},
148 {0x006f, 0x000a},
149 {0x0070, 0x8000},
150 {0x0071, 0x8000},
151 {0x0072, 0x8000},
152 {0x0073, 0x7000},
153 {0x0074, 0x7770},
154 {0x0075, 0x0002},
155 {0x0076, 0x0001},
156 {0x0078, 0x00f0},
157 {0x0079, 0x0000},
158 {0x007a, 0x0000},
159 {0x007b, 0x0000},
160 {0x007c, 0x0000},
161 {0x007d, 0x0123},
162 {0x007e, 0x4500},
163 {0x007f, 0x8003},
164 {0x0080, 0x0000},
165 {0x0081, 0x0000},
166 {0x0082, 0x0000},
167 {0x0083, 0x0000},
168 {0x0084, 0x0000},
169 {0x0085, 0x0000},
170 {0x0086, 0x0008},
171 {0x0087, 0x0000},
172 {0x0088, 0x0000},
173 {0x0089, 0x0000},
174 {0x008a, 0x0000},
175 {0x008b, 0x0000},
176 {0x008c, 0x0003},
177 {0x008e, 0x0060},
178 {0x008f, 0x1000},
179 {0x0091, 0x0c26},
180 {0x0092, 0x0073},
181 {0x0093, 0x0000},
182 {0x0094, 0x0080},
183 {0x0098, 0x0000},
184 {0x0099, 0x0000},
185 {0x009a, 0x0007},
186 {0x009f, 0x0000},
187 {0x00a0, 0x0000},
188 {0x00a1, 0x0002},
189 {0x00a2, 0x0001},
190 {0x00a3, 0x0002},
191 {0x00a4, 0x0001},
192 {0x00ae, 0x2040},
193 {0x00af, 0x0000},
194 {0x00b6, 0x0000},
195 {0x00b7, 0x0000},
196 {0x00b8, 0x0000},
197 {0x00b9, 0x0000},
198 {0x00ba, 0x0002},
199 {0x00bb, 0x0000},
200 {0x00be, 0x0000},
201 {0x00c0, 0x0000},
202 {0x00c1, 0x0aaa},
203 {0x00c2, 0xaa80},
204 {0x00c3, 0x0003},
205 {0x00c4, 0x0000},
206 {0x00d0, 0x0000},
207 {0x00d1, 0x2244},
208 {0x00d3, 0x3300},
209 {0x00d4, 0x2200},
210 {0x00d9, 0x0809},
211 {0x00da, 0x0000},
212 {0x00db, 0x0008},
213 {0x00dc, 0x00c0},
214 {0x00dd, 0x6724},
215 {0x00de, 0x3131},
216 {0x00df, 0x0008},
217 {0x00e0, 0x4000},
218 {0x00e1, 0x3131},
219 {0x00e2, 0x600c},
220 {0x00ea, 0xb320},
221 {0x00eb, 0x0000},
222 {0x00ec, 0xb300},
223 {0x00ed, 0x0000},
224 {0x00ee, 0xb320},
225 {0x00ef, 0x0000},
226 {0x00f0, 0x0201},
227 {0x00f1, 0x0ddd},
228 {0x00f2, 0x0ddd},
229 {0x00f6, 0x0000},
230 {0x00f7, 0x0000},
231 {0x00f8, 0x0000},
232 {0x00fa, 0x0000},
233 {0x00fb, 0x0000},
234 {0x00fc, 0x0000},
235 {0x00fd, 0x0000},
236 {0x00fe, 0x10ec},
237 {0x00ff, 0x6451},
238 {0x0100, 0xaaaa},
239 {0x0101, 0x000a},
240 {0x010a, 0xaaaa},
241 {0x010b, 0xa0a0},
242 {0x010c, 0xaeae},
243 {0x010d, 0xaaaa},
244 {0x010e, 0xaaaa},
245 {0x010f, 0xaaaa},
246 {0x0110, 0xe002},
247 {0x0111, 0xa402},
248 {0x0112, 0xaaaa},
249 {0x0113, 0x2000},
250 {0x0117, 0x0f00},
251 {0x0125, 0x0410},
252 {0x0132, 0x0000},
253 {0x0133, 0x0000},
254 {0x0137, 0x5540},
255 {0x0138, 0x3700},
256 {0x0139, 0x79a1},
257 {0x013a, 0x2020},
258 {0x013b, 0x2020},
259 {0x013c, 0x2005},
260 {0x013f, 0x0000},
261 {0x0145, 0x0002},
262 {0x0146, 0x0000},
263 {0x0147, 0x0000},
264 {0x0148, 0x0000},
265 {0x0150, 0x0000},
266 {0x0160, 0x4eff},
267 {0x0161, 0x0080},
268 {0x0162, 0x0200},
269 {0x0163, 0x0800},
270 {0x0164, 0x0000},
271 {0x0165, 0x0000},
272 {0x0166, 0x0000},
273 {0x0167, 0x000f},
274 {0x0170, 0x4e87},
275 {0x0171, 0x0080},
276 {0x0172, 0x0200},
277 {0x0173, 0x0800},
278 {0x0174, 0x00ff},
279 {0x0175, 0x0000},
280 {0x0190, 0x413d},
281 {0x0191, 0x4139},
282 {0x0192, 0x4135},
283 {0x0193, 0x413d},
284 {0x0194, 0x0000},
285 {0x0195, 0x0000},
286 {0x0196, 0x0000},
287 {0x0197, 0x0000},
288 {0x0198, 0x0000},
289 {0x0199, 0x0000},
290 {0x01a0, 0x1e64},
291 {0x01a1, 0x06a3},
292 {0x01a2, 0x0000},
293 {0x01a3, 0x0000},
294 {0x01a4, 0x0000},
295 {0x01a5, 0x0000},
296 {0x01a6, 0x0000},
297 {0x01a7, 0x8000},
298 {0x01a8, 0x0000},
299 {0x01a9, 0x0000},
300 {0x01aa, 0x0000},
301 {0x01ab, 0x0000},
302 {0x01b5, 0x0000},
303 {0x01b6, 0x01c3},
304 {0x01b7, 0x02a0},
305 {0x01b8, 0x03e9},
306 {0x01b9, 0x1389},
307 {0x01ba, 0xc351},
308 {0x01bb, 0x0009},
309 {0x01bc, 0x0018},
310 {0x01bd, 0x002a},
311 {0x01be, 0x004c},
312 {0x01bf, 0x0097},
313 {0x01c0, 0x433d},
314 {0x01c1, 0x0000},
315 {0x01c2, 0x0000},
316 {0x01c3, 0x0000},
317 {0x01c4, 0x0000},
318 {0x01c5, 0x0000},
319 {0x01c6, 0x0000},
320 {0x01c7, 0x0000},
321 {0x01c8, 0x40af},
322 {0x01c9, 0x0702},
323 {0x01ca, 0x0000},
324 {0x01cb, 0x0000},
325 {0x01cc, 0x5757},
326 {0x01cd, 0x5757},
327 {0x01ce, 0x5757},
328 {0x01cf, 0x5757},
329 {0x01d0, 0x5757},
330 {0x01d1, 0x5757},
331 {0x01d2, 0x5757},
332 {0x01d3, 0x5757},
333 {0x01d4, 0x5757},
334 {0x01d5, 0x5757},
335 {0x01d6, 0x003c},
336 {0x01da, 0x0000},
337 {0x01db, 0x0000},
338 {0x01dc, 0x0000},
339 {0x01de, 0x7c00},
340 {0x01df, 0x0320},
341 {0x01e0, 0x06a1},
342 {0x01e1, 0x0000},
343 {0x01e2, 0x0000},
344 {0x01e3, 0x0000},
345 {0x01e4, 0x0000},
346 {0x01e6, 0x0001},
347 {0x01e7, 0x0000},
348 {0x01e8, 0x0000},
349 {0x01ea, 0xbf3f},
350 {0x01eb, 0x0000},
351 {0x01ec, 0x0000},
352 {0x01ed, 0x0000},
353 {0x01ee, 0x0000},
354 {0x01ef, 0x0000},
355 {0x01f0, 0x0000},
356 {0x01f1, 0x0000},
357 {0x01f2, 0x0000},
358 {0x01f3, 0x0000},
359 {0x01f4, 0x0000},
360 {0x0200, 0x0000},
361 {0x0201, 0x0000},
362 {0x0202, 0x0000},
363 {0x0203, 0x0000},
364 {0x0204, 0x0000},
365 {0x0205, 0x0000},
366 {0x0206, 0x0000},
367 {0x0207, 0x0000},
368 {0x0208, 0x0000},
369 {0x0210, 0x60b1},
370 {0x0211, 0xa005},
371 {0x0212, 0x024c},
372 {0x0213, 0xf7ff},
373 {0x0214, 0x024c},
374 {0x0215, 0x0102},
375 {0x0216, 0x00a3},
376 {0x0217, 0x0048},
377 {0x0218, 0xa2c0},
378 {0x0219, 0x0400},
379 {0x021a, 0x00c8},
380 {0x021b, 0x00c0},
381 {0x02ff, 0x0110},
382 {0x0300, 0x001f},
383 {0x0301, 0x032c},
384 {0x0302, 0x5f21},
385 {0x0303, 0x4000},
386 {0x0304, 0x4000},
387 {0x0305, 0x06d5},
388 {0x0306, 0x8000},
389 {0x0307, 0x0700},
390 {0x0310, 0x4560},
391 {0x0311, 0xa4a8},
392 {0x0312, 0x7418},
393 {0x0313, 0x0000},
394 {0x0314, 0x0006},
395 {0x0315, 0xffff},
396 {0x0316, 0xc400},
397 {0x0317, 0x0000},
398 {0x0330, 0x00a6},
399 {0x0331, 0x04c3},
400 {0x0332, 0x27c8},
401 {0x0333, 0xbf50},
402 {0x0334, 0x0045},
403 {0x0335, 0x0007},
404 {0x0336, 0x7418},
405 {0x0337, 0x0501},
406 {0x0338, 0x0000},
407 {0x0339, 0x0010},
408 {0x033a, 0x1010},
409 {0x03c0, 0x7e00},
410 {0x03c1, 0x8000},
411 {0x03c2, 0x8000},
412 {0x03c3, 0x8000},
413 {0x03c4, 0x8000},
414 {0x03c5, 0x8000},
415 {0x03c6, 0x8000},
416 {0x03c7, 0x8000},
417 {0x03c8, 0x8000},
418 {0x03c9, 0x8000},
419 {0x03ca, 0x8000},
420 {0x03cb, 0x8000},
421 {0x03cc, 0x8000},
422 {0x03d0, 0x0000},
423 {0x03d1, 0x0000},
424 {0x03d2, 0x0000},
425 {0x03d3, 0x0000},
426 {0x03d4, 0x2000},
427 {0x03d5, 0x2000},
428 {0x03d6, 0x0000},
429 {0x03d7, 0x0000},
430 {0x03d8, 0x2000},
431 {0x03d9, 0x2000},
432 {0x03da, 0x2000},
433 {0x03db, 0x2000},
434 {0x03dc, 0x0000},
435 {0x03dd, 0x0000},
436 {0x03de, 0x0000},
437 {0x03df, 0x2000},
438 {0x03e0, 0x0000},
439 {0x03e1, 0x0000},
440 {0x03e2, 0x0000},
441 {0x03e3, 0x0000},
442 {0x03e4, 0x0000},
443 {0x03e5, 0x0000},
444 {0x03e6, 0x0000},
445 {0x03e7, 0x0000},
446 {0x03e8, 0x0000},
447 {0x03e9, 0x0000},
448 {0x03ea, 0x0000},
449 {0x03eb, 0x0000},
450 {0x03ec, 0x0000},
451 {0x03ed, 0x0000},
452 {0x03ee, 0x0000},
453 {0x03ef, 0x0000},
454 {0x03f0, 0x0800},
455 {0x03f1, 0x0800},
456 {0x03f2, 0x0800},
457 {0x03f3, 0x0800},
458 };
459
rt5665_volatile_register(struct device * dev,unsigned int reg)460 static bool rt5665_volatile_register(struct device *dev, unsigned int reg)
461 {
462 switch (reg) {
463 case RT5665_RESET:
464 case RT5665_EJD_CTRL_2:
465 case RT5665_GPIO_STA:
466 case RT5665_INT_ST_1:
467 case RT5665_IL_CMD_1:
468 case RT5665_4BTN_IL_CMD_1:
469 case RT5665_PSV_IL_CMD_1:
470 case RT5665_AJD1_CTRL:
471 case RT5665_JD_CTRL_3:
472 case RT5665_STO_NG2_CTRL_1:
473 case RT5665_SAR_IL_CMD_4:
474 case RT5665_DEVICE_ID:
475 case RT5665_STO1_DAC_SIL_DET ... RT5665_STO2_DAC_SIL_DET:
476 case RT5665_MONO_AMP_CALIB_STA1 ... RT5665_MONO_AMP_CALIB_STA6:
477 case RT5665_HP_IMP_SENS_CTRL_12 ... RT5665_HP_IMP_SENS_CTRL_15:
478 case RT5665_HP_CALIB_STA_1 ... RT5665_HP_CALIB_STA_11:
479 return true;
480 default:
481 return false;
482 }
483 }
484
rt5665_readable_register(struct device * dev,unsigned int reg)485 static bool rt5665_readable_register(struct device *dev, unsigned int reg)
486 {
487 switch (reg) {
488 case RT5665_RESET:
489 case RT5665_VENDOR_ID:
490 case RT5665_VENDOR_ID_1:
491 case RT5665_DEVICE_ID:
492 case RT5665_LOUT:
493 case RT5665_HP_CTRL_1:
494 case RT5665_HP_CTRL_2:
495 case RT5665_MONO_OUT:
496 case RT5665_HPL_GAIN:
497 case RT5665_HPR_GAIN:
498 case RT5665_MONO_GAIN:
499 case RT5665_CAL_BST_CTRL:
500 case RT5665_CBJ_BST_CTRL:
501 case RT5665_IN1_IN2:
502 case RT5665_IN3_IN4:
503 case RT5665_INL1_INR1_VOL:
504 case RT5665_EJD_CTRL_1:
505 case RT5665_EJD_CTRL_2:
506 case RT5665_EJD_CTRL_3:
507 case RT5665_EJD_CTRL_4:
508 case RT5665_EJD_CTRL_5:
509 case RT5665_EJD_CTRL_6:
510 case RT5665_EJD_CTRL_7:
511 case RT5665_DAC2_CTRL:
512 case RT5665_DAC2_DIG_VOL:
513 case RT5665_DAC1_DIG_VOL:
514 case RT5665_DAC3_DIG_VOL:
515 case RT5665_DAC3_CTRL:
516 case RT5665_STO1_ADC_DIG_VOL:
517 case RT5665_MONO_ADC_DIG_VOL:
518 case RT5665_STO2_ADC_DIG_VOL:
519 case RT5665_STO1_ADC_BOOST:
520 case RT5665_MONO_ADC_BOOST:
521 case RT5665_STO2_ADC_BOOST:
522 case RT5665_HP_IMP_GAIN_1:
523 case RT5665_HP_IMP_GAIN_2:
524 case RT5665_STO1_ADC_MIXER:
525 case RT5665_MONO_ADC_MIXER:
526 case RT5665_STO2_ADC_MIXER:
527 case RT5665_AD_DA_MIXER:
528 case RT5665_STO1_DAC_MIXER:
529 case RT5665_MONO_DAC_MIXER:
530 case RT5665_STO2_DAC_MIXER:
531 case RT5665_A_DAC1_MUX:
532 case RT5665_A_DAC2_MUX:
533 case RT5665_DIG_INF2_DATA:
534 case RT5665_DIG_INF3_DATA:
535 case RT5665_PDM_OUT_CTRL:
536 case RT5665_PDM_DATA_CTRL_1:
537 case RT5665_PDM_DATA_CTRL_2:
538 case RT5665_PDM_DATA_CTRL_3:
539 case RT5665_PDM_DATA_CTRL_4:
540 case RT5665_REC1_GAIN:
541 case RT5665_REC1_L1_MIXER:
542 case RT5665_REC1_L2_MIXER:
543 case RT5665_REC1_R1_MIXER:
544 case RT5665_REC1_R2_MIXER:
545 case RT5665_REC2_GAIN:
546 case RT5665_REC2_L1_MIXER:
547 case RT5665_REC2_L2_MIXER:
548 case RT5665_REC2_R1_MIXER:
549 case RT5665_REC2_R2_MIXER:
550 case RT5665_CAL_REC:
551 case RT5665_ALC_BACK_GAIN:
552 case RT5665_MONOMIX_GAIN:
553 case RT5665_MONOMIX_IN_GAIN:
554 case RT5665_OUT_L_GAIN:
555 case RT5665_OUT_L_MIXER:
556 case RT5665_OUT_R_GAIN:
557 case RT5665_OUT_R_MIXER:
558 case RT5665_LOUT_MIXER:
559 case RT5665_PWR_DIG_1:
560 case RT5665_PWR_DIG_2:
561 case RT5665_PWR_ANLG_1:
562 case RT5665_PWR_ANLG_2:
563 case RT5665_PWR_ANLG_3:
564 case RT5665_PWR_MIXER:
565 case RT5665_PWR_VOL:
566 case RT5665_CLK_DET:
567 case RT5665_HPF_CTRL1:
568 case RT5665_DMIC_CTRL_1:
569 case RT5665_DMIC_CTRL_2:
570 case RT5665_I2S1_SDP:
571 case RT5665_I2S2_SDP:
572 case RT5665_I2S3_SDP:
573 case RT5665_ADDA_CLK_1:
574 case RT5665_ADDA_CLK_2:
575 case RT5665_I2S1_F_DIV_CTRL_1:
576 case RT5665_I2S1_F_DIV_CTRL_2:
577 case RT5665_TDM_CTRL_1:
578 case RT5665_TDM_CTRL_2:
579 case RT5665_TDM_CTRL_3:
580 case RT5665_TDM_CTRL_4:
581 case RT5665_TDM_CTRL_5:
582 case RT5665_TDM_CTRL_6:
583 case RT5665_TDM_CTRL_7:
584 case RT5665_TDM_CTRL_8:
585 case RT5665_GLB_CLK:
586 case RT5665_PLL_CTRL_1:
587 case RT5665_PLL_CTRL_2:
588 case RT5665_ASRC_1:
589 case RT5665_ASRC_2:
590 case RT5665_ASRC_3:
591 case RT5665_ASRC_4:
592 case RT5665_ASRC_5:
593 case RT5665_ASRC_6:
594 case RT5665_ASRC_7:
595 case RT5665_ASRC_8:
596 case RT5665_ASRC_9:
597 case RT5665_ASRC_10:
598 case RT5665_DEPOP_1:
599 case RT5665_DEPOP_2:
600 case RT5665_HP_CHARGE_PUMP_1:
601 case RT5665_HP_CHARGE_PUMP_2:
602 case RT5665_MICBIAS_1:
603 case RT5665_MICBIAS_2:
604 case RT5665_ASRC_12:
605 case RT5665_ASRC_13:
606 case RT5665_ASRC_14:
607 case RT5665_RC_CLK_CTRL:
608 case RT5665_I2S_M_CLK_CTRL_1:
609 case RT5665_I2S2_F_DIV_CTRL_1:
610 case RT5665_I2S2_F_DIV_CTRL_2:
611 case RT5665_I2S3_F_DIV_CTRL_1:
612 case RT5665_I2S3_F_DIV_CTRL_2:
613 case RT5665_EQ_CTRL_1:
614 case RT5665_EQ_CTRL_2:
615 case RT5665_IRQ_CTRL_1:
616 case RT5665_IRQ_CTRL_2:
617 case RT5665_IRQ_CTRL_3:
618 case RT5665_IRQ_CTRL_4:
619 case RT5665_IRQ_CTRL_5:
620 case RT5665_IRQ_CTRL_6:
621 case RT5665_INT_ST_1:
622 case RT5665_GPIO_CTRL_1:
623 case RT5665_GPIO_CTRL_2:
624 case RT5665_GPIO_CTRL_3:
625 case RT5665_GPIO_CTRL_4:
626 case RT5665_GPIO_STA:
627 case RT5665_HP_AMP_DET_CTRL_1:
628 case RT5665_HP_AMP_DET_CTRL_2:
629 case RT5665_MID_HP_AMP_DET:
630 case RT5665_LOW_HP_AMP_DET:
631 case RT5665_SV_ZCD_1:
632 case RT5665_SV_ZCD_2:
633 case RT5665_IL_CMD_1:
634 case RT5665_IL_CMD_2:
635 case RT5665_IL_CMD_3:
636 case RT5665_IL_CMD_4:
637 case RT5665_4BTN_IL_CMD_1:
638 case RT5665_4BTN_IL_CMD_2:
639 case RT5665_4BTN_IL_CMD_3:
640 case RT5665_PSV_IL_CMD_1:
641 case RT5665_ADC_STO1_HP_CTRL_1:
642 case RT5665_ADC_STO1_HP_CTRL_2:
643 case RT5665_ADC_MONO_HP_CTRL_1:
644 case RT5665_ADC_MONO_HP_CTRL_2:
645 case RT5665_ADC_STO2_HP_CTRL_1:
646 case RT5665_ADC_STO2_HP_CTRL_2:
647 case RT5665_AJD1_CTRL:
648 case RT5665_JD1_THD:
649 case RT5665_JD2_THD:
650 case RT5665_JD_CTRL_1:
651 case RT5665_JD_CTRL_2:
652 case RT5665_JD_CTRL_3:
653 case RT5665_DIG_MISC:
654 case RT5665_DUMMY_2:
655 case RT5665_DUMMY_3:
656 case RT5665_DAC_ADC_DIG_VOL1:
657 case RT5665_DAC_ADC_DIG_VOL2:
658 case RT5665_BIAS_CUR_CTRL_1:
659 case RT5665_BIAS_CUR_CTRL_2:
660 case RT5665_BIAS_CUR_CTRL_3:
661 case RT5665_BIAS_CUR_CTRL_4:
662 case RT5665_BIAS_CUR_CTRL_5:
663 case RT5665_BIAS_CUR_CTRL_6:
664 case RT5665_BIAS_CUR_CTRL_7:
665 case RT5665_BIAS_CUR_CTRL_8:
666 case RT5665_BIAS_CUR_CTRL_9:
667 case RT5665_BIAS_CUR_CTRL_10:
668 case RT5665_VREF_REC_OP_FB_CAP_CTRL:
669 case RT5665_CHARGE_PUMP_1:
670 case RT5665_DIG_IN_CTRL_1:
671 case RT5665_DIG_IN_CTRL_2:
672 case RT5665_PAD_DRIVING_CTRL:
673 case RT5665_SOFT_RAMP_DEPOP:
674 case RT5665_PLL:
675 case RT5665_CHOP_DAC:
676 case RT5665_CHOP_ADC:
677 case RT5665_CALIB_ADC_CTRL:
678 case RT5665_VOL_TEST:
679 case RT5665_TEST_MODE_CTRL_1:
680 case RT5665_TEST_MODE_CTRL_2:
681 case RT5665_TEST_MODE_CTRL_3:
682 case RT5665_TEST_MODE_CTRL_4:
683 case RT5665_BASSBACK_CTRL:
684 case RT5665_STO_NG2_CTRL_1:
685 case RT5665_STO_NG2_CTRL_2:
686 case RT5665_STO_NG2_CTRL_3:
687 case RT5665_STO_NG2_CTRL_4:
688 case RT5665_STO_NG2_CTRL_5:
689 case RT5665_STO_NG2_CTRL_6:
690 case RT5665_STO_NG2_CTRL_7:
691 case RT5665_STO_NG2_CTRL_8:
692 case RT5665_MONO_NG2_CTRL_1:
693 case RT5665_MONO_NG2_CTRL_2:
694 case RT5665_MONO_NG2_CTRL_3:
695 case RT5665_MONO_NG2_CTRL_4:
696 case RT5665_MONO_NG2_CTRL_5:
697 case RT5665_MONO_NG2_CTRL_6:
698 case RT5665_STO1_DAC_SIL_DET:
699 case RT5665_MONOL_DAC_SIL_DET:
700 case RT5665_MONOR_DAC_SIL_DET:
701 case RT5665_STO2_DAC_SIL_DET:
702 case RT5665_SIL_PSV_CTRL1:
703 case RT5665_SIL_PSV_CTRL2:
704 case RT5665_SIL_PSV_CTRL3:
705 case RT5665_SIL_PSV_CTRL4:
706 case RT5665_SIL_PSV_CTRL5:
707 case RT5665_SIL_PSV_CTRL6:
708 case RT5665_MONO_AMP_CALIB_CTRL_1:
709 case RT5665_MONO_AMP_CALIB_CTRL_2:
710 case RT5665_MONO_AMP_CALIB_CTRL_3:
711 case RT5665_MONO_AMP_CALIB_CTRL_4:
712 case RT5665_MONO_AMP_CALIB_CTRL_5:
713 case RT5665_MONO_AMP_CALIB_CTRL_6:
714 case RT5665_MONO_AMP_CALIB_CTRL_7:
715 case RT5665_MONO_AMP_CALIB_STA1:
716 case RT5665_MONO_AMP_CALIB_STA2:
717 case RT5665_MONO_AMP_CALIB_STA3:
718 case RT5665_MONO_AMP_CALIB_STA4:
719 case RT5665_MONO_AMP_CALIB_STA6:
720 case RT5665_HP_IMP_SENS_CTRL_01:
721 case RT5665_HP_IMP_SENS_CTRL_02:
722 case RT5665_HP_IMP_SENS_CTRL_03:
723 case RT5665_HP_IMP_SENS_CTRL_04:
724 case RT5665_HP_IMP_SENS_CTRL_05:
725 case RT5665_HP_IMP_SENS_CTRL_06:
726 case RT5665_HP_IMP_SENS_CTRL_07:
727 case RT5665_HP_IMP_SENS_CTRL_08:
728 case RT5665_HP_IMP_SENS_CTRL_09:
729 case RT5665_HP_IMP_SENS_CTRL_10:
730 case RT5665_HP_IMP_SENS_CTRL_11:
731 case RT5665_HP_IMP_SENS_CTRL_12:
732 case RT5665_HP_IMP_SENS_CTRL_13:
733 case RT5665_HP_IMP_SENS_CTRL_14:
734 case RT5665_HP_IMP_SENS_CTRL_15:
735 case RT5665_HP_IMP_SENS_CTRL_16:
736 case RT5665_HP_IMP_SENS_CTRL_17:
737 case RT5665_HP_IMP_SENS_CTRL_18:
738 case RT5665_HP_IMP_SENS_CTRL_19:
739 case RT5665_HP_IMP_SENS_CTRL_20:
740 case RT5665_HP_IMP_SENS_CTRL_21:
741 case RT5665_HP_IMP_SENS_CTRL_22:
742 case RT5665_HP_IMP_SENS_CTRL_23:
743 case RT5665_HP_IMP_SENS_CTRL_24:
744 case RT5665_HP_IMP_SENS_CTRL_25:
745 case RT5665_HP_IMP_SENS_CTRL_26:
746 case RT5665_HP_IMP_SENS_CTRL_27:
747 case RT5665_HP_IMP_SENS_CTRL_28:
748 case RT5665_HP_IMP_SENS_CTRL_29:
749 case RT5665_HP_IMP_SENS_CTRL_30:
750 case RT5665_HP_IMP_SENS_CTRL_31:
751 case RT5665_HP_IMP_SENS_CTRL_32:
752 case RT5665_HP_IMP_SENS_CTRL_33:
753 case RT5665_HP_IMP_SENS_CTRL_34:
754 case RT5665_HP_LOGIC_CTRL_1:
755 case RT5665_HP_LOGIC_CTRL_2:
756 case RT5665_HP_LOGIC_CTRL_3:
757 case RT5665_HP_CALIB_CTRL_1:
758 case RT5665_HP_CALIB_CTRL_2:
759 case RT5665_HP_CALIB_CTRL_3:
760 case RT5665_HP_CALIB_CTRL_4:
761 case RT5665_HP_CALIB_CTRL_5:
762 case RT5665_HP_CALIB_CTRL_6:
763 case RT5665_HP_CALIB_CTRL_7:
764 case RT5665_HP_CALIB_CTRL_9:
765 case RT5665_HP_CALIB_CTRL_10:
766 case RT5665_HP_CALIB_CTRL_11:
767 case RT5665_HP_CALIB_STA_1:
768 case RT5665_HP_CALIB_STA_2:
769 case RT5665_HP_CALIB_STA_3:
770 case RT5665_HP_CALIB_STA_4:
771 case RT5665_HP_CALIB_STA_5:
772 case RT5665_HP_CALIB_STA_6:
773 case RT5665_HP_CALIB_STA_7:
774 case RT5665_HP_CALIB_STA_8:
775 case RT5665_HP_CALIB_STA_9:
776 case RT5665_HP_CALIB_STA_10:
777 case RT5665_HP_CALIB_STA_11:
778 case RT5665_PGM_TAB_CTRL1:
779 case RT5665_PGM_TAB_CTRL2:
780 case RT5665_PGM_TAB_CTRL3:
781 case RT5665_PGM_TAB_CTRL4:
782 case RT5665_PGM_TAB_CTRL5:
783 case RT5665_PGM_TAB_CTRL6:
784 case RT5665_PGM_TAB_CTRL7:
785 case RT5665_PGM_TAB_CTRL8:
786 case RT5665_PGM_TAB_CTRL9:
787 case RT5665_SAR_IL_CMD_1:
788 case RT5665_SAR_IL_CMD_2:
789 case RT5665_SAR_IL_CMD_3:
790 case RT5665_SAR_IL_CMD_4:
791 case RT5665_SAR_IL_CMD_5:
792 case RT5665_SAR_IL_CMD_6:
793 case RT5665_SAR_IL_CMD_7:
794 case RT5665_SAR_IL_CMD_8:
795 case RT5665_SAR_IL_CMD_9:
796 case RT5665_SAR_IL_CMD_10:
797 case RT5665_SAR_IL_CMD_11:
798 case RT5665_SAR_IL_CMD_12:
799 case RT5665_DRC1_CTRL_0:
800 case RT5665_DRC1_CTRL_1:
801 case RT5665_DRC1_CTRL_2:
802 case RT5665_DRC1_CTRL_3:
803 case RT5665_DRC1_CTRL_4:
804 case RT5665_DRC1_CTRL_5:
805 case RT5665_DRC1_CTRL_6:
806 case RT5665_DRC1_HARD_LMT_CTRL_1:
807 case RT5665_DRC1_HARD_LMT_CTRL_2:
808 case RT5665_DRC1_PRIV_1:
809 case RT5665_DRC1_PRIV_2:
810 case RT5665_DRC1_PRIV_3:
811 case RT5665_DRC1_PRIV_4:
812 case RT5665_DRC1_PRIV_5:
813 case RT5665_DRC1_PRIV_6:
814 case RT5665_DRC1_PRIV_7:
815 case RT5665_DRC1_PRIV_8:
816 case RT5665_ALC_PGA_CTRL_1:
817 case RT5665_ALC_PGA_CTRL_2:
818 case RT5665_ALC_PGA_CTRL_3:
819 case RT5665_ALC_PGA_CTRL_4:
820 case RT5665_ALC_PGA_CTRL_5:
821 case RT5665_ALC_PGA_CTRL_6:
822 case RT5665_ALC_PGA_CTRL_7:
823 case RT5665_ALC_PGA_CTRL_8:
824 case RT5665_ALC_PGA_STA_1:
825 case RT5665_ALC_PGA_STA_2:
826 case RT5665_ALC_PGA_STA_3:
827 case RT5665_EQ_AUTO_RCV_CTRL1:
828 case RT5665_EQ_AUTO_RCV_CTRL2:
829 case RT5665_EQ_AUTO_RCV_CTRL3:
830 case RT5665_EQ_AUTO_RCV_CTRL4:
831 case RT5665_EQ_AUTO_RCV_CTRL5:
832 case RT5665_EQ_AUTO_RCV_CTRL6:
833 case RT5665_EQ_AUTO_RCV_CTRL7:
834 case RT5665_EQ_AUTO_RCV_CTRL8:
835 case RT5665_EQ_AUTO_RCV_CTRL9:
836 case RT5665_EQ_AUTO_RCV_CTRL10:
837 case RT5665_EQ_AUTO_RCV_CTRL11:
838 case RT5665_EQ_AUTO_RCV_CTRL12:
839 case RT5665_EQ_AUTO_RCV_CTRL13:
840 case RT5665_ADC_L_EQ_LPF1_A1:
841 case RT5665_R_EQ_LPF1_A1:
842 case RT5665_L_EQ_LPF1_H0:
843 case RT5665_R_EQ_LPF1_H0:
844 case RT5665_L_EQ_BPF1_A1:
845 case RT5665_R_EQ_BPF1_A1:
846 case RT5665_L_EQ_BPF1_A2:
847 case RT5665_R_EQ_BPF1_A2:
848 case RT5665_L_EQ_BPF1_H0:
849 case RT5665_R_EQ_BPF1_H0:
850 case RT5665_L_EQ_BPF2_A1:
851 case RT5665_R_EQ_BPF2_A1:
852 case RT5665_L_EQ_BPF2_A2:
853 case RT5665_R_EQ_BPF2_A2:
854 case RT5665_L_EQ_BPF2_H0:
855 case RT5665_R_EQ_BPF2_H0:
856 case RT5665_L_EQ_BPF3_A1:
857 case RT5665_R_EQ_BPF3_A1:
858 case RT5665_L_EQ_BPF3_A2:
859 case RT5665_R_EQ_BPF3_A2:
860 case RT5665_L_EQ_BPF3_H0:
861 case RT5665_R_EQ_BPF3_H0:
862 case RT5665_L_EQ_BPF4_A1:
863 case RT5665_R_EQ_BPF4_A1:
864 case RT5665_L_EQ_BPF4_A2:
865 case RT5665_R_EQ_BPF4_A2:
866 case RT5665_L_EQ_BPF4_H0:
867 case RT5665_R_EQ_BPF4_H0:
868 case RT5665_L_EQ_HPF1_A1:
869 case RT5665_R_EQ_HPF1_A1:
870 case RT5665_L_EQ_HPF1_H0:
871 case RT5665_R_EQ_HPF1_H0:
872 case RT5665_L_EQ_PRE_VOL:
873 case RT5665_R_EQ_PRE_VOL:
874 case RT5665_L_EQ_POST_VOL:
875 case RT5665_R_EQ_POST_VOL:
876 case RT5665_SCAN_MODE_CTRL:
877 case RT5665_I2C_MODE:
878 return true;
879 default:
880 return false;
881 }
882 }
883
884 static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -2250, 150, 0);
885 static const DECLARE_TLV_DB_SCALE(mono_vol_tlv, -1400, 150, 0);
886 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
887 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
888 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
889 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
890 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
891 static const DECLARE_TLV_DB_SCALE(in_bst_tlv, -1200, 75, 0);
892
893 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
894 static const DECLARE_TLV_DB_RANGE(bst_tlv,
895 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
896 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
897 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
898 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
899 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
900 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
901 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
902 );
903
904 /* Interface data select */
905 static const char * const rt5665_data_select[] = {
906 "L/R", "R/L", "L/L", "R/R"
907 };
908
909 static SOC_ENUM_SINGLE_DECL(rt5665_if1_1_01_adc_enum,
910 RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT01_SFT, rt5665_data_select);
911
912 static SOC_ENUM_SINGLE_DECL(rt5665_if1_1_23_adc_enum,
913 RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT23_SFT, rt5665_data_select);
914
915 static SOC_ENUM_SINGLE_DECL(rt5665_if1_1_45_adc_enum,
916 RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT45_SFT, rt5665_data_select);
917
918 static SOC_ENUM_SINGLE_DECL(rt5665_if1_1_67_adc_enum,
919 RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT67_SFT, rt5665_data_select);
920
921 static SOC_ENUM_SINGLE_DECL(rt5665_if1_2_01_adc_enum,
922 RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT01_SFT, rt5665_data_select);
923
924 static SOC_ENUM_SINGLE_DECL(rt5665_if1_2_23_adc_enum,
925 RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT23_SFT, rt5665_data_select);
926
927 static SOC_ENUM_SINGLE_DECL(rt5665_if1_2_45_adc_enum,
928 RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT45_SFT, rt5665_data_select);
929
930 static SOC_ENUM_SINGLE_DECL(rt5665_if1_2_67_adc_enum,
931 RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT67_SFT, rt5665_data_select);
932
933 static SOC_ENUM_SINGLE_DECL(rt5665_if2_1_dac_enum,
934 RT5665_DIG_INF2_DATA, RT5665_IF2_1_DAC_SEL_SFT, rt5665_data_select);
935
936 static SOC_ENUM_SINGLE_DECL(rt5665_if2_1_adc_enum,
937 RT5665_DIG_INF2_DATA, RT5665_IF2_1_ADC_SEL_SFT, rt5665_data_select);
938
939 static SOC_ENUM_SINGLE_DECL(rt5665_if2_2_dac_enum,
940 RT5665_DIG_INF2_DATA, RT5665_IF2_2_DAC_SEL_SFT, rt5665_data_select);
941
942 static SOC_ENUM_SINGLE_DECL(rt5665_if2_2_adc_enum,
943 RT5665_DIG_INF2_DATA, RT5665_IF2_2_ADC_SEL_SFT, rt5665_data_select);
944
945 static SOC_ENUM_SINGLE_DECL(rt5665_if3_dac_enum,
946 RT5665_DIG_INF3_DATA, RT5665_IF3_DAC_SEL_SFT, rt5665_data_select);
947
948 static SOC_ENUM_SINGLE_DECL(rt5665_if3_adc_enum,
949 RT5665_DIG_INF3_DATA, RT5665_IF3_ADC_SEL_SFT, rt5665_data_select);
950
951 static const struct snd_kcontrol_new rt5665_if1_1_01_adc_swap_mux =
952 SOC_DAPM_ENUM("IF1_1 01 ADC Swap Mux", rt5665_if1_1_01_adc_enum);
953
954 static const struct snd_kcontrol_new rt5665_if1_1_23_adc_swap_mux =
955 SOC_DAPM_ENUM("IF1_1 23 ADC Swap Mux", rt5665_if1_1_23_adc_enum);
956
957 static const struct snd_kcontrol_new rt5665_if1_1_45_adc_swap_mux =
958 SOC_DAPM_ENUM("IF1_1 45 ADC Swap Mux", rt5665_if1_1_45_adc_enum);
959
960 static const struct snd_kcontrol_new rt5665_if1_1_67_adc_swap_mux =
961 SOC_DAPM_ENUM("IF1_1 67 ADC Swap Mux", rt5665_if1_1_67_adc_enum);
962
963 static const struct snd_kcontrol_new rt5665_if1_2_01_adc_swap_mux =
964 SOC_DAPM_ENUM("IF1_2 01 ADC Swap Mux", rt5665_if1_2_01_adc_enum);
965
966 static const struct snd_kcontrol_new rt5665_if1_2_23_adc_swap_mux =
967 SOC_DAPM_ENUM("IF1_2 23 ADC1 Swap Mux", rt5665_if1_2_23_adc_enum);
968
969 static const struct snd_kcontrol_new rt5665_if1_2_45_adc_swap_mux =
970 SOC_DAPM_ENUM("IF1_2 45 ADC1 Swap Mux", rt5665_if1_2_45_adc_enum);
971
972 static const struct snd_kcontrol_new rt5665_if1_2_67_adc_swap_mux =
973 SOC_DAPM_ENUM("IF1_2 67 ADC1 Swap Mux", rt5665_if1_2_67_adc_enum);
974
975 static const struct snd_kcontrol_new rt5665_if2_1_dac_swap_mux =
976 SOC_DAPM_ENUM("IF2_1 DAC Swap Source", rt5665_if2_1_dac_enum);
977
978 static const struct snd_kcontrol_new rt5665_if2_1_adc_swap_mux =
979 SOC_DAPM_ENUM("IF2_1 ADC Swap Source", rt5665_if2_1_adc_enum);
980
981 static const struct snd_kcontrol_new rt5665_if2_2_dac_swap_mux =
982 SOC_DAPM_ENUM("IF2_2 DAC Swap Source", rt5665_if2_2_dac_enum);
983
984 static const struct snd_kcontrol_new rt5665_if2_2_adc_swap_mux =
985 SOC_DAPM_ENUM("IF2_2 ADC Swap Source", rt5665_if2_2_adc_enum);
986
987 static const struct snd_kcontrol_new rt5665_if3_dac_swap_mux =
988 SOC_DAPM_ENUM("IF3 DAC Swap Source", rt5665_if3_dac_enum);
989
990 static const struct snd_kcontrol_new rt5665_if3_adc_swap_mux =
991 SOC_DAPM_ENUM("IF3 ADC Swap Source", rt5665_if3_adc_enum);
992
rt5665_hp_vol_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)993 static int rt5665_hp_vol_put(struct snd_kcontrol *kcontrol,
994 struct snd_ctl_elem_value *ucontrol)
995 {
996 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
997 int ret = snd_soc_put_volsw(kcontrol, ucontrol);
998
999 if (snd_soc_component_read(component, RT5665_STO_NG2_CTRL_1) & RT5665_NG2_EN) {
1000 snd_soc_component_update_bits(component, RT5665_STO_NG2_CTRL_1,
1001 RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
1002 snd_soc_component_update_bits(component, RT5665_STO_NG2_CTRL_1,
1003 RT5665_NG2_EN_MASK, RT5665_NG2_EN);
1004 }
1005
1006 return ret;
1007 }
1008
rt5665_mono_vol_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1009 static int rt5665_mono_vol_put(struct snd_kcontrol *kcontrol,
1010 struct snd_ctl_elem_value *ucontrol)
1011 {
1012 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1013 int ret = snd_soc_put_volsw(kcontrol, ucontrol);
1014
1015 if (snd_soc_component_read(component, RT5665_MONO_NG2_CTRL_1) & RT5665_NG2_EN) {
1016 snd_soc_component_update_bits(component, RT5665_MONO_NG2_CTRL_1,
1017 RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
1018 snd_soc_component_update_bits(component, RT5665_MONO_NG2_CTRL_1,
1019 RT5665_NG2_EN_MASK, RT5665_NG2_EN);
1020 }
1021
1022 return ret;
1023 }
1024
rt5665_button_detect(struct snd_soc_component * component)1025 static int rt5665_button_detect(struct snd_soc_component *component)
1026 {
1027 int btn_type, val;
1028
1029 val = snd_soc_component_read(component, RT5665_4BTN_IL_CMD_1);
1030 btn_type = val & 0xfff0;
1031 snd_soc_component_write(component, RT5665_4BTN_IL_CMD_1, val);
1032
1033 return btn_type;
1034 }
1035
rt5665_enable_push_button_irq(struct snd_soc_component * component,bool enable)1036 static void rt5665_enable_push_button_irq(struct snd_soc_component *component,
1037 bool enable)
1038 {
1039 if (enable) {
1040 snd_soc_component_write(component, RT5665_4BTN_IL_CMD_1, 0x0003);
1041 snd_soc_component_update_bits(component, RT5665_SAR_IL_CMD_9, 0x1, 0x1);
1042 snd_soc_component_write(component, RT5665_IL_CMD_1, 0x0048);
1043 snd_soc_component_update_bits(component, RT5665_4BTN_IL_CMD_2,
1044 RT5665_4BTN_IL_MASK | RT5665_4BTN_IL_RST_MASK,
1045 RT5665_4BTN_IL_EN | RT5665_4BTN_IL_NOR);
1046 snd_soc_component_update_bits(component, RT5665_IRQ_CTRL_3,
1047 RT5665_IL_IRQ_MASK, RT5665_IL_IRQ_EN);
1048 } else {
1049 snd_soc_component_update_bits(component, RT5665_IRQ_CTRL_3,
1050 RT5665_IL_IRQ_MASK, RT5665_IL_IRQ_DIS);
1051 snd_soc_component_update_bits(component, RT5665_4BTN_IL_CMD_2,
1052 RT5665_4BTN_IL_MASK, RT5665_4BTN_IL_DIS);
1053 snd_soc_component_update_bits(component, RT5665_4BTN_IL_CMD_2,
1054 RT5665_4BTN_IL_RST_MASK, RT5665_4BTN_IL_RST);
1055 }
1056 }
1057
1058 /**
1059 * rt5665_headset_detect - Detect headset.
1060 * @component: SoC audio component device.
1061 * @jack_insert: Jack insert or not.
1062 *
1063 * Detect whether is headset or not when jack inserted.
1064 *
1065 * Returns detect status.
1066 */
rt5665_headset_detect(struct snd_soc_component * component,int jack_insert)1067 static int rt5665_headset_detect(struct snd_soc_component *component, int jack_insert)
1068 {
1069 struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
1070 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
1071 unsigned int sar_hs_type, val;
1072
1073 if (jack_insert) {
1074 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
1075 snd_soc_dapm_sync(dapm);
1076
1077 regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2, 0x100,
1078 0x100);
1079
1080 regmap_read(rt5665->regmap, RT5665_GPIO_STA, &val);
1081 if (val & 0x4) {
1082 regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1,
1083 0x100, 0);
1084
1085 regmap_read(rt5665->regmap, RT5665_GPIO_STA, &val);
1086 while (val & 0x4) {
1087 usleep_range(10000, 15000);
1088 regmap_read(rt5665->regmap, RT5665_GPIO_STA,
1089 &val);
1090 }
1091 }
1092
1093 regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1,
1094 0x1a0, 0x120);
1095 regmap_write(rt5665->regmap, RT5665_EJD_CTRL_3, 0x3424);
1096 regmap_write(rt5665->regmap, RT5665_IL_CMD_1, 0x0048);
1097 regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1, 0xa291);
1098
1099 usleep_range(10000, 15000);
1100
1101 rt5665->sar_adc_value = snd_soc_component_read(rt5665->component,
1102 RT5665_SAR_IL_CMD_4) & 0x7ff;
1103
1104 sar_hs_type = rt5665->pdata.sar_hs_type ?
1105 rt5665->pdata.sar_hs_type : 729;
1106
1107 if (rt5665->sar_adc_value > sar_hs_type) {
1108 rt5665->jack_type = SND_JACK_HEADSET;
1109 rt5665_enable_push_button_irq(component, true);
1110 } else {
1111 rt5665->jack_type = SND_JACK_HEADPHONE;
1112 regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1,
1113 0x2291);
1114 regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2,
1115 0x100, 0);
1116 snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1117 snd_soc_dapm_sync(dapm);
1118 }
1119 } else {
1120 regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1, 0x2291);
1121 regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2, 0x100, 0);
1122 snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1123 snd_soc_dapm_sync(dapm);
1124 if (rt5665->jack_type == SND_JACK_HEADSET)
1125 rt5665_enable_push_button_irq(component, false);
1126 rt5665->jack_type = 0;
1127 }
1128
1129 dev_dbg(component->dev, "jack_type = %d\n", rt5665->jack_type);
1130 return rt5665->jack_type;
1131 }
1132
rt5665_irq(int irq,void * data)1133 static irqreturn_t rt5665_irq(int irq, void *data)
1134 {
1135 struct rt5665_priv *rt5665 = data;
1136
1137 mod_delayed_work(system_power_efficient_wq,
1138 &rt5665->jack_detect_work, msecs_to_jiffies(250));
1139
1140 return IRQ_HANDLED;
1141 }
1142
rt5665_jd_check_handler(struct work_struct * work)1143 static void rt5665_jd_check_handler(struct work_struct *work)
1144 {
1145 struct rt5665_priv *rt5665 = container_of(work, struct rt5665_priv,
1146 jd_check_work.work);
1147
1148 if (snd_soc_component_read(rt5665->component, RT5665_AJD1_CTRL) & 0x0010) {
1149 /* jack out */
1150 rt5665->jack_type = rt5665_headset_detect(rt5665->component, 0);
1151
1152 snd_soc_jack_report(rt5665->hs_jack, rt5665->jack_type,
1153 SND_JACK_HEADSET |
1154 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1155 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1156 } else {
1157 schedule_delayed_work(&rt5665->jd_check_work, 500);
1158 }
1159 }
1160
rt5665_set_jack_detect(struct snd_soc_component * component,struct snd_soc_jack * hs_jack,void * data)1161 static int rt5665_set_jack_detect(struct snd_soc_component *component,
1162 struct snd_soc_jack *hs_jack, void *data)
1163 {
1164 struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
1165
1166 switch (rt5665->pdata.jd_src) {
1167 case RT5665_JD1:
1168 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
1169 RT5665_GP1_PIN_MASK, RT5665_GP1_PIN_IRQ);
1170 regmap_update_bits(rt5665->regmap, RT5665_RC_CLK_CTRL,
1171 0xc000, 0xc000);
1172 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_2,
1173 RT5665_PWR_JD1, RT5665_PWR_JD1);
1174 regmap_update_bits(rt5665->regmap, RT5665_IRQ_CTRL_1, 0x8, 0x8);
1175 break;
1176
1177 case RT5665_JD_NULL:
1178 break;
1179
1180 default:
1181 dev_warn(component->dev, "Wrong JD source\n");
1182 break;
1183 }
1184
1185 rt5665->hs_jack = hs_jack;
1186
1187 return 0;
1188 }
1189
rt5665_jack_detect_handler(struct work_struct * work)1190 static void rt5665_jack_detect_handler(struct work_struct *work)
1191 {
1192 struct rt5665_priv *rt5665 =
1193 container_of(work, struct rt5665_priv, jack_detect_work.work);
1194 int val, btn_type;
1195
1196 while (!rt5665->component) {
1197 pr_debug("%s codec = null\n", __func__);
1198 usleep_range(10000, 15000);
1199 }
1200
1201 while (!snd_soc_card_is_instantiated(rt5665->component->card)) {
1202 pr_debug("%s\n", __func__);
1203 usleep_range(10000, 15000);
1204 }
1205
1206 while (!rt5665->calibration_done) {
1207 pr_debug("%s calibration not ready\n", __func__);
1208 usleep_range(10000, 15000);
1209 }
1210
1211 mutex_lock(&rt5665->calibrate_mutex);
1212
1213 val = snd_soc_component_read(rt5665->component, RT5665_AJD1_CTRL) & 0x0010;
1214 if (!val) {
1215 /* jack in */
1216 if (rt5665->jack_type == 0) {
1217 /* jack was out, report jack type */
1218 rt5665->jack_type =
1219 rt5665_headset_detect(rt5665->component, 1);
1220 } else {
1221 /* jack is already in, report button event */
1222 rt5665->jack_type = SND_JACK_HEADSET;
1223 btn_type = rt5665_button_detect(rt5665->component);
1224 /**
1225 * rt5665 can report three kinds of button behavior,
1226 * one click, double click and hold. However,
1227 * currently we will report button pressed/released
1228 * event. So all the three button behaviors are
1229 * treated as button pressed.
1230 */
1231 switch (btn_type) {
1232 case 0x8000:
1233 case 0x4000:
1234 case 0x2000:
1235 rt5665->jack_type |= SND_JACK_BTN_0;
1236 break;
1237 case 0x1000:
1238 case 0x0800:
1239 case 0x0400:
1240 rt5665->jack_type |= SND_JACK_BTN_1;
1241 break;
1242 case 0x0200:
1243 case 0x0100:
1244 case 0x0080:
1245 rt5665->jack_type |= SND_JACK_BTN_2;
1246 break;
1247 case 0x0040:
1248 case 0x0020:
1249 case 0x0010:
1250 rt5665->jack_type |= SND_JACK_BTN_3;
1251 break;
1252 case 0x0000: /* unpressed */
1253 break;
1254 default:
1255 btn_type = 0;
1256 dev_err(rt5665->component->dev,
1257 "Unexpected button code 0x%04x\n",
1258 btn_type);
1259 break;
1260 }
1261 }
1262 } else {
1263 /* jack out */
1264 rt5665->jack_type = rt5665_headset_detect(rt5665->component, 0);
1265 }
1266
1267 snd_soc_jack_report(rt5665->hs_jack, rt5665->jack_type,
1268 SND_JACK_HEADSET |
1269 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1270 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1271
1272 if (rt5665->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1273 SND_JACK_BTN_2 | SND_JACK_BTN_3))
1274 schedule_delayed_work(&rt5665->jd_check_work, 0);
1275 else
1276 cancel_delayed_work_sync(&rt5665->jd_check_work);
1277
1278 mutex_unlock(&rt5665->calibrate_mutex);
1279 }
1280
1281 static const char * const rt5665_clk_sync[] = {
1282 "I2S1_1", "I2S1_2", "I2S2", "I2S3", "IF2 Slave", "IF3 Slave"
1283 };
1284
1285 static const struct soc_enum rt5665_enum[] = {
1286 SOC_ENUM_SINGLE(RT5665_I2S1_SDP, 11, 5, rt5665_clk_sync),
1287 SOC_ENUM_SINGLE(RT5665_I2S2_SDP, 11, 5, rt5665_clk_sync),
1288 SOC_ENUM_SINGLE(RT5665_I2S3_SDP, 11, 5, rt5665_clk_sync),
1289 };
1290
1291 static const struct snd_kcontrol_new rt5665_snd_controls[] = {
1292 /* Headphone Output Volume */
1293 SOC_DOUBLE_R_EXT_TLV("Headphone Playback Volume", RT5665_HPL_GAIN,
1294 RT5665_HPR_GAIN, RT5665_G_HP_SFT, 15, 1, snd_soc_get_volsw,
1295 rt5665_hp_vol_put, hp_vol_tlv),
1296
1297 /* Mono Output Volume */
1298 SOC_SINGLE_EXT_TLV("Mono Playback Volume", RT5665_MONO_GAIN,
1299 RT5665_L_VOL_SFT, 15, 1, snd_soc_get_volsw,
1300 rt5665_mono_vol_put, mono_vol_tlv),
1301
1302 SOC_SINGLE_TLV("MONOVOL Playback Volume", RT5665_MONO_OUT,
1303 RT5665_L_VOL_SFT, 39, 1, out_vol_tlv),
1304
1305 /* Output Volume */
1306 SOC_DOUBLE_TLV("OUT Playback Volume", RT5665_LOUT, RT5665_L_VOL_SFT,
1307 RT5665_R_VOL_SFT, 39, 1, out_vol_tlv),
1308
1309 /* DAC Digital Volume */
1310 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5665_DAC1_DIG_VOL,
1311 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 175, 0, dac_vol_tlv),
1312 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5665_DAC2_DIG_VOL,
1313 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 175, 0, dac_vol_tlv),
1314 SOC_DOUBLE("DAC2 Playback Switch", RT5665_DAC2_CTRL,
1315 RT5665_M_DAC2_L_VOL_SFT, RT5665_M_DAC2_R_VOL_SFT, 1, 1),
1316
1317 /* IN1/IN2/IN3/IN4 Volume */
1318 SOC_SINGLE_TLV("IN1 Boost Volume", RT5665_IN1_IN2,
1319 RT5665_BST1_SFT, 69, 0, in_bst_tlv),
1320 SOC_SINGLE_TLV("IN2 Boost Volume", RT5665_IN1_IN2,
1321 RT5665_BST2_SFT, 69, 0, in_bst_tlv),
1322 SOC_SINGLE_TLV("IN3 Boost Volume", RT5665_IN3_IN4,
1323 RT5665_BST3_SFT, 69, 0, in_bst_tlv),
1324 SOC_SINGLE_TLV("IN4 Boost Volume", RT5665_IN3_IN4,
1325 RT5665_BST4_SFT, 69, 0, in_bst_tlv),
1326 SOC_SINGLE_TLV("CBJ Boost Volume", RT5665_CBJ_BST_CTRL,
1327 RT5665_BST_CBJ_SFT, 8, 0, bst_tlv),
1328
1329 /* INL/INR Volume Control */
1330 SOC_DOUBLE_TLV("IN Capture Volume", RT5665_INL1_INR1_VOL,
1331 RT5665_INL_VOL_SFT, RT5665_INR_VOL_SFT, 31, 1, in_vol_tlv),
1332
1333 /* ADC Digital Volume Control */
1334 SOC_DOUBLE("STO1 ADC Capture Switch", RT5665_STO1_ADC_DIG_VOL,
1335 RT5665_L_MUTE_SFT, RT5665_R_MUTE_SFT, 1, 1),
1336 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5665_STO1_ADC_DIG_VOL,
1337 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 127, 0, adc_vol_tlv),
1338 SOC_DOUBLE("Mono ADC Capture Switch", RT5665_MONO_ADC_DIG_VOL,
1339 RT5665_L_MUTE_SFT, RT5665_R_MUTE_SFT, 1, 1),
1340 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5665_MONO_ADC_DIG_VOL,
1341 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 127, 0, adc_vol_tlv),
1342 SOC_DOUBLE("STO2 ADC Capture Switch", RT5665_STO2_ADC_DIG_VOL,
1343 RT5665_L_MUTE_SFT, RT5665_R_MUTE_SFT, 1, 1),
1344 SOC_DOUBLE_TLV("STO2 ADC Capture Volume", RT5665_STO2_ADC_DIG_VOL,
1345 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 127, 0, adc_vol_tlv),
1346
1347 /* ADC Boost Volume Control */
1348 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5665_STO1_ADC_BOOST,
1349 RT5665_STO1_ADC_L_BST_SFT, RT5665_STO1_ADC_R_BST_SFT,
1350 3, 0, adc_bst_tlv),
1351
1352 SOC_DOUBLE_TLV("Mono ADC Boost Gain Volume", RT5665_MONO_ADC_BOOST,
1353 RT5665_MONO_ADC_L_BST_SFT, RT5665_MONO_ADC_R_BST_SFT,
1354 3, 0, adc_bst_tlv),
1355
1356 SOC_DOUBLE_TLV("STO2 ADC Boost Gain Volume", RT5665_STO2_ADC_BOOST,
1357 RT5665_STO2_ADC_L_BST_SFT, RT5665_STO2_ADC_R_BST_SFT,
1358 3, 0, adc_bst_tlv),
1359
1360 /* I2S3 CLK Source */
1361 SOC_ENUM("I2S1 Master Clk Sel", rt5665_enum[0]),
1362 SOC_ENUM("I2S2 Master Clk Sel", rt5665_enum[1]),
1363 SOC_ENUM("I2S3 Master Clk Sel", rt5665_enum[2]),
1364 };
1365
1366 /**
1367 * set_dmic_clk - Set parameter of dmic.
1368 *
1369 * @w: DAPM widget.
1370 * @kcontrol: The kcontrol of this widget.
1371 * @event: Event id.
1372 *
1373 * Choose dmic clock between 1MHz and 3MHz.
1374 * It is better for clock to approximate 3MHz.
1375 */
set_dmic_clk(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1376 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1377 struct snd_kcontrol *kcontrol, int event)
1378 {
1379 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1380 struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
1381 int pd, idx;
1382
1383 pd = rl6231_get_pre_div(rt5665->regmap,
1384 RT5665_ADDA_CLK_1, RT5665_I2S_PD1_SFT);
1385 idx = rl6231_calc_dmic_clk(rt5665->sysclk / pd);
1386
1387 if (idx < 0)
1388 dev_err(component->dev, "Failed to set DMIC clock\n");
1389 else {
1390 snd_soc_component_update_bits(component, RT5665_DMIC_CTRL_1,
1391 RT5665_DMIC_CLK_MASK, idx << RT5665_DMIC_CLK_SFT);
1392 }
1393 return idx;
1394 }
1395
rt5665_charge_pump_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1396 static int rt5665_charge_pump_event(struct snd_soc_dapm_widget *w,
1397 struct snd_kcontrol *kcontrol, int event)
1398 {
1399 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1400
1401 switch (event) {
1402 case SND_SOC_DAPM_PRE_PMU:
1403 snd_soc_component_update_bits(component, RT5665_HP_CHARGE_PUMP_1,
1404 RT5665_PM_HP_MASK | RT5665_OSW_L_MASK,
1405 RT5665_PM_HP_HV | RT5665_OSW_L_EN);
1406 break;
1407 case SND_SOC_DAPM_POST_PMD:
1408 snd_soc_component_update_bits(component, RT5665_HP_CHARGE_PUMP_1,
1409 RT5665_PM_HP_MASK | RT5665_OSW_L_MASK,
1410 RT5665_PM_HP_LV | RT5665_OSW_L_DIS);
1411 break;
1412 default:
1413 return 0;
1414 }
1415
1416 return 0;
1417 }
1418
is_sys_clk_from_pll(struct snd_soc_dapm_widget * w,struct snd_soc_dapm_widget * sink)1419 static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *w,
1420 struct snd_soc_dapm_widget *sink)
1421 {
1422 unsigned int val;
1423 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1424
1425 val = snd_soc_component_read(component, RT5665_GLB_CLK);
1426 val &= RT5665_SCLK_SRC_MASK;
1427 if (val == RT5665_SCLK_SRC_PLL1)
1428 return 1;
1429 else
1430 return 0;
1431 }
1432
is_using_asrc(struct snd_soc_dapm_widget * w,struct snd_soc_dapm_widget * sink)1433 static int is_using_asrc(struct snd_soc_dapm_widget *w,
1434 struct snd_soc_dapm_widget *sink)
1435 {
1436 unsigned int reg, shift, val;
1437 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1438
1439 switch (w->shift) {
1440 case RT5665_ADC_MONO_R_ASRC_SFT:
1441 reg = RT5665_ASRC_3;
1442 shift = RT5665_AD_MONOR_CLK_SEL_SFT;
1443 break;
1444 case RT5665_ADC_MONO_L_ASRC_SFT:
1445 reg = RT5665_ASRC_3;
1446 shift = RT5665_AD_MONOL_CLK_SEL_SFT;
1447 break;
1448 case RT5665_ADC_STO1_ASRC_SFT:
1449 reg = RT5665_ASRC_3;
1450 shift = RT5665_AD_STO1_CLK_SEL_SFT;
1451 break;
1452 case RT5665_ADC_STO2_ASRC_SFT:
1453 reg = RT5665_ASRC_3;
1454 shift = RT5665_AD_STO2_CLK_SEL_SFT;
1455 break;
1456 case RT5665_DAC_MONO_R_ASRC_SFT:
1457 reg = RT5665_ASRC_2;
1458 shift = RT5665_DA_MONOR_CLK_SEL_SFT;
1459 break;
1460 case RT5665_DAC_MONO_L_ASRC_SFT:
1461 reg = RT5665_ASRC_2;
1462 shift = RT5665_DA_MONOL_CLK_SEL_SFT;
1463 break;
1464 case RT5665_DAC_STO1_ASRC_SFT:
1465 reg = RT5665_ASRC_2;
1466 shift = RT5665_DA_STO1_CLK_SEL_SFT;
1467 break;
1468 case RT5665_DAC_STO2_ASRC_SFT:
1469 reg = RT5665_ASRC_2;
1470 shift = RT5665_DA_STO2_CLK_SEL_SFT;
1471 break;
1472 default:
1473 return 0;
1474 }
1475
1476 val = (snd_soc_component_read(component, reg) >> shift) & 0xf;
1477 switch (val) {
1478 case RT5665_CLK_SEL_I2S1_ASRC:
1479 case RT5665_CLK_SEL_I2S2_ASRC:
1480 case RT5665_CLK_SEL_I2S3_ASRC:
1481 /* I2S_Pre_Div1 should be 1 in asrc mode */
1482 snd_soc_component_update_bits(component, RT5665_ADDA_CLK_1,
1483 RT5665_I2S_PD1_MASK, RT5665_I2S_PD1_2);
1484 return 1;
1485 default:
1486 return 0;
1487 }
1488
1489 }
1490
1491 /* Digital Mixer */
1492 static const struct snd_kcontrol_new rt5665_sto1_adc_l_mix[] = {
1493 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO1_ADC_MIXER,
1494 RT5665_M_STO1_ADC_L1_SFT, 1, 1),
1495 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO1_ADC_MIXER,
1496 RT5665_M_STO1_ADC_L2_SFT, 1, 1),
1497 };
1498
1499 static const struct snd_kcontrol_new rt5665_sto1_adc_r_mix[] = {
1500 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO1_ADC_MIXER,
1501 RT5665_M_STO1_ADC_R1_SFT, 1, 1),
1502 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO1_ADC_MIXER,
1503 RT5665_M_STO1_ADC_R2_SFT, 1, 1),
1504 };
1505
1506 static const struct snd_kcontrol_new rt5665_sto2_adc_l_mix[] = {
1507 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO2_ADC_MIXER,
1508 RT5665_M_STO2_ADC_L1_SFT, 1, 1),
1509 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO2_ADC_MIXER,
1510 RT5665_M_STO2_ADC_L2_SFT, 1, 1),
1511 };
1512
1513 static const struct snd_kcontrol_new rt5665_sto2_adc_r_mix[] = {
1514 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO2_ADC_MIXER,
1515 RT5665_M_STO2_ADC_R1_SFT, 1, 1),
1516 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO2_ADC_MIXER,
1517 RT5665_M_STO2_ADC_R2_SFT, 1, 1),
1518 };
1519
1520 static const struct snd_kcontrol_new rt5665_mono_adc_l_mix[] = {
1521 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_MONO_ADC_MIXER,
1522 RT5665_M_MONO_ADC_L1_SFT, 1, 1),
1523 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_MONO_ADC_MIXER,
1524 RT5665_M_MONO_ADC_L2_SFT, 1, 1),
1525 };
1526
1527 static const struct snd_kcontrol_new rt5665_mono_adc_r_mix[] = {
1528 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_MONO_ADC_MIXER,
1529 RT5665_M_MONO_ADC_R1_SFT, 1, 1),
1530 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_MONO_ADC_MIXER,
1531 RT5665_M_MONO_ADC_R2_SFT, 1, 1),
1532 };
1533
1534 static const struct snd_kcontrol_new rt5665_dac_l_mix[] = {
1535 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5665_AD_DA_MIXER,
1536 RT5665_M_ADCMIX_L_SFT, 1, 1),
1537 SOC_DAPM_SINGLE("DAC1 Switch", RT5665_AD_DA_MIXER,
1538 RT5665_M_DAC1_L_SFT, 1, 1),
1539 };
1540
1541 static const struct snd_kcontrol_new rt5665_dac_r_mix[] = {
1542 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5665_AD_DA_MIXER,
1543 RT5665_M_ADCMIX_R_SFT, 1, 1),
1544 SOC_DAPM_SINGLE("DAC1 Switch", RT5665_AD_DA_MIXER,
1545 RT5665_M_DAC1_R_SFT, 1, 1),
1546 };
1547
1548 static const struct snd_kcontrol_new rt5665_sto1_dac_l_mix[] = {
1549 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_STO1_DAC_MIXER,
1550 RT5665_M_DAC_L1_STO_L_SFT, 1, 1),
1551 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_STO1_DAC_MIXER,
1552 RT5665_M_DAC_R1_STO_L_SFT, 1, 1),
1553 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_STO1_DAC_MIXER,
1554 RT5665_M_DAC_L2_STO_L_SFT, 1, 1),
1555 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_STO1_DAC_MIXER,
1556 RT5665_M_DAC_R2_STO_L_SFT, 1, 1),
1557 };
1558
1559 static const struct snd_kcontrol_new rt5665_sto1_dac_r_mix[] = {
1560 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_STO1_DAC_MIXER,
1561 RT5665_M_DAC_L1_STO_R_SFT, 1, 1),
1562 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_STO1_DAC_MIXER,
1563 RT5665_M_DAC_R1_STO_R_SFT, 1, 1),
1564 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_STO1_DAC_MIXER,
1565 RT5665_M_DAC_L2_STO_R_SFT, 1, 1),
1566 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_STO1_DAC_MIXER,
1567 RT5665_M_DAC_R2_STO_R_SFT, 1, 1),
1568 };
1569
1570 static const struct snd_kcontrol_new rt5665_sto2_dac_l_mix[] = {
1571 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_STO2_DAC_MIXER,
1572 RT5665_M_DAC_L1_STO2_L_SFT, 1, 1),
1573 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_STO2_DAC_MIXER,
1574 RT5665_M_DAC_L2_STO2_L_SFT, 1, 1),
1575 SOC_DAPM_SINGLE("DAC L3 Switch", RT5665_STO2_DAC_MIXER,
1576 RT5665_M_DAC_L3_STO2_L_SFT, 1, 1),
1577 };
1578
1579 static const struct snd_kcontrol_new rt5665_sto2_dac_r_mix[] = {
1580 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_STO2_DAC_MIXER,
1581 RT5665_M_DAC_R1_STO2_R_SFT, 1, 1),
1582 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_STO2_DAC_MIXER,
1583 RT5665_M_DAC_R2_STO2_R_SFT, 1, 1),
1584 SOC_DAPM_SINGLE("DAC R3 Switch", RT5665_STO2_DAC_MIXER,
1585 RT5665_M_DAC_R3_STO2_R_SFT, 1, 1),
1586 };
1587
1588 static const struct snd_kcontrol_new rt5665_mono_dac_l_mix[] = {
1589 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_MONO_DAC_MIXER,
1590 RT5665_M_DAC_L1_MONO_L_SFT, 1, 1),
1591 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_MONO_DAC_MIXER,
1592 RT5665_M_DAC_R1_MONO_L_SFT, 1, 1),
1593 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONO_DAC_MIXER,
1594 RT5665_M_DAC_L2_MONO_L_SFT, 1, 1),
1595 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_MONO_DAC_MIXER,
1596 RT5665_M_DAC_R2_MONO_L_SFT, 1, 1),
1597 };
1598
1599 static const struct snd_kcontrol_new rt5665_mono_dac_r_mix[] = {
1600 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_MONO_DAC_MIXER,
1601 RT5665_M_DAC_L1_MONO_R_SFT, 1, 1),
1602 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_MONO_DAC_MIXER,
1603 RT5665_M_DAC_R1_MONO_R_SFT, 1, 1),
1604 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONO_DAC_MIXER,
1605 RT5665_M_DAC_L2_MONO_R_SFT, 1, 1),
1606 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_MONO_DAC_MIXER,
1607 RT5665_M_DAC_R2_MONO_R_SFT, 1, 1),
1608 };
1609
1610 /* Analog Input Mixer */
1611 static const struct snd_kcontrol_new rt5665_rec1_l_mix[] = {
1612 SOC_DAPM_SINGLE("CBJ Switch", RT5665_REC1_L2_MIXER,
1613 RT5665_M_CBJ_RM1_L_SFT, 1, 1),
1614 SOC_DAPM_SINGLE("INL Switch", RT5665_REC1_L2_MIXER,
1615 RT5665_M_INL_RM1_L_SFT, 1, 1),
1616 SOC_DAPM_SINGLE("INR Switch", RT5665_REC1_L2_MIXER,
1617 RT5665_M_INR_RM1_L_SFT, 1, 1),
1618 SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC1_L2_MIXER,
1619 RT5665_M_BST4_RM1_L_SFT, 1, 1),
1620 SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC1_L2_MIXER,
1621 RT5665_M_BST3_RM1_L_SFT, 1, 1),
1622 SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC1_L2_MIXER,
1623 RT5665_M_BST2_RM1_L_SFT, 1, 1),
1624 SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC1_L2_MIXER,
1625 RT5665_M_BST1_RM1_L_SFT, 1, 1),
1626 };
1627
1628 static const struct snd_kcontrol_new rt5665_rec1_r_mix[] = {
1629 SOC_DAPM_SINGLE("MONOVOL Switch", RT5665_REC1_R2_MIXER,
1630 RT5665_M_AEC_REF_RM1_R_SFT, 1, 1),
1631 SOC_DAPM_SINGLE("INR Switch", RT5665_REC1_R2_MIXER,
1632 RT5665_M_INR_RM1_R_SFT, 1, 1),
1633 SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC1_R2_MIXER,
1634 RT5665_M_BST4_RM1_R_SFT, 1, 1),
1635 SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC1_R2_MIXER,
1636 RT5665_M_BST3_RM1_R_SFT, 1, 1),
1637 SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC1_R2_MIXER,
1638 RT5665_M_BST2_RM1_R_SFT, 1, 1),
1639 SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC1_R2_MIXER,
1640 RT5665_M_BST1_RM1_R_SFT, 1, 1),
1641 };
1642
1643 static const struct snd_kcontrol_new rt5665_rec2_l_mix[] = {
1644 SOC_DAPM_SINGLE("INL Switch", RT5665_REC2_L2_MIXER,
1645 RT5665_M_INL_RM2_L_SFT, 1, 1),
1646 SOC_DAPM_SINGLE("INR Switch", RT5665_REC2_L2_MIXER,
1647 RT5665_M_INR_RM2_L_SFT, 1, 1),
1648 SOC_DAPM_SINGLE("CBJ Switch", RT5665_REC2_L2_MIXER,
1649 RT5665_M_CBJ_RM2_L_SFT, 1, 1),
1650 SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC2_L2_MIXER,
1651 RT5665_M_BST4_RM2_L_SFT, 1, 1),
1652 SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC2_L2_MIXER,
1653 RT5665_M_BST3_RM2_L_SFT, 1, 1),
1654 SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC2_L2_MIXER,
1655 RT5665_M_BST2_RM2_L_SFT, 1, 1),
1656 SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC2_L2_MIXER,
1657 RT5665_M_BST1_RM2_L_SFT, 1, 1),
1658 };
1659
1660 static const struct snd_kcontrol_new rt5665_rec2_r_mix[] = {
1661 SOC_DAPM_SINGLE("MONOVOL Switch", RT5665_REC2_R2_MIXER,
1662 RT5665_M_MONOVOL_RM2_R_SFT, 1, 1),
1663 SOC_DAPM_SINGLE("INL Switch", RT5665_REC2_R2_MIXER,
1664 RT5665_M_INL_RM2_R_SFT, 1, 1),
1665 SOC_DAPM_SINGLE("INR Switch", RT5665_REC2_R2_MIXER,
1666 RT5665_M_INR_RM2_R_SFT, 1, 1),
1667 SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC2_R2_MIXER,
1668 RT5665_M_BST4_RM2_R_SFT, 1, 1),
1669 SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC2_R2_MIXER,
1670 RT5665_M_BST3_RM2_R_SFT, 1, 1),
1671 SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC2_R2_MIXER,
1672 RT5665_M_BST2_RM2_R_SFT, 1, 1),
1673 SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC2_R2_MIXER,
1674 RT5665_M_BST1_RM2_R_SFT, 1, 1),
1675 };
1676
1677 static const struct snd_kcontrol_new rt5665_monovol_mix[] = {
1678 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONOMIX_IN_GAIN,
1679 RT5665_M_DAC_L2_MM_SFT, 1, 1),
1680 SOC_DAPM_SINGLE("RECMIX2L Switch", RT5665_MONOMIX_IN_GAIN,
1681 RT5665_M_RECMIC2L_MM_SFT, 1, 1),
1682 SOC_DAPM_SINGLE("BST1 Switch", RT5665_MONOMIX_IN_GAIN,
1683 RT5665_M_BST1_MM_SFT, 1, 1),
1684 SOC_DAPM_SINGLE("BST2 Switch", RT5665_MONOMIX_IN_GAIN,
1685 RT5665_M_BST2_MM_SFT, 1, 1),
1686 SOC_DAPM_SINGLE("BST3 Switch", RT5665_MONOMIX_IN_GAIN,
1687 RT5665_M_BST3_MM_SFT, 1, 1),
1688 };
1689
1690 static const struct snd_kcontrol_new rt5665_out_l_mix[] = {
1691 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_OUT_L_MIXER,
1692 RT5665_M_DAC_L2_OM_L_SFT, 1, 1),
1693 SOC_DAPM_SINGLE("INL Switch", RT5665_OUT_L_MIXER,
1694 RT5665_M_IN_L_OM_L_SFT, 1, 1),
1695 SOC_DAPM_SINGLE("BST1 Switch", RT5665_OUT_L_MIXER,
1696 RT5665_M_BST1_OM_L_SFT, 1, 1),
1697 SOC_DAPM_SINGLE("BST2 Switch", RT5665_OUT_L_MIXER,
1698 RT5665_M_BST2_OM_L_SFT, 1, 1),
1699 SOC_DAPM_SINGLE("BST3 Switch", RT5665_OUT_L_MIXER,
1700 RT5665_M_BST3_OM_L_SFT, 1, 1),
1701 };
1702
1703 static const struct snd_kcontrol_new rt5665_out_r_mix[] = {
1704 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_OUT_R_MIXER,
1705 RT5665_M_DAC_R2_OM_R_SFT, 1, 1),
1706 SOC_DAPM_SINGLE("INR Switch", RT5665_OUT_R_MIXER,
1707 RT5665_M_IN_R_OM_R_SFT, 1, 1),
1708 SOC_DAPM_SINGLE("BST2 Switch", RT5665_OUT_R_MIXER,
1709 RT5665_M_BST2_OM_R_SFT, 1, 1),
1710 SOC_DAPM_SINGLE("BST3 Switch", RT5665_OUT_R_MIXER,
1711 RT5665_M_BST3_OM_R_SFT, 1, 1),
1712 SOC_DAPM_SINGLE("BST4 Switch", RT5665_OUT_R_MIXER,
1713 RT5665_M_BST4_OM_R_SFT, 1, 1),
1714 };
1715
1716 static const struct snd_kcontrol_new rt5665_mono_mix[] = {
1717 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONOMIX_IN_GAIN,
1718 RT5665_M_DAC_L2_MA_SFT, 1, 1),
1719 SOC_DAPM_SINGLE("MONOVOL Switch", RT5665_MONOMIX_IN_GAIN,
1720 RT5665_M_MONOVOL_MA_SFT, 1, 1),
1721 };
1722
1723 static const struct snd_kcontrol_new rt5665_lout_l_mix[] = {
1724 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_LOUT_MIXER,
1725 RT5665_M_DAC_L2_LM_SFT, 1, 1),
1726 SOC_DAPM_SINGLE("OUTVOL L Switch", RT5665_LOUT_MIXER,
1727 RT5665_M_OV_L_LM_SFT, 1, 1),
1728 };
1729
1730 static const struct snd_kcontrol_new rt5665_lout_r_mix[] = {
1731 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_LOUT_MIXER,
1732 RT5665_M_DAC_R2_LM_SFT, 1, 1),
1733 SOC_DAPM_SINGLE("OUTVOL R Switch", RT5665_LOUT_MIXER,
1734 RT5665_M_OV_R_LM_SFT, 1, 1),
1735 };
1736
1737 /*DAC L2, DAC R2*/
1738 /*MX-17 [6:4], MX-17 [2:0]*/
1739 static const char * const rt5665_dac2_src[] = {
1740 "IF1 DAC2", "IF2_1 DAC", "IF2_2 DAC", "IF3 DAC", "Mono ADC MIX"
1741 };
1742
1743 static SOC_ENUM_SINGLE_DECL(
1744 rt5665_dac_l2_enum, RT5665_DAC2_CTRL,
1745 RT5665_DAC_L2_SEL_SFT, rt5665_dac2_src);
1746
1747 static const struct snd_kcontrol_new rt5665_dac_l2_mux =
1748 SOC_DAPM_ENUM("Digital DAC L2 Source", rt5665_dac_l2_enum);
1749
1750 static SOC_ENUM_SINGLE_DECL(
1751 rt5665_dac_r2_enum, RT5665_DAC2_CTRL,
1752 RT5665_DAC_R2_SEL_SFT, rt5665_dac2_src);
1753
1754 static const struct snd_kcontrol_new rt5665_dac_r2_mux =
1755 SOC_DAPM_ENUM("Digital DAC R2 Source", rt5665_dac_r2_enum);
1756
1757 /*DAC L3, DAC R3*/
1758 /*MX-1B [6:4], MX-1B [2:0]*/
1759 static const char * const rt5665_dac3_src[] = {
1760 "IF1 DAC2", "IF2_1 DAC", "IF2_2 DAC", "IF3 DAC", "STO2 ADC MIX"
1761 };
1762
1763 static SOC_ENUM_SINGLE_DECL(
1764 rt5665_dac_l3_enum, RT5665_DAC3_CTRL,
1765 RT5665_DAC_L3_SEL_SFT, rt5665_dac3_src);
1766
1767 static const struct snd_kcontrol_new rt5665_dac_l3_mux =
1768 SOC_DAPM_ENUM("Digital DAC L3 Source", rt5665_dac_l3_enum);
1769
1770 static SOC_ENUM_SINGLE_DECL(
1771 rt5665_dac_r3_enum, RT5665_DAC3_CTRL,
1772 RT5665_DAC_R3_SEL_SFT, rt5665_dac3_src);
1773
1774 static const struct snd_kcontrol_new rt5665_dac_r3_mux =
1775 SOC_DAPM_ENUM("Digital DAC R3 Source", rt5665_dac_r3_enum);
1776
1777 /* STO1 ADC1 Source */
1778 /* MX-26 [13] [5] */
1779 static const char * const rt5665_sto1_adc1_src[] = {
1780 "DD Mux", "ADC"
1781 };
1782
1783 static SOC_ENUM_SINGLE_DECL(
1784 rt5665_sto1_adc1l_enum, RT5665_STO1_ADC_MIXER,
1785 RT5665_STO1_ADC1L_SRC_SFT, rt5665_sto1_adc1_src);
1786
1787 static const struct snd_kcontrol_new rt5665_sto1_adc1l_mux =
1788 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5665_sto1_adc1l_enum);
1789
1790 static SOC_ENUM_SINGLE_DECL(
1791 rt5665_sto1_adc1r_enum, RT5665_STO1_ADC_MIXER,
1792 RT5665_STO1_ADC1R_SRC_SFT, rt5665_sto1_adc1_src);
1793
1794 static const struct snd_kcontrol_new rt5665_sto1_adc1r_mux =
1795 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5665_sto1_adc1r_enum);
1796
1797 /* STO1 ADC Source */
1798 /* MX-26 [11:10] [3:2] */
1799 static const char * const rt5665_sto1_adc_src[] = {
1800 "ADC1 L", "ADC1 R", "ADC2 L", "ADC2 R"
1801 };
1802
1803 static SOC_ENUM_SINGLE_DECL(
1804 rt5665_sto1_adcl_enum, RT5665_STO1_ADC_MIXER,
1805 RT5665_STO1_ADCL_SRC_SFT, rt5665_sto1_adc_src);
1806
1807 static const struct snd_kcontrol_new rt5665_sto1_adcl_mux =
1808 SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5665_sto1_adcl_enum);
1809
1810 static SOC_ENUM_SINGLE_DECL(
1811 rt5665_sto1_adcr_enum, RT5665_STO1_ADC_MIXER,
1812 RT5665_STO1_ADCR_SRC_SFT, rt5665_sto1_adc_src);
1813
1814 static const struct snd_kcontrol_new rt5665_sto1_adcr_mux =
1815 SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5665_sto1_adcr_enum);
1816
1817 /* STO1 ADC2 Source */
1818 /* MX-26 [12] [4] */
1819 static const char * const rt5665_sto1_adc2_src[] = {
1820 "DAC MIX", "DMIC"
1821 };
1822
1823 static SOC_ENUM_SINGLE_DECL(
1824 rt5665_sto1_adc2l_enum, RT5665_STO1_ADC_MIXER,
1825 RT5665_STO1_ADC2L_SRC_SFT, rt5665_sto1_adc2_src);
1826
1827 static const struct snd_kcontrol_new rt5665_sto1_adc2l_mux =
1828 SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5665_sto1_adc2l_enum);
1829
1830 static SOC_ENUM_SINGLE_DECL(
1831 rt5665_sto1_adc2r_enum, RT5665_STO1_ADC_MIXER,
1832 RT5665_STO1_ADC2R_SRC_SFT, rt5665_sto1_adc2_src);
1833
1834 static const struct snd_kcontrol_new rt5665_sto1_adc2r_mux =
1835 SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5665_sto1_adc2r_enum);
1836
1837 /* STO1 DMIC Source */
1838 /* MX-26 [8] */
1839 static const char * const rt5665_sto1_dmic_src[] = {
1840 "DMIC1", "DMIC2"
1841 };
1842
1843 static SOC_ENUM_SINGLE_DECL(
1844 rt5665_sto1_dmic_enum, RT5665_STO1_ADC_MIXER,
1845 RT5665_STO1_DMIC_SRC_SFT, rt5665_sto1_dmic_src);
1846
1847 static const struct snd_kcontrol_new rt5665_sto1_dmic_mux =
1848 SOC_DAPM_ENUM("Stereo1 DMIC Mux", rt5665_sto1_dmic_enum);
1849
1850 /* MX-26 [9] */
1851 static const char * const rt5665_sto1_dd_l_src[] = {
1852 "STO2 DAC", "MONO DAC"
1853 };
1854
1855 static SOC_ENUM_SINGLE_DECL(
1856 rt5665_sto1_dd_l_enum, RT5665_STO1_ADC_MIXER,
1857 RT5665_STO1_DD_L_SRC_SFT, rt5665_sto1_dd_l_src);
1858
1859 static const struct snd_kcontrol_new rt5665_sto1_dd_l_mux =
1860 SOC_DAPM_ENUM("Stereo1 DD L Source", rt5665_sto1_dd_l_enum);
1861
1862 /* MX-26 [1:0] */
1863 static const char * const rt5665_sto1_dd_r_src[] = {
1864 "STO2 DAC", "MONO DAC", "AEC REF"
1865 };
1866
1867 static SOC_ENUM_SINGLE_DECL(
1868 rt5665_sto1_dd_r_enum, RT5665_STO1_ADC_MIXER,
1869 RT5665_STO1_DD_R_SRC_SFT, rt5665_sto1_dd_r_src);
1870
1871 static const struct snd_kcontrol_new rt5665_sto1_dd_r_mux =
1872 SOC_DAPM_ENUM("Stereo1 DD R Source", rt5665_sto1_dd_r_enum);
1873
1874 /* MONO ADC L2 Source */
1875 /* MX-27 [12] */
1876 static const char * const rt5665_mono_adc_l2_src[] = {
1877 "DAC MIXL", "DMIC"
1878 };
1879
1880 static SOC_ENUM_SINGLE_DECL(
1881 rt5665_mono_adc_l2_enum, RT5665_MONO_ADC_MIXER,
1882 RT5665_MONO_ADC_L2_SRC_SFT, rt5665_mono_adc_l2_src);
1883
1884 static const struct snd_kcontrol_new rt5665_mono_adc_l2_mux =
1885 SOC_DAPM_ENUM("Mono ADC L2 Source", rt5665_mono_adc_l2_enum);
1886
1887
1888 /* MONO ADC L1 Source */
1889 /* MX-27 [13] */
1890 static const char * const rt5665_mono_adc_l1_src[] = {
1891 "DD Mux", "ADC"
1892 };
1893
1894 static SOC_ENUM_SINGLE_DECL(
1895 rt5665_mono_adc_l1_enum, RT5665_MONO_ADC_MIXER,
1896 RT5665_MONO_ADC_L1_SRC_SFT, rt5665_mono_adc_l1_src);
1897
1898 static const struct snd_kcontrol_new rt5665_mono_adc_l1_mux =
1899 SOC_DAPM_ENUM("Mono ADC L1 Source", rt5665_mono_adc_l1_enum);
1900
1901 /* MX-27 [9][1]*/
1902 static const char * const rt5665_mono_dd_src[] = {
1903 "STO2 DAC", "MONO DAC"
1904 };
1905
1906 static SOC_ENUM_SINGLE_DECL(
1907 rt5665_mono_dd_l_enum, RT5665_MONO_ADC_MIXER,
1908 RT5665_MONO_DD_L_SRC_SFT, rt5665_mono_dd_src);
1909
1910 static const struct snd_kcontrol_new rt5665_mono_dd_l_mux =
1911 SOC_DAPM_ENUM("Mono DD L Source", rt5665_mono_dd_l_enum);
1912
1913 static SOC_ENUM_SINGLE_DECL(
1914 rt5665_mono_dd_r_enum, RT5665_MONO_ADC_MIXER,
1915 RT5665_MONO_DD_R_SRC_SFT, rt5665_mono_dd_src);
1916
1917 static const struct snd_kcontrol_new rt5665_mono_dd_r_mux =
1918 SOC_DAPM_ENUM("Mono DD R Source", rt5665_mono_dd_r_enum);
1919
1920 /* MONO ADC L Source, MONO ADC R Source*/
1921 /* MX-27 [11:10], MX-27 [3:2] */
1922 static const char * const rt5665_mono_adc_src[] = {
1923 "ADC1 L", "ADC1 R", "ADC2 L", "ADC2 R"
1924 };
1925
1926 static SOC_ENUM_SINGLE_DECL(
1927 rt5665_mono_adc_l_enum, RT5665_MONO_ADC_MIXER,
1928 RT5665_MONO_ADC_L_SRC_SFT, rt5665_mono_adc_src);
1929
1930 static const struct snd_kcontrol_new rt5665_mono_adc_l_mux =
1931 SOC_DAPM_ENUM("Mono ADC L Source", rt5665_mono_adc_l_enum);
1932
1933 static SOC_ENUM_SINGLE_DECL(
1934 rt5665_mono_adcr_enum, RT5665_MONO_ADC_MIXER,
1935 RT5665_MONO_ADC_R_SRC_SFT, rt5665_mono_adc_src);
1936
1937 static const struct snd_kcontrol_new rt5665_mono_adc_r_mux =
1938 SOC_DAPM_ENUM("Mono ADC R Source", rt5665_mono_adcr_enum);
1939
1940 /* MONO DMIC L Source */
1941 /* MX-27 [8] */
1942 static const char * const rt5665_mono_dmic_l_src[] = {
1943 "DMIC1 L", "DMIC2 L"
1944 };
1945
1946 static SOC_ENUM_SINGLE_DECL(
1947 rt5665_mono_dmic_l_enum, RT5665_MONO_ADC_MIXER,
1948 RT5665_MONO_DMIC_L_SRC_SFT, rt5665_mono_dmic_l_src);
1949
1950 static const struct snd_kcontrol_new rt5665_mono_dmic_l_mux =
1951 SOC_DAPM_ENUM("Mono DMIC L Source", rt5665_mono_dmic_l_enum);
1952
1953 /* MONO ADC R2 Source */
1954 /* MX-27 [4] */
1955 static const char * const rt5665_mono_adc_r2_src[] = {
1956 "DAC MIXR", "DMIC"
1957 };
1958
1959 static SOC_ENUM_SINGLE_DECL(
1960 rt5665_mono_adc_r2_enum, RT5665_MONO_ADC_MIXER,
1961 RT5665_MONO_ADC_R2_SRC_SFT, rt5665_mono_adc_r2_src);
1962
1963 static const struct snd_kcontrol_new rt5665_mono_adc_r2_mux =
1964 SOC_DAPM_ENUM("Mono ADC R2 Source", rt5665_mono_adc_r2_enum);
1965
1966 /* MONO ADC R1 Source */
1967 /* MX-27 [5] */
1968 static const char * const rt5665_mono_adc_r1_src[] = {
1969 "DD Mux", "ADC"
1970 };
1971
1972 static SOC_ENUM_SINGLE_DECL(
1973 rt5665_mono_adc_r1_enum, RT5665_MONO_ADC_MIXER,
1974 RT5665_MONO_ADC_R1_SRC_SFT, rt5665_mono_adc_r1_src);
1975
1976 static const struct snd_kcontrol_new rt5665_mono_adc_r1_mux =
1977 SOC_DAPM_ENUM("Mono ADC R1 Source", rt5665_mono_adc_r1_enum);
1978
1979 /* MONO DMIC R Source */
1980 /* MX-27 [0] */
1981 static const char * const rt5665_mono_dmic_r_src[] = {
1982 "DMIC1 R", "DMIC2 R"
1983 };
1984
1985 static SOC_ENUM_SINGLE_DECL(
1986 rt5665_mono_dmic_r_enum, RT5665_MONO_ADC_MIXER,
1987 RT5665_MONO_DMIC_R_SRC_SFT, rt5665_mono_dmic_r_src);
1988
1989 static const struct snd_kcontrol_new rt5665_mono_dmic_r_mux =
1990 SOC_DAPM_ENUM("Mono DMIC R Source", rt5665_mono_dmic_r_enum);
1991
1992
1993 /* STO2 ADC1 Source */
1994 /* MX-28 [13] [5] */
1995 static const char * const rt5665_sto2_adc1_src[] = {
1996 "DD Mux", "ADC"
1997 };
1998
1999 static SOC_ENUM_SINGLE_DECL(
2000 rt5665_sto2_adc1l_enum, RT5665_STO2_ADC_MIXER,
2001 RT5665_STO2_ADC1L_SRC_SFT, rt5665_sto2_adc1_src);
2002
2003 static const struct snd_kcontrol_new rt5665_sto2_adc1l_mux =
2004 SOC_DAPM_ENUM("Stereo2 ADC1L Source", rt5665_sto2_adc1l_enum);
2005
2006 static SOC_ENUM_SINGLE_DECL(
2007 rt5665_sto2_adc1r_enum, RT5665_STO2_ADC_MIXER,
2008 RT5665_STO2_ADC1R_SRC_SFT, rt5665_sto2_adc1_src);
2009
2010 static const struct snd_kcontrol_new rt5665_sto2_adc1r_mux =
2011 SOC_DAPM_ENUM("Stereo2 ADC1L Source", rt5665_sto2_adc1r_enum);
2012
2013 /* STO2 ADC Source */
2014 /* MX-28 [11:10] [3:2] */
2015 static const char * const rt5665_sto2_adc_src[] = {
2016 "ADC1 L", "ADC1 R", "ADC2 L"
2017 };
2018
2019 static SOC_ENUM_SINGLE_DECL(
2020 rt5665_sto2_adcl_enum, RT5665_STO2_ADC_MIXER,
2021 RT5665_STO2_ADCL_SRC_SFT, rt5665_sto2_adc_src);
2022
2023 static const struct snd_kcontrol_new rt5665_sto2_adcl_mux =
2024 SOC_DAPM_ENUM("Stereo2 ADCL Source", rt5665_sto2_adcl_enum);
2025
2026 static SOC_ENUM_SINGLE_DECL(
2027 rt5665_sto2_adcr_enum, RT5665_STO2_ADC_MIXER,
2028 RT5665_STO2_ADCR_SRC_SFT, rt5665_sto2_adc_src);
2029
2030 static const struct snd_kcontrol_new rt5665_sto2_adcr_mux =
2031 SOC_DAPM_ENUM("Stereo2 ADCR Source", rt5665_sto2_adcr_enum);
2032
2033 /* STO2 ADC2 Source */
2034 /* MX-28 [12] [4] */
2035 static const char * const rt5665_sto2_adc2_src[] = {
2036 "DAC MIX", "DMIC"
2037 };
2038
2039 static SOC_ENUM_SINGLE_DECL(
2040 rt5665_sto2_adc2l_enum, RT5665_STO2_ADC_MIXER,
2041 RT5665_STO2_ADC2L_SRC_SFT, rt5665_sto2_adc2_src);
2042
2043 static const struct snd_kcontrol_new rt5665_sto2_adc2l_mux =
2044 SOC_DAPM_ENUM("Stereo2 ADC2L Source", rt5665_sto2_adc2l_enum);
2045
2046 static SOC_ENUM_SINGLE_DECL(
2047 rt5665_sto2_adc2r_enum, RT5665_STO2_ADC_MIXER,
2048 RT5665_STO2_ADC2R_SRC_SFT, rt5665_sto2_adc2_src);
2049
2050 static const struct snd_kcontrol_new rt5665_sto2_adc2r_mux =
2051 SOC_DAPM_ENUM("Stereo2 ADC2R Source", rt5665_sto2_adc2r_enum);
2052
2053 /* STO2 DMIC Source */
2054 /* MX-28 [8] */
2055 static const char * const rt5665_sto2_dmic_src[] = {
2056 "DMIC1", "DMIC2"
2057 };
2058
2059 static SOC_ENUM_SINGLE_DECL(
2060 rt5665_sto2_dmic_enum, RT5665_STO2_ADC_MIXER,
2061 RT5665_STO2_DMIC_SRC_SFT, rt5665_sto2_dmic_src);
2062
2063 static const struct snd_kcontrol_new rt5665_sto2_dmic_mux =
2064 SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5665_sto2_dmic_enum);
2065
2066 /* MX-28 [9] */
2067 static const char * const rt5665_sto2_dd_l_src[] = {
2068 "STO2 DAC", "MONO DAC"
2069 };
2070
2071 static SOC_ENUM_SINGLE_DECL(
2072 rt5665_sto2_dd_l_enum, RT5665_STO2_ADC_MIXER,
2073 RT5665_STO2_DD_L_SRC_SFT, rt5665_sto2_dd_l_src);
2074
2075 static const struct snd_kcontrol_new rt5665_sto2_dd_l_mux =
2076 SOC_DAPM_ENUM("Stereo2 DD L Source", rt5665_sto2_dd_l_enum);
2077
2078 /* MX-28 [1] */
2079 static const char * const rt5665_sto2_dd_r_src[] = {
2080 "STO2 DAC", "MONO DAC"
2081 };
2082
2083 static SOC_ENUM_SINGLE_DECL(
2084 rt5665_sto2_dd_r_enum, RT5665_STO2_ADC_MIXER,
2085 RT5665_STO2_DD_R_SRC_SFT, rt5665_sto2_dd_r_src);
2086
2087 static const struct snd_kcontrol_new rt5665_sto2_dd_r_mux =
2088 SOC_DAPM_ENUM("Stereo2 DD R Source", rt5665_sto2_dd_r_enum);
2089
2090 /* DAC R1 Source, DAC L1 Source*/
2091 /* MX-29 [11:10], MX-29 [9:8]*/
2092 static const char * const rt5665_dac1_src[] = {
2093 "IF1 DAC1", "IF2_1 DAC", "IF2_2 DAC", "IF3 DAC"
2094 };
2095
2096 static SOC_ENUM_SINGLE_DECL(
2097 rt5665_dac_r1_enum, RT5665_AD_DA_MIXER,
2098 RT5665_DAC1_R_SEL_SFT, rt5665_dac1_src);
2099
2100 static const struct snd_kcontrol_new rt5665_dac_r1_mux =
2101 SOC_DAPM_ENUM("DAC R1 Source", rt5665_dac_r1_enum);
2102
2103 static SOC_ENUM_SINGLE_DECL(
2104 rt5665_dac_l1_enum, RT5665_AD_DA_MIXER,
2105 RT5665_DAC1_L_SEL_SFT, rt5665_dac1_src);
2106
2107 static const struct snd_kcontrol_new rt5665_dac_l1_mux =
2108 SOC_DAPM_ENUM("DAC L1 Source", rt5665_dac_l1_enum);
2109
2110 /* DAC Digital Mixer L Source, DAC Digital Mixer R Source*/
2111 /* MX-2D [13:12], MX-2D [9:8]*/
2112 static const char * const rt5665_dig_dac_mix_src[] = {
2113 "Stereo1 DAC Mixer", "Stereo2 DAC Mixer", "Mono DAC Mixer"
2114 };
2115
2116 static SOC_ENUM_SINGLE_DECL(
2117 rt5665_dig_dac_mixl_enum, RT5665_A_DAC1_MUX,
2118 RT5665_DAC_MIX_L_SFT, rt5665_dig_dac_mix_src);
2119
2120 static const struct snd_kcontrol_new rt5665_dig_dac_mixl_mux =
2121 SOC_DAPM_ENUM("DAC Digital Mixer L Source", rt5665_dig_dac_mixl_enum);
2122
2123 static SOC_ENUM_SINGLE_DECL(
2124 rt5665_dig_dac_mixr_enum, RT5665_A_DAC1_MUX,
2125 RT5665_DAC_MIX_R_SFT, rt5665_dig_dac_mix_src);
2126
2127 static const struct snd_kcontrol_new rt5665_dig_dac_mixr_mux =
2128 SOC_DAPM_ENUM("DAC Digital Mixer R Source", rt5665_dig_dac_mixr_enum);
2129
2130 /* Analog DAC L1 Source, Analog DAC R1 Source*/
2131 /* MX-2D [5:4], MX-2D [1:0]*/
2132 static const char * const rt5665_alg_dac1_src[] = {
2133 "Stereo1 DAC Mixer", "DAC1", "DMIC1"
2134 };
2135
2136 static SOC_ENUM_SINGLE_DECL(
2137 rt5665_alg_dac_l1_enum, RT5665_A_DAC1_MUX,
2138 RT5665_A_DACL1_SFT, rt5665_alg_dac1_src);
2139
2140 static const struct snd_kcontrol_new rt5665_alg_dac_l1_mux =
2141 SOC_DAPM_ENUM("Analog DAC L1 Source", rt5665_alg_dac_l1_enum);
2142
2143 static SOC_ENUM_SINGLE_DECL(
2144 rt5665_alg_dac_r1_enum, RT5665_A_DAC1_MUX,
2145 RT5665_A_DACR1_SFT, rt5665_alg_dac1_src);
2146
2147 static const struct snd_kcontrol_new rt5665_alg_dac_r1_mux =
2148 SOC_DAPM_ENUM("Analog DAC R1 Source", rt5665_alg_dac_r1_enum);
2149
2150 /* Analog DAC LR Source, Analog DAC R2 Source*/
2151 /* MX-2E [5:4], MX-2E [0]*/
2152 static const char * const rt5665_alg_dac2_src[] = {
2153 "Mono DAC Mixer", "DAC2"
2154 };
2155
2156 static SOC_ENUM_SINGLE_DECL(
2157 rt5665_alg_dac_l2_enum, RT5665_A_DAC2_MUX,
2158 RT5665_A_DACL2_SFT, rt5665_alg_dac2_src);
2159
2160 static const struct snd_kcontrol_new rt5665_alg_dac_l2_mux =
2161 SOC_DAPM_ENUM("Analog DAC L2 Source", rt5665_alg_dac_l2_enum);
2162
2163 static SOC_ENUM_SINGLE_DECL(
2164 rt5665_alg_dac_r2_enum, RT5665_A_DAC2_MUX,
2165 RT5665_A_DACR2_SFT, rt5665_alg_dac2_src);
2166
2167 static const struct snd_kcontrol_new rt5665_alg_dac_r2_mux =
2168 SOC_DAPM_ENUM("Analog DAC R2 Source", rt5665_alg_dac_r2_enum);
2169
2170 /* Interface2 ADC Data Input*/
2171 /* MX-2F [14:12] */
2172 static const char * const rt5665_if2_1_adc_in_src[] = {
2173 "STO1 ADC", "STO2 ADC", "MONO ADC", "IF1 DAC1",
2174 "IF1 DAC2", "IF2_2 DAC", "IF3 DAC", "DAC1 MIX"
2175 };
2176
2177 static SOC_ENUM_SINGLE_DECL(
2178 rt5665_if2_1_adc_in_enum, RT5665_DIG_INF2_DATA,
2179 RT5665_IF2_1_ADC_IN_SFT, rt5665_if2_1_adc_in_src);
2180
2181 static const struct snd_kcontrol_new rt5665_if2_1_adc_in_mux =
2182 SOC_DAPM_ENUM("IF2_1 ADC IN Source", rt5665_if2_1_adc_in_enum);
2183
2184 /* MX-2F [6:4] */
2185 static const char * const rt5665_if2_2_adc_in_src[] = {
2186 "STO1 ADC", "STO2 ADC", "MONO ADC", "IF1 DAC1",
2187 "IF1 DAC2", "IF2_1 DAC", "IF3 DAC", "DAC1 MIX"
2188 };
2189
2190 static SOC_ENUM_SINGLE_DECL(
2191 rt5665_if2_2_adc_in_enum, RT5665_DIG_INF2_DATA,
2192 RT5665_IF2_2_ADC_IN_SFT, rt5665_if2_2_adc_in_src);
2193
2194 static const struct snd_kcontrol_new rt5665_if2_2_adc_in_mux =
2195 SOC_DAPM_ENUM("IF2_1 ADC IN Source", rt5665_if2_2_adc_in_enum);
2196
2197 /* Interface3 ADC Data Input*/
2198 /* MX-30 [6:4] */
2199 static const char * const rt5665_if3_adc_in_src[] = {
2200 "STO1 ADC", "STO2 ADC", "MONO ADC", "IF1 DAC1",
2201 "IF1 DAC2", "IF2_1 DAC", "IF2_2 DAC", "DAC1 MIX"
2202 };
2203
2204 static SOC_ENUM_SINGLE_DECL(
2205 rt5665_if3_adc_in_enum, RT5665_DIG_INF3_DATA,
2206 RT5665_IF3_ADC_IN_SFT, rt5665_if3_adc_in_src);
2207
2208 static const struct snd_kcontrol_new rt5665_if3_adc_in_mux =
2209 SOC_DAPM_ENUM("IF3 ADC IN Source", rt5665_if3_adc_in_enum);
2210
2211 /* PDM 1 L/R*/
2212 /* MX-31 [11:10] [9:8] */
2213 static const char * const rt5665_pdm_src[] = {
2214 "Stereo1 DAC", "Stereo2 DAC", "Mono DAC"
2215 };
2216
2217 static SOC_ENUM_SINGLE_DECL(
2218 rt5665_pdm_l_enum, RT5665_PDM_OUT_CTRL,
2219 RT5665_PDM1_L_SFT, rt5665_pdm_src);
2220
2221 static const struct snd_kcontrol_new rt5665_pdm_l_mux =
2222 SOC_DAPM_ENUM("PDM L Source", rt5665_pdm_l_enum);
2223
2224 static SOC_ENUM_SINGLE_DECL(
2225 rt5665_pdm_r_enum, RT5665_PDM_OUT_CTRL,
2226 RT5665_PDM1_R_SFT, rt5665_pdm_src);
2227
2228 static const struct snd_kcontrol_new rt5665_pdm_r_mux =
2229 SOC_DAPM_ENUM("PDM R Source", rt5665_pdm_r_enum);
2230
2231
2232 /* I2S1 TDM ADCDAT Source */
2233 /* MX-7a[10] */
2234 static const char * const rt5665_if1_1_adc1_data_src[] = {
2235 "STO1 ADC", "IF2_1 DAC",
2236 };
2237
2238 static SOC_ENUM_SINGLE_DECL(
2239 rt5665_if1_1_adc1_data_enum, RT5665_TDM_CTRL_3,
2240 RT5665_IF1_ADC1_SEL_SFT, rt5665_if1_1_adc1_data_src);
2241
2242 static const struct snd_kcontrol_new rt5665_if1_1_adc1_mux =
2243 SOC_DAPM_ENUM("IF1_1 ADC1 Source", rt5665_if1_1_adc1_data_enum);
2244
2245 /* MX-7a[9] */
2246 static const char * const rt5665_if1_1_adc2_data_src[] = {
2247 "STO2 ADC", "IF2_2 DAC",
2248 };
2249
2250 static SOC_ENUM_SINGLE_DECL(
2251 rt5665_if1_1_adc2_data_enum, RT5665_TDM_CTRL_3,
2252 RT5665_IF1_ADC2_SEL_SFT, rt5665_if1_1_adc2_data_src);
2253
2254 static const struct snd_kcontrol_new rt5665_if1_1_adc2_mux =
2255 SOC_DAPM_ENUM("IF1_1 ADC2 Source", rt5665_if1_1_adc2_data_enum);
2256
2257 /* MX-7a[8] */
2258 static const char * const rt5665_if1_1_adc3_data_src[] = {
2259 "MONO ADC", "IF3 DAC",
2260 };
2261
2262 static SOC_ENUM_SINGLE_DECL(
2263 rt5665_if1_1_adc3_data_enum, RT5665_TDM_CTRL_3,
2264 RT5665_IF1_ADC3_SEL_SFT, rt5665_if1_1_adc3_data_src);
2265
2266 static const struct snd_kcontrol_new rt5665_if1_1_adc3_mux =
2267 SOC_DAPM_ENUM("IF1_1 ADC3 Source", rt5665_if1_1_adc3_data_enum);
2268
2269 /* MX-7b[10] */
2270 static const char * const rt5665_if1_2_adc1_data_src[] = {
2271 "STO1 ADC", "IF1 DAC",
2272 };
2273
2274 static SOC_ENUM_SINGLE_DECL(
2275 rt5665_if1_2_adc1_data_enum, RT5665_TDM_CTRL_4,
2276 RT5665_IF1_ADC1_SEL_SFT, rt5665_if1_2_adc1_data_src);
2277
2278 static const struct snd_kcontrol_new rt5665_if1_2_adc1_mux =
2279 SOC_DAPM_ENUM("IF1_2 ADC1 Source", rt5665_if1_2_adc1_data_enum);
2280
2281 /* MX-7b[9] */
2282 static const char * const rt5665_if1_2_adc2_data_src[] = {
2283 "STO2 ADC", "IF2_1 DAC",
2284 };
2285
2286 static SOC_ENUM_SINGLE_DECL(
2287 rt5665_if1_2_adc2_data_enum, RT5665_TDM_CTRL_4,
2288 RT5665_IF1_ADC2_SEL_SFT, rt5665_if1_2_adc2_data_src);
2289
2290 static const struct snd_kcontrol_new rt5665_if1_2_adc2_mux =
2291 SOC_DAPM_ENUM("IF1_2 ADC2 Source", rt5665_if1_2_adc2_data_enum);
2292
2293 /* MX-7b[8] */
2294 static const char * const rt5665_if1_2_adc3_data_src[] = {
2295 "MONO ADC", "IF2_2 DAC",
2296 };
2297
2298 static SOC_ENUM_SINGLE_DECL(
2299 rt5665_if1_2_adc3_data_enum, RT5665_TDM_CTRL_4,
2300 RT5665_IF1_ADC3_SEL_SFT, rt5665_if1_2_adc3_data_src);
2301
2302 static const struct snd_kcontrol_new rt5665_if1_2_adc3_mux =
2303 SOC_DAPM_ENUM("IF1_2 ADC3 Source", rt5665_if1_2_adc3_data_enum);
2304
2305 /* MX-7b[7] */
2306 static const char * const rt5665_if1_2_adc4_data_src[] = {
2307 "DAC1", "IF3 DAC",
2308 };
2309
2310 static SOC_ENUM_SINGLE_DECL(
2311 rt5665_if1_2_adc4_data_enum, RT5665_TDM_CTRL_4,
2312 RT5665_IF1_ADC4_SEL_SFT, rt5665_if1_2_adc4_data_src);
2313
2314 static const struct snd_kcontrol_new rt5665_if1_2_adc4_mux =
2315 SOC_DAPM_ENUM("IF1_2 ADC4 Source", rt5665_if1_2_adc4_data_enum);
2316
2317 /* MX-7a[4:0] MX-7b[4:0] */
2318 static const char * const rt5665_tdm_adc_data_src[] = {
2319 "1234", "1243", "1324", "1342", "1432", "1423",
2320 "2134", "2143", "2314", "2341", "2431", "2413",
2321 "3124", "3142", "3214", "3241", "3412", "3421",
2322 "4123", "4132", "4213", "4231", "4312", "4321"
2323 };
2324
2325 static SOC_ENUM_SINGLE_DECL(
2326 rt5665_tdm1_adc_data_enum, RT5665_TDM_CTRL_3,
2327 RT5665_TDM_ADC_SEL_SFT, rt5665_tdm_adc_data_src);
2328
2329 static const struct snd_kcontrol_new rt5665_tdm1_adc_mux =
2330 SOC_DAPM_ENUM("TDM1 ADC Mux", rt5665_tdm1_adc_data_enum);
2331
2332 static SOC_ENUM_SINGLE_DECL(
2333 rt5665_tdm2_adc_data_enum, RT5665_TDM_CTRL_4,
2334 RT5665_TDM_ADC_SEL_SFT, rt5665_tdm_adc_data_src);
2335
2336 static const struct snd_kcontrol_new rt5665_tdm2_adc_mux =
2337 SOC_DAPM_ENUM("TDM2 ADCDAT Source", rt5665_tdm2_adc_data_enum);
2338
2339 /* Out Volume Switch */
2340 static const struct snd_kcontrol_new monovol_switch =
2341 SOC_DAPM_SINGLE("Switch", RT5665_MONO_OUT, RT5665_VOL_L_SFT, 1, 1);
2342
2343 static const struct snd_kcontrol_new outvol_l_switch =
2344 SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_VOL_L_SFT, 1, 1);
2345
2346 static const struct snd_kcontrol_new outvol_r_switch =
2347 SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_VOL_R_SFT, 1, 1);
2348
2349 /* Out Switch */
2350 static const struct snd_kcontrol_new mono_switch =
2351 SOC_DAPM_SINGLE("Switch", RT5665_MONO_OUT, RT5665_L_MUTE_SFT, 1, 1);
2352
2353 static const struct snd_kcontrol_new hpo_switch =
2354 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5665_HP_CTRL_2,
2355 RT5665_VOL_L_SFT, 1, 0);
2356
2357 static const struct snd_kcontrol_new lout_l_switch =
2358 SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_L_MUTE_SFT, 1, 1);
2359
2360 static const struct snd_kcontrol_new lout_r_switch =
2361 SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_R_MUTE_SFT, 1, 1);
2362
2363 static const struct snd_kcontrol_new pdm_l_switch =
2364 SOC_DAPM_SINGLE("Switch", RT5665_PDM_OUT_CTRL,
2365 RT5665_M_PDM1_L_SFT, 1, 1);
2366
2367 static const struct snd_kcontrol_new pdm_r_switch =
2368 SOC_DAPM_SINGLE("Switch", RT5665_PDM_OUT_CTRL,
2369 RT5665_M_PDM1_R_SFT, 1, 1);
2370
rt5665_mono_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)2371 static int rt5665_mono_event(struct snd_soc_dapm_widget *w,
2372 struct snd_kcontrol *kcontrol, int event)
2373 {
2374 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2375
2376 switch (event) {
2377 case SND_SOC_DAPM_PRE_PMU:
2378 snd_soc_component_update_bits(component, RT5665_MONO_NG2_CTRL_1,
2379 RT5665_NG2_EN_MASK, RT5665_NG2_EN);
2380 snd_soc_component_update_bits(component, RT5665_MONO_AMP_CALIB_CTRL_1, 0x40,
2381 0x0);
2382 snd_soc_component_update_bits(component, RT5665_MONO_OUT, 0x10, 0x10);
2383 snd_soc_component_update_bits(component, RT5665_MONO_OUT, 0x20, 0x20);
2384 break;
2385
2386 case SND_SOC_DAPM_POST_PMD:
2387 snd_soc_component_update_bits(component, RT5665_MONO_OUT, 0x20, 0);
2388 snd_soc_component_update_bits(component, RT5665_MONO_OUT, 0x10, 0);
2389 snd_soc_component_update_bits(component, RT5665_MONO_AMP_CALIB_CTRL_1, 0x40,
2390 0x40);
2391 snd_soc_component_update_bits(component, RT5665_MONO_NG2_CTRL_1,
2392 RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
2393 break;
2394
2395 default:
2396 return 0;
2397 }
2398
2399 return 0;
2400
2401 }
2402
rt5665_hp_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)2403 static int rt5665_hp_event(struct snd_soc_dapm_widget *w,
2404 struct snd_kcontrol *kcontrol, int event)
2405 {
2406 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2407
2408 switch (event) {
2409 case SND_SOC_DAPM_PRE_PMU:
2410 snd_soc_component_update_bits(component, RT5665_STO_NG2_CTRL_1,
2411 RT5665_NG2_EN_MASK, RT5665_NG2_EN);
2412 snd_soc_component_write(component, RT5665_HP_LOGIC_CTRL_2, 0x0003);
2413 break;
2414
2415 case SND_SOC_DAPM_POST_PMD:
2416 snd_soc_component_write(component, RT5665_HP_LOGIC_CTRL_2, 0x0002);
2417 snd_soc_component_update_bits(component, RT5665_STO_NG2_CTRL_1,
2418 RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
2419 break;
2420
2421 default:
2422 return 0;
2423 }
2424
2425 return 0;
2426
2427 }
2428
rt5665_lout_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)2429 static int rt5665_lout_event(struct snd_soc_dapm_widget *w,
2430 struct snd_kcontrol *kcontrol, int event)
2431 {
2432 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2433
2434 switch (event) {
2435 case SND_SOC_DAPM_POST_PMU:
2436 snd_soc_component_update_bits(component, RT5665_DEPOP_1,
2437 RT5665_PUMP_EN, RT5665_PUMP_EN);
2438 break;
2439
2440 case SND_SOC_DAPM_PRE_PMD:
2441 snd_soc_component_update_bits(component, RT5665_DEPOP_1,
2442 RT5665_PUMP_EN, 0);
2443 break;
2444
2445 default:
2446 return 0;
2447 }
2448
2449 return 0;
2450
2451 }
2452
set_dmic_power(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)2453 static int set_dmic_power(struct snd_soc_dapm_widget *w,
2454 struct snd_kcontrol *kcontrol, int event)
2455 {
2456 switch (event) {
2457 case SND_SOC_DAPM_POST_PMU:
2458 /*Add delay to avoid pop noise*/
2459 msleep(150);
2460 break;
2461
2462 default:
2463 return 0;
2464 }
2465
2466 return 0;
2467 }
2468
rt5665_set_verf(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)2469 static int rt5665_set_verf(struct snd_soc_dapm_widget *w,
2470 struct snd_kcontrol *kcontrol, int event)
2471 {
2472 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2473
2474 switch (event) {
2475 case SND_SOC_DAPM_PRE_PMU:
2476 switch (w->shift) {
2477 case RT5665_PWR_VREF1_BIT:
2478 snd_soc_component_update_bits(component, RT5665_PWR_ANLG_1,
2479 RT5665_PWR_FV1, 0);
2480 break;
2481
2482 case RT5665_PWR_VREF2_BIT:
2483 snd_soc_component_update_bits(component, RT5665_PWR_ANLG_1,
2484 RT5665_PWR_FV2, 0);
2485 break;
2486
2487 case RT5665_PWR_VREF3_BIT:
2488 snd_soc_component_update_bits(component, RT5665_PWR_ANLG_1,
2489 RT5665_PWR_FV3, 0);
2490 break;
2491
2492 default:
2493 break;
2494 }
2495 break;
2496
2497 case SND_SOC_DAPM_POST_PMU:
2498 usleep_range(15000, 20000);
2499 switch (w->shift) {
2500 case RT5665_PWR_VREF1_BIT:
2501 snd_soc_component_update_bits(component, RT5665_PWR_ANLG_1,
2502 RT5665_PWR_FV1, RT5665_PWR_FV1);
2503 break;
2504
2505 case RT5665_PWR_VREF2_BIT:
2506 snd_soc_component_update_bits(component, RT5665_PWR_ANLG_1,
2507 RT5665_PWR_FV2, RT5665_PWR_FV2);
2508 break;
2509
2510 case RT5665_PWR_VREF3_BIT:
2511 snd_soc_component_update_bits(component, RT5665_PWR_ANLG_1,
2512 RT5665_PWR_FV3, RT5665_PWR_FV3);
2513 break;
2514
2515 default:
2516 break;
2517 }
2518 break;
2519
2520 default:
2521 return 0;
2522 }
2523
2524 return 0;
2525 }
2526
rt5665_i2s_pin_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)2527 static int rt5665_i2s_pin_event(struct snd_soc_dapm_widget *w,
2528 struct snd_kcontrol *kcontrol, int event)
2529 {
2530 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2531 unsigned int val1, val2, mask1 = 0, mask2 = 0;
2532
2533 switch (w->shift) {
2534 case RT5665_PWR_I2S2_1_BIT:
2535 mask1 = RT5665_GP2_PIN_MASK | RT5665_GP3_PIN_MASK |
2536 RT5665_GP4_PIN_MASK | RT5665_GP5_PIN_MASK;
2537 val1 = RT5665_GP2_PIN_BCLK2 | RT5665_GP3_PIN_LRCK2 |
2538 RT5665_GP4_PIN_DACDAT2_1 | RT5665_GP5_PIN_ADCDAT2_1;
2539 break;
2540 case RT5665_PWR_I2S2_2_BIT:
2541 mask1 = RT5665_GP2_PIN_MASK | RT5665_GP3_PIN_MASK |
2542 RT5665_GP8_PIN_MASK;
2543 val1 = RT5665_GP2_PIN_BCLK2 | RT5665_GP3_PIN_LRCK2 |
2544 RT5665_GP8_PIN_DACDAT2_2;
2545 mask2 = RT5665_GP9_PIN_MASK;
2546 val2 = RT5665_GP9_PIN_ADCDAT2_2;
2547 break;
2548 case RT5665_PWR_I2S3_BIT:
2549 mask1 = RT5665_GP6_PIN_MASK | RT5665_GP7_PIN_MASK |
2550 RT5665_GP8_PIN_MASK;
2551 val1 = RT5665_GP6_PIN_BCLK3 | RT5665_GP7_PIN_LRCK3 |
2552 RT5665_GP8_PIN_DACDAT3;
2553 mask2 = RT5665_GP9_PIN_MASK;
2554 val2 = RT5665_GP9_PIN_ADCDAT3;
2555 break;
2556 }
2557 switch (event) {
2558 case SND_SOC_DAPM_PRE_PMU:
2559 if (mask1)
2560 snd_soc_component_update_bits(component, RT5665_GPIO_CTRL_1,
2561 mask1, val1);
2562 if (mask2)
2563 snd_soc_component_update_bits(component, RT5665_GPIO_CTRL_2,
2564 mask2, val2);
2565 break;
2566 case SND_SOC_DAPM_POST_PMD:
2567 if (mask1)
2568 snd_soc_component_update_bits(component, RT5665_GPIO_CTRL_1,
2569 mask1, 0);
2570 if (mask2)
2571 snd_soc_component_update_bits(component, RT5665_GPIO_CTRL_2,
2572 mask2, 0);
2573 break;
2574 default:
2575 return 0;
2576 }
2577
2578 return 0;
2579 }
2580
2581 static const struct snd_soc_dapm_widget rt5665_dapm_widgets[] = {
2582 SND_SOC_DAPM_SUPPLY("LDO2", RT5665_PWR_ANLG_3, RT5665_PWR_LDO2_BIT, 0,
2583 NULL, 0),
2584 SND_SOC_DAPM_SUPPLY("PLL", RT5665_PWR_ANLG_3, RT5665_PWR_PLL_BIT, 0,
2585 NULL, 0),
2586 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5665_PWR_VOL,
2587 RT5665_PWR_MIC_DET_BIT, 0, NULL, 0),
2588 SND_SOC_DAPM_SUPPLY("Vref1", RT5665_PWR_ANLG_1, RT5665_PWR_VREF1_BIT, 0,
2589 rt5665_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
2590 SND_SOC_DAPM_SUPPLY("Vref2", RT5665_PWR_ANLG_1, RT5665_PWR_VREF2_BIT, 0,
2591 rt5665_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
2592 SND_SOC_DAPM_SUPPLY("Vref3", RT5665_PWR_ANLG_1, RT5665_PWR_VREF3_BIT, 0,
2593 rt5665_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
2594
2595 /* ASRC */
2596 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5665_ASRC_1,
2597 RT5665_I2S1_ASRC_SFT, 0, NULL, 0),
2598 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5665_ASRC_1,
2599 RT5665_I2S2_ASRC_SFT, 0, NULL, 0),
2600 SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5665_ASRC_1,
2601 RT5665_I2S3_ASRC_SFT, 0, NULL, 0),
2602 SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5665_ASRC_1,
2603 RT5665_DAC_STO1_ASRC_SFT, 0, NULL, 0),
2604 SND_SOC_DAPM_SUPPLY_S("DAC STO2 ASRC", 1, RT5665_ASRC_1,
2605 RT5665_DAC_STO2_ASRC_SFT, 0, NULL, 0),
2606 SND_SOC_DAPM_SUPPLY_S("DAC Mono L ASRC", 1, RT5665_ASRC_1,
2607 RT5665_DAC_MONO_L_ASRC_SFT, 0, NULL, 0),
2608 SND_SOC_DAPM_SUPPLY_S("DAC Mono R ASRC", 1, RT5665_ASRC_1,
2609 RT5665_DAC_MONO_R_ASRC_SFT, 0, NULL, 0),
2610 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5665_ASRC_1,
2611 RT5665_ADC_STO1_ASRC_SFT, 0, NULL, 0),
2612 SND_SOC_DAPM_SUPPLY_S("ADC STO2 ASRC", 1, RT5665_ASRC_1,
2613 RT5665_ADC_STO2_ASRC_SFT, 0, NULL, 0),
2614 SND_SOC_DAPM_SUPPLY_S("ADC Mono L ASRC", 1, RT5665_ASRC_1,
2615 RT5665_ADC_MONO_L_ASRC_SFT, 0, NULL, 0),
2616 SND_SOC_DAPM_SUPPLY_S("ADC Mono R ASRC", 1, RT5665_ASRC_1,
2617 RT5665_ADC_MONO_R_ASRC_SFT, 0, NULL, 0),
2618 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5665_ASRC_1,
2619 RT5665_DMIC_STO1_ASRC_SFT, 0, NULL, 0),
2620 SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC", 1, RT5665_ASRC_1,
2621 RT5665_DMIC_STO2_ASRC_SFT, 0, NULL, 0),
2622 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5665_ASRC_1,
2623 RT5665_DMIC_MONO_L_ASRC_SFT, 0, NULL, 0),
2624 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5665_ASRC_1,
2625 RT5665_DMIC_MONO_R_ASRC_SFT, 0, NULL, 0),
2626
2627 /* Input Side */
2628 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5665_PWR_ANLG_2, RT5665_PWR_MB1_BIT,
2629 0, NULL, 0),
2630 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5665_PWR_ANLG_2, RT5665_PWR_MB2_BIT,
2631 0, NULL, 0),
2632 SND_SOC_DAPM_SUPPLY("MICBIAS3", RT5665_PWR_ANLG_2, RT5665_PWR_MB3_BIT,
2633 0, NULL, 0),
2634
2635 /* Input Lines */
2636 SND_SOC_DAPM_INPUT("DMIC L1"),
2637 SND_SOC_DAPM_INPUT("DMIC R1"),
2638 SND_SOC_DAPM_INPUT("DMIC L2"),
2639 SND_SOC_DAPM_INPUT("DMIC R2"),
2640
2641 SND_SOC_DAPM_INPUT("IN1P"),
2642 SND_SOC_DAPM_INPUT("IN1N"),
2643 SND_SOC_DAPM_INPUT("IN2P"),
2644 SND_SOC_DAPM_INPUT("IN2N"),
2645 SND_SOC_DAPM_INPUT("IN3P"),
2646 SND_SOC_DAPM_INPUT("IN3N"),
2647 SND_SOC_DAPM_INPUT("IN4P"),
2648 SND_SOC_DAPM_INPUT("IN4N"),
2649
2650 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2651 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2652
2653 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
2654 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
2655 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5665_DMIC_CTRL_1,
2656 RT5665_DMIC_1_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
2657 SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5665_DMIC_CTRL_1,
2658 RT5665_DMIC_2_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
2659
2660 /* Boost */
2661 SND_SOC_DAPM_PGA("BST1", SND_SOC_NOPM,
2662 0, 0, NULL, 0),
2663 SND_SOC_DAPM_PGA("BST2", SND_SOC_NOPM,
2664 0, 0, NULL, 0),
2665 SND_SOC_DAPM_PGA("BST3", SND_SOC_NOPM,
2666 0, 0, NULL, 0),
2667 SND_SOC_DAPM_PGA("BST4", SND_SOC_NOPM,
2668 0, 0, NULL, 0),
2669 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM,
2670 0, 0, NULL, 0),
2671 SND_SOC_DAPM_SUPPLY("BST1 Power", RT5665_PWR_ANLG_2,
2672 RT5665_PWR_BST1_BIT, 0, NULL, 0),
2673 SND_SOC_DAPM_SUPPLY("BST2 Power", RT5665_PWR_ANLG_2,
2674 RT5665_PWR_BST2_BIT, 0, NULL, 0),
2675 SND_SOC_DAPM_SUPPLY("BST3 Power", RT5665_PWR_ANLG_2,
2676 RT5665_PWR_BST3_BIT, 0, NULL, 0),
2677 SND_SOC_DAPM_SUPPLY("BST4 Power", RT5665_PWR_ANLG_2,
2678 RT5665_PWR_BST4_BIT, 0, NULL, 0),
2679 SND_SOC_DAPM_SUPPLY("BST1P Power", RT5665_PWR_ANLG_2,
2680 RT5665_PWR_BST1_P_BIT, 0, NULL, 0),
2681 SND_SOC_DAPM_SUPPLY("BST2P Power", RT5665_PWR_ANLG_2,
2682 RT5665_PWR_BST2_P_BIT, 0, NULL, 0),
2683 SND_SOC_DAPM_SUPPLY("BST3P Power", RT5665_PWR_ANLG_2,
2684 RT5665_PWR_BST3_P_BIT, 0, NULL, 0),
2685 SND_SOC_DAPM_SUPPLY("BST4P Power", RT5665_PWR_ANLG_2,
2686 RT5665_PWR_BST4_P_BIT, 0, NULL, 0),
2687 SND_SOC_DAPM_SUPPLY("CBJ Power", RT5665_PWR_ANLG_3,
2688 RT5665_PWR_CBJ_BIT, 0, NULL, 0),
2689
2690
2691 /* Input Volume */
2692 SND_SOC_DAPM_PGA("INL VOL", RT5665_PWR_VOL, RT5665_PWR_IN_L_BIT,
2693 0, NULL, 0),
2694 SND_SOC_DAPM_PGA("INR VOL", RT5665_PWR_VOL, RT5665_PWR_IN_R_BIT,
2695 0, NULL, 0),
2696
2697 /* REC Mixer */
2698 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5665_rec1_l_mix,
2699 ARRAY_SIZE(rt5665_rec1_l_mix)),
2700 SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM, 0, 0, rt5665_rec1_r_mix,
2701 ARRAY_SIZE(rt5665_rec1_r_mix)),
2702 SND_SOC_DAPM_MIXER("RECMIX2L", SND_SOC_NOPM, 0, 0, rt5665_rec2_l_mix,
2703 ARRAY_SIZE(rt5665_rec2_l_mix)),
2704 SND_SOC_DAPM_MIXER("RECMIX2R", SND_SOC_NOPM, 0, 0, rt5665_rec2_r_mix,
2705 ARRAY_SIZE(rt5665_rec2_r_mix)),
2706 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5665_PWR_ANLG_2,
2707 RT5665_PWR_RM1_L_BIT, 0, NULL, 0),
2708 SND_SOC_DAPM_SUPPLY("RECMIX1R Power", RT5665_PWR_ANLG_2,
2709 RT5665_PWR_RM1_R_BIT, 0, NULL, 0),
2710 SND_SOC_DAPM_SUPPLY("RECMIX2L Power", RT5665_PWR_MIXER,
2711 RT5665_PWR_RM2_L_BIT, 0, NULL, 0),
2712 SND_SOC_DAPM_SUPPLY("RECMIX2R Power", RT5665_PWR_MIXER,
2713 RT5665_PWR_RM2_R_BIT, 0, NULL, 0),
2714
2715 /* ADCs */
2716 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
2717 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
2718 SND_SOC_DAPM_ADC("ADC2 L", NULL, SND_SOC_NOPM, 0, 0),
2719 SND_SOC_DAPM_ADC("ADC2 R", NULL, SND_SOC_NOPM, 0, 0),
2720
2721 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5665_PWR_DIG_1,
2722 RT5665_PWR_ADC_L1_BIT, 0, NULL, 0),
2723 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5665_PWR_DIG_1,
2724 RT5665_PWR_ADC_R1_BIT, 0, NULL, 0),
2725 SND_SOC_DAPM_SUPPLY("ADC2 L Power", RT5665_PWR_DIG_1,
2726 RT5665_PWR_ADC_L2_BIT, 0, NULL, 0),
2727 SND_SOC_DAPM_SUPPLY("ADC2 R Power", RT5665_PWR_DIG_1,
2728 RT5665_PWR_ADC_R2_BIT, 0, NULL, 0),
2729 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5665_CHOP_ADC,
2730 RT5665_CKGEN_ADC1_SFT, 0, NULL, 0),
2731 SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5665_CHOP_ADC,
2732 RT5665_CKGEN_ADC2_SFT, 0, NULL, 0),
2733
2734 /* ADC Mux */
2735 SND_SOC_DAPM_MUX("Stereo1 DMIC L Mux", SND_SOC_NOPM, 0, 0,
2736 &rt5665_sto1_dmic_mux),
2737 SND_SOC_DAPM_MUX("Stereo1 DMIC R Mux", SND_SOC_NOPM, 0, 0,
2738 &rt5665_sto1_dmic_mux),
2739 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2740 &rt5665_sto1_adc1l_mux),
2741 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2742 &rt5665_sto1_adc1r_mux),
2743 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2744 &rt5665_sto1_adc2l_mux),
2745 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2746 &rt5665_sto1_adc2r_mux),
2747 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
2748 &rt5665_sto1_adcl_mux),
2749 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
2750 &rt5665_sto1_adcr_mux),
2751 SND_SOC_DAPM_MUX("Stereo1 DD L Mux", SND_SOC_NOPM, 0, 0,
2752 &rt5665_sto1_dd_l_mux),
2753 SND_SOC_DAPM_MUX("Stereo1 DD R Mux", SND_SOC_NOPM, 0, 0,
2754 &rt5665_sto1_dd_r_mux),
2755 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2756 &rt5665_mono_adc_l2_mux),
2757 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2758 &rt5665_mono_adc_r2_mux),
2759 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2760 &rt5665_mono_adc_l1_mux),
2761 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2762 &rt5665_mono_adc_r1_mux),
2763 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2764 &rt5665_mono_dmic_l_mux),
2765 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2766 &rt5665_mono_dmic_r_mux),
2767 SND_SOC_DAPM_MUX("Mono ADC L Mux", SND_SOC_NOPM, 0, 0,
2768 &rt5665_mono_adc_l_mux),
2769 SND_SOC_DAPM_MUX("Mono ADC R Mux", SND_SOC_NOPM, 0, 0,
2770 &rt5665_mono_adc_r_mux),
2771 SND_SOC_DAPM_MUX("Mono DD L Mux", SND_SOC_NOPM, 0, 0,
2772 &rt5665_mono_dd_l_mux),
2773 SND_SOC_DAPM_MUX("Mono DD R Mux", SND_SOC_NOPM, 0, 0,
2774 &rt5665_mono_dd_r_mux),
2775 SND_SOC_DAPM_MUX("Stereo2 DMIC L Mux", SND_SOC_NOPM, 0, 0,
2776 &rt5665_sto2_dmic_mux),
2777 SND_SOC_DAPM_MUX("Stereo2 DMIC R Mux", SND_SOC_NOPM, 0, 0,
2778 &rt5665_sto2_dmic_mux),
2779 SND_SOC_DAPM_MUX("Stereo2 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2780 &rt5665_sto2_adc1l_mux),
2781 SND_SOC_DAPM_MUX("Stereo2 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2782 &rt5665_sto2_adc1r_mux),
2783 SND_SOC_DAPM_MUX("Stereo2 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2784 &rt5665_sto2_adc2l_mux),
2785 SND_SOC_DAPM_MUX("Stereo2 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2786 &rt5665_sto2_adc2r_mux),
2787 SND_SOC_DAPM_MUX("Stereo2 ADC L Mux", SND_SOC_NOPM, 0, 0,
2788 &rt5665_sto2_adcl_mux),
2789 SND_SOC_DAPM_MUX("Stereo2 ADC R Mux", SND_SOC_NOPM, 0, 0,
2790 &rt5665_sto2_adcr_mux),
2791 SND_SOC_DAPM_MUX("Stereo2 DD L Mux", SND_SOC_NOPM, 0, 0,
2792 &rt5665_sto2_dd_l_mux),
2793 SND_SOC_DAPM_MUX("Stereo2 DD R Mux", SND_SOC_NOPM, 0, 0,
2794 &rt5665_sto2_dd_r_mux),
2795 /* ADC Mixer */
2796 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5665_PWR_DIG_2,
2797 RT5665_PWR_ADC_S1F_BIT, 0, NULL, 0),
2798 SND_SOC_DAPM_SUPPLY("ADC Stereo2 Filter", RT5665_PWR_DIG_2,
2799 RT5665_PWR_ADC_S2F_BIT, 0, NULL, 0),
2800 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5665_STO1_ADC_DIG_VOL,
2801 RT5665_L_MUTE_SFT, 1, rt5665_sto1_adc_l_mix,
2802 ARRAY_SIZE(rt5665_sto1_adc_l_mix)),
2803 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5665_STO1_ADC_DIG_VOL,
2804 RT5665_R_MUTE_SFT, 1, rt5665_sto1_adc_r_mix,
2805 ARRAY_SIZE(rt5665_sto1_adc_r_mix)),
2806 SND_SOC_DAPM_MIXER("Stereo2 ADC MIXL", RT5665_STO2_ADC_DIG_VOL,
2807 RT5665_L_MUTE_SFT, 1, rt5665_sto2_adc_l_mix,
2808 ARRAY_SIZE(rt5665_sto2_adc_l_mix)),
2809 SND_SOC_DAPM_MIXER("Stereo2 ADC MIXR", RT5665_STO2_ADC_DIG_VOL,
2810 RT5665_R_MUTE_SFT, 1, rt5665_sto2_adc_r_mix,
2811 ARRAY_SIZE(rt5665_sto2_adc_r_mix)),
2812 SND_SOC_DAPM_SUPPLY("ADC Mono Left Filter", RT5665_PWR_DIG_2,
2813 RT5665_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2814 SND_SOC_DAPM_MIXER("Mono ADC MIXL", RT5665_MONO_ADC_DIG_VOL,
2815 RT5665_L_MUTE_SFT, 1, rt5665_mono_adc_l_mix,
2816 ARRAY_SIZE(rt5665_mono_adc_l_mix)),
2817 SND_SOC_DAPM_SUPPLY("ADC Mono Right Filter", RT5665_PWR_DIG_2,
2818 RT5665_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2819 SND_SOC_DAPM_MIXER("Mono ADC MIXR", RT5665_MONO_ADC_DIG_VOL,
2820 RT5665_R_MUTE_SFT, 1, rt5665_mono_adc_r_mix,
2821 ARRAY_SIZE(rt5665_mono_adc_r_mix)),
2822
2823 /* ADC PGA */
2824 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2825 SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2826 SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2827
2828 /* Digital Interface */
2829 SND_SOC_DAPM_SUPPLY("I2S1_1", RT5665_PWR_DIG_1, RT5665_PWR_I2S1_1_BIT,
2830 0, NULL, 0),
2831 SND_SOC_DAPM_SUPPLY("I2S1_2", RT5665_PWR_DIG_1, RT5665_PWR_I2S1_2_BIT,
2832 0, NULL, 0),
2833 SND_SOC_DAPM_SUPPLY("I2S2_1", RT5665_PWR_DIG_1, RT5665_PWR_I2S2_1_BIT,
2834 0, rt5665_i2s_pin_event, SND_SOC_DAPM_PRE_PMU |
2835 SND_SOC_DAPM_POST_PMD),
2836 SND_SOC_DAPM_SUPPLY("I2S2_2", RT5665_PWR_DIG_1, RT5665_PWR_I2S2_2_BIT,
2837 0, rt5665_i2s_pin_event, SND_SOC_DAPM_PRE_PMU |
2838 SND_SOC_DAPM_POST_PMD),
2839 SND_SOC_DAPM_SUPPLY("I2S3", RT5665_PWR_DIG_1, RT5665_PWR_I2S3_BIT,
2840 0, rt5665_i2s_pin_event, SND_SOC_DAPM_PRE_PMU |
2841 SND_SOC_DAPM_POST_PMD),
2842 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2843 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2844 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2845 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2846 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2847 SND_SOC_DAPM_PGA("IF1 DAC2 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2848 SND_SOC_DAPM_PGA("IF1 DAC2 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2849 SND_SOC_DAPM_PGA("IF1 DAC3 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2850 SND_SOC_DAPM_PGA("IF1 DAC3 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2851
2852 SND_SOC_DAPM_PGA("IF2_1 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2853 SND_SOC_DAPM_PGA("IF2_2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2854 SND_SOC_DAPM_PGA("IF2_1 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2855 SND_SOC_DAPM_PGA("IF2_1 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2856 SND_SOC_DAPM_PGA("IF2_2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2857 SND_SOC_DAPM_PGA("IF2_2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2858 SND_SOC_DAPM_PGA("IF2_1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2859 SND_SOC_DAPM_PGA("IF2_2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2860
2861 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2862 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2863 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2864 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2865
2866 /* Digital Interface Select */
2867 SND_SOC_DAPM_MUX("IF1_1_ADC1 Mux", SND_SOC_NOPM, 0, 0,
2868 &rt5665_if1_1_adc1_mux),
2869 SND_SOC_DAPM_MUX("IF1_1_ADC2 Mux", SND_SOC_NOPM, 0, 0,
2870 &rt5665_if1_1_adc2_mux),
2871 SND_SOC_DAPM_MUX("IF1_1_ADC3 Mux", SND_SOC_NOPM, 0, 0,
2872 &rt5665_if1_1_adc3_mux),
2873 SND_SOC_DAPM_PGA("IF1_1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2874 SND_SOC_DAPM_MUX("IF1_2_ADC1 Mux", SND_SOC_NOPM, 0, 0,
2875 &rt5665_if1_2_adc1_mux),
2876 SND_SOC_DAPM_MUX("IF1_2_ADC2 Mux", SND_SOC_NOPM, 0, 0,
2877 &rt5665_if1_2_adc2_mux),
2878 SND_SOC_DAPM_MUX("IF1_2_ADC3 Mux", SND_SOC_NOPM, 0, 0,
2879 &rt5665_if1_2_adc3_mux),
2880 SND_SOC_DAPM_MUX("IF1_2_ADC4 Mux", SND_SOC_NOPM, 0, 0,
2881 &rt5665_if1_2_adc4_mux),
2882 SND_SOC_DAPM_MUX("TDM1 slot 01 Data Mux", SND_SOC_NOPM, 0, 0,
2883 &rt5665_tdm1_adc_mux),
2884 SND_SOC_DAPM_MUX("TDM1 slot 23 Data Mux", SND_SOC_NOPM, 0, 0,
2885 &rt5665_tdm1_adc_mux),
2886 SND_SOC_DAPM_MUX("TDM1 slot 45 Data Mux", SND_SOC_NOPM, 0, 0,
2887 &rt5665_tdm1_adc_mux),
2888 SND_SOC_DAPM_MUX("TDM1 slot 67 Data Mux", SND_SOC_NOPM, 0, 0,
2889 &rt5665_tdm1_adc_mux),
2890 SND_SOC_DAPM_MUX("TDM2 slot 01 Data Mux", SND_SOC_NOPM, 0, 0,
2891 &rt5665_tdm2_adc_mux),
2892 SND_SOC_DAPM_MUX("TDM2 slot 23 Data Mux", SND_SOC_NOPM, 0, 0,
2893 &rt5665_tdm2_adc_mux),
2894 SND_SOC_DAPM_MUX("TDM2 slot 45 Data Mux", SND_SOC_NOPM, 0, 0,
2895 &rt5665_tdm2_adc_mux),
2896 SND_SOC_DAPM_MUX("TDM2 slot 67 Data Mux", SND_SOC_NOPM, 0, 0,
2897 &rt5665_tdm2_adc_mux),
2898 SND_SOC_DAPM_MUX("IF2_1 ADC Mux", SND_SOC_NOPM, 0, 0,
2899 &rt5665_if2_1_adc_in_mux),
2900 SND_SOC_DAPM_MUX("IF2_2 ADC Mux", SND_SOC_NOPM, 0, 0,
2901 &rt5665_if2_2_adc_in_mux),
2902 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
2903 &rt5665_if3_adc_in_mux),
2904 SND_SOC_DAPM_MUX("IF1_1 0 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2905 &rt5665_if1_1_01_adc_swap_mux),
2906 SND_SOC_DAPM_MUX("IF1_1 1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2907 &rt5665_if1_1_01_adc_swap_mux),
2908 SND_SOC_DAPM_MUX("IF1_1 2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2909 &rt5665_if1_1_23_adc_swap_mux),
2910 SND_SOC_DAPM_MUX("IF1_1 3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2911 &rt5665_if1_1_23_adc_swap_mux),
2912 SND_SOC_DAPM_MUX("IF1_1 4 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2913 &rt5665_if1_1_45_adc_swap_mux),
2914 SND_SOC_DAPM_MUX("IF1_1 5 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2915 &rt5665_if1_1_45_adc_swap_mux),
2916 SND_SOC_DAPM_MUX("IF1_1 6 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2917 &rt5665_if1_1_67_adc_swap_mux),
2918 SND_SOC_DAPM_MUX("IF1_1 7 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2919 &rt5665_if1_1_67_adc_swap_mux),
2920 SND_SOC_DAPM_MUX("IF1_2 0 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2921 &rt5665_if1_2_01_adc_swap_mux),
2922 SND_SOC_DAPM_MUX("IF1_2 1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2923 &rt5665_if1_2_01_adc_swap_mux),
2924 SND_SOC_DAPM_MUX("IF1_2 2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2925 &rt5665_if1_2_23_adc_swap_mux),
2926 SND_SOC_DAPM_MUX("IF1_2 3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2927 &rt5665_if1_2_23_adc_swap_mux),
2928 SND_SOC_DAPM_MUX("IF1_2 4 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2929 &rt5665_if1_2_45_adc_swap_mux),
2930 SND_SOC_DAPM_MUX("IF1_2 5 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2931 &rt5665_if1_2_45_adc_swap_mux),
2932 SND_SOC_DAPM_MUX("IF1_2 6 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2933 &rt5665_if1_2_67_adc_swap_mux),
2934 SND_SOC_DAPM_MUX("IF1_2 7 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2935 &rt5665_if1_2_67_adc_swap_mux),
2936 SND_SOC_DAPM_MUX("IF2_1 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
2937 &rt5665_if2_1_dac_swap_mux),
2938 SND_SOC_DAPM_MUX("IF2_1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2939 &rt5665_if2_1_adc_swap_mux),
2940 SND_SOC_DAPM_MUX("IF2_2 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
2941 &rt5665_if2_2_dac_swap_mux),
2942 SND_SOC_DAPM_MUX("IF2_2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2943 &rt5665_if2_2_adc_swap_mux),
2944 SND_SOC_DAPM_MUX("IF3 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
2945 &rt5665_if3_dac_swap_mux),
2946 SND_SOC_DAPM_MUX("IF3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2947 &rt5665_if3_adc_swap_mux),
2948
2949 /* Audio Interface */
2950 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 0", "AIF1_1 Capture",
2951 0, SND_SOC_NOPM, 0, 0),
2952 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 1", "AIF1_1 Capture",
2953 1, SND_SOC_NOPM, 0, 0),
2954 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 2", "AIF1_1 Capture",
2955 2, SND_SOC_NOPM, 0, 0),
2956 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 3", "AIF1_1 Capture",
2957 3, SND_SOC_NOPM, 0, 0),
2958 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 4", "AIF1_1 Capture",
2959 4, SND_SOC_NOPM, 0, 0),
2960 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 5", "AIF1_1 Capture",
2961 5, SND_SOC_NOPM, 0, 0),
2962 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 6", "AIF1_1 Capture",
2963 6, SND_SOC_NOPM, 0, 0),
2964 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 7", "AIF1_1 Capture",
2965 7, SND_SOC_NOPM, 0, 0),
2966 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 0", "AIF1_2 Capture",
2967 0, SND_SOC_NOPM, 0, 0),
2968 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 1", "AIF1_2 Capture",
2969 1, SND_SOC_NOPM, 0, 0),
2970 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 2", "AIF1_2 Capture",
2971 2, SND_SOC_NOPM, 0, 0),
2972 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 3", "AIF1_2 Capture",
2973 3, SND_SOC_NOPM, 0, 0),
2974 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 4", "AIF1_2 Capture",
2975 4, SND_SOC_NOPM, 0, 0),
2976 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 5", "AIF1_2 Capture",
2977 5, SND_SOC_NOPM, 0, 0),
2978 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 6", "AIF1_2 Capture",
2979 6, SND_SOC_NOPM, 0, 0),
2980 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 7", "AIF1_2 Capture",
2981 7, SND_SOC_NOPM, 0, 0),
2982 SND_SOC_DAPM_AIF_OUT("AIF2_1TX", "AIF2_1 Capture",
2983 0, SND_SOC_NOPM, 0, 0),
2984 SND_SOC_DAPM_AIF_OUT("AIF2_2TX", "AIF2_2 Capture",
2985 0, SND_SOC_NOPM, 0, 0),
2986 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture",
2987 0, SND_SOC_NOPM, 0, 0),
2988 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback",
2989 0, SND_SOC_NOPM, 0, 0),
2990 SND_SOC_DAPM_AIF_IN("AIF2_1RX", "AIF2_1 Playback",
2991 0, SND_SOC_NOPM, 0, 0),
2992 SND_SOC_DAPM_AIF_IN("AIF2_2RX", "AIF2_2 Playback",
2993 0, SND_SOC_NOPM, 0, 0),
2994 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback",
2995 0, SND_SOC_NOPM, 0, 0),
2996
2997 /* Output Side */
2998 /* DAC mixer before sound effect */
2999 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
3000 rt5665_dac_l_mix, ARRAY_SIZE(rt5665_dac_l_mix)),
3001 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
3002 rt5665_dac_r_mix, ARRAY_SIZE(rt5665_dac_r_mix)),
3003
3004 /* DAC channel Mux */
3005 SND_SOC_DAPM_MUX("DAC L1 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l1_mux),
3006 SND_SOC_DAPM_MUX("DAC R1 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r1_mux),
3007 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l2_mux),
3008 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r2_mux),
3009 SND_SOC_DAPM_MUX("DAC L3 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l3_mux),
3010 SND_SOC_DAPM_MUX("DAC R3 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r3_mux),
3011
3012 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0,
3013 &rt5665_alg_dac_l1_mux),
3014 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0,
3015 &rt5665_alg_dac_r1_mux),
3016 SND_SOC_DAPM_MUX("DAC L2 Source", SND_SOC_NOPM, 0, 0,
3017 &rt5665_alg_dac_l2_mux),
3018 SND_SOC_DAPM_MUX("DAC R2 Source", SND_SOC_NOPM, 0, 0,
3019 &rt5665_alg_dac_r2_mux),
3020
3021 /* DAC Mixer */
3022 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5665_PWR_DIG_2,
3023 RT5665_PWR_DAC_S1F_BIT, 0, NULL, 0),
3024 SND_SOC_DAPM_SUPPLY("DAC Stereo2 Filter", RT5665_PWR_DIG_2,
3025 RT5665_PWR_DAC_S2F_BIT, 0, NULL, 0),
3026 SND_SOC_DAPM_SUPPLY("DAC Mono Left Filter", RT5665_PWR_DIG_2,
3027 RT5665_PWR_DAC_MF_L_BIT, 0, NULL, 0),
3028 SND_SOC_DAPM_SUPPLY("DAC Mono Right Filter", RT5665_PWR_DIG_2,
3029 RT5665_PWR_DAC_MF_R_BIT, 0, NULL, 0),
3030 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,
3031 rt5665_sto1_dac_l_mix, ARRAY_SIZE(rt5665_sto1_dac_l_mix)),
3032 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,
3033 rt5665_sto1_dac_r_mix, ARRAY_SIZE(rt5665_sto1_dac_r_mix)),
3034 SND_SOC_DAPM_MIXER("Stereo2 DAC MIXL", SND_SOC_NOPM, 0, 0,
3035 rt5665_sto2_dac_l_mix, ARRAY_SIZE(rt5665_sto2_dac_l_mix)),
3036 SND_SOC_DAPM_MIXER("Stereo2 DAC MIXR", SND_SOC_NOPM, 0, 0,
3037 rt5665_sto2_dac_r_mix, ARRAY_SIZE(rt5665_sto2_dac_r_mix)),
3038 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
3039 rt5665_mono_dac_l_mix, ARRAY_SIZE(rt5665_mono_dac_l_mix)),
3040 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
3041 rt5665_mono_dac_r_mix, ARRAY_SIZE(rt5665_mono_dac_r_mix)),
3042 SND_SOC_DAPM_MUX("DAC MIXL", SND_SOC_NOPM, 0, 0,
3043 &rt5665_dig_dac_mixl_mux),
3044 SND_SOC_DAPM_MUX("DAC MIXR", SND_SOC_NOPM, 0, 0,
3045 &rt5665_dig_dac_mixr_mux),
3046
3047 /* DACs */
3048 SND_SOC_DAPM_DAC("DAC L1", NULL, SND_SOC_NOPM, 0, 0),
3049 SND_SOC_DAPM_DAC("DAC R1", NULL, SND_SOC_NOPM, 0, 0),
3050
3051 SND_SOC_DAPM_SUPPLY("DAC L2 Power", RT5665_PWR_DIG_1,
3052 RT5665_PWR_DAC_L2_BIT, 0, NULL, 0),
3053 SND_SOC_DAPM_SUPPLY("DAC R2 Power", RT5665_PWR_DIG_1,
3054 RT5665_PWR_DAC_R2_BIT, 0, NULL, 0),
3055 SND_SOC_DAPM_DAC("DAC L2", NULL, SND_SOC_NOPM, 0, 0),
3056 SND_SOC_DAPM_DAC("DAC R2", NULL, SND_SOC_NOPM, 0, 0),
3057 SND_SOC_DAPM_PGA("DAC1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3058
3059 SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 1, RT5665_CHOP_DAC,
3060 RT5665_CKGEN_DAC1_SFT, 0, NULL, 0),
3061 SND_SOC_DAPM_SUPPLY_S("DAC 2 Clock", 1, RT5665_CHOP_DAC,
3062 RT5665_CKGEN_DAC2_SFT, 0, NULL, 0),
3063
3064 /* OUT Mixer */
3065 SND_SOC_DAPM_MIXER("MONOVOL MIX", RT5665_PWR_MIXER, RT5665_PWR_MM_BIT,
3066 0, rt5665_monovol_mix, ARRAY_SIZE(rt5665_monovol_mix)),
3067 SND_SOC_DAPM_MIXER("OUT MIXL", RT5665_PWR_MIXER, RT5665_PWR_OM_L_BIT,
3068 0, rt5665_out_l_mix, ARRAY_SIZE(rt5665_out_l_mix)),
3069 SND_SOC_DAPM_MIXER("OUT MIXR", RT5665_PWR_MIXER, RT5665_PWR_OM_R_BIT,
3070 0, rt5665_out_r_mix, ARRAY_SIZE(rt5665_out_r_mix)),
3071
3072 /* Output Volume */
3073 SND_SOC_DAPM_SWITCH("MONOVOL", RT5665_PWR_VOL, RT5665_PWR_MV_BIT, 0,
3074 &monovol_switch),
3075 SND_SOC_DAPM_SWITCH("OUTVOL L", RT5665_PWR_VOL, RT5665_PWR_OV_L_BIT, 0,
3076 &outvol_l_switch),
3077 SND_SOC_DAPM_SWITCH("OUTVOL R", RT5665_PWR_VOL, RT5665_PWR_OV_R_BIT, 0,
3078 &outvol_r_switch),
3079
3080 /* MONO/HPO/LOUT */
3081 SND_SOC_DAPM_MIXER("Mono MIX", SND_SOC_NOPM, 0, 0, rt5665_mono_mix,
3082 ARRAY_SIZE(rt5665_mono_mix)),
3083 SND_SOC_DAPM_MIXER("LOUT L MIX", SND_SOC_NOPM, 0, 0, rt5665_lout_l_mix,
3084 ARRAY_SIZE(rt5665_lout_l_mix)),
3085 SND_SOC_DAPM_MIXER("LOUT R MIX", SND_SOC_NOPM, 0, 0, rt5665_lout_r_mix,
3086 ARRAY_SIZE(rt5665_lout_r_mix)),
3087 SND_SOC_DAPM_PGA_S("Mono Amp", 1, RT5665_PWR_ANLG_1, RT5665_PWR_MA_BIT,
3088 0, rt5665_mono_event, SND_SOC_DAPM_POST_PMD |
3089 SND_SOC_DAPM_PRE_PMU),
3090 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5665_hp_event,
3091 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
3092 SND_SOC_DAPM_PGA_S("LOUT Amp", 1, RT5665_PWR_ANLG_1,
3093 RT5665_PWR_LM_BIT, 0, rt5665_lout_event,
3094 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD |
3095 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
3096
3097 SND_SOC_DAPM_SUPPLY("Charge Pump", SND_SOC_NOPM, 0, 0,
3098 rt5665_charge_pump_event, SND_SOC_DAPM_PRE_PMU |
3099 SND_SOC_DAPM_POST_PMD),
3100
3101 SND_SOC_DAPM_SWITCH("Mono Playback", SND_SOC_NOPM, 0, 0,
3102 &mono_switch),
3103 SND_SOC_DAPM_SWITCH("HPO Playback", SND_SOC_NOPM, 0, 0,
3104 &hpo_switch),
3105 SND_SOC_DAPM_SWITCH("LOUT L Playback", SND_SOC_NOPM, 0, 0,
3106 &lout_l_switch),
3107 SND_SOC_DAPM_SWITCH("LOUT R Playback", SND_SOC_NOPM, 0, 0,
3108 &lout_r_switch),
3109 SND_SOC_DAPM_SWITCH("PDM L Playback", SND_SOC_NOPM, 0, 0,
3110 &pdm_l_switch),
3111 SND_SOC_DAPM_SWITCH("PDM R Playback", SND_SOC_NOPM, 0, 0,
3112 &pdm_r_switch),
3113
3114 /* PDM */
3115 SND_SOC_DAPM_SUPPLY("PDM Power", RT5665_PWR_DIG_2,
3116 RT5665_PWR_PDM1_BIT, 0, NULL, 0),
3117 SND_SOC_DAPM_MUX("PDM L Mux", SND_SOC_NOPM,
3118 0, 1, &rt5665_pdm_l_mux),
3119 SND_SOC_DAPM_MUX("PDM R Mux", SND_SOC_NOPM,
3120 0, 1, &rt5665_pdm_r_mux),
3121
3122 /* CLK DET */
3123 SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5665_CLK_DET, RT5665_SYS_CLK_DET,
3124 0, NULL, 0),
3125 SND_SOC_DAPM_SUPPLY("CLKDET HP", RT5665_CLK_DET, RT5665_HP_CLK_DET,
3126 0, NULL, 0),
3127 SND_SOC_DAPM_SUPPLY("CLKDET MONO", RT5665_CLK_DET, RT5665_MONO_CLK_DET,
3128 0, NULL, 0),
3129 SND_SOC_DAPM_SUPPLY("CLKDET LOUT", RT5665_CLK_DET, RT5665_LOUT_CLK_DET,
3130 0, NULL, 0),
3131 SND_SOC_DAPM_SUPPLY("CLKDET", RT5665_CLK_DET, RT5665_POW_CLK_DET,
3132 0, NULL, 0),
3133
3134 /* Output Lines */
3135 SND_SOC_DAPM_OUTPUT("HPOL"),
3136 SND_SOC_DAPM_OUTPUT("HPOR"),
3137 SND_SOC_DAPM_OUTPUT("LOUTL"),
3138 SND_SOC_DAPM_OUTPUT("LOUTR"),
3139 SND_SOC_DAPM_OUTPUT("MONOOUT"),
3140 SND_SOC_DAPM_OUTPUT("PDML"),
3141 SND_SOC_DAPM_OUTPUT("PDMR"),
3142 };
3143
3144 static const struct snd_soc_dapm_route rt5665_dapm_routes[] = {
3145 /*PLL*/
3146 {"ADC Stereo1 Filter", NULL, "PLL", is_sys_clk_from_pll},
3147 {"ADC Stereo2 Filter", NULL, "PLL", is_sys_clk_from_pll},
3148 {"ADC Mono Left Filter", NULL, "PLL", is_sys_clk_from_pll},
3149 {"ADC Mono Right Filter", NULL, "PLL", is_sys_clk_from_pll},
3150 {"DAC Stereo1 Filter", NULL, "PLL", is_sys_clk_from_pll},
3151 {"DAC Stereo2 Filter", NULL, "PLL", is_sys_clk_from_pll},
3152 {"DAC Mono Left Filter", NULL, "PLL", is_sys_clk_from_pll},
3153 {"DAC Mono Right Filter", NULL, "PLL", is_sys_clk_from_pll},
3154
3155 /*ASRC*/
3156 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
3157 {"ADC Stereo2 Filter", NULL, "ADC STO2 ASRC", is_using_asrc},
3158 {"ADC Mono Left Filter", NULL, "ADC Mono L ASRC", is_using_asrc},
3159 {"ADC Mono Right Filter", NULL, "ADC Mono R ASRC", is_using_asrc},
3160 {"DAC Mono Left Filter", NULL, "DAC Mono L ASRC", is_using_asrc},
3161 {"DAC Mono Right Filter", NULL, "DAC Mono R ASRC", is_using_asrc},
3162 {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
3163 {"DAC Stereo2 Filter", NULL, "DAC STO2 ASRC", is_using_asrc},
3164 {"I2S1 ASRC", NULL, "CLKDET"},
3165 {"I2S2 ASRC", NULL, "CLKDET"},
3166 {"I2S3 ASRC", NULL, "CLKDET"},
3167
3168 /*Vref*/
3169 {"Mic Det Power", NULL, "Vref2"},
3170 {"MICBIAS1", NULL, "Vref1"},
3171 {"MICBIAS1", NULL, "Vref2"},
3172 {"MICBIAS2", NULL, "Vref1"},
3173 {"MICBIAS2", NULL, "Vref2"},
3174 {"MICBIAS3", NULL, "Vref1"},
3175 {"MICBIAS3", NULL, "Vref2"},
3176
3177 {"Stereo1 DMIC L Mux", NULL, "DMIC STO1 ASRC"},
3178 {"Stereo1 DMIC R Mux", NULL, "DMIC STO1 ASRC"},
3179 {"Stereo2 DMIC L Mux", NULL, "DMIC STO2 ASRC"},
3180 {"Stereo2 DMIC R Mux", NULL, "DMIC STO2 ASRC"},
3181 {"Mono DMIC L Mux", NULL, "DMIC MONO L ASRC"},
3182 {"Mono DMIC R Mux", NULL, "DMIC MONO R ASRC"},
3183
3184 {"I2S1_1", NULL, "I2S1 ASRC"},
3185 {"I2S1_2", NULL, "I2S1 ASRC"},
3186 {"I2S2_1", NULL, "I2S2 ASRC"},
3187 {"I2S2_2", NULL, "I2S2 ASRC"},
3188 {"I2S3", NULL, "I2S3 ASRC"},
3189
3190 {"CLKDET SYS", NULL, "CLKDET"},
3191 {"CLKDET HP", NULL, "CLKDET"},
3192 {"CLKDET MONO", NULL, "CLKDET"},
3193 {"CLKDET LOUT", NULL, "CLKDET"},
3194
3195 {"IN1P", NULL, "LDO2"},
3196 {"IN2P", NULL, "LDO2"},
3197 {"IN3P", NULL, "LDO2"},
3198 {"IN4P", NULL, "LDO2"},
3199
3200 {"DMIC1", NULL, "DMIC L1"},
3201 {"DMIC1", NULL, "DMIC R1"},
3202 {"DMIC2", NULL, "DMIC L2"},
3203 {"DMIC2", NULL, "DMIC R2"},
3204
3205 {"BST1", NULL, "IN1P"},
3206 {"BST1", NULL, "IN1N"},
3207 {"BST1", NULL, "BST1 Power"},
3208 {"BST1", NULL, "BST1P Power"},
3209 {"BST2", NULL, "IN2P"},
3210 {"BST2", NULL, "IN2N"},
3211 {"BST2", NULL, "BST2 Power"},
3212 {"BST2", NULL, "BST2P Power"},
3213 {"BST3", NULL, "IN3P"},
3214 {"BST3", NULL, "IN3N"},
3215 {"BST3", NULL, "BST3 Power"},
3216 {"BST3", NULL, "BST3P Power"},
3217 {"BST4", NULL, "IN4P"},
3218 {"BST4", NULL, "IN4N"},
3219 {"BST4", NULL, "BST4 Power"},
3220 {"BST4", NULL, "BST4P Power"},
3221 {"BST1 CBJ", NULL, "IN1P"},
3222 {"BST1 CBJ", NULL, "IN1N"},
3223 {"BST1 CBJ", NULL, "CBJ Power"},
3224 {"CBJ Power", NULL, "Vref2"},
3225
3226 {"INL VOL", NULL, "IN3P"},
3227 {"INR VOL", NULL, "IN3N"},
3228
3229 {"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
3230 {"RECMIX1L", "INL Switch", "INL VOL"},
3231 {"RECMIX1L", "INR Switch", "INR VOL"},
3232 {"RECMIX1L", "BST4 Switch", "BST4"},
3233 {"RECMIX1L", "BST3 Switch", "BST3"},
3234 {"RECMIX1L", "BST2 Switch", "BST2"},
3235 {"RECMIX1L", "BST1 Switch", "BST1"},
3236 {"RECMIX1L", NULL, "RECMIX1L Power"},
3237
3238 {"RECMIX1R", "MONOVOL Switch", "MONOVOL"},
3239 {"RECMIX1R", "INR Switch", "INR VOL"},
3240 {"RECMIX1R", "BST4 Switch", "BST4"},
3241 {"RECMIX1R", "BST3 Switch", "BST3"},
3242 {"RECMIX1R", "BST2 Switch", "BST2"},
3243 {"RECMIX1R", "BST1 Switch", "BST1"},
3244 {"RECMIX1R", NULL, "RECMIX1R Power"},
3245
3246 {"RECMIX2L", "CBJ Switch", "BST1 CBJ"},
3247 {"RECMIX2L", "INL Switch", "INL VOL"},
3248 {"RECMIX2L", "INR Switch", "INR VOL"},
3249 {"RECMIX2L", "BST4 Switch", "BST4"},
3250 {"RECMIX2L", "BST3 Switch", "BST3"},
3251 {"RECMIX2L", "BST2 Switch", "BST2"},
3252 {"RECMIX2L", "BST1 Switch", "BST1"},
3253 {"RECMIX2L", NULL, "RECMIX2L Power"},
3254
3255 {"RECMIX2R", "MONOVOL Switch", "MONOVOL"},
3256 {"RECMIX2R", "INL Switch", "INL VOL"},
3257 {"RECMIX2R", "INR Switch", "INR VOL"},
3258 {"RECMIX2R", "BST4 Switch", "BST4"},
3259 {"RECMIX2R", "BST3 Switch", "BST3"},
3260 {"RECMIX2R", "BST2 Switch", "BST2"},
3261 {"RECMIX2R", "BST1 Switch", "BST1"},
3262 {"RECMIX2R", NULL, "RECMIX2R Power"},
3263
3264 {"ADC1 L", NULL, "RECMIX1L"},
3265 {"ADC1 L", NULL, "ADC1 L Power"},
3266 {"ADC1 L", NULL, "ADC1 clock"},
3267 {"ADC1 R", NULL, "RECMIX1R"},
3268 {"ADC1 R", NULL, "ADC1 R Power"},
3269 {"ADC1 R", NULL, "ADC1 clock"},
3270
3271 {"ADC2 L", NULL, "RECMIX2L"},
3272 {"ADC2 L", NULL, "ADC2 L Power"},
3273 {"ADC2 L", NULL, "ADC2 clock"},
3274 {"ADC2 R", NULL, "RECMIX2R"},
3275 {"ADC2 R", NULL, "ADC2 R Power"},
3276 {"ADC2 R", NULL, "ADC2 clock"},
3277
3278 {"DMIC L1", NULL, "DMIC CLK"},
3279 {"DMIC L1", NULL, "DMIC1 Power"},
3280 {"DMIC R1", NULL, "DMIC CLK"},
3281 {"DMIC R1", NULL, "DMIC1 Power"},
3282 {"DMIC L2", NULL, "DMIC CLK"},
3283 {"DMIC L2", NULL, "DMIC2 Power"},
3284 {"DMIC R2", NULL, "DMIC CLK"},
3285 {"DMIC R2", NULL, "DMIC2 Power"},
3286
3287 {"Stereo1 DMIC L Mux", "DMIC1", "DMIC L1"},
3288 {"Stereo1 DMIC L Mux", "DMIC2", "DMIC L2"},
3289
3290 {"Stereo1 DMIC R Mux", "DMIC1", "DMIC R1"},
3291 {"Stereo1 DMIC R Mux", "DMIC2", "DMIC R2"},
3292
3293 {"Mono DMIC L Mux", "DMIC1 L", "DMIC L1"},
3294 {"Mono DMIC L Mux", "DMIC2 L", "DMIC L2"},
3295
3296 {"Mono DMIC R Mux", "DMIC1 R", "DMIC R1"},
3297 {"Mono DMIC R Mux", "DMIC2 R", "DMIC R2"},
3298
3299 {"Stereo2 DMIC L Mux", "DMIC1", "DMIC L1"},
3300 {"Stereo2 DMIC L Mux", "DMIC2", "DMIC L2"},
3301
3302 {"Stereo2 DMIC R Mux", "DMIC1", "DMIC R1"},
3303 {"Stereo2 DMIC R Mux", "DMIC2", "DMIC R2"},
3304
3305 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
3306 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
3307 {"Stereo1 ADC L Mux", "ADC2 L", "ADC2 L"},
3308 {"Stereo1 ADC L Mux", "ADC2 R", "ADC2 R"},
3309 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
3310 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
3311 {"Stereo1 ADC R Mux", "ADC2 L", "ADC2 L"},
3312 {"Stereo1 ADC R Mux", "ADC2 R", "ADC2 R"},
3313
3314 {"Stereo1 DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"},
3315 {"Stereo1 DD L Mux", "MONO DAC", "Mono DAC MIXL"},
3316
3317 {"Stereo1 DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"},
3318 {"Stereo1 DD R Mux", "MONO DAC", "Mono DAC MIXR"},
3319
3320 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
3321 {"Stereo1 ADC L1 Mux", "DD Mux", "Stereo1 DD L Mux"},
3322 {"Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC L Mux"},
3323 {"Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL"},
3324
3325 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
3326 {"Stereo1 ADC R1 Mux", "DD Mux", "Stereo1 DD R Mux"},
3327 {"Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC R Mux"},
3328 {"Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR"},
3329
3330 {"Mono ADC L Mux", "ADC1 L", "ADC1 L"},
3331 {"Mono ADC L Mux", "ADC1 R", "ADC1 R"},
3332 {"Mono ADC L Mux", "ADC2 L", "ADC2 L"},
3333 {"Mono ADC L Mux", "ADC2 R", "ADC2 R"},
3334
3335 {"Mono ADC R Mux", "ADC1 L", "ADC1 L"},
3336 {"Mono ADC R Mux", "ADC1 R", "ADC1 R"},
3337 {"Mono ADC R Mux", "ADC2 L", "ADC2 L"},
3338 {"Mono ADC R Mux", "ADC2 R", "ADC2 R"},
3339
3340 {"Mono DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"},
3341 {"Mono DD L Mux", "MONO DAC", "Mono DAC MIXL"},
3342
3343 {"Mono DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"},
3344 {"Mono DD R Mux", "MONO DAC", "Mono DAC MIXR"},
3345
3346 {"Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux"},
3347 {"Mono ADC L2 Mux", "DAC MIXL", "DAC MIXL"},
3348 {"Mono ADC L1 Mux", "DD Mux", "Mono DD L Mux"},
3349 {"Mono ADC L1 Mux", "ADC", "Mono ADC L Mux"},
3350
3351 {"Mono ADC R1 Mux", "DD Mux", "Mono DD R Mux"},
3352 {"Mono ADC R1 Mux", "ADC", "Mono ADC R Mux"},
3353 {"Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux"},
3354 {"Mono ADC R2 Mux", "DAC MIXR", "DAC MIXR"},
3355
3356 {"Stereo2 ADC L Mux", "ADC1 L", "ADC1 L"},
3357 {"Stereo2 ADC L Mux", "ADC2 L", "ADC2 L"},
3358 {"Stereo2 ADC L Mux", "ADC1 R", "ADC1 R"},
3359 {"Stereo2 ADC R Mux", "ADC1 L", "ADC1 L"},
3360 {"Stereo2 ADC R Mux", "ADC2 L", "ADC2 L"},
3361 {"Stereo2 ADC R Mux", "ADC1 R", "ADC1 R"},
3362
3363 {"Stereo2 DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"},
3364 {"Stereo2 DD L Mux", "MONO DAC", "Mono DAC MIXL"},
3365
3366 {"Stereo2 DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"},
3367 {"Stereo2 DD R Mux", "MONO DAC", "Mono DAC MIXR"},
3368
3369 {"Stereo2 ADC L1 Mux", "ADC", "Stereo2 ADC L Mux"},
3370 {"Stereo2 ADC L1 Mux", "DD Mux", "Stereo2 DD L Mux"},
3371 {"Stereo2 ADC L2 Mux", "DMIC", "Stereo2 DMIC L Mux"},
3372 {"Stereo2 ADC L2 Mux", "DAC MIX", "DAC MIXL"},
3373
3374 {"Stereo2 ADC R1 Mux", "ADC", "Stereo2 ADC R Mux"},
3375 {"Stereo2 ADC R1 Mux", "DD Mux", "Stereo2 DD R Mux"},
3376 {"Stereo2 ADC R2 Mux", "DMIC", "Stereo2 DMIC R Mux"},
3377 {"Stereo2 ADC R2 Mux", "DAC MIX", "DAC MIXR"},
3378
3379 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
3380 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
3381 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
3382
3383 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
3384 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
3385 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
3386
3387 {"Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux"},
3388 {"Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux"},
3389 {"Mono ADC MIXL", NULL, "ADC Mono Left Filter"},
3390
3391 {"Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux"},
3392 {"Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux"},
3393 {"Mono ADC MIXR", NULL, "ADC Mono Right Filter"},
3394
3395 {"Stereo2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC L1 Mux"},
3396 {"Stereo2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC L2 Mux"},
3397 {"Stereo2 ADC MIXL", NULL, "ADC Stereo2 Filter"},
3398
3399 {"Stereo2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC R1 Mux"},
3400 {"Stereo2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC R2 Mux"},
3401 {"Stereo2 ADC MIXR", NULL, "ADC Stereo2 Filter"},
3402
3403 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
3404 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
3405 {"Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL"},
3406 {"Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR"},
3407 {"Mono ADC MIX", NULL, "Mono ADC MIXL"},
3408 {"Mono ADC MIX", NULL, "Mono ADC MIXR"},
3409
3410 {"IF1_1_ADC1 Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3411 {"IF1_1_ADC1 Mux", "IF2_1 DAC", "IF2_1 DAC"},
3412 {"IF1_1_ADC2 Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3413 {"IF1_1_ADC2 Mux", "IF2_2 DAC", "IF2_2 DAC"},
3414 {"IF1_1_ADC3 Mux", "MONO ADC", "Mono ADC MIX"},
3415 {"IF1_1_ADC3 Mux", "IF3 DAC", "IF3 DAC"},
3416 {"IF1_1_ADC4", NULL, "DAC1 MIX"},
3417
3418 {"IF1_2_ADC1 Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3419 {"IF1_2_ADC1 Mux", "IF1 DAC", "IF1 DAC1"},
3420 {"IF1_2_ADC2 Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3421 {"IF1_2_ADC2 Mux", "IF2_1 DAC", "IF2_1 DAC"},
3422 {"IF1_2_ADC3 Mux", "MONO ADC", "Mono ADC MIX"},
3423 {"IF1_2_ADC3 Mux", "IF2_2 DAC", "IF2_2 DAC"},
3424 {"IF1_2_ADC4 Mux", "DAC1", "DAC1 MIX"},
3425 {"IF1_2_ADC4 Mux", "IF3 DAC", "IF3 DAC"},
3426
3427 {"TDM1 slot 01 Data Mux", "1234", "IF1_1_ADC1 Mux"},
3428 {"TDM1 slot 01 Data Mux", "1243", "IF1_1_ADC1 Mux"},
3429 {"TDM1 slot 01 Data Mux", "1324", "IF1_1_ADC1 Mux"},
3430 {"TDM1 slot 01 Data Mux", "1342", "IF1_1_ADC1 Mux"},
3431 {"TDM1 slot 01 Data Mux", "1432", "IF1_1_ADC1 Mux"},
3432 {"TDM1 slot 01 Data Mux", "1423", "IF1_1_ADC1 Mux"},
3433 {"TDM1 slot 01 Data Mux", "2134", "IF1_1_ADC2 Mux"},
3434 {"TDM1 slot 01 Data Mux", "2143", "IF1_1_ADC2 Mux"},
3435 {"TDM1 slot 01 Data Mux", "2314", "IF1_1_ADC2 Mux"},
3436 {"TDM1 slot 01 Data Mux", "2341", "IF1_1_ADC2 Mux"},
3437 {"TDM1 slot 01 Data Mux", "2431", "IF1_1_ADC2 Mux"},
3438 {"TDM1 slot 01 Data Mux", "2413", "IF1_1_ADC2 Mux"},
3439 {"TDM1 slot 01 Data Mux", "3124", "IF1_1_ADC3 Mux"},
3440 {"TDM1 slot 01 Data Mux", "3142", "IF1_1_ADC3 Mux"},
3441 {"TDM1 slot 01 Data Mux", "3214", "IF1_1_ADC3 Mux"},
3442 {"TDM1 slot 01 Data Mux", "3241", "IF1_1_ADC3 Mux"},
3443 {"TDM1 slot 01 Data Mux", "3412", "IF1_1_ADC3 Mux"},
3444 {"TDM1 slot 01 Data Mux", "3421", "IF1_1_ADC3 Mux"},
3445 {"TDM1 slot 01 Data Mux", "4123", "IF1_1_ADC4"},
3446 {"TDM1 slot 01 Data Mux", "4132", "IF1_1_ADC4"},
3447 {"TDM1 slot 01 Data Mux", "4213", "IF1_1_ADC4"},
3448 {"TDM1 slot 01 Data Mux", "4231", "IF1_1_ADC4"},
3449 {"TDM1 slot 01 Data Mux", "4312", "IF1_1_ADC4"},
3450 {"TDM1 slot 01 Data Mux", "4321", "IF1_1_ADC4"},
3451 {"TDM1 slot 01 Data Mux", NULL, "I2S1_1"},
3452
3453 {"TDM1 slot 23 Data Mux", "1234", "IF1_1_ADC2 Mux"},
3454 {"TDM1 slot 23 Data Mux", "1243", "IF1_1_ADC2 Mux"},
3455 {"TDM1 slot 23 Data Mux", "1324", "IF1_1_ADC3 Mux"},
3456 {"TDM1 slot 23 Data Mux", "1342", "IF1_1_ADC3 Mux"},
3457 {"TDM1 slot 23 Data Mux", "1432", "IF1_1_ADC4"},
3458 {"TDM1 slot 23 Data Mux", "1423", "IF1_1_ADC4"},
3459 {"TDM1 slot 23 Data Mux", "2134", "IF1_1_ADC1 Mux"},
3460 {"TDM1 slot 23 Data Mux", "2143", "IF1_1_ADC1 Mux"},
3461 {"TDM1 slot 23 Data Mux", "2314", "IF1_1_ADC3 Mux"},
3462 {"TDM1 slot 23 Data Mux", "2341", "IF1_1_ADC3 Mux"},
3463 {"TDM1 slot 23 Data Mux", "2431", "IF1_1_ADC4"},
3464 {"TDM1 slot 23 Data Mux", "2413", "IF1_1_ADC4"},
3465 {"TDM1 slot 23 Data Mux", "3124", "IF1_1_ADC1 Mux"},
3466 {"TDM1 slot 23 Data Mux", "3142", "IF1_1_ADC1 Mux"},
3467 {"TDM1 slot 23 Data Mux", "3214", "IF1_1_ADC2 Mux"},
3468 {"TDM1 slot 23 Data Mux", "3241", "IF1_1_ADC2 Mux"},
3469 {"TDM1 slot 23 Data Mux", "3412", "IF1_1_ADC4"},
3470 {"TDM1 slot 23 Data Mux", "3421", "IF1_1_ADC4"},
3471 {"TDM1 slot 23 Data Mux", "4123", "IF1_1_ADC1 Mux"},
3472 {"TDM1 slot 23 Data Mux", "4132", "IF1_1_ADC1 Mux"},
3473 {"TDM1 slot 23 Data Mux", "4213", "IF1_1_ADC2 Mux"},
3474 {"TDM1 slot 23 Data Mux", "4231", "IF1_1_ADC2 Mux"},
3475 {"TDM1 slot 23 Data Mux", "4312", "IF1_1_ADC3 Mux"},
3476 {"TDM1 slot 23 Data Mux", "4321", "IF1_1_ADC3 Mux"},
3477 {"TDM1 slot 23 Data Mux", NULL, "I2S1_1"},
3478
3479 {"TDM1 slot 45 Data Mux", "1234", "IF1_1_ADC3 Mux"},
3480 {"TDM1 slot 45 Data Mux", "1243", "IF1_1_ADC4"},
3481 {"TDM1 slot 45 Data Mux", "1324", "IF1_1_ADC2 Mux"},
3482 {"TDM1 slot 45 Data Mux", "1342", "IF1_1_ADC4"},
3483 {"TDM1 slot 45 Data Mux", "1432", "IF1_1_ADC3 Mux"},
3484 {"TDM1 slot 45 Data Mux", "1423", "IF1_1_ADC2 Mux"},
3485 {"TDM1 slot 45 Data Mux", "2134", "IF1_1_ADC3 Mux"},
3486 {"TDM1 slot 45 Data Mux", "2143", "IF1_1_ADC4"},
3487 {"TDM1 slot 45 Data Mux", "2314", "IF1_1_ADC1 Mux"},
3488 {"TDM1 slot 45 Data Mux", "2341", "IF1_1_ADC4"},
3489 {"TDM1 slot 45 Data Mux", "2431", "IF1_1_ADC3 Mux"},
3490 {"TDM1 slot 45 Data Mux", "2413", "IF1_1_ADC1 Mux"},
3491 {"TDM1 slot 45 Data Mux", "3124", "IF1_1_ADC2 Mux"},
3492 {"TDM1 slot 45 Data Mux", "3142", "IF1_1_ADC4"},
3493 {"TDM1 slot 45 Data Mux", "3214", "IF1_1_ADC1 Mux"},
3494 {"TDM1 slot 45 Data Mux", "3241", "IF1_1_ADC4"},
3495 {"TDM1 slot 45 Data Mux", "3412", "IF1_1_ADC1 Mux"},
3496 {"TDM1 slot 45 Data Mux", "3421", "IF1_1_ADC2 Mux"},
3497 {"TDM1 slot 45 Data Mux", "4123", "IF1_1_ADC2 Mux"},
3498 {"TDM1 slot 45 Data Mux", "4132", "IF1_1_ADC3 Mux"},
3499 {"TDM1 slot 45 Data Mux", "4213", "IF1_1_ADC1 Mux"},
3500 {"TDM1 slot 45 Data Mux", "4231", "IF1_1_ADC3 Mux"},
3501 {"TDM1 slot 45 Data Mux", "4312", "IF1_1_ADC1 Mux"},
3502 {"TDM1 slot 45 Data Mux", "4321", "IF1_1_ADC2 Mux"},
3503 {"TDM1 slot 45 Data Mux", NULL, "I2S1_1"},
3504
3505 {"TDM1 slot 67 Data Mux", "1234", "IF1_1_ADC4"},
3506 {"TDM1 slot 67 Data Mux", "1243", "IF1_1_ADC3 Mux"},
3507 {"TDM1 slot 67 Data Mux", "1324", "IF1_1_ADC4"},
3508 {"TDM1 slot 67 Data Mux", "1342", "IF1_1_ADC2 Mux"},
3509 {"TDM1 slot 67 Data Mux", "1432", "IF1_1_ADC2 Mux"},
3510 {"TDM1 slot 67 Data Mux", "1423", "IF1_1_ADC3 Mux"},
3511 {"TDM1 slot 67 Data Mux", "2134", "IF1_1_ADC4"},
3512 {"TDM1 slot 67 Data Mux", "2143", "IF1_1_ADC3 Mux"},
3513 {"TDM1 slot 67 Data Mux", "2314", "IF1_1_ADC4"},
3514 {"TDM1 slot 67 Data Mux", "2341", "IF1_1_ADC1 Mux"},
3515 {"TDM1 slot 67 Data Mux", "2431", "IF1_1_ADC1 Mux"},
3516 {"TDM1 slot 67 Data Mux", "2413", "IF1_1_ADC3 Mux"},
3517 {"TDM1 slot 67 Data Mux", "3124", "IF1_1_ADC4"},
3518 {"TDM1 slot 67 Data Mux", "3142", "IF1_1_ADC2 Mux"},
3519 {"TDM1 slot 67 Data Mux", "3214", "IF1_1_ADC4"},
3520 {"TDM1 slot 67 Data Mux", "3241", "IF1_1_ADC1 Mux"},
3521 {"TDM1 slot 67 Data Mux", "3412", "IF1_1_ADC2 Mux"},
3522 {"TDM1 slot 67 Data Mux", "3421", "IF1_1_ADC1 Mux"},
3523 {"TDM1 slot 67 Data Mux", "4123", "IF1_1_ADC3 Mux"},
3524 {"TDM1 slot 67 Data Mux", "4132", "IF1_1_ADC2 Mux"},
3525 {"TDM1 slot 67 Data Mux", "4213", "IF1_1_ADC3 Mux"},
3526 {"TDM1 slot 67 Data Mux", "4231", "IF1_1_ADC1 Mux"},
3527 {"TDM1 slot 67 Data Mux", "4312", "IF1_1_ADC2 Mux"},
3528 {"TDM1 slot 67 Data Mux", "4321", "IF1_1_ADC1 Mux"},
3529 {"TDM1 slot 67 Data Mux", NULL, "I2S1_1"},
3530
3531
3532 {"TDM2 slot 01 Data Mux", "1234", "IF1_2_ADC1 Mux"},
3533 {"TDM2 slot 01 Data Mux", "1243", "IF1_2_ADC1 Mux"},
3534 {"TDM2 slot 01 Data Mux", "1324", "IF1_2_ADC1 Mux"},
3535 {"TDM2 slot 01 Data Mux", "1342", "IF1_2_ADC1 Mux"},
3536 {"TDM2 slot 01 Data Mux", "1432", "IF1_2_ADC1 Mux"},
3537 {"TDM2 slot 01 Data Mux", "1423", "IF1_2_ADC1 Mux"},
3538 {"TDM2 slot 01 Data Mux", "2134", "IF1_2_ADC2 Mux"},
3539 {"TDM2 slot 01 Data Mux", "2143", "IF1_2_ADC2 Mux"},
3540 {"TDM2 slot 01 Data Mux", "2314", "IF1_2_ADC2 Mux"},
3541 {"TDM2 slot 01 Data Mux", "2341", "IF1_2_ADC2 Mux"},
3542 {"TDM2 slot 01 Data Mux", "2431", "IF1_2_ADC2 Mux"},
3543 {"TDM2 slot 01 Data Mux", "2413", "IF1_2_ADC2 Mux"},
3544 {"TDM2 slot 01 Data Mux", "3124", "IF1_2_ADC3 Mux"},
3545 {"TDM2 slot 01 Data Mux", "3142", "IF1_2_ADC3 Mux"},
3546 {"TDM2 slot 01 Data Mux", "3214", "IF1_2_ADC3 Mux"},
3547 {"TDM2 slot 01 Data Mux", "3241", "IF1_2_ADC3 Mux"},
3548 {"TDM2 slot 01 Data Mux", "3412", "IF1_2_ADC3 Mux"},
3549 {"TDM2 slot 01 Data Mux", "3421", "IF1_2_ADC3 Mux"},
3550 {"TDM2 slot 01 Data Mux", "4123", "IF1_2_ADC4 Mux"},
3551 {"TDM2 slot 01 Data Mux", "4132", "IF1_2_ADC4 Mux"},
3552 {"TDM2 slot 01 Data Mux", "4213", "IF1_2_ADC4 Mux"},
3553 {"TDM2 slot 01 Data Mux", "4231", "IF1_2_ADC4 Mux"},
3554 {"TDM2 slot 01 Data Mux", "4312", "IF1_2_ADC4 Mux"},
3555 {"TDM2 slot 01 Data Mux", "4321", "IF1_2_ADC4 Mux"},
3556 {"TDM2 slot 01 Data Mux", NULL, "I2S1_2"},
3557
3558 {"TDM2 slot 23 Data Mux", "1234", "IF1_2_ADC2 Mux"},
3559 {"TDM2 slot 23 Data Mux", "1243", "IF1_2_ADC2 Mux"},
3560 {"TDM2 slot 23 Data Mux", "1324", "IF1_2_ADC3 Mux"},
3561 {"TDM2 slot 23 Data Mux", "1342", "IF1_2_ADC3 Mux"},
3562 {"TDM2 slot 23 Data Mux", "1432", "IF1_2_ADC4 Mux"},
3563 {"TDM2 slot 23 Data Mux", "1423", "IF1_2_ADC4 Mux"},
3564 {"TDM2 slot 23 Data Mux", "2134", "IF1_2_ADC1 Mux"},
3565 {"TDM2 slot 23 Data Mux", "2143", "IF1_2_ADC1 Mux"},
3566 {"TDM2 slot 23 Data Mux", "2314", "IF1_2_ADC3 Mux"},
3567 {"TDM2 slot 23 Data Mux", "2341", "IF1_2_ADC3 Mux"},
3568 {"TDM2 slot 23 Data Mux", "2431", "IF1_2_ADC4 Mux"},
3569 {"TDM2 slot 23 Data Mux", "2413", "IF1_2_ADC4 Mux"},
3570 {"TDM2 slot 23 Data Mux", "3124", "IF1_2_ADC1 Mux"},
3571 {"TDM2 slot 23 Data Mux", "3142", "IF1_2_ADC1 Mux"},
3572 {"TDM2 slot 23 Data Mux", "3214", "IF1_2_ADC2 Mux"},
3573 {"TDM2 slot 23 Data Mux", "3241", "IF1_2_ADC2 Mux"},
3574 {"TDM2 slot 23 Data Mux", "3412", "IF1_2_ADC4 Mux"},
3575 {"TDM2 slot 23 Data Mux", "3421", "IF1_2_ADC4 Mux"},
3576 {"TDM2 slot 23 Data Mux", "4123", "IF1_2_ADC1 Mux"},
3577 {"TDM2 slot 23 Data Mux", "4132", "IF1_2_ADC1 Mux"},
3578 {"TDM2 slot 23 Data Mux", "4213", "IF1_2_ADC2 Mux"},
3579 {"TDM2 slot 23 Data Mux", "4231", "IF1_2_ADC2 Mux"},
3580 {"TDM2 slot 23 Data Mux", "4312", "IF1_2_ADC3 Mux"},
3581 {"TDM2 slot 23 Data Mux", "4321", "IF1_2_ADC3 Mux"},
3582 {"TDM2 slot 23 Data Mux", NULL, "I2S1_2"},
3583
3584 {"TDM2 slot 45 Data Mux", "1234", "IF1_2_ADC3 Mux"},
3585 {"TDM2 slot 45 Data Mux", "1243", "IF1_2_ADC4 Mux"},
3586 {"TDM2 slot 45 Data Mux", "1324", "IF1_2_ADC2 Mux"},
3587 {"TDM2 slot 45 Data Mux", "1342", "IF1_2_ADC4 Mux"},
3588 {"TDM2 slot 45 Data Mux", "1432", "IF1_2_ADC3 Mux"},
3589 {"TDM2 slot 45 Data Mux", "1423", "IF1_2_ADC2 Mux"},
3590 {"TDM2 slot 45 Data Mux", "2134", "IF1_2_ADC3 Mux"},
3591 {"TDM2 slot 45 Data Mux", "2143", "IF1_2_ADC4 Mux"},
3592 {"TDM2 slot 45 Data Mux", "2314", "IF1_2_ADC1 Mux"},
3593 {"TDM2 slot 45 Data Mux", "2341", "IF1_2_ADC4 Mux"},
3594 {"TDM2 slot 45 Data Mux", "2431", "IF1_2_ADC3 Mux"},
3595 {"TDM2 slot 45 Data Mux", "2413", "IF1_2_ADC1 Mux"},
3596 {"TDM2 slot 45 Data Mux", "3124", "IF1_2_ADC2 Mux"},
3597 {"TDM2 slot 45 Data Mux", "3142", "IF1_2_ADC4 Mux"},
3598 {"TDM2 slot 45 Data Mux", "3214", "IF1_2_ADC1 Mux"},
3599 {"TDM2 slot 45 Data Mux", "3241", "IF1_2_ADC4 Mux"},
3600 {"TDM2 slot 45 Data Mux", "3412", "IF1_2_ADC1 Mux"},
3601 {"TDM2 slot 45 Data Mux", "3421", "IF1_2_ADC2 Mux"},
3602 {"TDM2 slot 45 Data Mux", "4123", "IF1_2_ADC2 Mux"},
3603 {"TDM2 slot 45 Data Mux", "4132", "IF1_2_ADC3 Mux"},
3604 {"TDM2 slot 45 Data Mux", "4213", "IF1_2_ADC1 Mux"},
3605 {"TDM2 slot 45 Data Mux", "4231", "IF1_2_ADC3 Mux"},
3606 {"TDM2 slot 45 Data Mux", "4312", "IF1_2_ADC1 Mux"},
3607 {"TDM2 slot 45 Data Mux", "4321", "IF1_2_ADC2 Mux"},
3608 {"TDM2 slot 45 Data Mux", NULL, "I2S1_2"},
3609
3610 {"TDM2 slot 67 Data Mux", "1234", "IF1_2_ADC4 Mux"},
3611 {"TDM2 slot 67 Data Mux", "1243", "IF1_2_ADC3 Mux"},
3612 {"TDM2 slot 67 Data Mux", "1324", "IF1_2_ADC4 Mux"},
3613 {"TDM2 slot 67 Data Mux", "1342", "IF1_2_ADC2 Mux"},
3614 {"TDM2 slot 67 Data Mux", "1432", "IF1_2_ADC2 Mux"},
3615 {"TDM2 slot 67 Data Mux", "1423", "IF1_2_ADC3 Mux"},
3616 {"TDM2 slot 67 Data Mux", "2134", "IF1_2_ADC4 Mux"},
3617 {"TDM2 slot 67 Data Mux", "2143", "IF1_2_ADC3 Mux"},
3618 {"TDM2 slot 67 Data Mux", "2314", "IF1_2_ADC4 Mux"},
3619 {"TDM2 slot 67 Data Mux", "2341", "IF1_2_ADC1 Mux"},
3620 {"TDM2 slot 67 Data Mux", "2431", "IF1_2_ADC1 Mux"},
3621 {"TDM2 slot 67 Data Mux", "2413", "IF1_2_ADC3 Mux"},
3622 {"TDM2 slot 67 Data Mux", "3124", "IF1_2_ADC4 Mux"},
3623 {"TDM2 slot 67 Data Mux", "3142", "IF1_2_ADC2 Mux"},
3624 {"TDM2 slot 67 Data Mux", "3214", "IF1_2_ADC4 Mux"},
3625 {"TDM2 slot 67 Data Mux", "3241", "IF1_2_ADC1 Mux"},
3626 {"TDM2 slot 67 Data Mux", "3412", "IF1_2_ADC2 Mux"},
3627 {"TDM2 slot 67 Data Mux", "3421", "IF1_2_ADC1 Mux"},
3628 {"TDM2 slot 67 Data Mux", "4123", "IF1_2_ADC3 Mux"},
3629 {"TDM2 slot 67 Data Mux", "4132", "IF1_2_ADC2 Mux"},
3630 {"TDM2 slot 67 Data Mux", "4213", "IF1_2_ADC3 Mux"},
3631 {"TDM2 slot 67 Data Mux", "4231", "IF1_2_ADC1 Mux"},
3632 {"TDM2 slot 67 Data Mux", "4312", "IF1_2_ADC2 Mux"},
3633 {"TDM2 slot 67 Data Mux", "4321", "IF1_2_ADC1 Mux"},
3634 {"TDM2 slot 67 Data Mux", NULL, "I2S1_2"},
3635
3636 {"IF1_1 0 ADC Swap Mux", "L/R", "TDM1 slot 01 Data Mux"},
3637 {"IF1_1 0 ADC Swap Mux", "L/L", "TDM1 slot 01 Data Mux"},
3638 {"IF1_1 1 ADC Swap Mux", "R/L", "TDM1 slot 01 Data Mux"},
3639 {"IF1_1 1 ADC Swap Mux", "R/R", "TDM1 slot 01 Data Mux"},
3640 {"IF1_1 2 ADC Swap Mux", "L/R", "TDM1 slot 23 Data Mux"},
3641 {"IF1_1 2 ADC Swap Mux", "R/L", "TDM1 slot 23 Data Mux"},
3642 {"IF1_1 3 ADC Swap Mux", "L/L", "TDM1 slot 23 Data Mux"},
3643 {"IF1_1 3 ADC Swap Mux", "R/R", "TDM1 slot 23 Data Mux"},
3644 {"IF1_1 4 ADC Swap Mux", "L/R", "TDM1 slot 45 Data Mux"},
3645 {"IF1_1 4 ADC Swap Mux", "R/L", "TDM1 slot 45 Data Mux"},
3646 {"IF1_1 5 ADC Swap Mux", "L/L", "TDM1 slot 45 Data Mux"},
3647 {"IF1_1 5 ADC Swap Mux", "R/R", "TDM1 slot 45 Data Mux"},
3648 {"IF1_1 6 ADC Swap Mux", "L/R", "TDM1 slot 67 Data Mux"},
3649 {"IF1_1 6 ADC Swap Mux", "R/L", "TDM1 slot 67 Data Mux"},
3650 {"IF1_1 7 ADC Swap Mux", "L/L", "TDM1 slot 67 Data Mux"},
3651 {"IF1_1 7 ADC Swap Mux", "R/R", "TDM1 slot 67 Data Mux"},
3652 {"IF1_2 0 ADC Swap Mux", "L/R", "TDM2 slot 01 Data Mux"},
3653 {"IF1_2 0 ADC Swap Mux", "R/L", "TDM2 slot 01 Data Mux"},
3654 {"IF1_2 1 ADC Swap Mux", "L/L", "TDM2 slot 01 Data Mux"},
3655 {"IF1_2 1 ADC Swap Mux", "R/R", "TDM2 slot 01 Data Mux"},
3656 {"IF1_2 2 ADC Swap Mux", "L/R", "TDM2 slot 23 Data Mux"},
3657 {"IF1_2 2 ADC Swap Mux", "R/L", "TDM2 slot 23 Data Mux"},
3658 {"IF1_2 3 ADC Swap Mux", "L/L", "TDM2 slot 23 Data Mux"},
3659 {"IF1_2 3 ADC Swap Mux", "R/R", "TDM2 slot 23 Data Mux"},
3660 {"IF1_2 4 ADC Swap Mux", "L/R", "TDM2 slot 45 Data Mux"},
3661 {"IF1_2 4 ADC Swap Mux", "R/L", "TDM2 slot 45 Data Mux"},
3662 {"IF1_2 5 ADC Swap Mux", "L/L", "TDM2 slot 45 Data Mux"},
3663 {"IF1_2 5 ADC Swap Mux", "R/R", "TDM2 slot 45 Data Mux"},
3664 {"IF1_2 6 ADC Swap Mux", "L/R", "TDM2 slot 67 Data Mux"},
3665 {"IF1_2 6 ADC Swap Mux", "R/L", "TDM2 slot 67 Data Mux"},
3666 {"IF1_2 7 ADC Swap Mux", "L/L", "TDM2 slot 67 Data Mux"},
3667 {"IF1_2 7 ADC Swap Mux", "R/R", "TDM2 slot 67 Data Mux"},
3668
3669 {"IF2_1 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3670 {"IF2_1 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3671 {"IF2_1 ADC Mux", "MONO ADC", "Mono ADC MIX"},
3672 {"IF2_1 ADC Mux", "IF1 DAC1", "IF1 DAC1"},
3673 {"IF2_1 ADC Mux", "IF1 DAC2", "IF1 DAC2"},
3674 {"IF2_1 ADC Mux", "IF2_2 DAC", "IF2_2 DAC"},
3675 {"IF2_1 ADC Mux", "IF3 DAC", "IF3 DAC"},
3676 {"IF2_1 ADC Mux", "DAC1 MIX", "DAC1 MIX"},
3677 {"IF2_1 ADC", NULL, "IF2_1 ADC Mux"},
3678 {"IF2_1 ADC", NULL, "I2S2_1"},
3679
3680 {"IF2_2 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3681 {"IF2_2 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3682 {"IF2_2 ADC Mux", "MONO ADC", "Mono ADC MIX"},
3683 {"IF2_2 ADC Mux", "IF1 DAC1", "IF1 DAC1"},
3684 {"IF2_2 ADC Mux", "IF1 DAC2", "IF1 DAC2"},
3685 {"IF2_2 ADC Mux", "IF2_1 DAC", "IF2_1 DAC"},
3686 {"IF2_2 ADC Mux", "IF3 DAC", "IF3 DAC"},
3687 {"IF2_2 ADC Mux", "DAC1 MIX", "DAC1 MIX"},
3688 {"IF2_2 ADC", NULL, "IF2_2 ADC Mux"},
3689 {"IF2_2 ADC", NULL, "I2S2_2"},
3690
3691 {"IF3 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3692 {"IF3 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3693 {"IF3 ADC Mux", "MONO ADC", "Mono ADC MIX"},
3694 {"IF3 ADC Mux", "IF1 DAC1", "IF1 DAC1"},
3695 {"IF3 ADC Mux", "IF1 DAC2", "IF1 DAC2"},
3696 {"IF3 ADC Mux", "IF2_1 DAC", "IF2_1 DAC"},
3697 {"IF3 ADC Mux", "IF2_2 DAC", "IF2_2 DAC"},
3698 {"IF3 ADC Mux", "DAC1 MIX", "DAC1 MIX"},
3699 {"IF3 ADC", NULL, "IF3 ADC Mux"},
3700 {"IF3 ADC", NULL, "I2S3"},
3701
3702 {"AIF1_1TX slot 0", NULL, "IF1_1 0 ADC Swap Mux"},
3703 {"AIF1_1TX slot 1", NULL, "IF1_1 1 ADC Swap Mux"},
3704 {"AIF1_1TX slot 2", NULL, "IF1_1 2 ADC Swap Mux"},
3705 {"AIF1_1TX slot 3", NULL, "IF1_1 3 ADC Swap Mux"},
3706 {"AIF1_1TX slot 4", NULL, "IF1_1 4 ADC Swap Mux"},
3707 {"AIF1_1TX slot 5", NULL, "IF1_1 5 ADC Swap Mux"},
3708 {"AIF1_1TX slot 6", NULL, "IF1_1 6 ADC Swap Mux"},
3709 {"AIF1_1TX slot 7", NULL, "IF1_1 7 ADC Swap Mux"},
3710 {"AIF1_2TX slot 0", NULL, "IF1_2 0 ADC Swap Mux"},
3711 {"AIF1_2TX slot 1", NULL, "IF1_2 1 ADC Swap Mux"},
3712 {"AIF1_2TX slot 2", NULL, "IF1_2 2 ADC Swap Mux"},
3713 {"AIF1_2TX slot 3", NULL, "IF1_2 3 ADC Swap Mux"},
3714 {"AIF1_2TX slot 4", NULL, "IF1_2 4 ADC Swap Mux"},
3715 {"AIF1_2TX slot 5", NULL, "IF1_2 5 ADC Swap Mux"},
3716 {"AIF1_2TX slot 6", NULL, "IF1_2 6 ADC Swap Mux"},
3717 {"AIF1_2TX slot 7", NULL, "IF1_2 7 ADC Swap Mux"},
3718 {"IF2_1 ADC Swap Mux", "L/R", "IF2_1 ADC"},
3719 {"IF2_1 ADC Swap Mux", "R/L", "IF2_1 ADC"},
3720 {"IF2_1 ADC Swap Mux", "L/L", "IF2_1 ADC"},
3721 {"IF2_1 ADC Swap Mux", "R/R", "IF2_1 ADC"},
3722 {"AIF2_1TX", NULL, "IF2_1 ADC Swap Mux"},
3723 {"IF2_2 ADC Swap Mux", "L/R", "IF2_2 ADC"},
3724 {"IF2_2 ADC Swap Mux", "R/L", "IF2_2 ADC"},
3725 {"IF2_2 ADC Swap Mux", "L/L", "IF2_2 ADC"},
3726 {"IF2_2 ADC Swap Mux", "R/R", "IF2_2 ADC"},
3727 {"AIF2_2TX", NULL, "IF2_2 ADC Swap Mux"},
3728 {"IF3 ADC Swap Mux", "L/R", "IF3 ADC"},
3729 {"IF3 ADC Swap Mux", "R/L", "IF3 ADC"},
3730 {"IF3 ADC Swap Mux", "L/L", "IF3 ADC"},
3731 {"IF3 ADC Swap Mux", "R/R", "IF3 ADC"},
3732 {"AIF3TX", NULL, "IF3 ADC Swap Mux"},
3733
3734 {"IF1 DAC1", NULL, "AIF1RX"},
3735 {"IF1 DAC2", NULL, "AIF1RX"},
3736 {"IF1 DAC3", NULL, "AIF1RX"},
3737 {"IF2_1 DAC Swap Mux", "L/R", "AIF2_1RX"},
3738 {"IF2_1 DAC Swap Mux", "R/L", "AIF2_1RX"},
3739 {"IF2_1 DAC Swap Mux", "L/L", "AIF2_1RX"},
3740 {"IF2_1 DAC Swap Mux", "R/R", "AIF2_1RX"},
3741 {"IF2_2 DAC Swap Mux", "L/R", "AIF2_2RX"},
3742 {"IF2_2 DAC Swap Mux", "R/L", "AIF2_2RX"},
3743 {"IF2_2 DAC Swap Mux", "L/L", "AIF2_2RX"},
3744 {"IF2_2 DAC Swap Mux", "R/R", "AIF2_2RX"},
3745 {"IF2_1 DAC", NULL, "IF2_1 DAC Swap Mux"},
3746 {"IF2_2 DAC", NULL, "IF2_2 DAC Swap Mux"},
3747 {"IF3 DAC Swap Mux", "L/R", "AIF3RX"},
3748 {"IF3 DAC Swap Mux", "R/L", "AIF3RX"},
3749 {"IF3 DAC Swap Mux", "L/L", "AIF3RX"},
3750 {"IF3 DAC Swap Mux", "R/R", "AIF3RX"},
3751 {"IF3 DAC", NULL, "IF3 DAC Swap Mux"},
3752
3753 {"IF1 DAC1", NULL, "I2S1_1"},
3754 {"IF1 DAC2", NULL, "I2S1_1"},
3755 {"IF1 DAC3", NULL, "I2S1_1"},
3756 {"IF2_1 DAC", NULL, "I2S2_1"},
3757 {"IF2_2 DAC", NULL, "I2S2_2"},
3758 {"IF3 DAC", NULL, "I2S3"},
3759
3760 {"IF1 DAC1 L", NULL, "IF1 DAC1"},
3761 {"IF1 DAC1 R", NULL, "IF1 DAC1"},
3762 {"IF1 DAC2 L", NULL, "IF1 DAC2"},
3763 {"IF1 DAC2 R", NULL, "IF1 DAC2"},
3764 {"IF1 DAC3 L", NULL, "IF1 DAC3"},
3765 {"IF1 DAC3 R", NULL, "IF1 DAC3"},
3766 {"IF2_1 DAC L", NULL, "IF2_1 DAC"},
3767 {"IF2_1 DAC R", NULL, "IF2_1 DAC"},
3768 {"IF2_2 DAC L", NULL, "IF2_2 DAC"},
3769 {"IF2_2 DAC R", NULL, "IF2_2 DAC"},
3770 {"IF3 DAC L", NULL, "IF3 DAC"},
3771 {"IF3 DAC R", NULL, "IF3 DAC"},
3772
3773 {"DAC L1 Mux", "IF1 DAC1", "IF1 DAC1 L"},
3774 {"DAC L1 Mux", "IF2_1 DAC", "IF2_1 DAC L"},
3775 {"DAC L1 Mux", "IF2_2 DAC", "IF2_2 DAC L"},
3776 {"DAC L1 Mux", "IF3 DAC", "IF3 DAC L"},
3777 {"DAC L1 Mux", NULL, "DAC Stereo1 Filter"},
3778
3779 {"DAC R1 Mux", "IF1 DAC1", "IF1 DAC1 R"},
3780 {"DAC R1 Mux", "IF2_1 DAC", "IF2_1 DAC R"},
3781 {"DAC R1 Mux", "IF2_2 DAC", "IF2_2 DAC R"},
3782 {"DAC R1 Mux", "IF3 DAC", "IF3 DAC R"},
3783 {"DAC R1 Mux", NULL, "DAC Stereo1 Filter"},
3784
3785 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
3786 {"DAC1 MIXL", "DAC1 Switch", "DAC L1 Mux"},
3787 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
3788 {"DAC1 MIXR", "DAC1 Switch", "DAC R1 Mux"},
3789
3790 {"DAC1 MIX", NULL, "DAC1 MIXL"},
3791 {"DAC1 MIX", NULL, "DAC1 MIXR"},
3792
3793 {"DAC L2 Mux", "IF1 DAC2", "IF1 DAC2 L"},
3794 {"DAC L2 Mux", "IF2_1 DAC", "IF2_1 DAC L"},
3795 {"DAC L2 Mux", "IF2_2 DAC", "IF2_2 DAC L"},
3796 {"DAC L2 Mux", "IF3 DAC", "IF3 DAC L"},
3797 {"DAC L2 Mux", "Mono ADC MIX", "Mono ADC MIXL"},
3798 {"DAC L2 Mux", NULL, "DAC Mono Left Filter"},
3799
3800 {"DAC R2 Mux", "IF1 DAC2", "IF1 DAC2 R"},
3801 {"DAC R2 Mux", "IF2_1 DAC", "IF2_1 DAC R"},
3802 {"DAC R2 Mux", "IF2_2 DAC", "IF2_2 DAC R"},
3803 {"DAC R2 Mux", "IF3 DAC", "IF3 DAC R"},
3804 {"DAC R2 Mux", "Mono ADC MIX", "Mono ADC MIXR"},
3805 {"DAC R2 Mux", NULL, "DAC Mono Right Filter"},
3806
3807 {"DAC L3 Mux", "IF1 DAC2", "IF1 DAC2 L"},
3808 {"DAC L3 Mux", "IF2_1 DAC", "IF2_1 DAC L"},
3809 {"DAC L3 Mux", "IF2_2 DAC", "IF2_2 DAC L"},
3810 {"DAC L3 Mux", "IF3 DAC", "IF3 DAC L"},
3811 {"DAC L3 Mux", "STO2 ADC MIX", "Stereo2 ADC MIXL"},
3812 {"DAC L3 Mux", NULL, "DAC Stereo2 Filter"},
3813
3814 {"DAC R3 Mux", "IF1 DAC2", "IF1 DAC2 R"},
3815 {"DAC R3 Mux", "IF2_1 DAC", "IF2_1 DAC R"},
3816 {"DAC R3 Mux", "IF2_2 DAC", "IF2_2 DAC R"},
3817 {"DAC R3 Mux", "IF3 DAC", "IF3 DAC R"},
3818 {"DAC R3 Mux", "STO2 ADC MIX", "Stereo2 ADC MIXR"},
3819 {"DAC R3 Mux", NULL, "DAC Stereo2 Filter"},
3820
3821 {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
3822 {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
3823 {"Stereo1 DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
3824 {"Stereo1 DAC MIXL", "DAC R2 Switch", "DAC R2 Mux"},
3825
3826 {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
3827 {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
3828 {"Stereo1 DAC MIXR", "DAC L2 Switch", "DAC L2 Mux"},
3829 {"Stereo1 DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
3830
3831 {"Stereo2 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
3832 {"Stereo2 DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
3833 {"Stereo2 DAC MIXL", "DAC L3 Switch", "DAC L3 Mux"},
3834
3835 {"Stereo2 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
3836 {"Stereo2 DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
3837 {"Stereo2 DAC MIXR", "DAC R3 Switch", "DAC R3 Mux"},
3838
3839 {"Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
3840 {"Mono DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
3841 {"Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
3842 {"Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Mux"},
3843 {"Mono DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
3844 {"Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
3845 {"Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Mux"},
3846 {"Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
3847
3848 {"DAC MIXL", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
3849 {"DAC MIXL", "Stereo2 DAC Mixer", "Stereo2 DAC MIXL"},
3850 {"DAC MIXL", "Mono DAC Mixer", "Mono DAC MIXL"},
3851 {"DAC MIXR", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
3852 {"DAC MIXR", "Stereo2 DAC Mixer", "Stereo2 DAC MIXR"},
3853 {"DAC MIXR", "Mono DAC Mixer", "Mono DAC MIXR"},
3854
3855 {"DAC L1 Source", "DAC1", "DAC1 MIXL"},
3856 {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
3857 {"DAC L1 Source", "DMIC1", "DMIC L1"},
3858 {"DAC R1 Source", "DAC1", "DAC1 MIXR"},
3859 {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
3860 {"DAC R1 Source", "DMIC1", "DMIC R1"},
3861
3862 {"DAC L2 Source", "DAC2", "DAC L2 Mux"},
3863 {"DAC L2 Source", "Mono DAC Mixer", "Mono DAC MIXL"},
3864 {"DAC L2 Source", NULL, "DAC L2 Power"},
3865 {"DAC R2 Source", "DAC2", "DAC R2 Mux"},
3866 {"DAC R2 Source", "Mono DAC Mixer", "Mono DAC MIXR"},
3867 {"DAC R2 Source", NULL, "DAC R2 Power"},
3868
3869 {"DAC L1", NULL, "DAC L1 Source"},
3870 {"DAC R1", NULL, "DAC R1 Source"},
3871 {"DAC L2", NULL, "DAC L2 Source"},
3872 {"DAC R2", NULL, "DAC R2 Source"},
3873
3874 {"DAC L1", NULL, "DAC 1 Clock"},
3875 {"DAC R1", NULL, "DAC 1 Clock"},
3876 {"DAC L2", NULL, "DAC 2 Clock"},
3877 {"DAC R2", NULL, "DAC 2 Clock"},
3878
3879 {"MONOVOL MIX", "DAC L2 Switch", "DAC L2"},
3880 {"MONOVOL MIX", "RECMIX2L Switch", "RECMIX2L"},
3881 {"MONOVOL MIX", "BST1 Switch", "BST1"},
3882 {"MONOVOL MIX", "BST2 Switch", "BST2"},
3883 {"MONOVOL MIX", "BST3 Switch", "BST3"},
3884
3885 {"OUT MIXL", "DAC L2 Switch", "DAC L2"},
3886 {"OUT MIXL", "INL Switch", "INL VOL"},
3887 {"OUT MIXL", "BST1 Switch", "BST1"},
3888 {"OUT MIXL", "BST2 Switch", "BST2"},
3889 {"OUT MIXL", "BST3 Switch", "BST3"},
3890 {"OUT MIXR", "DAC R2 Switch", "DAC R2"},
3891 {"OUT MIXR", "INR Switch", "INR VOL"},
3892 {"OUT MIXR", "BST2 Switch", "BST2"},
3893 {"OUT MIXR", "BST3 Switch", "BST3"},
3894 {"OUT MIXR", "BST4 Switch", "BST4"},
3895
3896 {"MONOVOL", "Switch", "MONOVOL MIX"},
3897 {"Mono MIX", "DAC L2 Switch", "DAC L2"},
3898 {"Mono MIX", "MONOVOL Switch", "MONOVOL"},
3899 {"Mono Amp", NULL, "Mono MIX"},
3900 {"Mono Amp", NULL, "Vref2"},
3901 {"Mono Amp", NULL, "Vref3"},
3902 {"Mono Amp", NULL, "CLKDET SYS"},
3903 {"Mono Amp", NULL, "CLKDET MONO"},
3904 {"Mono Playback", "Switch", "Mono Amp"},
3905 {"MONOOUT", NULL, "Mono Playback"},
3906
3907 {"HP Amp", NULL, "DAC L1"},
3908 {"HP Amp", NULL, "DAC R1"},
3909 {"HP Amp", NULL, "Charge Pump"},
3910 {"HP Amp", NULL, "CLKDET SYS"},
3911 {"HP Amp", NULL, "CLKDET HP"},
3912 {"HP Amp", NULL, "CBJ Power"},
3913 {"HP Amp", NULL, "Vref2"},
3914 {"HPO Playback", "Switch", "HP Amp"},
3915 {"HPOL", NULL, "HPO Playback"},
3916 {"HPOR", NULL, "HPO Playback"},
3917
3918 {"OUTVOL L", "Switch", "OUT MIXL"},
3919 {"OUTVOL R", "Switch", "OUT MIXR"},
3920 {"LOUT L MIX", "DAC L2 Switch", "DAC L2"},
3921 {"LOUT L MIX", "OUTVOL L Switch", "OUTVOL L"},
3922 {"LOUT R MIX", "DAC R2 Switch", "DAC R2"},
3923 {"LOUT R MIX", "OUTVOL R Switch", "OUTVOL R"},
3924 {"LOUT Amp", NULL, "LOUT L MIX"},
3925 {"LOUT Amp", NULL, "LOUT R MIX"},
3926 {"LOUT Amp", NULL, "Vref1"},
3927 {"LOUT Amp", NULL, "Vref2"},
3928 {"LOUT Amp", NULL, "CLKDET SYS"},
3929 {"LOUT Amp", NULL, "CLKDET LOUT"},
3930 {"LOUT L Playback", "Switch", "LOUT Amp"},
3931 {"LOUT R Playback", "Switch", "LOUT Amp"},
3932 {"LOUTL", NULL, "LOUT L Playback"},
3933 {"LOUTR", NULL, "LOUT R Playback"},
3934
3935 {"PDM L Mux", "Mono DAC", "Mono DAC MIXL"},
3936 {"PDM L Mux", "Stereo1 DAC", "Stereo1 DAC MIXL"},
3937 {"PDM L Mux", "Stereo2 DAC", "Stereo2 DAC MIXL"},
3938 {"PDM L Mux", NULL, "PDM Power"},
3939 {"PDM R Mux", "Mono DAC", "Mono DAC MIXR"},
3940 {"PDM R Mux", "Stereo1 DAC", "Stereo1 DAC MIXR"},
3941 {"PDM R Mux", "Stereo2 DAC", "Stereo2 DAC MIXR"},
3942 {"PDM R Mux", NULL, "PDM Power"},
3943 {"PDM L Playback", "Switch", "PDM L Mux"},
3944 {"PDM R Playback", "Switch", "PDM R Mux"},
3945 {"PDML", NULL, "PDM L Playback"},
3946 {"PDMR", NULL, "PDM R Playback"},
3947 };
3948
rt5665_set_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)3949 static int rt5665_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
3950 unsigned int rx_mask, int slots, int slot_width)
3951 {
3952 struct snd_soc_component *component = dai->component;
3953 unsigned int val = 0;
3954
3955 if (rx_mask || tx_mask)
3956 val |= RT5665_I2S1_MODE_TDM;
3957
3958 switch (slots) {
3959 case 4:
3960 val |= RT5665_TDM_IN_CH_4;
3961 val |= RT5665_TDM_OUT_CH_4;
3962 break;
3963 case 6:
3964 val |= RT5665_TDM_IN_CH_6;
3965 val |= RT5665_TDM_OUT_CH_6;
3966 break;
3967 case 8:
3968 val |= RT5665_TDM_IN_CH_8;
3969 val |= RT5665_TDM_OUT_CH_8;
3970 break;
3971 case 2:
3972 break;
3973 default:
3974 return -EINVAL;
3975 }
3976
3977 switch (slot_width) {
3978 case 20:
3979 val |= RT5665_TDM_IN_LEN_20;
3980 val |= RT5665_TDM_OUT_LEN_20;
3981 break;
3982 case 24:
3983 val |= RT5665_TDM_IN_LEN_24;
3984 val |= RT5665_TDM_OUT_LEN_24;
3985 break;
3986 case 32:
3987 val |= RT5665_TDM_IN_LEN_32;
3988 val |= RT5665_TDM_OUT_LEN_32;
3989 break;
3990 case 16:
3991 break;
3992 default:
3993 return -EINVAL;
3994 }
3995
3996 snd_soc_component_update_bits(component, RT5665_TDM_CTRL_1,
3997 RT5665_I2S1_MODE_MASK | RT5665_TDM_IN_CH_MASK |
3998 RT5665_TDM_OUT_CH_MASK | RT5665_TDM_IN_LEN_MASK |
3999 RT5665_TDM_OUT_LEN_MASK, val);
4000
4001 return 0;
4002 }
4003
4004
rt5665_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)4005 static int rt5665_hw_params(struct snd_pcm_substream *substream,
4006 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
4007 {
4008 struct snd_soc_component *component = dai->component;
4009 struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
4010 unsigned int val_len = 0, val_clk, reg_clk, mask_clk, val_bits = 0x0100;
4011 int pre_div, frame_size;
4012
4013 rt5665->lrck[dai->id] = params_rate(params);
4014 pre_div = rl6231_get_clk_info(rt5665->sysclk, rt5665->lrck[dai->id]);
4015 if (pre_div < 0) {
4016 dev_warn(component->dev, "Force using PLL");
4017 snd_soc_component_set_pll(component, 0, RT5665_PLL1_S_MCLK,
4018 rt5665->sysclk, rt5665->lrck[dai->id] * 512);
4019 snd_soc_component_set_sysclk(component, RT5665_SCLK_S_PLL1, 0,
4020 rt5665->lrck[dai->id] * 512, 0);
4021 pre_div = 1;
4022 }
4023 frame_size = snd_soc_params_to_frame_size(params);
4024 if (frame_size < 0) {
4025 dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);
4026 return -EINVAL;
4027 }
4028
4029 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
4030 rt5665->lrck[dai->id], pre_div, dai->id);
4031
4032 switch (params_width(params)) {
4033 case 16:
4034 val_bits = 0x0100;
4035 break;
4036 case 20:
4037 val_len |= RT5665_I2S_DL_20;
4038 val_bits = 0x1300;
4039 break;
4040 case 24:
4041 val_len |= RT5665_I2S_DL_24;
4042 val_bits = 0x2500;
4043 break;
4044 case 8:
4045 val_len |= RT5665_I2S_DL_8;
4046 break;
4047 default:
4048 return -EINVAL;
4049 }
4050
4051 switch (dai->id) {
4052 case RT5665_AIF1_1:
4053 case RT5665_AIF1_2:
4054 if (params_channels(params) > 2)
4055 rt5665_set_tdm_slot(dai, 0xf, 0xf,
4056 params_channels(params), params_width(params));
4057 reg_clk = RT5665_ADDA_CLK_1;
4058 mask_clk = RT5665_I2S_PD1_MASK;
4059 val_clk = pre_div << RT5665_I2S_PD1_SFT;
4060 snd_soc_component_update_bits(component, RT5665_I2S1_SDP,
4061 RT5665_I2S_DL_MASK, val_len);
4062 break;
4063 case RT5665_AIF2_1:
4064 case RT5665_AIF2_2:
4065 reg_clk = RT5665_ADDA_CLK_2;
4066 mask_clk = RT5665_I2S_PD2_MASK;
4067 val_clk = pre_div << RT5665_I2S_PD2_SFT;
4068 snd_soc_component_update_bits(component, RT5665_I2S2_SDP,
4069 RT5665_I2S_DL_MASK, val_len);
4070 break;
4071 case RT5665_AIF3:
4072 reg_clk = RT5665_ADDA_CLK_2;
4073 mask_clk = RT5665_I2S_PD3_MASK;
4074 val_clk = pre_div << RT5665_I2S_PD3_SFT;
4075 snd_soc_component_update_bits(component, RT5665_I2S3_SDP,
4076 RT5665_I2S_DL_MASK, val_len);
4077 break;
4078 default:
4079 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
4080 return -EINVAL;
4081 }
4082
4083 snd_soc_component_update_bits(component, reg_clk, mask_clk, val_clk);
4084 snd_soc_component_update_bits(component, RT5665_STO1_DAC_SIL_DET, 0x3700, val_bits);
4085
4086 switch (rt5665->lrck[dai->id]) {
4087 case 192000:
4088 snd_soc_component_update_bits(component, RT5665_ADDA_CLK_1,
4089 RT5665_DAC_OSR_MASK | RT5665_ADC_OSR_MASK,
4090 RT5665_DAC_OSR_32 | RT5665_ADC_OSR_32);
4091 break;
4092 case 96000:
4093 snd_soc_component_update_bits(component, RT5665_ADDA_CLK_1,
4094 RT5665_DAC_OSR_MASK | RT5665_ADC_OSR_MASK,
4095 RT5665_DAC_OSR_64 | RT5665_ADC_OSR_64);
4096 break;
4097 default:
4098 snd_soc_component_update_bits(component, RT5665_ADDA_CLK_1,
4099 RT5665_DAC_OSR_MASK | RT5665_ADC_OSR_MASK,
4100 RT5665_DAC_OSR_128 | RT5665_ADC_OSR_128);
4101 break;
4102 }
4103
4104 if (rt5665->master[RT5665_AIF2_1] || rt5665->master[RT5665_AIF2_2]) {
4105 snd_soc_component_update_bits(component, RT5665_I2S_M_CLK_CTRL_1,
4106 RT5665_I2S2_M_PD_MASK, pre_div << RT5665_I2S2_M_PD_SFT);
4107 }
4108 if (rt5665->master[RT5665_AIF3]) {
4109 snd_soc_component_update_bits(component, RT5665_I2S_M_CLK_CTRL_1,
4110 RT5665_I2S3_M_PD_MASK, pre_div << RT5665_I2S3_M_PD_SFT);
4111 }
4112
4113 return 0;
4114 }
4115
rt5665_set_dai_fmt(struct snd_soc_dai * dai,unsigned int fmt)4116 static int rt5665_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
4117 {
4118 struct snd_soc_component *component = dai->component;
4119 struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
4120 unsigned int reg_val = 0;
4121
4122 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
4123 case SND_SOC_DAIFMT_CBP_CFP:
4124 rt5665->master[dai->id] = 1;
4125 break;
4126 case SND_SOC_DAIFMT_CBC_CFC:
4127 reg_val |= RT5665_I2S_MS_S;
4128 rt5665->master[dai->id] = 0;
4129 break;
4130 default:
4131 return -EINVAL;
4132 }
4133
4134 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
4135 case SND_SOC_DAIFMT_NB_NF:
4136 break;
4137 case SND_SOC_DAIFMT_IB_NF:
4138 reg_val |= RT5665_I2S_BP_INV;
4139 break;
4140 default:
4141 return -EINVAL;
4142 }
4143
4144 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
4145 case SND_SOC_DAIFMT_I2S:
4146 break;
4147 case SND_SOC_DAIFMT_LEFT_J:
4148 reg_val |= RT5665_I2S_DF_LEFT;
4149 break;
4150 case SND_SOC_DAIFMT_DSP_A:
4151 reg_val |= RT5665_I2S_DF_PCM_A;
4152 break;
4153 case SND_SOC_DAIFMT_DSP_B:
4154 reg_val |= RT5665_I2S_DF_PCM_B;
4155 break;
4156 default:
4157 return -EINVAL;
4158 }
4159
4160 switch (dai->id) {
4161 case RT5665_AIF1_1:
4162 case RT5665_AIF1_2:
4163 snd_soc_component_update_bits(component, RT5665_I2S1_SDP,
4164 RT5665_I2S_MS_MASK | RT5665_I2S_BP_MASK |
4165 RT5665_I2S_DF_MASK, reg_val);
4166 break;
4167 case RT5665_AIF2_1:
4168 case RT5665_AIF2_2:
4169 snd_soc_component_update_bits(component, RT5665_I2S2_SDP,
4170 RT5665_I2S_MS_MASK | RT5665_I2S_BP_MASK |
4171 RT5665_I2S_DF_MASK, reg_val);
4172 break;
4173 case RT5665_AIF3:
4174 snd_soc_component_update_bits(component, RT5665_I2S3_SDP,
4175 RT5665_I2S_MS_MASK | RT5665_I2S_BP_MASK |
4176 RT5665_I2S_DF_MASK, reg_val);
4177 break;
4178 default:
4179 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
4180 return -EINVAL;
4181 }
4182 return 0;
4183 }
4184
rt5665_set_component_sysclk(struct snd_soc_component * component,int clk_id,int source,unsigned int freq,int dir)4185 static int rt5665_set_component_sysclk(struct snd_soc_component *component, int clk_id,
4186 int source, unsigned int freq, int dir)
4187 {
4188 struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
4189 unsigned int reg_val = 0, src = 0;
4190
4191 if (freq == rt5665->sysclk && clk_id == rt5665->sysclk_src)
4192 return 0;
4193
4194 switch (clk_id) {
4195 case RT5665_SCLK_S_MCLK:
4196 reg_val |= RT5665_SCLK_SRC_MCLK;
4197 src = RT5665_CLK_SRC_MCLK;
4198 break;
4199 case RT5665_SCLK_S_PLL1:
4200 reg_val |= RT5665_SCLK_SRC_PLL1;
4201 src = RT5665_CLK_SRC_PLL1;
4202 break;
4203 case RT5665_SCLK_S_RCCLK:
4204 reg_val |= RT5665_SCLK_SRC_RCCLK;
4205 src = RT5665_CLK_SRC_RCCLK;
4206 break;
4207 default:
4208 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
4209 return -EINVAL;
4210 }
4211 snd_soc_component_update_bits(component, RT5665_GLB_CLK,
4212 RT5665_SCLK_SRC_MASK, reg_val);
4213
4214 if (rt5665->master[RT5665_AIF2_1] || rt5665->master[RT5665_AIF2_2]) {
4215 snd_soc_component_update_bits(component, RT5665_I2S_M_CLK_CTRL_1,
4216 RT5665_I2S2_SRC_MASK, src << RT5665_I2S2_SRC_SFT);
4217 }
4218 if (rt5665->master[RT5665_AIF3]) {
4219 snd_soc_component_update_bits(component, RT5665_I2S_M_CLK_CTRL_1,
4220 RT5665_I2S3_SRC_MASK, src << RT5665_I2S3_SRC_SFT);
4221 }
4222
4223 rt5665->sysclk = freq;
4224 rt5665->sysclk_src = clk_id;
4225
4226 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
4227
4228 return 0;
4229 }
4230
rt5665_set_component_pll(struct snd_soc_component * component,int pll_id,int source,unsigned int freq_in,unsigned int freq_out)4231 static int rt5665_set_component_pll(struct snd_soc_component *component, int pll_id,
4232 int source, unsigned int freq_in,
4233 unsigned int freq_out)
4234 {
4235 struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
4236 struct rl6231_pll_code pll_code;
4237 int ret;
4238
4239 if (source == rt5665->pll_src && freq_in == rt5665->pll_in &&
4240 freq_out == rt5665->pll_out)
4241 return 0;
4242
4243 if (!freq_in || !freq_out) {
4244 dev_dbg(component->dev, "PLL disabled\n");
4245
4246 rt5665->pll_in = 0;
4247 rt5665->pll_out = 0;
4248 snd_soc_component_update_bits(component, RT5665_GLB_CLK,
4249 RT5665_SCLK_SRC_MASK, RT5665_SCLK_SRC_MCLK);
4250 return 0;
4251 }
4252
4253 switch (source) {
4254 case RT5665_PLL1_S_MCLK:
4255 snd_soc_component_update_bits(component, RT5665_GLB_CLK,
4256 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_MCLK);
4257 break;
4258 case RT5665_PLL1_S_BCLK1:
4259 snd_soc_component_update_bits(component, RT5665_GLB_CLK,
4260 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_BCLK1);
4261 break;
4262 case RT5665_PLL1_S_BCLK2:
4263 snd_soc_component_update_bits(component, RT5665_GLB_CLK,
4264 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_BCLK2);
4265 break;
4266 case RT5665_PLL1_S_BCLK3:
4267 snd_soc_component_update_bits(component, RT5665_GLB_CLK,
4268 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_BCLK3);
4269 break;
4270 default:
4271 dev_err(component->dev, "Unknown PLL Source %d\n", source);
4272 return -EINVAL;
4273 }
4274
4275 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
4276 if (ret < 0) {
4277 dev_err(component->dev, "Unsupported input clock %d\n", freq_in);
4278 return ret;
4279 }
4280
4281 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
4282 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
4283 pll_code.n_code, pll_code.k_code);
4284
4285 snd_soc_component_write(component, RT5665_PLL_CTRL_1,
4286 pll_code.n_code << RT5665_PLL_N_SFT | pll_code.k_code);
4287 snd_soc_component_write(component, RT5665_PLL_CTRL_2,
4288 ((pll_code.m_bp ? 0 : pll_code.m_code) << RT5665_PLL_M_SFT) |
4289 (pll_code.m_bp << RT5665_PLL_M_BP_SFT));
4290
4291 rt5665->pll_in = freq_in;
4292 rt5665->pll_out = freq_out;
4293 rt5665->pll_src = source;
4294
4295 return 0;
4296 }
4297
rt5665_set_bclk_ratio(struct snd_soc_dai * dai,unsigned int ratio)4298 static int rt5665_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
4299 {
4300 struct snd_soc_component *component = dai->component;
4301 struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
4302
4303 dev_dbg(component->dev, "%s ratio=%d\n", __func__, ratio);
4304
4305 rt5665->bclk[dai->id] = ratio;
4306
4307 if (ratio == 64) {
4308 switch (dai->id) {
4309 case RT5665_AIF2_1:
4310 case RT5665_AIF2_2:
4311 snd_soc_component_update_bits(component, RT5665_ADDA_CLK_2,
4312 RT5665_I2S_BCLK_MS2_MASK,
4313 RT5665_I2S_BCLK_MS2_64);
4314 break;
4315 case RT5665_AIF3:
4316 snd_soc_component_update_bits(component, RT5665_ADDA_CLK_2,
4317 RT5665_I2S_BCLK_MS3_MASK,
4318 RT5665_I2S_BCLK_MS3_64);
4319 break;
4320 }
4321 }
4322
4323 return 0;
4324 }
4325
rt5665_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)4326 static int rt5665_set_bias_level(struct snd_soc_component *component,
4327 enum snd_soc_bias_level level)
4328 {
4329 struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
4330
4331 switch (level) {
4332 case SND_SOC_BIAS_PREPARE:
4333 regmap_update_bits(rt5665->regmap, RT5665_DIG_MISC,
4334 RT5665_DIG_GATE_CTRL, RT5665_DIG_GATE_CTRL);
4335 break;
4336
4337 case SND_SOC_BIAS_STANDBY:
4338 regmap_update_bits(rt5665->regmap, RT5665_PWR_DIG_1,
4339 RT5665_PWR_LDO, RT5665_PWR_LDO);
4340 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1,
4341 RT5665_PWR_MB, RT5665_PWR_MB);
4342 regmap_update_bits(rt5665->regmap, RT5665_DIG_MISC,
4343 RT5665_DIG_GATE_CTRL, 0);
4344 break;
4345 case SND_SOC_BIAS_OFF:
4346 regmap_update_bits(rt5665->regmap, RT5665_PWR_DIG_1,
4347 RT5665_PWR_LDO, 0);
4348 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1,
4349 RT5665_PWR_MB, 0);
4350 break;
4351
4352 default:
4353 break;
4354 }
4355
4356 return 0;
4357 }
4358
rt5665_probe(struct snd_soc_component * component)4359 static int rt5665_probe(struct snd_soc_component *component)
4360 {
4361 struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
4362
4363 rt5665->component = component;
4364
4365 schedule_delayed_work(&rt5665->calibrate_work, msecs_to_jiffies(100));
4366
4367 return 0;
4368 }
4369
rt5665_remove(struct snd_soc_component * component)4370 static void rt5665_remove(struct snd_soc_component *component)
4371 {
4372 struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
4373
4374 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4375 }
4376
4377 #ifdef CONFIG_PM
rt5665_suspend(struct snd_soc_component * component)4378 static int rt5665_suspend(struct snd_soc_component *component)
4379 {
4380 struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
4381
4382 regcache_cache_only(rt5665->regmap, true);
4383 regcache_mark_dirty(rt5665->regmap);
4384 return 0;
4385 }
4386
rt5665_resume(struct snd_soc_component * component)4387 static int rt5665_resume(struct snd_soc_component *component)
4388 {
4389 struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
4390
4391 regcache_cache_only(rt5665->regmap, false);
4392 regcache_sync(rt5665->regmap);
4393
4394 return 0;
4395 }
4396 #else
4397 #define rt5665_suspend NULL
4398 #define rt5665_resume NULL
4399 #endif
4400
4401 #define RT5665_STEREO_RATES SNDRV_PCM_RATE_8000_192000
4402 #define RT5665_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
4403 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
4404
4405 static const struct snd_soc_dai_ops rt5665_aif_dai_ops = {
4406 .hw_params = rt5665_hw_params,
4407 .set_fmt = rt5665_set_dai_fmt,
4408 .set_tdm_slot = rt5665_set_tdm_slot,
4409 .set_bclk_ratio = rt5665_set_bclk_ratio,
4410 };
4411
4412 static struct snd_soc_dai_driver rt5665_dai[] = {
4413 {
4414 .name = "rt5665-aif1_1",
4415 .id = RT5665_AIF1_1,
4416 .playback = {
4417 .stream_name = "AIF1 Playback",
4418 .channels_min = 1,
4419 .channels_max = 8,
4420 .rates = RT5665_STEREO_RATES,
4421 .formats = RT5665_FORMATS,
4422 },
4423 .capture = {
4424 .stream_name = "AIF1_1 Capture",
4425 .channels_min = 1,
4426 .channels_max = 8,
4427 .rates = RT5665_STEREO_RATES,
4428 .formats = RT5665_FORMATS,
4429 },
4430 .ops = &rt5665_aif_dai_ops,
4431 },
4432 {
4433 .name = "rt5665-aif1_2",
4434 .id = RT5665_AIF1_2,
4435 .capture = {
4436 .stream_name = "AIF1_2 Capture",
4437 .channels_min = 1,
4438 .channels_max = 8,
4439 .rates = RT5665_STEREO_RATES,
4440 .formats = RT5665_FORMATS,
4441 },
4442 .ops = &rt5665_aif_dai_ops,
4443 },
4444 {
4445 .name = "rt5665-aif2_1",
4446 .id = RT5665_AIF2_1,
4447 .playback = {
4448 .stream_name = "AIF2_1 Playback",
4449 .channels_min = 1,
4450 .channels_max = 2,
4451 .rates = RT5665_STEREO_RATES,
4452 .formats = RT5665_FORMATS,
4453 },
4454 .capture = {
4455 .stream_name = "AIF2_1 Capture",
4456 .channels_min = 1,
4457 .channels_max = 2,
4458 .rates = RT5665_STEREO_RATES,
4459 .formats = RT5665_FORMATS,
4460 },
4461 .ops = &rt5665_aif_dai_ops,
4462 },
4463 {
4464 .name = "rt5665-aif2_2",
4465 .id = RT5665_AIF2_2,
4466 .playback = {
4467 .stream_name = "AIF2_2 Playback",
4468 .channels_min = 1,
4469 .channels_max = 2,
4470 .rates = RT5665_STEREO_RATES,
4471 .formats = RT5665_FORMATS,
4472 },
4473 .capture = {
4474 .stream_name = "AIF2_2 Capture",
4475 .channels_min = 1,
4476 .channels_max = 2,
4477 .rates = RT5665_STEREO_RATES,
4478 .formats = RT5665_FORMATS,
4479 },
4480 .ops = &rt5665_aif_dai_ops,
4481 },
4482 {
4483 .name = "rt5665-aif3",
4484 .id = RT5665_AIF3,
4485 .playback = {
4486 .stream_name = "AIF3 Playback",
4487 .channels_min = 1,
4488 .channels_max = 2,
4489 .rates = RT5665_STEREO_RATES,
4490 .formats = RT5665_FORMATS,
4491 },
4492 .capture = {
4493 .stream_name = "AIF3 Capture",
4494 .channels_min = 1,
4495 .channels_max = 2,
4496 .rates = RT5665_STEREO_RATES,
4497 .formats = RT5665_FORMATS,
4498 },
4499 .ops = &rt5665_aif_dai_ops,
4500 },
4501 };
4502
4503 static const struct snd_soc_component_driver soc_component_dev_rt5665 = {
4504 .probe = rt5665_probe,
4505 .remove = rt5665_remove,
4506 .suspend = rt5665_suspend,
4507 .resume = rt5665_resume,
4508 .set_bias_level = rt5665_set_bias_level,
4509 .controls = rt5665_snd_controls,
4510 .num_controls = ARRAY_SIZE(rt5665_snd_controls),
4511 .dapm_widgets = rt5665_dapm_widgets,
4512 .num_dapm_widgets = ARRAY_SIZE(rt5665_dapm_widgets),
4513 .dapm_routes = rt5665_dapm_routes,
4514 .num_dapm_routes = ARRAY_SIZE(rt5665_dapm_routes),
4515 .set_sysclk = rt5665_set_component_sysclk,
4516 .set_pll = rt5665_set_component_pll,
4517 .set_jack = rt5665_set_jack_detect,
4518 .use_pmdown_time = 1,
4519 .endianness = 1,
4520 };
4521
4522
4523 static const struct regmap_config rt5665_regmap = {
4524 .reg_bits = 16,
4525 .val_bits = 16,
4526 .max_register = 0x0400,
4527 .volatile_reg = rt5665_volatile_register,
4528 .readable_reg = rt5665_readable_register,
4529 .cache_type = REGCACHE_MAPLE,
4530 .reg_defaults = rt5665_reg,
4531 .num_reg_defaults = ARRAY_SIZE(rt5665_reg),
4532 .use_single_read = true,
4533 .use_single_write = true,
4534 };
4535
4536 static const struct i2c_device_id rt5665_i2c_id[] = {
4537 {"rt5665"},
4538 {}
4539 };
4540 MODULE_DEVICE_TABLE(i2c, rt5665_i2c_id);
4541
rt5665_parse_dt(struct rt5665_priv * rt5665,struct device * dev)4542 static int rt5665_parse_dt(struct rt5665_priv *rt5665, struct device *dev)
4543 {
4544 rt5665->pdata.in1_diff = of_property_read_bool(dev->of_node,
4545 "realtek,in1-differential");
4546 rt5665->pdata.in2_diff = of_property_read_bool(dev->of_node,
4547 "realtek,in2-differential");
4548 rt5665->pdata.in3_diff = of_property_read_bool(dev->of_node,
4549 "realtek,in3-differential");
4550 rt5665->pdata.in4_diff = of_property_read_bool(dev->of_node,
4551 "realtek,in4-differential");
4552
4553 of_property_read_u32(dev->of_node, "realtek,dmic1-data-pin",
4554 &rt5665->pdata.dmic1_data_pin);
4555 of_property_read_u32(dev->of_node, "realtek,dmic2-data-pin",
4556 &rt5665->pdata.dmic2_data_pin);
4557 of_property_read_u32(dev->of_node, "realtek,jd-src",
4558 &rt5665->pdata.jd_src);
4559
4560 return 0;
4561 }
4562
rt5665_calibrate(struct rt5665_priv * rt5665)4563 static void rt5665_calibrate(struct rt5665_priv *rt5665)
4564 {
4565 int value, count;
4566
4567 mutex_lock(&rt5665->calibrate_mutex);
4568
4569 regcache_cache_bypass(rt5665->regmap, true);
4570
4571 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4572 regmap_write(rt5665->regmap, RT5665_BIAS_CUR_CTRL_8, 0xa602);
4573 regmap_write(rt5665->regmap, RT5665_HP_CHARGE_PUMP_1, 0x0c26);
4574 regmap_write(rt5665->regmap, RT5665_MONOMIX_IN_GAIN, 0x021f);
4575 regmap_write(rt5665->regmap, RT5665_MONO_OUT, 0x480a);
4576 regmap_write(rt5665->regmap, RT5665_PWR_MIXER, 0x083f);
4577 regmap_write(rt5665->regmap, RT5665_PWR_DIG_1, 0x0180);
4578 regmap_write(rt5665->regmap, RT5665_EJD_CTRL_1, 0x4040);
4579 regmap_write(rt5665->regmap, RT5665_HP_LOGIC_CTRL_2, 0x0000);
4580 regmap_write(rt5665->regmap, RT5665_DIG_MISC, 0x0001);
4581 regmap_write(rt5665->regmap, RT5665_MICBIAS_2, 0x0380);
4582 regmap_write(rt5665->regmap, RT5665_GLB_CLK, 0x8000);
4583 regmap_write(rt5665->regmap, RT5665_ADDA_CLK_1, 0x1000);
4584 regmap_write(rt5665->regmap, RT5665_CHOP_DAC, 0x3030);
4585 regmap_write(rt5665->regmap, RT5665_CALIB_ADC_CTRL, 0x3c05);
4586 regmap_write(rt5665->regmap, RT5665_PWR_ANLG_1, 0xaa3e);
4587 usleep_range(15000, 20000);
4588 regmap_write(rt5665->regmap, RT5665_PWR_ANLG_1, 0xfe7e);
4589 regmap_write(rt5665->regmap, RT5665_HP_CALIB_CTRL_2, 0x0321);
4590
4591 regmap_write(rt5665->regmap, RT5665_HP_CALIB_CTRL_1, 0xfc00);
4592 count = 0;
4593 while (true) {
4594 regmap_read(rt5665->regmap, RT5665_HP_CALIB_STA_1, &value);
4595 if (value & 0x8000)
4596 usleep_range(10000, 10005);
4597 else
4598 break;
4599
4600 if (count > 60) {
4601 pr_err("HP Calibration Failure\n");
4602 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4603 regcache_cache_bypass(rt5665->regmap, false);
4604 goto out_unlock;
4605 }
4606
4607 count++;
4608 }
4609
4610 regmap_write(rt5665->regmap, RT5665_MONO_AMP_CALIB_CTRL_1, 0x9e24);
4611 count = 0;
4612 while (true) {
4613 regmap_read(rt5665->regmap, RT5665_MONO_AMP_CALIB_STA1, &value);
4614 if (value & 0x8000)
4615 usleep_range(10000, 10005);
4616 else
4617 break;
4618
4619 if (count > 60) {
4620 pr_err("MONO Calibration Failure\n");
4621 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4622 regcache_cache_bypass(rt5665->regmap, false);
4623 goto out_unlock;
4624 }
4625
4626 count++;
4627 }
4628
4629 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4630 regcache_cache_bypass(rt5665->regmap, false);
4631
4632 regcache_mark_dirty(rt5665->regmap);
4633 regcache_sync(rt5665->regmap);
4634
4635 regmap_write(rt5665->regmap, RT5665_BIAS_CUR_CTRL_8, 0xa602);
4636 regmap_write(rt5665->regmap, RT5665_ASRC_8, 0x0120);
4637
4638 out_unlock:
4639 rt5665->calibration_done = true;
4640 mutex_unlock(&rt5665->calibrate_mutex);
4641 }
4642
rt5665_calibrate_handler(struct work_struct * work)4643 static void rt5665_calibrate_handler(struct work_struct *work)
4644 {
4645 struct rt5665_priv *rt5665 = container_of(work, struct rt5665_priv,
4646 calibrate_work.work);
4647
4648 while (!snd_soc_card_is_instantiated(rt5665->component->card)) {
4649 pr_debug("%s\n", __func__);
4650 usleep_range(10000, 15000);
4651 }
4652
4653 rt5665_calibrate(rt5665);
4654 }
4655
rt5665_i2c_probe(struct i2c_client * i2c)4656 static int rt5665_i2c_probe(struct i2c_client *i2c)
4657 {
4658 struct rt5665_platform_data *pdata = dev_get_platdata(&i2c->dev);
4659 struct rt5665_priv *rt5665;
4660 int ret;
4661 unsigned int val;
4662
4663 rt5665 = devm_kzalloc(&i2c->dev, sizeof(struct rt5665_priv),
4664 GFP_KERNEL);
4665
4666 if (rt5665 == NULL)
4667 return -ENOMEM;
4668
4669 i2c_set_clientdata(i2c, rt5665);
4670
4671 if (pdata)
4672 rt5665->pdata = *pdata;
4673 else
4674 rt5665_parse_dt(rt5665, &i2c->dev);
4675
4676 ret = devm_regulator_bulk_get_enable(&i2c->dev, ARRAY_SIZE(rt5665_supply_names),
4677 rt5665_supply_names);
4678 if (ret != 0) {
4679 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
4680 return ret;
4681 }
4682
4683 rt5665->gpiod_ldo1_en = devm_gpiod_get_optional(&i2c->dev,
4684 "realtek,ldo1-en",
4685 GPIOD_OUT_HIGH);
4686 if (IS_ERR(rt5665->gpiod_ldo1_en)) {
4687 dev_err(&i2c->dev, "Failed gpio request ldo1_en\n");
4688 return PTR_ERR(rt5665->gpiod_ldo1_en);
4689 }
4690
4691 /* Sleep for 300 ms miniumum */
4692 usleep_range(300000, 350000);
4693
4694 rt5665->regmap = devm_regmap_init_i2c(i2c, &rt5665_regmap);
4695 if (IS_ERR(rt5665->regmap)) {
4696 ret = PTR_ERR(rt5665->regmap);
4697 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
4698 ret);
4699 return ret;
4700 }
4701
4702 regmap_read(rt5665->regmap, RT5665_DEVICE_ID, &val);
4703 if (val != DEVICE_ID) {
4704 dev_err(&i2c->dev,
4705 "Device with ID register %x is not rt5665\n", val);
4706 return -ENODEV;
4707 }
4708
4709 regmap_read(rt5665->regmap, RT5665_RESET, &val);
4710 switch (val) {
4711 case 0x0:
4712 rt5665->id = CODEC_5666;
4713 break;
4714 case 0x3:
4715 default:
4716 rt5665->id = CODEC_5665;
4717 break;
4718 }
4719
4720 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4721
4722 /* line in diff mode*/
4723 if (rt5665->pdata.in1_diff)
4724 regmap_update_bits(rt5665->regmap, RT5665_IN1_IN2,
4725 RT5665_IN1_DF_MASK, RT5665_IN1_DF_MASK);
4726 if (rt5665->pdata.in2_diff)
4727 regmap_update_bits(rt5665->regmap, RT5665_IN1_IN2,
4728 RT5665_IN2_DF_MASK, RT5665_IN2_DF_MASK);
4729 if (rt5665->pdata.in3_diff)
4730 regmap_update_bits(rt5665->regmap, RT5665_IN3_IN4,
4731 RT5665_IN3_DF_MASK, RT5665_IN3_DF_MASK);
4732 if (rt5665->pdata.in4_diff)
4733 regmap_update_bits(rt5665->regmap, RT5665_IN3_IN4,
4734 RT5665_IN4_DF_MASK, RT5665_IN4_DF_MASK);
4735
4736 /* DMIC pin*/
4737 if (rt5665->pdata.dmic1_data_pin != RT5665_DMIC1_NULL ||
4738 rt5665->pdata.dmic2_data_pin != RT5665_DMIC2_NULL) {
4739 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_2,
4740 RT5665_GP9_PIN_MASK, RT5665_GP9_PIN_DMIC1_SCL);
4741 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
4742 RT5665_GP8_PIN_MASK, RT5665_GP8_PIN_DMIC2_SCL);
4743 switch (rt5665->pdata.dmic1_data_pin) {
4744 case RT5665_DMIC1_DATA_IN2N:
4745 regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1,
4746 RT5665_DMIC_1_DP_MASK, RT5665_DMIC_1_DP_IN2N);
4747 break;
4748
4749 case RT5665_DMIC1_DATA_GPIO4:
4750 regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1,
4751 RT5665_DMIC_1_DP_MASK, RT5665_DMIC_1_DP_GPIO4);
4752 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
4753 RT5665_GP4_PIN_MASK, RT5665_GP4_PIN_DMIC1_SDA);
4754 break;
4755
4756 default:
4757 dev_dbg(&i2c->dev, "no DMIC1\n");
4758 break;
4759 }
4760
4761 switch (rt5665->pdata.dmic2_data_pin) {
4762 case RT5665_DMIC2_DATA_IN2P:
4763 regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1,
4764 RT5665_DMIC_2_DP_MASK, RT5665_DMIC_2_DP_IN2P);
4765 break;
4766
4767 case RT5665_DMIC2_DATA_GPIO5:
4768 regmap_update_bits(rt5665->regmap,
4769 RT5665_DMIC_CTRL_1,
4770 RT5665_DMIC_2_DP_MASK,
4771 RT5665_DMIC_2_DP_GPIO5);
4772 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
4773 RT5665_GP5_PIN_MASK, RT5665_GP5_PIN_DMIC2_SDA);
4774 break;
4775
4776 default:
4777 dev_dbg(&i2c->dev, "no DMIC2\n");
4778 break;
4779
4780 }
4781 }
4782
4783 regmap_write(rt5665->regmap, RT5665_HP_LOGIC_CTRL_2, 0x0002);
4784 regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1,
4785 0xf000 | RT5665_VREF_POW_MASK, 0xe000 | RT5665_VREF_POW_REG);
4786 /* Work around for pow_pump */
4787 regmap_update_bits(rt5665->regmap, RT5665_STO1_DAC_SIL_DET,
4788 RT5665_DEB_STO_DAC_MASK, RT5665_DEB_80_MS);
4789
4790 regmap_update_bits(rt5665->regmap, RT5665_HP_CHARGE_PUMP_1,
4791 RT5665_PM_HP_MASK, RT5665_PM_HP_HV);
4792
4793 /* Set GPIO4,8 as input for combo jack */
4794 if (rt5665->id == CODEC_5666) {
4795 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_2,
4796 RT5665_GP4_PF_MASK, RT5665_GP4_PF_IN);
4797 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_3,
4798 RT5665_GP8_PF_MASK, RT5665_GP8_PF_IN);
4799 }
4800
4801 /* Enhance performance*/
4802 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1,
4803 RT5665_HP_DRIVER_MASK | RT5665_LDO1_DVO_MASK,
4804 RT5665_HP_DRIVER_5X | RT5665_LDO1_DVO_12);
4805
4806 INIT_DELAYED_WORK(&rt5665->jack_detect_work,
4807 rt5665_jack_detect_handler);
4808 INIT_DELAYED_WORK(&rt5665->calibrate_work,
4809 rt5665_calibrate_handler);
4810 INIT_DELAYED_WORK(&rt5665->jd_check_work,
4811 rt5665_jd_check_handler);
4812
4813 mutex_init(&rt5665->calibrate_mutex);
4814
4815 if (i2c->irq) {
4816 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
4817 rt5665_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
4818 | IRQF_ONESHOT, "rt5665", rt5665);
4819 if (ret)
4820 dev_err(&i2c->dev, "Failed to request IRQ: %d\n", ret);
4821
4822 }
4823
4824 return devm_snd_soc_register_component(&i2c->dev,
4825 &soc_component_dev_rt5665,
4826 rt5665_dai, ARRAY_SIZE(rt5665_dai));
4827 }
4828
rt5665_i2c_shutdown(struct i2c_client * client)4829 static void rt5665_i2c_shutdown(struct i2c_client *client)
4830 {
4831 struct rt5665_priv *rt5665 = i2c_get_clientdata(client);
4832
4833 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4834 }
4835
4836 #ifdef CONFIG_OF
4837 static const struct of_device_id rt5665_of_match[] = {
4838 {.compatible = "realtek,rt5665"},
4839 {.compatible = "realtek,rt5666"},
4840 { }
4841 };
4842 MODULE_DEVICE_TABLE(of, rt5665_of_match);
4843 #endif
4844
4845 #ifdef CONFIG_ACPI
4846 static const struct acpi_device_id rt5665_acpi_match[] = {
4847 { "10EC5665" },
4848 { "10EC5666" },
4849 { }
4850 };
4851 MODULE_DEVICE_TABLE(acpi, rt5665_acpi_match);
4852 #endif
4853
4854 static struct i2c_driver rt5665_i2c_driver = {
4855 .driver = {
4856 .name = "rt5665",
4857 .of_match_table = of_match_ptr(rt5665_of_match),
4858 .acpi_match_table = ACPI_PTR(rt5665_acpi_match),
4859 },
4860 .probe = rt5665_i2c_probe,
4861 .shutdown = rt5665_i2c_shutdown,
4862 .id_table = rt5665_i2c_id,
4863 };
4864 module_i2c_driver(rt5665_i2c_driver);
4865
4866 MODULE_DESCRIPTION("ASoC RT5665 driver");
4867 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
4868 MODULE_LICENSE("GPL v2");
4869