1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * rt5665.c -- RT5665/RT5658 ALSA SoC audio codec driver
4 *
5 * Copyright 2016 Realtek Semiconductor Corp.
6 * Author: Bard Liao <bardliao@realtek.com>
7 */
8
9 #include <linux/module.h>
10 #include <linux/moduleparam.h>
11 #include <linux/init.h>
12 #include <linux/delay.h>
13 #include <linux/pm.h>
14 #include <linux/i2c.h>
15 #include <linux/platform_device.h>
16 #include <linux/spi/spi.h>
17 #include <linux/acpi.h>
18 #include <linux/gpio/consumer.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/mutex.h>
21 #include <sound/core.h>
22 #include <sound/pcm.h>
23 #include <sound/pcm_params.h>
24 #include <sound/jack.h>
25 #include <sound/soc.h>
26 #include <sound/soc-dapm.h>
27 #include <sound/initval.h>
28 #include <sound/tlv.h>
29 #include <sound/rt5665.h>
30
31 #include "rl6231.h"
32 #include "rt5665.h"
33
34 static const char * const rt5665_supply_names[] = {
35 "AVDD",
36 "MICVDD",
37 "VBAT",
38 };
39
40 struct rt5665_priv {
41 struct snd_soc_component *component;
42 struct rt5665_platform_data pdata;
43 struct regmap *regmap;
44 struct gpio_desc *gpiod_ldo1_en;
45 struct gpio_desc *gpiod_reset;
46 struct snd_soc_jack *hs_jack;
47 struct delayed_work jack_detect_work;
48 struct delayed_work calibrate_work;
49 struct delayed_work jd_check_work;
50 struct mutex calibrate_mutex;
51
52 int sysclk;
53 int sysclk_src;
54 int lrck[RT5665_AIFS];
55 int bclk[RT5665_AIFS];
56 int master[RT5665_AIFS];
57 int id;
58
59 int pll_src;
60 int pll_in;
61 int pll_out;
62
63 int jack_type;
64 int irq_work_delay_time;
65 unsigned int sar_adc_value;
66 bool calibration_done;
67 };
68
69 static const struct reg_default rt5665_reg[] = {
70 {0x0000, 0x0000},
71 {0x0001, 0xc8c8},
72 {0x0002, 0x8080},
73 {0x0003, 0x8000},
74 {0x0004, 0xc80a},
75 {0x0005, 0x0000},
76 {0x0006, 0x0000},
77 {0x0007, 0x0000},
78 {0x000a, 0x0000},
79 {0x000b, 0x0000},
80 {0x000c, 0x0000},
81 {0x000d, 0x0000},
82 {0x000f, 0x0808},
83 {0x0010, 0x4040},
84 {0x0011, 0x0000},
85 {0x0012, 0x1404},
86 {0x0013, 0x1000},
87 {0x0014, 0xa00a},
88 {0x0015, 0x0404},
89 {0x0016, 0x0404},
90 {0x0017, 0x0011},
91 {0x0018, 0xafaf},
92 {0x0019, 0xafaf},
93 {0x001a, 0xafaf},
94 {0x001b, 0x0011},
95 {0x001c, 0x2f2f},
96 {0x001d, 0x2f2f},
97 {0x001e, 0x2f2f},
98 {0x001f, 0x0000},
99 {0x0020, 0x0000},
100 {0x0021, 0x0000},
101 {0x0022, 0x5757},
102 {0x0023, 0x0039},
103 {0x0026, 0xc0c0},
104 {0x0027, 0xc0c0},
105 {0x0028, 0xc0c0},
106 {0x0029, 0x8080},
107 {0x002a, 0xaaaa},
108 {0x002b, 0xaaaa},
109 {0x002c, 0xaba8},
110 {0x002d, 0x0000},
111 {0x002e, 0x0000},
112 {0x002f, 0x0000},
113 {0x0030, 0x0000},
114 {0x0031, 0x5000},
115 {0x0032, 0x0000},
116 {0x0033, 0x0000},
117 {0x0034, 0x0000},
118 {0x0035, 0x0000},
119 {0x003a, 0x0000},
120 {0x003b, 0x0000},
121 {0x003c, 0x00ff},
122 {0x003d, 0x0000},
123 {0x003e, 0x00ff},
124 {0x003f, 0x0000},
125 {0x0040, 0x0000},
126 {0x0041, 0x00ff},
127 {0x0042, 0x0000},
128 {0x0043, 0x00ff},
129 {0x0044, 0x0c0c},
130 {0x0049, 0xc00b},
131 {0x004a, 0x0000},
132 {0x004b, 0x031f},
133 {0x004d, 0x0000},
134 {0x004e, 0x001f},
135 {0x004f, 0x0000},
136 {0x0050, 0x001f},
137 {0x0052, 0xf000},
138 {0x0061, 0x0000},
139 {0x0062, 0x0000},
140 {0x0063, 0x003e},
141 {0x0064, 0x0000},
142 {0x0065, 0x0000},
143 {0x0066, 0x003f},
144 {0x0067, 0x0000},
145 {0x006b, 0x0000},
146 {0x006d, 0xff00},
147 {0x006e, 0x2808},
148 {0x006f, 0x000a},
149 {0x0070, 0x8000},
150 {0x0071, 0x8000},
151 {0x0072, 0x8000},
152 {0x0073, 0x7000},
153 {0x0074, 0x7770},
154 {0x0075, 0x0002},
155 {0x0076, 0x0001},
156 {0x0078, 0x00f0},
157 {0x0079, 0x0000},
158 {0x007a, 0x0000},
159 {0x007b, 0x0000},
160 {0x007c, 0x0000},
161 {0x007d, 0x0123},
162 {0x007e, 0x4500},
163 {0x007f, 0x8003},
164 {0x0080, 0x0000},
165 {0x0081, 0x0000},
166 {0x0082, 0x0000},
167 {0x0083, 0x0000},
168 {0x0084, 0x0000},
169 {0x0085, 0x0000},
170 {0x0086, 0x0008},
171 {0x0087, 0x0000},
172 {0x0088, 0x0000},
173 {0x0089, 0x0000},
174 {0x008a, 0x0000},
175 {0x008b, 0x0000},
176 {0x008c, 0x0003},
177 {0x008e, 0x0060},
178 {0x008f, 0x1000},
179 {0x0091, 0x0c26},
180 {0x0092, 0x0073},
181 {0x0093, 0x0000},
182 {0x0094, 0x0080},
183 {0x0098, 0x0000},
184 {0x0099, 0x0000},
185 {0x009a, 0x0007},
186 {0x009f, 0x0000},
187 {0x00a0, 0x0000},
188 {0x00a1, 0x0002},
189 {0x00a2, 0x0001},
190 {0x00a3, 0x0002},
191 {0x00a4, 0x0001},
192 {0x00ae, 0x2040},
193 {0x00af, 0x0000},
194 {0x00b6, 0x0000},
195 {0x00b7, 0x0000},
196 {0x00b8, 0x0000},
197 {0x00b9, 0x0000},
198 {0x00ba, 0x0002},
199 {0x00bb, 0x0000},
200 {0x00be, 0x0000},
201 {0x00c0, 0x0000},
202 {0x00c1, 0x0aaa},
203 {0x00c2, 0xaa80},
204 {0x00c3, 0x0003},
205 {0x00c4, 0x0000},
206 {0x00d0, 0x0000},
207 {0x00d1, 0x2244},
208 {0x00d3, 0x3300},
209 {0x00d4, 0x2200},
210 {0x00d9, 0x0809},
211 {0x00da, 0x0000},
212 {0x00db, 0x0008},
213 {0x00dc, 0x00c0},
214 {0x00dd, 0x6724},
215 {0x00de, 0x3131},
216 {0x00df, 0x0008},
217 {0x00e0, 0x4000},
218 {0x00e1, 0x3131},
219 {0x00e2, 0x600c},
220 {0x00ea, 0xb320},
221 {0x00eb, 0x0000},
222 {0x00ec, 0xb300},
223 {0x00ed, 0x0000},
224 {0x00ee, 0xb320},
225 {0x00ef, 0x0000},
226 {0x00f0, 0x0201},
227 {0x00f1, 0x0ddd},
228 {0x00f2, 0x0ddd},
229 {0x00f6, 0x0000},
230 {0x00f7, 0x0000},
231 {0x00f8, 0x0000},
232 {0x00fa, 0x0000},
233 {0x00fb, 0x0000},
234 {0x00fc, 0x0000},
235 {0x00fd, 0x0000},
236 {0x00fe, 0x10ec},
237 {0x00ff, 0x6451},
238 {0x0100, 0xaaaa},
239 {0x0101, 0x000a},
240 {0x010a, 0xaaaa},
241 {0x010b, 0xa0a0},
242 {0x010c, 0xaeae},
243 {0x010d, 0xaaaa},
244 {0x010e, 0xaaaa},
245 {0x010f, 0xaaaa},
246 {0x0110, 0xe002},
247 {0x0111, 0xa402},
248 {0x0112, 0xaaaa},
249 {0x0113, 0x2000},
250 {0x0117, 0x0f00},
251 {0x0125, 0x0410},
252 {0x0132, 0x0000},
253 {0x0133, 0x0000},
254 {0x0137, 0x5540},
255 {0x0138, 0x3700},
256 {0x0139, 0x79a1},
257 {0x013a, 0x2020},
258 {0x013b, 0x2020},
259 {0x013c, 0x2005},
260 {0x013f, 0x0000},
261 {0x0145, 0x0002},
262 {0x0146, 0x0000},
263 {0x0147, 0x0000},
264 {0x0148, 0x0000},
265 {0x0150, 0x0000},
266 {0x0160, 0x4eff},
267 {0x0161, 0x0080},
268 {0x0162, 0x0200},
269 {0x0163, 0x0800},
270 {0x0164, 0x0000},
271 {0x0165, 0x0000},
272 {0x0166, 0x0000},
273 {0x0167, 0x000f},
274 {0x0170, 0x4e87},
275 {0x0171, 0x0080},
276 {0x0172, 0x0200},
277 {0x0173, 0x0800},
278 {0x0174, 0x00ff},
279 {0x0175, 0x0000},
280 {0x0190, 0x413d},
281 {0x0191, 0x4139},
282 {0x0192, 0x4135},
283 {0x0193, 0x413d},
284 {0x0194, 0x0000},
285 {0x0195, 0x0000},
286 {0x0196, 0x0000},
287 {0x0197, 0x0000},
288 {0x0198, 0x0000},
289 {0x0199, 0x0000},
290 {0x01a0, 0x1e64},
291 {0x01a1, 0x06a3},
292 {0x01a2, 0x0000},
293 {0x01a3, 0x0000},
294 {0x01a4, 0x0000},
295 {0x01a5, 0x0000},
296 {0x01a6, 0x0000},
297 {0x01a7, 0x8000},
298 {0x01a8, 0x0000},
299 {0x01a9, 0x0000},
300 {0x01aa, 0x0000},
301 {0x01ab, 0x0000},
302 {0x01b5, 0x0000},
303 {0x01b6, 0x01c3},
304 {0x01b7, 0x02a0},
305 {0x01b8, 0x03e9},
306 {0x01b9, 0x1389},
307 {0x01ba, 0xc351},
308 {0x01bb, 0x0009},
309 {0x01bc, 0x0018},
310 {0x01bd, 0x002a},
311 {0x01be, 0x004c},
312 {0x01bf, 0x0097},
313 {0x01c0, 0x433d},
314 {0x01c1, 0x0000},
315 {0x01c2, 0x0000},
316 {0x01c3, 0x0000},
317 {0x01c4, 0x0000},
318 {0x01c5, 0x0000},
319 {0x01c6, 0x0000},
320 {0x01c7, 0x0000},
321 {0x01c8, 0x40af},
322 {0x01c9, 0x0702},
323 {0x01ca, 0x0000},
324 {0x01cb, 0x0000},
325 {0x01cc, 0x5757},
326 {0x01cd, 0x5757},
327 {0x01ce, 0x5757},
328 {0x01cf, 0x5757},
329 {0x01d0, 0x5757},
330 {0x01d1, 0x5757},
331 {0x01d2, 0x5757},
332 {0x01d3, 0x5757},
333 {0x01d4, 0x5757},
334 {0x01d5, 0x5757},
335 {0x01d6, 0x003c},
336 {0x01da, 0x0000},
337 {0x01db, 0x0000},
338 {0x01dc, 0x0000},
339 {0x01de, 0x7c00},
340 {0x01df, 0x0320},
341 {0x01e0, 0x06a1},
342 {0x01e1, 0x0000},
343 {0x01e2, 0x0000},
344 {0x01e3, 0x0000},
345 {0x01e4, 0x0000},
346 {0x01e6, 0x0001},
347 {0x01e7, 0x0000},
348 {0x01e8, 0x0000},
349 {0x01ea, 0xbf3f},
350 {0x01eb, 0x0000},
351 {0x01ec, 0x0000},
352 {0x01ed, 0x0000},
353 {0x01ee, 0x0000},
354 {0x01ef, 0x0000},
355 {0x01f0, 0x0000},
356 {0x01f1, 0x0000},
357 {0x01f2, 0x0000},
358 {0x01f3, 0x0000},
359 {0x01f4, 0x0000},
360 {0x0200, 0x0000},
361 {0x0201, 0x0000},
362 {0x0202, 0x0000},
363 {0x0203, 0x0000},
364 {0x0204, 0x0000},
365 {0x0205, 0x0000},
366 {0x0206, 0x0000},
367 {0x0207, 0x0000},
368 {0x0208, 0x0000},
369 {0x0210, 0x60b1},
370 {0x0211, 0xa005},
371 {0x0212, 0x024c},
372 {0x0213, 0xf7ff},
373 {0x0214, 0x024c},
374 {0x0215, 0x0102},
375 {0x0216, 0x00a3},
376 {0x0217, 0x0048},
377 {0x0218, 0xa2c0},
378 {0x0219, 0x0400},
379 {0x021a, 0x00c8},
380 {0x021b, 0x00c0},
381 {0x02ff, 0x0110},
382 {0x0300, 0x001f},
383 {0x0301, 0x032c},
384 {0x0302, 0x5f21},
385 {0x0303, 0x4000},
386 {0x0304, 0x4000},
387 {0x0305, 0x06d5},
388 {0x0306, 0x8000},
389 {0x0307, 0x0700},
390 {0x0310, 0x4560},
391 {0x0311, 0xa4a8},
392 {0x0312, 0x7418},
393 {0x0313, 0x0000},
394 {0x0314, 0x0006},
395 {0x0315, 0xffff},
396 {0x0316, 0xc400},
397 {0x0317, 0x0000},
398 {0x0330, 0x00a6},
399 {0x0331, 0x04c3},
400 {0x0332, 0x27c8},
401 {0x0333, 0xbf50},
402 {0x0334, 0x0045},
403 {0x0335, 0x0007},
404 {0x0336, 0x7418},
405 {0x0337, 0x0501},
406 {0x0338, 0x0000},
407 {0x0339, 0x0010},
408 {0x033a, 0x1010},
409 {0x03c0, 0x7e00},
410 {0x03c1, 0x8000},
411 {0x03c2, 0x8000},
412 {0x03c3, 0x8000},
413 {0x03c4, 0x8000},
414 {0x03c5, 0x8000},
415 {0x03c6, 0x8000},
416 {0x03c7, 0x8000},
417 {0x03c8, 0x8000},
418 {0x03c9, 0x8000},
419 {0x03ca, 0x8000},
420 {0x03cb, 0x8000},
421 {0x03cc, 0x8000},
422 {0x03d0, 0x0000},
423 {0x03d1, 0x0000},
424 {0x03d2, 0x0000},
425 {0x03d3, 0x0000},
426 {0x03d4, 0x2000},
427 {0x03d5, 0x2000},
428 {0x03d6, 0x0000},
429 {0x03d7, 0x0000},
430 {0x03d8, 0x2000},
431 {0x03d9, 0x2000},
432 {0x03da, 0x2000},
433 {0x03db, 0x2000},
434 {0x03dc, 0x0000},
435 {0x03dd, 0x0000},
436 {0x03de, 0x0000},
437 {0x03df, 0x2000},
438 {0x03e0, 0x0000},
439 {0x03e1, 0x0000},
440 {0x03e2, 0x0000},
441 {0x03e3, 0x0000},
442 {0x03e4, 0x0000},
443 {0x03e5, 0x0000},
444 {0x03e6, 0x0000},
445 {0x03e7, 0x0000},
446 {0x03e8, 0x0000},
447 {0x03e9, 0x0000},
448 {0x03ea, 0x0000},
449 {0x03eb, 0x0000},
450 {0x03ec, 0x0000},
451 {0x03ed, 0x0000},
452 {0x03ee, 0x0000},
453 {0x03ef, 0x0000},
454 {0x03f0, 0x0800},
455 {0x03f1, 0x0800},
456 {0x03f2, 0x0800},
457 {0x03f3, 0x0800},
458 };
459
rt5665_volatile_register(struct device * dev,unsigned int reg)460 static bool rt5665_volatile_register(struct device *dev, unsigned int reg)
461 {
462 switch (reg) {
463 case RT5665_RESET:
464 case RT5665_EJD_CTRL_2:
465 case RT5665_GPIO_STA:
466 case RT5665_INT_ST_1:
467 case RT5665_IL_CMD_1:
468 case RT5665_4BTN_IL_CMD_1:
469 case RT5665_PSV_IL_CMD_1:
470 case RT5665_AJD1_CTRL:
471 case RT5665_JD_CTRL_3:
472 case RT5665_STO_NG2_CTRL_1:
473 case RT5665_SAR_IL_CMD_4:
474 case RT5665_DEVICE_ID:
475 case RT5665_STO1_DAC_SIL_DET ... RT5665_STO2_DAC_SIL_DET:
476 case RT5665_MONO_AMP_CALIB_STA1 ... RT5665_MONO_AMP_CALIB_STA6:
477 case RT5665_HP_IMP_SENS_CTRL_12 ... RT5665_HP_IMP_SENS_CTRL_15:
478 case RT5665_HP_CALIB_STA_1 ... RT5665_HP_CALIB_STA_11:
479 return true;
480 default:
481 return false;
482 }
483 }
484
rt5665_readable_register(struct device * dev,unsigned int reg)485 static bool rt5665_readable_register(struct device *dev, unsigned int reg)
486 {
487 switch (reg) {
488 case RT5665_RESET:
489 case RT5665_VENDOR_ID:
490 case RT5665_VENDOR_ID_1:
491 case RT5665_DEVICE_ID:
492 case RT5665_LOUT:
493 case RT5665_HP_CTRL_1:
494 case RT5665_HP_CTRL_2:
495 case RT5665_MONO_OUT:
496 case RT5665_HPL_GAIN:
497 case RT5665_HPR_GAIN:
498 case RT5665_MONO_GAIN:
499 case RT5665_CAL_BST_CTRL:
500 case RT5665_CBJ_BST_CTRL:
501 case RT5665_IN1_IN2:
502 case RT5665_IN3_IN4:
503 case RT5665_INL1_INR1_VOL:
504 case RT5665_EJD_CTRL_1:
505 case RT5665_EJD_CTRL_2:
506 case RT5665_EJD_CTRL_3:
507 case RT5665_EJD_CTRL_4:
508 case RT5665_EJD_CTRL_5:
509 case RT5665_EJD_CTRL_6:
510 case RT5665_EJD_CTRL_7:
511 case RT5665_DAC2_CTRL:
512 case RT5665_DAC2_DIG_VOL:
513 case RT5665_DAC1_DIG_VOL:
514 case RT5665_DAC3_DIG_VOL:
515 case RT5665_DAC3_CTRL:
516 case RT5665_STO1_ADC_DIG_VOL:
517 case RT5665_MONO_ADC_DIG_VOL:
518 case RT5665_STO2_ADC_DIG_VOL:
519 case RT5665_STO1_ADC_BOOST:
520 case RT5665_MONO_ADC_BOOST:
521 case RT5665_STO2_ADC_BOOST:
522 case RT5665_HP_IMP_GAIN_1:
523 case RT5665_HP_IMP_GAIN_2:
524 case RT5665_STO1_ADC_MIXER:
525 case RT5665_MONO_ADC_MIXER:
526 case RT5665_STO2_ADC_MIXER:
527 case RT5665_AD_DA_MIXER:
528 case RT5665_STO1_DAC_MIXER:
529 case RT5665_MONO_DAC_MIXER:
530 case RT5665_STO2_DAC_MIXER:
531 case RT5665_A_DAC1_MUX:
532 case RT5665_A_DAC2_MUX:
533 case RT5665_DIG_INF2_DATA:
534 case RT5665_DIG_INF3_DATA:
535 case RT5665_PDM_OUT_CTRL:
536 case RT5665_PDM_DATA_CTRL_1:
537 case RT5665_PDM_DATA_CTRL_2:
538 case RT5665_PDM_DATA_CTRL_3:
539 case RT5665_PDM_DATA_CTRL_4:
540 case RT5665_REC1_GAIN:
541 case RT5665_REC1_L1_MIXER:
542 case RT5665_REC1_L2_MIXER:
543 case RT5665_REC1_R1_MIXER:
544 case RT5665_REC1_R2_MIXER:
545 case RT5665_REC2_GAIN:
546 case RT5665_REC2_L1_MIXER:
547 case RT5665_REC2_L2_MIXER:
548 case RT5665_REC2_R1_MIXER:
549 case RT5665_REC2_R2_MIXER:
550 case RT5665_CAL_REC:
551 case RT5665_ALC_BACK_GAIN:
552 case RT5665_MONOMIX_GAIN:
553 case RT5665_MONOMIX_IN_GAIN:
554 case RT5665_OUT_L_GAIN:
555 case RT5665_OUT_L_MIXER:
556 case RT5665_OUT_R_GAIN:
557 case RT5665_OUT_R_MIXER:
558 case RT5665_LOUT_MIXER:
559 case RT5665_PWR_DIG_1:
560 case RT5665_PWR_DIG_2:
561 case RT5665_PWR_ANLG_1:
562 case RT5665_PWR_ANLG_2:
563 case RT5665_PWR_ANLG_3:
564 case RT5665_PWR_MIXER:
565 case RT5665_PWR_VOL:
566 case RT5665_CLK_DET:
567 case RT5665_HPF_CTRL1:
568 case RT5665_DMIC_CTRL_1:
569 case RT5665_DMIC_CTRL_2:
570 case RT5665_I2S1_SDP:
571 case RT5665_I2S2_SDP:
572 case RT5665_I2S3_SDP:
573 case RT5665_ADDA_CLK_1:
574 case RT5665_ADDA_CLK_2:
575 case RT5665_I2S1_F_DIV_CTRL_1:
576 case RT5665_I2S1_F_DIV_CTRL_2:
577 case RT5665_TDM_CTRL_1:
578 case RT5665_TDM_CTRL_2:
579 case RT5665_TDM_CTRL_3:
580 case RT5665_TDM_CTRL_4:
581 case RT5665_TDM_CTRL_5:
582 case RT5665_TDM_CTRL_6:
583 case RT5665_TDM_CTRL_7:
584 case RT5665_TDM_CTRL_8:
585 case RT5665_GLB_CLK:
586 case RT5665_PLL_CTRL_1:
587 case RT5665_PLL_CTRL_2:
588 case RT5665_ASRC_1:
589 case RT5665_ASRC_2:
590 case RT5665_ASRC_3:
591 case RT5665_ASRC_4:
592 case RT5665_ASRC_5:
593 case RT5665_ASRC_6:
594 case RT5665_ASRC_7:
595 case RT5665_ASRC_8:
596 case RT5665_ASRC_9:
597 case RT5665_ASRC_10:
598 case RT5665_DEPOP_1:
599 case RT5665_DEPOP_2:
600 case RT5665_HP_CHARGE_PUMP_1:
601 case RT5665_HP_CHARGE_PUMP_2:
602 case RT5665_MICBIAS_1:
603 case RT5665_MICBIAS_2:
604 case RT5665_ASRC_12:
605 case RT5665_ASRC_13:
606 case RT5665_ASRC_14:
607 case RT5665_RC_CLK_CTRL:
608 case RT5665_I2S_M_CLK_CTRL_1:
609 case RT5665_I2S2_F_DIV_CTRL_1:
610 case RT5665_I2S2_F_DIV_CTRL_2:
611 case RT5665_I2S3_F_DIV_CTRL_1:
612 case RT5665_I2S3_F_DIV_CTRL_2:
613 case RT5665_EQ_CTRL_1:
614 case RT5665_EQ_CTRL_2:
615 case RT5665_IRQ_CTRL_1:
616 case RT5665_IRQ_CTRL_2:
617 case RT5665_IRQ_CTRL_3:
618 case RT5665_IRQ_CTRL_4:
619 case RT5665_IRQ_CTRL_5:
620 case RT5665_IRQ_CTRL_6:
621 case RT5665_INT_ST_1:
622 case RT5665_GPIO_CTRL_1:
623 case RT5665_GPIO_CTRL_2:
624 case RT5665_GPIO_CTRL_3:
625 case RT5665_GPIO_CTRL_4:
626 case RT5665_GPIO_STA:
627 case RT5665_HP_AMP_DET_CTRL_1:
628 case RT5665_HP_AMP_DET_CTRL_2:
629 case RT5665_MID_HP_AMP_DET:
630 case RT5665_LOW_HP_AMP_DET:
631 case RT5665_SV_ZCD_1:
632 case RT5665_SV_ZCD_2:
633 case RT5665_IL_CMD_1:
634 case RT5665_IL_CMD_2:
635 case RT5665_IL_CMD_3:
636 case RT5665_IL_CMD_4:
637 case RT5665_4BTN_IL_CMD_1:
638 case RT5665_4BTN_IL_CMD_2:
639 case RT5665_4BTN_IL_CMD_3:
640 case RT5665_PSV_IL_CMD_1:
641 case RT5665_ADC_STO1_HP_CTRL_1:
642 case RT5665_ADC_STO1_HP_CTRL_2:
643 case RT5665_ADC_MONO_HP_CTRL_1:
644 case RT5665_ADC_MONO_HP_CTRL_2:
645 case RT5665_ADC_STO2_HP_CTRL_1:
646 case RT5665_ADC_STO2_HP_CTRL_2:
647 case RT5665_AJD1_CTRL:
648 case RT5665_JD1_THD:
649 case RT5665_JD2_THD:
650 case RT5665_JD_CTRL_1:
651 case RT5665_JD_CTRL_2:
652 case RT5665_JD_CTRL_3:
653 case RT5665_DIG_MISC:
654 case RT5665_DUMMY_2:
655 case RT5665_DUMMY_3:
656 case RT5665_DAC_ADC_DIG_VOL1:
657 case RT5665_DAC_ADC_DIG_VOL2:
658 case RT5665_BIAS_CUR_CTRL_1:
659 case RT5665_BIAS_CUR_CTRL_2:
660 case RT5665_BIAS_CUR_CTRL_3:
661 case RT5665_BIAS_CUR_CTRL_4:
662 case RT5665_BIAS_CUR_CTRL_5:
663 case RT5665_BIAS_CUR_CTRL_6:
664 case RT5665_BIAS_CUR_CTRL_7:
665 case RT5665_BIAS_CUR_CTRL_8:
666 case RT5665_BIAS_CUR_CTRL_9:
667 case RT5665_BIAS_CUR_CTRL_10:
668 case RT5665_VREF_REC_OP_FB_CAP_CTRL:
669 case RT5665_CHARGE_PUMP_1:
670 case RT5665_DIG_IN_CTRL_1:
671 case RT5665_DIG_IN_CTRL_2:
672 case RT5665_PAD_DRIVING_CTRL:
673 case RT5665_SOFT_RAMP_DEPOP:
674 case RT5665_PLL:
675 case RT5665_CHOP_DAC:
676 case RT5665_CHOP_ADC:
677 case RT5665_CALIB_ADC_CTRL:
678 case RT5665_VOL_TEST:
679 case RT5665_TEST_MODE_CTRL_1:
680 case RT5665_TEST_MODE_CTRL_2:
681 case RT5665_TEST_MODE_CTRL_3:
682 case RT5665_TEST_MODE_CTRL_4:
683 case RT5665_BASSBACK_CTRL:
684 case RT5665_STO_NG2_CTRL_1:
685 case RT5665_STO_NG2_CTRL_2:
686 case RT5665_STO_NG2_CTRL_3:
687 case RT5665_STO_NG2_CTRL_4:
688 case RT5665_STO_NG2_CTRL_5:
689 case RT5665_STO_NG2_CTRL_6:
690 case RT5665_STO_NG2_CTRL_7:
691 case RT5665_STO_NG2_CTRL_8:
692 case RT5665_MONO_NG2_CTRL_1:
693 case RT5665_MONO_NG2_CTRL_2:
694 case RT5665_MONO_NG2_CTRL_3:
695 case RT5665_MONO_NG2_CTRL_4:
696 case RT5665_MONO_NG2_CTRL_5:
697 case RT5665_MONO_NG2_CTRL_6:
698 case RT5665_STO1_DAC_SIL_DET:
699 case RT5665_MONOL_DAC_SIL_DET:
700 case RT5665_MONOR_DAC_SIL_DET:
701 case RT5665_STO2_DAC_SIL_DET:
702 case RT5665_SIL_PSV_CTRL1:
703 case RT5665_SIL_PSV_CTRL2:
704 case RT5665_SIL_PSV_CTRL3:
705 case RT5665_SIL_PSV_CTRL4:
706 case RT5665_SIL_PSV_CTRL5:
707 case RT5665_SIL_PSV_CTRL6:
708 case RT5665_MONO_AMP_CALIB_CTRL_1:
709 case RT5665_MONO_AMP_CALIB_CTRL_2:
710 case RT5665_MONO_AMP_CALIB_CTRL_3:
711 case RT5665_MONO_AMP_CALIB_CTRL_4:
712 case RT5665_MONO_AMP_CALIB_CTRL_5:
713 case RT5665_MONO_AMP_CALIB_CTRL_6:
714 case RT5665_MONO_AMP_CALIB_CTRL_7:
715 case RT5665_MONO_AMP_CALIB_STA1:
716 case RT5665_MONO_AMP_CALIB_STA2:
717 case RT5665_MONO_AMP_CALIB_STA3:
718 case RT5665_MONO_AMP_CALIB_STA4:
719 case RT5665_MONO_AMP_CALIB_STA6:
720 case RT5665_HP_IMP_SENS_CTRL_01:
721 case RT5665_HP_IMP_SENS_CTRL_02:
722 case RT5665_HP_IMP_SENS_CTRL_03:
723 case RT5665_HP_IMP_SENS_CTRL_04:
724 case RT5665_HP_IMP_SENS_CTRL_05:
725 case RT5665_HP_IMP_SENS_CTRL_06:
726 case RT5665_HP_IMP_SENS_CTRL_07:
727 case RT5665_HP_IMP_SENS_CTRL_08:
728 case RT5665_HP_IMP_SENS_CTRL_09:
729 case RT5665_HP_IMP_SENS_CTRL_10:
730 case RT5665_HP_IMP_SENS_CTRL_11:
731 case RT5665_HP_IMP_SENS_CTRL_12:
732 case RT5665_HP_IMP_SENS_CTRL_13:
733 case RT5665_HP_IMP_SENS_CTRL_14:
734 case RT5665_HP_IMP_SENS_CTRL_15:
735 case RT5665_HP_IMP_SENS_CTRL_16:
736 case RT5665_HP_IMP_SENS_CTRL_17:
737 case RT5665_HP_IMP_SENS_CTRL_18:
738 case RT5665_HP_IMP_SENS_CTRL_19:
739 case RT5665_HP_IMP_SENS_CTRL_20:
740 case RT5665_HP_IMP_SENS_CTRL_21:
741 case RT5665_HP_IMP_SENS_CTRL_22:
742 case RT5665_HP_IMP_SENS_CTRL_23:
743 case RT5665_HP_IMP_SENS_CTRL_24:
744 case RT5665_HP_IMP_SENS_CTRL_25:
745 case RT5665_HP_IMP_SENS_CTRL_26:
746 case RT5665_HP_IMP_SENS_CTRL_27:
747 case RT5665_HP_IMP_SENS_CTRL_28:
748 case RT5665_HP_IMP_SENS_CTRL_29:
749 case RT5665_HP_IMP_SENS_CTRL_30:
750 case RT5665_HP_IMP_SENS_CTRL_31:
751 case RT5665_HP_IMP_SENS_CTRL_32:
752 case RT5665_HP_IMP_SENS_CTRL_33:
753 case RT5665_HP_IMP_SENS_CTRL_34:
754 case RT5665_HP_LOGIC_CTRL_1:
755 case RT5665_HP_LOGIC_CTRL_2:
756 case RT5665_HP_LOGIC_CTRL_3:
757 case RT5665_HP_CALIB_CTRL_1:
758 case RT5665_HP_CALIB_CTRL_2:
759 case RT5665_HP_CALIB_CTRL_3:
760 case RT5665_HP_CALIB_CTRL_4:
761 case RT5665_HP_CALIB_CTRL_5:
762 case RT5665_HP_CALIB_CTRL_6:
763 case RT5665_HP_CALIB_CTRL_7:
764 case RT5665_HP_CALIB_CTRL_9:
765 case RT5665_HP_CALIB_CTRL_10:
766 case RT5665_HP_CALIB_CTRL_11:
767 case RT5665_HP_CALIB_STA_1:
768 case RT5665_HP_CALIB_STA_2:
769 case RT5665_HP_CALIB_STA_3:
770 case RT5665_HP_CALIB_STA_4:
771 case RT5665_HP_CALIB_STA_5:
772 case RT5665_HP_CALIB_STA_6:
773 case RT5665_HP_CALIB_STA_7:
774 case RT5665_HP_CALIB_STA_8:
775 case RT5665_HP_CALIB_STA_9:
776 case RT5665_HP_CALIB_STA_10:
777 case RT5665_HP_CALIB_STA_11:
778 case RT5665_PGM_TAB_CTRL1:
779 case RT5665_PGM_TAB_CTRL2:
780 case RT5665_PGM_TAB_CTRL3:
781 case RT5665_PGM_TAB_CTRL4:
782 case RT5665_PGM_TAB_CTRL5:
783 case RT5665_PGM_TAB_CTRL6:
784 case RT5665_PGM_TAB_CTRL7:
785 case RT5665_PGM_TAB_CTRL8:
786 case RT5665_PGM_TAB_CTRL9:
787 case RT5665_SAR_IL_CMD_1:
788 case RT5665_SAR_IL_CMD_2:
789 case RT5665_SAR_IL_CMD_3:
790 case RT5665_SAR_IL_CMD_4:
791 case RT5665_SAR_IL_CMD_5:
792 case RT5665_SAR_IL_CMD_6:
793 case RT5665_SAR_IL_CMD_7:
794 case RT5665_SAR_IL_CMD_8:
795 case RT5665_SAR_IL_CMD_9:
796 case RT5665_SAR_IL_CMD_10:
797 case RT5665_SAR_IL_CMD_11:
798 case RT5665_SAR_IL_CMD_12:
799 case RT5665_DRC1_CTRL_0:
800 case RT5665_DRC1_CTRL_1:
801 case RT5665_DRC1_CTRL_2:
802 case RT5665_DRC1_CTRL_3:
803 case RT5665_DRC1_CTRL_4:
804 case RT5665_DRC1_CTRL_5:
805 case RT5665_DRC1_CTRL_6:
806 case RT5665_DRC1_HARD_LMT_CTRL_1:
807 case RT5665_DRC1_HARD_LMT_CTRL_2:
808 case RT5665_DRC1_PRIV_1:
809 case RT5665_DRC1_PRIV_2:
810 case RT5665_DRC1_PRIV_3:
811 case RT5665_DRC1_PRIV_4:
812 case RT5665_DRC1_PRIV_5:
813 case RT5665_DRC1_PRIV_6:
814 case RT5665_DRC1_PRIV_7:
815 case RT5665_DRC1_PRIV_8:
816 case RT5665_ALC_PGA_CTRL_1:
817 case RT5665_ALC_PGA_CTRL_2:
818 case RT5665_ALC_PGA_CTRL_3:
819 case RT5665_ALC_PGA_CTRL_4:
820 case RT5665_ALC_PGA_CTRL_5:
821 case RT5665_ALC_PGA_CTRL_6:
822 case RT5665_ALC_PGA_CTRL_7:
823 case RT5665_ALC_PGA_CTRL_8:
824 case RT5665_ALC_PGA_STA_1:
825 case RT5665_ALC_PGA_STA_2:
826 case RT5665_ALC_PGA_STA_3:
827 case RT5665_EQ_AUTO_RCV_CTRL1:
828 case RT5665_EQ_AUTO_RCV_CTRL2:
829 case RT5665_EQ_AUTO_RCV_CTRL3:
830 case RT5665_EQ_AUTO_RCV_CTRL4:
831 case RT5665_EQ_AUTO_RCV_CTRL5:
832 case RT5665_EQ_AUTO_RCV_CTRL6:
833 case RT5665_EQ_AUTO_RCV_CTRL7:
834 case RT5665_EQ_AUTO_RCV_CTRL8:
835 case RT5665_EQ_AUTO_RCV_CTRL9:
836 case RT5665_EQ_AUTO_RCV_CTRL10:
837 case RT5665_EQ_AUTO_RCV_CTRL11:
838 case RT5665_EQ_AUTO_RCV_CTRL12:
839 case RT5665_EQ_AUTO_RCV_CTRL13:
840 case RT5665_ADC_L_EQ_LPF1_A1:
841 case RT5665_R_EQ_LPF1_A1:
842 case RT5665_L_EQ_LPF1_H0:
843 case RT5665_R_EQ_LPF1_H0:
844 case RT5665_L_EQ_BPF1_A1:
845 case RT5665_R_EQ_BPF1_A1:
846 case RT5665_L_EQ_BPF1_A2:
847 case RT5665_R_EQ_BPF1_A2:
848 case RT5665_L_EQ_BPF1_H0:
849 case RT5665_R_EQ_BPF1_H0:
850 case RT5665_L_EQ_BPF2_A1:
851 case RT5665_R_EQ_BPF2_A1:
852 case RT5665_L_EQ_BPF2_A2:
853 case RT5665_R_EQ_BPF2_A2:
854 case RT5665_L_EQ_BPF2_H0:
855 case RT5665_R_EQ_BPF2_H0:
856 case RT5665_L_EQ_BPF3_A1:
857 case RT5665_R_EQ_BPF3_A1:
858 case RT5665_L_EQ_BPF3_A2:
859 case RT5665_R_EQ_BPF3_A2:
860 case RT5665_L_EQ_BPF3_H0:
861 case RT5665_R_EQ_BPF3_H0:
862 case RT5665_L_EQ_BPF4_A1:
863 case RT5665_R_EQ_BPF4_A1:
864 case RT5665_L_EQ_BPF4_A2:
865 case RT5665_R_EQ_BPF4_A2:
866 case RT5665_L_EQ_BPF4_H0:
867 case RT5665_R_EQ_BPF4_H0:
868 case RT5665_L_EQ_HPF1_A1:
869 case RT5665_R_EQ_HPF1_A1:
870 case RT5665_L_EQ_HPF1_H0:
871 case RT5665_R_EQ_HPF1_H0:
872 case RT5665_L_EQ_PRE_VOL:
873 case RT5665_R_EQ_PRE_VOL:
874 case RT5665_L_EQ_POST_VOL:
875 case RT5665_R_EQ_POST_VOL:
876 case RT5665_SCAN_MODE_CTRL:
877 case RT5665_I2C_MODE:
878 return true;
879 default:
880 return false;
881 }
882 }
883
884 static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -2250, 150, 0);
885 static const DECLARE_TLV_DB_SCALE(mono_vol_tlv, -1400, 150, 0);
886 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
887 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
888 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
889 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
890 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
891 static const DECLARE_TLV_DB_SCALE(in_bst_tlv, -1200, 75, 0);
892
893 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
894 static const DECLARE_TLV_DB_RANGE(bst_tlv,
895 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
896 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
897 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
898 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
899 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
900 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
901 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
902 );
903
904 /* Interface data select */
905 static const char * const rt5665_data_select[] = {
906 "L/R", "R/L", "L/L", "R/R"
907 };
908
909 static SOC_ENUM_SINGLE_DECL(rt5665_if1_1_01_adc_enum,
910 RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT01_SFT, rt5665_data_select);
911
912 static SOC_ENUM_SINGLE_DECL(rt5665_if1_1_23_adc_enum,
913 RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT23_SFT, rt5665_data_select);
914
915 static SOC_ENUM_SINGLE_DECL(rt5665_if1_1_45_adc_enum,
916 RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT45_SFT, rt5665_data_select);
917
918 static SOC_ENUM_SINGLE_DECL(rt5665_if1_1_67_adc_enum,
919 RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT67_SFT, rt5665_data_select);
920
921 static SOC_ENUM_SINGLE_DECL(rt5665_if1_2_01_adc_enum,
922 RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT01_SFT, rt5665_data_select);
923
924 static SOC_ENUM_SINGLE_DECL(rt5665_if1_2_23_adc_enum,
925 RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT23_SFT, rt5665_data_select);
926
927 static SOC_ENUM_SINGLE_DECL(rt5665_if1_2_45_adc_enum,
928 RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT45_SFT, rt5665_data_select);
929
930 static SOC_ENUM_SINGLE_DECL(rt5665_if1_2_67_adc_enum,
931 RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT67_SFT, rt5665_data_select);
932
933 static SOC_ENUM_SINGLE_DECL(rt5665_if2_1_dac_enum,
934 RT5665_DIG_INF2_DATA, RT5665_IF2_1_DAC_SEL_SFT, rt5665_data_select);
935
936 static SOC_ENUM_SINGLE_DECL(rt5665_if2_1_adc_enum,
937 RT5665_DIG_INF2_DATA, RT5665_IF2_1_ADC_SEL_SFT, rt5665_data_select);
938
939 static SOC_ENUM_SINGLE_DECL(rt5665_if2_2_dac_enum,
940 RT5665_DIG_INF2_DATA, RT5665_IF2_2_DAC_SEL_SFT, rt5665_data_select);
941
942 static SOC_ENUM_SINGLE_DECL(rt5665_if2_2_adc_enum,
943 RT5665_DIG_INF2_DATA, RT5665_IF2_2_ADC_SEL_SFT, rt5665_data_select);
944
945 static SOC_ENUM_SINGLE_DECL(rt5665_if3_dac_enum,
946 RT5665_DIG_INF3_DATA, RT5665_IF3_DAC_SEL_SFT, rt5665_data_select);
947
948 static SOC_ENUM_SINGLE_DECL(rt5665_if3_adc_enum,
949 RT5665_DIG_INF3_DATA, RT5665_IF3_ADC_SEL_SFT, rt5665_data_select);
950
951 static const struct snd_kcontrol_new rt5665_if1_1_01_adc_swap_mux =
952 SOC_DAPM_ENUM("IF1_1 01 ADC Swap Mux", rt5665_if1_1_01_adc_enum);
953
954 static const struct snd_kcontrol_new rt5665_if1_1_23_adc_swap_mux =
955 SOC_DAPM_ENUM("IF1_1 23 ADC Swap Mux", rt5665_if1_1_23_adc_enum);
956
957 static const struct snd_kcontrol_new rt5665_if1_1_45_adc_swap_mux =
958 SOC_DAPM_ENUM("IF1_1 45 ADC Swap Mux", rt5665_if1_1_45_adc_enum);
959
960 static const struct snd_kcontrol_new rt5665_if1_1_67_adc_swap_mux =
961 SOC_DAPM_ENUM("IF1_1 67 ADC Swap Mux", rt5665_if1_1_67_adc_enum);
962
963 static const struct snd_kcontrol_new rt5665_if1_2_01_adc_swap_mux =
964 SOC_DAPM_ENUM("IF1_2 01 ADC Swap Mux", rt5665_if1_2_01_adc_enum);
965
966 static const struct snd_kcontrol_new rt5665_if1_2_23_adc_swap_mux =
967 SOC_DAPM_ENUM("IF1_2 23 ADC1 Swap Mux", rt5665_if1_2_23_adc_enum);
968
969 static const struct snd_kcontrol_new rt5665_if1_2_45_adc_swap_mux =
970 SOC_DAPM_ENUM("IF1_2 45 ADC1 Swap Mux", rt5665_if1_2_45_adc_enum);
971
972 static const struct snd_kcontrol_new rt5665_if1_2_67_adc_swap_mux =
973 SOC_DAPM_ENUM("IF1_2 67 ADC1 Swap Mux", rt5665_if1_2_67_adc_enum);
974
975 static const struct snd_kcontrol_new rt5665_if2_1_dac_swap_mux =
976 SOC_DAPM_ENUM("IF2_1 DAC Swap Source", rt5665_if2_1_dac_enum);
977
978 static const struct snd_kcontrol_new rt5665_if2_1_adc_swap_mux =
979 SOC_DAPM_ENUM("IF2_1 ADC Swap Source", rt5665_if2_1_adc_enum);
980
981 static const struct snd_kcontrol_new rt5665_if2_2_dac_swap_mux =
982 SOC_DAPM_ENUM("IF2_2 DAC Swap Source", rt5665_if2_2_dac_enum);
983
984 static const struct snd_kcontrol_new rt5665_if2_2_adc_swap_mux =
985 SOC_DAPM_ENUM("IF2_2 ADC Swap Source", rt5665_if2_2_adc_enum);
986
987 static const struct snd_kcontrol_new rt5665_if3_dac_swap_mux =
988 SOC_DAPM_ENUM("IF3 DAC Swap Source", rt5665_if3_dac_enum);
989
990 static const struct snd_kcontrol_new rt5665_if3_adc_swap_mux =
991 SOC_DAPM_ENUM("IF3 ADC Swap Source", rt5665_if3_adc_enum);
992
rt5665_hp_vol_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)993 static int rt5665_hp_vol_put(struct snd_kcontrol *kcontrol,
994 struct snd_ctl_elem_value *ucontrol)
995 {
996 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
997 int ret = snd_soc_put_volsw(kcontrol, ucontrol);
998
999 if (snd_soc_component_read(component, RT5665_STO_NG2_CTRL_1) & RT5665_NG2_EN) {
1000 snd_soc_component_update_bits(component, RT5665_STO_NG2_CTRL_1,
1001 RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
1002 snd_soc_component_update_bits(component, RT5665_STO_NG2_CTRL_1,
1003 RT5665_NG2_EN_MASK, RT5665_NG2_EN);
1004 }
1005
1006 return ret;
1007 }
1008
rt5665_mono_vol_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1009 static int rt5665_mono_vol_put(struct snd_kcontrol *kcontrol,
1010 struct snd_ctl_elem_value *ucontrol)
1011 {
1012 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1013 int ret = snd_soc_put_volsw(kcontrol, ucontrol);
1014
1015 if (snd_soc_component_read(component, RT5665_MONO_NG2_CTRL_1) & RT5665_NG2_EN) {
1016 snd_soc_component_update_bits(component, RT5665_MONO_NG2_CTRL_1,
1017 RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
1018 snd_soc_component_update_bits(component, RT5665_MONO_NG2_CTRL_1,
1019 RT5665_NG2_EN_MASK, RT5665_NG2_EN);
1020 }
1021
1022 return ret;
1023 }
1024
1025 /**
1026 * rt5665_sel_asrc_clk_src - select ASRC clock source for a set of filters
1027 * @component: SoC audio component device.
1028 * @filter_mask: mask of filters.
1029 * @clk_src: clock source
1030 *
1031 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5665 can
1032 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
1033 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
1034 * ASRC function will track i2s clock and generate a corresponding system clock
1035 * for codec. This function provides an API to select the clock source for a
1036 * set of filters specified by the mask. And the codec driver will turn on ASRC
1037 * for these filters if ASRC is selected as their clock source.
1038 */
rt5665_sel_asrc_clk_src(struct snd_soc_component * component,unsigned int filter_mask,unsigned int clk_src)1039 int rt5665_sel_asrc_clk_src(struct snd_soc_component *component,
1040 unsigned int filter_mask, unsigned int clk_src)
1041 {
1042 unsigned int asrc2_mask = 0;
1043 unsigned int asrc2_value = 0;
1044 unsigned int asrc3_mask = 0;
1045 unsigned int asrc3_value = 0;
1046
1047 switch (clk_src) {
1048 case RT5665_CLK_SEL_SYS:
1049 case RT5665_CLK_SEL_I2S1_ASRC:
1050 case RT5665_CLK_SEL_I2S2_ASRC:
1051 case RT5665_CLK_SEL_I2S3_ASRC:
1052 case RT5665_CLK_SEL_SYS2:
1053 case RT5665_CLK_SEL_SYS3:
1054 case RT5665_CLK_SEL_SYS4:
1055 break;
1056
1057 default:
1058 return -EINVAL;
1059 }
1060
1061 if (filter_mask & RT5665_DA_STEREO1_FILTER) {
1062 asrc2_mask |= RT5665_DA_STO1_CLK_SEL_MASK;
1063 asrc2_value = (asrc2_value & ~RT5665_DA_STO1_CLK_SEL_MASK)
1064 | (clk_src << RT5665_DA_STO1_CLK_SEL_SFT);
1065 }
1066
1067 if (filter_mask & RT5665_DA_STEREO2_FILTER) {
1068 asrc2_mask |= RT5665_DA_STO2_CLK_SEL_MASK;
1069 asrc2_value = (asrc2_value & ~RT5665_DA_STO2_CLK_SEL_MASK)
1070 | (clk_src << RT5665_DA_STO2_CLK_SEL_SFT);
1071 }
1072
1073 if (filter_mask & RT5665_DA_MONO_L_FILTER) {
1074 asrc2_mask |= RT5665_DA_MONOL_CLK_SEL_MASK;
1075 asrc2_value = (asrc2_value & ~RT5665_DA_MONOL_CLK_SEL_MASK)
1076 | (clk_src << RT5665_DA_MONOL_CLK_SEL_SFT);
1077 }
1078
1079 if (filter_mask & RT5665_DA_MONO_R_FILTER) {
1080 asrc2_mask |= RT5665_DA_MONOR_CLK_SEL_MASK;
1081 asrc2_value = (asrc2_value & ~RT5665_DA_MONOR_CLK_SEL_MASK)
1082 | (clk_src << RT5665_DA_MONOR_CLK_SEL_SFT);
1083 }
1084
1085 if (filter_mask & RT5665_AD_STEREO1_FILTER) {
1086 asrc3_mask |= RT5665_AD_STO1_CLK_SEL_MASK;
1087 asrc3_value = (asrc2_value & ~RT5665_AD_STO1_CLK_SEL_MASK)
1088 | (clk_src << RT5665_AD_STO1_CLK_SEL_SFT);
1089 }
1090
1091 if (filter_mask & RT5665_AD_STEREO2_FILTER) {
1092 asrc3_mask |= RT5665_AD_STO2_CLK_SEL_MASK;
1093 asrc3_value = (asrc2_value & ~RT5665_AD_STO2_CLK_SEL_MASK)
1094 | (clk_src << RT5665_AD_STO2_CLK_SEL_SFT);
1095 }
1096
1097 if (filter_mask & RT5665_AD_MONO_L_FILTER) {
1098 asrc3_mask |= RT5665_AD_MONOL_CLK_SEL_MASK;
1099 asrc3_value = (asrc3_value & ~RT5665_AD_MONOL_CLK_SEL_MASK)
1100 | (clk_src << RT5665_AD_MONOL_CLK_SEL_SFT);
1101 }
1102
1103 if (filter_mask & RT5665_AD_MONO_R_FILTER) {
1104 asrc3_mask |= RT5665_AD_MONOR_CLK_SEL_MASK;
1105 asrc3_value = (asrc3_value & ~RT5665_AD_MONOR_CLK_SEL_MASK)
1106 | (clk_src << RT5665_AD_MONOR_CLK_SEL_SFT);
1107 }
1108
1109 if (asrc2_mask)
1110 snd_soc_component_update_bits(component, RT5665_ASRC_2,
1111 asrc2_mask, asrc2_value);
1112
1113 if (asrc3_mask)
1114 snd_soc_component_update_bits(component, RT5665_ASRC_3,
1115 asrc3_mask, asrc3_value);
1116
1117 return 0;
1118 }
1119 EXPORT_SYMBOL_GPL(rt5665_sel_asrc_clk_src);
1120
rt5665_button_detect(struct snd_soc_component * component)1121 static int rt5665_button_detect(struct snd_soc_component *component)
1122 {
1123 int btn_type, val;
1124
1125 val = snd_soc_component_read(component, RT5665_4BTN_IL_CMD_1);
1126 btn_type = val & 0xfff0;
1127 snd_soc_component_write(component, RT5665_4BTN_IL_CMD_1, val);
1128
1129 return btn_type;
1130 }
1131
rt5665_enable_push_button_irq(struct snd_soc_component * component,bool enable)1132 static void rt5665_enable_push_button_irq(struct snd_soc_component *component,
1133 bool enable)
1134 {
1135 if (enable) {
1136 snd_soc_component_write(component, RT5665_4BTN_IL_CMD_1, 0x0003);
1137 snd_soc_component_update_bits(component, RT5665_SAR_IL_CMD_9, 0x1, 0x1);
1138 snd_soc_component_write(component, RT5665_IL_CMD_1, 0x0048);
1139 snd_soc_component_update_bits(component, RT5665_4BTN_IL_CMD_2,
1140 RT5665_4BTN_IL_MASK | RT5665_4BTN_IL_RST_MASK,
1141 RT5665_4BTN_IL_EN | RT5665_4BTN_IL_NOR);
1142 snd_soc_component_update_bits(component, RT5665_IRQ_CTRL_3,
1143 RT5665_IL_IRQ_MASK, RT5665_IL_IRQ_EN);
1144 } else {
1145 snd_soc_component_update_bits(component, RT5665_IRQ_CTRL_3,
1146 RT5665_IL_IRQ_MASK, RT5665_IL_IRQ_DIS);
1147 snd_soc_component_update_bits(component, RT5665_4BTN_IL_CMD_2,
1148 RT5665_4BTN_IL_MASK, RT5665_4BTN_IL_DIS);
1149 snd_soc_component_update_bits(component, RT5665_4BTN_IL_CMD_2,
1150 RT5665_4BTN_IL_RST_MASK, RT5665_4BTN_IL_RST);
1151 }
1152 }
1153
1154 /**
1155 * rt5665_headset_detect - Detect headset.
1156 * @component: SoC audio component device.
1157 * @jack_insert: Jack insert or not.
1158 *
1159 * Detect whether is headset or not when jack inserted.
1160 *
1161 * Returns detect status.
1162 */
rt5665_headset_detect(struct snd_soc_component * component,int jack_insert)1163 static int rt5665_headset_detect(struct snd_soc_component *component, int jack_insert)
1164 {
1165 struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
1166 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
1167 unsigned int sar_hs_type, val;
1168
1169 if (jack_insert) {
1170 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
1171 snd_soc_dapm_sync(dapm);
1172
1173 regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2, 0x100,
1174 0x100);
1175
1176 regmap_read(rt5665->regmap, RT5665_GPIO_STA, &val);
1177 if (val & 0x4) {
1178 regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1,
1179 0x100, 0);
1180
1181 regmap_read(rt5665->regmap, RT5665_GPIO_STA, &val);
1182 while (val & 0x4) {
1183 usleep_range(10000, 15000);
1184 regmap_read(rt5665->regmap, RT5665_GPIO_STA,
1185 &val);
1186 }
1187 }
1188
1189 regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1,
1190 0x1a0, 0x120);
1191 regmap_write(rt5665->regmap, RT5665_EJD_CTRL_3, 0x3424);
1192 regmap_write(rt5665->regmap, RT5665_IL_CMD_1, 0x0048);
1193 regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1, 0xa291);
1194
1195 usleep_range(10000, 15000);
1196
1197 rt5665->sar_adc_value = snd_soc_component_read(rt5665->component,
1198 RT5665_SAR_IL_CMD_4) & 0x7ff;
1199
1200 sar_hs_type = rt5665->pdata.sar_hs_type ?
1201 rt5665->pdata.sar_hs_type : 729;
1202
1203 if (rt5665->sar_adc_value > sar_hs_type) {
1204 rt5665->jack_type = SND_JACK_HEADSET;
1205 rt5665_enable_push_button_irq(component, true);
1206 } else {
1207 rt5665->jack_type = SND_JACK_HEADPHONE;
1208 regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1,
1209 0x2291);
1210 regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2,
1211 0x100, 0);
1212 snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1213 snd_soc_dapm_sync(dapm);
1214 }
1215 } else {
1216 regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1, 0x2291);
1217 regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2, 0x100, 0);
1218 snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1219 snd_soc_dapm_sync(dapm);
1220 if (rt5665->jack_type == SND_JACK_HEADSET)
1221 rt5665_enable_push_button_irq(component, false);
1222 rt5665->jack_type = 0;
1223 }
1224
1225 dev_dbg(component->dev, "jack_type = %d\n", rt5665->jack_type);
1226 return rt5665->jack_type;
1227 }
1228
rt5665_irq(int irq,void * data)1229 static irqreturn_t rt5665_irq(int irq, void *data)
1230 {
1231 struct rt5665_priv *rt5665 = data;
1232
1233 mod_delayed_work(system_power_efficient_wq,
1234 &rt5665->jack_detect_work, msecs_to_jiffies(250));
1235
1236 return IRQ_HANDLED;
1237 }
1238
rt5665_jd_check_handler(struct work_struct * work)1239 static void rt5665_jd_check_handler(struct work_struct *work)
1240 {
1241 struct rt5665_priv *rt5665 = container_of(work, struct rt5665_priv,
1242 jd_check_work.work);
1243
1244 if (snd_soc_component_read(rt5665->component, RT5665_AJD1_CTRL) & 0x0010) {
1245 /* jack out */
1246 rt5665->jack_type = rt5665_headset_detect(rt5665->component, 0);
1247
1248 snd_soc_jack_report(rt5665->hs_jack, rt5665->jack_type,
1249 SND_JACK_HEADSET |
1250 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1251 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1252 } else {
1253 schedule_delayed_work(&rt5665->jd_check_work, 500);
1254 }
1255 }
1256
rt5665_set_jack_detect(struct snd_soc_component * component,struct snd_soc_jack * hs_jack,void * data)1257 static int rt5665_set_jack_detect(struct snd_soc_component *component,
1258 struct snd_soc_jack *hs_jack, void *data)
1259 {
1260 struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
1261
1262 switch (rt5665->pdata.jd_src) {
1263 case RT5665_JD1:
1264 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
1265 RT5665_GP1_PIN_MASK, RT5665_GP1_PIN_IRQ);
1266 regmap_update_bits(rt5665->regmap, RT5665_RC_CLK_CTRL,
1267 0xc000, 0xc000);
1268 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_2,
1269 RT5665_PWR_JD1, RT5665_PWR_JD1);
1270 regmap_update_bits(rt5665->regmap, RT5665_IRQ_CTRL_1, 0x8, 0x8);
1271 break;
1272
1273 case RT5665_JD_NULL:
1274 break;
1275
1276 default:
1277 dev_warn(component->dev, "Wrong JD source\n");
1278 break;
1279 }
1280
1281 rt5665->hs_jack = hs_jack;
1282
1283 return 0;
1284 }
1285
rt5665_jack_detect_handler(struct work_struct * work)1286 static void rt5665_jack_detect_handler(struct work_struct *work)
1287 {
1288 struct rt5665_priv *rt5665 =
1289 container_of(work, struct rt5665_priv, jack_detect_work.work);
1290 int val, btn_type;
1291
1292 while (!rt5665->component) {
1293 pr_debug("%s codec = null\n", __func__);
1294 usleep_range(10000, 15000);
1295 }
1296
1297 while (!snd_soc_card_is_instantiated(rt5665->component->card)) {
1298 pr_debug("%s\n", __func__);
1299 usleep_range(10000, 15000);
1300 }
1301
1302 while (!rt5665->calibration_done) {
1303 pr_debug("%s calibration not ready\n", __func__);
1304 usleep_range(10000, 15000);
1305 }
1306
1307 mutex_lock(&rt5665->calibrate_mutex);
1308
1309 val = snd_soc_component_read(rt5665->component, RT5665_AJD1_CTRL) & 0x0010;
1310 if (!val) {
1311 /* jack in */
1312 if (rt5665->jack_type == 0) {
1313 /* jack was out, report jack type */
1314 rt5665->jack_type =
1315 rt5665_headset_detect(rt5665->component, 1);
1316 } else {
1317 /* jack is already in, report button event */
1318 rt5665->jack_type = SND_JACK_HEADSET;
1319 btn_type = rt5665_button_detect(rt5665->component);
1320 /**
1321 * rt5665 can report three kinds of button behavior,
1322 * one click, double click and hold. However,
1323 * currently we will report button pressed/released
1324 * event. So all the three button behaviors are
1325 * treated as button pressed.
1326 */
1327 switch (btn_type) {
1328 case 0x8000:
1329 case 0x4000:
1330 case 0x2000:
1331 rt5665->jack_type |= SND_JACK_BTN_0;
1332 break;
1333 case 0x1000:
1334 case 0x0800:
1335 case 0x0400:
1336 rt5665->jack_type |= SND_JACK_BTN_1;
1337 break;
1338 case 0x0200:
1339 case 0x0100:
1340 case 0x0080:
1341 rt5665->jack_type |= SND_JACK_BTN_2;
1342 break;
1343 case 0x0040:
1344 case 0x0020:
1345 case 0x0010:
1346 rt5665->jack_type |= SND_JACK_BTN_3;
1347 break;
1348 case 0x0000: /* unpressed */
1349 break;
1350 default:
1351 btn_type = 0;
1352 dev_err(rt5665->component->dev,
1353 "Unexpected button code 0x%04x\n",
1354 btn_type);
1355 break;
1356 }
1357 }
1358 } else {
1359 /* jack out */
1360 rt5665->jack_type = rt5665_headset_detect(rt5665->component, 0);
1361 }
1362
1363 snd_soc_jack_report(rt5665->hs_jack, rt5665->jack_type,
1364 SND_JACK_HEADSET |
1365 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1366 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1367
1368 if (rt5665->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1369 SND_JACK_BTN_2 | SND_JACK_BTN_3))
1370 schedule_delayed_work(&rt5665->jd_check_work, 0);
1371 else
1372 cancel_delayed_work_sync(&rt5665->jd_check_work);
1373
1374 mutex_unlock(&rt5665->calibrate_mutex);
1375 }
1376
1377 static const char * const rt5665_clk_sync[] = {
1378 "I2S1_1", "I2S1_2", "I2S2", "I2S3", "IF2 Slave", "IF3 Slave"
1379 };
1380
1381 static const struct soc_enum rt5665_enum[] = {
1382 SOC_ENUM_SINGLE(RT5665_I2S1_SDP, 11, 5, rt5665_clk_sync),
1383 SOC_ENUM_SINGLE(RT5665_I2S2_SDP, 11, 5, rt5665_clk_sync),
1384 SOC_ENUM_SINGLE(RT5665_I2S3_SDP, 11, 5, rt5665_clk_sync),
1385 };
1386
1387 static const struct snd_kcontrol_new rt5665_snd_controls[] = {
1388 /* Headphone Output Volume */
1389 SOC_DOUBLE_R_EXT_TLV("Headphone Playback Volume", RT5665_HPL_GAIN,
1390 RT5665_HPR_GAIN, RT5665_G_HP_SFT, 15, 1, snd_soc_get_volsw,
1391 rt5665_hp_vol_put, hp_vol_tlv),
1392
1393 /* Mono Output Volume */
1394 SOC_SINGLE_EXT_TLV("Mono Playback Volume", RT5665_MONO_GAIN,
1395 RT5665_L_VOL_SFT, 15, 1, snd_soc_get_volsw,
1396 rt5665_mono_vol_put, mono_vol_tlv),
1397
1398 SOC_SINGLE_TLV("MONOVOL Playback Volume", RT5665_MONO_OUT,
1399 RT5665_L_VOL_SFT, 39, 1, out_vol_tlv),
1400
1401 /* Output Volume */
1402 SOC_DOUBLE_TLV("OUT Playback Volume", RT5665_LOUT, RT5665_L_VOL_SFT,
1403 RT5665_R_VOL_SFT, 39, 1, out_vol_tlv),
1404
1405 /* DAC Digital Volume */
1406 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5665_DAC1_DIG_VOL,
1407 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 175, 0, dac_vol_tlv),
1408 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5665_DAC2_DIG_VOL,
1409 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 175, 0, dac_vol_tlv),
1410 SOC_DOUBLE("DAC2 Playback Switch", RT5665_DAC2_CTRL,
1411 RT5665_M_DAC2_L_VOL_SFT, RT5665_M_DAC2_R_VOL_SFT, 1, 1),
1412
1413 /* IN1/IN2/IN3/IN4 Volume */
1414 SOC_SINGLE_TLV("IN1 Boost Volume", RT5665_IN1_IN2,
1415 RT5665_BST1_SFT, 69, 0, in_bst_tlv),
1416 SOC_SINGLE_TLV("IN2 Boost Volume", RT5665_IN1_IN2,
1417 RT5665_BST2_SFT, 69, 0, in_bst_tlv),
1418 SOC_SINGLE_TLV("IN3 Boost Volume", RT5665_IN3_IN4,
1419 RT5665_BST3_SFT, 69, 0, in_bst_tlv),
1420 SOC_SINGLE_TLV("IN4 Boost Volume", RT5665_IN3_IN4,
1421 RT5665_BST4_SFT, 69, 0, in_bst_tlv),
1422 SOC_SINGLE_TLV("CBJ Boost Volume", RT5665_CBJ_BST_CTRL,
1423 RT5665_BST_CBJ_SFT, 8, 0, bst_tlv),
1424
1425 /* INL/INR Volume Control */
1426 SOC_DOUBLE_TLV("IN Capture Volume", RT5665_INL1_INR1_VOL,
1427 RT5665_INL_VOL_SFT, RT5665_INR_VOL_SFT, 31, 1, in_vol_tlv),
1428
1429 /* ADC Digital Volume Control */
1430 SOC_DOUBLE("STO1 ADC Capture Switch", RT5665_STO1_ADC_DIG_VOL,
1431 RT5665_L_MUTE_SFT, RT5665_R_MUTE_SFT, 1, 1),
1432 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5665_STO1_ADC_DIG_VOL,
1433 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 127, 0, adc_vol_tlv),
1434 SOC_DOUBLE("Mono ADC Capture Switch", RT5665_MONO_ADC_DIG_VOL,
1435 RT5665_L_MUTE_SFT, RT5665_R_MUTE_SFT, 1, 1),
1436 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5665_MONO_ADC_DIG_VOL,
1437 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 127, 0, adc_vol_tlv),
1438 SOC_DOUBLE("STO2 ADC Capture Switch", RT5665_STO2_ADC_DIG_VOL,
1439 RT5665_L_MUTE_SFT, RT5665_R_MUTE_SFT, 1, 1),
1440 SOC_DOUBLE_TLV("STO2 ADC Capture Volume", RT5665_STO2_ADC_DIG_VOL,
1441 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 127, 0, adc_vol_tlv),
1442
1443 /* ADC Boost Volume Control */
1444 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5665_STO1_ADC_BOOST,
1445 RT5665_STO1_ADC_L_BST_SFT, RT5665_STO1_ADC_R_BST_SFT,
1446 3, 0, adc_bst_tlv),
1447
1448 SOC_DOUBLE_TLV("Mono ADC Boost Gain Volume", RT5665_MONO_ADC_BOOST,
1449 RT5665_MONO_ADC_L_BST_SFT, RT5665_MONO_ADC_R_BST_SFT,
1450 3, 0, adc_bst_tlv),
1451
1452 SOC_DOUBLE_TLV("STO2 ADC Boost Gain Volume", RT5665_STO2_ADC_BOOST,
1453 RT5665_STO2_ADC_L_BST_SFT, RT5665_STO2_ADC_R_BST_SFT,
1454 3, 0, adc_bst_tlv),
1455
1456 /* I2S3 CLK Source */
1457 SOC_ENUM("I2S1 Master Clk Sel", rt5665_enum[0]),
1458 SOC_ENUM("I2S2 Master Clk Sel", rt5665_enum[1]),
1459 SOC_ENUM("I2S3 Master Clk Sel", rt5665_enum[2]),
1460 };
1461
1462 /**
1463 * set_dmic_clk - Set parameter of dmic.
1464 *
1465 * @w: DAPM widget.
1466 * @kcontrol: The kcontrol of this widget.
1467 * @event: Event id.
1468 *
1469 * Choose dmic clock between 1MHz and 3MHz.
1470 * It is better for clock to approximate 3MHz.
1471 */
set_dmic_clk(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1472 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1473 struct snd_kcontrol *kcontrol, int event)
1474 {
1475 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1476 struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
1477 int pd, idx;
1478
1479 pd = rl6231_get_pre_div(rt5665->regmap,
1480 RT5665_ADDA_CLK_1, RT5665_I2S_PD1_SFT);
1481 idx = rl6231_calc_dmic_clk(rt5665->sysclk / pd);
1482
1483 if (idx < 0)
1484 dev_err(component->dev, "Failed to set DMIC clock\n");
1485 else {
1486 snd_soc_component_update_bits(component, RT5665_DMIC_CTRL_1,
1487 RT5665_DMIC_CLK_MASK, idx << RT5665_DMIC_CLK_SFT);
1488 }
1489 return idx;
1490 }
1491
rt5665_charge_pump_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1492 static int rt5665_charge_pump_event(struct snd_soc_dapm_widget *w,
1493 struct snd_kcontrol *kcontrol, int event)
1494 {
1495 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1496
1497 switch (event) {
1498 case SND_SOC_DAPM_PRE_PMU:
1499 snd_soc_component_update_bits(component, RT5665_HP_CHARGE_PUMP_1,
1500 RT5665_PM_HP_MASK | RT5665_OSW_L_MASK,
1501 RT5665_PM_HP_HV | RT5665_OSW_L_EN);
1502 break;
1503 case SND_SOC_DAPM_POST_PMD:
1504 snd_soc_component_update_bits(component, RT5665_HP_CHARGE_PUMP_1,
1505 RT5665_PM_HP_MASK | RT5665_OSW_L_MASK,
1506 RT5665_PM_HP_LV | RT5665_OSW_L_DIS);
1507 break;
1508 default:
1509 return 0;
1510 }
1511
1512 return 0;
1513 }
1514
is_sys_clk_from_pll(struct snd_soc_dapm_widget * w,struct snd_soc_dapm_widget * sink)1515 static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *w,
1516 struct snd_soc_dapm_widget *sink)
1517 {
1518 unsigned int val;
1519 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1520
1521 val = snd_soc_component_read(component, RT5665_GLB_CLK);
1522 val &= RT5665_SCLK_SRC_MASK;
1523 if (val == RT5665_SCLK_SRC_PLL1)
1524 return 1;
1525 else
1526 return 0;
1527 }
1528
is_using_asrc(struct snd_soc_dapm_widget * w,struct snd_soc_dapm_widget * sink)1529 static int is_using_asrc(struct snd_soc_dapm_widget *w,
1530 struct snd_soc_dapm_widget *sink)
1531 {
1532 unsigned int reg, shift, val;
1533 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1534
1535 switch (w->shift) {
1536 case RT5665_ADC_MONO_R_ASRC_SFT:
1537 reg = RT5665_ASRC_3;
1538 shift = RT5665_AD_MONOR_CLK_SEL_SFT;
1539 break;
1540 case RT5665_ADC_MONO_L_ASRC_SFT:
1541 reg = RT5665_ASRC_3;
1542 shift = RT5665_AD_MONOL_CLK_SEL_SFT;
1543 break;
1544 case RT5665_ADC_STO1_ASRC_SFT:
1545 reg = RT5665_ASRC_3;
1546 shift = RT5665_AD_STO1_CLK_SEL_SFT;
1547 break;
1548 case RT5665_ADC_STO2_ASRC_SFT:
1549 reg = RT5665_ASRC_3;
1550 shift = RT5665_AD_STO2_CLK_SEL_SFT;
1551 break;
1552 case RT5665_DAC_MONO_R_ASRC_SFT:
1553 reg = RT5665_ASRC_2;
1554 shift = RT5665_DA_MONOR_CLK_SEL_SFT;
1555 break;
1556 case RT5665_DAC_MONO_L_ASRC_SFT:
1557 reg = RT5665_ASRC_2;
1558 shift = RT5665_DA_MONOL_CLK_SEL_SFT;
1559 break;
1560 case RT5665_DAC_STO1_ASRC_SFT:
1561 reg = RT5665_ASRC_2;
1562 shift = RT5665_DA_STO1_CLK_SEL_SFT;
1563 break;
1564 case RT5665_DAC_STO2_ASRC_SFT:
1565 reg = RT5665_ASRC_2;
1566 shift = RT5665_DA_STO2_CLK_SEL_SFT;
1567 break;
1568 default:
1569 return 0;
1570 }
1571
1572 val = (snd_soc_component_read(component, reg) >> shift) & 0xf;
1573 switch (val) {
1574 case RT5665_CLK_SEL_I2S1_ASRC:
1575 case RT5665_CLK_SEL_I2S2_ASRC:
1576 case RT5665_CLK_SEL_I2S3_ASRC:
1577 /* I2S_Pre_Div1 should be 1 in asrc mode */
1578 snd_soc_component_update_bits(component, RT5665_ADDA_CLK_1,
1579 RT5665_I2S_PD1_MASK, RT5665_I2S_PD1_2);
1580 return 1;
1581 default:
1582 return 0;
1583 }
1584
1585 }
1586
1587 /* Digital Mixer */
1588 static const struct snd_kcontrol_new rt5665_sto1_adc_l_mix[] = {
1589 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO1_ADC_MIXER,
1590 RT5665_M_STO1_ADC_L1_SFT, 1, 1),
1591 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO1_ADC_MIXER,
1592 RT5665_M_STO1_ADC_L2_SFT, 1, 1),
1593 };
1594
1595 static const struct snd_kcontrol_new rt5665_sto1_adc_r_mix[] = {
1596 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO1_ADC_MIXER,
1597 RT5665_M_STO1_ADC_R1_SFT, 1, 1),
1598 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO1_ADC_MIXER,
1599 RT5665_M_STO1_ADC_R2_SFT, 1, 1),
1600 };
1601
1602 static const struct snd_kcontrol_new rt5665_sto2_adc_l_mix[] = {
1603 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO2_ADC_MIXER,
1604 RT5665_M_STO2_ADC_L1_SFT, 1, 1),
1605 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO2_ADC_MIXER,
1606 RT5665_M_STO2_ADC_L2_SFT, 1, 1),
1607 };
1608
1609 static const struct snd_kcontrol_new rt5665_sto2_adc_r_mix[] = {
1610 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO2_ADC_MIXER,
1611 RT5665_M_STO2_ADC_R1_SFT, 1, 1),
1612 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO2_ADC_MIXER,
1613 RT5665_M_STO2_ADC_R2_SFT, 1, 1),
1614 };
1615
1616 static const struct snd_kcontrol_new rt5665_mono_adc_l_mix[] = {
1617 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_MONO_ADC_MIXER,
1618 RT5665_M_MONO_ADC_L1_SFT, 1, 1),
1619 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_MONO_ADC_MIXER,
1620 RT5665_M_MONO_ADC_L2_SFT, 1, 1),
1621 };
1622
1623 static const struct snd_kcontrol_new rt5665_mono_adc_r_mix[] = {
1624 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_MONO_ADC_MIXER,
1625 RT5665_M_MONO_ADC_R1_SFT, 1, 1),
1626 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_MONO_ADC_MIXER,
1627 RT5665_M_MONO_ADC_R2_SFT, 1, 1),
1628 };
1629
1630 static const struct snd_kcontrol_new rt5665_dac_l_mix[] = {
1631 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5665_AD_DA_MIXER,
1632 RT5665_M_ADCMIX_L_SFT, 1, 1),
1633 SOC_DAPM_SINGLE("DAC1 Switch", RT5665_AD_DA_MIXER,
1634 RT5665_M_DAC1_L_SFT, 1, 1),
1635 };
1636
1637 static const struct snd_kcontrol_new rt5665_dac_r_mix[] = {
1638 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5665_AD_DA_MIXER,
1639 RT5665_M_ADCMIX_R_SFT, 1, 1),
1640 SOC_DAPM_SINGLE("DAC1 Switch", RT5665_AD_DA_MIXER,
1641 RT5665_M_DAC1_R_SFT, 1, 1),
1642 };
1643
1644 static const struct snd_kcontrol_new rt5665_sto1_dac_l_mix[] = {
1645 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_STO1_DAC_MIXER,
1646 RT5665_M_DAC_L1_STO_L_SFT, 1, 1),
1647 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_STO1_DAC_MIXER,
1648 RT5665_M_DAC_R1_STO_L_SFT, 1, 1),
1649 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_STO1_DAC_MIXER,
1650 RT5665_M_DAC_L2_STO_L_SFT, 1, 1),
1651 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_STO1_DAC_MIXER,
1652 RT5665_M_DAC_R2_STO_L_SFT, 1, 1),
1653 };
1654
1655 static const struct snd_kcontrol_new rt5665_sto1_dac_r_mix[] = {
1656 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_STO1_DAC_MIXER,
1657 RT5665_M_DAC_L1_STO_R_SFT, 1, 1),
1658 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_STO1_DAC_MIXER,
1659 RT5665_M_DAC_R1_STO_R_SFT, 1, 1),
1660 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_STO1_DAC_MIXER,
1661 RT5665_M_DAC_L2_STO_R_SFT, 1, 1),
1662 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_STO1_DAC_MIXER,
1663 RT5665_M_DAC_R2_STO_R_SFT, 1, 1),
1664 };
1665
1666 static const struct snd_kcontrol_new rt5665_sto2_dac_l_mix[] = {
1667 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_STO2_DAC_MIXER,
1668 RT5665_M_DAC_L1_STO2_L_SFT, 1, 1),
1669 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_STO2_DAC_MIXER,
1670 RT5665_M_DAC_L2_STO2_L_SFT, 1, 1),
1671 SOC_DAPM_SINGLE("DAC L3 Switch", RT5665_STO2_DAC_MIXER,
1672 RT5665_M_DAC_L3_STO2_L_SFT, 1, 1),
1673 };
1674
1675 static const struct snd_kcontrol_new rt5665_sto2_dac_r_mix[] = {
1676 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_STO2_DAC_MIXER,
1677 RT5665_M_DAC_R1_STO2_R_SFT, 1, 1),
1678 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_STO2_DAC_MIXER,
1679 RT5665_M_DAC_R2_STO2_R_SFT, 1, 1),
1680 SOC_DAPM_SINGLE("DAC R3 Switch", RT5665_STO2_DAC_MIXER,
1681 RT5665_M_DAC_R3_STO2_R_SFT, 1, 1),
1682 };
1683
1684 static const struct snd_kcontrol_new rt5665_mono_dac_l_mix[] = {
1685 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_MONO_DAC_MIXER,
1686 RT5665_M_DAC_L1_MONO_L_SFT, 1, 1),
1687 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_MONO_DAC_MIXER,
1688 RT5665_M_DAC_R1_MONO_L_SFT, 1, 1),
1689 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONO_DAC_MIXER,
1690 RT5665_M_DAC_L2_MONO_L_SFT, 1, 1),
1691 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_MONO_DAC_MIXER,
1692 RT5665_M_DAC_R2_MONO_L_SFT, 1, 1),
1693 };
1694
1695 static const struct snd_kcontrol_new rt5665_mono_dac_r_mix[] = {
1696 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_MONO_DAC_MIXER,
1697 RT5665_M_DAC_L1_MONO_R_SFT, 1, 1),
1698 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_MONO_DAC_MIXER,
1699 RT5665_M_DAC_R1_MONO_R_SFT, 1, 1),
1700 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONO_DAC_MIXER,
1701 RT5665_M_DAC_L2_MONO_R_SFT, 1, 1),
1702 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_MONO_DAC_MIXER,
1703 RT5665_M_DAC_R2_MONO_R_SFT, 1, 1),
1704 };
1705
1706 /* Analog Input Mixer */
1707 static const struct snd_kcontrol_new rt5665_rec1_l_mix[] = {
1708 SOC_DAPM_SINGLE("CBJ Switch", RT5665_REC1_L2_MIXER,
1709 RT5665_M_CBJ_RM1_L_SFT, 1, 1),
1710 SOC_DAPM_SINGLE("INL Switch", RT5665_REC1_L2_MIXER,
1711 RT5665_M_INL_RM1_L_SFT, 1, 1),
1712 SOC_DAPM_SINGLE("INR Switch", RT5665_REC1_L2_MIXER,
1713 RT5665_M_INR_RM1_L_SFT, 1, 1),
1714 SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC1_L2_MIXER,
1715 RT5665_M_BST4_RM1_L_SFT, 1, 1),
1716 SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC1_L2_MIXER,
1717 RT5665_M_BST3_RM1_L_SFT, 1, 1),
1718 SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC1_L2_MIXER,
1719 RT5665_M_BST2_RM1_L_SFT, 1, 1),
1720 SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC1_L2_MIXER,
1721 RT5665_M_BST1_RM1_L_SFT, 1, 1),
1722 };
1723
1724 static const struct snd_kcontrol_new rt5665_rec1_r_mix[] = {
1725 SOC_DAPM_SINGLE("MONOVOL Switch", RT5665_REC1_R2_MIXER,
1726 RT5665_M_AEC_REF_RM1_R_SFT, 1, 1),
1727 SOC_DAPM_SINGLE("INR Switch", RT5665_REC1_R2_MIXER,
1728 RT5665_M_INR_RM1_R_SFT, 1, 1),
1729 SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC1_R2_MIXER,
1730 RT5665_M_BST4_RM1_R_SFT, 1, 1),
1731 SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC1_R2_MIXER,
1732 RT5665_M_BST3_RM1_R_SFT, 1, 1),
1733 SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC1_R2_MIXER,
1734 RT5665_M_BST2_RM1_R_SFT, 1, 1),
1735 SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC1_R2_MIXER,
1736 RT5665_M_BST1_RM1_R_SFT, 1, 1),
1737 };
1738
1739 static const struct snd_kcontrol_new rt5665_rec2_l_mix[] = {
1740 SOC_DAPM_SINGLE("INL Switch", RT5665_REC2_L2_MIXER,
1741 RT5665_M_INL_RM2_L_SFT, 1, 1),
1742 SOC_DAPM_SINGLE("INR Switch", RT5665_REC2_L2_MIXER,
1743 RT5665_M_INR_RM2_L_SFT, 1, 1),
1744 SOC_DAPM_SINGLE("CBJ Switch", RT5665_REC2_L2_MIXER,
1745 RT5665_M_CBJ_RM2_L_SFT, 1, 1),
1746 SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC2_L2_MIXER,
1747 RT5665_M_BST4_RM2_L_SFT, 1, 1),
1748 SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC2_L2_MIXER,
1749 RT5665_M_BST3_RM2_L_SFT, 1, 1),
1750 SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC2_L2_MIXER,
1751 RT5665_M_BST2_RM2_L_SFT, 1, 1),
1752 SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC2_L2_MIXER,
1753 RT5665_M_BST1_RM2_L_SFT, 1, 1),
1754 };
1755
1756 static const struct snd_kcontrol_new rt5665_rec2_r_mix[] = {
1757 SOC_DAPM_SINGLE("MONOVOL Switch", RT5665_REC2_R2_MIXER,
1758 RT5665_M_MONOVOL_RM2_R_SFT, 1, 1),
1759 SOC_DAPM_SINGLE("INL Switch", RT5665_REC2_R2_MIXER,
1760 RT5665_M_INL_RM2_R_SFT, 1, 1),
1761 SOC_DAPM_SINGLE("INR Switch", RT5665_REC2_R2_MIXER,
1762 RT5665_M_INR_RM2_R_SFT, 1, 1),
1763 SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC2_R2_MIXER,
1764 RT5665_M_BST4_RM2_R_SFT, 1, 1),
1765 SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC2_R2_MIXER,
1766 RT5665_M_BST3_RM2_R_SFT, 1, 1),
1767 SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC2_R2_MIXER,
1768 RT5665_M_BST2_RM2_R_SFT, 1, 1),
1769 SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC2_R2_MIXER,
1770 RT5665_M_BST1_RM2_R_SFT, 1, 1),
1771 };
1772
1773 static const struct snd_kcontrol_new rt5665_monovol_mix[] = {
1774 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONOMIX_IN_GAIN,
1775 RT5665_M_DAC_L2_MM_SFT, 1, 1),
1776 SOC_DAPM_SINGLE("RECMIX2L Switch", RT5665_MONOMIX_IN_GAIN,
1777 RT5665_M_RECMIC2L_MM_SFT, 1, 1),
1778 SOC_DAPM_SINGLE("BST1 Switch", RT5665_MONOMIX_IN_GAIN,
1779 RT5665_M_BST1_MM_SFT, 1, 1),
1780 SOC_DAPM_SINGLE("BST2 Switch", RT5665_MONOMIX_IN_GAIN,
1781 RT5665_M_BST2_MM_SFT, 1, 1),
1782 SOC_DAPM_SINGLE("BST3 Switch", RT5665_MONOMIX_IN_GAIN,
1783 RT5665_M_BST3_MM_SFT, 1, 1),
1784 };
1785
1786 static const struct snd_kcontrol_new rt5665_out_l_mix[] = {
1787 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_OUT_L_MIXER,
1788 RT5665_M_DAC_L2_OM_L_SFT, 1, 1),
1789 SOC_DAPM_SINGLE("INL Switch", RT5665_OUT_L_MIXER,
1790 RT5665_M_IN_L_OM_L_SFT, 1, 1),
1791 SOC_DAPM_SINGLE("BST1 Switch", RT5665_OUT_L_MIXER,
1792 RT5665_M_BST1_OM_L_SFT, 1, 1),
1793 SOC_DAPM_SINGLE("BST2 Switch", RT5665_OUT_L_MIXER,
1794 RT5665_M_BST2_OM_L_SFT, 1, 1),
1795 SOC_DAPM_SINGLE("BST3 Switch", RT5665_OUT_L_MIXER,
1796 RT5665_M_BST3_OM_L_SFT, 1, 1),
1797 };
1798
1799 static const struct snd_kcontrol_new rt5665_out_r_mix[] = {
1800 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_OUT_R_MIXER,
1801 RT5665_M_DAC_R2_OM_R_SFT, 1, 1),
1802 SOC_DAPM_SINGLE("INR Switch", RT5665_OUT_R_MIXER,
1803 RT5665_M_IN_R_OM_R_SFT, 1, 1),
1804 SOC_DAPM_SINGLE("BST2 Switch", RT5665_OUT_R_MIXER,
1805 RT5665_M_BST2_OM_R_SFT, 1, 1),
1806 SOC_DAPM_SINGLE("BST3 Switch", RT5665_OUT_R_MIXER,
1807 RT5665_M_BST3_OM_R_SFT, 1, 1),
1808 SOC_DAPM_SINGLE("BST4 Switch", RT5665_OUT_R_MIXER,
1809 RT5665_M_BST4_OM_R_SFT, 1, 1),
1810 };
1811
1812 static const struct snd_kcontrol_new rt5665_mono_mix[] = {
1813 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONOMIX_IN_GAIN,
1814 RT5665_M_DAC_L2_MA_SFT, 1, 1),
1815 SOC_DAPM_SINGLE("MONOVOL Switch", RT5665_MONOMIX_IN_GAIN,
1816 RT5665_M_MONOVOL_MA_SFT, 1, 1),
1817 };
1818
1819 static const struct snd_kcontrol_new rt5665_lout_l_mix[] = {
1820 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_LOUT_MIXER,
1821 RT5665_M_DAC_L2_LM_SFT, 1, 1),
1822 SOC_DAPM_SINGLE("OUTVOL L Switch", RT5665_LOUT_MIXER,
1823 RT5665_M_OV_L_LM_SFT, 1, 1),
1824 };
1825
1826 static const struct snd_kcontrol_new rt5665_lout_r_mix[] = {
1827 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_LOUT_MIXER,
1828 RT5665_M_DAC_R2_LM_SFT, 1, 1),
1829 SOC_DAPM_SINGLE("OUTVOL R Switch", RT5665_LOUT_MIXER,
1830 RT5665_M_OV_R_LM_SFT, 1, 1),
1831 };
1832
1833 /*DAC L2, DAC R2*/
1834 /*MX-17 [6:4], MX-17 [2:0]*/
1835 static const char * const rt5665_dac2_src[] = {
1836 "IF1 DAC2", "IF2_1 DAC", "IF2_2 DAC", "IF3 DAC", "Mono ADC MIX"
1837 };
1838
1839 static SOC_ENUM_SINGLE_DECL(
1840 rt5665_dac_l2_enum, RT5665_DAC2_CTRL,
1841 RT5665_DAC_L2_SEL_SFT, rt5665_dac2_src);
1842
1843 static const struct snd_kcontrol_new rt5665_dac_l2_mux =
1844 SOC_DAPM_ENUM("Digital DAC L2 Source", rt5665_dac_l2_enum);
1845
1846 static SOC_ENUM_SINGLE_DECL(
1847 rt5665_dac_r2_enum, RT5665_DAC2_CTRL,
1848 RT5665_DAC_R2_SEL_SFT, rt5665_dac2_src);
1849
1850 static const struct snd_kcontrol_new rt5665_dac_r2_mux =
1851 SOC_DAPM_ENUM("Digital DAC R2 Source", rt5665_dac_r2_enum);
1852
1853 /*DAC L3, DAC R3*/
1854 /*MX-1B [6:4], MX-1B [2:0]*/
1855 static const char * const rt5665_dac3_src[] = {
1856 "IF1 DAC2", "IF2_1 DAC", "IF2_2 DAC", "IF3 DAC", "STO2 ADC MIX"
1857 };
1858
1859 static SOC_ENUM_SINGLE_DECL(
1860 rt5665_dac_l3_enum, RT5665_DAC3_CTRL,
1861 RT5665_DAC_L3_SEL_SFT, rt5665_dac3_src);
1862
1863 static const struct snd_kcontrol_new rt5665_dac_l3_mux =
1864 SOC_DAPM_ENUM("Digital DAC L3 Source", rt5665_dac_l3_enum);
1865
1866 static SOC_ENUM_SINGLE_DECL(
1867 rt5665_dac_r3_enum, RT5665_DAC3_CTRL,
1868 RT5665_DAC_R3_SEL_SFT, rt5665_dac3_src);
1869
1870 static const struct snd_kcontrol_new rt5665_dac_r3_mux =
1871 SOC_DAPM_ENUM("Digital DAC R3 Source", rt5665_dac_r3_enum);
1872
1873 /* STO1 ADC1 Source */
1874 /* MX-26 [13] [5] */
1875 static const char * const rt5665_sto1_adc1_src[] = {
1876 "DD Mux", "ADC"
1877 };
1878
1879 static SOC_ENUM_SINGLE_DECL(
1880 rt5665_sto1_adc1l_enum, RT5665_STO1_ADC_MIXER,
1881 RT5665_STO1_ADC1L_SRC_SFT, rt5665_sto1_adc1_src);
1882
1883 static const struct snd_kcontrol_new rt5665_sto1_adc1l_mux =
1884 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5665_sto1_adc1l_enum);
1885
1886 static SOC_ENUM_SINGLE_DECL(
1887 rt5665_sto1_adc1r_enum, RT5665_STO1_ADC_MIXER,
1888 RT5665_STO1_ADC1R_SRC_SFT, rt5665_sto1_adc1_src);
1889
1890 static const struct snd_kcontrol_new rt5665_sto1_adc1r_mux =
1891 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5665_sto1_adc1r_enum);
1892
1893 /* STO1 ADC Source */
1894 /* MX-26 [11:10] [3:2] */
1895 static const char * const rt5665_sto1_adc_src[] = {
1896 "ADC1 L", "ADC1 R", "ADC2 L", "ADC2 R"
1897 };
1898
1899 static SOC_ENUM_SINGLE_DECL(
1900 rt5665_sto1_adcl_enum, RT5665_STO1_ADC_MIXER,
1901 RT5665_STO1_ADCL_SRC_SFT, rt5665_sto1_adc_src);
1902
1903 static const struct snd_kcontrol_new rt5665_sto1_adcl_mux =
1904 SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5665_sto1_adcl_enum);
1905
1906 static SOC_ENUM_SINGLE_DECL(
1907 rt5665_sto1_adcr_enum, RT5665_STO1_ADC_MIXER,
1908 RT5665_STO1_ADCR_SRC_SFT, rt5665_sto1_adc_src);
1909
1910 static const struct snd_kcontrol_new rt5665_sto1_adcr_mux =
1911 SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5665_sto1_adcr_enum);
1912
1913 /* STO1 ADC2 Source */
1914 /* MX-26 [12] [4] */
1915 static const char * const rt5665_sto1_adc2_src[] = {
1916 "DAC MIX", "DMIC"
1917 };
1918
1919 static SOC_ENUM_SINGLE_DECL(
1920 rt5665_sto1_adc2l_enum, RT5665_STO1_ADC_MIXER,
1921 RT5665_STO1_ADC2L_SRC_SFT, rt5665_sto1_adc2_src);
1922
1923 static const struct snd_kcontrol_new rt5665_sto1_adc2l_mux =
1924 SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5665_sto1_adc2l_enum);
1925
1926 static SOC_ENUM_SINGLE_DECL(
1927 rt5665_sto1_adc2r_enum, RT5665_STO1_ADC_MIXER,
1928 RT5665_STO1_ADC2R_SRC_SFT, rt5665_sto1_adc2_src);
1929
1930 static const struct snd_kcontrol_new rt5665_sto1_adc2r_mux =
1931 SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5665_sto1_adc2r_enum);
1932
1933 /* STO1 DMIC Source */
1934 /* MX-26 [8] */
1935 static const char * const rt5665_sto1_dmic_src[] = {
1936 "DMIC1", "DMIC2"
1937 };
1938
1939 static SOC_ENUM_SINGLE_DECL(
1940 rt5665_sto1_dmic_enum, RT5665_STO1_ADC_MIXER,
1941 RT5665_STO1_DMIC_SRC_SFT, rt5665_sto1_dmic_src);
1942
1943 static const struct snd_kcontrol_new rt5665_sto1_dmic_mux =
1944 SOC_DAPM_ENUM("Stereo1 DMIC Mux", rt5665_sto1_dmic_enum);
1945
1946 /* MX-26 [9] */
1947 static const char * const rt5665_sto1_dd_l_src[] = {
1948 "STO2 DAC", "MONO DAC"
1949 };
1950
1951 static SOC_ENUM_SINGLE_DECL(
1952 rt5665_sto1_dd_l_enum, RT5665_STO1_ADC_MIXER,
1953 RT5665_STO1_DD_L_SRC_SFT, rt5665_sto1_dd_l_src);
1954
1955 static const struct snd_kcontrol_new rt5665_sto1_dd_l_mux =
1956 SOC_DAPM_ENUM("Stereo1 DD L Source", rt5665_sto1_dd_l_enum);
1957
1958 /* MX-26 [1:0] */
1959 static const char * const rt5665_sto1_dd_r_src[] = {
1960 "STO2 DAC", "MONO DAC", "AEC REF"
1961 };
1962
1963 static SOC_ENUM_SINGLE_DECL(
1964 rt5665_sto1_dd_r_enum, RT5665_STO1_ADC_MIXER,
1965 RT5665_STO1_DD_R_SRC_SFT, rt5665_sto1_dd_r_src);
1966
1967 static const struct snd_kcontrol_new rt5665_sto1_dd_r_mux =
1968 SOC_DAPM_ENUM("Stereo1 DD R Source", rt5665_sto1_dd_r_enum);
1969
1970 /* MONO ADC L2 Source */
1971 /* MX-27 [12] */
1972 static const char * const rt5665_mono_adc_l2_src[] = {
1973 "DAC MIXL", "DMIC"
1974 };
1975
1976 static SOC_ENUM_SINGLE_DECL(
1977 rt5665_mono_adc_l2_enum, RT5665_MONO_ADC_MIXER,
1978 RT5665_MONO_ADC_L2_SRC_SFT, rt5665_mono_adc_l2_src);
1979
1980 static const struct snd_kcontrol_new rt5665_mono_adc_l2_mux =
1981 SOC_DAPM_ENUM("Mono ADC L2 Source", rt5665_mono_adc_l2_enum);
1982
1983
1984 /* MONO ADC L1 Source */
1985 /* MX-27 [13] */
1986 static const char * const rt5665_mono_adc_l1_src[] = {
1987 "DD Mux", "ADC"
1988 };
1989
1990 static SOC_ENUM_SINGLE_DECL(
1991 rt5665_mono_adc_l1_enum, RT5665_MONO_ADC_MIXER,
1992 RT5665_MONO_ADC_L1_SRC_SFT, rt5665_mono_adc_l1_src);
1993
1994 static const struct snd_kcontrol_new rt5665_mono_adc_l1_mux =
1995 SOC_DAPM_ENUM("Mono ADC L1 Source", rt5665_mono_adc_l1_enum);
1996
1997 /* MX-27 [9][1]*/
1998 static const char * const rt5665_mono_dd_src[] = {
1999 "STO2 DAC", "MONO DAC"
2000 };
2001
2002 static SOC_ENUM_SINGLE_DECL(
2003 rt5665_mono_dd_l_enum, RT5665_MONO_ADC_MIXER,
2004 RT5665_MONO_DD_L_SRC_SFT, rt5665_mono_dd_src);
2005
2006 static const struct snd_kcontrol_new rt5665_mono_dd_l_mux =
2007 SOC_DAPM_ENUM("Mono DD L Source", rt5665_mono_dd_l_enum);
2008
2009 static SOC_ENUM_SINGLE_DECL(
2010 rt5665_mono_dd_r_enum, RT5665_MONO_ADC_MIXER,
2011 RT5665_MONO_DD_R_SRC_SFT, rt5665_mono_dd_src);
2012
2013 static const struct snd_kcontrol_new rt5665_mono_dd_r_mux =
2014 SOC_DAPM_ENUM("Mono DD R Source", rt5665_mono_dd_r_enum);
2015
2016 /* MONO ADC L Source, MONO ADC R Source*/
2017 /* MX-27 [11:10], MX-27 [3:2] */
2018 static const char * const rt5665_mono_adc_src[] = {
2019 "ADC1 L", "ADC1 R", "ADC2 L", "ADC2 R"
2020 };
2021
2022 static SOC_ENUM_SINGLE_DECL(
2023 rt5665_mono_adc_l_enum, RT5665_MONO_ADC_MIXER,
2024 RT5665_MONO_ADC_L_SRC_SFT, rt5665_mono_adc_src);
2025
2026 static const struct snd_kcontrol_new rt5665_mono_adc_l_mux =
2027 SOC_DAPM_ENUM("Mono ADC L Source", rt5665_mono_adc_l_enum);
2028
2029 static SOC_ENUM_SINGLE_DECL(
2030 rt5665_mono_adcr_enum, RT5665_MONO_ADC_MIXER,
2031 RT5665_MONO_ADC_R_SRC_SFT, rt5665_mono_adc_src);
2032
2033 static const struct snd_kcontrol_new rt5665_mono_adc_r_mux =
2034 SOC_DAPM_ENUM("Mono ADC R Source", rt5665_mono_adcr_enum);
2035
2036 /* MONO DMIC L Source */
2037 /* MX-27 [8] */
2038 static const char * const rt5665_mono_dmic_l_src[] = {
2039 "DMIC1 L", "DMIC2 L"
2040 };
2041
2042 static SOC_ENUM_SINGLE_DECL(
2043 rt5665_mono_dmic_l_enum, RT5665_MONO_ADC_MIXER,
2044 RT5665_MONO_DMIC_L_SRC_SFT, rt5665_mono_dmic_l_src);
2045
2046 static const struct snd_kcontrol_new rt5665_mono_dmic_l_mux =
2047 SOC_DAPM_ENUM("Mono DMIC L Source", rt5665_mono_dmic_l_enum);
2048
2049 /* MONO ADC R2 Source */
2050 /* MX-27 [4] */
2051 static const char * const rt5665_mono_adc_r2_src[] = {
2052 "DAC MIXR", "DMIC"
2053 };
2054
2055 static SOC_ENUM_SINGLE_DECL(
2056 rt5665_mono_adc_r2_enum, RT5665_MONO_ADC_MIXER,
2057 RT5665_MONO_ADC_R2_SRC_SFT, rt5665_mono_adc_r2_src);
2058
2059 static const struct snd_kcontrol_new rt5665_mono_adc_r2_mux =
2060 SOC_DAPM_ENUM("Mono ADC R2 Source", rt5665_mono_adc_r2_enum);
2061
2062 /* MONO ADC R1 Source */
2063 /* MX-27 [5] */
2064 static const char * const rt5665_mono_adc_r1_src[] = {
2065 "DD Mux", "ADC"
2066 };
2067
2068 static SOC_ENUM_SINGLE_DECL(
2069 rt5665_mono_adc_r1_enum, RT5665_MONO_ADC_MIXER,
2070 RT5665_MONO_ADC_R1_SRC_SFT, rt5665_mono_adc_r1_src);
2071
2072 static const struct snd_kcontrol_new rt5665_mono_adc_r1_mux =
2073 SOC_DAPM_ENUM("Mono ADC R1 Source", rt5665_mono_adc_r1_enum);
2074
2075 /* MONO DMIC R Source */
2076 /* MX-27 [0] */
2077 static const char * const rt5665_mono_dmic_r_src[] = {
2078 "DMIC1 R", "DMIC2 R"
2079 };
2080
2081 static SOC_ENUM_SINGLE_DECL(
2082 rt5665_mono_dmic_r_enum, RT5665_MONO_ADC_MIXER,
2083 RT5665_MONO_DMIC_R_SRC_SFT, rt5665_mono_dmic_r_src);
2084
2085 static const struct snd_kcontrol_new rt5665_mono_dmic_r_mux =
2086 SOC_DAPM_ENUM("Mono DMIC R Source", rt5665_mono_dmic_r_enum);
2087
2088
2089 /* STO2 ADC1 Source */
2090 /* MX-28 [13] [5] */
2091 static const char * const rt5665_sto2_adc1_src[] = {
2092 "DD Mux", "ADC"
2093 };
2094
2095 static SOC_ENUM_SINGLE_DECL(
2096 rt5665_sto2_adc1l_enum, RT5665_STO2_ADC_MIXER,
2097 RT5665_STO2_ADC1L_SRC_SFT, rt5665_sto2_adc1_src);
2098
2099 static const struct snd_kcontrol_new rt5665_sto2_adc1l_mux =
2100 SOC_DAPM_ENUM("Stereo2 ADC1L Source", rt5665_sto2_adc1l_enum);
2101
2102 static SOC_ENUM_SINGLE_DECL(
2103 rt5665_sto2_adc1r_enum, RT5665_STO2_ADC_MIXER,
2104 RT5665_STO2_ADC1R_SRC_SFT, rt5665_sto2_adc1_src);
2105
2106 static const struct snd_kcontrol_new rt5665_sto2_adc1r_mux =
2107 SOC_DAPM_ENUM("Stereo2 ADC1L Source", rt5665_sto2_adc1r_enum);
2108
2109 /* STO2 ADC Source */
2110 /* MX-28 [11:10] [3:2] */
2111 static const char * const rt5665_sto2_adc_src[] = {
2112 "ADC1 L", "ADC1 R", "ADC2 L"
2113 };
2114
2115 static SOC_ENUM_SINGLE_DECL(
2116 rt5665_sto2_adcl_enum, RT5665_STO2_ADC_MIXER,
2117 RT5665_STO2_ADCL_SRC_SFT, rt5665_sto2_adc_src);
2118
2119 static const struct snd_kcontrol_new rt5665_sto2_adcl_mux =
2120 SOC_DAPM_ENUM("Stereo2 ADCL Source", rt5665_sto2_adcl_enum);
2121
2122 static SOC_ENUM_SINGLE_DECL(
2123 rt5665_sto2_adcr_enum, RT5665_STO2_ADC_MIXER,
2124 RT5665_STO2_ADCR_SRC_SFT, rt5665_sto2_adc_src);
2125
2126 static const struct snd_kcontrol_new rt5665_sto2_adcr_mux =
2127 SOC_DAPM_ENUM("Stereo2 ADCR Source", rt5665_sto2_adcr_enum);
2128
2129 /* STO2 ADC2 Source */
2130 /* MX-28 [12] [4] */
2131 static const char * const rt5665_sto2_adc2_src[] = {
2132 "DAC MIX", "DMIC"
2133 };
2134
2135 static SOC_ENUM_SINGLE_DECL(
2136 rt5665_sto2_adc2l_enum, RT5665_STO2_ADC_MIXER,
2137 RT5665_STO2_ADC2L_SRC_SFT, rt5665_sto2_adc2_src);
2138
2139 static const struct snd_kcontrol_new rt5665_sto2_adc2l_mux =
2140 SOC_DAPM_ENUM("Stereo2 ADC2L Source", rt5665_sto2_adc2l_enum);
2141
2142 static SOC_ENUM_SINGLE_DECL(
2143 rt5665_sto2_adc2r_enum, RT5665_STO2_ADC_MIXER,
2144 RT5665_STO2_ADC2R_SRC_SFT, rt5665_sto2_adc2_src);
2145
2146 static const struct snd_kcontrol_new rt5665_sto2_adc2r_mux =
2147 SOC_DAPM_ENUM("Stereo2 ADC2R Source", rt5665_sto2_adc2r_enum);
2148
2149 /* STO2 DMIC Source */
2150 /* MX-28 [8] */
2151 static const char * const rt5665_sto2_dmic_src[] = {
2152 "DMIC1", "DMIC2"
2153 };
2154
2155 static SOC_ENUM_SINGLE_DECL(
2156 rt5665_sto2_dmic_enum, RT5665_STO2_ADC_MIXER,
2157 RT5665_STO2_DMIC_SRC_SFT, rt5665_sto2_dmic_src);
2158
2159 static const struct snd_kcontrol_new rt5665_sto2_dmic_mux =
2160 SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5665_sto2_dmic_enum);
2161
2162 /* MX-28 [9] */
2163 static const char * const rt5665_sto2_dd_l_src[] = {
2164 "STO2 DAC", "MONO DAC"
2165 };
2166
2167 static SOC_ENUM_SINGLE_DECL(
2168 rt5665_sto2_dd_l_enum, RT5665_STO2_ADC_MIXER,
2169 RT5665_STO2_DD_L_SRC_SFT, rt5665_sto2_dd_l_src);
2170
2171 static const struct snd_kcontrol_new rt5665_sto2_dd_l_mux =
2172 SOC_DAPM_ENUM("Stereo2 DD L Source", rt5665_sto2_dd_l_enum);
2173
2174 /* MX-28 [1] */
2175 static const char * const rt5665_sto2_dd_r_src[] = {
2176 "STO2 DAC", "MONO DAC"
2177 };
2178
2179 static SOC_ENUM_SINGLE_DECL(
2180 rt5665_sto2_dd_r_enum, RT5665_STO2_ADC_MIXER,
2181 RT5665_STO2_DD_R_SRC_SFT, rt5665_sto2_dd_r_src);
2182
2183 static const struct snd_kcontrol_new rt5665_sto2_dd_r_mux =
2184 SOC_DAPM_ENUM("Stereo2 DD R Source", rt5665_sto2_dd_r_enum);
2185
2186 /* DAC R1 Source, DAC L1 Source*/
2187 /* MX-29 [11:10], MX-29 [9:8]*/
2188 static const char * const rt5665_dac1_src[] = {
2189 "IF1 DAC1", "IF2_1 DAC", "IF2_2 DAC", "IF3 DAC"
2190 };
2191
2192 static SOC_ENUM_SINGLE_DECL(
2193 rt5665_dac_r1_enum, RT5665_AD_DA_MIXER,
2194 RT5665_DAC1_R_SEL_SFT, rt5665_dac1_src);
2195
2196 static const struct snd_kcontrol_new rt5665_dac_r1_mux =
2197 SOC_DAPM_ENUM("DAC R1 Source", rt5665_dac_r1_enum);
2198
2199 static SOC_ENUM_SINGLE_DECL(
2200 rt5665_dac_l1_enum, RT5665_AD_DA_MIXER,
2201 RT5665_DAC1_L_SEL_SFT, rt5665_dac1_src);
2202
2203 static const struct snd_kcontrol_new rt5665_dac_l1_mux =
2204 SOC_DAPM_ENUM("DAC L1 Source", rt5665_dac_l1_enum);
2205
2206 /* DAC Digital Mixer L Source, DAC Digital Mixer R Source*/
2207 /* MX-2D [13:12], MX-2D [9:8]*/
2208 static const char * const rt5665_dig_dac_mix_src[] = {
2209 "Stereo1 DAC Mixer", "Stereo2 DAC Mixer", "Mono DAC Mixer"
2210 };
2211
2212 static SOC_ENUM_SINGLE_DECL(
2213 rt5665_dig_dac_mixl_enum, RT5665_A_DAC1_MUX,
2214 RT5665_DAC_MIX_L_SFT, rt5665_dig_dac_mix_src);
2215
2216 static const struct snd_kcontrol_new rt5665_dig_dac_mixl_mux =
2217 SOC_DAPM_ENUM("DAC Digital Mixer L Source", rt5665_dig_dac_mixl_enum);
2218
2219 static SOC_ENUM_SINGLE_DECL(
2220 rt5665_dig_dac_mixr_enum, RT5665_A_DAC1_MUX,
2221 RT5665_DAC_MIX_R_SFT, rt5665_dig_dac_mix_src);
2222
2223 static const struct snd_kcontrol_new rt5665_dig_dac_mixr_mux =
2224 SOC_DAPM_ENUM("DAC Digital Mixer R Source", rt5665_dig_dac_mixr_enum);
2225
2226 /* Analog DAC L1 Source, Analog DAC R1 Source*/
2227 /* MX-2D [5:4], MX-2D [1:0]*/
2228 static const char * const rt5665_alg_dac1_src[] = {
2229 "Stereo1 DAC Mixer", "DAC1", "DMIC1"
2230 };
2231
2232 static SOC_ENUM_SINGLE_DECL(
2233 rt5665_alg_dac_l1_enum, RT5665_A_DAC1_MUX,
2234 RT5665_A_DACL1_SFT, rt5665_alg_dac1_src);
2235
2236 static const struct snd_kcontrol_new rt5665_alg_dac_l1_mux =
2237 SOC_DAPM_ENUM("Analog DAC L1 Source", rt5665_alg_dac_l1_enum);
2238
2239 static SOC_ENUM_SINGLE_DECL(
2240 rt5665_alg_dac_r1_enum, RT5665_A_DAC1_MUX,
2241 RT5665_A_DACR1_SFT, rt5665_alg_dac1_src);
2242
2243 static const struct snd_kcontrol_new rt5665_alg_dac_r1_mux =
2244 SOC_DAPM_ENUM("Analog DAC R1 Source", rt5665_alg_dac_r1_enum);
2245
2246 /* Analog DAC LR Source, Analog DAC R2 Source*/
2247 /* MX-2E [5:4], MX-2E [0]*/
2248 static const char * const rt5665_alg_dac2_src[] = {
2249 "Mono DAC Mixer", "DAC2"
2250 };
2251
2252 static SOC_ENUM_SINGLE_DECL(
2253 rt5665_alg_dac_l2_enum, RT5665_A_DAC2_MUX,
2254 RT5665_A_DACL2_SFT, rt5665_alg_dac2_src);
2255
2256 static const struct snd_kcontrol_new rt5665_alg_dac_l2_mux =
2257 SOC_DAPM_ENUM("Analog DAC L2 Source", rt5665_alg_dac_l2_enum);
2258
2259 static SOC_ENUM_SINGLE_DECL(
2260 rt5665_alg_dac_r2_enum, RT5665_A_DAC2_MUX,
2261 RT5665_A_DACR2_SFT, rt5665_alg_dac2_src);
2262
2263 static const struct snd_kcontrol_new rt5665_alg_dac_r2_mux =
2264 SOC_DAPM_ENUM("Analog DAC R2 Source", rt5665_alg_dac_r2_enum);
2265
2266 /* Interface2 ADC Data Input*/
2267 /* MX-2F [14:12] */
2268 static const char * const rt5665_if2_1_adc_in_src[] = {
2269 "STO1 ADC", "STO2 ADC", "MONO ADC", "IF1 DAC1",
2270 "IF1 DAC2", "IF2_2 DAC", "IF3 DAC", "DAC1 MIX"
2271 };
2272
2273 static SOC_ENUM_SINGLE_DECL(
2274 rt5665_if2_1_adc_in_enum, RT5665_DIG_INF2_DATA,
2275 RT5665_IF2_1_ADC_IN_SFT, rt5665_if2_1_adc_in_src);
2276
2277 static const struct snd_kcontrol_new rt5665_if2_1_adc_in_mux =
2278 SOC_DAPM_ENUM("IF2_1 ADC IN Source", rt5665_if2_1_adc_in_enum);
2279
2280 /* MX-2F [6:4] */
2281 static const char * const rt5665_if2_2_adc_in_src[] = {
2282 "STO1 ADC", "STO2 ADC", "MONO ADC", "IF1 DAC1",
2283 "IF1 DAC2", "IF2_1 DAC", "IF3 DAC", "DAC1 MIX"
2284 };
2285
2286 static SOC_ENUM_SINGLE_DECL(
2287 rt5665_if2_2_adc_in_enum, RT5665_DIG_INF2_DATA,
2288 RT5665_IF2_2_ADC_IN_SFT, rt5665_if2_2_adc_in_src);
2289
2290 static const struct snd_kcontrol_new rt5665_if2_2_adc_in_mux =
2291 SOC_DAPM_ENUM("IF2_1 ADC IN Source", rt5665_if2_2_adc_in_enum);
2292
2293 /* Interface3 ADC Data Input*/
2294 /* MX-30 [6:4] */
2295 static const char * const rt5665_if3_adc_in_src[] = {
2296 "STO1 ADC", "STO2 ADC", "MONO ADC", "IF1 DAC1",
2297 "IF1 DAC2", "IF2_1 DAC", "IF2_2 DAC", "DAC1 MIX"
2298 };
2299
2300 static SOC_ENUM_SINGLE_DECL(
2301 rt5665_if3_adc_in_enum, RT5665_DIG_INF3_DATA,
2302 RT5665_IF3_ADC_IN_SFT, rt5665_if3_adc_in_src);
2303
2304 static const struct snd_kcontrol_new rt5665_if3_adc_in_mux =
2305 SOC_DAPM_ENUM("IF3 ADC IN Source", rt5665_if3_adc_in_enum);
2306
2307 /* PDM 1 L/R*/
2308 /* MX-31 [11:10] [9:8] */
2309 static const char * const rt5665_pdm_src[] = {
2310 "Stereo1 DAC", "Stereo2 DAC", "Mono DAC"
2311 };
2312
2313 static SOC_ENUM_SINGLE_DECL(
2314 rt5665_pdm_l_enum, RT5665_PDM_OUT_CTRL,
2315 RT5665_PDM1_L_SFT, rt5665_pdm_src);
2316
2317 static const struct snd_kcontrol_new rt5665_pdm_l_mux =
2318 SOC_DAPM_ENUM("PDM L Source", rt5665_pdm_l_enum);
2319
2320 static SOC_ENUM_SINGLE_DECL(
2321 rt5665_pdm_r_enum, RT5665_PDM_OUT_CTRL,
2322 RT5665_PDM1_R_SFT, rt5665_pdm_src);
2323
2324 static const struct snd_kcontrol_new rt5665_pdm_r_mux =
2325 SOC_DAPM_ENUM("PDM R Source", rt5665_pdm_r_enum);
2326
2327
2328 /* I2S1 TDM ADCDAT Source */
2329 /* MX-7a[10] */
2330 static const char * const rt5665_if1_1_adc1_data_src[] = {
2331 "STO1 ADC", "IF2_1 DAC",
2332 };
2333
2334 static SOC_ENUM_SINGLE_DECL(
2335 rt5665_if1_1_adc1_data_enum, RT5665_TDM_CTRL_3,
2336 RT5665_IF1_ADC1_SEL_SFT, rt5665_if1_1_adc1_data_src);
2337
2338 static const struct snd_kcontrol_new rt5665_if1_1_adc1_mux =
2339 SOC_DAPM_ENUM("IF1_1 ADC1 Source", rt5665_if1_1_adc1_data_enum);
2340
2341 /* MX-7a[9] */
2342 static const char * const rt5665_if1_1_adc2_data_src[] = {
2343 "STO2 ADC", "IF2_2 DAC",
2344 };
2345
2346 static SOC_ENUM_SINGLE_DECL(
2347 rt5665_if1_1_adc2_data_enum, RT5665_TDM_CTRL_3,
2348 RT5665_IF1_ADC2_SEL_SFT, rt5665_if1_1_adc2_data_src);
2349
2350 static const struct snd_kcontrol_new rt5665_if1_1_adc2_mux =
2351 SOC_DAPM_ENUM("IF1_1 ADC2 Source", rt5665_if1_1_adc2_data_enum);
2352
2353 /* MX-7a[8] */
2354 static const char * const rt5665_if1_1_adc3_data_src[] = {
2355 "MONO ADC", "IF3 DAC",
2356 };
2357
2358 static SOC_ENUM_SINGLE_DECL(
2359 rt5665_if1_1_adc3_data_enum, RT5665_TDM_CTRL_3,
2360 RT5665_IF1_ADC3_SEL_SFT, rt5665_if1_1_adc3_data_src);
2361
2362 static const struct snd_kcontrol_new rt5665_if1_1_adc3_mux =
2363 SOC_DAPM_ENUM("IF1_1 ADC3 Source", rt5665_if1_1_adc3_data_enum);
2364
2365 /* MX-7b[10] */
2366 static const char * const rt5665_if1_2_adc1_data_src[] = {
2367 "STO1 ADC", "IF1 DAC",
2368 };
2369
2370 static SOC_ENUM_SINGLE_DECL(
2371 rt5665_if1_2_adc1_data_enum, RT5665_TDM_CTRL_4,
2372 RT5665_IF1_ADC1_SEL_SFT, rt5665_if1_2_adc1_data_src);
2373
2374 static const struct snd_kcontrol_new rt5665_if1_2_adc1_mux =
2375 SOC_DAPM_ENUM("IF1_2 ADC1 Source", rt5665_if1_2_adc1_data_enum);
2376
2377 /* MX-7b[9] */
2378 static const char * const rt5665_if1_2_adc2_data_src[] = {
2379 "STO2 ADC", "IF2_1 DAC",
2380 };
2381
2382 static SOC_ENUM_SINGLE_DECL(
2383 rt5665_if1_2_adc2_data_enum, RT5665_TDM_CTRL_4,
2384 RT5665_IF1_ADC2_SEL_SFT, rt5665_if1_2_adc2_data_src);
2385
2386 static const struct snd_kcontrol_new rt5665_if1_2_adc2_mux =
2387 SOC_DAPM_ENUM("IF1_2 ADC2 Source", rt5665_if1_2_adc2_data_enum);
2388
2389 /* MX-7b[8] */
2390 static const char * const rt5665_if1_2_adc3_data_src[] = {
2391 "MONO ADC", "IF2_2 DAC",
2392 };
2393
2394 static SOC_ENUM_SINGLE_DECL(
2395 rt5665_if1_2_adc3_data_enum, RT5665_TDM_CTRL_4,
2396 RT5665_IF1_ADC3_SEL_SFT, rt5665_if1_2_adc3_data_src);
2397
2398 static const struct snd_kcontrol_new rt5665_if1_2_adc3_mux =
2399 SOC_DAPM_ENUM("IF1_2 ADC3 Source", rt5665_if1_2_adc3_data_enum);
2400
2401 /* MX-7b[7] */
2402 static const char * const rt5665_if1_2_adc4_data_src[] = {
2403 "DAC1", "IF3 DAC",
2404 };
2405
2406 static SOC_ENUM_SINGLE_DECL(
2407 rt5665_if1_2_adc4_data_enum, RT5665_TDM_CTRL_4,
2408 RT5665_IF1_ADC4_SEL_SFT, rt5665_if1_2_adc4_data_src);
2409
2410 static const struct snd_kcontrol_new rt5665_if1_2_adc4_mux =
2411 SOC_DAPM_ENUM("IF1_2 ADC4 Source", rt5665_if1_2_adc4_data_enum);
2412
2413 /* MX-7a[4:0] MX-7b[4:0] */
2414 static const char * const rt5665_tdm_adc_data_src[] = {
2415 "1234", "1243", "1324", "1342", "1432", "1423",
2416 "2134", "2143", "2314", "2341", "2431", "2413",
2417 "3124", "3142", "3214", "3241", "3412", "3421",
2418 "4123", "4132", "4213", "4231", "4312", "4321"
2419 };
2420
2421 static SOC_ENUM_SINGLE_DECL(
2422 rt5665_tdm1_adc_data_enum, RT5665_TDM_CTRL_3,
2423 RT5665_TDM_ADC_SEL_SFT, rt5665_tdm_adc_data_src);
2424
2425 static const struct snd_kcontrol_new rt5665_tdm1_adc_mux =
2426 SOC_DAPM_ENUM("TDM1 ADC Mux", rt5665_tdm1_adc_data_enum);
2427
2428 static SOC_ENUM_SINGLE_DECL(
2429 rt5665_tdm2_adc_data_enum, RT5665_TDM_CTRL_4,
2430 RT5665_TDM_ADC_SEL_SFT, rt5665_tdm_adc_data_src);
2431
2432 static const struct snd_kcontrol_new rt5665_tdm2_adc_mux =
2433 SOC_DAPM_ENUM("TDM2 ADCDAT Source", rt5665_tdm2_adc_data_enum);
2434
2435 /* Out Volume Switch */
2436 static const struct snd_kcontrol_new monovol_switch =
2437 SOC_DAPM_SINGLE("Switch", RT5665_MONO_OUT, RT5665_VOL_L_SFT, 1, 1);
2438
2439 static const struct snd_kcontrol_new outvol_l_switch =
2440 SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_VOL_L_SFT, 1, 1);
2441
2442 static const struct snd_kcontrol_new outvol_r_switch =
2443 SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_VOL_R_SFT, 1, 1);
2444
2445 /* Out Switch */
2446 static const struct snd_kcontrol_new mono_switch =
2447 SOC_DAPM_SINGLE("Switch", RT5665_MONO_OUT, RT5665_L_MUTE_SFT, 1, 1);
2448
2449 static const struct snd_kcontrol_new hpo_switch =
2450 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5665_HP_CTRL_2,
2451 RT5665_VOL_L_SFT, 1, 0);
2452
2453 static const struct snd_kcontrol_new lout_l_switch =
2454 SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_L_MUTE_SFT, 1, 1);
2455
2456 static const struct snd_kcontrol_new lout_r_switch =
2457 SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_R_MUTE_SFT, 1, 1);
2458
2459 static const struct snd_kcontrol_new pdm_l_switch =
2460 SOC_DAPM_SINGLE("Switch", RT5665_PDM_OUT_CTRL,
2461 RT5665_M_PDM1_L_SFT, 1, 1);
2462
2463 static const struct snd_kcontrol_new pdm_r_switch =
2464 SOC_DAPM_SINGLE("Switch", RT5665_PDM_OUT_CTRL,
2465 RT5665_M_PDM1_R_SFT, 1, 1);
2466
rt5665_mono_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)2467 static int rt5665_mono_event(struct snd_soc_dapm_widget *w,
2468 struct snd_kcontrol *kcontrol, int event)
2469 {
2470 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2471
2472 switch (event) {
2473 case SND_SOC_DAPM_PRE_PMU:
2474 snd_soc_component_update_bits(component, RT5665_MONO_NG2_CTRL_1,
2475 RT5665_NG2_EN_MASK, RT5665_NG2_EN);
2476 snd_soc_component_update_bits(component, RT5665_MONO_AMP_CALIB_CTRL_1, 0x40,
2477 0x0);
2478 snd_soc_component_update_bits(component, RT5665_MONO_OUT, 0x10, 0x10);
2479 snd_soc_component_update_bits(component, RT5665_MONO_OUT, 0x20, 0x20);
2480 break;
2481
2482 case SND_SOC_DAPM_POST_PMD:
2483 snd_soc_component_update_bits(component, RT5665_MONO_OUT, 0x20, 0);
2484 snd_soc_component_update_bits(component, RT5665_MONO_OUT, 0x10, 0);
2485 snd_soc_component_update_bits(component, RT5665_MONO_AMP_CALIB_CTRL_1, 0x40,
2486 0x40);
2487 snd_soc_component_update_bits(component, RT5665_MONO_NG2_CTRL_1,
2488 RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
2489 break;
2490
2491 default:
2492 return 0;
2493 }
2494
2495 return 0;
2496
2497 }
2498
rt5665_hp_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)2499 static int rt5665_hp_event(struct snd_soc_dapm_widget *w,
2500 struct snd_kcontrol *kcontrol, int event)
2501 {
2502 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2503
2504 switch (event) {
2505 case SND_SOC_DAPM_PRE_PMU:
2506 snd_soc_component_update_bits(component, RT5665_STO_NG2_CTRL_1,
2507 RT5665_NG2_EN_MASK, RT5665_NG2_EN);
2508 snd_soc_component_write(component, RT5665_HP_LOGIC_CTRL_2, 0x0003);
2509 break;
2510
2511 case SND_SOC_DAPM_POST_PMD:
2512 snd_soc_component_write(component, RT5665_HP_LOGIC_CTRL_2, 0x0002);
2513 snd_soc_component_update_bits(component, RT5665_STO_NG2_CTRL_1,
2514 RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
2515 break;
2516
2517 default:
2518 return 0;
2519 }
2520
2521 return 0;
2522
2523 }
2524
rt5665_lout_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)2525 static int rt5665_lout_event(struct snd_soc_dapm_widget *w,
2526 struct snd_kcontrol *kcontrol, int event)
2527 {
2528 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2529
2530 switch (event) {
2531 case SND_SOC_DAPM_POST_PMU:
2532 snd_soc_component_update_bits(component, RT5665_DEPOP_1,
2533 RT5665_PUMP_EN, RT5665_PUMP_EN);
2534 break;
2535
2536 case SND_SOC_DAPM_PRE_PMD:
2537 snd_soc_component_update_bits(component, RT5665_DEPOP_1,
2538 RT5665_PUMP_EN, 0);
2539 break;
2540
2541 default:
2542 return 0;
2543 }
2544
2545 return 0;
2546
2547 }
2548
set_dmic_power(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)2549 static int set_dmic_power(struct snd_soc_dapm_widget *w,
2550 struct snd_kcontrol *kcontrol, int event)
2551 {
2552 switch (event) {
2553 case SND_SOC_DAPM_POST_PMU:
2554 /*Add delay to avoid pop noise*/
2555 msleep(150);
2556 break;
2557
2558 default:
2559 return 0;
2560 }
2561
2562 return 0;
2563 }
2564
rt5665_set_verf(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)2565 static int rt5665_set_verf(struct snd_soc_dapm_widget *w,
2566 struct snd_kcontrol *kcontrol, int event)
2567 {
2568 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2569
2570 switch (event) {
2571 case SND_SOC_DAPM_PRE_PMU:
2572 switch (w->shift) {
2573 case RT5665_PWR_VREF1_BIT:
2574 snd_soc_component_update_bits(component, RT5665_PWR_ANLG_1,
2575 RT5665_PWR_FV1, 0);
2576 break;
2577
2578 case RT5665_PWR_VREF2_BIT:
2579 snd_soc_component_update_bits(component, RT5665_PWR_ANLG_1,
2580 RT5665_PWR_FV2, 0);
2581 break;
2582
2583 case RT5665_PWR_VREF3_BIT:
2584 snd_soc_component_update_bits(component, RT5665_PWR_ANLG_1,
2585 RT5665_PWR_FV3, 0);
2586 break;
2587
2588 default:
2589 break;
2590 }
2591 break;
2592
2593 case SND_SOC_DAPM_POST_PMU:
2594 usleep_range(15000, 20000);
2595 switch (w->shift) {
2596 case RT5665_PWR_VREF1_BIT:
2597 snd_soc_component_update_bits(component, RT5665_PWR_ANLG_1,
2598 RT5665_PWR_FV1, RT5665_PWR_FV1);
2599 break;
2600
2601 case RT5665_PWR_VREF2_BIT:
2602 snd_soc_component_update_bits(component, RT5665_PWR_ANLG_1,
2603 RT5665_PWR_FV2, RT5665_PWR_FV2);
2604 break;
2605
2606 case RT5665_PWR_VREF3_BIT:
2607 snd_soc_component_update_bits(component, RT5665_PWR_ANLG_1,
2608 RT5665_PWR_FV3, RT5665_PWR_FV3);
2609 break;
2610
2611 default:
2612 break;
2613 }
2614 break;
2615
2616 default:
2617 return 0;
2618 }
2619
2620 return 0;
2621 }
2622
rt5665_i2s_pin_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)2623 static int rt5665_i2s_pin_event(struct snd_soc_dapm_widget *w,
2624 struct snd_kcontrol *kcontrol, int event)
2625 {
2626 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2627 unsigned int val1, val2, mask1 = 0, mask2 = 0;
2628
2629 switch (w->shift) {
2630 case RT5665_PWR_I2S2_1_BIT:
2631 mask1 = RT5665_GP2_PIN_MASK | RT5665_GP3_PIN_MASK |
2632 RT5665_GP4_PIN_MASK | RT5665_GP5_PIN_MASK;
2633 val1 = RT5665_GP2_PIN_BCLK2 | RT5665_GP3_PIN_LRCK2 |
2634 RT5665_GP4_PIN_DACDAT2_1 | RT5665_GP5_PIN_ADCDAT2_1;
2635 break;
2636 case RT5665_PWR_I2S2_2_BIT:
2637 mask1 = RT5665_GP2_PIN_MASK | RT5665_GP3_PIN_MASK |
2638 RT5665_GP8_PIN_MASK;
2639 val1 = RT5665_GP2_PIN_BCLK2 | RT5665_GP3_PIN_LRCK2 |
2640 RT5665_GP8_PIN_DACDAT2_2;
2641 mask2 = RT5665_GP9_PIN_MASK;
2642 val2 = RT5665_GP9_PIN_ADCDAT2_2;
2643 break;
2644 case RT5665_PWR_I2S3_BIT:
2645 mask1 = RT5665_GP6_PIN_MASK | RT5665_GP7_PIN_MASK |
2646 RT5665_GP8_PIN_MASK;
2647 val1 = RT5665_GP6_PIN_BCLK3 | RT5665_GP7_PIN_LRCK3 |
2648 RT5665_GP8_PIN_DACDAT3;
2649 mask2 = RT5665_GP9_PIN_MASK;
2650 val2 = RT5665_GP9_PIN_ADCDAT3;
2651 break;
2652 }
2653 switch (event) {
2654 case SND_SOC_DAPM_PRE_PMU:
2655 if (mask1)
2656 snd_soc_component_update_bits(component, RT5665_GPIO_CTRL_1,
2657 mask1, val1);
2658 if (mask2)
2659 snd_soc_component_update_bits(component, RT5665_GPIO_CTRL_2,
2660 mask2, val2);
2661 break;
2662 case SND_SOC_DAPM_POST_PMD:
2663 if (mask1)
2664 snd_soc_component_update_bits(component, RT5665_GPIO_CTRL_1,
2665 mask1, 0);
2666 if (mask2)
2667 snd_soc_component_update_bits(component, RT5665_GPIO_CTRL_2,
2668 mask2, 0);
2669 break;
2670 default:
2671 return 0;
2672 }
2673
2674 return 0;
2675 }
2676
2677 static const struct snd_soc_dapm_widget rt5665_dapm_widgets[] = {
2678 SND_SOC_DAPM_SUPPLY("LDO2", RT5665_PWR_ANLG_3, RT5665_PWR_LDO2_BIT, 0,
2679 NULL, 0),
2680 SND_SOC_DAPM_SUPPLY("PLL", RT5665_PWR_ANLG_3, RT5665_PWR_PLL_BIT, 0,
2681 NULL, 0),
2682 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5665_PWR_VOL,
2683 RT5665_PWR_MIC_DET_BIT, 0, NULL, 0),
2684 SND_SOC_DAPM_SUPPLY("Vref1", RT5665_PWR_ANLG_1, RT5665_PWR_VREF1_BIT, 0,
2685 rt5665_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
2686 SND_SOC_DAPM_SUPPLY("Vref2", RT5665_PWR_ANLG_1, RT5665_PWR_VREF2_BIT, 0,
2687 rt5665_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
2688 SND_SOC_DAPM_SUPPLY("Vref3", RT5665_PWR_ANLG_1, RT5665_PWR_VREF3_BIT, 0,
2689 rt5665_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
2690
2691 /* ASRC */
2692 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5665_ASRC_1,
2693 RT5665_I2S1_ASRC_SFT, 0, NULL, 0),
2694 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5665_ASRC_1,
2695 RT5665_I2S2_ASRC_SFT, 0, NULL, 0),
2696 SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5665_ASRC_1,
2697 RT5665_I2S3_ASRC_SFT, 0, NULL, 0),
2698 SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5665_ASRC_1,
2699 RT5665_DAC_STO1_ASRC_SFT, 0, NULL, 0),
2700 SND_SOC_DAPM_SUPPLY_S("DAC STO2 ASRC", 1, RT5665_ASRC_1,
2701 RT5665_DAC_STO2_ASRC_SFT, 0, NULL, 0),
2702 SND_SOC_DAPM_SUPPLY_S("DAC Mono L ASRC", 1, RT5665_ASRC_1,
2703 RT5665_DAC_MONO_L_ASRC_SFT, 0, NULL, 0),
2704 SND_SOC_DAPM_SUPPLY_S("DAC Mono R ASRC", 1, RT5665_ASRC_1,
2705 RT5665_DAC_MONO_R_ASRC_SFT, 0, NULL, 0),
2706 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5665_ASRC_1,
2707 RT5665_ADC_STO1_ASRC_SFT, 0, NULL, 0),
2708 SND_SOC_DAPM_SUPPLY_S("ADC STO2 ASRC", 1, RT5665_ASRC_1,
2709 RT5665_ADC_STO2_ASRC_SFT, 0, NULL, 0),
2710 SND_SOC_DAPM_SUPPLY_S("ADC Mono L ASRC", 1, RT5665_ASRC_1,
2711 RT5665_ADC_MONO_L_ASRC_SFT, 0, NULL, 0),
2712 SND_SOC_DAPM_SUPPLY_S("ADC Mono R ASRC", 1, RT5665_ASRC_1,
2713 RT5665_ADC_MONO_R_ASRC_SFT, 0, NULL, 0),
2714 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5665_ASRC_1,
2715 RT5665_DMIC_STO1_ASRC_SFT, 0, NULL, 0),
2716 SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC", 1, RT5665_ASRC_1,
2717 RT5665_DMIC_STO2_ASRC_SFT, 0, NULL, 0),
2718 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5665_ASRC_1,
2719 RT5665_DMIC_MONO_L_ASRC_SFT, 0, NULL, 0),
2720 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5665_ASRC_1,
2721 RT5665_DMIC_MONO_R_ASRC_SFT, 0, NULL, 0),
2722
2723 /* Input Side */
2724 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5665_PWR_ANLG_2, RT5665_PWR_MB1_BIT,
2725 0, NULL, 0),
2726 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5665_PWR_ANLG_2, RT5665_PWR_MB2_BIT,
2727 0, NULL, 0),
2728 SND_SOC_DAPM_SUPPLY("MICBIAS3", RT5665_PWR_ANLG_2, RT5665_PWR_MB3_BIT,
2729 0, NULL, 0),
2730
2731 /* Input Lines */
2732 SND_SOC_DAPM_INPUT("DMIC L1"),
2733 SND_SOC_DAPM_INPUT("DMIC R1"),
2734 SND_SOC_DAPM_INPUT("DMIC L2"),
2735 SND_SOC_DAPM_INPUT("DMIC R2"),
2736
2737 SND_SOC_DAPM_INPUT("IN1P"),
2738 SND_SOC_DAPM_INPUT("IN1N"),
2739 SND_SOC_DAPM_INPUT("IN2P"),
2740 SND_SOC_DAPM_INPUT("IN2N"),
2741 SND_SOC_DAPM_INPUT("IN3P"),
2742 SND_SOC_DAPM_INPUT("IN3N"),
2743 SND_SOC_DAPM_INPUT("IN4P"),
2744 SND_SOC_DAPM_INPUT("IN4N"),
2745
2746 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2747 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2748
2749 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
2750 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
2751 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5665_DMIC_CTRL_1,
2752 RT5665_DMIC_1_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
2753 SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5665_DMIC_CTRL_1,
2754 RT5665_DMIC_2_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
2755
2756 /* Boost */
2757 SND_SOC_DAPM_PGA("BST1", SND_SOC_NOPM,
2758 0, 0, NULL, 0),
2759 SND_SOC_DAPM_PGA("BST2", SND_SOC_NOPM,
2760 0, 0, NULL, 0),
2761 SND_SOC_DAPM_PGA("BST3", SND_SOC_NOPM,
2762 0, 0, NULL, 0),
2763 SND_SOC_DAPM_PGA("BST4", SND_SOC_NOPM,
2764 0, 0, NULL, 0),
2765 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM,
2766 0, 0, NULL, 0),
2767 SND_SOC_DAPM_SUPPLY("BST1 Power", RT5665_PWR_ANLG_2,
2768 RT5665_PWR_BST1_BIT, 0, NULL, 0),
2769 SND_SOC_DAPM_SUPPLY("BST2 Power", RT5665_PWR_ANLG_2,
2770 RT5665_PWR_BST2_BIT, 0, NULL, 0),
2771 SND_SOC_DAPM_SUPPLY("BST3 Power", RT5665_PWR_ANLG_2,
2772 RT5665_PWR_BST3_BIT, 0, NULL, 0),
2773 SND_SOC_DAPM_SUPPLY("BST4 Power", RT5665_PWR_ANLG_2,
2774 RT5665_PWR_BST4_BIT, 0, NULL, 0),
2775 SND_SOC_DAPM_SUPPLY("BST1P Power", RT5665_PWR_ANLG_2,
2776 RT5665_PWR_BST1_P_BIT, 0, NULL, 0),
2777 SND_SOC_DAPM_SUPPLY("BST2P Power", RT5665_PWR_ANLG_2,
2778 RT5665_PWR_BST2_P_BIT, 0, NULL, 0),
2779 SND_SOC_DAPM_SUPPLY("BST3P Power", RT5665_PWR_ANLG_2,
2780 RT5665_PWR_BST3_P_BIT, 0, NULL, 0),
2781 SND_SOC_DAPM_SUPPLY("BST4P Power", RT5665_PWR_ANLG_2,
2782 RT5665_PWR_BST4_P_BIT, 0, NULL, 0),
2783 SND_SOC_DAPM_SUPPLY("CBJ Power", RT5665_PWR_ANLG_3,
2784 RT5665_PWR_CBJ_BIT, 0, NULL, 0),
2785
2786
2787 /* Input Volume */
2788 SND_SOC_DAPM_PGA("INL VOL", RT5665_PWR_VOL, RT5665_PWR_IN_L_BIT,
2789 0, NULL, 0),
2790 SND_SOC_DAPM_PGA("INR VOL", RT5665_PWR_VOL, RT5665_PWR_IN_R_BIT,
2791 0, NULL, 0),
2792
2793 /* REC Mixer */
2794 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5665_rec1_l_mix,
2795 ARRAY_SIZE(rt5665_rec1_l_mix)),
2796 SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM, 0, 0, rt5665_rec1_r_mix,
2797 ARRAY_SIZE(rt5665_rec1_r_mix)),
2798 SND_SOC_DAPM_MIXER("RECMIX2L", SND_SOC_NOPM, 0, 0, rt5665_rec2_l_mix,
2799 ARRAY_SIZE(rt5665_rec2_l_mix)),
2800 SND_SOC_DAPM_MIXER("RECMIX2R", SND_SOC_NOPM, 0, 0, rt5665_rec2_r_mix,
2801 ARRAY_SIZE(rt5665_rec2_r_mix)),
2802 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5665_PWR_ANLG_2,
2803 RT5665_PWR_RM1_L_BIT, 0, NULL, 0),
2804 SND_SOC_DAPM_SUPPLY("RECMIX1R Power", RT5665_PWR_ANLG_2,
2805 RT5665_PWR_RM1_R_BIT, 0, NULL, 0),
2806 SND_SOC_DAPM_SUPPLY("RECMIX2L Power", RT5665_PWR_MIXER,
2807 RT5665_PWR_RM2_L_BIT, 0, NULL, 0),
2808 SND_SOC_DAPM_SUPPLY("RECMIX2R Power", RT5665_PWR_MIXER,
2809 RT5665_PWR_RM2_R_BIT, 0, NULL, 0),
2810
2811 /* ADCs */
2812 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
2813 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
2814 SND_SOC_DAPM_ADC("ADC2 L", NULL, SND_SOC_NOPM, 0, 0),
2815 SND_SOC_DAPM_ADC("ADC2 R", NULL, SND_SOC_NOPM, 0, 0),
2816
2817 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5665_PWR_DIG_1,
2818 RT5665_PWR_ADC_L1_BIT, 0, NULL, 0),
2819 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5665_PWR_DIG_1,
2820 RT5665_PWR_ADC_R1_BIT, 0, NULL, 0),
2821 SND_SOC_DAPM_SUPPLY("ADC2 L Power", RT5665_PWR_DIG_1,
2822 RT5665_PWR_ADC_L2_BIT, 0, NULL, 0),
2823 SND_SOC_DAPM_SUPPLY("ADC2 R Power", RT5665_PWR_DIG_1,
2824 RT5665_PWR_ADC_R2_BIT, 0, NULL, 0),
2825 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5665_CHOP_ADC,
2826 RT5665_CKGEN_ADC1_SFT, 0, NULL, 0),
2827 SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5665_CHOP_ADC,
2828 RT5665_CKGEN_ADC2_SFT, 0, NULL, 0),
2829
2830 /* ADC Mux */
2831 SND_SOC_DAPM_MUX("Stereo1 DMIC L Mux", SND_SOC_NOPM, 0, 0,
2832 &rt5665_sto1_dmic_mux),
2833 SND_SOC_DAPM_MUX("Stereo1 DMIC R Mux", SND_SOC_NOPM, 0, 0,
2834 &rt5665_sto1_dmic_mux),
2835 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2836 &rt5665_sto1_adc1l_mux),
2837 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2838 &rt5665_sto1_adc1r_mux),
2839 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2840 &rt5665_sto1_adc2l_mux),
2841 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2842 &rt5665_sto1_adc2r_mux),
2843 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
2844 &rt5665_sto1_adcl_mux),
2845 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
2846 &rt5665_sto1_adcr_mux),
2847 SND_SOC_DAPM_MUX("Stereo1 DD L Mux", SND_SOC_NOPM, 0, 0,
2848 &rt5665_sto1_dd_l_mux),
2849 SND_SOC_DAPM_MUX("Stereo1 DD R Mux", SND_SOC_NOPM, 0, 0,
2850 &rt5665_sto1_dd_r_mux),
2851 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2852 &rt5665_mono_adc_l2_mux),
2853 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2854 &rt5665_mono_adc_r2_mux),
2855 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2856 &rt5665_mono_adc_l1_mux),
2857 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2858 &rt5665_mono_adc_r1_mux),
2859 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2860 &rt5665_mono_dmic_l_mux),
2861 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2862 &rt5665_mono_dmic_r_mux),
2863 SND_SOC_DAPM_MUX("Mono ADC L Mux", SND_SOC_NOPM, 0, 0,
2864 &rt5665_mono_adc_l_mux),
2865 SND_SOC_DAPM_MUX("Mono ADC R Mux", SND_SOC_NOPM, 0, 0,
2866 &rt5665_mono_adc_r_mux),
2867 SND_SOC_DAPM_MUX("Mono DD L Mux", SND_SOC_NOPM, 0, 0,
2868 &rt5665_mono_dd_l_mux),
2869 SND_SOC_DAPM_MUX("Mono DD R Mux", SND_SOC_NOPM, 0, 0,
2870 &rt5665_mono_dd_r_mux),
2871 SND_SOC_DAPM_MUX("Stereo2 DMIC L Mux", SND_SOC_NOPM, 0, 0,
2872 &rt5665_sto2_dmic_mux),
2873 SND_SOC_DAPM_MUX("Stereo2 DMIC R Mux", SND_SOC_NOPM, 0, 0,
2874 &rt5665_sto2_dmic_mux),
2875 SND_SOC_DAPM_MUX("Stereo2 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2876 &rt5665_sto2_adc1l_mux),
2877 SND_SOC_DAPM_MUX("Stereo2 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2878 &rt5665_sto2_adc1r_mux),
2879 SND_SOC_DAPM_MUX("Stereo2 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2880 &rt5665_sto2_adc2l_mux),
2881 SND_SOC_DAPM_MUX("Stereo2 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2882 &rt5665_sto2_adc2r_mux),
2883 SND_SOC_DAPM_MUX("Stereo2 ADC L Mux", SND_SOC_NOPM, 0, 0,
2884 &rt5665_sto2_adcl_mux),
2885 SND_SOC_DAPM_MUX("Stereo2 ADC R Mux", SND_SOC_NOPM, 0, 0,
2886 &rt5665_sto2_adcr_mux),
2887 SND_SOC_DAPM_MUX("Stereo2 DD L Mux", SND_SOC_NOPM, 0, 0,
2888 &rt5665_sto2_dd_l_mux),
2889 SND_SOC_DAPM_MUX("Stereo2 DD R Mux", SND_SOC_NOPM, 0, 0,
2890 &rt5665_sto2_dd_r_mux),
2891 /* ADC Mixer */
2892 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5665_PWR_DIG_2,
2893 RT5665_PWR_ADC_S1F_BIT, 0, NULL, 0),
2894 SND_SOC_DAPM_SUPPLY("ADC Stereo2 Filter", RT5665_PWR_DIG_2,
2895 RT5665_PWR_ADC_S2F_BIT, 0, NULL, 0),
2896 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5665_STO1_ADC_DIG_VOL,
2897 RT5665_L_MUTE_SFT, 1, rt5665_sto1_adc_l_mix,
2898 ARRAY_SIZE(rt5665_sto1_adc_l_mix)),
2899 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5665_STO1_ADC_DIG_VOL,
2900 RT5665_R_MUTE_SFT, 1, rt5665_sto1_adc_r_mix,
2901 ARRAY_SIZE(rt5665_sto1_adc_r_mix)),
2902 SND_SOC_DAPM_MIXER("Stereo2 ADC MIXL", RT5665_STO2_ADC_DIG_VOL,
2903 RT5665_L_MUTE_SFT, 1, rt5665_sto2_adc_l_mix,
2904 ARRAY_SIZE(rt5665_sto2_adc_l_mix)),
2905 SND_SOC_DAPM_MIXER("Stereo2 ADC MIXR", RT5665_STO2_ADC_DIG_VOL,
2906 RT5665_R_MUTE_SFT, 1, rt5665_sto2_adc_r_mix,
2907 ARRAY_SIZE(rt5665_sto2_adc_r_mix)),
2908 SND_SOC_DAPM_SUPPLY("ADC Mono Left Filter", RT5665_PWR_DIG_2,
2909 RT5665_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2910 SND_SOC_DAPM_MIXER("Mono ADC MIXL", RT5665_MONO_ADC_DIG_VOL,
2911 RT5665_L_MUTE_SFT, 1, rt5665_mono_adc_l_mix,
2912 ARRAY_SIZE(rt5665_mono_adc_l_mix)),
2913 SND_SOC_DAPM_SUPPLY("ADC Mono Right Filter", RT5665_PWR_DIG_2,
2914 RT5665_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2915 SND_SOC_DAPM_MIXER("Mono ADC MIXR", RT5665_MONO_ADC_DIG_VOL,
2916 RT5665_R_MUTE_SFT, 1, rt5665_mono_adc_r_mix,
2917 ARRAY_SIZE(rt5665_mono_adc_r_mix)),
2918
2919 /* ADC PGA */
2920 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2921 SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2922 SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2923
2924 /* Digital Interface */
2925 SND_SOC_DAPM_SUPPLY("I2S1_1", RT5665_PWR_DIG_1, RT5665_PWR_I2S1_1_BIT,
2926 0, NULL, 0),
2927 SND_SOC_DAPM_SUPPLY("I2S1_2", RT5665_PWR_DIG_1, RT5665_PWR_I2S1_2_BIT,
2928 0, NULL, 0),
2929 SND_SOC_DAPM_SUPPLY("I2S2_1", RT5665_PWR_DIG_1, RT5665_PWR_I2S2_1_BIT,
2930 0, rt5665_i2s_pin_event, SND_SOC_DAPM_PRE_PMU |
2931 SND_SOC_DAPM_POST_PMD),
2932 SND_SOC_DAPM_SUPPLY("I2S2_2", RT5665_PWR_DIG_1, RT5665_PWR_I2S2_2_BIT,
2933 0, rt5665_i2s_pin_event, SND_SOC_DAPM_PRE_PMU |
2934 SND_SOC_DAPM_POST_PMD),
2935 SND_SOC_DAPM_SUPPLY("I2S3", RT5665_PWR_DIG_1, RT5665_PWR_I2S3_BIT,
2936 0, rt5665_i2s_pin_event, SND_SOC_DAPM_PRE_PMU |
2937 SND_SOC_DAPM_POST_PMD),
2938 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2939 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2940 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2941 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2942 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2943 SND_SOC_DAPM_PGA("IF1 DAC2 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2944 SND_SOC_DAPM_PGA("IF1 DAC2 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2945 SND_SOC_DAPM_PGA("IF1 DAC3 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2946 SND_SOC_DAPM_PGA("IF1 DAC3 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2947
2948 SND_SOC_DAPM_PGA("IF2_1 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2949 SND_SOC_DAPM_PGA("IF2_2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2950 SND_SOC_DAPM_PGA("IF2_1 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2951 SND_SOC_DAPM_PGA("IF2_1 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2952 SND_SOC_DAPM_PGA("IF2_2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2953 SND_SOC_DAPM_PGA("IF2_2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2954 SND_SOC_DAPM_PGA("IF2_1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2955 SND_SOC_DAPM_PGA("IF2_2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2956
2957 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2958 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2959 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2960 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2961
2962 /* Digital Interface Select */
2963 SND_SOC_DAPM_MUX("IF1_1_ADC1 Mux", SND_SOC_NOPM, 0, 0,
2964 &rt5665_if1_1_adc1_mux),
2965 SND_SOC_DAPM_MUX("IF1_1_ADC2 Mux", SND_SOC_NOPM, 0, 0,
2966 &rt5665_if1_1_adc2_mux),
2967 SND_SOC_DAPM_MUX("IF1_1_ADC3 Mux", SND_SOC_NOPM, 0, 0,
2968 &rt5665_if1_1_adc3_mux),
2969 SND_SOC_DAPM_PGA("IF1_1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2970 SND_SOC_DAPM_MUX("IF1_2_ADC1 Mux", SND_SOC_NOPM, 0, 0,
2971 &rt5665_if1_2_adc1_mux),
2972 SND_SOC_DAPM_MUX("IF1_2_ADC2 Mux", SND_SOC_NOPM, 0, 0,
2973 &rt5665_if1_2_adc2_mux),
2974 SND_SOC_DAPM_MUX("IF1_2_ADC3 Mux", SND_SOC_NOPM, 0, 0,
2975 &rt5665_if1_2_adc3_mux),
2976 SND_SOC_DAPM_MUX("IF1_2_ADC4 Mux", SND_SOC_NOPM, 0, 0,
2977 &rt5665_if1_2_adc4_mux),
2978 SND_SOC_DAPM_MUX("TDM1 slot 01 Data Mux", SND_SOC_NOPM, 0, 0,
2979 &rt5665_tdm1_adc_mux),
2980 SND_SOC_DAPM_MUX("TDM1 slot 23 Data Mux", SND_SOC_NOPM, 0, 0,
2981 &rt5665_tdm1_adc_mux),
2982 SND_SOC_DAPM_MUX("TDM1 slot 45 Data Mux", SND_SOC_NOPM, 0, 0,
2983 &rt5665_tdm1_adc_mux),
2984 SND_SOC_DAPM_MUX("TDM1 slot 67 Data Mux", SND_SOC_NOPM, 0, 0,
2985 &rt5665_tdm1_adc_mux),
2986 SND_SOC_DAPM_MUX("TDM2 slot 01 Data Mux", SND_SOC_NOPM, 0, 0,
2987 &rt5665_tdm2_adc_mux),
2988 SND_SOC_DAPM_MUX("TDM2 slot 23 Data Mux", SND_SOC_NOPM, 0, 0,
2989 &rt5665_tdm2_adc_mux),
2990 SND_SOC_DAPM_MUX("TDM2 slot 45 Data Mux", SND_SOC_NOPM, 0, 0,
2991 &rt5665_tdm2_adc_mux),
2992 SND_SOC_DAPM_MUX("TDM2 slot 67 Data Mux", SND_SOC_NOPM, 0, 0,
2993 &rt5665_tdm2_adc_mux),
2994 SND_SOC_DAPM_MUX("IF2_1 ADC Mux", SND_SOC_NOPM, 0, 0,
2995 &rt5665_if2_1_adc_in_mux),
2996 SND_SOC_DAPM_MUX("IF2_2 ADC Mux", SND_SOC_NOPM, 0, 0,
2997 &rt5665_if2_2_adc_in_mux),
2998 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
2999 &rt5665_if3_adc_in_mux),
3000 SND_SOC_DAPM_MUX("IF1_1 0 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3001 &rt5665_if1_1_01_adc_swap_mux),
3002 SND_SOC_DAPM_MUX("IF1_1 1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3003 &rt5665_if1_1_01_adc_swap_mux),
3004 SND_SOC_DAPM_MUX("IF1_1 2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3005 &rt5665_if1_1_23_adc_swap_mux),
3006 SND_SOC_DAPM_MUX("IF1_1 3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3007 &rt5665_if1_1_23_adc_swap_mux),
3008 SND_SOC_DAPM_MUX("IF1_1 4 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3009 &rt5665_if1_1_45_adc_swap_mux),
3010 SND_SOC_DAPM_MUX("IF1_1 5 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3011 &rt5665_if1_1_45_adc_swap_mux),
3012 SND_SOC_DAPM_MUX("IF1_1 6 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3013 &rt5665_if1_1_67_adc_swap_mux),
3014 SND_SOC_DAPM_MUX("IF1_1 7 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3015 &rt5665_if1_1_67_adc_swap_mux),
3016 SND_SOC_DAPM_MUX("IF1_2 0 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3017 &rt5665_if1_2_01_adc_swap_mux),
3018 SND_SOC_DAPM_MUX("IF1_2 1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3019 &rt5665_if1_2_01_adc_swap_mux),
3020 SND_SOC_DAPM_MUX("IF1_2 2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3021 &rt5665_if1_2_23_adc_swap_mux),
3022 SND_SOC_DAPM_MUX("IF1_2 3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3023 &rt5665_if1_2_23_adc_swap_mux),
3024 SND_SOC_DAPM_MUX("IF1_2 4 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3025 &rt5665_if1_2_45_adc_swap_mux),
3026 SND_SOC_DAPM_MUX("IF1_2 5 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3027 &rt5665_if1_2_45_adc_swap_mux),
3028 SND_SOC_DAPM_MUX("IF1_2 6 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3029 &rt5665_if1_2_67_adc_swap_mux),
3030 SND_SOC_DAPM_MUX("IF1_2 7 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3031 &rt5665_if1_2_67_adc_swap_mux),
3032 SND_SOC_DAPM_MUX("IF2_1 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
3033 &rt5665_if2_1_dac_swap_mux),
3034 SND_SOC_DAPM_MUX("IF2_1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3035 &rt5665_if2_1_adc_swap_mux),
3036 SND_SOC_DAPM_MUX("IF2_2 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
3037 &rt5665_if2_2_dac_swap_mux),
3038 SND_SOC_DAPM_MUX("IF2_2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3039 &rt5665_if2_2_adc_swap_mux),
3040 SND_SOC_DAPM_MUX("IF3 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
3041 &rt5665_if3_dac_swap_mux),
3042 SND_SOC_DAPM_MUX("IF3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3043 &rt5665_if3_adc_swap_mux),
3044
3045 /* Audio Interface */
3046 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 0", "AIF1_1 Capture",
3047 0, SND_SOC_NOPM, 0, 0),
3048 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 1", "AIF1_1 Capture",
3049 1, SND_SOC_NOPM, 0, 0),
3050 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 2", "AIF1_1 Capture",
3051 2, SND_SOC_NOPM, 0, 0),
3052 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 3", "AIF1_1 Capture",
3053 3, SND_SOC_NOPM, 0, 0),
3054 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 4", "AIF1_1 Capture",
3055 4, SND_SOC_NOPM, 0, 0),
3056 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 5", "AIF1_1 Capture",
3057 5, SND_SOC_NOPM, 0, 0),
3058 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 6", "AIF1_1 Capture",
3059 6, SND_SOC_NOPM, 0, 0),
3060 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 7", "AIF1_1 Capture",
3061 7, SND_SOC_NOPM, 0, 0),
3062 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 0", "AIF1_2 Capture",
3063 0, SND_SOC_NOPM, 0, 0),
3064 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 1", "AIF1_2 Capture",
3065 1, SND_SOC_NOPM, 0, 0),
3066 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 2", "AIF1_2 Capture",
3067 2, SND_SOC_NOPM, 0, 0),
3068 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 3", "AIF1_2 Capture",
3069 3, SND_SOC_NOPM, 0, 0),
3070 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 4", "AIF1_2 Capture",
3071 4, SND_SOC_NOPM, 0, 0),
3072 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 5", "AIF1_2 Capture",
3073 5, SND_SOC_NOPM, 0, 0),
3074 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 6", "AIF1_2 Capture",
3075 6, SND_SOC_NOPM, 0, 0),
3076 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 7", "AIF1_2 Capture",
3077 7, SND_SOC_NOPM, 0, 0),
3078 SND_SOC_DAPM_AIF_OUT("AIF2_1TX", "AIF2_1 Capture",
3079 0, SND_SOC_NOPM, 0, 0),
3080 SND_SOC_DAPM_AIF_OUT("AIF2_2TX", "AIF2_2 Capture",
3081 0, SND_SOC_NOPM, 0, 0),
3082 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture",
3083 0, SND_SOC_NOPM, 0, 0),
3084 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback",
3085 0, SND_SOC_NOPM, 0, 0),
3086 SND_SOC_DAPM_AIF_IN("AIF2_1RX", "AIF2_1 Playback",
3087 0, SND_SOC_NOPM, 0, 0),
3088 SND_SOC_DAPM_AIF_IN("AIF2_2RX", "AIF2_2 Playback",
3089 0, SND_SOC_NOPM, 0, 0),
3090 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback",
3091 0, SND_SOC_NOPM, 0, 0),
3092
3093 /* Output Side */
3094 /* DAC mixer before sound effect */
3095 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
3096 rt5665_dac_l_mix, ARRAY_SIZE(rt5665_dac_l_mix)),
3097 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
3098 rt5665_dac_r_mix, ARRAY_SIZE(rt5665_dac_r_mix)),
3099
3100 /* DAC channel Mux */
3101 SND_SOC_DAPM_MUX("DAC L1 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l1_mux),
3102 SND_SOC_DAPM_MUX("DAC R1 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r1_mux),
3103 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l2_mux),
3104 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r2_mux),
3105 SND_SOC_DAPM_MUX("DAC L3 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l3_mux),
3106 SND_SOC_DAPM_MUX("DAC R3 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r3_mux),
3107
3108 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0,
3109 &rt5665_alg_dac_l1_mux),
3110 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0,
3111 &rt5665_alg_dac_r1_mux),
3112 SND_SOC_DAPM_MUX("DAC L2 Source", SND_SOC_NOPM, 0, 0,
3113 &rt5665_alg_dac_l2_mux),
3114 SND_SOC_DAPM_MUX("DAC R2 Source", SND_SOC_NOPM, 0, 0,
3115 &rt5665_alg_dac_r2_mux),
3116
3117 /* DAC Mixer */
3118 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5665_PWR_DIG_2,
3119 RT5665_PWR_DAC_S1F_BIT, 0, NULL, 0),
3120 SND_SOC_DAPM_SUPPLY("DAC Stereo2 Filter", RT5665_PWR_DIG_2,
3121 RT5665_PWR_DAC_S2F_BIT, 0, NULL, 0),
3122 SND_SOC_DAPM_SUPPLY("DAC Mono Left Filter", RT5665_PWR_DIG_2,
3123 RT5665_PWR_DAC_MF_L_BIT, 0, NULL, 0),
3124 SND_SOC_DAPM_SUPPLY("DAC Mono Right Filter", RT5665_PWR_DIG_2,
3125 RT5665_PWR_DAC_MF_R_BIT, 0, NULL, 0),
3126 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,
3127 rt5665_sto1_dac_l_mix, ARRAY_SIZE(rt5665_sto1_dac_l_mix)),
3128 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,
3129 rt5665_sto1_dac_r_mix, ARRAY_SIZE(rt5665_sto1_dac_r_mix)),
3130 SND_SOC_DAPM_MIXER("Stereo2 DAC MIXL", SND_SOC_NOPM, 0, 0,
3131 rt5665_sto2_dac_l_mix, ARRAY_SIZE(rt5665_sto2_dac_l_mix)),
3132 SND_SOC_DAPM_MIXER("Stereo2 DAC MIXR", SND_SOC_NOPM, 0, 0,
3133 rt5665_sto2_dac_r_mix, ARRAY_SIZE(rt5665_sto2_dac_r_mix)),
3134 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
3135 rt5665_mono_dac_l_mix, ARRAY_SIZE(rt5665_mono_dac_l_mix)),
3136 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
3137 rt5665_mono_dac_r_mix, ARRAY_SIZE(rt5665_mono_dac_r_mix)),
3138 SND_SOC_DAPM_MUX("DAC MIXL", SND_SOC_NOPM, 0, 0,
3139 &rt5665_dig_dac_mixl_mux),
3140 SND_SOC_DAPM_MUX("DAC MIXR", SND_SOC_NOPM, 0, 0,
3141 &rt5665_dig_dac_mixr_mux),
3142
3143 /* DACs */
3144 SND_SOC_DAPM_DAC("DAC L1", NULL, SND_SOC_NOPM, 0, 0),
3145 SND_SOC_DAPM_DAC("DAC R1", NULL, SND_SOC_NOPM, 0, 0),
3146
3147 SND_SOC_DAPM_SUPPLY("DAC L2 Power", RT5665_PWR_DIG_1,
3148 RT5665_PWR_DAC_L2_BIT, 0, NULL, 0),
3149 SND_SOC_DAPM_SUPPLY("DAC R2 Power", RT5665_PWR_DIG_1,
3150 RT5665_PWR_DAC_R2_BIT, 0, NULL, 0),
3151 SND_SOC_DAPM_DAC("DAC L2", NULL, SND_SOC_NOPM, 0, 0),
3152 SND_SOC_DAPM_DAC("DAC R2", NULL, SND_SOC_NOPM, 0, 0),
3153 SND_SOC_DAPM_PGA("DAC1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3154
3155 SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 1, RT5665_CHOP_DAC,
3156 RT5665_CKGEN_DAC1_SFT, 0, NULL, 0),
3157 SND_SOC_DAPM_SUPPLY_S("DAC 2 Clock", 1, RT5665_CHOP_DAC,
3158 RT5665_CKGEN_DAC2_SFT, 0, NULL, 0),
3159
3160 /* OUT Mixer */
3161 SND_SOC_DAPM_MIXER("MONOVOL MIX", RT5665_PWR_MIXER, RT5665_PWR_MM_BIT,
3162 0, rt5665_monovol_mix, ARRAY_SIZE(rt5665_monovol_mix)),
3163 SND_SOC_DAPM_MIXER("OUT MIXL", RT5665_PWR_MIXER, RT5665_PWR_OM_L_BIT,
3164 0, rt5665_out_l_mix, ARRAY_SIZE(rt5665_out_l_mix)),
3165 SND_SOC_DAPM_MIXER("OUT MIXR", RT5665_PWR_MIXER, RT5665_PWR_OM_R_BIT,
3166 0, rt5665_out_r_mix, ARRAY_SIZE(rt5665_out_r_mix)),
3167
3168 /* Output Volume */
3169 SND_SOC_DAPM_SWITCH("MONOVOL", RT5665_PWR_VOL, RT5665_PWR_MV_BIT, 0,
3170 &monovol_switch),
3171 SND_SOC_DAPM_SWITCH("OUTVOL L", RT5665_PWR_VOL, RT5665_PWR_OV_L_BIT, 0,
3172 &outvol_l_switch),
3173 SND_SOC_DAPM_SWITCH("OUTVOL R", RT5665_PWR_VOL, RT5665_PWR_OV_R_BIT, 0,
3174 &outvol_r_switch),
3175
3176 /* MONO/HPO/LOUT */
3177 SND_SOC_DAPM_MIXER("Mono MIX", SND_SOC_NOPM, 0, 0, rt5665_mono_mix,
3178 ARRAY_SIZE(rt5665_mono_mix)),
3179 SND_SOC_DAPM_MIXER("LOUT L MIX", SND_SOC_NOPM, 0, 0, rt5665_lout_l_mix,
3180 ARRAY_SIZE(rt5665_lout_l_mix)),
3181 SND_SOC_DAPM_MIXER("LOUT R MIX", SND_SOC_NOPM, 0, 0, rt5665_lout_r_mix,
3182 ARRAY_SIZE(rt5665_lout_r_mix)),
3183 SND_SOC_DAPM_PGA_S("Mono Amp", 1, RT5665_PWR_ANLG_1, RT5665_PWR_MA_BIT,
3184 0, rt5665_mono_event, SND_SOC_DAPM_POST_PMD |
3185 SND_SOC_DAPM_PRE_PMU),
3186 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5665_hp_event,
3187 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
3188 SND_SOC_DAPM_PGA_S("LOUT Amp", 1, RT5665_PWR_ANLG_1,
3189 RT5665_PWR_LM_BIT, 0, rt5665_lout_event,
3190 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD |
3191 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
3192
3193 SND_SOC_DAPM_SUPPLY("Charge Pump", SND_SOC_NOPM, 0, 0,
3194 rt5665_charge_pump_event, SND_SOC_DAPM_PRE_PMU |
3195 SND_SOC_DAPM_POST_PMD),
3196
3197 SND_SOC_DAPM_SWITCH("Mono Playback", SND_SOC_NOPM, 0, 0,
3198 &mono_switch),
3199 SND_SOC_DAPM_SWITCH("HPO Playback", SND_SOC_NOPM, 0, 0,
3200 &hpo_switch),
3201 SND_SOC_DAPM_SWITCH("LOUT L Playback", SND_SOC_NOPM, 0, 0,
3202 &lout_l_switch),
3203 SND_SOC_DAPM_SWITCH("LOUT R Playback", SND_SOC_NOPM, 0, 0,
3204 &lout_r_switch),
3205 SND_SOC_DAPM_SWITCH("PDM L Playback", SND_SOC_NOPM, 0, 0,
3206 &pdm_l_switch),
3207 SND_SOC_DAPM_SWITCH("PDM R Playback", SND_SOC_NOPM, 0, 0,
3208 &pdm_r_switch),
3209
3210 /* PDM */
3211 SND_SOC_DAPM_SUPPLY("PDM Power", RT5665_PWR_DIG_2,
3212 RT5665_PWR_PDM1_BIT, 0, NULL, 0),
3213 SND_SOC_DAPM_MUX("PDM L Mux", SND_SOC_NOPM,
3214 0, 1, &rt5665_pdm_l_mux),
3215 SND_SOC_DAPM_MUX("PDM R Mux", SND_SOC_NOPM,
3216 0, 1, &rt5665_pdm_r_mux),
3217
3218 /* CLK DET */
3219 SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5665_CLK_DET, RT5665_SYS_CLK_DET,
3220 0, NULL, 0),
3221 SND_SOC_DAPM_SUPPLY("CLKDET HP", RT5665_CLK_DET, RT5665_HP_CLK_DET,
3222 0, NULL, 0),
3223 SND_SOC_DAPM_SUPPLY("CLKDET MONO", RT5665_CLK_DET, RT5665_MONO_CLK_DET,
3224 0, NULL, 0),
3225 SND_SOC_DAPM_SUPPLY("CLKDET LOUT", RT5665_CLK_DET, RT5665_LOUT_CLK_DET,
3226 0, NULL, 0),
3227 SND_SOC_DAPM_SUPPLY("CLKDET", RT5665_CLK_DET, RT5665_POW_CLK_DET,
3228 0, NULL, 0),
3229
3230 /* Output Lines */
3231 SND_SOC_DAPM_OUTPUT("HPOL"),
3232 SND_SOC_DAPM_OUTPUT("HPOR"),
3233 SND_SOC_DAPM_OUTPUT("LOUTL"),
3234 SND_SOC_DAPM_OUTPUT("LOUTR"),
3235 SND_SOC_DAPM_OUTPUT("MONOOUT"),
3236 SND_SOC_DAPM_OUTPUT("PDML"),
3237 SND_SOC_DAPM_OUTPUT("PDMR"),
3238 };
3239
3240 static const struct snd_soc_dapm_route rt5665_dapm_routes[] = {
3241 /*PLL*/
3242 {"ADC Stereo1 Filter", NULL, "PLL", is_sys_clk_from_pll},
3243 {"ADC Stereo2 Filter", NULL, "PLL", is_sys_clk_from_pll},
3244 {"ADC Mono Left Filter", NULL, "PLL", is_sys_clk_from_pll},
3245 {"ADC Mono Right Filter", NULL, "PLL", is_sys_clk_from_pll},
3246 {"DAC Stereo1 Filter", NULL, "PLL", is_sys_clk_from_pll},
3247 {"DAC Stereo2 Filter", NULL, "PLL", is_sys_clk_from_pll},
3248 {"DAC Mono Left Filter", NULL, "PLL", is_sys_clk_from_pll},
3249 {"DAC Mono Right Filter", NULL, "PLL", is_sys_clk_from_pll},
3250
3251 /*ASRC*/
3252 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
3253 {"ADC Stereo2 Filter", NULL, "ADC STO2 ASRC", is_using_asrc},
3254 {"ADC Mono Left Filter", NULL, "ADC Mono L ASRC", is_using_asrc},
3255 {"ADC Mono Right Filter", NULL, "ADC Mono R ASRC", is_using_asrc},
3256 {"DAC Mono Left Filter", NULL, "DAC Mono L ASRC", is_using_asrc},
3257 {"DAC Mono Right Filter", NULL, "DAC Mono R ASRC", is_using_asrc},
3258 {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
3259 {"DAC Stereo2 Filter", NULL, "DAC STO2 ASRC", is_using_asrc},
3260 {"I2S1 ASRC", NULL, "CLKDET"},
3261 {"I2S2 ASRC", NULL, "CLKDET"},
3262 {"I2S3 ASRC", NULL, "CLKDET"},
3263
3264 /*Vref*/
3265 {"Mic Det Power", NULL, "Vref2"},
3266 {"MICBIAS1", NULL, "Vref1"},
3267 {"MICBIAS1", NULL, "Vref2"},
3268 {"MICBIAS2", NULL, "Vref1"},
3269 {"MICBIAS2", NULL, "Vref2"},
3270 {"MICBIAS3", NULL, "Vref1"},
3271 {"MICBIAS3", NULL, "Vref2"},
3272
3273 {"Stereo1 DMIC L Mux", NULL, "DMIC STO1 ASRC"},
3274 {"Stereo1 DMIC R Mux", NULL, "DMIC STO1 ASRC"},
3275 {"Stereo2 DMIC L Mux", NULL, "DMIC STO2 ASRC"},
3276 {"Stereo2 DMIC R Mux", NULL, "DMIC STO2 ASRC"},
3277 {"Mono DMIC L Mux", NULL, "DMIC MONO L ASRC"},
3278 {"Mono DMIC R Mux", NULL, "DMIC MONO R ASRC"},
3279
3280 {"I2S1_1", NULL, "I2S1 ASRC"},
3281 {"I2S1_2", NULL, "I2S1 ASRC"},
3282 {"I2S2_1", NULL, "I2S2 ASRC"},
3283 {"I2S2_2", NULL, "I2S2 ASRC"},
3284 {"I2S3", NULL, "I2S3 ASRC"},
3285
3286 {"CLKDET SYS", NULL, "CLKDET"},
3287 {"CLKDET HP", NULL, "CLKDET"},
3288 {"CLKDET MONO", NULL, "CLKDET"},
3289 {"CLKDET LOUT", NULL, "CLKDET"},
3290
3291 {"IN1P", NULL, "LDO2"},
3292 {"IN2P", NULL, "LDO2"},
3293 {"IN3P", NULL, "LDO2"},
3294 {"IN4P", NULL, "LDO2"},
3295
3296 {"DMIC1", NULL, "DMIC L1"},
3297 {"DMIC1", NULL, "DMIC R1"},
3298 {"DMIC2", NULL, "DMIC L2"},
3299 {"DMIC2", NULL, "DMIC R2"},
3300
3301 {"BST1", NULL, "IN1P"},
3302 {"BST1", NULL, "IN1N"},
3303 {"BST1", NULL, "BST1 Power"},
3304 {"BST1", NULL, "BST1P Power"},
3305 {"BST2", NULL, "IN2P"},
3306 {"BST2", NULL, "IN2N"},
3307 {"BST2", NULL, "BST2 Power"},
3308 {"BST2", NULL, "BST2P Power"},
3309 {"BST3", NULL, "IN3P"},
3310 {"BST3", NULL, "IN3N"},
3311 {"BST3", NULL, "BST3 Power"},
3312 {"BST3", NULL, "BST3P Power"},
3313 {"BST4", NULL, "IN4P"},
3314 {"BST4", NULL, "IN4N"},
3315 {"BST4", NULL, "BST4 Power"},
3316 {"BST4", NULL, "BST4P Power"},
3317 {"BST1 CBJ", NULL, "IN1P"},
3318 {"BST1 CBJ", NULL, "IN1N"},
3319 {"BST1 CBJ", NULL, "CBJ Power"},
3320 {"CBJ Power", NULL, "Vref2"},
3321
3322 {"INL VOL", NULL, "IN3P"},
3323 {"INR VOL", NULL, "IN3N"},
3324
3325 {"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
3326 {"RECMIX1L", "INL Switch", "INL VOL"},
3327 {"RECMIX1L", "INR Switch", "INR VOL"},
3328 {"RECMIX1L", "BST4 Switch", "BST4"},
3329 {"RECMIX1L", "BST3 Switch", "BST3"},
3330 {"RECMIX1L", "BST2 Switch", "BST2"},
3331 {"RECMIX1L", "BST1 Switch", "BST1"},
3332 {"RECMIX1L", NULL, "RECMIX1L Power"},
3333
3334 {"RECMIX1R", "MONOVOL Switch", "MONOVOL"},
3335 {"RECMIX1R", "INR Switch", "INR VOL"},
3336 {"RECMIX1R", "BST4 Switch", "BST4"},
3337 {"RECMIX1R", "BST3 Switch", "BST3"},
3338 {"RECMIX1R", "BST2 Switch", "BST2"},
3339 {"RECMIX1R", "BST1 Switch", "BST1"},
3340 {"RECMIX1R", NULL, "RECMIX1R Power"},
3341
3342 {"RECMIX2L", "CBJ Switch", "BST1 CBJ"},
3343 {"RECMIX2L", "INL Switch", "INL VOL"},
3344 {"RECMIX2L", "INR Switch", "INR VOL"},
3345 {"RECMIX2L", "BST4 Switch", "BST4"},
3346 {"RECMIX2L", "BST3 Switch", "BST3"},
3347 {"RECMIX2L", "BST2 Switch", "BST2"},
3348 {"RECMIX2L", "BST1 Switch", "BST1"},
3349 {"RECMIX2L", NULL, "RECMIX2L Power"},
3350
3351 {"RECMIX2R", "MONOVOL Switch", "MONOVOL"},
3352 {"RECMIX2R", "INL Switch", "INL VOL"},
3353 {"RECMIX2R", "INR Switch", "INR VOL"},
3354 {"RECMIX2R", "BST4 Switch", "BST4"},
3355 {"RECMIX2R", "BST3 Switch", "BST3"},
3356 {"RECMIX2R", "BST2 Switch", "BST2"},
3357 {"RECMIX2R", "BST1 Switch", "BST1"},
3358 {"RECMIX2R", NULL, "RECMIX2R Power"},
3359
3360 {"ADC1 L", NULL, "RECMIX1L"},
3361 {"ADC1 L", NULL, "ADC1 L Power"},
3362 {"ADC1 L", NULL, "ADC1 clock"},
3363 {"ADC1 R", NULL, "RECMIX1R"},
3364 {"ADC1 R", NULL, "ADC1 R Power"},
3365 {"ADC1 R", NULL, "ADC1 clock"},
3366
3367 {"ADC2 L", NULL, "RECMIX2L"},
3368 {"ADC2 L", NULL, "ADC2 L Power"},
3369 {"ADC2 L", NULL, "ADC2 clock"},
3370 {"ADC2 R", NULL, "RECMIX2R"},
3371 {"ADC2 R", NULL, "ADC2 R Power"},
3372 {"ADC2 R", NULL, "ADC2 clock"},
3373
3374 {"DMIC L1", NULL, "DMIC CLK"},
3375 {"DMIC L1", NULL, "DMIC1 Power"},
3376 {"DMIC R1", NULL, "DMIC CLK"},
3377 {"DMIC R1", NULL, "DMIC1 Power"},
3378 {"DMIC L2", NULL, "DMIC CLK"},
3379 {"DMIC L2", NULL, "DMIC2 Power"},
3380 {"DMIC R2", NULL, "DMIC CLK"},
3381 {"DMIC R2", NULL, "DMIC2 Power"},
3382
3383 {"Stereo1 DMIC L Mux", "DMIC1", "DMIC L1"},
3384 {"Stereo1 DMIC L Mux", "DMIC2", "DMIC L2"},
3385
3386 {"Stereo1 DMIC R Mux", "DMIC1", "DMIC R1"},
3387 {"Stereo1 DMIC R Mux", "DMIC2", "DMIC R2"},
3388
3389 {"Mono DMIC L Mux", "DMIC1 L", "DMIC L1"},
3390 {"Mono DMIC L Mux", "DMIC2 L", "DMIC L2"},
3391
3392 {"Mono DMIC R Mux", "DMIC1 R", "DMIC R1"},
3393 {"Mono DMIC R Mux", "DMIC2 R", "DMIC R2"},
3394
3395 {"Stereo2 DMIC L Mux", "DMIC1", "DMIC L1"},
3396 {"Stereo2 DMIC L Mux", "DMIC2", "DMIC L2"},
3397
3398 {"Stereo2 DMIC R Mux", "DMIC1", "DMIC R1"},
3399 {"Stereo2 DMIC R Mux", "DMIC2", "DMIC R2"},
3400
3401 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
3402 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
3403 {"Stereo1 ADC L Mux", "ADC2 L", "ADC2 L"},
3404 {"Stereo1 ADC L Mux", "ADC2 R", "ADC2 R"},
3405 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
3406 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
3407 {"Stereo1 ADC R Mux", "ADC2 L", "ADC2 L"},
3408 {"Stereo1 ADC R Mux", "ADC2 R", "ADC2 R"},
3409
3410 {"Stereo1 DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"},
3411 {"Stereo1 DD L Mux", "MONO DAC", "Mono DAC MIXL"},
3412
3413 {"Stereo1 DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"},
3414 {"Stereo1 DD R Mux", "MONO DAC", "Mono DAC MIXR"},
3415
3416 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
3417 {"Stereo1 ADC L1 Mux", "DD Mux", "Stereo1 DD L Mux"},
3418 {"Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC L Mux"},
3419 {"Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL"},
3420
3421 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
3422 {"Stereo1 ADC R1 Mux", "DD Mux", "Stereo1 DD R Mux"},
3423 {"Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC R Mux"},
3424 {"Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR"},
3425
3426 {"Mono ADC L Mux", "ADC1 L", "ADC1 L"},
3427 {"Mono ADC L Mux", "ADC1 R", "ADC1 R"},
3428 {"Mono ADC L Mux", "ADC2 L", "ADC2 L"},
3429 {"Mono ADC L Mux", "ADC2 R", "ADC2 R"},
3430
3431 {"Mono ADC R Mux", "ADC1 L", "ADC1 L"},
3432 {"Mono ADC R Mux", "ADC1 R", "ADC1 R"},
3433 {"Mono ADC R Mux", "ADC2 L", "ADC2 L"},
3434 {"Mono ADC R Mux", "ADC2 R", "ADC2 R"},
3435
3436 {"Mono DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"},
3437 {"Mono DD L Mux", "MONO DAC", "Mono DAC MIXL"},
3438
3439 {"Mono DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"},
3440 {"Mono DD R Mux", "MONO DAC", "Mono DAC MIXR"},
3441
3442 {"Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux"},
3443 {"Mono ADC L2 Mux", "DAC MIXL", "DAC MIXL"},
3444 {"Mono ADC L1 Mux", "DD Mux", "Mono DD L Mux"},
3445 {"Mono ADC L1 Mux", "ADC", "Mono ADC L Mux"},
3446
3447 {"Mono ADC R1 Mux", "DD Mux", "Mono DD R Mux"},
3448 {"Mono ADC R1 Mux", "ADC", "Mono ADC R Mux"},
3449 {"Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux"},
3450 {"Mono ADC R2 Mux", "DAC MIXR", "DAC MIXR"},
3451
3452 {"Stereo2 ADC L Mux", "ADC1 L", "ADC1 L"},
3453 {"Stereo2 ADC L Mux", "ADC2 L", "ADC2 L"},
3454 {"Stereo2 ADC L Mux", "ADC1 R", "ADC1 R"},
3455 {"Stereo2 ADC R Mux", "ADC1 L", "ADC1 L"},
3456 {"Stereo2 ADC R Mux", "ADC2 L", "ADC2 L"},
3457 {"Stereo2 ADC R Mux", "ADC1 R", "ADC1 R"},
3458
3459 {"Stereo2 DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"},
3460 {"Stereo2 DD L Mux", "MONO DAC", "Mono DAC MIXL"},
3461
3462 {"Stereo2 DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"},
3463 {"Stereo2 DD R Mux", "MONO DAC", "Mono DAC MIXR"},
3464
3465 {"Stereo2 ADC L1 Mux", "ADC", "Stereo2 ADC L Mux"},
3466 {"Stereo2 ADC L1 Mux", "DD Mux", "Stereo2 DD L Mux"},
3467 {"Stereo2 ADC L2 Mux", "DMIC", "Stereo2 DMIC L Mux"},
3468 {"Stereo2 ADC L2 Mux", "DAC MIX", "DAC MIXL"},
3469
3470 {"Stereo2 ADC R1 Mux", "ADC", "Stereo2 ADC R Mux"},
3471 {"Stereo2 ADC R1 Mux", "DD Mux", "Stereo2 DD R Mux"},
3472 {"Stereo2 ADC R2 Mux", "DMIC", "Stereo2 DMIC R Mux"},
3473 {"Stereo2 ADC R2 Mux", "DAC MIX", "DAC MIXR"},
3474
3475 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
3476 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
3477 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
3478
3479 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
3480 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
3481 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
3482
3483 {"Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux"},
3484 {"Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux"},
3485 {"Mono ADC MIXL", NULL, "ADC Mono Left Filter"},
3486
3487 {"Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux"},
3488 {"Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux"},
3489 {"Mono ADC MIXR", NULL, "ADC Mono Right Filter"},
3490
3491 {"Stereo2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC L1 Mux"},
3492 {"Stereo2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC L2 Mux"},
3493 {"Stereo2 ADC MIXL", NULL, "ADC Stereo2 Filter"},
3494
3495 {"Stereo2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC R1 Mux"},
3496 {"Stereo2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC R2 Mux"},
3497 {"Stereo2 ADC MIXR", NULL, "ADC Stereo2 Filter"},
3498
3499 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
3500 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
3501 {"Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL"},
3502 {"Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR"},
3503 {"Mono ADC MIX", NULL, "Mono ADC MIXL"},
3504 {"Mono ADC MIX", NULL, "Mono ADC MIXR"},
3505
3506 {"IF1_1_ADC1 Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3507 {"IF1_1_ADC1 Mux", "IF2_1 DAC", "IF2_1 DAC"},
3508 {"IF1_1_ADC2 Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3509 {"IF1_1_ADC2 Mux", "IF2_2 DAC", "IF2_2 DAC"},
3510 {"IF1_1_ADC3 Mux", "MONO ADC", "Mono ADC MIX"},
3511 {"IF1_1_ADC3 Mux", "IF3 DAC", "IF3 DAC"},
3512 {"IF1_1_ADC4", NULL, "DAC1 MIX"},
3513
3514 {"IF1_2_ADC1 Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3515 {"IF1_2_ADC1 Mux", "IF1 DAC", "IF1 DAC1"},
3516 {"IF1_2_ADC2 Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3517 {"IF1_2_ADC2 Mux", "IF2_1 DAC", "IF2_1 DAC"},
3518 {"IF1_2_ADC3 Mux", "MONO ADC", "Mono ADC MIX"},
3519 {"IF1_2_ADC3 Mux", "IF2_2 DAC", "IF2_2 DAC"},
3520 {"IF1_2_ADC4 Mux", "DAC1", "DAC1 MIX"},
3521 {"IF1_2_ADC4 Mux", "IF3 DAC", "IF3 DAC"},
3522
3523 {"TDM1 slot 01 Data Mux", "1234", "IF1_1_ADC1 Mux"},
3524 {"TDM1 slot 01 Data Mux", "1243", "IF1_1_ADC1 Mux"},
3525 {"TDM1 slot 01 Data Mux", "1324", "IF1_1_ADC1 Mux"},
3526 {"TDM1 slot 01 Data Mux", "1342", "IF1_1_ADC1 Mux"},
3527 {"TDM1 slot 01 Data Mux", "1432", "IF1_1_ADC1 Mux"},
3528 {"TDM1 slot 01 Data Mux", "1423", "IF1_1_ADC1 Mux"},
3529 {"TDM1 slot 01 Data Mux", "2134", "IF1_1_ADC2 Mux"},
3530 {"TDM1 slot 01 Data Mux", "2143", "IF1_1_ADC2 Mux"},
3531 {"TDM1 slot 01 Data Mux", "2314", "IF1_1_ADC2 Mux"},
3532 {"TDM1 slot 01 Data Mux", "2341", "IF1_1_ADC2 Mux"},
3533 {"TDM1 slot 01 Data Mux", "2431", "IF1_1_ADC2 Mux"},
3534 {"TDM1 slot 01 Data Mux", "2413", "IF1_1_ADC2 Mux"},
3535 {"TDM1 slot 01 Data Mux", "3124", "IF1_1_ADC3 Mux"},
3536 {"TDM1 slot 01 Data Mux", "3142", "IF1_1_ADC3 Mux"},
3537 {"TDM1 slot 01 Data Mux", "3214", "IF1_1_ADC3 Mux"},
3538 {"TDM1 slot 01 Data Mux", "3241", "IF1_1_ADC3 Mux"},
3539 {"TDM1 slot 01 Data Mux", "3412", "IF1_1_ADC3 Mux"},
3540 {"TDM1 slot 01 Data Mux", "3421", "IF1_1_ADC3 Mux"},
3541 {"TDM1 slot 01 Data Mux", "4123", "IF1_1_ADC4"},
3542 {"TDM1 slot 01 Data Mux", "4132", "IF1_1_ADC4"},
3543 {"TDM1 slot 01 Data Mux", "4213", "IF1_1_ADC4"},
3544 {"TDM1 slot 01 Data Mux", "4231", "IF1_1_ADC4"},
3545 {"TDM1 slot 01 Data Mux", "4312", "IF1_1_ADC4"},
3546 {"TDM1 slot 01 Data Mux", "4321", "IF1_1_ADC4"},
3547 {"TDM1 slot 01 Data Mux", NULL, "I2S1_1"},
3548
3549 {"TDM1 slot 23 Data Mux", "1234", "IF1_1_ADC2 Mux"},
3550 {"TDM1 slot 23 Data Mux", "1243", "IF1_1_ADC2 Mux"},
3551 {"TDM1 slot 23 Data Mux", "1324", "IF1_1_ADC3 Mux"},
3552 {"TDM1 slot 23 Data Mux", "1342", "IF1_1_ADC3 Mux"},
3553 {"TDM1 slot 23 Data Mux", "1432", "IF1_1_ADC4"},
3554 {"TDM1 slot 23 Data Mux", "1423", "IF1_1_ADC4"},
3555 {"TDM1 slot 23 Data Mux", "2134", "IF1_1_ADC1 Mux"},
3556 {"TDM1 slot 23 Data Mux", "2143", "IF1_1_ADC1 Mux"},
3557 {"TDM1 slot 23 Data Mux", "2314", "IF1_1_ADC3 Mux"},
3558 {"TDM1 slot 23 Data Mux", "2341", "IF1_1_ADC3 Mux"},
3559 {"TDM1 slot 23 Data Mux", "2431", "IF1_1_ADC4"},
3560 {"TDM1 slot 23 Data Mux", "2413", "IF1_1_ADC4"},
3561 {"TDM1 slot 23 Data Mux", "3124", "IF1_1_ADC1 Mux"},
3562 {"TDM1 slot 23 Data Mux", "3142", "IF1_1_ADC1 Mux"},
3563 {"TDM1 slot 23 Data Mux", "3214", "IF1_1_ADC2 Mux"},
3564 {"TDM1 slot 23 Data Mux", "3241", "IF1_1_ADC2 Mux"},
3565 {"TDM1 slot 23 Data Mux", "3412", "IF1_1_ADC4"},
3566 {"TDM1 slot 23 Data Mux", "3421", "IF1_1_ADC4"},
3567 {"TDM1 slot 23 Data Mux", "4123", "IF1_1_ADC1 Mux"},
3568 {"TDM1 slot 23 Data Mux", "4132", "IF1_1_ADC1 Mux"},
3569 {"TDM1 slot 23 Data Mux", "4213", "IF1_1_ADC2 Mux"},
3570 {"TDM1 slot 23 Data Mux", "4231", "IF1_1_ADC2 Mux"},
3571 {"TDM1 slot 23 Data Mux", "4312", "IF1_1_ADC3 Mux"},
3572 {"TDM1 slot 23 Data Mux", "4321", "IF1_1_ADC3 Mux"},
3573 {"TDM1 slot 23 Data Mux", NULL, "I2S1_1"},
3574
3575 {"TDM1 slot 45 Data Mux", "1234", "IF1_1_ADC3 Mux"},
3576 {"TDM1 slot 45 Data Mux", "1243", "IF1_1_ADC4"},
3577 {"TDM1 slot 45 Data Mux", "1324", "IF1_1_ADC2 Mux"},
3578 {"TDM1 slot 45 Data Mux", "1342", "IF1_1_ADC4"},
3579 {"TDM1 slot 45 Data Mux", "1432", "IF1_1_ADC3 Mux"},
3580 {"TDM1 slot 45 Data Mux", "1423", "IF1_1_ADC2 Mux"},
3581 {"TDM1 slot 45 Data Mux", "2134", "IF1_1_ADC3 Mux"},
3582 {"TDM1 slot 45 Data Mux", "2143", "IF1_1_ADC4"},
3583 {"TDM1 slot 45 Data Mux", "2314", "IF1_1_ADC1 Mux"},
3584 {"TDM1 slot 45 Data Mux", "2341", "IF1_1_ADC4"},
3585 {"TDM1 slot 45 Data Mux", "2431", "IF1_1_ADC3 Mux"},
3586 {"TDM1 slot 45 Data Mux", "2413", "IF1_1_ADC1 Mux"},
3587 {"TDM1 slot 45 Data Mux", "3124", "IF1_1_ADC2 Mux"},
3588 {"TDM1 slot 45 Data Mux", "3142", "IF1_1_ADC4"},
3589 {"TDM1 slot 45 Data Mux", "3214", "IF1_1_ADC1 Mux"},
3590 {"TDM1 slot 45 Data Mux", "3241", "IF1_1_ADC4"},
3591 {"TDM1 slot 45 Data Mux", "3412", "IF1_1_ADC1 Mux"},
3592 {"TDM1 slot 45 Data Mux", "3421", "IF1_1_ADC2 Mux"},
3593 {"TDM1 slot 45 Data Mux", "4123", "IF1_1_ADC2 Mux"},
3594 {"TDM1 slot 45 Data Mux", "4132", "IF1_1_ADC3 Mux"},
3595 {"TDM1 slot 45 Data Mux", "4213", "IF1_1_ADC1 Mux"},
3596 {"TDM1 slot 45 Data Mux", "4231", "IF1_1_ADC3 Mux"},
3597 {"TDM1 slot 45 Data Mux", "4312", "IF1_1_ADC1 Mux"},
3598 {"TDM1 slot 45 Data Mux", "4321", "IF1_1_ADC2 Mux"},
3599 {"TDM1 slot 45 Data Mux", NULL, "I2S1_1"},
3600
3601 {"TDM1 slot 67 Data Mux", "1234", "IF1_1_ADC4"},
3602 {"TDM1 slot 67 Data Mux", "1243", "IF1_1_ADC3 Mux"},
3603 {"TDM1 slot 67 Data Mux", "1324", "IF1_1_ADC4"},
3604 {"TDM1 slot 67 Data Mux", "1342", "IF1_1_ADC2 Mux"},
3605 {"TDM1 slot 67 Data Mux", "1432", "IF1_1_ADC2 Mux"},
3606 {"TDM1 slot 67 Data Mux", "1423", "IF1_1_ADC3 Mux"},
3607 {"TDM1 slot 67 Data Mux", "2134", "IF1_1_ADC4"},
3608 {"TDM1 slot 67 Data Mux", "2143", "IF1_1_ADC3 Mux"},
3609 {"TDM1 slot 67 Data Mux", "2314", "IF1_1_ADC4"},
3610 {"TDM1 slot 67 Data Mux", "2341", "IF1_1_ADC1 Mux"},
3611 {"TDM1 slot 67 Data Mux", "2431", "IF1_1_ADC1 Mux"},
3612 {"TDM1 slot 67 Data Mux", "2413", "IF1_1_ADC3 Mux"},
3613 {"TDM1 slot 67 Data Mux", "3124", "IF1_1_ADC4"},
3614 {"TDM1 slot 67 Data Mux", "3142", "IF1_1_ADC2 Mux"},
3615 {"TDM1 slot 67 Data Mux", "3214", "IF1_1_ADC4"},
3616 {"TDM1 slot 67 Data Mux", "3241", "IF1_1_ADC1 Mux"},
3617 {"TDM1 slot 67 Data Mux", "3412", "IF1_1_ADC2 Mux"},
3618 {"TDM1 slot 67 Data Mux", "3421", "IF1_1_ADC1 Mux"},
3619 {"TDM1 slot 67 Data Mux", "4123", "IF1_1_ADC3 Mux"},
3620 {"TDM1 slot 67 Data Mux", "4132", "IF1_1_ADC2 Mux"},
3621 {"TDM1 slot 67 Data Mux", "4213", "IF1_1_ADC3 Mux"},
3622 {"TDM1 slot 67 Data Mux", "4231", "IF1_1_ADC1 Mux"},
3623 {"TDM1 slot 67 Data Mux", "4312", "IF1_1_ADC2 Mux"},
3624 {"TDM1 slot 67 Data Mux", "4321", "IF1_1_ADC1 Mux"},
3625 {"TDM1 slot 67 Data Mux", NULL, "I2S1_1"},
3626
3627
3628 {"TDM2 slot 01 Data Mux", "1234", "IF1_2_ADC1 Mux"},
3629 {"TDM2 slot 01 Data Mux", "1243", "IF1_2_ADC1 Mux"},
3630 {"TDM2 slot 01 Data Mux", "1324", "IF1_2_ADC1 Mux"},
3631 {"TDM2 slot 01 Data Mux", "1342", "IF1_2_ADC1 Mux"},
3632 {"TDM2 slot 01 Data Mux", "1432", "IF1_2_ADC1 Mux"},
3633 {"TDM2 slot 01 Data Mux", "1423", "IF1_2_ADC1 Mux"},
3634 {"TDM2 slot 01 Data Mux", "2134", "IF1_2_ADC2 Mux"},
3635 {"TDM2 slot 01 Data Mux", "2143", "IF1_2_ADC2 Mux"},
3636 {"TDM2 slot 01 Data Mux", "2314", "IF1_2_ADC2 Mux"},
3637 {"TDM2 slot 01 Data Mux", "2341", "IF1_2_ADC2 Mux"},
3638 {"TDM2 slot 01 Data Mux", "2431", "IF1_2_ADC2 Mux"},
3639 {"TDM2 slot 01 Data Mux", "2413", "IF1_2_ADC2 Mux"},
3640 {"TDM2 slot 01 Data Mux", "3124", "IF1_2_ADC3 Mux"},
3641 {"TDM2 slot 01 Data Mux", "3142", "IF1_2_ADC3 Mux"},
3642 {"TDM2 slot 01 Data Mux", "3214", "IF1_2_ADC3 Mux"},
3643 {"TDM2 slot 01 Data Mux", "3241", "IF1_2_ADC3 Mux"},
3644 {"TDM2 slot 01 Data Mux", "3412", "IF1_2_ADC3 Mux"},
3645 {"TDM2 slot 01 Data Mux", "3421", "IF1_2_ADC3 Mux"},
3646 {"TDM2 slot 01 Data Mux", "4123", "IF1_2_ADC4 Mux"},
3647 {"TDM2 slot 01 Data Mux", "4132", "IF1_2_ADC4 Mux"},
3648 {"TDM2 slot 01 Data Mux", "4213", "IF1_2_ADC4 Mux"},
3649 {"TDM2 slot 01 Data Mux", "4231", "IF1_2_ADC4 Mux"},
3650 {"TDM2 slot 01 Data Mux", "4312", "IF1_2_ADC4 Mux"},
3651 {"TDM2 slot 01 Data Mux", "4321", "IF1_2_ADC4 Mux"},
3652 {"TDM2 slot 01 Data Mux", NULL, "I2S1_2"},
3653
3654 {"TDM2 slot 23 Data Mux", "1234", "IF1_2_ADC2 Mux"},
3655 {"TDM2 slot 23 Data Mux", "1243", "IF1_2_ADC2 Mux"},
3656 {"TDM2 slot 23 Data Mux", "1324", "IF1_2_ADC3 Mux"},
3657 {"TDM2 slot 23 Data Mux", "1342", "IF1_2_ADC3 Mux"},
3658 {"TDM2 slot 23 Data Mux", "1432", "IF1_2_ADC4 Mux"},
3659 {"TDM2 slot 23 Data Mux", "1423", "IF1_2_ADC4 Mux"},
3660 {"TDM2 slot 23 Data Mux", "2134", "IF1_2_ADC1 Mux"},
3661 {"TDM2 slot 23 Data Mux", "2143", "IF1_2_ADC1 Mux"},
3662 {"TDM2 slot 23 Data Mux", "2314", "IF1_2_ADC3 Mux"},
3663 {"TDM2 slot 23 Data Mux", "2341", "IF1_2_ADC3 Mux"},
3664 {"TDM2 slot 23 Data Mux", "2431", "IF1_2_ADC4 Mux"},
3665 {"TDM2 slot 23 Data Mux", "2413", "IF1_2_ADC4 Mux"},
3666 {"TDM2 slot 23 Data Mux", "3124", "IF1_2_ADC1 Mux"},
3667 {"TDM2 slot 23 Data Mux", "3142", "IF1_2_ADC1 Mux"},
3668 {"TDM2 slot 23 Data Mux", "3214", "IF1_2_ADC2 Mux"},
3669 {"TDM2 slot 23 Data Mux", "3241", "IF1_2_ADC2 Mux"},
3670 {"TDM2 slot 23 Data Mux", "3412", "IF1_2_ADC4 Mux"},
3671 {"TDM2 slot 23 Data Mux", "3421", "IF1_2_ADC4 Mux"},
3672 {"TDM2 slot 23 Data Mux", "4123", "IF1_2_ADC1 Mux"},
3673 {"TDM2 slot 23 Data Mux", "4132", "IF1_2_ADC1 Mux"},
3674 {"TDM2 slot 23 Data Mux", "4213", "IF1_2_ADC2 Mux"},
3675 {"TDM2 slot 23 Data Mux", "4231", "IF1_2_ADC2 Mux"},
3676 {"TDM2 slot 23 Data Mux", "4312", "IF1_2_ADC3 Mux"},
3677 {"TDM2 slot 23 Data Mux", "4321", "IF1_2_ADC3 Mux"},
3678 {"TDM2 slot 23 Data Mux", NULL, "I2S1_2"},
3679
3680 {"TDM2 slot 45 Data Mux", "1234", "IF1_2_ADC3 Mux"},
3681 {"TDM2 slot 45 Data Mux", "1243", "IF1_2_ADC4 Mux"},
3682 {"TDM2 slot 45 Data Mux", "1324", "IF1_2_ADC2 Mux"},
3683 {"TDM2 slot 45 Data Mux", "1342", "IF1_2_ADC4 Mux"},
3684 {"TDM2 slot 45 Data Mux", "1432", "IF1_2_ADC3 Mux"},
3685 {"TDM2 slot 45 Data Mux", "1423", "IF1_2_ADC2 Mux"},
3686 {"TDM2 slot 45 Data Mux", "2134", "IF1_2_ADC3 Mux"},
3687 {"TDM2 slot 45 Data Mux", "2143", "IF1_2_ADC4 Mux"},
3688 {"TDM2 slot 45 Data Mux", "2314", "IF1_2_ADC1 Mux"},
3689 {"TDM2 slot 45 Data Mux", "2341", "IF1_2_ADC4 Mux"},
3690 {"TDM2 slot 45 Data Mux", "2431", "IF1_2_ADC3 Mux"},
3691 {"TDM2 slot 45 Data Mux", "2413", "IF1_2_ADC1 Mux"},
3692 {"TDM2 slot 45 Data Mux", "3124", "IF1_2_ADC2 Mux"},
3693 {"TDM2 slot 45 Data Mux", "3142", "IF1_2_ADC4 Mux"},
3694 {"TDM2 slot 45 Data Mux", "3214", "IF1_2_ADC1 Mux"},
3695 {"TDM2 slot 45 Data Mux", "3241", "IF1_2_ADC4 Mux"},
3696 {"TDM2 slot 45 Data Mux", "3412", "IF1_2_ADC1 Mux"},
3697 {"TDM2 slot 45 Data Mux", "3421", "IF1_2_ADC2 Mux"},
3698 {"TDM2 slot 45 Data Mux", "4123", "IF1_2_ADC2 Mux"},
3699 {"TDM2 slot 45 Data Mux", "4132", "IF1_2_ADC3 Mux"},
3700 {"TDM2 slot 45 Data Mux", "4213", "IF1_2_ADC1 Mux"},
3701 {"TDM2 slot 45 Data Mux", "4231", "IF1_2_ADC3 Mux"},
3702 {"TDM2 slot 45 Data Mux", "4312", "IF1_2_ADC1 Mux"},
3703 {"TDM2 slot 45 Data Mux", "4321", "IF1_2_ADC2 Mux"},
3704 {"TDM2 slot 45 Data Mux", NULL, "I2S1_2"},
3705
3706 {"TDM2 slot 67 Data Mux", "1234", "IF1_2_ADC4 Mux"},
3707 {"TDM2 slot 67 Data Mux", "1243", "IF1_2_ADC3 Mux"},
3708 {"TDM2 slot 67 Data Mux", "1324", "IF1_2_ADC4 Mux"},
3709 {"TDM2 slot 67 Data Mux", "1342", "IF1_2_ADC2 Mux"},
3710 {"TDM2 slot 67 Data Mux", "1432", "IF1_2_ADC2 Mux"},
3711 {"TDM2 slot 67 Data Mux", "1423", "IF1_2_ADC3 Mux"},
3712 {"TDM2 slot 67 Data Mux", "2134", "IF1_2_ADC4 Mux"},
3713 {"TDM2 slot 67 Data Mux", "2143", "IF1_2_ADC3 Mux"},
3714 {"TDM2 slot 67 Data Mux", "2314", "IF1_2_ADC4 Mux"},
3715 {"TDM2 slot 67 Data Mux", "2341", "IF1_2_ADC1 Mux"},
3716 {"TDM2 slot 67 Data Mux", "2431", "IF1_2_ADC1 Mux"},
3717 {"TDM2 slot 67 Data Mux", "2413", "IF1_2_ADC3 Mux"},
3718 {"TDM2 slot 67 Data Mux", "3124", "IF1_2_ADC4 Mux"},
3719 {"TDM2 slot 67 Data Mux", "3142", "IF1_2_ADC2 Mux"},
3720 {"TDM2 slot 67 Data Mux", "3214", "IF1_2_ADC4 Mux"},
3721 {"TDM2 slot 67 Data Mux", "3241", "IF1_2_ADC1 Mux"},
3722 {"TDM2 slot 67 Data Mux", "3412", "IF1_2_ADC2 Mux"},
3723 {"TDM2 slot 67 Data Mux", "3421", "IF1_2_ADC1 Mux"},
3724 {"TDM2 slot 67 Data Mux", "4123", "IF1_2_ADC3 Mux"},
3725 {"TDM2 slot 67 Data Mux", "4132", "IF1_2_ADC2 Mux"},
3726 {"TDM2 slot 67 Data Mux", "4213", "IF1_2_ADC3 Mux"},
3727 {"TDM2 slot 67 Data Mux", "4231", "IF1_2_ADC1 Mux"},
3728 {"TDM2 slot 67 Data Mux", "4312", "IF1_2_ADC2 Mux"},
3729 {"TDM2 slot 67 Data Mux", "4321", "IF1_2_ADC1 Mux"},
3730 {"TDM2 slot 67 Data Mux", NULL, "I2S1_2"},
3731
3732 {"IF1_1 0 ADC Swap Mux", "L/R", "TDM1 slot 01 Data Mux"},
3733 {"IF1_1 0 ADC Swap Mux", "L/L", "TDM1 slot 01 Data Mux"},
3734 {"IF1_1 1 ADC Swap Mux", "R/L", "TDM1 slot 01 Data Mux"},
3735 {"IF1_1 1 ADC Swap Mux", "R/R", "TDM1 slot 01 Data Mux"},
3736 {"IF1_1 2 ADC Swap Mux", "L/R", "TDM1 slot 23 Data Mux"},
3737 {"IF1_1 2 ADC Swap Mux", "R/L", "TDM1 slot 23 Data Mux"},
3738 {"IF1_1 3 ADC Swap Mux", "L/L", "TDM1 slot 23 Data Mux"},
3739 {"IF1_1 3 ADC Swap Mux", "R/R", "TDM1 slot 23 Data Mux"},
3740 {"IF1_1 4 ADC Swap Mux", "L/R", "TDM1 slot 45 Data Mux"},
3741 {"IF1_1 4 ADC Swap Mux", "R/L", "TDM1 slot 45 Data Mux"},
3742 {"IF1_1 5 ADC Swap Mux", "L/L", "TDM1 slot 45 Data Mux"},
3743 {"IF1_1 5 ADC Swap Mux", "R/R", "TDM1 slot 45 Data Mux"},
3744 {"IF1_1 6 ADC Swap Mux", "L/R", "TDM1 slot 67 Data Mux"},
3745 {"IF1_1 6 ADC Swap Mux", "R/L", "TDM1 slot 67 Data Mux"},
3746 {"IF1_1 7 ADC Swap Mux", "L/L", "TDM1 slot 67 Data Mux"},
3747 {"IF1_1 7 ADC Swap Mux", "R/R", "TDM1 slot 67 Data Mux"},
3748 {"IF1_2 0 ADC Swap Mux", "L/R", "TDM2 slot 01 Data Mux"},
3749 {"IF1_2 0 ADC Swap Mux", "R/L", "TDM2 slot 01 Data Mux"},
3750 {"IF1_2 1 ADC Swap Mux", "L/L", "TDM2 slot 01 Data Mux"},
3751 {"IF1_2 1 ADC Swap Mux", "R/R", "TDM2 slot 01 Data Mux"},
3752 {"IF1_2 2 ADC Swap Mux", "L/R", "TDM2 slot 23 Data Mux"},
3753 {"IF1_2 2 ADC Swap Mux", "R/L", "TDM2 slot 23 Data Mux"},
3754 {"IF1_2 3 ADC Swap Mux", "L/L", "TDM2 slot 23 Data Mux"},
3755 {"IF1_2 3 ADC Swap Mux", "R/R", "TDM2 slot 23 Data Mux"},
3756 {"IF1_2 4 ADC Swap Mux", "L/R", "TDM2 slot 45 Data Mux"},
3757 {"IF1_2 4 ADC Swap Mux", "R/L", "TDM2 slot 45 Data Mux"},
3758 {"IF1_2 5 ADC Swap Mux", "L/L", "TDM2 slot 45 Data Mux"},
3759 {"IF1_2 5 ADC Swap Mux", "R/R", "TDM2 slot 45 Data Mux"},
3760 {"IF1_2 6 ADC Swap Mux", "L/R", "TDM2 slot 67 Data Mux"},
3761 {"IF1_2 6 ADC Swap Mux", "R/L", "TDM2 slot 67 Data Mux"},
3762 {"IF1_2 7 ADC Swap Mux", "L/L", "TDM2 slot 67 Data Mux"},
3763 {"IF1_2 7 ADC Swap Mux", "R/R", "TDM2 slot 67 Data Mux"},
3764
3765 {"IF2_1 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3766 {"IF2_1 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3767 {"IF2_1 ADC Mux", "MONO ADC", "Mono ADC MIX"},
3768 {"IF2_1 ADC Mux", "IF1 DAC1", "IF1 DAC1"},
3769 {"IF2_1 ADC Mux", "IF1 DAC2", "IF1 DAC2"},
3770 {"IF2_1 ADC Mux", "IF2_2 DAC", "IF2_2 DAC"},
3771 {"IF2_1 ADC Mux", "IF3 DAC", "IF3 DAC"},
3772 {"IF2_1 ADC Mux", "DAC1 MIX", "DAC1 MIX"},
3773 {"IF2_1 ADC", NULL, "IF2_1 ADC Mux"},
3774 {"IF2_1 ADC", NULL, "I2S2_1"},
3775
3776 {"IF2_2 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3777 {"IF2_2 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3778 {"IF2_2 ADC Mux", "MONO ADC", "Mono ADC MIX"},
3779 {"IF2_2 ADC Mux", "IF1 DAC1", "IF1 DAC1"},
3780 {"IF2_2 ADC Mux", "IF1 DAC2", "IF1 DAC2"},
3781 {"IF2_2 ADC Mux", "IF2_1 DAC", "IF2_1 DAC"},
3782 {"IF2_2 ADC Mux", "IF3 DAC", "IF3 DAC"},
3783 {"IF2_2 ADC Mux", "DAC1 MIX", "DAC1 MIX"},
3784 {"IF2_2 ADC", NULL, "IF2_2 ADC Mux"},
3785 {"IF2_2 ADC", NULL, "I2S2_2"},
3786
3787 {"IF3 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3788 {"IF3 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3789 {"IF3 ADC Mux", "MONO ADC", "Mono ADC MIX"},
3790 {"IF3 ADC Mux", "IF1 DAC1", "IF1 DAC1"},
3791 {"IF3 ADC Mux", "IF1 DAC2", "IF1 DAC2"},
3792 {"IF3 ADC Mux", "IF2_1 DAC", "IF2_1 DAC"},
3793 {"IF3 ADC Mux", "IF2_2 DAC", "IF2_2 DAC"},
3794 {"IF3 ADC Mux", "DAC1 MIX", "DAC1 MIX"},
3795 {"IF3 ADC", NULL, "IF3 ADC Mux"},
3796 {"IF3 ADC", NULL, "I2S3"},
3797
3798 {"AIF1_1TX slot 0", NULL, "IF1_1 0 ADC Swap Mux"},
3799 {"AIF1_1TX slot 1", NULL, "IF1_1 1 ADC Swap Mux"},
3800 {"AIF1_1TX slot 2", NULL, "IF1_1 2 ADC Swap Mux"},
3801 {"AIF1_1TX slot 3", NULL, "IF1_1 3 ADC Swap Mux"},
3802 {"AIF1_1TX slot 4", NULL, "IF1_1 4 ADC Swap Mux"},
3803 {"AIF1_1TX slot 5", NULL, "IF1_1 5 ADC Swap Mux"},
3804 {"AIF1_1TX slot 6", NULL, "IF1_1 6 ADC Swap Mux"},
3805 {"AIF1_1TX slot 7", NULL, "IF1_1 7 ADC Swap Mux"},
3806 {"AIF1_2TX slot 0", NULL, "IF1_2 0 ADC Swap Mux"},
3807 {"AIF1_2TX slot 1", NULL, "IF1_2 1 ADC Swap Mux"},
3808 {"AIF1_2TX slot 2", NULL, "IF1_2 2 ADC Swap Mux"},
3809 {"AIF1_2TX slot 3", NULL, "IF1_2 3 ADC Swap Mux"},
3810 {"AIF1_2TX slot 4", NULL, "IF1_2 4 ADC Swap Mux"},
3811 {"AIF1_2TX slot 5", NULL, "IF1_2 5 ADC Swap Mux"},
3812 {"AIF1_2TX slot 6", NULL, "IF1_2 6 ADC Swap Mux"},
3813 {"AIF1_2TX slot 7", NULL, "IF1_2 7 ADC Swap Mux"},
3814 {"IF2_1 ADC Swap Mux", "L/R", "IF2_1 ADC"},
3815 {"IF2_1 ADC Swap Mux", "R/L", "IF2_1 ADC"},
3816 {"IF2_1 ADC Swap Mux", "L/L", "IF2_1 ADC"},
3817 {"IF2_1 ADC Swap Mux", "R/R", "IF2_1 ADC"},
3818 {"AIF2_1TX", NULL, "IF2_1 ADC Swap Mux"},
3819 {"IF2_2 ADC Swap Mux", "L/R", "IF2_2 ADC"},
3820 {"IF2_2 ADC Swap Mux", "R/L", "IF2_2 ADC"},
3821 {"IF2_2 ADC Swap Mux", "L/L", "IF2_2 ADC"},
3822 {"IF2_2 ADC Swap Mux", "R/R", "IF2_2 ADC"},
3823 {"AIF2_2TX", NULL, "IF2_2 ADC Swap Mux"},
3824 {"IF3 ADC Swap Mux", "L/R", "IF3 ADC"},
3825 {"IF3 ADC Swap Mux", "R/L", "IF3 ADC"},
3826 {"IF3 ADC Swap Mux", "L/L", "IF3 ADC"},
3827 {"IF3 ADC Swap Mux", "R/R", "IF3 ADC"},
3828 {"AIF3TX", NULL, "IF3 ADC Swap Mux"},
3829
3830 {"IF1 DAC1", NULL, "AIF1RX"},
3831 {"IF1 DAC2", NULL, "AIF1RX"},
3832 {"IF1 DAC3", NULL, "AIF1RX"},
3833 {"IF2_1 DAC Swap Mux", "L/R", "AIF2_1RX"},
3834 {"IF2_1 DAC Swap Mux", "R/L", "AIF2_1RX"},
3835 {"IF2_1 DAC Swap Mux", "L/L", "AIF2_1RX"},
3836 {"IF2_1 DAC Swap Mux", "R/R", "AIF2_1RX"},
3837 {"IF2_2 DAC Swap Mux", "L/R", "AIF2_2RX"},
3838 {"IF2_2 DAC Swap Mux", "R/L", "AIF2_2RX"},
3839 {"IF2_2 DAC Swap Mux", "L/L", "AIF2_2RX"},
3840 {"IF2_2 DAC Swap Mux", "R/R", "AIF2_2RX"},
3841 {"IF2_1 DAC", NULL, "IF2_1 DAC Swap Mux"},
3842 {"IF2_2 DAC", NULL, "IF2_2 DAC Swap Mux"},
3843 {"IF3 DAC Swap Mux", "L/R", "AIF3RX"},
3844 {"IF3 DAC Swap Mux", "R/L", "AIF3RX"},
3845 {"IF3 DAC Swap Mux", "L/L", "AIF3RX"},
3846 {"IF3 DAC Swap Mux", "R/R", "AIF3RX"},
3847 {"IF3 DAC", NULL, "IF3 DAC Swap Mux"},
3848
3849 {"IF1 DAC1", NULL, "I2S1_1"},
3850 {"IF1 DAC2", NULL, "I2S1_1"},
3851 {"IF1 DAC3", NULL, "I2S1_1"},
3852 {"IF2_1 DAC", NULL, "I2S2_1"},
3853 {"IF2_2 DAC", NULL, "I2S2_2"},
3854 {"IF3 DAC", NULL, "I2S3"},
3855
3856 {"IF1 DAC1 L", NULL, "IF1 DAC1"},
3857 {"IF1 DAC1 R", NULL, "IF1 DAC1"},
3858 {"IF1 DAC2 L", NULL, "IF1 DAC2"},
3859 {"IF1 DAC2 R", NULL, "IF1 DAC2"},
3860 {"IF1 DAC3 L", NULL, "IF1 DAC3"},
3861 {"IF1 DAC3 R", NULL, "IF1 DAC3"},
3862 {"IF2_1 DAC L", NULL, "IF2_1 DAC"},
3863 {"IF2_1 DAC R", NULL, "IF2_1 DAC"},
3864 {"IF2_2 DAC L", NULL, "IF2_2 DAC"},
3865 {"IF2_2 DAC R", NULL, "IF2_2 DAC"},
3866 {"IF3 DAC L", NULL, "IF3 DAC"},
3867 {"IF3 DAC R", NULL, "IF3 DAC"},
3868
3869 {"DAC L1 Mux", "IF1 DAC1", "IF1 DAC1 L"},
3870 {"DAC L1 Mux", "IF2_1 DAC", "IF2_1 DAC L"},
3871 {"DAC L1 Mux", "IF2_2 DAC", "IF2_2 DAC L"},
3872 {"DAC L1 Mux", "IF3 DAC", "IF3 DAC L"},
3873 {"DAC L1 Mux", NULL, "DAC Stereo1 Filter"},
3874
3875 {"DAC R1 Mux", "IF1 DAC1", "IF1 DAC1 R"},
3876 {"DAC R1 Mux", "IF2_1 DAC", "IF2_1 DAC R"},
3877 {"DAC R1 Mux", "IF2_2 DAC", "IF2_2 DAC R"},
3878 {"DAC R1 Mux", "IF3 DAC", "IF3 DAC R"},
3879 {"DAC R1 Mux", NULL, "DAC Stereo1 Filter"},
3880
3881 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
3882 {"DAC1 MIXL", "DAC1 Switch", "DAC L1 Mux"},
3883 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
3884 {"DAC1 MIXR", "DAC1 Switch", "DAC R1 Mux"},
3885
3886 {"DAC1 MIX", NULL, "DAC1 MIXL"},
3887 {"DAC1 MIX", NULL, "DAC1 MIXR"},
3888
3889 {"DAC L2 Mux", "IF1 DAC2", "IF1 DAC2 L"},
3890 {"DAC L2 Mux", "IF2_1 DAC", "IF2_1 DAC L"},
3891 {"DAC L2 Mux", "IF2_2 DAC", "IF2_2 DAC L"},
3892 {"DAC L2 Mux", "IF3 DAC", "IF3 DAC L"},
3893 {"DAC L2 Mux", "Mono ADC MIX", "Mono ADC MIXL"},
3894 {"DAC L2 Mux", NULL, "DAC Mono Left Filter"},
3895
3896 {"DAC R2 Mux", "IF1 DAC2", "IF1 DAC2 R"},
3897 {"DAC R2 Mux", "IF2_1 DAC", "IF2_1 DAC R"},
3898 {"DAC R2 Mux", "IF2_2 DAC", "IF2_2 DAC R"},
3899 {"DAC R2 Mux", "IF3 DAC", "IF3 DAC R"},
3900 {"DAC R2 Mux", "Mono ADC MIX", "Mono ADC MIXR"},
3901 {"DAC R2 Mux", NULL, "DAC Mono Right Filter"},
3902
3903 {"DAC L3 Mux", "IF1 DAC2", "IF1 DAC2 L"},
3904 {"DAC L3 Mux", "IF2_1 DAC", "IF2_1 DAC L"},
3905 {"DAC L3 Mux", "IF2_2 DAC", "IF2_2 DAC L"},
3906 {"DAC L3 Mux", "IF3 DAC", "IF3 DAC L"},
3907 {"DAC L3 Mux", "STO2 ADC MIX", "Stereo2 ADC MIXL"},
3908 {"DAC L3 Mux", NULL, "DAC Stereo2 Filter"},
3909
3910 {"DAC R3 Mux", "IF1 DAC2", "IF1 DAC2 R"},
3911 {"DAC R3 Mux", "IF2_1 DAC", "IF2_1 DAC R"},
3912 {"DAC R3 Mux", "IF2_2 DAC", "IF2_2 DAC R"},
3913 {"DAC R3 Mux", "IF3 DAC", "IF3 DAC R"},
3914 {"DAC R3 Mux", "STO2 ADC MIX", "Stereo2 ADC MIXR"},
3915 {"DAC R3 Mux", NULL, "DAC Stereo2 Filter"},
3916
3917 {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
3918 {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
3919 {"Stereo1 DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
3920 {"Stereo1 DAC MIXL", "DAC R2 Switch", "DAC R2 Mux"},
3921
3922 {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
3923 {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
3924 {"Stereo1 DAC MIXR", "DAC L2 Switch", "DAC L2 Mux"},
3925 {"Stereo1 DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
3926
3927 {"Stereo2 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
3928 {"Stereo2 DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
3929 {"Stereo2 DAC MIXL", "DAC L3 Switch", "DAC L3 Mux"},
3930
3931 {"Stereo2 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
3932 {"Stereo2 DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
3933 {"Stereo2 DAC MIXR", "DAC R3 Switch", "DAC R3 Mux"},
3934
3935 {"Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
3936 {"Mono DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
3937 {"Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
3938 {"Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Mux"},
3939 {"Mono DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
3940 {"Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
3941 {"Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Mux"},
3942 {"Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
3943
3944 {"DAC MIXL", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
3945 {"DAC MIXL", "Stereo2 DAC Mixer", "Stereo2 DAC MIXL"},
3946 {"DAC MIXL", "Mono DAC Mixer", "Mono DAC MIXL"},
3947 {"DAC MIXR", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
3948 {"DAC MIXR", "Stereo2 DAC Mixer", "Stereo2 DAC MIXR"},
3949 {"DAC MIXR", "Mono DAC Mixer", "Mono DAC MIXR"},
3950
3951 {"DAC L1 Source", "DAC1", "DAC1 MIXL"},
3952 {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
3953 {"DAC L1 Source", "DMIC1", "DMIC L1"},
3954 {"DAC R1 Source", "DAC1", "DAC1 MIXR"},
3955 {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
3956 {"DAC R1 Source", "DMIC1", "DMIC R1"},
3957
3958 {"DAC L2 Source", "DAC2", "DAC L2 Mux"},
3959 {"DAC L2 Source", "Mono DAC Mixer", "Mono DAC MIXL"},
3960 {"DAC L2 Source", NULL, "DAC L2 Power"},
3961 {"DAC R2 Source", "DAC2", "DAC R2 Mux"},
3962 {"DAC R2 Source", "Mono DAC Mixer", "Mono DAC MIXR"},
3963 {"DAC R2 Source", NULL, "DAC R2 Power"},
3964
3965 {"DAC L1", NULL, "DAC L1 Source"},
3966 {"DAC R1", NULL, "DAC R1 Source"},
3967 {"DAC L2", NULL, "DAC L2 Source"},
3968 {"DAC R2", NULL, "DAC R2 Source"},
3969
3970 {"DAC L1", NULL, "DAC 1 Clock"},
3971 {"DAC R1", NULL, "DAC 1 Clock"},
3972 {"DAC L2", NULL, "DAC 2 Clock"},
3973 {"DAC R2", NULL, "DAC 2 Clock"},
3974
3975 {"MONOVOL MIX", "DAC L2 Switch", "DAC L2"},
3976 {"MONOVOL MIX", "RECMIX2L Switch", "RECMIX2L"},
3977 {"MONOVOL MIX", "BST1 Switch", "BST1"},
3978 {"MONOVOL MIX", "BST2 Switch", "BST2"},
3979 {"MONOVOL MIX", "BST3 Switch", "BST3"},
3980
3981 {"OUT MIXL", "DAC L2 Switch", "DAC L2"},
3982 {"OUT MIXL", "INL Switch", "INL VOL"},
3983 {"OUT MIXL", "BST1 Switch", "BST1"},
3984 {"OUT MIXL", "BST2 Switch", "BST2"},
3985 {"OUT MIXL", "BST3 Switch", "BST3"},
3986 {"OUT MIXR", "DAC R2 Switch", "DAC R2"},
3987 {"OUT MIXR", "INR Switch", "INR VOL"},
3988 {"OUT MIXR", "BST2 Switch", "BST2"},
3989 {"OUT MIXR", "BST3 Switch", "BST3"},
3990 {"OUT MIXR", "BST4 Switch", "BST4"},
3991
3992 {"MONOVOL", "Switch", "MONOVOL MIX"},
3993 {"Mono MIX", "DAC L2 Switch", "DAC L2"},
3994 {"Mono MIX", "MONOVOL Switch", "MONOVOL"},
3995 {"Mono Amp", NULL, "Mono MIX"},
3996 {"Mono Amp", NULL, "Vref2"},
3997 {"Mono Amp", NULL, "Vref3"},
3998 {"Mono Amp", NULL, "CLKDET SYS"},
3999 {"Mono Amp", NULL, "CLKDET MONO"},
4000 {"Mono Playback", "Switch", "Mono Amp"},
4001 {"MONOOUT", NULL, "Mono Playback"},
4002
4003 {"HP Amp", NULL, "DAC L1"},
4004 {"HP Amp", NULL, "DAC R1"},
4005 {"HP Amp", NULL, "Charge Pump"},
4006 {"HP Amp", NULL, "CLKDET SYS"},
4007 {"HP Amp", NULL, "CLKDET HP"},
4008 {"HP Amp", NULL, "CBJ Power"},
4009 {"HP Amp", NULL, "Vref2"},
4010 {"HPO Playback", "Switch", "HP Amp"},
4011 {"HPOL", NULL, "HPO Playback"},
4012 {"HPOR", NULL, "HPO Playback"},
4013
4014 {"OUTVOL L", "Switch", "OUT MIXL"},
4015 {"OUTVOL R", "Switch", "OUT MIXR"},
4016 {"LOUT L MIX", "DAC L2 Switch", "DAC L2"},
4017 {"LOUT L MIX", "OUTVOL L Switch", "OUTVOL L"},
4018 {"LOUT R MIX", "DAC R2 Switch", "DAC R2"},
4019 {"LOUT R MIX", "OUTVOL R Switch", "OUTVOL R"},
4020 {"LOUT Amp", NULL, "LOUT L MIX"},
4021 {"LOUT Amp", NULL, "LOUT R MIX"},
4022 {"LOUT Amp", NULL, "Vref1"},
4023 {"LOUT Amp", NULL, "Vref2"},
4024 {"LOUT Amp", NULL, "CLKDET SYS"},
4025 {"LOUT Amp", NULL, "CLKDET LOUT"},
4026 {"LOUT L Playback", "Switch", "LOUT Amp"},
4027 {"LOUT R Playback", "Switch", "LOUT Amp"},
4028 {"LOUTL", NULL, "LOUT L Playback"},
4029 {"LOUTR", NULL, "LOUT R Playback"},
4030
4031 {"PDM L Mux", "Mono DAC", "Mono DAC MIXL"},
4032 {"PDM L Mux", "Stereo1 DAC", "Stereo1 DAC MIXL"},
4033 {"PDM L Mux", "Stereo2 DAC", "Stereo2 DAC MIXL"},
4034 {"PDM L Mux", NULL, "PDM Power"},
4035 {"PDM R Mux", "Mono DAC", "Mono DAC MIXR"},
4036 {"PDM R Mux", "Stereo1 DAC", "Stereo1 DAC MIXR"},
4037 {"PDM R Mux", "Stereo2 DAC", "Stereo2 DAC MIXR"},
4038 {"PDM R Mux", NULL, "PDM Power"},
4039 {"PDM L Playback", "Switch", "PDM L Mux"},
4040 {"PDM R Playback", "Switch", "PDM R Mux"},
4041 {"PDML", NULL, "PDM L Playback"},
4042 {"PDMR", NULL, "PDM R Playback"},
4043 };
4044
rt5665_set_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)4045 static int rt5665_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
4046 unsigned int rx_mask, int slots, int slot_width)
4047 {
4048 struct snd_soc_component *component = dai->component;
4049 unsigned int val = 0;
4050
4051 if (rx_mask || tx_mask)
4052 val |= RT5665_I2S1_MODE_TDM;
4053
4054 switch (slots) {
4055 case 4:
4056 val |= RT5665_TDM_IN_CH_4;
4057 val |= RT5665_TDM_OUT_CH_4;
4058 break;
4059 case 6:
4060 val |= RT5665_TDM_IN_CH_6;
4061 val |= RT5665_TDM_OUT_CH_6;
4062 break;
4063 case 8:
4064 val |= RT5665_TDM_IN_CH_8;
4065 val |= RT5665_TDM_OUT_CH_8;
4066 break;
4067 case 2:
4068 break;
4069 default:
4070 return -EINVAL;
4071 }
4072
4073 switch (slot_width) {
4074 case 20:
4075 val |= RT5665_TDM_IN_LEN_20;
4076 val |= RT5665_TDM_OUT_LEN_20;
4077 break;
4078 case 24:
4079 val |= RT5665_TDM_IN_LEN_24;
4080 val |= RT5665_TDM_OUT_LEN_24;
4081 break;
4082 case 32:
4083 val |= RT5665_TDM_IN_LEN_32;
4084 val |= RT5665_TDM_OUT_LEN_32;
4085 break;
4086 case 16:
4087 break;
4088 default:
4089 return -EINVAL;
4090 }
4091
4092 snd_soc_component_update_bits(component, RT5665_TDM_CTRL_1,
4093 RT5665_I2S1_MODE_MASK | RT5665_TDM_IN_CH_MASK |
4094 RT5665_TDM_OUT_CH_MASK | RT5665_TDM_IN_LEN_MASK |
4095 RT5665_TDM_OUT_LEN_MASK, val);
4096
4097 return 0;
4098 }
4099
4100
rt5665_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)4101 static int rt5665_hw_params(struct snd_pcm_substream *substream,
4102 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
4103 {
4104 struct snd_soc_component *component = dai->component;
4105 struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
4106 unsigned int val_len = 0, val_clk, reg_clk, mask_clk, val_bits = 0x0100;
4107 int pre_div, frame_size;
4108
4109 rt5665->lrck[dai->id] = params_rate(params);
4110 pre_div = rl6231_get_clk_info(rt5665->sysclk, rt5665->lrck[dai->id]);
4111 if (pre_div < 0) {
4112 dev_warn(component->dev, "Force using PLL");
4113 snd_soc_component_set_pll(component, 0, RT5665_PLL1_S_MCLK,
4114 rt5665->sysclk, rt5665->lrck[dai->id] * 512);
4115 snd_soc_component_set_sysclk(component, RT5665_SCLK_S_PLL1, 0,
4116 rt5665->lrck[dai->id] * 512, 0);
4117 pre_div = 1;
4118 }
4119 frame_size = snd_soc_params_to_frame_size(params);
4120 if (frame_size < 0) {
4121 dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);
4122 return -EINVAL;
4123 }
4124
4125 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
4126 rt5665->lrck[dai->id], pre_div, dai->id);
4127
4128 switch (params_width(params)) {
4129 case 16:
4130 val_bits = 0x0100;
4131 break;
4132 case 20:
4133 val_len |= RT5665_I2S_DL_20;
4134 val_bits = 0x1300;
4135 break;
4136 case 24:
4137 val_len |= RT5665_I2S_DL_24;
4138 val_bits = 0x2500;
4139 break;
4140 case 8:
4141 val_len |= RT5665_I2S_DL_8;
4142 break;
4143 default:
4144 return -EINVAL;
4145 }
4146
4147 switch (dai->id) {
4148 case RT5665_AIF1_1:
4149 case RT5665_AIF1_2:
4150 if (params_channels(params) > 2)
4151 rt5665_set_tdm_slot(dai, 0xf, 0xf,
4152 params_channels(params), params_width(params));
4153 reg_clk = RT5665_ADDA_CLK_1;
4154 mask_clk = RT5665_I2S_PD1_MASK;
4155 val_clk = pre_div << RT5665_I2S_PD1_SFT;
4156 snd_soc_component_update_bits(component, RT5665_I2S1_SDP,
4157 RT5665_I2S_DL_MASK, val_len);
4158 break;
4159 case RT5665_AIF2_1:
4160 case RT5665_AIF2_2:
4161 reg_clk = RT5665_ADDA_CLK_2;
4162 mask_clk = RT5665_I2S_PD2_MASK;
4163 val_clk = pre_div << RT5665_I2S_PD2_SFT;
4164 snd_soc_component_update_bits(component, RT5665_I2S2_SDP,
4165 RT5665_I2S_DL_MASK, val_len);
4166 break;
4167 case RT5665_AIF3:
4168 reg_clk = RT5665_ADDA_CLK_2;
4169 mask_clk = RT5665_I2S_PD3_MASK;
4170 val_clk = pre_div << RT5665_I2S_PD3_SFT;
4171 snd_soc_component_update_bits(component, RT5665_I2S3_SDP,
4172 RT5665_I2S_DL_MASK, val_len);
4173 break;
4174 default:
4175 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
4176 return -EINVAL;
4177 }
4178
4179 snd_soc_component_update_bits(component, reg_clk, mask_clk, val_clk);
4180 snd_soc_component_update_bits(component, RT5665_STO1_DAC_SIL_DET, 0x3700, val_bits);
4181
4182 switch (rt5665->lrck[dai->id]) {
4183 case 192000:
4184 snd_soc_component_update_bits(component, RT5665_ADDA_CLK_1,
4185 RT5665_DAC_OSR_MASK | RT5665_ADC_OSR_MASK,
4186 RT5665_DAC_OSR_32 | RT5665_ADC_OSR_32);
4187 break;
4188 case 96000:
4189 snd_soc_component_update_bits(component, RT5665_ADDA_CLK_1,
4190 RT5665_DAC_OSR_MASK | RT5665_ADC_OSR_MASK,
4191 RT5665_DAC_OSR_64 | RT5665_ADC_OSR_64);
4192 break;
4193 default:
4194 snd_soc_component_update_bits(component, RT5665_ADDA_CLK_1,
4195 RT5665_DAC_OSR_MASK | RT5665_ADC_OSR_MASK,
4196 RT5665_DAC_OSR_128 | RT5665_ADC_OSR_128);
4197 break;
4198 }
4199
4200 if (rt5665->master[RT5665_AIF2_1] || rt5665->master[RT5665_AIF2_2]) {
4201 snd_soc_component_update_bits(component, RT5665_I2S_M_CLK_CTRL_1,
4202 RT5665_I2S2_M_PD_MASK, pre_div << RT5665_I2S2_M_PD_SFT);
4203 }
4204 if (rt5665->master[RT5665_AIF3]) {
4205 snd_soc_component_update_bits(component, RT5665_I2S_M_CLK_CTRL_1,
4206 RT5665_I2S3_M_PD_MASK, pre_div << RT5665_I2S3_M_PD_SFT);
4207 }
4208
4209 return 0;
4210 }
4211
rt5665_set_dai_fmt(struct snd_soc_dai * dai,unsigned int fmt)4212 static int rt5665_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
4213 {
4214 struct snd_soc_component *component = dai->component;
4215 struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
4216 unsigned int reg_val = 0;
4217
4218 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
4219 case SND_SOC_DAIFMT_CBP_CFP:
4220 rt5665->master[dai->id] = 1;
4221 break;
4222 case SND_SOC_DAIFMT_CBC_CFC:
4223 reg_val |= RT5665_I2S_MS_S;
4224 rt5665->master[dai->id] = 0;
4225 break;
4226 default:
4227 return -EINVAL;
4228 }
4229
4230 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
4231 case SND_SOC_DAIFMT_NB_NF:
4232 break;
4233 case SND_SOC_DAIFMT_IB_NF:
4234 reg_val |= RT5665_I2S_BP_INV;
4235 break;
4236 default:
4237 return -EINVAL;
4238 }
4239
4240 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
4241 case SND_SOC_DAIFMT_I2S:
4242 break;
4243 case SND_SOC_DAIFMT_LEFT_J:
4244 reg_val |= RT5665_I2S_DF_LEFT;
4245 break;
4246 case SND_SOC_DAIFMT_DSP_A:
4247 reg_val |= RT5665_I2S_DF_PCM_A;
4248 break;
4249 case SND_SOC_DAIFMT_DSP_B:
4250 reg_val |= RT5665_I2S_DF_PCM_B;
4251 break;
4252 default:
4253 return -EINVAL;
4254 }
4255
4256 switch (dai->id) {
4257 case RT5665_AIF1_1:
4258 case RT5665_AIF1_2:
4259 snd_soc_component_update_bits(component, RT5665_I2S1_SDP,
4260 RT5665_I2S_MS_MASK | RT5665_I2S_BP_MASK |
4261 RT5665_I2S_DF_MASK, reg_val);
4262 break;
4263 case RT5665_AIF2_1:
4264 case RT5665_AIF2_2:
4265 snd_soc_component_update_bits(component, RT5665_I2S2_SDP,
4266 RT5665_I2S_MS_MASK | RT5665_I2S_BP_MASK |
4267 RT5665_I2S_DF_MASK, reg_val);
4268 break;
4269 case RT5665_AIF3:
4270 snd_soc_component_update_bits(component, RT5665_I2S3_SDP,
4271 RT5665_I2S_MS_MASK | RT5665_I2S_BP_MASK |
4272 RT5665_I2S_DF_MASK, reg_val);
4273 break;
4274 default:
4275 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
4276 return -EINVAL;
4277 }
4278 return 0;
4279 }
4280
rt5665_set_component_sysclk(struct snd_soc_component * component,int clk_id,int source,unsigned int freq,int dir)4281 static int rt5665_set_component_sysclk(struct snd_soc_component *component, int clk_id,
4282 int source, unsigned int freq, int dir)
4283 {
4284 struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
4285 unsigned int reg_val = 0, src = 0;
4286
4287 if (freq == rt5665->sysclk && clk_id == rt5665->sysclk_src)
4288 return 0;
4289
4290 switch (clk_id) {
4291 case RT5665_SCLK_S_MCLK:
4292 reg_val |= RT5665_SCLK_SRC_MCLK;
4293 src = RT5665_CLK_SRC_MCLK;
4294 break;
4295 case RT5665_SCLK_S_PLL1:
4296 reg_val |= RT5665_SCLK_SRC_PLL1;
4297 src = RT5665_CLK_SRC_PLL1;
4298 break;
4299 case RT5665_SCLK_S_RCCLK:
4300 reg_val |= RT5665_SCLK_SRC_RCCLK;
4301 src = RT5665_CLK_SRC_RCCLK;
4302 break;
4303 default:
4304 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
4305 return -EINVAL;
4306 }
4307 snd_soc_component_update_bits(component, RT5665_GLB_CLK,
4308 RT5665_SCLK_SRC_MASK, reg_val);
4309
4310 if (rt5665->master[RT5665_AIF2_1] || rt5665->master[RT5665_AIF2_2]) {
4311 snd_soc_component_update_bits(component, RT5665_I2S_M_CLK_CTRL_1,
4312 RT5665_I2S2_SRC_MASK, src << RT5665_I2S2_SRC_SFT);
4313 }
4314 if (rt5665->master[RT5665_AIF3]) {
4315 snd_soc_component_update_bits(component, RT5665_I2S_M_CLK_CTRL_1,
4316 RT5665_I2S3_SRC_MASK, src << RT5665_I2S3_SRC_SFT);
4317 }
4318
4319 rt5665->sysclk = freq;
4320 rt5665->sysclk_src = clk_id;
4321
4322 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
4323
4324 return 0;
4325 }
4326
rt5665_set_component_pll(struct snd_soc_component * component,int pll_id,int source,unsigned int freq_in,unsigned int freq_out)4327 static int rt5665_set_component_pll(struct snd_soc_component *component, int pll_id,
4328 int source, unsigned int freq_in,
4329 unsigned int freq_out)
4330 {
4331 struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
4332 struct rl6231_pll_code pll_code;
4333 int ret;
4334
4335 if (source == rt5665->pll_src && freq_in == rt5665->pll_in &&
4336 freq_out == rt5665->pll_out)
4337 return 0;
4338
4339 if (!freq_in || !freq_out) {
4340 dev_dbg(component->dev, "PLL disabled\n");
4341
4342 rt5665->pll_in = 0;
4343 rt5665->pll_out = 0;
4344 snd_soc_component_update_bits(component, RT5665_GLB_CLK,
4345 RT5665_SCLK_SRC_MASK, RT5665_SCLK_SRC_MCLK);
4346 return 0;
4347 }
4348
4349 switch (source) {
4350 case RT5665_PLL1_S_MCLK:
4351 snd_soc_component_update_bits(component, RT5665_GLB_CLK,
4352 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_MCLK);
4353 break;
4354 case RT5665_PLL1_S_BCLK1:
4355 snd_soc_component_update_bits(component, RT5665_GLB_CLK,
4356 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_BCLK1);
4357 break;
4358 case RT5665_PLL1_S_BCLK2:
4359 snd_soc_component_update_bits(component, RT5665_GLB_CLK,
4360 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_BCLK2);
4361 break;
4362 case RT5665_PLL1_S_BCLK3:
4363 snd_soc_component_update_bits(component, RT5665_GLB_CLK,
4364 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_BCLK3);
4365 break;
4366 default:
4367 dev_err(component->dev, "Unknown PLL Source %d\n", source);
4368 return -EINVAL;
4369 }
4370
4371 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
4372 if (ret < 0) {
4373 dev_err(component->dev, "Unsupported input clock %d\n", freq_in);
4374 return ret;
4375 }
4376
4377 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
4378 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
4379 pll_code.n_code, pll_code.k_code);
4380
4381 snd_soc_component_write(component, RT5665_PLL_CTRL_1,
4382 pll_code.n_code << RT5665_PLL_N_SFT | pll_code.k_code);
4383 snd_soc_component_write(component, RT5665_PLL_CTRL_2,
4384 ((pll_code.m_bp ? 0 : pll_code.m_code) << RT5665_PLL_M_SFT) |
4385 (pll_code.m_bp << RT5665_PLL_M_BP_SFT));
4386
4387 rt5665->pll_in = freq_in;
4388 rt5665->pll_out = freq_out;
4389 rt5665->pll_src = source;
4390
4391 return 0;
4392 }
4393
rt5665_set_bclk_ratio(struct snd_soc_dai * dai,unsigned int ratio)4394 static int rt5665_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
4395 {
4396 struct snd_soc_component *component = dai->component;
4397 struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
4398
4399 dev_dbg(component->dev, "%s ratio=%d\n", __func__, ratio);
4400
4401 rt5665->bclk[dai->id] = ratio;
4402
4403 if (ratio == 64) {
4404 switch (dai->id) {
4405 case RT5665_AIF2_1:
4406 case RT5665_AIF2_2:
4407 snd_soc_component_update_bits(component, RT5665_ADDA_CLK_2,
4408 RT5665_I2S_BCLK_MS2_MASK,
4409 RT5665_I2S_BCLK_MS2_64);
4410 break;
4411 case RT5665_AIF3:
4412 snd_soc_component_update_bits(component, RT5665_ADDA_CLK_2,
4413 RT5665_I2S_BCLK_MS3_MASK,
4414 RT5665_I2S_BCLK_MS3_64);
4415 break;
4416 }
4417 }
4418
4419 return 0;
4420 }
4421
rt5665_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)4422 static int rt5665_set_bias_level(struct snd_soc_component *component,
4423 enum snd_soc_bias_level level)
4424 {
4425 struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
4426
4427 switch (level) {
4428 case SND_SOC_BIAS_PREPARE:
4429 regmap_update_bits(rt5665->regmap, RT5665_DIG_MISC,
4430 RT5665_DIG_GATE_CTRL, RT5665_DIG_GATE_CTRL);
4431 break;
4432
4433 case SND_SOC_BIAS_STANDBY:
4434 regmap_update_bits(rt5665->regmap, RT5665_PWR_DIG_1,
4435 RT5665_PWR_LDO, RT5665_PWR_LDO);
4436 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1,
4437 RT5665_PWR_MB, RT5665_PWR_MB);
4438 regmap_update_bits(rt5665->regmap, RT5665_DIG_MISC,
4439 RT5665_DIG_GATE_CTRL, 0);
4440 break;
4441 case SND_SOC_BIAS_OFF:
4442 regmap_update_bits(rt5665->regmap, RT5665_PWR_DIG_1,
4443 RT5665_PWR_LDO, 0);
4444 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1,
4445 RT5665_PWR_MB, 0);
4446 break;
4447
4448 default:
4449 break;
4450 }
4451
4452 return 0;
4453 }
4454
rt5665_probe(struct snd_soc_component * component)4455 static int rt5665_probe(struct snd_soc_component *component)
4456 {
4457 struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
4458
4459 rt5665->component = component;
4460
4461 schedule_delayed_work(&rt5665->calibrate_work, msecs_to_jiffies(100));
4462
4463 return 0;
4464 }
4465
rt5665_remove(struct snd_soc_component * component)4466 static void rt5665_remove(struct snd_soc_component *component)
4467 {
4468 struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
4469
4470 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4471 }
4472
4473 #ifdef CONFIG_PM
rt5665_suspend(struct snd_soc_component * component)4474 static int rt5665_suspend(struct snd_soc_component *component)
4475 {
4476 struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
4477
4478 regcache_cache_only(rt5665->regmap, true);
4479 regcache_mark_dirty(rt5665->regmap);
4480 return 0;
4481 }
4482
rt5665_resume(struct snd_soc_component * component)4483 static int rt5665_resume(struct snd_soc_component *component)
4484 {
4485 struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component);
4486
4487 regcache_cache_only(rt5665->regmap, false);
4488 regcache_sync(rt5665->regmap);
4489
4490 return 0;
4491 }
4492 #else
4493 #define rt5665_suspend NULL
4494 #define rt5665_resume NULL
4495 #endif
4496
4497 #define RT5665_STEREO_RATES SNDRV_PCM_RATE_8000_192000
4498 #define RT5665_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
4499 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
4500
4501 static const struct snd_soc_dai_ops rt5665_aif_dai_ops = {
4502 .hw_params = rt5665_hw_params,
4503 .set_fmt = rt5665_set_dai_fmt,
4504 .set_tdm_slot = rt5665_set_tdm_slot,
4505 .set_bclk_ratio = rt5665_set_bclk_ratio,
4506 };
4507
4508 static struct snd_soc_dai_driver rt5665_dai[] = {
4509 {
4510 .name = "rt5665-aif1_1",
4511 .id = RT5665_AIF1_1,
4512 .playback = {
4513 .stream_name = "AIF1 Playback",
4514 .channels_min = 1,
4515 .channels_max = 8,
4516 .rates = RT5665_STEREO_RATES,
4517 .formats = RT5665_FORMATS,
4518 },
4519 .capture = {
4520 .stream_name = "AIF1_1 Capture",
4521 .channels_min = 1,
4522 .channels_max = 8,
4523 .rates = RT5665_STEREO_RATES,
4524 .formats = RT5665_FORMATS,
4525 },
4526 .ops = &rt5665_aif_dai_ops,
4527 },
4528 {
4529 .name = "rt5665-aif1_2",
4530 .id = RT5665_AIF1_2,
4531 .capture = {
4532 .stream_name = "AIF1_2 Capture",
4533 .channels_min = 1,
4534 .channels_max = 8,
4535 .rates = RT5665_STEREO_RATES,
4536 .formats = RT5665_FORMATS,
4537 },
4538 .ops = &rt5665_aif_dai_ops,
4539 },
4540 {
4541 .name = "rt5665-aif2_1",
4542 .id = RT5665_AIF2_1,
4543 .playback = {
4544 .stream_name = "AIF2_1 Playback",
4545 .channels_min = 1,
4546 .channels_max = 2,
4547 .rates = RT5665_STEREO_RATES,
4548 .formats = RT5665_FORMATS,
4549 },
4550 .capture = {
4551 .stream_name = "AIF2_1 Capture",
4552 .channels_min = 1,
4553 .channels_max = 2,
4554 .rates = RT5665_STEREO_RATES,
4555 .formats = RT5665_FORMATS,
4556 },
4557 .ops = &rt5665_aif_dai_ops,
4558 },
4559 {
4560 .name = "rt5665-aif2_2",
4561 .id = RT5665_AIF2_2,
4562 .playback = {
4563 .stream_name = "AIF2_2 Playback",
4564 .channels_min = 1,
4565 .channels_max = 2,
4566 .rates = RT5665_STEREO_RATES,
4567 .formats = RT5665_FORMATS,
4568 },
4569 .capture = {
4570 .stream_name = "AIF2_2 Capture",
4571 .channels_min = 1,
4572 .channels_max = 2,
4573 .rates = RT5665_STEREO_RATES,
4574 .formats = RT5665_FORMATS,
4575 },
4576 .ops = &rt5665_aif_dai_ops,
4577 },
4578 {
4579 .name = "rt5665-aif3",
4580 .id = RT5665_AIF3,
4581 .playback = {
4582 .stream_name = "AIF3 Playback",
4583 .channels_min = 1,
4584 .channels_max = 2,
4585 .rates = RT5665_STEREO_RATES,
4586 .formats = RT5665_FORMATS,
4587 },
4588 .capture = {
4589 .stream_name = "AIF3 Capture",
4590 .channels_min = 1,
4591 .channels_max = 2,
4592 .rates = RT5665_STEREO_RATES,
4593 .formats = RT5665_FORMATS,
4594 },
4595 .ops = &rt5665_aif_dai_ops,
4596 },
4597 };
4598
4599 static const struct snd_soc_component_driver soc_component_dev_rt5665 = {
4600 .probe = rt5665_probe,
4601 .remove = rt5665_remove,
4602 .suspend = rt5665_suspend,
4603 .resume = rt5665_resume,
4604 .set_bias_level = rt5665_set_bias_level,
4605 .controls = rt5665_snd_controls,
4606 .num_controls = ARRAY_SIZE(rt5665_snd_controls),
4607 .dapm_widgets = rt5665_dapm_widgets,
4608 .num_dapm_widgets = ARRAY_SIZE(rt5665_dapm_widgets),
4609 .dapm_routes = rt5665_dapm_routes,
4610 .num_dapm_routes = ARRAY_SIZE(rt5665_dapm_routes),
4611 .set_sysclk = rt5665_set_component_sysclk,
4612 .set_pll = rt5665_set_component_pll,
4613 .set_jack = rt5665_set_jack_detect,
4614 .use_pmdown_time = 1,
4615 .endianness = 1,
4616 };
4617
4618
4619 static const struct regmap_config rt5665_regmap = {
4620 .reg_bits = 16,
4621 .val_bits = 16,
4622 .max_register = 0x0400,
4623 .volatile_reg = rt5665_volatile_register,
4624 .readable_reg = rt5665_readable_register,
4625 .cache_type = REGCACHE_MAPLE,
4626 .reg_defaults = rt5665_reg,
4627 .num_reg_defaults = ARRAY_SIZE(rt5665_reg),
4628 .use_single_read = true,
4629 .use_single_write = true,
4630 };
4631
4632 static const struct i2c_device_id rt5665_i2c_id[] = {
4633 {"rt5665"},
4634 {}
4635 };
4636 MODULE_DEVICE_TABLE(i2c, rt5665_i2c_id);
4637
rt5665_parse_dt(struct rt5665_priv * rt5665,struct device * dev)4638 static int rt5665_parse_dt(struct rt5665_priv *rt5665, struct device *dev)
4639 {
4640 rt5665->pdata.in1_diff = of_property_read_bool(dev->of_node,
4641 "realtek,in1-differential");
4642 rt5665->pdata.in2_diff = of_property_read_bool(dev->of_node,
4643 "realtek,in2-differential");
4644 rt5665->pdata.in3_diff = of_property_read_bool(dev->of_node,
4645 "realtek,in3-differential");
4646 rt5665->pdata.in4_diff = of_property_read_bool(dev->of_node,
4647 "realtek,in4-differential");
4648
4649 of_property_read_u32(dev->of_node, "realtek,dmic1-data-pin",
4650 &rt5665->pdata.dmic1_data_pin);
4651 of_property_read_u32(dev->of_node, "realtek,dmic2-data-pin",
4652 &rt5665->pdata.dmic2_data_pin);
4653 of_property_read_u32(dev->of_node, "realtek,jd-src",
4654 &rt5665->pdata.jd_src);
4655
4656 return 0;
4657 }
4658
rt5665_calibrate(struct rt5665_priv * rt5665)4659 static void rt5665_calibrate(struct rt5665_priv *rt5665)
4660 {
4661 int value, count;
4662
4663 mutex_lock(&rt5665->calibrate_mutex);
4664
4665 regcache_cache_bypass(rt5665->regmap, true);
4666
4667 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4668 regmap_write(rt5665->regmap, RT5665_BIAS_CUR_CTRL_8, 0xa602);
4669 regmap_write(rt5665->regmap, RT5665_HP_CHARGE_PUMP_1, 0x0c26);
4670 regmap_write(rt5665->regmap, RT5665_MONOMIX_IN_GAIN, 0x021f);
4671 regmap_write(rt5665->regmap, RT5665_MONO_OUT, 0x480a);
4672 regmap_write(rt5665->regmap, RT5665_PWR_MIXER, 0x083f);
4673 regmap_write(rt5665->regmap, RT5665_PWR_DIG_1, 0x0180);
4674 regmap_write(rt5665->regmap, RT5665_EJD_CTRL_1, 0x4040);
4675 regmap_write(rt5665->regmap, RT5665_HP_LOGIC_CTRL_2, 0x0000);
4676 regmap_write(rt5665->regmap, RT5665_DIG_MISC, 0x0001);
4677 regmap_write(rt5665->regmap, RT5665_MICBIAS_2, 0x0380);
4678 regmap_write(rt5665->regmap, RT5665_GLB_CLK, 0x8000);
4679 regmap_write(rt5665->regmap, RT5665_ADDA_CLK_1, 0x1000);
4680 regmap_write(rt5665->regmap, RT5665_CHOP_DAC, 0x3030);
4681 regmap_write(rt5665->regmap, RT5665_CALIB_ADC_CTRL, 0x3c05);
4682 regmap_write(rt5665->regmap, RT5665_PWR_ANLG_1, 0xaa3e);
4683 usleep_range(15000, 20000);
4684 regmap_write(rt5665->regmap, RT5665_PWR_ANLG_1, 0xfe7e);
4685 regmap_write(rt5665->regmap, RT5665_HP_CALIB_CTRL_2, 0x0321);
4686
4687 regmap_write(rt5665->regmap, RT5665_HP_CALIB_CTRL_1, 0xfc00);
4688 count = 0;
4689 while (true) {
4690 regmap_read(rt5665->regmap, RT5665_HP_CALIB_STA_1, &value);
4691 if (value & 0x8000)
4692 usleep_range(10000, 10005);
4693 else
4694 break;
4695
4696 if (count > 60) {
4697 pr_err("HP Calibration Failure\n");
4698 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4699 regcache_cache_bypass(rt5665->regmap, false);
4700 goto out_unlock;
4701 }
4702
4703 count++;
4704 }
4705
4706 regmap_write(rt5665->regmap, RT5665_MONO_AMP_CALIB_CTRL_1, 0x9e24);
4707 count = 0;
4708 while (true) {
4709 regmap_read(rt5665->regmap, RT5665_MONO_AMP_CALIB_STA1, &value);
4710 if (value & 0x8000)
4711 usleep_range(10000, 10005);
4712 else
4713 break;
4714
4715 if (count > 60) {
4716 pr_err("MONO Calibration Failure\n");
4717 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4718 regcache_cache_bypass(rt5665->regmap, false);
4719 goto out_unlock;
4720 }
4721
4722 count++;
4723 }
4724
4725 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4726 regcache_cache_bypass(rt5665->regmap, false);
4727
4728 regcache_mark_dirty(rt5665->regmap);
4729 regcache_sync(rt5665->regmap);
4730
4731 regmap_write(rt5665->regmap, RT5665_BIAS_CUR_CTRL_8, 0xa602);
4732 regmap_write(rt5665->regmap, RT5665_ASRC_8, 0x0120);
4733
4734 out_unlock:
4735 rt5665->calibration_done = true;
4736 mutex_unlock(&rt5665->calibrate_mutex);
4737 }
4738
rt5665_calibrate_handler(struct work_struct * work)4739 static void rt5665_calibrate_handler(struct work_struct *work)
4740 {
4741 struct rt5665_priv *rt5665 = container_of(work, struct rt5665_priv,
4742 calibrate_work.work);
4743
4744 while (!snd_soc_card_is_instantiated(rt5665->component->card)) {
4745 pr_debug("%s\n", __func__);
4746 usleep_range(10000, 15000);
4747 }
4748
4749 rt5665_calibrate(rt5665);
4750 }
4751
rt5665_i2c_probe(struct i2c_client * i2c)4752 static int rt5665_i2c_probe(struct i2c_client *i2c)
4753 {
4754 struct rt5665_platform_data *pdata = dev_get_platdata(&i2c->dev);
4755 struct rt5665_priv *rt5665;
4756 int ret;
4757 unsigned int val;
4758
4759 rt5665 = devm_kzalloc(&i2c->dev, sizeof(struct rt5665_priv),
4760 GFP_KERNEL);
4761
4762 if (rt5665 == NULL)
4763 return -ENOMEM;
4764
4765 i2c_set_clientdata(i2c, rt5665);
4766
4767 if (pdata)
4768 rt5665->pdata = *pdata;
4769 else
4770 rt5665_parse_dt(rt5665, &i2c->dev);
4771
4772 ret = devm_regulator_bulk_get_enable(&i2c->dev, ARRAY_SIZE(rt5665_supply_names),
4773 rt5665_supply_names);
4774 if (ret != 0) {
4775 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
4776 return ret;
4777 }
4778
4779 rt5665->gpiod_ldo1_en = devm_gpiod_get_optional(&i2c->dev,
4780 "realtek,ldo1-en",
4781 GPIOD_OUT_HIGH);
4782 if (IS_ERR(rt5665->gpiod_ldo1_en)) {
4783 dev_err(&i2c->dev, "Failed gpio request ldo1_en\n");
4784 return PTR_ERR(rt5665->gpiod_ldo1_en);
4785 }
4786
4787 /* Sleep for 300 ms miniumum */
4788 usleep_range(300000, 350000);
4789
4790 rt5665->regmap = devm_regmap_init_i2c(i2c, &rt5665_regmap);
4791 if (IS_ERR(rt5665->regmap)) {
4792 ret = PTR_ERR(rt5665->regmap);
4793 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
4794 ret);
4795 return ret;
4796 }
4797
4798 regmap_read(rt5665->regmap, RT5665_DEVICE_ID, &val);
4799 if (val != DEVICE_ID) {
4800 dev_err(&i2c->dev,
4801 "Device with ID register %x is not rt5665\n", val);
4802 return -ENODEV;
4803 }
4804
4805 regmap_read(rt5665->regmap, RT5665_RESET, &val);
4806 switch (val) {
4807 case 0x0:
4808 rt5665->id = CODEC_5666;
4809 break;
4810 case 0x3:
4811 default:
4812 rt5665->id = CODEC_5665;
4813 break;
4814 }
4815
4816 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4817
4818 /* line in diff mode*/
4819 if (rt5665->pdata.in1_diff)
4820 regmap_update_bits(rt5665->regmap, RT5665_IN1_IN2,
4821 RT5665_IN1_DF_MASK, RT5665_IN1_DF_MASK);
4822 if (rt5665->pdata.in2_diff)
4823 regmap_update_bits(rt5665->regmap, RT5665_IN1_IN2,
4824 RT5665_IN2_DF_MASK, RT5665_IN2_DF_MASK);
4825 if (rt5665->pdata.in3_diff)
4826 regmap_update_bits(rt5665->regmap, RT5665_IN3_IN4,
4827 RT5665_IN3_DF_MASK, RT5665_IN3_DF_MASK);
4828 if (rt5665->pdata.in4_diff)
4829 regmap_update_bits(rt5665->regmap, RT5665_IN3_IN4,
4830 RT5665_IN4_DF_MASK, RT5665_IN4_DF_MASK);
4831
4832 /* DMIC pin*/
4833 if (rt5665->pdata.dmic1_data_pin != RT5665_DMIC1_NULL ||
4834 rt5665->pdata.dmic2_data_pin != RT5665_DMIC2_NULL) {
4835 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_2,
4836 RT5665_GP9_PIN_MASK, RT5665_GP9_PIN_DMIC1_SCL);
4837 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
4838 RT5665_GP8_PIN_MASK, RT5665_GP8_PIN_DMIC2_SCL);
4839 switch (rt5665->pdata.dmic1_data_pin) {
4840 case RT5665_DMIC1_DATA_IN2N:
4841 regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1,
4842 RT5665_DMIC_1_DP_MASK, RT5665_DMIC_1_DP_IN2N);
4843 break;
4844
4845 case RT5665_DMIC1_DATA_GPIO4:
4846 regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1,
4847 RT5665_DMIC_1_DP_MASK, RT5665_DMIC_1_DP_GPIO4);
4848 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
4849 RT5665_GP4_PIN_MASK, RT5665_GP4_PIN_DMIC1_SDA);
4850 break;
4851
4852 default:
4853 dev_dbg(&i2c->dev, "no DMIC1\n");
4854 break;
4855 }
4856
4857 switch (rt5665->pdata.dmic2_data_pin) {
4858 case RT5665_DMIC2_DATA_IN2P:
4859 regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1,
4860 RT5665_DMIC_2_DP_MASK, RT5665_DMIC_2_DP_IN2P);
4861 break;
4862
4863 case RT5665_DMIC2_DATA_GPIO5:
4864 regmap_update_bits(rt5665->regmap,
4865 RT5665_DMIC_CTRL_1,
4866 RT5665_DMIC_2_DP_MASK,
4867 RT5665_DMIC_2_DP_GPIO5);
4868 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
4869 RT5665_GP5_PIN_MASK, RT5665_GP5_PIN_DMIC2_SDA);
4870 break;
4871
4872 default:
4873 dev_dbg(&i2c->dev, "no DMIC2\n");
4874 break;
4875
4876 }
4877 }
4878
4879 regmap_write(rt5665->regmap, RT5665_HP_LOGIC_CTRL_2, 0x0002);
4880 regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1,
4881 0xf000 | RT5665_VREF_POW_MASK, 0xe000 | RT5665_VREF_POW_REG);
4882 /* Work around for pow_pump */
4883 regmap_update_bits(rt5665->regmap, RT5665_STO1_DAC_SIL_DET,
4884 RT5665_DEB_STO_DAC_MASK, RT5665_DEB_80_MS);
4885
4886 regmap_update_bits(rt5665->regmap, RT5665_HP_CHARGE_PUMP_1,
4887 RT5665_PM_HP_MASK, RT5665_PM_HP_HV);
4888
4889 /* Set GPIO4,8 as input for combo jack */
4890 if (rt5665->id == CODEC_5666) {
4891 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_2,
4892 RT5665_GP4_PF_MASK, RT5665_GP4_PF_IN);
4893 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_3,
4894 RT5665_GP8_PF_MASK, RT5665_GP8_PF_IN);
4895 }
4896
4897 /* Enhance performance*/
4898 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1,
4899 RT5665_HP_DRIVER_MASK | RT5665_LDO1_DVO_MASK,
4900 RT5665_HP_DRIVER_5X | RT5665_LDO1_DVO_12);
4901
4902 INIT_DELAYED_WORK(&rt5665->jack_detect_work,
4903 rt5665_jack_detect_handler);
4904 INIT_DELAYED_WORK(&rt5665->calibrate_work,
4905 rt5665_calibrate_handler);
4906 INIT_DELAYED_WORK(&rt5665->jd_check_work,
4907 rt5665_jd_check_handler);
4908
4909 mutex_init(&rt5665->calibrate_mutex);
4910
4911 if (i2c->irq) {
4912 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
4913 rt5665_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
4914 | IRQF_ONESHOT, "rt5665", rt5665);
4915 if (ret)
4916 dev_err(&i2c->dev, "Failed to request IRQ: %d\n", ret);
4917
4918 }
4919
4920 return devm_snd_soc_register_component(&i2c->dev,
4921 &soc_component_dev_rt5665,
4922 rt5665_dai, ARRAY_SIZE(rt5665_dai));
4923 }
4924
rt5665_i2c_shutdown(struct i2c_client * client)4925 static void rt5665_i2c_shutdown(struct i2c_client *client)
4926 {
4927 struct rt5665_priv *rt5665 = i2c_get_clientdata(client);
4928
4929 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4930 }
4931
4932 #ifdef CONFIG_OF
4933 static const struct of_device_id rt5665_of_match[] = {
4934 {.compatible = "realtek,rt5665"},
4935 {.compatible = "realtek,rt5666"},
4936 { }
4937 };
4938 MODULE_DEVICE_TABLE(of, rt5665_of_match);
4939 #endif
4940
4941 #ifdef CONFIG_ACPI
4942 static const struct acpi_device_id rt5665_acpi_match[] = {
4943 { "10EC5665" },
4944 { "10EC5666" },
4945 { }
4946 };
4947 MODULE_DEVICE_TABLE(acpi, rt5665_acpi_match);
4948 #endif
4949
4950 static struct i2c_driver rt5665_i2c_driver = {
4951 .driver = {
4952 .name = "rt5665",
4953 .of_match_table = of_match_ptr(rt5665_of_match),
4954 .acpi_match_table = ACPI_PTR(rt5665_acpi_match),
4955 },
4956 .probe = rt5665_i2c_probe,
4957 .shutdown = rt5665_i2c_shutdown,
4958 .id_table = rt5665_i2c_id,
4959 };
4960 module_i2c_driver(rt5665_i2c_driver);
4961
4962 MODULE_DESCRIPTION("ASoC RT5665 driver");
4963 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
4964 MODULE_LICENSE("GPL v2");
4965