1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * rt5645.c -- RT5645 ALSA SoC audio codec driver
4 *
5 * Copyright 2013 Realtek Semiconductor Corp.
6 * Author: Bard Liao <bardliao@realtek.com>
7 */
8
9 #include <linux/module.h>
10 #include <linux/moduleparam.h>
11 #include <linux/init.h>
12 #include <linux/delay.h>
13 #include <linux/pm.h>
14 #include <linux/i2c.h>
15 #include <linux/platform_device.h>
16 #include <linux/spi/spi.h>
17 #include <linux/gpio/consumer.h>
18 #include <linux/acpi.h>
19 #include <linux/dmi.h>
20 #include <linux/regulator/consumer.h>
21 #include <sound/core.h>
22 #include <sound/pcm.h>
23 #include <sound/pcm_params.h>
24 #include <sound/jack.h>
25 #include <sound/soc.h>
26 #include <sound/soc-dapm.h>
27 #include <sound/initval.h>
28 #include <sound/tlv.h>
29
30 #include "rl6231.h"
31 #include "rt5645.h"
32
33 #define QUIRK_INV_JD1_1(q) ((q) & 1)
34 #define QUIRK_LEVEL_IRQ(q) (((q) >> 1) & 1)
35 #define QUIRK_IN2_DIFF(q) (((q) >> 2) & 1)
36 #define QUIRK_INV_HP_POL(q) (((q) >> 3) & 1)
37 #define QUIRK_JD_MODE(q) (((q) >> 4) & 7)
38 #define QUIRK_DMIC1_DATA_PIN(q) (((q) >> 8) & 3)
39 #define QUIRK_DMIC2_DATA_PIN(q) (((q) >> 12) & 3)
40
41 static unsigned int quirk = -1;
42 module_param(quirk, uint, 0444);
43 MODULE_PARM_DESC(quirk, "RT5645 pdata quirk override");
44
45 static const struct acpi_gpio_mapping *cht_rt5645_gpios;
46
47 #define RT5645_DEVICE_ID 0x6308
48 #define RT5650_DEVICE_ID 0x6419
49
50 #define RT5645_PR_RANGE_BASE (0xff + 1)
51 #define RT5645_PR_SPACING 0x100
52
53 #define RT5645_PR_BASE (RT5645_PR_RANGE_BASE + (0 * RT5645_PR_SPACING))
54
55 #define RT5645_HWEQ_NUM 57
56
57 #define TIME_TO_POWER_MS 400
58
59 static const struct regmap_range_cfg rt5645_ranges[] = {
60 {
61 .name = "PR",
62 .range_min = RT5645_PR_BASE,
63 .range_max = RT5645_PR_BASE + 0xf8,
64 .selector_reg = RT5645_PRIV_INDEX,
65 .selector_mask = 0xff,
66 .selector_shift = 0x0,
67 .window_start = RT5645_PRIV_DATA,
68 .window_len = 0x1,
69 },
70 };
71
72 static const struct reg_sequence init_list[] = {
73 {RT5645_PR_BASE + 0x3d, 0x3600},
74 {RT5645_PR_BASE + 0x1c, 0xfd70},
75 {RT5645_PR_BASE + 0x20, 0x611f},
76 {RT5645_PR_BASE + 0x21, 0x4040},
77 {RT5645_PR_BASE + 0x23, 0x0004},
78 {RT5645_ASRC_4, 0x0120},
79 };
80
81 static const struct reg_sequence rt5650_init_list[] = {
82 {0xf6, 0x0100},
83 {RT5645_PWR_ANLG1, 0x02},
84 {RT5645_IL_CMD3, 0x6728},
85 {RT5645_PR_BASE + 0x3a, 0x0000},
86 };
87
88 static const struct reg_default rt5645_reg[] = {
89 { 0x00, 0x0000 },
90 { 0x01, 0xc8c8 },
91 { 0x02, 0xc8c8 },
92 { 0x03, 0xc8c8 },
93 { 0x0a, 0x0002 },
94 { 0x0b, 0x2827 },
95 { 0x0c, 0xe000 },
96 { 0x0d, 0x0000 },
97 { 0x0e, 0x0000 },
98 { 0x0f, 0x0808 },
99 { 0x14, 0x3333 },
100 { 0x16, 0x4b00 },
101 { 0x18, 0x018b },
102 { 0x19, 0xafaf },
103 { 0x1a, 0xafaf },
104 { 0x1b, 0x0001 },
105 { 0x1c, 0x2f2f },
106 { 0x1d, 0x2f2f },
107 { 0x1e, 0x0000 },
108 { 0x20, 0x0000 },
109 { 0x27, 0x7060 },
110 { 0x28, 0x7070 },
111 { 0x29, 0x8080 },
112 { 0x2a, 0x5656 },
113 { 0x2b, 0x5454 },
114 { 0x2c, 0xaaa0 },
115 { 0x2d, 0x0000 },
116 { 0x2f, 0x1002 },
117 { 0x31, 0x5000 },
118 { 0x32, 0x0000 },
119 { 0x33, 0x0000 },
120 { 0x34, 0x0000 },
121 { 0x35, 0x0000 },
122 { 0x3b, 0x0000 },
123 { 0x3c, 0x007f },
124 { 0x3d, 0x0000 },
125 { 0x3e, 0x007f },
126 { 0x3f, 0x0000 },
127 { 0x40, 0x001f },
128 { 0x41, 0x0000 },
129 { 0x42, 0x001f },
130 { 0x45, 0x6000 },
131 { 0x46, 0x003e },
132 { 0x47, 0x003e },
133 { 0x48, 0xf807 },
134 { 0x4a, 0x0004 },
135 { 0x4d, 0x0000 },
136 { 0x4e, 0x0000 },
137 { 0x4f, 0x01ff },
138 { 0x50, 0x0000 },
139 { 0x51, 0x0000 },
140 { 0x52, 0x01ff },
141 { 0x53, 0xf000 },
142 { 0x56, 0x0111 },
143 { 0x57, 0x0064 },
144 { 0x58, 0xef0e },
145 { 0x59, 0xf0f0 },
146 { 0x5a, 0xef0e },
147 { 0x5b, 0xf0f0 },
148 { 0x5c, 0xef0e },
149 { 0x5d, 0xf0f0 },
150 { 0x5e, 0xf000 },
151 { 0x5f, 0x0000 },
152 { 0x61, 0x0300 },
153 { 0x62, 0x0000 },
154 { 0x63, 0x00c2 },
155 { 0x64, 0x0000 },
156 { 0x65, 0x0000 },
157 { 0x66, 0x0000 },
158 { 0x6a, 0x0000 },
159 { 0x6c, 0x0aaa },
160 { 0x70, 0x8000 },
161 { 0x71, 0x8000 },
162 { 0x72, 0x8000 },
163 { 0x73, 0x7770 },
164 { 0x74, 0x3e00 },
165 { 0x75, 0x2409 },
166 { 0x76, 0x000a },
167 { 0x77, 0x0c00 },
168 { 0x78, 0x0000 },
169 { 0x79, 0x0123 },
170 { 0x80, 0x0000 },
171 { 0x81, 0x0000 },
172 { 0x82, 0x0000 },
173 { 0x83, 0x0000 },
174 { 0x84, 0x0000 },
175 { 0x85, 0x0000 },
176 { 0x8a, 0x0120 },
177 { 0x8e, 0x0004 },
178 { 0x8f, 0x1100 },
179 { 0x90, 0x0646 },
180 { 0x91, 0x0c06 },
181 { 0x93, 0x0000 },
182 { 0x94, 0x0200 },
183 { 0x95, 0x0000 },
184 { 0x9a, 0x2184 },
185 { 0x9b, 0x010a },
186 { 0x9c, 0x0aea },
187 { 0x9d, 0x000c },
188 { 0x9e, 0x0400 },
189 { 0xa0, 0xa0a8 },
190 { 0xa1, 0x0059 },
191 { 0xa2, 0x0001 },
192 { 0xae, 0x6000 },
193 { 0xaf, 0x0000 },
194 { 0xb0, 0x6000 },
195 { 0xb1, 0x0000 },
196 { 0xb2, 0x0000 },
197 { 0xb3, 0x001f },
198 { 0xb4, 0x020c },
199 { 0xb5, 0x1f00 },
200 { 0xb6, 0x0000 },
201 { 0xbb, 0x0000 },
202 { 0xbc, 0x0000 },
203 { 0xbd, 0x0000 },
204 { 0xbe, 0x0000 },
205 { 0xbf, 0x3100 },
206 { 0xc0, 0x0000 },
207 { 0xc1, 0x0000 },
208 { 0xc2, 0x0000 },
209 { 0xc3, 0x2000 },
210 { 0xcd, 0x0000 },
211 { 0xce, 0x0000 },
212 { 0xcf, 0x1813 },
213 { 0xd0, 0x0690 },
214 { 0xd1, 0x1c17 },
215 { 0xd3, 0xb320 },
216 { 0xd4, 0x0000 },
217 { 0xd6, 0x0400 },
218 { 0xd9, 0x0809 },
219 { 0xda, 0x0000 },
220 { 0xdb, 0x0003 },
221 { 0xdc, 0x0049 },
222 { 0xdd, 0x001b },
223 { 0xdf, 0x0008 },
224 { 0xe0, 0x4000 },
225 { 0xe6, 0x8000 },
226 { 0xe7, 0x0200 },
227 { 0xec, 0xb300 },
228 { 0xed, 0x0000 },
229 { 0xf0, 0x001f },
230 { 0xf1, 0x020c },
231 { 0xf2, 0x1f00 },
232 { 0xf3, 0x0000 },
233 { 0xf4, 0x4000 },
234 { 0xf8, 0x0000 },
235 { 0xf9, 0x0000 },
236 { 0xfa, 0x2060 },
237 { 0xfb, 0x4040 },
238 { 0xfc, 0x0000 },
239 { 0xfd, 0x0002 },
240 { 0xfe, 0x10ec },
241 { 0xff, 0x6308 },
242 };
243
244 static const struct reg_default rt5650_reg[] = {
245 { 0x00, 0x0000 },
246 { 0x01, 0xc8c8 },
247 { 0x02, 0xc8c8 },
248 { 0x03, 0xc8c8 },
249 { 0x0a, 0x0002 },
250 { 0x0b, 0x2827 },
251 { 0x0c, 0xe000 },
252 { 0x0d, 0x0000 },
253 { 0x0e, 0x0000 },
254 { 0x0f, 0x0808 },
255 { 0x14, 0x3333 },
256 { 0x16, 0x4b00 },
257 { 0x18, 0x018b },
258 { 0x19, 0xafaf },
259 { 0x1a, 0xafaf },
260 { 0x1b, 0x0001 },
261 { 0x1c, 0x2f2f },
262 { 0x1d, 0x2f2f },
263 { 0x1e, 0x0000 },
264 { 0x20, 0x0000 },
265 { 0x27, 0x7060 },
266 { 0x28, 0x7070 },
267 { 0x29, 0x8080 },
268 { 0x2a, 0x5656 },
269 { 0x2b, 0x5454 },
270 { 0x2c, 0xaaa0 },
271 { 0x2d, 0x0000 },
272 { 0x2f, 0x5002 },
273 { 0x31, 0x5000 },
274 { 0x32, 0x0000 },
275 { 0x33, 0x0000 },
276 { 0x34, 0x0000 },
277 { 0x35, 0x0000 },
278 { 0x3b, 0x0000 },
279 { 0x3c, 0x007f },
280 { 0x3d, 0x0000 },
281 { 0x3e, 0x007f },
282 { 0x3f, 0x0000 },
283 { 0x40, 0x001f },
284 { 0x41, 0x0000 },
285 { 0x42, 0x001f },
286 { 0x45, 0x6000 },
287 { 0x46, 0x003e },
288 { 0x47, 0x003e },
289 { 0x48, 0xf807 },
290 { 0x4a, 0x0004 },
291 { 0x4d, 0x0000 },
292 { 0x4e, 0x0000 },
293 { 0x4f, 0x01ff },
294 { 0x50, 0x0000 },
295 { 0x51, 0x0000 },
296 { 0x52, 0x01ff },
297 { 0x53, 0xf000 },
298 { 0x56, 0x0111 },
299 { 0x57, 0x0064 },
300 { 0x58, 0xef0e },
301 { 0x59, 0xf0f0 },
302 { 0x5a, 0xef0e },
303 { 0x5b, 0xf0f0 },
304 { 0x5c, 0xef0e },
305 { 0x5d, 0xf0f0 },
306 { 0x5e, 0xf000 },
307 { 0x5f, 0x0000 },
308 { 0x61, 0x0300 },
309 { 0x62, 0x0000 },
310 { 0x63, 0x00c2 },
311 { 0x64, 0x0000 },
312 { 0x65, 0x0000 },
313 { 0x66, 0x0000 },
314 { 0x6a, 0x0000 },
315 { 0x6c, 0x0aaa },
316 { 0x70, 0x8000 },
317 { 0x71, 0x8000 },
318 { 0x72, 0x8000 },
319 { 0x73, 0x7770 },
320 { 0x74, 0x3e00 },
321 { 0x75, 0x2409 },
322 { 0x76, 0x000a },
323 { 0x77, 0x0c00 },
324 { 0x78, 0x0000 },
325 { 0x79, 0x0123 },
326 { 0x7a, 0x0123 },
327 { 0x80, 0x0000 },
328 { 0x81, 0x0000 },
329 { 0x82, 0x0000 },
330 { 0x83, 0x0000 },
331 { 0x84, 0x0000 },
332 { 0x85, 0x0000 },
333 { 0x8a, 0x0120 },
334 { 0x8e, 0x0004 },
335 { 0x8f, 0x1100 },
336 { 0x90, 0x0646 },
337 { 0x91, 0x0c06 },
338 { 0x93, 0x0000 },
339 { 0x94, 0x0200 },
340 { 0x95, 0x0000 },
341 { 0x9a, 0x2184 },
342 { 0x9b, 0x010a },
343 { 0x9c, 0x0aea },
344 { 0x9d, 0x000c },
345 { 0x9e, 0x0400 },
346 { 0xa0, 0xa0a8 },
347 { 0xa1, 0x0059 },
348 { 0xa2, 0x0001 },
349 { 0xae, 0x6000 },
350 { 0xaf, 0x0000 },
351 { 0xb0, 0x6000 },
352 { 0xb1, 0x0000 },
353 { 0xb2, 0x0000 },
354 { 0xb3, 0x001f },
355 { 0xb4, 0x020c },
356 { 0xb5, 0x1f00 },
357 { 0xb6, 0x0000 },
358 { 0xbb, 0x0000 },
359 { 0xbc, 0x0000 },
360 { 0xbd, 0x0000 },
361 { 0xbe, 0x0000 },
362 { 0xbf, 0x3100 },
363 { 0xc0, 0x0000 },
364 { 0xc1, 0x0000 },
365 { 0xc2, 0x0000 },
366 { 0xc3, 0x2000 },
367 { 0xcd, 0x0000 },
368 { 0xce, 0x0000 },
369 { 0xcf, 0x1813 },
370 { 0xd0, 0x0690 },
371 { 0xd1, 0x1c17 },
372 { 0xd3, 0xb320 },
373 { 0xd4, 0x0000 },
374 { 0xd6, 0x0400 },
375 { 0xd9, 0x0809 },
376 { 0xda, 0x0000 },
377 { 0xdb, 0x0003 },
378 { 0xdc, 0x0049 },
379 { 0xdd, 0x001b },
380 { 0xdf, 0x0008 },
381 { 0xe0, 0x4000 },
382 { 0xe6, 0x8000 },
383 { 0xe7, 0x0200 },
384 { 0xec, 0xb300 },
385 { 0xed, 0x0000 },
386 { 0xf0, 0x001f },
387 { 0xf1, 0x020c },
388 { 0xf2, 0x1f00 },
389 { 0xf3, 0x0000 },
390 { 0xf4, 0x4000 },
391 { 0xf8, 0x0000 },
392 { 0xf9, 0x0000 },
393 { 0xfa, 0x2060 },
394 { 0xfb, 0x4040 },
395 { 0xfc, 0x0000 },
396 { 0xfd, 0x0002 },
397 { 0xfe, 0x10ec },
398 { 0xff, 0x6308 },
399 };
400
401 struct rt5645_eq_param_s {
402 unsigned short reg;
403 unsigned short val;
404 };
405
406 struct rt5645_eq_param_s_be16 {
407 __be16 reg;
408 __be16 val;
409 };
410
411 static const char *const rt5645_supply_names[] = {
412 "avdd",
413 "cpvdd",
414 };
415
416 struct rt5645_platform_data {
417 /* IN2 can optionally be differential */
418 bool in2_diff;
419
420 unsigned int dmic1_data_pin;
421 /* 0 = IN2N; 1 = GPIO5; 2 = GPIO11 */
422 unsigned int dmic2_data_pin;
423 /* 0 = IN2P; 1 = GPIO6; 2 = GPIO10; 3 = GPIO12 */
424
425 unsigned int jd_mode;
426 /* Use level triggered irq */
427 bool level_trigger_irq;
428 /* Invert JD1_1 status polarity */
429 bool inv_jd1_1;
430 /* Invert HP detect status polarity */
431 bool inv_hp_pol;
432
433 /* Only 1 speaker connected */
434 bool mono_speaker;
435
436 /* Value to assign to snd_soc_card.long_name */
437 const char *long_name;
438
439 /* Some (package) variants have the headset-mic pin not-connected */
440 bool no_headset_mic;
441 };
442
443 struct rt5645_priv {
444 struct snd_soc_component *component;
445 struct rt5645_platform_data pdata;
446 struct regmap *regmap;
447 struct i2c_client *i2c;
448 struct gpio_desc *gpiod_hp_det;
449 struct gpio_desc *gpiod_cbj_sleeve;
450 struct snd_soc_jack *hp_jack;
451 struct snd_soc_jack *mic_jack;
452 struct snd_soc_jack *btn_jack;
453 struct delayed_work jack_detect_work, rcclock_work;
454 struct regulator_bulk_data supplies[ARRAY_SIZE(rt5645_supply_names)];
455 struct rt5645_eq_param_s *eq_param;
456 struct timer_list btn_check_timer;
457 struct mutex jd_mutex;
458
459 int codec_type;
460 int sysclk;
461 int sysclk_src;
462 int lrck[RT5645_AIFS];
463 int bclk[RT5645_AIFS];
464 int master[RT5645_AIFS];
465
466 int pll_src;
467 int pll_in;
468 int pll_out;
469
470 int jack_type;
471 bool en_button_func;
472 int v_id;
473 };
474
rt5645_reset(struct snd_soc_component * component)475 static int rt5645_reset(struct snd_soc_component *component)
476 {
477 return snd_soc_component_write(component, RT5645_RESET, 0);
478 }
479
rt5645_volatile_register(struct device * dev,unsigned int reg)480 static bool rt5645_volatile_register(struct device *dev, unsigned int reg)
481 {
482 int i;
483
484 for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) {
485 if (reg >= rt5645_ranges[i].range_min &&
486 reg <= rt5645_ranges[i].range_max) {
487 return true;
488 }
489 }
490
491 switch (reg) {
492 case RT5645_RESET:
493 case RT5645_PRIV_INDEX:
494 case RT5645_PRIV_DATA:
495 case RT5645_IN1_CTRL1:
496 case RT5645_IN1_CTRL2:
497 case RT5645_IN1_CTRL3:
498 case RT5645_A_JD_CTRL1:
499 case RT5645_ADC_EQ_CTRL1:
500 case RT5645_EQ_CTRL1:
501 case RT5645_ALC_CTRL_1:
502 case RT5645_IRQ_CTRL2:
503 case RT5645_IRQ_CTRL3:
504 case RT5645_INT_IRQ_ST:
505 case RT5645_IL_CMD:
506 case RT5650_4BTN_IL_CMD1:
507 case RT5645_VENDOR_ID:
508 case RT5645_VENDOR_ID1:
509 case RT5645_VENDOR_ID2:
510 return true;
511 default:
512 return false;
513 }
514 }
515
rt5645_readable_register(struct device * dev,unsigned int reg)516 static bool rt5645_readable_register(struct device *dev, unsigned int reg)
517 {
518 int i;
519
520 for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) {
521 if (reg >= rt5645_ranges[i].range_min &&
522 reg <= rt5645_ranges[i].range_max) {
523 return true;
524 }
525 }
526
527 switch (reg) {
528 case RT5645_RESET:
529 case RT5645_SPK_VOL:
530 case RT5645_HP_VOL:
531 case RT5645_LOUT1:
532 case RT5645_IN1_CTRL1:
533 case RT5645_IN1_CTRL2:
534 case RT5645_IN1_CTRL3:
535 case RT5645_IN2_CTRL:
536 case RT5645_INL1_INR1_VOL:
537 case RT5645_SPK_FUNC_LIM:
538 case RT5645_ADJ_HPF_CTRL:
539 case RT5645_DAC1_DIG_VOL:
540 case RT5645_DAC2_DIG_VOL:
541 case RT5645_DAC_CTRL:
542 case RT5645_STO1_ADC_DIG_VOL:
543 case RT5645_MONO_ADC_DIG_VOL:
544 case RT5645_ADC_BST_VOL1:
545 case RT5645_ADC_BST_VOL2:
546 case RT5645_STO1_ADC_MIXER:
547 case RT5645_MONO_ADC_MIXER:
548 case RT5645_AD_DA_MIXER:
549 case RT5645_STO_DAC_MIXER:
550 case RT5645_MONO_DAC_MIXER:
551 case RT5645_DIG_MIXER:
552 case RT5650_A_DAC_SOUR:
553 case RT5645_DIG_INF1_DATA:
554 case RT5645_PDM_OUT_CTRL:
555 case RT5645_REC_L1_MIXER:
556 case RT5645_REC_L2_MIXER:
557 case RT5645_REC_R1_MIXER:
558 case RT5645_REC_R2_MIXER:
559 case RT5645_HPMIXL_CTRL:
560 case RT5645_HPOMIXL_CTRL:
561 case RT5645_HPMIXR_CTRL:
562 case RT5645_HPOMIXR_CTRL:
563 case RT5645_HPO_MIXER:
564 case RT5645_SPK_L_MIXER:
565 case RT5645_SPK_R_MIXER:
566 case RT5645_SPO_MIXER:
567 case RT5645_SPO_CLSD_RATIO:
568 case RT5645_OUT_L1_MIXER:
569 case RT5645_OUT_R1_MIXER:
570 case RT5645_OUT_L_GAIN1:
571 case RT5645_OUT_L_GAIN2:
572 case RT5645_OUT_R_GAIN1:
573 case RT5645_OUT_R_GAIN2:
574 case RT5645_LOUT_MIXER:
575 case RT5645_HAPTIC_CTRL1:
576 case RT5645_HAPTIC_CTRL2:
577 case RT5645_HAPTIC_CTRL3:
578 case RT5645_HAPTIC_CTRL4:
579 case RT5645_HAPTIC_CTRL5:
580 case RT5645_HAPTIC_CTRL6:
581 case RT5645_HAPTIC_CTRL7:
582 case RT5645_HAPTIC_CTRL8:
583 case RT5645_HAPTIC_CTRL9:
584 case RT5645_HAPTIC_CTRL10:
585 case RT5645_PWR_DIG1:
586 case RT5645_PWR_DIG2:
587 case RT5645_PWR_ANLG1:
588 case RT5645_PWR_ANLG2:
589 case RT5645_PWR_MIXER:
590 case RT5645_PWR_VOL:
591 case RT5645_PRIV_INDEX:
592 case RT5645_PRIV_DATA:
593 case RT5645_I2S1_SDP:
594 case RT5645_I2S2_SDP:
595 case RT5645_ADDA_CLK1:
596 case RT5645_ADDA_CLK2:
597 case RT5645_DMIC_CTRL1:
598 case RT5645_DMIC_CTRL2:
599 case RT5645_TDM_CTRL_1:
600 case RT5645_TDM_CTRL_2:
601 case RT5645_TDM_CTRL_3:
602 case RT5650_TDM_CTRL_4:
603 case RT5645_GLB_CLK:
604 case RT5645_PLL_CTRL1:
605 case RT5645_PLL_CTRL2:
606 case RT5645_ASRC_1:
607 case RT5645_ASRC_2:
608 case RT5645_ASRC_3:
609 case RT5645_ASRC_4:
610 case RT5645_DEPOP_M1:
611 case RT5645_DEPOP_M2:
612 case RT5645_DEPOP_M3:
613 case RT5645_CHARGE_PUMP:
614 case RT5645_MICBIAS:
615 case RT5645_A_JD_CTRL1:
616 case RT5645_VAD_CTRL4:
617 case RT5645_CLSD_OUT_CTRL:
618 case RT5645_ADC_EQ_CTRL1:
619 case RT5645_ADC_EQ_CTRL2:
620 case RT5645_EQ_CTRL1:
621 case RT5645_EQ_CTRL2:
622 case RT5645_ALC_CTRL_1:
623 case RT5645_ALC_CTRL_2:
624 case RT5645_ALC_CTRL_3:
625 case RT5645_ALC_CTRL_4:
626 case RT5645_ALC_CTRL_5:
627 case RT5645_JD_CTRL:
628 case RT5645_IRQ_CTRL1:
629 case RT5645_IRQ_CTRL2:
630 case RT5645_IRQ_CTRL3:
631 case RT5645_INT_IRQ_ST:
632 case RT5645_GPIO_CTRL1:
633 case RT5645_GPIO_CTRL2:
634 case RT5645_GPIO_CTRL3:
635 case RT5645_BASS_BACK:
636 case RT5645_MP3_PLUS1:
637 case RT5645_MP3_PLUS2:
638 case RT5645_ADJ_HPF1:
639 case RT5645_ADJ_HPF2:
640 case RT5645_HP_CALIB_AMP_DET:
641 case RT5645_SV_ZCD1:
642 case RT5645_SV_ZCD2:
643 case RT5645_IL_CMD:
644 case RT5645_IL_CMD2:
645 case RT5645_IL_CMD3:
646 case RT5650_4BTN_IL_CMD1:
647 case RT5650_4BTN_IL_CMD2:
648 case RT5645_DRC1_HL_CTRL1:
649 case RT5645_DRC2_HL_CTRL1:
650 case RT5645_ADC_MONO_HP_CTRL1:
651 case RT5645_ADC_MONO_HP_CTRL2:
652 case RT5645_DRC2_CTRL1:
653 case RT5645_DRC2_CTRL2:
654 case RT5645_DRC2_CTRL3:
655 case RT5645_DRC2_CTRL4:
656 case RT5645_DRC2_CTRL5:
657 case RT5645_JD_CTRL3:
658 case RT5645_JD_CTRL4:
659 case RT5645_GEN_CTRL1:
660 case RT5645_GEN_CTRL2:
661 case RT5645_GEN_CTRL3:
662 case RT5645_VENDOR_ID:
663 case RT5645_VENDOR_ID1:
664 case RT5645_VENDOR_ID2:
665 return true;
666 default:
667 return false;
668 }
669 }
670
671 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
672 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
673 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
674 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
675 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
676
677 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
678 static const DECLARE_TLV_DB_RANGE(bst_tlv,
679 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
680 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
681 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
682 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
683 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
684 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
685 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
686 );
687
688 /* {-6, -4.5, -3, -1.5, 0, 0.82, 1.58, 2.28} dB */
689 static const DECLARE_TLV_DB_RANGE(spk_clsd_tlv,
690 0, 4, TLV_DB_SCALE_ITEM(-600, 150, 0),
691 5, 5, TLV_DB_SCALE_ITEM(82, 0, 0),
692 6, 6, TLV_DB_SCALE_ITEM(158, 0, 0),
693 7, 7, TLV_DB_SCALE_ITEM(228, 0, 0)
694 );
695
rt5645_hweq_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)696 static int rt5645_hweq_info(struct snd_kcontrol *kcontrol,
697 struct snd_ctl_elem_info *uinfo)
698 {
699 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
700 uinfo->count = RT5645_HWEQ_NUM * sizeof(struct rt5645_eq_param_s);
701
702 return 0;
703 }
704
rt5645_hweq_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)705 static int rt5645_hweq_get(struct snd_kcontrol *kcontrol,
706 struct snd_ctl_elem_value *ucontrol)
707 {
708 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
709 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
710 struct rt5645_eq_param_s_be16 *eq_param =
711 (struct rt5645_eq_param_s_be16 *)ucontrol->value.bytes.data;
712 int i;
713
714 for (i = 0; i < RT5645_HWEQ_NUM; i++) {
715 eq_param[i].reg = cpu_to_be16(rt5645->eq_param[i].reg);
716 eq_param[i].val = cpu_to_be16(rt5645->eq_param[i].val);
717 }
718
719 return 0;
720 }
721
rt5645_validate_hweq(unsigned short reg)722 static bool rt5645_validate_hweq(unsigned short reg)
723 {
724 if ((reg >= 0x1a4 && reg <= 0x1cd) || (reg >= 0x1e5 && reg <= 0x1f8) ||
725 (reg == RT5645_EQ_CTRL2))
726 return true;
727
728 return false;
729 }
730
rt5645_hweq_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)731 static int rt5645_hweq_put(struct snd_kcontrol *kcontrol,
732 struct snd_ctl_elem_value *ucontrol)
733 {
734 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
735 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
736 struct rt5645_eq_param_s_be16 *eq_param =
737 (struct rt5645_eq_param_s_be16 *)ucontrol->value.bytes.data;
738 int i;
739
740 for (i = 0; i < RT5645_HWEQ_NUM; i++) {
741 rt5645->eq_param[i].reg = be16_to_cpu(eq_param[i].reg);
742 rt5645->eq_param[i].val = be16_to_cpu(eq_param[i].val);
743 }
744
745 /* The final setting of the table should be RT5645_EQ_CTRL2 */
746 for (i = RT5645_HWEQ_NUM - 1; i >= 0; i--) {
747 if (rt5645->eq_param[i].reg == 0)
748 continue;
749 else if (rt5645->eq_param[i].reg != RT5645_EQ_CTRL2)
750 return 0;
751 else
752 break;
753 }
754
755 for (i = 0; i < RT5645_HWEQ_NUM; i++) {
756 if (!rt5645_validate_hweq(rt5645->eq_param[i].reg) &&
757 rt5645->eq_param[i].reg != 0)
758 return 0;
759 else if (rt5645->eq_param[i].reg == 0)
760 break;
761 }
762
763 return 0;
764 }
765
766 #define RT5645_HWEQ(xname) \
767 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
768 .info = rt5645_hweq_info, \
769 .get = rt5645_hweq_get, \
770 .put = rt5645_hweq_put \
771 }
772
rt5645_spk_put_volsw(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)773 static int rt5645_spk_put_volsw(struct snd_kcontrol *kcontrol,
774 struct snd_ctl_elem_value *ucontrol)
775 {
776 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
777 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
778 int ret;
779
780 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
781 RT5645_PWR_CLK25M_MASK, RT5645_PWR_CLK25M_PU);
782
783 ret = snd_soc_put_volsw(kcontrol, ucontrol);
784
785 mod_delayed_work(system_power_efficient_wq, &rt5645->rcclock_work,
786 msecs_to_jiffies(200));
787
788 return ret;
789 }
790
791 static const char * const rt5645_dac1_vol_ctrl_mode_text[] = {
792 "immediately", "zero crossing", "soft ramp"
793 };
794
795 static SOC_ENUM_SINGLE_DECL(
796 rt5645_dac1_vol_ctrl_mode, RT5645_PR_BASE,
797 RT5645_DA1_ZDET_SFT, rt5645_dac1_vol_ctrl_mode_text);
798
799 static const struct snd_kcontrol_new rt5645_snd_controls[] = {
800 /* Speaker Output Volume */
801 SOC_DOUBLE("Speaker Channel Switch", RT5645_SPK_VOL,
802 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
803 SOC_DOUBLE_EXT_TLV("Speaker Playback Volume", RT5645_SPK_VOL,
804 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, snd_soc_get_volsw,
805 rt5645_spk_put_volsw, out_vol_tlv),
806
807 /* ClassD modulator Speaker Gain Ratio */
808 SOC_SINGLE_TLV("Speaker ClassD Playback Volume", RT5645_SPO_CLSD_RATIO,
809 RT5645_SPK_G_CLSD_SFT, 7, 0, spk_clsd_tlv),
810
811 /* Headphone Output Volume */
812 SOC_DOUBLE("Headphone Channel Switch", RT5645_HP_VOL,
813 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
814 SOC_DOUBLE_TLV("Headphone Playback Volume", RT5645_HP_VOL,
815 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
816
817 /* OUTPUT Control */
818 SOC_DOUBLE("OUT Playback Switch", RT5645_LOUT1,
819 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
820 SOC_DOUBLE("OUT Channel Switch", RT5645_LOUT1,
821 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
822 SOC_DOUBLE_TLV("OUT Playback Volume", RT5645_LOUT1,
823 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
824
825 /* DAC Digital Volume */
826 SOC_DOUBLE("DAC2 Playback Switch", RT5645_DAC_CTRL,
827 RT5645_M_DAC_L2_VOL_SFT, RT5645_M_DAC_R2_VOL_SFT, 1, 1),
828 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5645_DAC1_DIG_VOL,
829 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),
830 SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5645_DAC2_DIG_VOL,
831 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),
832
833 /* IN1/IN2 Control */
834 SOC_SINGLE_TLV("IN1 Boost", RT5645_IN1_CTRL1,
835 RT5645_BST_SFT1, 12, 0, bst_tlv),
836 SOC_SINGLE_TLV("IN2 Boost", RT5645_IN2_CTRL,
837 RT5645_BST_SFT2, 8, 0, bst_tlv),
838
839 /* INL/INR Volume Control */
840 SOC_DOUBLE_TLV("IN Capture Volume", RT5645_INL1_INR1_VOL,
841 RT5645_INL_VOL_SFT, RT5645_INR_VOL_SFT, 31, 1, in_vol_tlv),
842
843 /* ADC Digital Volume Control */
844 SOC_DOUBLE("ADC Capture Switch", RT5645_STO1_ADC_DIG_VOL,
845 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
846 SOC_DOUBLE_TLV("ADC Capture Volume", RT5645_STO1_ADC_DIG_VOL,
847 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
848 SOC_DOUBLE("Mono ADC Capture Switch", RT5645_MONO_ADC_DIG_VOL,
849 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
850 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5645_MONO_ADC_DIG_VOL,
851 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
852
853 /* ADC Boost Volume Control */
854 SOC_DOUBLE_TLV("ADC Boost Capture Volume", RT5645_ADC_BST_VOL1,
855 RT5645_STO1_ADC_L_BST_SFT, RT5645_STO1_ADC_R_BST_SFT, 3, 0,
856 adc_bst_tlv),
857 SOC_DOUBLE_TLV("Mono ADC Boost Capture Volume", RT5645_ADC_BST_VOL2,
858 RT5645_MONO_ADC_L_BST_SFT, RT5645_MONO_ADC_R_BST_SFT, 3, 0,
859 adc_bst_tlv),
860
861 /* I2S2 function select */
862 SOC_SINGLE("I2S2 Func Switch", RT5645_GPIO_CTRL1, RT5645_I2S2_SEL_SFT,
863 1, 1),
864 RT5645_HWEQ("Speaker HWEQ"),
865
866 /* Digital Soft Volume Control */
867 SOC_ENUM("DAC1 Digital Volume Control Func", rt5645_dac1_vol_ctrl_mode),
868 };
869
870 /**
871 * set_dmic_clk - Set parameter of dmic.
872 *
873 * @w: DAPM widget.
874 * @kcontrol: The kcontrol of this widget.
875 * @event: Event id.
876 *
877 */
set_dmic_clk(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)878 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
879 struct snd_kcontrol *kcontrol, int event)
880 {
881 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
882 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
883 int idx, rate;
884
885 rate = rt5645->sysclk / rl6231_get_pre_div(rt5645->regmap,
886 RT5645_ADDA_CLK1, RT5645_I2S_PD1_SFT);
887 idx = rl6231_calc_dmic_clk(rate);
888 if (idx < 0)
889 dev_err(component->dev, "Failed to set DMIC clock\n");
890 else
891 snd_soc_component_update_bits(component, RT5645_DMIC_CTRL1,
892 RT5645_DMIC_CLK_MASK, idx << RT5645_DMIC_CLK_SFT);
893 return idx;
894 }
895
is_sys_clk_from_pll(struct snd_soc_dapm_widget * source,struct snd_soc_dapm_widget * sink)896 static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
897 struct snd_soc_dapm_widget *sink)
898 {
899 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
900 unsigned int val;
901
902 val = snd_soc_component_read(component, RT5645_GLB_CLK);
903 val &= RT5645_SCLK_SRC_MASK;
904 if (val == RT5645_SCLK_SRC_PLL1)
905 return 1;
906 else
907 return 0;
908 }
909
is_using_asrc(struct snd_soc_dapm_widget * source,struct snd_soc_dapm_widget * sink)910 static int is_using_asrc(struct snd_soc_dapm_widget *source,
911 struct snd_soc_dapm_widget *sink)
912 {
913 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
914 unsigned int reg, shift, val;
915
916 switch (source->shift) {
917 case 0:
918 reg = RT5645_ASRC_3;
919 shift = 0;
920 break;
921 case 1:
922 reg = RT5645_ASRC_3;
923 shift = 4;
924 break;
925 case 3:
926 reg = RT5645_ASRC_2;
927 shift = 0;
928 break;
929 case 8:
930 reg = RT5645_ASRC_2;
931 shift = 4;
932 break;
933 case 9:
934 reg = RT5645_ASRC_2;
935 shift = 8;
936 break;
937 case 10:
938 reg = RT5645_ASRC_2;
939 shift = 12;
940 break;
941 default:
942 return 0;
943 }
944
945 val = (snd_soc_component_read(component, reg) >> shift) & 0xf;
946 switch (val) {
947 case 1:
948 case 2:
949 case 3:
950 case 4:
951 return 1;
952 default:
953 return 0;
954 }
955
956 }
957
rt5645_enable_hweq(struct snd_soc_component * component)958 static int rt5645_enable_hweq(struct snd_soc_component *component)
959 {
960 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
961 int i;
962
963 for (i = 0; i < RT5645_HWEQ_NUM; i++) {
964 if (rt5645_validate_hweq(rt5645->eq_param[i].reg))
965 regmap_write(rt5645->regmap, rt5645->eq_param[i].reg,
966 rt5645->eq_param[i].val);
967 else
968 break;
969 }
970
971 return 0;
972 }
973
974 /**
975 * rt5645_sel_asrc_clk_src - select ASRC clock source for a set of filters
976 * @component: SoC audio component device.
977 * @filter_mask: mask of filters.
978 * @clk_src: clock source
979 *
980 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5645 can
981 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
982 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
983 * ASRC function will track i2s clock and generate a corresponding system clock
984 * for codec. This function provides an API to select the clock source for a
985 * set of filters specified by the mask. And the codec driver will turn on ASRC
986 * for these filters if ASRC is selected as their clock source.
987 */
rt5645_sel_asrc_clk_src(struct snd_soc_component * component,unsigned int filter_mask,unsigned int clk_src)988 int rt5645_sel_asrc_clk_src(struct snd_soc_component *component,
989 unsigned int filter_mask, unsigned int clk_src)
990 {
991 unsigned int asrc2_mask = 0;
992 unsigned int asrc2_value = 0;
993 unsigned int asrc3_mask = 0;
994 unsigned int asrc3_value = 0;
995
996 switch (clk_src) {
997 case RT5645_CLK_SEL_SYS:
998 case RT5645_CLK_SEL_I2S1_ASRC:
999 case RT5645_CLK_SEL_I2S2_ASRC:
1000 case RT5645_CLK_SEL_SYS2:
1001 break;
1002
1003 default:
1004 return -EINVAL;
1005 }
1006
1007 if (filter_mask & RT5645_DA_STEREO_FILTER) {
1008 asrc2_mask |= RT5645_DA_STO_CLK_SEL_MASK;
1009 asrc2_value = (asrc2_value & ~RT5645_DA_STO_CLK_SEL_MASK)
1010 | (clk_src << RT5645_DA_STO_CLK_SEL_SFT);
1011 }
1012
1013 if (filter_mask & RT5645_DA_MONO_L_FILTER) {
1014 asrc2_mask |= RT5645_DA_MONOL_CLK_SEL_MASK;
1015 asrc2_value = (asrc2_value & ~RT5645_DA_MONOL_CLK_SEL_MASK)
1016 | (clk_src << RT5645_DA_MONOL_CLK_SEL_SFT);
1017 }
1018
1019 if (filter_mask & RT5645_DA_MONO_R_FILTER) {
1020 asrc2_mask |= RT5645_DA_MONOR_CLK_SEL_MASK;
1021 asrc2_value = (asrc2_value & ~RT5645_DA_MONOR_CLK_SEL_MASK)
1022 | (clk_src << RT5645_DA_MONOR_CLK_SEL_SFT);
1023 }
1024
1025 if (filter_mask & RT5645_AD_STEREO_FILTER) {
1026 asrc2_mask |= RT5645_AD_STO1_CLK_SEL_MASK;
1027 asrc2_value = (asrc2_value & ~RT5645_AD_STO1_CLK_SEL_MASK)
1028 | (clk_src << RT5645_AD_STO1_CLK_SEL_SFT);
1029 }
1030
1031 if (filter_mask & RT5645_AD_MONO_L_FILTER) {
1032 asrc3_mask |= RT5645_AD_MONOL_CLK_SEL_MASK;
1033 asrc3_value = (asrc3_value & ~RT5645_AD_MONOL_CLK_SEL_MASK)
1034 | (clk_src << RT5645_AD_MONOL_CLK_SEL_SFT);
1035 }
1036
1037 if (filter_mask & RT5645_AD_MONO_R_FILTER) {
1038 asrc3_mask |= RT5645_AD_MONOR_CLK_SEL_MASK;
1039 asrc3_value = (asrc3_value & ~RT5645_AD_MONOR_CLK_SEL_MASK)
1040 | (clk_src << RT5645_AD_MONOR_CLK_SEL_SFT);
1041 }
1042
1043 if (asrc2_mask)
1044 snd_soc_component_update_bits(component, RT5645_ASRC_2,
1045 asrc2_mask, asrc2_value);
1046
1047 if (asrc3_mask)
1048 snd_soc_component_update_bits(component, RT5645_ASRC_3,
1049 asrc3_mask, asrc3_value);
1050
1051 return 0;
1052 }
1053 EXPORT_SYMBOL_GPL(rt5645_sel_asrc_clk_src);
1054
1055 /* Digital Mixer */
1056 static const struct snd_kcontrol_new rt5645_sto1_adc_l_mix[] = {
1057 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER,
1058 RT5645_M_ADC_L1_SFT, 1, 1),
1059 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER,
1060 RT5645_M_ADC_L2_SFT, 1, 1),
1061 };
1062
1063 static const struct snd_kcontrol_new rt5645_sto1_adc_r_mix[] = {
1064 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER,
1065 RT5645_M_ADC_R1_SFT, 1, 1),
1066 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER,
1067 RT5645_M_ADC_R2_SFT, 1, 1),
1068 };
1069
1070 static const struct snd_kcontrol_new rt5645_mono_adc_l_mix[] = {
1071 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER,
1072 RT5645_M_MONO_ADC_L1_SFT, 1, 1),
1073 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER,
1074 RT5645_M_MONO_ADC_L2_SFT, 1, 1),
1075 };
1076
1077 static const struct snd_kcontrol_new rt5645_mono_adc_r_mix[] = {
1078 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER,
1079 RT5645_M_MONO_ADC_R1_SFT, 1, 1),
1080 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER,
1081 RT5645_M_MONO_ADC_R2_SFT, 1, 1),
1082 };
1083
1084 static const struct snd_kcontrol_new rt5645_dac_l_mix[] = {
1085 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER,
1086 RT5645_M_ADCMIX_L_SFT, 1, 1),
1087 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 Switch", RT5645_AD_DA_MIXER,
1088 RT5645_M_DAC1_L_SFT, 1, 1),
1089 };
1090
1091 static const struct snd_kcontrol_new rt5645_dac_r_mix[] = {
1092 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER,
1093 RT5645_M_ADCMIX_R_SFT, 1, 1),
1094 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 Switch", RT5645_AD_DA_MIXER,
1095 RT5645_M_DAC1_R_SFT, 1, 1),
1096 };
1097
1098 static const struct snd_kcontrol_new rt5645_sto_dac_l_mix[] = {
1099 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER,
1100 RT5645_M_DAC_L1_SFT, 1, 1),
1101 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_STO_DAC_MIXER,
1102 RT5645_M_DAC_L2_SFT, 1, 1),
1103 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER,
1104 RT5645_M_DAC_R1_STO_L_SFT, 1, 1),
1105 };
1106
1107 static const struct snd_kcontrol_new rt5645_sto_dac_r_mix[] = {
1108 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER,
1109 RT5645_M_DAC_R1_SFT, 1, 1),
1110 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_STO_DAC_MIXER,
1111 RT5645_M_DAC_R2_SFT, 1, 1),
1112 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER,
1113 RT5645_M_DAC_L1_STO_R_SFT, 1, 1),
1114 };
1115
1116 static const struct snd_kcontrol_new rt5645_mono_dac_l_mix[] = {
1117 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_MONO_DAC_MIXER,
1118 RT5645_M_DAC_L1_MONO_L_SFT, 1, 1),
1119 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER,
1120 RT5645_M_DAC_L2_MONO_L_SFT, 1, 1),
1121 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER,
1122 RT5645_M_DAC_R2_MONO_L_SFT, 1, 1),
1123 };
1124
1125 static const struct snd_kcontrol_new rt5645_mono_dac_r_mix[] = {
1126 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_MONO_DAC_MIXER,
1127 RT5645_M_DAC_R1_MONO_R_SFT, 1, 1),
1128 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER,
1129 RT5645_M_DAC_R2_MONO_R_SFT, 1, 1),
1130 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER,
1131 RT5645_M_DAC_L2_MONO_R_SFT, 1, 1),
1132 };
1133
1134 static const struct snd_kcontrol_new rt5645_dig_l_mix[] = {
1135 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5645_DIG_MIXER,
1136 RT5645_M_STO_L_DAC_L_SFT, 1, 1),
1137 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER,
1138 RT5645_M_DAC_L2_DAC_L_SFT, 1, 1),
1139 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER,
1140 RT5645_M_DAC_R2_DAC_L_SFT, 1, 1),
1141 };
1142
1143 static const struct snd_kcontrol_new rt5645_dig_r_mix[] = {
1144 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5645_DIG_MIXER,
1145 RT5645_M_STO_R_DAC_R_SFT, 1, 1),
1146 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER,
1147 RT5645_M_DAC_R2_DAC_R_SFT, 1, 1),
1148 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER,
1149 RT5645_M_DAC_L2_DAC_R_SFT, 1, 1),
1150 };
1151
1152 /* Analog Input Mixer */
1153 static const struct snd_kcontrol_new rt5645_rec_l_mix[] = {
1154 SOC_DAPM_SINGLE("HPOL Switch", RT5645_REC_L2_MIXER,
1155 RT5645_M_HP_L_RM_L_SFT, 1, 1),
1156 SOC_DAPM_SINGLE("INL Switch", RT5645_REC_L2_MIXER,
1157 RT5645_M_IN_L_RM_L_SFT, 1, 1),
1158 SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_L2_MIXER,
1159 RT5645_M_BST2_RM_L_SFT, 1, 1),
1160 SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_L2_MIXER,
1161 RT5645_M_BST1_RM_L_SFT, 1, 1),
1162 SOC_DAPM_SINGLE("OUT MIXL Switch", RT5645_REC_L2_MIXER,
1163 RT5645_M_OM_L_RM_L_SFT, 1, 1),
1164 };
1165
1166 static const struct snd_kcontrol_new rt5645_rec_r_mix[] = {
1167 SOC_DAPM_SINGLE("HPOR Switch", RT5645_REC_R2_MIXER,
1168 RT5645_M_HP_R_RM_R_SFT, 1, 1),
1169 SOC_DAPM_SINGLE("INR Switch", RT5645_REC_R2_MIXER,
1170 RT5645_M_IN_R_RM_R_SFT, 1, 1),
1171 SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_R2_MIXER,
1172 RT5645_M_BST2_RM_R_SFT, 1, 1),
1173 SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_R2_MIXER,
1174 RT5645_M_BST1_RM_R_SFT, 1, 1),
1175 SOC_DAPM_SINGLE("OUT MIXR Switch", RT5645_REC_R2_MIXER,
1176 RT5645_M_OM_R_RM_R_SFT, 1, 1),
1177 };
1178
1179 static const struct snd_kcontrol_new rt5645_spk_l_mix[] = {
1180 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPK_L_MIXER,
1181 RT5645_M_DAC_L1_SM_L_SFT, 1, 1),
1182 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_SPK_L_MIXER,
1183 RT5645_M_DAC_L2_SM_L_SFT, 1, 1),
1184 SOC_DAPM_SINGLE("INL Switch", RT5645_SPK_L_MIXER,
1185 RT5645_M_IN_L_SM_L_SFT, 1, 1),
1186 SOC_DAPM_SINGLE("BST1 Switch", RT5645_SPK_L_MIXER,
1187 RT5645_M_BST1_L_SM_L_SFT, 1, 1),
1188 };
1189
1190 static const struct snd_kcontrol_new rt5645_spk_r_mix[] = {
1191 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPK_R_MIXER,
1192 RT5645_M_DAC_R1_SM_R_SFT, 1, 1),
1193 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_SPK_R_MIXER,
1194 RT5645_M_DAC_R2_SM_R_SFT, 1, 1),
1195 SOC_DAPM_SINGLE("INR Switch", RT5645_SPK_R_MIXER,
1196 RT5645_M_IN_R_SM_R_SFT, 1, 1),
1197 SOC_DAPM_SINGLE("BST2 Switch", RT5645_SPK_R_MIXER,
1198 RT5645_M_BST2_R_SM_R_SFT, 1, 1),
1199 };
1200
1201 static const struct snd_kcontrol_new rt5645_out_l_mix[] = {
1202 SOC_DAPM_SINGLE("BST1 Switch", RT5645_OUT_L1_MIXER,
1203 RT5645_M_BST1_OM_L_SFT, 1, 1),
1204 SOC_DAPM_SINGLE("INL Switch", RT5645_OUT_L1_MIXER,
1205 RT5645_M_IN_L_OM_L_SFT, 1, 1),
1206 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_OUT_L1_MIXER,
1207 RT5645_M_DAC_L2_OM_L_SFT, 1, 1),
1208 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_OUT_L1_MIXER,
1209 RT5645_M_DAC_L1_OM_L_SFT, 1, 1),
1210 };
1211
1212 static const struct snd_kcontrol_new rt5645_out_r_mix[] = {
1213 SOC_DAPM_SINGLE("BST2 Switch", RT5645_OUT_R1_MIXER,
1214 RT5645_M_BST2_OM_R_SFT, 1, 1),
1215 SOC_DAPM_SINGLE("INR Switch", RT5645_OUT_R1_MIXER,
1216 RT5645_M_IN_R_OM_R_SFT, 1, 1),
1217 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_OUT_R1_MIXER,
1218 RT5645_M_DAC_R2_OM_R_SFT, 1, 1),
1219 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_OUT_R1_MIXER,
1220 RT5645_M_DAC_R1_OM_R_SFT, 1, 1),
1221 };
1222
1223 static const struct snd_kcontrol_new rt5645_spo_l_mix[] = {
1224 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER,
1225 RT5645_M_DAC_R1_SPM_L_SFT, 1, 1),
1226 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPO_MIXER,
1227 RT5645_M_DAC_L1_SPM_L_SFT, 1, 1),
1228 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER,
1229 RT5645_M_SV_R_SPM_L_SFT, 1, 1),
1230 SOC_DAPM_SINGLE("SPKVOL L Switch", RT5645_SPO_MIXER,
1231 RT5645_M_SV_L_SPM_L_SFT, 1, 1),
1232 };
1233
1234 static const struct snd_kcontrol_new rt5645_spo_r_mix[] = {
1235 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER,
1236 RT5645_M_DAC_R1_SPM_R_SFT, 1, 1),
1237 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER,
1238 RT5645_M_SV_R_SPM_R_SFT, 1, 1),
1239 };
1240
1241 static const struct snd_kcontrol_new rt5645_hpo_mix[] = {
1242 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPO_MIXER,
1243 RT5645_M_DAC1_HM_SFT, 1, 1),
1244 SOC_DAPM_SINGLE("HPVOL Switch", RT5645_HPO_MIXER,
1245 RT5645_M_HPVOL_HM_SFT, 1, 1),
1246 };
1247
1248 static const struct snd_kcontrol_new rt5645_hpvoll_mix[] = {
1249 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXL_CTRL,
1250 RT5645_M_DAC1_HV_SFT, 1, 1),
1251 SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXL_CTRL,
1252 RT5645_M_DAC2_HV_SFT, 1, 1),
1253 SOC_DAPM_SINGLE("INL Switch", RT5645_HPOMIXL_CTRL,
1254 RT5645_M_IN_HV_SFT, 1, 1),
1255 SOC_DAPM_SINGLE("BST1 Switch", RT5645_HPOMIXL_CTRL,
1256 RT5645_M_BST1_HV_SFT, 1, 1),
1257 };
1258
1259 static const struct snd_kcontrol_new rt5645_hpvolr_mix[] = {
1260 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXR_CTRL,
1261 RT5645_M_DAC1_HV_SFT, 1, 1),
1262 SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXR_CTRL,
1263 RT5645_M_DAC2_HV_SFT, 1, 1),
1264 SOC_DAPM_SINGLE("INR Switch", RT5645_HPOMIXR_CTRL,
1265 RT5645_M_IN_HV_SFT, 1, 1),
1266 SOC_DAPM_SINGLE("BST2 Switch", RT5645_HPOMIXR_CTRL,
1267 RT5645_M_BST2_HV_SFT, 1, 1),
1268 };
1269
1270 static const struct snd_kcontrol_new rt5645_lout_mix[] = {
1271 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_LOUT_MIXER,
1272 RT5645_M_DAC_L1_LM_SFT, 1, 1),
1273 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_LOUT_MIXER,
1274 RT5645_M_DAC_R1_LM_SFT, 1, 1),
1275 SOC_DAPM_SINGLE("OUTMIX L Switch", RT5645_LOUT_MIXER,
1276 RT5645_M_OV_L_LM_SFT, 1, 1),
1277 SOC_DAPM_SINGLE("OUTMIX R Switch", RT5645_LOUT_MIXER,
1278 RT5645_M_OV_R_LM_SFT, 1, 1),
1279 };
1280
1281 /*DAC1 L/R source*/ /* MX-29 [9:8] [11:10] */
1282 static const char * const rt5645_dac1_src[] = {
1283 "IF1 DAC", "IF2 DAC", "IF3 DAC"
1284 };
1285
1286 static SOC_ENUM_SINGLE_DECL(
1287 rt5645_dac1l_enum, RT5645_AD_DA_MIXER,
1288 RT5645_DAC1_L_SEL_SFT, rt5645_dac1_src);
1289
1290 static const struct snd_kcontrol_new rt5645_dac1l_mux =
1291 SOC_DAPM_ENUM("DAC1 L source", rt5645_dac1l_enum);
1292
1293 static SOC_ENUM_SINGLE_DECL(
1294 rt5645_dac1r_enum, RT5645_AD_DA_MIXER,
1295 RT5645_DAC1_R_SEL_SFT, rt5645_dac1_src);
1296
1297 static const struct snd_kcontrol_new rt5645_dac1r_mux =
1298 SOC_DAPM_ENUM("DAC1 R source", rt5645_dac1r_enum);
1299
1300 /*DAC2 L/R source*/ /* MX-1B [6:4] [2:0] */
1301 static const char * const rt5645_dac12_src[] = {
1302 "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "VAD_ADC"
1303 };
1304
1305 static SOC_ENUM_SINGLE_DECL(
1306 rt5645_dac2l_enum, RT5645_DAC_CTRL,
1307 RT5645_DAC2_L_SEL_SFT, rt5645_dac12_src);
1308
1309 static const struct snd_kcontrol_new rt5645_dac_l2_mux =
1310 SOC_DAPM_ENUM("DAC2 L source", rt5645_dac2l_enum);
1311
1312 static const char * const rt5645_dacr2_src[] = {
1313 "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "Haptic"
1314 };
1315
1316 static SOC_ENUM_SINGLE_DECL(
1317 rt5645_dac2r_enum, RT5645_DAC_CTRL,
1318 RT5645_DAC2_R_SEL_SFT, rt5645_dacr2_src);
1319
1320 static const struct snd_kcontrol_new rt5645_dac_r2_mux =
1321 SOC_DAPM_ENUM("DAC2 R source", rt5645_dac2r_enum);
1322
1323 /* Stereo1 ADC source */
1324 /* MX-27 [12] */
1325 static const char * const rt5645_stereo_adc1_src[] = {
1326 "DAC MIX", "ADC"
1327 };
1328
1329 static SOC_ENUM_SINGLE_DECL(
1330 rt5645_stereo1_adc1_enum, RT5645_STO1_ADC_MIXER,
1331 RT5645_ADC_1_SRC_SFT, rt5645_stereo_adc1_src);
1332
1333 static const struct snd_kcontrol_new rt5645_sto_adc1_mux =
1334 SOC_DAPM_ENUM("Stereo1 ADC1 Mux", rt5645_stereo1_adc1_enum);
1335
1336 /* MX-27 [11] */
1337 static const char * const rt5645_stereo_adc2_src[] = {
1338 "DAC MIX", "DMIC"
1339 };
1340
1341 static SOC_ENUM_SINGLE_DECL(
1342 rt5645_stereo1_adc2_enum, RT5645_STO1_ADC_MIXER,
1343 RT5645_ADC_2_SRC_SFT, rt5645_stereo_adc2_src);
1344
1345 static const struct snd_kcontrol_new rt5645_sto_adc2_mux =
1346 SOC_DAPM_ENUM("Stereo1 ADC2 Mux", rt5645_stereo1_adc2_enum);
1347
1348 /* MX-27 [8] */
1349 static const char * const rt5645_stereo_dmic_src[] = {
1350 "DMIC1", "DMIC2"
1351 };
1352
1353 static SOC_ENUM_SINGLE_DECL(
1354 rt5645_stereo1_dmic_enum, RT5645_STO1_ADC_MIXER,
1355 RT5645_DMIC_SRC_SFT, rt5645_stereo_dmic_src);
1356
1357 static const struct snd_kcontrol_new rt5645_sto1_dmic_mux =
1358 SOC_DAPM_ENUM("Stereo1 DMIC source", rt5645_stereo1_dmic_enum);
1359
1360 /* Mono ADC source */
1361 /* MX-28 [12] */
1362 static const char * const rt5645_mono_adc_l1_src[] = {
1363 "Mono DAC MIXL", "ADC"
1364 };
1365
1366 static SOC_ENUM_SINGLE_DECL(
1367 rt5645_mono_adc_l1_enum, RT5645_MONO_ADC_MIXER,
1368 RT5645_MONO_ADC_L1_SRC_SFT, rt5645_mono_adc_l1_src);
1369
1370 static const struct snd_kcontrol_new rt5645_mono_adc_l1_mux =
1371 SOC_DAPM_ENUM("Mono ADC1 left source", rt5645_mono_adc_l1_enum);
1372 /* MX-28 [11] */
1373 static const char * const rt5645_mono_adc_l2_src[] = {
1374 "Mono DAC MIXL", "DMIC"
1375 };
1376
1377 static SOC_ENUM_SINGLE_DECL(
1378 rt5645_mono_adc_l2_enum, RT5645_MONO_ADC_MIXER,
1379 RT5645_MONO_ADC_L2_SRC_SFT, rt5645_mono_adc_l2_src);
1380
1381 static const struct snd_kcontrol_new rt5645_mono_adc_l2_mux =
1382 SOC_DAPM_ENUM("Mono ADC2 left source", rt5645_mono_adc_l2_enum);
1383
1384 /* MX-28 [8] */
1385 static const char * const rt5645_mono_dmic_src[] = {
1386 "DMIC1", "DMIC2"
1387 };
1388
1389 static SOC_ENUM_SINGLE_DECL(
1390 rt5645_mono_dmic_l_enum, RT5645_MONO_ADC_MIXER,
1391 RT5645_MONO_DMIC_L_SRC_SFT, rt5645_mono_dmic_src);
1392
1393 static const struct snd_kcontrol_new rt5645_mono_dmic_l_mux =
1394 SOC_DAPM_ENUM("Mono DMIC left source", rt5645_mono_dmic_l_enum);
1395 /* MX-28 [1:0] */
1396 static SOC_ENUM_SINGLE_DECL(
1397 rt5645_mono_dmic_r_enum, RT5645_MONO_ADC_MIXER,
1398 RT5645_MONO_DMIC_R_SRC_SFT, rt5645_mono_dmic_src);
1399
1400 static const struct snd_kcontrol_new rt5645_mono_dmic_r_mux =
1401 SOC_DAPM_ENUM("Mono DMIC Right source", rt5645_mono_dmic_r_enum);
1402 /* MX-28 [4] */
1403 static const char * const rt5645_mono_adc_r1_src[] = {
1404 "Mono DAC MIXR", "ADC"
1405 };
1406
1407 static SOC_ENUM_SINGLE_DECL(
1408 rt5645_mono_adc_r1_enum, RT5645_MONO_ADC_MIXER,
1409 RT5645_MONO_ADC_R1_SRC_SFT, rt5645_mono_adc_r1_src);
1410
1411 static const struct snd_kcontrol_new rt5645_mono_adc_r1_mux =
1412 SOC_DAPM_ENUM("Mono ADC1 right source", rt5645_mono_adc_r1_enum);
1413 /* MX-28 [3] */
1414 static const char * const rt5645_mono_adc_r2_src[] = {
1415 "Mono DAC MIXR", "DMIC"
1416 };
1417
1418 static SOC_ENUM_SINGLE_DECL(
1419 rt5645_mono_adc_r2_enum, RT5645_MONO_ADC_MIXER,
1420 RT5645_MONO_ADC_R2_SRC_SFT, rt5645_mono_adc_r2_src);
1421
1422 static const struct snd_kcontrol_new rt5645_mono_adc_r2_mux =
1423 SOC_DAPM_ENUM("Mono ADC2 right source", rt5645_mono_adc_r2_enum);
1424
1425 /* MX-77 [9:8] */
1426 static const char * const rt5645_if1_adc_in_src[] = {
1427 "IF_ADC1/IF_ADC2/VAD_ADC", "IF_ADC2/IF_ADC1/VAD_ADC",
1428 "VAD_ADC/IF_ADC1/IF_ADC2", "VAD_ADC/IF_ADC2/IF_ADC1"
1429 };
1430
1431 static SOC_ENUM_SINGLE_DECL(
1432 rt5645_if1_adc_in_enum, RT5645_TDM_CTRL_1,
1433 RT5645_IF1_ADC_IN_SFT, rt5645_if1_adc_in_src);
1434
1435 static const struct snd_kcontrol_new rt5645_if1_adc_in_mux =
1436 SOC_DAPM_ENUM("IF1 ADC IN source", rt5645_if1_adc_in_enum);
1437
1438 /* MX-78 [4:0] */
1439 static const char * const rt5650_if1_adc_in_src[] = {
1440 "IF_ADC1/IF_ADC2/DAC_REF/Null",
1441 "IF_ADC1/IF_ADC2/Null/DAC_REF",
1442 "IF_ADC1/DAC_REF/IF_ADC2/Null",
1443 "IF_ADC1/DAC_REF/Null/IF_ADC2",
1444 "IF_ADC1/Null/DAC_REF/IF_ADC2",
1445 "IF_ADC1/Null/IF_ADC2/DAC_REF",
1446
1447 "IF_ADC2/IF_ADC1/DAC_REF/Null",
1448 "IF_ADC2/IF_ADC1/Null/DAC_REF",
1449 "IF_ADC2/DAC_REF/IF_ADC1/Null",
1450 "IF_ADC2/DAC_REF/Null/IF_ADC1",
1451 "IF_ADC2/Null/DAC_REF/IF_ADC1",
1452 "IF_ADC2/Null/IF_ADC1/DAC_REF",
1453
1454 "DAC_REF/IF_ADC1/IF_ADC2/Null",
1455 "DAC_REF/IF_ADC1/Null/IF_ADC2",
1456 "DAC_REF/IF_ADC2/IF_ADC1/Null",
1457 "DAC_REF/IF_ADC2/Null/IF_ADC1",
1458 "DAC_REF/Null/IF_ADC1/IF_ADC2",
1459 "DAC_REF/Null/IF_ADC2/IF_ADC1",
1460
1461 "Null/IF_ADC1/IF_ADC2/DAC_REF",
1462 "Null/IF_ADC1/DAC_REF/IF_ADC2",
1463 "Null/IF_ADC2/IF_ADC1/DAC_REF",
1464 "Null/IF_ADC2/DAC_REF/IF_ADC1",
1465 "Null/DAC_REF/IF_ADC1/IF_ADC2",
1466 "Null/DAC_REF/IF_ADC2/IF_ADC1",
1467 };
1468
1469 static SOC_ENUM_SINGLE_DECL(
1470 rt5650_if1_adc_in_enum, RT5645_TDM_CTRL_2,
1471 0, rt5650_if1_adc_in_src);
1472
1473 static const struct snd_kcontrol_new rt5650_if1_adc_in_mux =
1474 SOC_DAPM_ENUM("IF1 ADC IN source", rt5650_if1_adc_in_enum);
1475
1476 /* MX-78 [15:14][13:12][11:10] */
1477 static const char * const rt5645_tdm_adc_swap_select[] = {
1478 "L/R", "R/L", "L/L", "R/R"
1479 };
1480
1481 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot0_1_enum,
1482 RT5645_TDM_CTRL_2, 14, rt5645_tdm_adc_swap_select);
1483
1484 static const struct snd_kcontrol_new rt5650_if1_adc1_in_mux =
1485 SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5650_tdm_adc_slot0_1_enum);
1486
1487 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot2_3_enum,
1488 RT5645_TDM_CTRL_2, 12, rt5645_tdm_adc_swap_select);
1489
1490 static const struct snd_kcontrol_new rt5650_if1_adc2_in_mux =
1491 SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5650_tdm_adc_slot2_3_enum);
1492
1493 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot4_5_enum,
1494 RT5645_TDM_CTRL_2, 10, rt5645_tdm_adc_swap_select);
1495
1496 static const struct snd_kcontrol_new rt5650_if1_adc3_in_mux =
1497 SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5650_tdm_adc_slot4_5_enum);
1498
1499 /* MX-77 [7:6][5:4][3:2] */
1500 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot0_1_enum,
1501 RT5645_TDM_CTRL_1, 6, rt5645_tdm_adc_swap_select);
1502
1503 static const struct snd_kcontrol_new rt5645_if1_adc1_in_mux =
1504 SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5645_tdm_adc_slot0_1_enum);
1505
1506 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot2_3_enum,
1507 RT5645_TDM_CTRL_1, 4, rt5645_tdm_adc_swap_select);
1508
1509 static const struct snd_kcontrol_new rt5645_if1_adc2_in_mux =
1510 SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5645_tdm_adc_slot2_3_enum);
1511
1512 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot4_5_enum,
1513 RT5645_TDM_CTRL_1, 2, rt5645_tdm_adc_swap_select);
1514
1515 static const struct snd_kcontrol_new rt5645_if1_adc3_in_mux =
1516 SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5645_tdm_adc_slot4_5_enum);
1517
1518 /* MX-79 [14:12][10:8][6:4][2:0] */
1519 static const char * const rt5645_tdm_dac_swap_select[] = {
1520 "Slot0", "Slot1", "Slot2", "Slot3"
1521 };
1522
1523 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac0_enum,
1524 RT5645_TDM_CTRL_3, 12, rt5645_tdm_dac_swap_select);
1525
1526 static const struct snd_kcontrol_new rt5645_if1_dac0_tdm_sel_mux =
1527 SOC_DAPM_ENUM("IF1 DAC0 source", rt5645_tdm_dac0_enum);
1528
1529 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac1_enum,
1530 RT5645_TDM_CTRL_3, 8, rt5645_tdm_dac_swap_select);
1531
1532 static const struct snd_kcontrol_new rt5645_if1_dac1_tdm_sel_mux =
1533 SOC_DAPM_ENUM("IF1 DAC1 source", rt5645_tdm_dac1_enum);
1534
1535 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac2_enum,
1536 RT5645_TDM_CTRL_3, 4, rt5645_tdm_dac_swap_select);
1537
1538 static const struct snd_kcontrol_new rt5645_if1_dac2_tdm_sel_mux =
1539 SOC_DAPM_ENUM("IF1 DAC2 source", rt5645_tdm_dac2_enum);
1540
1541 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac3_enum,
1542 RT5645_TDM_CTRL_3, 0, rt5645_tdm_dac_swap_select);
1543
1544 static const struct snd_kcontrol_new rt5645_if1_dac3_tdm_sel_mux =
1545 SOC_DAPM_ENUM("IF1 DAC3 source", rt5645_tdm_dac3_enum);
1546
1547 /* MX-7a [14:12][10:8][6:4][2:0] */
1548 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac0_enum,
1549 RT5650_TDM_CTRL_4, 12, rt5645_tdm_dac_swap_select);
1550
1551 static const struct snd_kcontrol_new rt5650_if1_dac0_tdm_sel_mux =
1552 SOC_DAPM_ENUM("IF1 DAC0 source", rt5650_tdm_dac0_enum);
1553
1554 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac1_enum,
1555 RT5650_TDM_CTRL_4, 8, rt5645_tdm_dac_swap_select);
1556
1557 static const struct snd_kcontrol_new rt5650_if1_dac1_tdm_sel_mux =
1558 SOC_DAPM_ENUM("IF1 DAC1 source", rt5650_tdm_dac1_enum);
1559
1560 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac2_enum,
1561 RT5650_TDM_CTRL_4, 4, rt5645_tdm_dac_swap_select);
1562
1563 static const struct snd_kcontrol_new rt5650_if1_dac2_tdm_sel_mux =
1564 SOC_DAPM_ENUM("IF1 DAC2 source", rt5650_tdm_dac2_enum);
1565
1566 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac3_enum,
1567 RT5650_TDM_CTRL_4, 0, rt5645_tdm_dac_swap_select);
1568
1569 static const struct snd_kcontrol_new rt5650_if1_dac3_tdm_sel_mux =
1570 SOC_DAPM_ENUM("IF1 DAC3 source", rt5650_tdm_dac3_enum);
1571
1572 /* MX-2d [3] [2] */
1573 static const char * const rt5650_a_dac1_src[] = {
1574 "DAC1", "Stereo DAC Mixer"
1575 };
1576
1577 static SOC_ENUM_SINGLE_DECL(
1578 rt5650_a_dac1_l_enum, RT5650_A_DAC_SOUR,
1579 RT5650_A_DAC1_L_IN_SFT, rt5650_a_dac1_src);
1580
1581 static const struct snd_kcontrol_new rt5650_a_dac1_l_mux =
1582 SOC_DAPM_ENUM("A DAC1 L source", rt5650_a_dac1_l_enum);
1583
1584 static SOC_ENUM_SINGLE_DECL(
1585 rt5650_a_dac1_r_enum, RT5650_A_DAC_SOUR,
1586 RT5650_A_DAC1_R_IN_SFT, rt5650_a_dac1_src);
1587
1588 static const struct snd_kcontrol_new rt5650_a_dac1_r_mux =
1589 SOC_DAPM_ENUM("A DAC1 R source", rt5650_a_dac1_r_enum);
1590
1591 /* MX-2d [1] [0] */
1592 static const char * const rt5650_a_dac2_src[] = {
1593 "Stereo DAC Mixer", "Mono DAC Mixer"
1594 };
1595
1596 static SOC_ENUM_SINGLE_DECL(
1597 rt5650_a_dac2_l_enum, RT5650_A_DAC_SOUR,
1598 RT5650_A_DAC2_L_IN_SFT, rt5650_a_dac2_src);
1599
1600 static const struct snd_kcontrol_new rt5650_a_dac2_l_mux =
1601 SOC_DAPM_ENUM("A DAC2 L source", rt5650_a_dac2_l_enum);
1602
1603 static SOC_ENUM_SINGLE_DECL(
1604 rt5650_a_dac2_r_enum, RT5650_A_DAC_SOUR,
1605 RT5650_A_DAC2_R_IN_SFT, rt5650_a_dac2_src);
1606
1607 static const struct snd_kcontrol_new rt5650_a_dac2_r_mux =
1608 SOC_DAPM_ENUM("A DAC2 R source", rt5650_a_dac2_r_enum);
1609
1610 /* MX-2F [13:12] */
1611 static const char * const rt5645_if2_adc_in_src[] = {
1612 "IF_ADC1", "IF_ADC2", "VAD_ADC"
1613 };
1614
1615 static SOC_ENUM_SINGLE_DECL(
1616 rt5645_if2_adc_in_enum, RT5645_DIG_INF1_DATA,
1617 RT5645_IF2_ADC_IN_SFT, rt5645_if2_adc_in_src);
1618
1619 static const struct snd_kcontrol_new rt5645_if2_adc_in_mux =
1620 SOC_DAPM_ENUM("IF2 ADC IN source", rt5645_if2_adc_in_enum);
1621
1622 /* MX-31 [15] [13] [11] [9] */
1623 static const char * const rt5645_pdm_src[] = {
1624 "Mono DAC", "Stereo DAC"
1625 };
1626
1627 static SOC_ENUM_SINGLE_DECL(
1628 rt5645_pdm1_l_enum, RT5645_PDM_OUT_CTRL,
1629 RT5645_PDM1_L_SFT, rt5645_pdm_src);
1630
1631 static const struct snd_kcontrol_new rt5645_pdm1_l_mux =
1632 SOC_DAPM_ENUM("PDM1 L source", rt5645_pdm1_l_enum);
1633
1634 static SOC_ENUM_SINGLE_DECL(
1635 rt5645_pdm1_r_enum, RT5645_PDM_OUT_CTRL,
1636 RT5645_PDM1_R_SFT, rt5645_pdm_src);
1637
1638 static const struct snd_kcontrol_new rt5645_pdm1_r_mux =
1639 SOC_DAPM_ENUM("PDM1 R source", rt5645_pdm1_r_enum);
1640
1641 /* MX-9D [9:8] */
1642 static const char * const rt5645_vad_adc_src[] = {
1643 "Sto1 ADC L", "Mono ADC L", "Mono ADC R"
1644 };
1645
1646 static SOC_ENUM_SINGLE_DECL(
1647 rt5645_vad_adc_enum, RT5645_VAD_CTRL4,
1648 RT5645_VAD_SEL_SFT, rt5645_vad_adc_src);
1649
1650 static const struct snd_kcontrol_new rt5645_vad_adc_mux =
1651 SOC_DAPM_ENUM("VAD ADC source", rt5645_vad_adc_enum);
1652
1653 static const struct snd_kcontrol_new spk_l_vol_control =
1654 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL,
1655 RT5645_L_MUTE_SFT, 1, 1);
1656
1657 static const struct snd_kcontrol_new spk_r_vol_control =
1658 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL,
1659 RT5645_R_MUTE_SFT, 1, 1);
1660
1661 static const struct snd_kcontrol_new hp_l_vol_control =
1662 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL,
1663 RT5645_L_MUTE_SFT, 1, 1);
1664
1665 static const struct snd_kcontrol_new hp_r_vol_control =
1666 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL,
1667 RT5645_R_MUTE_SFT, 1, 1);
1668
1669 static const struct snd_kcontrol_new pdm1_l_vol_control =
1670 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL,
1671 RT5645_M_PDM1_L, 1, 1);
1672
1673 static const struct snd_kcontrol_new pdm1_r_vol_control =
1674 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL,
1675 RT5645_M_PDM1_R, 1, 1);
1676
hp_amp_power(struct snd_soc_component * component,int on)1677 static void hp_amp_power(struct snd_soc_component *component, int on)
1678 {
1679 static int hp_amp_power_count;
1680 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
1681 int i, val;
1682
1683 if (on) {
1684 if (hp_amp_power_count <= 0) {
1685 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
1686 snd_soc_component_write(component, RT5645_DEPOP_M2, 0x3100);
1687 snd_soc_component_write(component, RT5645_CHARGE_PUMP,
1688 0x0e06);
1689 snd_soc_component_write(component, RT5645_DEPOP_M1, 0x000d);
1690 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1691 RT5645_HP_DCC_INT1, 0x9f01);
1692 for (i = 0; i < 20; i++) {
1693 usleep_range(1000, 1500);
1694 regmap_read(rt5645->regmap, RT5645_PR_BASE +
1695 RT5645_HP_DCC_INT1, &val);
1696 if (!(val & 0x8000))
1697 break;
1698 }
1699 snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1700 RT5645_HP_CO_MASK, RT5645_HP_CO_EN);
1701 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1702 0x3e, 0x7400);
1703 snd_soc_component_write(component, RT5645_DEPOP_M3, 0x0737);
1704 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1705 RT5645_MAMP_INT_REG2, 0xfc00);
1706 snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1140);
1707 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
1708 RT5645_PWR_HP_L | RT5645_PWR_HP_R,
1709 RT5645_PWR_HP_L | RT5645_PWR_HP_R);
1710 msleep(90);
1711 } else {
1712 /* depop parameters */
1713 snd_soc_component_update_bits(component, RT5645_DEPOP_M2,
1714 RT5645_DEPOP_MASK, RT5645_DEPOP_MAN);
1715 snd_soc_component_write(component, RT5645_DEPOP_M1, 0x000d);
1716 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1717 RT5645_HP_DCC_INT1, 0x9f01);
1718 mdelay(150);
1719 /* headphone amp power on */
1720 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
1721 RT5645_PWR_FV1 | RT5645_PWR_FV2, 0);
1722 snd_soc_component_update_bits(component, RT5645_PWR_VOL,
1723 RT5645_PWR_HV_L | RT5645_PWR_HV_R,
1724 RT5645_PWR_HV_L | RT5645_PWR_HV_R);
1725 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
1726 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1727 RT5645_PWR_HA,
1728 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1729 RT5645_PWR_HA);
1730 mdelay(5);
1731 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
1732 RT5645_PWR_FV1 | RT5645_PWR_FV2,
1733 RT5645_PWR_FV1 | RT5645_PWR_FV2);
1734
1735 snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1736 RT5645_HP_CO_MASK | RT5645_HP_SG_MASK,
1737 RT5645_HP_CO_EN | RT5645_HP_SG_EN);
1738 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1739 0x14, 0x1aaa);
1740 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1741 0x24, 0x0430);
1742 }
1743 }
1744 hp_amp_power_count++;
1745 } else {
1746 hp_amp_power_count--;
1747 if (hp_amp_power_count <= 0) {
1748 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
1749 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1750 0x3e, 0x7400);
1751 snd_soc_component_write(component, RT5645_DEPOP_M3, 0x0737);
1752 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1753 RT5645_MAMP_INT_REG2, 0xfc00);
1754 snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1140);
1755 msleep(100);
1756 snd_soc_component_write(component, RT5645_DEPOP_M1, 0x0001);
1757 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
1758 RT5645_PWR_HP_L | RT5645_PWR_HP_R, 0);
1759 } else {
1760 snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1761 RT5645_HP_SG_MASK |
1762 RT5645_HP_L_SMT_MASK |
1763 RT5645_HP_R_SMT_MASK,
1764 RT5645_HP_SG_DIS |
1765 RT5645_HP_L_SMT_DIS |
1766 RT5645_HP_R_SMT_DIS);
1767 /* headphone amp power down */
1768 snd_soc_component_write(component, RT5645_DEPOP_M1, 0x0000);
1769 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
1770 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1771 RT5645_PWR_HA, 0);
1772 snd_soc_component_update_bits(component, RT5645_DEPOP_M2,
1773 RT5645_DEPOP_MASK, 0);
1774 }
1775 }
1776 }
1777 }
1778
rt5645_hp_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1779 static int rt5645_hp_event(struct snd_soc_dapm_widget *w,
1780 struct snd_kcontrol *kcontrol, int event)
1781 {
1782 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1783 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
1784
1785 switch (event) {
1786 case SND_SOC_DAPM_POST_PMU:
1787 hp_amp_power(component, 1);
1788 /* headphone unmute sequence */
1789 if (rt5645->codec_type == CODEC_TYPE_RT5645) {
1790 snd_soc_component_update_bits(component, RT5645_DEPOP_M3,
1791 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK |
1792 RT5645_CP_FQ3_MASK,
1793 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ1_SFT) |
1794 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) |
1795 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ3_SFT));
1796 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1797 RT5645_MAMP_INT_REG2, 0xfc00);
1798 snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1799 RT5645_SMT_TRIG_MASK, RT5645_SMT_TRIG_EN);
1800 snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1801 RT5645_RSTN_MASK, RT5645_RSTN_EN);
1802 snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1803 RT5645_RSTN_MASK | RT5645_HP_L_SMT_MASK |
1804 RT5645_HP_R_SMT_MASK, RT5645_RSTN_DIS |
1805 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);
1806 msleep(40);
1807 snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1808 RT5645_HP_SG_MASK | RT5645_HP_L_SMT_MASK |
1809 RT5645_HP_R_SMT_MASK, RT5645_HP_SG_DIS |
1810 RT5645_HP_L_SMT_DIS | RT5645_HP_R_SMT_DIS);
1811 }
1812 break;
1813
1814 case SND_SOC_DAPM_PRE_PMD:
1815 /* headphone mute sequence */
1816 if (rt5645->codec_type == CODEC_TYPE_RT5645) {
1817 snd_soc_component_update_bits(component, RT5645_DEPOP_M3,
1818 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK |
1819 RT5645_CP_FQ3_MASK,
1820 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ1_SFT) |
1821 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) |
1822 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ3_SFT));
1823 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1824 RT5645_MAMP_INT_REG2, 0xfc00);
1825 snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1826 RT5645_HP_SG_MASK, RT5645_HP_SG_EN);
1827 snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1828 RT5645_RSTP_MASK, RT5645_RSTP_EN);
1829 snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1830 RT5645_RSTP_MASK | RT5645_HP_L_SMT_MASK |
1831 RT5645_HP_R_SMT_MASK, RT5645_RSTP_DIS |
1832 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);
1833 msleep(30);
1834 }
1835 hp_amp_power(component, 0);
1836 break;
1837
1838 default:
1839 return 0;
1840 }
1841
1842 return 0;
1843 }
1844
rt5645_spk_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1845 static int rt5645_spk_event(struct snd_soc_dapm_widget *w,
1846 struct snd_kcontrol *kcontrol, int event)
1847 {
1848 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1849
1850 switch (event) {
1851 case SND_SOC_DAPM_POST_PMU:
1852 rt5645_enable_hweq(component);
1853 snd_soc_component_update_bits(component, RT5645_PWR_DIG1,
1854 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1855 RT5645_PWR_CLS_D_L,
1856 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1857 RT5645_PWR_CLS_D_L);
1858 snd_soc_component_update_bits(component, RT5645_GEN_CTRL3,
1859 RT5645_DET_CLK_MASK, RT5645_DET_CLK_MODE1);
1860 break;
1861
1862 case SND_SOC_DAPM_PRE_PMD:
1863 snd_soc_component_update_bits(component, RT5645_GEN_CTRL3,
1864 RT5645_DET_CLK_MASK, RT5645_DET_CLK_DIS);
1865 snd_soc_component_write(component, RT5645_EQ_CTRL2, 0);
1866 snd_soc_component_update_bits(component, RT5645_PWR_DIG1,
1867 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1868 RT5645_PWR_CLS_D_L, 0);
1869 break;
1870
1871 default:
1872 return 0;
1873 }
1874
1875 return 0;
1876 }
1877
rt5645_lout_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1878 static int rt5645_lout_event(struct snd_soc_dapm_widget *w,
1879 struct snd_kcontrol *kcontrol, int event)
1880 {
1881 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1882
1883 switch (event) {
1884 case SND_SOC_DAPM_POST_PMU:
1885 hp_amp_power(component, 1);
1886 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
1887 RT5645_PWR_LM, RT5645_PWR_LM);
1888 snd_soc_component_update_bits(component, RT5645_LOUT1,
1889 RT5645_L_MUTE | RT5645_R_MUTE, 0);
1890 break;
1891
1892 case SND_SOC_DAPM_PRE_PMD:
1893 snd_soc_component_update_bits(component, RT5645_LOUT1,
1894 RT5645_L_MUTE | RT5645_R_MUTE,
1895 RT5645_L_MUTE | RT5645_R_MUTE);
1896 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
1897 RT5645_PWR_LM, 0);
1898 hp_amp_power(component, 0);
1899 break;
1900
1901 default:
1902 return 0;
1903 }
1904
1905 return 0;
1906 }
1907
rt5645_bst2_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1908 static int rt5645_bst2_event(struct snd_soc_dapm_widget *w,
1909 struct snd_kcontrol *kcontrol, int event)
1910 {
1911 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1912
1913 switch (event) {
1914 case SND_SOC_DAPM_POST_PMU:
1915 snd_soc_component_update_bits(component, RT5645_PWR_ANLG2,
1916 RT5645_PWR_BST2_P, RT5645_PWR_BST2_P);
1917 break;
1918
1919 case SND_SOC_DAPM_PRE_PMD:
1920 snd_soc_component_update_bits(component, RT5645_PWR_ANLG2,
1921 RT5645_PWR_BST2_P, 0);
1922 break;
1923
1924 default:
1925 return 0;
1926 }
1927
1928 return 0;
1929 }
1930
rt5645_set_micbias1_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * k,int event)1931 static int rt5645_set_micbias1_event(struct snd_soc_dapm_widget *w,
1932 struct snd_kcontrol *k, int event)
1933 {
1934 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1935
1936 switch (event) {
1937 case SND_SOC_DAPM_PRE_PMU:
1938 snd_soc_component_update_bits(component, RT5645_GEN_CTRL2,
1939 RT5645_MICBIAS1_POW_CTRL_SEL_MASK,
1940 RT5645_MICBIAS1_POW_CTRL_SEL_M);
1941 break;
1942
1943 case SND_SOC_DAPM_POST_PMD:
1944 snd_soc_component_update_bits(component, RT5645_GEN_CTRL2,
1945 RT5645_MICBIAS1_POW_CTRL_SEL_MASK,
1946 RT5645_MICBIAS1_POW_CTRL_SEL_A);
1947 break;
1948
1949 default:
1950 return 0;
1951 }
1952
1953 return 0;
1954 }
1955
rt5645_set_micbias2_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * k,int event)1956 static int rt5645_set_micbias2_event(struct snd_soc_dapm_widget *w,
1957 struct snd_kcontrol *k, int event)
1958 {
1959 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1960
1961 switch (event) {
1962 case SND_SOC_DAPM_PRE_PMU:
1963 snd_soc_component_update_bits(component, RT5645_GEN_CTRL2,
1964 RT5645_MICBIAS2_POW_CTRL_SEL_MASK,
1965 RT5645_MICBIAS2_POW_CTRL_SEL_M);
1966 break;
1967
1968 case SND_SOC_DAPM_POST_PMD:
1969 snd_soc_component_update_bits(component, RT5645_GEN_CTRL2,
1970 RT5645_MICBIAS2_POW_CTRL_SEL_MASK,
1971 RT5645_MICBIAS2_POW_CTRL_SEL_A);
1972 break;
1973
1974 default:
1975 return 0;
1976 }
1977
1978 return 0;
1979 }
1980
1981 static const struct snd_soc_dapm_widget rt5645_dapm_widgets[] = {
1982 SND_SOC_DAPM_SUPPLY("LDO2", RT5645_PWR_MIXER,
1983 RT5645_PWR_LDO2_BIT, 0, NULL, 0),
1984 SND_SOC_DAPM_SUPPLY("PLL1", RT5645_PWR_ANLG2,
1985 RT5645_PWR_PLL_BIT, 0, NULL, 0),
1986
1987 SND_SOC_DAPM_SUPPLY("JD Power", RT5645_PWR_ANLG2,
1988 RT5645_PWR_JD1_BIT, 0, NULL, 0),
1989 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5645_PWR_VOL,
1990 RT5645_PWR_MIC_DET_BIT, 0, NULL, 0),
1991
1992 /* ASRC */
1993 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5645_ASRC_1,
1994 11, 0, NULL, 0),
1995 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5645_ASRC_1,
1996 12, 0, NULL, 0),
1997 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5645_ASRC_1,
1998 10, 0, NULL, 0),
1999 SND_SOC_DAPM_SUPPLY_S("DAC MONO L ASRC", 1, RT5645_ASRC_1,
2000 9, 0, NULL, 0),
2001 SND_SOC_DAPM_SUPPLY_S("DAC MONO R ASRC", 1, RT5645_ASRC_1,
2002 8, 0, NULL, 0),
2003 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5645_ASRC_1,
2004 7, 0, NULL, 0),
2005 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5645_ASRC_1,
2006 5, 0, NULL, 0),
2007 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5645_ASRC_1,
2008 4, 0, NULL, 0),
2009 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5645_ASRC_1,
2010 3, 0, NULL, 0),
2011 SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5645_ASRC_1,
2012 1, 0, NULL, 0),
2013 SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5645_ASRC_1,
2014 0, 0, NULL, 0),
2015
2016 /* Input Side */
2017 /* micbias */
2018 SND_SOC_DAPM_SUPPLY("micbias1", RT5645_PWR_ANLG2,
2019 RT5645_PWR_MB1_BIT, 0, rt5645_set_micbias1_event,
2020 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2021 SND_SOC_DAPM_SUPPLY("micbias2", RT5645_PWR_ANLG2,
2022 RT5645_PWR_MB2_BIT, 0, rt5645_set_micbias2_event,
2023 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2024 /* Input Lines */
2025 SND_SOC_DAPM_INPUT("DMIC L1"),
2026 SND_SOC_DAPM_INPUT("DMIC R1"),
2027 SND_SOC_DAPM_INPUT("DMIC L2"),
2028 SND_SOC_DAPM_INPUT("DMIC R2"),
2029
2030 SND_SOC_DAPM_INPUT("IN1P"),
2031 SND_SOC_DAPM_INPUT("IN1N"),
2032 SND_SOC_DAPM_INPUT("IN2P"),
2033 SND_SOC_DAPM_INPUT("IN2N"),
2034
2035 SND_SOC_DAPM_INPUT("Haptic Generator"),
2036
2037 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2038 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2039 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
2040 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
2041 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5645_DMIC_CTRL1,
2042 RT5645_DMIC_1_EN_SFT, 0, NULL, 0),
2043 SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5645_DMIC_CTRL1,
2044 RT5645_DMIC_2_EN_SFT, 0, NULL, 0),
2045 /* Boost */
2046 SND_SOC_DAPM_PGA("BST1", RT5645_PWR_ANLG2,
2047 RT5645_PWR_BST1_BIT, 0, NULL, 0),
2048 SND_SOC_DAPM_PGA_E("BST2", RT5645_PWR_ANLG2,
2049 RT5645_PWR_BST2_BIT, 0, NULL, 0, rt5645_bst2_event,
2050 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2051 /* Input Volume */
2052 SND_SOC_DAPM_PGA("INL VOL", RT5645_PWR_VOL,
2053 RT5645_PWR_IN_L_BIT, 0, NULL, 0),
2054 SND_SOC_DAPM_PGA("INR VOL", RT5645_PWR_VOL,
2055 RT5645_PWR_IN_R_BIT, 0, NULL, 0),
2056 /* REC Mixer */
2057 SND_SOC_DAPM_MIXER("RECMIXL", RT5645_PWR_MIXER, RT5645_PWR_RM_L_BIT,
2058 0, rt5645_rec_l_mix, ARRAY_SIZE(rt5645_rec_l_mix)),
2059 SND_SOC_DAPM_MIXER("RECMIXR", RT5645_PWR_MIXER, RT5645_PWR_RM_R_BIT,
2060 0, rt5645_rec_r_mix, ARRAY_SIZE(rt5645_rec_r_mix)),
2061 /* ADCs */
2062 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
2063 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
2064
2065 SND_SOC_DAPM_SUPPLY("ADC L power", RT5645_PWR_DIG1,
2066 RT5645_PWR_ADC_L_BIT, 0, NULL, 0),
2067 SND_SOC_DAPM_SUPPLY("ADC R power", RT5645_PWR_DIG1,
2068 RT5645_PWR_ADC_R_BIT, 0, NULL, 0),
2069
2070 /* ADC Mux */
2071 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
2072 &rt5645_sto1_dmic_mux),
2073 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2074 &rt5645_sto_adc2_mux),
2075 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2076 &rt5645_sto_adc2_mux),
2077 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2078 &rt5645_sto_adc1_mux),
2079 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2080 &rt5645_sto_adc1_mux),
2081 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2082 &rt5645_mono_dmic_l_mux),
2083 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2084 &rt5645_mono_dmic_r_mux),
2085 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2086 &rt5645_mono_adc_l2_mux),
2087 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2088 &rt5645_mono_adc_l1_mux),
2089 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2090 &rt5645_mono_adc_r1_mux),
2091 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2092 &rt5645_mono_adc_r2_mux),
2093 /* ADC Mixer */
2094
2095 SND_SOC_DAPM_SUPPLY_S("adc stereo1 filter", 1, RT5645_PWR_DIG2,
2096 RT5645_PWR_ADC_S1F_BIT, 0, NULL, 0),
2097 SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
2098 rt5645_sto1_adc_l_mix, ARRAY_SIZE(rt5645_sto1_adc_l_mix),
2099 NULL, 0),
2100 SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
2101 rt5645_sto1_adc_r_mix, ARRAY_SIZE(rt5645_sto1_adc_r_mix),
2102 NULL, 0),
2103 SND_SOC_DAPM_SUPPLY_S("adc mono left filter", 1, RT5645_PWR_DIG2,
2104 RT5645_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2105 SND_SOC_DAPM_MIXER_E("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
2106 rt5645_mono_adc_l_mix, ARRAY_SIZE(rt5645_mono_adc_l_mix),
2107 NULL, 0),
2108 SND_SOC_DAPM_SUPPLY_S("adc mono right filter", 1, RT5645_PWR_DIG2,
2109 RT5645_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2110 SND_SOC_DAPM_MIXER_E("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
2111 rt5645_mono_adc_r_mix, ARRAY_SIZE(rt5645_mono_adc_r_mix),
2112 NULL, 0),
2113
2114 /* ADC PGA */
2115 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2116 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2117 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2118 SND_SOC_DAPM_PGA("VAD_ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2119 SND_SOC_DAPM_PGA("IF_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2120 SND_SOC_DAPM_PGA("IF_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2121 SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2122 SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2123 SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2124 SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2125
2126 /* IF1 2 Mux */
2127 SND_SOC_DAPM_MUX("IF2 ADC Mux", SND_SOC_NOPM,
2128 0, 0, &rt5645_if2_adc_in_mux),
2129
2130 /* Digital Interface */
2131 SND_SOC_DAPM_SUPPLY("I2S1", RT5645_PWR_DIG1,
2132 RT5645_PWR_I2S1_BIT, 0, NULL, 0),
2133 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2134 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2135 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2136 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2137 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2138 SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2139 SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2140 SND_SOC_DAPM_SUPPLY("I2S2", RT5645_PWR_DIG1,
2141 RT5645_PWR_I2S2_BIT, 0, NULL, 0),
2142 SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2143 SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2144 SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2145 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2146
2147 /* Digital Interface Select */
2148 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM,
2149 0, 0, &rt5645_vad_adc_mux),
2150
2151 /* Audio Interface */
2152 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
2153 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
2154 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
2155 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
2156
2157 /* Output Side */
2158 /* DAC mixer before sound effect */
2159 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
2160 rt5645_dac_l_mix, ARRAY_SIZE(rt5645_dac_l_mix)),
2161 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
2162 rt5645_dac_r_mix, ARRAY_SIZE(rt5645_dac_r_mix)),
2163
2164 /* DAC2 channel Mux */
2165 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_l2_mux),
2166 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_r2_mux),
2167 SND_SOC_DAPM_PGA("DAC L2 Volume", RT5645_PWR_DIG1,
2168 RT5645_PWR_DAC_L2_BIT, 0, NULL, 0),
2169 SND_SOC_DAPM_PGA("DAC R2 Volume", RT5645_PWR_DIG1,
2170 RT5645_PWR_DAC_R2_BIT, 0, NULL, 0),
2171
2172 SND_SOC_DAPM_MUX("DAC1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1l_mux),
2173 SND_SOC_DAPM_MUX("DAC1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1r_mux),
2174
2175 /* DAC Mixer */
2176 SND_SOC_DAPM_SUPPLY_S("dac stereo1 filter", 1, RT5645_PWR_DIG2,
2177 RT5645_PWR_DAC_S1F_BIT, 0, NULL, 0),
2178 SND_SOC_DAPM_SUPPLY_S("dac mono left filter", 1, RT5645_PWR_DIG2,
2179 RT5645_PWR_DAC_MF_L_BIT, 0, NULL, 0),
2180 SND_SOC_DAPM_SUPPLY_S("dac mono right filter", 1, RT5645_PWR_DIG2,
2181 RT5645_PWR_DAC_MF_R_BIT, 0, NULL, 0),
2182 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
2183 rt5645_sto_dac_l_mix, ARRAY_SIZE(rt5645_sto_dac_l_mix)),
2184 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
2185 rt5645_sto_dac_r_mix, ARRAY_SIZE(rt5645_sto_dac_r_mix)),
2186 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
2187 rt5645_mono_dac_l_mix, ARRAY_SIZE(rt5645_mono_dac_l_mix)),
2188 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
2189 rt5645_mono_dac_r_mix, ARRAY_SIZE(rt5645_mono_dac_r_mix)),
2190 SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
2191 rt5645_dig_l_mix, ARRAY_SIZE(rt5645_dig_l_mix)),
2192 SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
2193 rt5645_dig_r_mix, ARRAY_SIZE(rt5645_dig_r_mix)),
2194
2195 /* DACs */
2196 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L1_BIT,
2197 0),
2198 SND_SOC_DAPM_DAC("DAC L2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L2_BIT,
2199 0),
2200 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R1_BIT,
2201 0),
2202 SND_SOC_DAPM_DAC("DAC R2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R2_BIT,
2203 0),
2204 /* OUT Mixer */
2205 SND_SOC_DAPM_MIXER("SPK MIXL", RT5645_PWR_MIXER, RT5645_PWR_SM_L_BIT,
2206 0, rt5645_spk_l_mix, ARRAY_SIZE(rt5645_spk_l_mix)),
2207 SND_SOC_DAPM_MIXER("SPK MIXR", RT5645_PWR_MIXER, RT5645_PWR_SM_R_BIT,
2208 0, rt5645_spk_r_mix, ARRAY_SIZE(rt5645_spk_r_mix)),
2209 SND_SOC_DAPM_MIXER("OUT MIXL", RT5645_PWR_MIXER, RT5645_PWR_OM_L_BIT,
2210 0, rt5645_out_l_mix, ARRAY_SIZE(rt5645_out_l_mix)),
2211 SND_SOC_DAPM_MIXER("OUT MIXR", RT5645_PWR_MIXER, RT5645_PWR_OM_R_BIT,
2212 0, rt5645_out_r_mix, ARRAY_SIZE(rt5645_out_r_mix)),
2213 /* Ouput Volume */
2214 SND_SOC_DAPM_SWITCH("SPKVOL L", RT5645_PWR_VOL, RT5645_PWR_SV_L_BIT, 0,
2215 &spk_l_vol_control),
2216 SND_SOC_DAPM_SWITCH("SPKVOL R", RT5645_PWR_VOL, RT5645_PWR_SV_R_BIT, 0,
2217 &spk_r_vol_control),
2218 SND_SOC_DAPM_MIXER("HPOVOL MIXL", RT5645_PWR_VOL, RT5645_PWR_HV_L_BIT,
2219 0, rt5645_hpvoll_mix, ARRAY_SIZE(rt5645_hpvoll_mix)),
2220 SND_SOC_DAPM_MIXER("HPOVOL MIXR", RT5645_PWR_VOL, RT5645_PWR_HV_R_BIT,
2221 0, rt5645_hpvolr_mix, ARRAY_SIZE(rt5645_hpvolr_mix)),
2222 SND_SOC_DAPM_SUPPLY("HPOVOL MIXL Power", RT5645_PWR_MIXER,
2223 RT5645_PWR_HM_L_BIT, 0, NULL, 0),
2224 SND_SOC_DAPM_SUPPLY("HPOVOL MIXR Power", RT5645_PWR_MIXER,
2225 RT5645_PWR_HM_R_BIT, 0, NULL, 0),
2226 SND_SOC_DAPM_PGA("DAC 1", SND_SOC_NOPM, 0, 0, NULL, 0),
2227 SND_SOC_DAPM_PGA("DAC 2", SND_SOC_NOPM, 0, 0, NULL, 0),
2228 SND_SOC_DAPM_PGA("HPOVOL", SND_SOC_NOPM, 0, 0, NULL, 0),
2229 SND_SOC_DAPM_SWITCH("HPOVOL L", SND_SOC_NOPM, 0, 0, &hp_l_vol_control),
2230 SND_SOC_DAPM_SWITCH("HPOVOL R", SND_SOC_NOPM, 0, 0, &hp_r_vol_control),
2231
2232 /* HPO/LOUT/Mono Mixer */
2233 SND_SOC_DAPM_MIXER("SPOL MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_l_mix,
2234 ARRAY_SIZE(rt5645_spo_l_mix)),
2235 SND_SOC_DAPM_MIXER("SPOR MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_r_mix,
2236 ARRAY_SIZE(rt5645_spo_r_mix)),
2237 SND_SOC_DAPM_MIXER("HPO MIX", SND_SOC_NOPM, 0, 0, rt5645_hpo_mix,
2238 ARRAY_SIZE(rt5645_hpo_mix)),
2239 SND_SOC_DAPM_MIXER("LOUT MIX", SND_SOC_NOPM, 0, 0, rt5645_lout_mix,
2240 ARRAY_SIZE(rt5645_lout_mix)),
2241
2242 SND_SOC_DAPM_PGA_S("HP amp", 1, SND_SOC_NOPM, 0, 0, rt5645_hp_event,
2243 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2244 SND_SOC_DAPM_PGA_S("LOUT amp", 1, SND_SOC_NOPM, 0, 0, rt5645_lout_event,
2245 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2246 SND_SOC_DAPM_PGA_S("SPK amp", 2, SND_SOC_NOPM, 0, 0, rt5645_spk_event,
2247 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2248
2249 /* PDM */
2250 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5645_PWR_DIG2, RT5645_PWR_PDM1_BIT,
2251 0, NULL, 0),
2252 SND_SOC_DAPM_MUX("PDM1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_l_mux),
2253 SND_SOC_DAPM_MUX("PDM1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_r_mux),
2254
2255 SND_SOC_DAPM_SWITCH("PDM1 L", SND_SOC_NOPM, 0, 0, &pdm1_l_vol_control),
2256 SND_SOC_DAPM_SWITCH("PDM1 R", SND_SOC_NOPM, 0, 0, &pdm1_r_vol_control),
2257
2258 /* Output Lines */
2259 SND_SOC_DAPM_OUTPUT("HPOL"),
2260 SND_SOC_DAPM_OUTPUT("HPOR"),
2261 SND_SOC_DAPM_OUTPUT("LOUTL"),
2262 SND_SOC_DAPM_OUTPUT("LOUTR"),
2263 SND_SOC_DAPM_OUTPUT("PDM1L"),
2264 SND_SOC_DAPM_OUTPUT("PDM1R"),
2265 SND_SOC_DAPM_OUTPUT("SPOL"),
2266 SND_SOC_DAPM_OUTPUT("SPOR"),
2267 };
2268
2269 static const struct snd_soc_dapm_widget rt5645_specific_dapm_widgets[] = {
2270 SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0,
2271 &rt5645_if1_dac0_tdm_sel_mux),
2272 SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0,
2273 &rt5645_if1_dac1_tdm_sel_mux),
2274 SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0,
2275 &rt5645_if1_dac2_tdm_sel_mux),
2276 SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0,
2277 &rt5645_if1_dac3_tdm_sel_mux),
2278 SND_SOC_DAPM_MUX("RT5645 IF1 ADC Mux", SND_SOC_NOPM,
2279 0, 0, &rt5645_if1_adc_in_mux),
2280 SND_SOC_DAPM_MUX("RT5645 IF1 ADC1 Swap Mux", SND_SOC_NOPM,
2281 0, 0, &rt5645_if1_adc1_in_mux),
2282 SND_SOC_DAPM_MUX("RT5645 IF1 ADC2 Swap Mux", SND_SOC_NOPM,
2283 0, 0, &rt5645_if1_adc2_in_mux),
2284 SND_SOC_DAPM_MUX("RT5645 IF1 ADC3 Swap Mux", SND_SOC_NOPM,
2285 0, 0, &rt5645_if1_adc3_in_mux),
2286 };
2287
2288 static const struct snd_soc_dapm_widget rt5650_specific_dapm_widgets[] = {
2289 SND_SOC_DAPM_MUX("A DAC1 L Mux", SND_SOC_NOPM,
2290 0, 0, &rt5650_a_dac1_l_mux),
2291 SND_SOC_DAPM_MUX("A DAC1 R Mux", SND_SOC_NOPM,
2292 0, 0, &rt5650_a_dac1_r_mux),
2293 SND_SOC_DAPM_MUX("A DAC2 L Mux", SND_SOC_NOPM,
2294 0, 0, &rt5650_a_dac2_l_mux),
2295 SND_SOC_DAPM_MUX("A DAC2 R Mux", SND_SOC_NOPM,
2296 0, 0, &rt5650_a_dac2_r_mux),
2297
2298 SND_SOC_DAPM_MUX("RT5650 IF1 ADC1 Swap Mux", SND_SOC_NOPM,
2299 0, 0, &rt5650_if1_adc1_in_mux),
2300 SND_SOC_DAPM_MUX("RT5650 IF1 ADC2 Swap Mux", SND_SOC_NOPM,
2301 0, 0, &rt5650_if1_adc2_in_mux),
2302 SND_SOC_DAPM_MUX("RT5650 IF1 ADC3 Swap Mux", SND_SOC_NOPM,
2303 0, 0, &rt5650_if1_adc3_in_mux),
2304 SND_SOC_DAPM_MUX("RT5650 IF1 ADC Mux", SND_SOC_NOPM,
2305 0, 0, &rt5650_if1_adc_in_mux),
2306
2307 SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0,
2308 &rt5650_if1_dac0_tdm_sel_mux),
2309 SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0,
2310 &rt5650_if1_dac1_tdm_sel_mux),
2311 SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0,
2312 &rt5650_if1_dac2_tdm_sel_mux),
2313 SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0,
2314 &rt5650_if1_dac3_tdm_sel_mux),
2315 };
2316
2317 static const struct snd_soc_dapm_route rt5645_dapm_routes[] = {
2318 { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc },
2319 { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc },
2320 { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc },
2321 { "dac mono left filter", NULL, "DAC MONO L ASRC", is_using_asrc },
2322 { "dac mono right filter", NULL, "DAC MONO R ASRC", is_using_asrc },
2323 { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc },
2324
2325 { "I2S1", NULL, "I2S1 ASRC" },
2326 { "I2S2", NULL, "I2S2 ASRC" },
2327
2328 { "IN1P", NULL, "LDO2" },
2329 { "IN2P", NULL, "LDO2" },
2330
2331 { "DMIC1", NULL, "DMIC L1" },
2332 { "DMIC1", NULL, "DMIC R1" },
2333 { "DMIC2", NULL, "DMIC L2" },
2334 { "DMIC2", NULL, "DMIC R2" },
2335
2336 { "BST1", NULL, "IN1P" },
2337 { "BST1", NULL, "IN1N" },
2338 { "BST1", NULL, "JD Power" },
2339 { "BST1", NULL, "Mic Det Power" },
2340 { "BST2", NULL, "IN2P" },
2341 { "BST2", NULL, "IN2N" },
2342
2343 { "INL VOL", NULL, "IN2P" },
2344 { "INR VOL", NULL, "IN2N" },
2345
2346 { "RECMIXL", "HPOL Switch", "HPOL" },
2347 { "RECMIXL", "INL Switch", "INL VOL" },
2348 { "RECMIXL", "BST2 Switch", "BST2" },
2349 { "RECMIXL", "BST1 Switch", "BST1" },
2350 { "RECMIXL", "OUT MIXL Switch", "OUT MIXL" },
2351
2352 { "RECMIXR", "HPOR Switch", "HPOR" },
2353 { "RECMIXR", "INR Switch", "INR VOL" },
2354 { "RECMIXR", "BST2 Switch", "BST2" },
2355 { "RECMIXR", "BST1 Switch", "BST1" },
2356 { "RECMIXR", "OUT MIXR Switch", "OUT MIXR" },
2357
2358 { "ADC L", NULL, "RECMIXL" },
2359 { "ADC L", NULL, "ADC L power" },
2360 { "ADC R", NULL, "RECMIXR" },
2361 { "ADC R", NULL, "ADC R power" },
2362
2363 {"DMIC L1", NULL, "DMIC CLK"},
2364 {"DMIC L1", NULL, "DMIC1 Power"},
2365 {"DMIC R1", NULL, "DMIC CLK"},
2366 {"DMIC R1", NULL, "DMIC1 Power"},
2367 {"DMIC L2", NULL, "DMIC CLK"},
2368 {"DMIC L2", NULL, "DMIC2 Power"},
2369 {"DMIC R2", NULL, "DMIC CLK"},
2370 {"DMIC R2", NULL, "DMIC2 Power"},
2371
2372 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
2373 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
2374 { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC" },
2375
2376 { "Mono DMIC L Mux", "DMIC1", "DMIC L1" },
2377 { "Mono DMIC L Mux", "DMIC2", "DMIC L2" },
2378 { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC" },
2379
2380 { "Mono DMIC R Mux", "DMIC1", "DMIC R1" },
2381 { "Mono DMIC R Mux", "DMIC2", "DMIC R2" },
2382 { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC" },
2383
2384 { "Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC Mux" },
2385 { "Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL" },
2386 { "Stereo1 ADC L1 Mux", "ADC", "ADC L" },
2387 { "Stereo1 ADC L1 Mux", "DAC MIX", "DAC MIXL" },
2388
2389 { "Stereo1 ADC R1 Mux", "ADC", "ADC R" },
2390 { "Stereo1 ADC R1 Mux", "DAC MIX", "DAC MIXR" },
2391 { "Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC Mux" },
2392 { "Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR" },
2393
2394 { "Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux" },
2395 { "Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
2396 { "Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
2397 { "Mono ADC L1 Mux", "ADC", "ADC L" },
2398
2399 { "Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
2400 { "Mono ADC R1 Mux", "ADC", "ADC R" },
2401 { "Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux" },
2402 { "Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
2403
2404 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux" },
2405 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux" },
2406 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux" },
2407 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux" },
2408
2409 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
2410 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
2411 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
2412
2413 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
2414 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
2415 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
2416
2417 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux" },
2418 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux" },
2419 { "Mono ADC MIXL", NULL, "adc mono left filter" },
2420 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
2421
2422 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux" },
2423 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux" },
2424 { "Mono ADC MIXR", NULL, "adc mono right filter" },
2425 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
2426
2427 { "VAD ADC Mux", "Sto1 ADC L", "Stereo1 ADC MIXL" },
2428 { "VAD ADC Mux", "Mono ADC L", "Mono ADC MIXL" },
2429 { "VAD ADC Mux", "Mono ADC R", "Mono ADC MIXR" },
2430
2431 { "IF_ADC1", NULL, "Stereo1 ADC MIXL" },
2432 { "IF_ADC1", NULL, "Stereo1 ADC MIXR" },
2433 { "IF_ADC2", NULL, "Mono ADC MIXL" },
2434 { "IF_ADC2", NULL, "Mono ADC MIXR" },
2435 { "VAD_ADC", NULL, "VAD ADC Mux" },
2436
2437 { "IF2 ADC Mux", "IF_ADC1", "IF_ADC1" },
2438 { "IF2 ADC Mux", "IF_ADC2", "IF_ADC2" },
2439 { "IF2 ADC Mux", "VAD_ADC", "VAD_ADC" },
2440
2441 { "IF1 ADC", NULL, "I2S1" },
2442 { "IF2 ADC", NULL, "I2S2" },
2443 { "IF2 ADC", NULL, "IF2 ADC Mux" },
2444
2445 { "AIF2TX", NULL, "IF2 ADC" },
2446
2447 { "IF1 DAC0", NULL, "AIF1RX" },
2448 { "IF1 DAC1", NULL, "AIF1RX" },
2449 { "IF1 DAC2", NULL, "AIF1RX" },
2450 { "IF1 DAC3", NULL, "AIF1RX" },
2451 { "IF2 DAC", NULL, "AIF2RX" },
2452
2453 { "IF1 DAC0", NULL, "I2S1" },
2454 { "IF1 DAC1", NULL, "I2S1" },
2455 { "IF1 DAC2", NULL, "I2S1" },
2456 { "IF1 DAC3", NULL, "I2S1" },
2457 { "IF2 DAC", NULL, "I2S2" },
2458
2459 { "IF2 DAC L", NULL, "IF2 DAC" },
2460 { "IF2 DAC R", NULL, "IF2 DAC" },
2461
2462 { "DAC1 L Mux", "IF2 DAC", "IF2 DAC L" },
2463 { "DAC1 R Mux", "IF2 DAC", "IF2 DAC R" },
2464
2465 { "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL" },
2466 { "DAC1 MIXL", "DAC1 Switch", "DAC1 L Mux" },
2467 { "DAC1 MIXL", NULL, "dac stereo1 filter" },
2468 { "DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR" },
2469 { "DAC1 MIXR", "DAC1 Switch", "DAC1 R Mux" },
2470 { "DAC1 MIXR", NULL, "dac stereo1 filter" },
2471
2472 { "DAC L2 Mux", "IF2 DAC", "IF2 DAC L" },
2473 { "DAC L2 Mux", "Mono ADC", "Mono ADC MIXL" },
2474 { "DAC L2 Mux", "VAD_ADC", "VAD_ADC" },
2475 { "DAC L2 Volume", NULL, "DAC L2 Mux" },
2476 { "DAC L2 Volume", NULL, "dac mono left filter" },
2477
2478 { "DAC R2 Mux", "IF2 DAC", "IF2 DAC R" },
2479 { "DAC R2 Mux", "Mono ADC", "Mono ADC MIXR" },
2480 { "DAC R2 Mux", "Haptic", "Haptic Generator" },
2481 { "DAC R2 Volume", NULL, "DAC R2 Mux" },
2482 { "DAC R2 Volume", NULL, "dac mono right filter" },
2483
2484 { "Stereo DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
2485 { "Stereo DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" },
2486 { "Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2487 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
2488 { "Stereo DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
2489 { "Stereo DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" },
2490 { "Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2491 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
2492
2493 { "Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
2494 { "Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2495 { "Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
2496 { "Mono DAC MIXL", NULL, "dac mono left filter" },
2497 { "Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
2498 { "Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2499 { "Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
2500 { "Mono DAC MIXR", NULL, "dac mono right filter" },
2501
2502 { "DAC MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
2503 { "DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2504 { "DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
2505 { "DAC MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
2506 { "DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2507 { "DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
2508
2509 { "DAC L1", NULL, "PLL1", is_sys_clk_from_pll },
2510 { "DAC R1", NULL, "PLL1", is_sys_clk_from_pll },
2511 { "DAC L2", NULL, "PLL1", is_sys_clk_from_pll },
2512 { "DAC R2", NULL, "PLL1", is_sys_clk_from_pll },
2513
2514 { "SPK MIXL", "BST1 Switch", "BST1" },
2515 { "SPK MIXL", "INL Switch", "INL VOL" },
2516 { "SPK MIXL", "DAC L1 Switch", "DAC L1" },
2517 { "SPK MIXL", "DAC L2 Switch", "DAC L2" },
2518 { "SPK MIXR", "BST2 Switch", "BST2" },
2519 { "SPK MIXR", "INR Switch", "INR VOL" },
2520 { "SPK MIXR", "DAC R1 Switch", "DAC R1" },
2521 { "SPK MIXR", "DAC R2 Switch", "DAC R2" },
2522
2523 { "OUT MIXL", "BST1 Switch", "BST1" },
2524 { "OUT MIXL", "INL Switch", "INL VOL" },
2525 { "OUT MIXL", "DAC L2 Switch", "DAC L2" },
2526 { "OUT MIXL", "DAC L1 Switch", "DAC L1" },
2527
2528 { "OUT MIXR", "BST2 Switch", "BST2" },
2529 { "OUT MIXR", "INR Switch", "INR VOL" },
2530 { "OUT MIXR", "DAC R2 Switch", "DAC R2" },
2531 { "OUT MIXR", "DAC R1 Switch", "DAC R1" },
2532
2533 { "HPOVOL MIXL", "DAC1 Switch", "DAC L1" },
2534 { "HPOVOL MIXL", "DAC2 Switch", "DAC L2" },
2535 { "HPOVOL MIXL", "INL Switch", "INL VOL" },
2536 { "HPOVOL MIXL", "BST1 Switch", "BST1" },
2537 { "HPOVOL MIXL", NULL, "HPOVOL MIXL Power" },
2538 { "HPOVOL MIXR", "DAC1 Switch", "DAC R1" },
2539 { "HPOVOL MIXR", "DAC2 Switch", "DAC R2" },
2540 { "HPOVOL MIXR", "INR Switch", "INR VOL" },
2541 { "HPOVOL MIXR", "BST2 Switch", "BST2" },
2542 { "HPOVOL MIXR", NULL, "HPOVOL MIXR Power" },
2543
2544 { "DAC 2", NULL, "DAC L2" },
2545 { "DAC 2", NULL, "DAC R2" },
2546 { "DAC 1", NULL, "DAC L1" },
2547 { "DAC 1", NULL, "DAC R1" },
2548 { "HPOVOL L", "Switch", "HPOVOL MIXL" },
2549 { "HPOVOL R", "Switch", "HPOVOL MIXR" },
2550 { "HPOVOL", NULL, "HPOVOL L" },
2551 { "HPOVOL", NULL, "HPOVOL R" },
2552 { "HPO MIX", "DAC1 Switch", "DAC 1" },
2553 { "HPO MIX", "HPVOL Switch", "HPOVOL" },
2554
2555 { "SPKVOL L", "Switch", "SPK MIXL" },
2556 { "SPKVOL R", "Switch", "SPK MIXR" },
2557
2558 { "SPOL MIX", "DAC L1 Switch", "DAC L1" },
2559 { "SPOL MIX", "SPKVOL L Switch", "SPKVOL L" },
2560 { "SPOR MIX", "DAC R1 Switch", "DAC R1" },
2561 { "SPOR MIX", "SPKVOL R Switch", "SPKVOL R" },
2562
2563 { "LOUT MIX", "DAC L1 Switch", "DAC L1" },
2564 { "LOUT MIX", "DAC R1 Switch", "DAC R1" },
2565 { "LOUT MIX", "OUTMIX L Switch", "OUT MIXL" },
2566 { "LOUT MIX", "OUTMIX R Switch", "OUT MIXR" },
2567
2568 { "PDM1 L Mux", "Stereo DAC", "Stereo DAC MIXL" },
2569 { "PDM1 L Mux", "Mono DAC", "Mono DAC MIXL" },
2570 { "PDM1 L Mux", NULL, "PDM1 Power" },
2571 { "PDM1 R Mux", "Stereo DAC", "Stereo DAC MIXR" },
2572 { "PDM1 R Mux", "Mono DAC", "Mono DAC MIXR" },
2573 { "PDM1 R Mux", NULL, "PDM1 Power" },
2574
2575 { "HP amp", NULL, "HPO MIX" },
2576 { "HP amp", NULL, "JD Power" },
2577 { "HP amp", NULL, "Mic Det Power" },
2578 { "HP amp", NULL, "LDO2" },
2579 { "HPOL", NULL, "HP amp" },
2580 { "HPOR", NULL, "HP amp" },
2581
2582 { "LOUT amp", NULL, "LOUT MIX" },
2583 { "LOUTL", NULL, "LOUT amp" },
2584 { "LOUTR", NULL, "LOUT amp" },
2585
2586 { "PDM1 L", "Switch", "PDM1 L Mux" },
2587 { "PDM1 R", "Switch", "PDM1 R Mux" },
2588
2589 { "PDM1L", NULL, "PDM1 L" },
2590 { "PDM1R", NULL, "PDM1 R" },
2591
2592 { "SPK amp", NULL, "SPOL MIX" },
2593 { "SPK amp", NULL, "SPOR MIX" },
2594 { "SPOL", NULL, "SPK amp" },
2595 { "SPOR", NULL, "SPK amp" },
2596 };
2597
2598 static const struct snd_soc_dapm_route rt5650_specific_dapm_routes[] = {
2599 { "A DAC1 L Mux", "DAC1", "DAC1 MIXL"},
2600 { "A DAC1 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"},
2601 { "A DAC1 R Mux", "DAC1", "DAC1 MIXR"},
2602 { "A DAC1 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"},
2603
2604 { "A DAC2 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"},
2605 { "A DAC2 L Mux", "Mono DAC Mixer", "Mono DAC MIXL"},
2606 { "A DAC2 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"},
2607 { "A DAC2 R Mux", "Mono DAC Mixer", "Mono DAC MIXR"},
2608
2609 { "DAC L1", NULL, "A DAC1 L Mux" },
2610 { "DAC R1", NULL, "A DAC1 R Mux" },
2611 { "DAC L2", NULL, "A DAC2 L Mux" },
2612 { "DAC R2", NULL, "A DAC2 R Mux" },
2613
2614 { "RT5650 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" },
2615 { "RT5650 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" },
2616 { "RT5650 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" },
2617 { "RT5650 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" },
2618
2619 { "RT5650 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" },
2620 { "RT5650 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" },
2621 { "RT5650 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" },
2622 { "RT5650 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" },
2623
2624 { "RT5650 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" },
2625 { "RT5650 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" },
2626 { "RT5650 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" },
2627 { "RT5650 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" },
2628
2629 { "IF1 ADC", NULL, "RT5650 IF1 ADC1 Swap Mux" },
2630 { "IF1 ADC", NULL, "RT5650 IF1 ADC2 Swap Mux" },
2631 { "IF1 ADC", NULL, "RT5650 IF1 ADC3 Swap Mux" },
2632
2633 { "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/DAC_REF/Null", "IF1 ADC" },
2634 { "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/Null/DAC_REF", "IF1 ADC" },
2635 { "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/IF_ADC2/Null", "IF1 ADC" },
2636 { "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/Null/IF_ADC2", "IF1 ADC" },
2637 { "RT5650 IF1 ADC Mux", "IF_ADC1/Null/DAC_REF/IF_ADC2", "IF1 ADC" },
2638 { "RT5650 IF1 ADC Mux", "IF_ADC1/Null/IF_ADC2/DAC_REF", "IF1 ADC" },
2639
2640 { "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/DAC_REF/Null", "IF1 ADC" },
2641 { "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/Null/DAC_REF", "IF1 ADC" },
2642 { "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/IF_ADC1/Null", "IF1 ADC" },
2643 { "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/Null/IF_ADC1", "IF1 ADC" },
2644 { "RT5650 IF1 ADC Mux", "IF_ADC2/Null/DAC_REF/IF_ADC1", "IF1 ADC" },
2645 { "RT5650 IF1 ADC Mux", "IF_ADC2/Null/IF_ADC1/DAC_REF", "IF1 ADC" },
2646
2647 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/IF_ADC2/Null", "IF1 ADC" },
2648 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/Null/IF_ADC2", "IF1 ADC" },
2649 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/IF_ADC1/Null", "IF1 ADC" },
2650 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/Null/IF_ADC1", "IF1 ADC" },
2651 { "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC1/IF_ADC2", "IF1 ADC" },
2652 { "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC2/IF_ADC1", "IF1 ADC" },
2653
2654 { "RT5650 IF1 ADC Mux", "Null/IF_ADC1/IF_ADC2/DAC_REF", "IF1 ADC" },
2655 { "RT5650 IF1 ADC Mux", "Null/IF_ADC1/DAC_REF/IF_ADC2", "IF1 ADC" },
2656 { "RT5650 IF1 ADC Mux", "Null/IF_ADC2/IF_ADC1/DAC_REF", "IF1 ADC" },
2657 { "RT5650 IF1 ADC Mux", "Null/IF_ADC2/DAC_REF/IF_ADC1", "IF1 ADC" },
2658 { "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC1/IF_ADC2", "IF1 ADC" },
2659 { "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC2/IF_ADC1", "IF1 ADC" },
2660 { "AIF1TX", NULL, "RT5650 IF1 ADC Mux" },
2661
2662 { "RT5650 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" },
2663 { "RT5650 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" },
2664 { "RT5650 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" },
2665 { "RT5650 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" },
2666
2667 { "RT5650 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" },
2668 { "RT5650 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" },
2669 { "RT5650 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" },
2670 { "RT5650 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" },
2671
2672 { "RT5650 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" },
2673 { "RT5650 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" },
2674 { "RT5650 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" },
2675 { "RT5650 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" },
2676
2677 { "RT5650 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" },
2678 { "RT5650 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" },
2679 { "RT5650 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" },
2680 { "RT5650 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" },
2681
2682 { "DAC1 L Mux", "IF1 DAC", "RT5650 IF1 DAC1 L Mux" },
2683 { "DAC1 R Mux", "IF1 DAC", "RT5650 IF1 DAC1 R Mux" },
2684
2685 { "DAC L2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 L Mux" },
2686 { "DAC R2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 R Mux" },
2687 };
2688
2689 static const struct snd_soc_dapm_route rt5645_specific_dapm_routes[] = {
2690 { "DAC L1", NULL, "Stereo DAC MIXL" },
2691 { "DAC R1", NULL, "Stereo DAC MIXR" },
2692 { "DAC L2", NULL, "Mono DAC MIXL" },
2693 { "DAC R2", NULL, "Mono DAC MIXR" },
2694
2695 { "RT5645 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" },
2696 { "RT5645 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" },
2697 { "RT5645 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" },
2698 { "RT5645 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" },
2699
2700 { "RT5645 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" },
2701 { "RT5645 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" },
2702 { "RT5645 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" },
2703 { "RT5645 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" },
2704
2705 { "RT5645 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" },
2706 { "RT5645 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" },
2707 { "RT5645 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" },
2708 { "RT5645 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" },
2709
2710 { "IF1 ADC", NULL, "RT5645 IF1 ADC1 Swap Mux" },
2711 { "IF1 ADC", NULL, "RT5645 IF1 ADC2 Swap Mux" },
2712 { "IF1 ADC", NULL, "RT5645 IF1 ADC3 Swap Mux" },
2713
2714 { "RT5645 IF1 ADC Mux", "IF_ADC1/IF_ADC2/VAD_ADC", "IF1 ADC" },
2715 { "RT5645 IF1 ADC Mux", "IF_ADC2/IF_ADC1/VAD_ADC", "IF1 ADC" },
2716 { "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC1/IF_ADC2", "IF1 ADC" },
2717 { "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC2/IF_ADC1", "IF1 ADC" },
2718 { "AIF1TX", NULL, "RT5645 IF1 ADC Mux" },
2719
2720 { "RT5645 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" },
2721 { "RT5645 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" },
2722 { "RT5645 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" },
2723 { "RT5645 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" },
2724
2725 { "RT5645 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" },
2726 { "RT5645 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" },
2727 { "RT5645 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" },
2728 { "RT5645 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" },
2729
2730 { "RT5645 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" },
2731 { "RT5645 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" },
2732 { "RT5645 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" },
2733 { "RT5645 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" },
2734
2735 { "RT5645 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" },
2736 { "RT5645 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" },
2737 { "RT5645 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" },
2738 { "RT5645 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" },
2739
2740 { "DAC1 L Mux", "IF1 DAC", "RT5645 IF1 DAC1 L Mux" },
2741 { "DAC1 R Mux", "IF1 DAC", "RT5645 IF1 DAC1 R Mux" },
2742
2743 { "DAC L2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 L Mux" },
2744 { "DAC R2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 R Mux" },
2745 };
2746
2747 static const struct snd_soc_dapm_route rt5645_old_dapm_routes[] = {
2748 { "SPOL MIX", "DAC R1 Switch", "DAC R1" },
2749 { "SPOL MIX", "SPKVOL R Switch", "SPKVOL R" },
2750 };
2751
rt5645_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)2752 static int rt5645_hw_params(struct snd_pcm_substream *substream,
2753 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2754 {
2755 struct snd_soc_component *component = dai->component;
2756 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
2757 unsigned int val_len = 0, val_clk, mask_clk, dl_sft;
2758 int pre_div, bclk_ms, frame_size;
2759
2760 rt5645->lrck[dai->id] = params_rate(params);
2761 pre_div = rl6231_get_clk_info(rt5645->sysclk, rt5645->lrck[dai->id]);
2762 if (pre_div < 0) {
2763 dev_err(component->dev, "Unsupported clock setting\n");
2764 return -EINVAL;
2765 }
2766 frame_size = snd_soc_params_to_frame_size(params);
2767 if (frame_size < 0) {
2768 dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);
2769 return -EINVAL;
2770 }
2771
2772 switch (rt5645->codec_type) {
2773 case CODEC_TYPE_RT5650:
2774 dl_sft = 4;
2775 break;
2776 default:
2777 dl_sft = 2;
2778 break;
2779 }
2780
2781 bclk_ms = frame_size > 32;
2782 rt5645->bclk[dai->id] = rt5645->lrck[dai->id] * (32 << bclk_ms);
2783
2784 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
2785 rt5645->bclk[dai->id], rt5645->lrck[dai->id]);
2786 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
2787 bclk_ms, pre_div, dai->id);
2788
2789 switch (params_width(params)) {
2790 case 16:
2791 break;
2792 case 20:
2793 val_len = 0x1;
2794 break;
2795 case 24:
2796 val_len = 0x2;
2797 break;
2798 case 8:
2799 val_len = 0x3;
2800 break;
2801 default:
2802 return -EINVAL;
2803 }
2804
2805 switch (dai->id) {
2806 case RT5645_AIF1:
2807 mask_clk = RT5645_I2S_PD1_MASK;
2808 val_clk = pre_div << RT5645_I2S_PD1_SFT;
2809 snd_soc_component_update_bits(component, RT5645_I2S1_SDP,
2810 (0x3 << dl_sft), (val_len << dl_sft));
2811 snd_soc_component_update_bits(component, RT5645_ADDA_CLK1, mask_clk, val_clk);
2812 break;
2813 case RT5645_AIF2:
2814 mask_clk = RT5645_I2S_BCLK_MS2_MASK | RT5645_I2S_PD2_MASK;
2815 val_clk = bclk_ms << RT5645_I2S_BCLK_MS2_SFT |
2816 pre_div << RT5645_I2S_PD2_SFT;
2817 snd_soc_component_update_bits(component, RT5645_I2S2_SDP,
2818 (0x3 << dl_sft), (val_len << dl_sft));
2819 snd_soc_component_update_bits(component, RT5645_ADDA_CLK1, mask_clk, val_clk);
2820 break;
2821 default:
2822 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2823 return -EINVAL;
2824 }
2825
2826 return 0;
2827 }
2828
rt5645_set_dai_fmt(struct snd_soc_dai * dai,unsigned int fmt)2829 static int rt5645_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2830 {
2831 struct snd_soc_component *component = dai->component;
2832 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
2833 unsigned int reg_val = 0, pol_sft;
2834
2835 switch (rt5645->codec_type) {
2836 case CODEC_TYPE_RT5650:
2837 pol_sft = 8;
2838 break;
2839 default:
2840 pol_sft = 7;
2841 break;
2842 }
2843
2844 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2845 case SND_SOC_DAIFMT_CBP_CFP:
2846 rt5645->master[dai->id] = 1;
2847 break;
2848 case SND_SOC_DAIFMT_CBC_CFC:
2849 reg_val |= RT5645_I2S_MS_S;
2850 rt5645->master[dai->id] = 0;
2851 break;
2852 default:
2853 return -EINVAL;
2854 }
2855
2856 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2857 case SND_SOC_DAIFMT_NB_NF:
2858 break;
2859 case SND_SOC_DAIFMT_IB_NF:
2860 reg_val |= (1 << pol_sft);
2861 break;
2862 default:
2863 return -EINVAL;
2864 }
2865
2866 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2867 case SND_SOC_DAIFMT_I2S:
2868 break;
2869 case SND_SOC_DAIFMT_LEFT_J:
2870 reg_val |= RT5645_I2S_DF_LEFT;
2871 break;
2872 case SND_SOC_DAIFMT_DSP_A:
2873 reg_val |= RT5645_I2S_DF_PCM_A;
2874 break;
2875 case SND_SOC_DAIFMT_DSP_B:
2876 reg_val |= RT5645_I2S_DF_PCM_B;
2877 break;
2878 default:
2879 return -EINVAL;
2880 }
2881 switch (dai->id) {
2882 case RT5645_AIF1:
2883 snd_soc_component_update_bits(component, RT5645_I2S1_SDP,
2884 RT5645_I2S_MS_MASK | (1 << pol_sft) |
2885 RT5645_I2S_DF_MASK, reg_val);
2886 break;
2887 case RT5645_AIF2:
2888 snd_soc_component_update_bits(component, RT5645_I2S2_SDP,
2889 RT5645_I2S_MS_MASK | (1 << pol_sft) |
2890 RT5645_I2S_DF_MASK, reg_val);
2891 break;
2892 default:
2893 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2894 return -EINVAL;
2895 }
2896 return 0;
2897 }
2898
rt5645_set_dai_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)2899 static int rt5645_set_dai_sysclk(struct snd_soc_dai *dai,
2900 int clk_id, unsigned int freq, int dir)
2901 {
2902 struct snd_soc_component *component = dai->component;
2903 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
2904 unsigned int reg_val = 0;
2905
2906 if (freq == rt5645->sysclk && clk_id == rt5645->sysclk_src)
2907 return 0;
2908
2909 switch (clk_id) {
2910 case RT5645_SCLK_S_MCLK:
2911 reg_val |= RT5645_SCLK_SRC_MCLK;
2912 break;
2913 case RT5645_SCLK_S_PLL1:
2914 reg_val |= RT5645_SCLK_SRC_PLL1;
2915 break;
2916 case RT5645_SCLK_S_RCCLK:
2917 reg_val |= RT5645_SCLK_SRC_RCCLK;
2918 break;
2919 default:
2920 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
2921 return -EINVAL;
2922 }
2923 snd_soc_component_update_bits(component, RT5645_GLB_CLK,
2924 RT5645_SCLK_SRC_MASK, reg_val);
2925 rt5645->sysclk = freq;
2926 rt5645->sysclk_src = clk_id;
2927
2928 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
2929
2930 return 0;
2931 }
2932
rt5645_set_dai_pll(struct snd_soc_dai * dai,int pll_id,int source,unsigned int freq_in,unsigned int freq_out)2933 static int rt5645_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
2934 unsigned int freq_in, unsigned int freq_out)
2935 {
2936 struct snd_soc_component *component = dai->component;
2937 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
2938 struct rl6231_pll_code pll_code;
2939 int ret;
2940
2941 if (source == rt5645->pll_src && freq_in == rt5645->pll_in &&
2942 freq_out == rt5645->pll_out)
2943 return 0;
2944
2945 if (!freq_in || !freq_out) {
2946 dev_dbg(component->dev, "PLL disabled\n");
2947
2948 rt5645->pll_in = 0;
2949 rt5645->pll_out = 0;
2950 snd_soc_component_update_bits(component, RT5645_GLB_CLK,
2951 RT5645_SCLK_SRC_MASK, RT5645_SCLK_SRC_MCLK);
2952 return 0;
2953 }
2954
2955 switch (source) {
2956 case RT5645_PLL1_S_MCLK:
2957 snd_soc_component_update_bits(component, RT5645_GLB_CLK,
2958 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_MCLK);
2959 break;
2960 case RT5645_PLL1_S_BCLK1:
2961 case RT5645_PLL1_S_BCLK2:
2962 switch (dai->id) {
2963 case RT5645_AIF1:
2964 snd_soc_component_update_bits(component, RT5645_GLB_CLK,
2965 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK1);
2966 break;
2967 case RT5645_AIF2:
2968 snd_soc_component_update_bits(component, RT5645_GLB_CLK,
2969 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK2);
2970 break;
2971 default:
2972 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2973 return -EINVAL;
2974 }
2975 break;
2976 default:
2977 dev_err(component->dev, "Unknown PLL source %d\n", source);
2978 return -EINVAL;
2979 }
2980
2981 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2982 if (ret < 0) {
2983 dev_err(component->dev, "Unsupported input clock %d\n", freq_in);
2984 return ret;
2985 }
2986
2987 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
2988 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2989 pll_code.n_code, pll_code.k_code);
2990
2991 snd_soc_component_write(component, RT5645_PLL_CTRL1,
2992 pll_code.n_code << RT5645_PLL_N_SFT | pll_code.k_code);
2993 snd_soc_component_write(component, RT5645_PLL_CTRL2,
2994 ((pll_code.m_bp ? 0 : pll_code.m_code) << RT5645_PLL_M_SFT) |
2995 (pll_code.m_bp << RT5645_PLL_M_BP_SFT));
2996
2997 rt5645->pll_in = freq_in;
2998 rt5645->pll_out = freq_out;
2999 rt5645->pll_src = source;
3000
3001 return 0;
3002 }
3003
rt5645_set_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)3004 static int rt5645_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
3005 unsigned int rx_mask, int slots, int slot_width)
3006 {
3007 struct snd_soc_component *component = dai->component;
3008 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
3009 unsigned int i_slot_sft, o_slot_sft, i_width_sht, o_width_sht, en_sft;
3010 unsigned int mask, val = 0;
3011
3012 switch (rt5645->codec_type) {
3013 case CODEC_TYPE_RT5650:
3014 en_sft = 15;
3015 i_slot_sft = 10;
3016 o_slot_sft = 8;
3017 i_width_sht = 6;
3018 o_width_sht = 4;
3019 mask = 0x8ff0;
3020 break;
3021 default:
3022 en_sft = 14;
3023 i_slot_sft = o_slot_sft = 12;
3024 i_width_sht = o_width_sht = 10;
3025 mask = 0x7c00;
3026 break;
3027 }
3028 if (rx_mask || tx_mask) {
3029 val |= (1 << en_sft);
3030 if (rt5645->codec_type == CODEC_TYPE_RT5645)
3031 snd_soc_component_update_bits(component, RT5645_BASS_BACK,
3032 RT5645_G_BB_BST_MASK, RT5645_G_BB_BST_25DB);
3033 }
3034
3035 switch (slots) {
3036 case 4:
3037 val |= (1 << i_slot_sft) | (1 << o_slot_sft);
3038 break;
3039 case 6:
3040 val |= (2 << i_slot_sft) | (2 << o_slot_sft);
3041 break;
3042 case 8:
3043 val |= (3 << i_slot_sft) | (3 << o_slot_sft);
3044 break;
3045 case 2:
3046 default:
3047 break;
3048 }
3049
3050 switch (slot_width) {
3051 case 20:
3052 val |= (1 << i_width_sht) | (1 << o_width_sht);
3053 break;
3054 case 24:
3055 val |= (2 << i_width_sht) | (2 << o_width_sht);
3056 break;
3057 case 32:
3058 val |= (3 << i_width_sht) | (3 << o_width_sht);
3059 break;
3060 case 16:
3061 default:
3062 break;
3063 }
3064
3065 snd_soc_component_update_bits(component, RT5645_TDM_CTRL_1, mask, val);
3066
3067 return 0;
3068 }
3069
rt5645_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)3070 static int rt5645_set_bias_level(struct snd_soc_component *component,
3071 enum snd_soc_bias_level level)
3072 {
3073 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
3074
3075 switch (level) {
3076 case SND_SOC_BIAS_PREPARE:
3077 if (SND_SOC_BIAS_STANDBY == snd_soc_component_get_bias_level(component)) {
3078 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
3079 RT5645_PWR_VREF1 | RT5645_PWR_MB |
3080 RT5645_PWR_BG | RT5645_PWR_VREF2,
3081 RT5645_PWR_VREF1 | RT5645_PWR_MB |
3082 RT5645_PWR_BG | RT5645_PWR_VREF2);
3083 mdelay(10);
3084 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
3085 RT5645_PWR_FV1 | RT5645_PWR_FV2,
3086 RT5645_PWR_FV1 | RT5645_PWR_FV2);
3087 snd_soc_component_update_bits(component, RT5645_GEN_CTRL1,
3088 RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL);
3089 }
3090 break;
3091
3092 case SND_SOC_BIAS_STANDBY:
3093 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
3094 RT5645_PWR_VREF1 | RT5645_PWR_MB |
3095 RT5645_PWR_BG | RT5645_PWR_VREF2,
3096 RT5645_PWR_VREF1 | RT5645_PWR_MB |
3097 RT5645_PWR_BG | RT5645_PWR_VREF2);
3098 mdelay(10);
3099 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
3100 RT5645_PWR_FV1 | RT5645_PWR_FV2,
3101 RT5645_PWR_FV1 | RT5645_PWR_FV2);
3102 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
3103 snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1140);
3104 msleep(40);
3105 if (rt5645->en_button_func)
3106 queue_delayed_work(system_power_efficient_wq,
3107 &rt5645->jack_detect_work,
3108 msecs_to_jiffies(0));
3109 }
3110 break;
3111
3112 case SND_SOC_BIAS_OFF:
3113 snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1100);
3114 if (!rt5645->en_button_func)
3115 snd_soc_component_update_bits(component, RT5645_GEN_CTRL1,
3116 RT5645_DIG_GATE_CTRL, 0);
3117 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
3118 RT5645_PWR_VREF1 | RT5645_PWR_MB |
3119 RT5645_PWR_BG | RT5645_PWR_VREF2 |
3120 RT5645_PWR_FV1 | RT5645_PWR_FV2, 0x0);
3121 break;
3122
3123 default:
3124 break;
3125 }
3126
3127 return 0;
3128 }
3129
rt5645_enable_push_button_irq(struct snd_soc_component * component,bool enable)3130 static void rt5645_enable_push_button_irq(struct snd_soc_component *component,
3131 bool enable)
3132 {
3133 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3134 int ret;
3135
3136 if (enable) {
3137 snd_soc_dapm_force_enable_pin(dapm, "ADC L power");
3138 snd_soc_dapm_force_enable_pin(dapm, "ADC R power");
3139 snd_soc_dapm_sync(dapm);
3140
3141 snd_soc_component_update_bits(component, RT5650_4BTN_IL_CMD2,
3142 RT5645_EN_4BTN_IL_MASK | RT5645_RST_4BTN_IL_MASK,
3143 RT5645_EN_4BTN_IL_EN | RT5645_RST_4BTN_IL_RST);
3144 usleep_range(10000, 15000);
3145 snd_soc_component_update_bits(component, RT5650_4BTN_IL_CMD2,
3146 RT5645_EN_4BTN_IL_MASK | RT5645_RST_4BTN_IL_MASK,
3147 RT5645_EN_4BTN_IL_EN | RT5645_RST_4BTN_IL_NORM);
3148 msleep(50);
3149 ret = snd_soc_component_read(component, RT5645_INT_IRQ_ST);
3150 pr_debug("%s read %x = %x\n", __func__, RT5645_INT_IRQ_ST,
3151 snd_soc_component_read(component, RT5645_INT_IRQ_ST));
3152 snd_soc_component_write(component, RT5645_INT_IRQ_ST, ret);
3153 ret = snd_soc_component_read(component, RT5650_4BTN_IL_CMD1);
3154 pr_debug("%s read %x = %x\n", __func__, RT5650_4BTN_IL_CMD1,
3155 snd_soc_component_read(component, RT5650_4BTN_IL_CMD1));
3156 snd_soc_component_write(component, RT5650_4BTN_IL_CMD1, ret);
3157 snd_soc_component_update_bits(component, RT5650_4BTN_IL_CMD1, 0x3, 0x3);
3158 snd_soc_component_update_bits(component,
3159 RT5645_INT_IRQ_ST, 0x8, 0x8);
3160 } else {
3161 snd_soc_component_update_bits(component, RT5650_4BTN_IL_CMD2, 0x8000, 0x0);
3162 snd_soc_component_update_bits(component, RT5645_INT_IRQ_ST, 0x8, 0x0);
3163
3164 snd_soc_dapm_disable_pin(dapm, "ADC L power");
3165 snd_soc_dapm_disable_pin(dapm, "ADC R power");
3166 snd_soc_dapm_sync(dapm);
3167 }
3168 }
3169
rt5645_jack_detect(struct snd_soc_component * component,int jack_insert)3170 static int rt5645_jack_detect(struct snd_soc_component *component, int jack_insert)
3171 {
3172 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3173 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
3174 unsigned int val;
3175
3176 if (jack_insert) {
3177 regmap_write(rt5645->regmap, RT5645_CHARGE_PUMP, 0x0206);
3178
3179 /* for jack type detect */
3180 snd_soc_dapm_force_enable_pin(dapm, "LDO2");
3181 snd_soc_dapm_force_enable_pin(dapm, "Mic Det Power");
3182 snd_soc_dapm_sync(dapm);
3183 if (!snd_soc_card_is_instantiated(dapm->card)) {
3184 /* Power up necessary bits for JD if dapm is
3185 not ready yet */
3186 regmap_update_bits(rt5645->regmap, RT5645_PWR_ANLG1,
3187 RT5645_PWR_MB | RT5645_PWR_VREF2,
3188 RT5645_PWR_MB | RT5645_PWR_VREF2);
3189 regmap_update_bits(rt5645->regmap, RT5645_PWR_MIXER,
3190 RT5645_PWR_LDO2, RT5645_PWR_LDO2);
3191 regmap_update_bits(rt5645->regmap, RT5645_PWR_VOL,
3192 RT5645_PWR_MIC_DET, RT5645_PWR_MIC_DET);
3193 }
3194
3195 regmap_write(rt5645->regmap, RT5645_JD_CTRL3, 0x00f0);
3196 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2,
3197 RT5645_CBJ_MN_JD, RT5645_CBJ_MN_JD);
3198 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1,
3199 RT5645_CBJ_BST1_EN, RT5645_CBJ_BST1_EN);
3200 msleep(100);
3201 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2,
3202 RT5645_CBJ_MN_JD, 0);
3203
3204 if (rt5645->gpiod_cbj_sleeve)
3205 gpiod_set_value(rt5645->gpiod_cbj_sleeve, 1);
3206
3207 msleep(600);
3208 regmap_read(rt5645->regmap, RT5645_IN1_CTRL3, &val);
3209 val &= 0x7;
3210 dev_dbg(component->dev, "val = %d\n", val);
3211
3212 if ((val == 1 || val == 2) && !rt5645->pdata.no_headset_mic) {
3213 rt5645->jack_type = SND_JACK_HEADSET;
3214 if (rt5645->en_button_func) {
3215 rt5645_enable_push_button_irq(component, true);
3216 }
3217 } else {
3218 if (rt5645->en_button_func)
3219 rt5645_enable_push_button_irq(component, false);
3220 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
3221 snd_soc_dapm_sync(dapm);
3222 rt5645->jack_type = SND_JACK_HEADPHONE;
3223 if (rt5645->gpiod_cbj_sleeve)
3224 gpiod_set_value(rt5645->gpiod_cbj_sleeve, 0);
3225 }
3226 if (rt5645->pdata.level_trigger_irq)
3227 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
3228 RT5645_JD_1_1_MASK, RT5645_JD_1_1_NOR);
3229
3230 regmap_write(rt5645->regmap, RT5645_CHARGE_PUMP, 0x0e06);
3231 } else { /* jack out */
3232 rt5645->jack_type = 0;
3233
3234 regmap_update_bits(rt5645->regmap, RT5645_HP_VOL,
3235 RT5645_L_MUTE | RT5645_R_MUTE,
3236 RT5645_L_MUTE | RT5645_R_MUTE);
3237 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2,
3238 RT5645_CBJ_MN_JD, RT5645_CBJ_MN_JD);
3239 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1,
3240 RT5645_CBJ_BST1_EN, 0);
3241
3242 if (rt5645->en_button_func)
3243 rt5645_enable_push_button_irq(component, false);
3244
3245 if (rt5645->pdata.jd_mode == 0)
3246 snd_soc_dapm_disable_pin(dapm, "LDO2");
3247 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
3248 snd_soc_dapm_sync(dapm);
3249 if (rt5645->pdata.level_trigger_irq)
3250 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
3251 RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV);
3252
3253 if (rt5645->gpiod_cbj_sleeve)
3254 gpiod_set_value(rt5645->gpiod_cbj_sleeve, 0);
3255 }
3256
3257 return rt5645->jack_type;
3258 }
3259
rt5645_button_detect(struct snd_soc_component * component)3260 static int rt5645_button_detect(struct snd_soc_component *component)
3261 {
3262 int btn_type, val;
3263
3264 val = snd_soc_component_read(component, RT5650_4BTN_IL_CMD1);
3265 pr_debug("val=0x%x\n", val);
3266 btn_type = val & 0xfff0;
3267 snd_soc_component_write(component, RT5650_4BTN_IL_CMD1, val);
3268
3269 return btn_type;
3270 }
3271
3272 static irqreturn_t rt5645_irq(int irq, void *data);
3273
rt5645_set_jack_detect(struct snd_soc_component * component,struct snd_soc_jack * hp_jack,struct snd_soc_jack * mic_jack,struct snd_soc_jack * btn_jack)3274 int rt5645_set_jack_detect(struct snd_soc_component *component,
3275 struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack,
3276 struct snd_soc_jack *btn_jack)
3277 {
3278 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
3279
3280 rt5645->hp_jack = hp_jack;
3281 rt5645->mic_jack = mic_jack;
3282 rt5645->btn_jack = btn_jack;
3283 if (rt5645->btn_jack && rt5645->codec_type == CODEC_TYPE_RT5650) {
3284 rt5645->en_button_func = true;
3285 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3286 RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ);
3287 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL1,
3288 RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL);
3289 regmap_update_bits(rt5645->regmap, RT5645_DEPOP_M1,
3290 RT5645_HP_CB_MASK, RT5645_HP_CB_PU);
3291 }
3292 rt5645_irq(0, rt5645);
3293
3294 return 0;
3295 }
3296 EXPORT_SYMBOL_GPL(rt5645_set_jack_detect);
3297
rt5645_component_set_jack(struct snd_soc_component * component,struct snd_soc_jack * hs_jack,void * data)3298 static int rt5645_component_set_jack(struct snd_soc_component *component,
3299 struct snd_soc_jack *hs_jack, void *data)
3300 {
3301 struct snd_soc_jack *mic_jack = NULL;
3302 struct snd_soc_jack *btn_jack = NULL;
3303 int type;
3304
3305 if (hs_jack) {
3306 type = *(int *)data;
3307
3308 if (type & SND_JACK_MICROPHONE)
3309 mic_jack = hs_jack;
3310 if (type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3311 SND_JACK_BTN_2 | SND_JACK_BTN_3))
3312 btn_jack = hs_jack;
3313 }
3314
3315 return rt5645_set_jack_detect(component, hs_jack, mic_jack, btn_jack);
3316 }
3317
rt5645_jack_detect_work(struct work_struct * work)3318 static void rt5645_jack_detect_work(struct work_struct *work)
3319 {
3320 struct rt5645_priv *rt5645 =
3321 container_of(work, struct rt5645_priv, jack_detect_work.work);
3322 int val, btn_type, gpio_state = 0, report = 0;
3323
3324 if (!rt5645->component)
3325 return;
3326
3327 mutex_lock(&rt5645->jd_mutex);
3328
3329 switch (rt5645->pdata.jd_mode) {
3330 case 0: /* Not using rt5645 JD */
3331 if (rt5645->gpiod_hp_det) {
3332 gpio_state = gpiod_get_value(rt5645->gpiod_hp_det);
3333 if (rt5645->pdata.inv_hp_pol)
3334 gpio_state ^= 1;
3335 dev_dbg(rt5645->component->dev, "gpio_state = %d\n",
3336 gpio_state);
3337 report = rt5645_jack_detect(rt5645->component, gpio_state);
3338 }
3339 snd_soc_jack_report(rt5645->hp_jack,
3340 report, SND_JACK_HEADPHONE);
3341 snd_soc_jack_report(rt5645->mic_jack,
3342 report, SND_JACK_MICROPHONE);
3343 mutex_unlock(&rt5645->jd_mutex);
3344 return;
3345 case 4:
3346 val = snd_soc_component_read(rt5645->component, RT5645_A_JD_CTRL1) & 0x0020;
3347 break;
3348 default: /* read rt5645 jd1_1 status */
3349 val = snd_soc_component_read(rt5645->component, RT5645_INT_IRQ_ST) & 0x1000;
3350 break;
3351
3352 }
3353
3354 if (!val && (rt5645->jack_type == 0)) { /* jack in */
3355 report = rt5645_jack_detect(rt5645->component, 1);
3356 } else if (!val && rt5645->jack_type == SND_JACK_HEADSET) {
3357 /* for push button and jack out */
3358 btn_type = 0;
3359 if (snd_soc_component_read(rt5645->component, RT5645_INT_IRQ_ST) & 0x4) {
3360 /* button pressed */
3361 report = SND_JACK_HEADSET;
3362 btn_type = rt5645_button_detect(rt5645->component);
3363 /* rt5650 can report three kinds of button behavior,
3364 one click, double click and hold. However,
3365 currently we will report button pressed/released
3366 event. So all the three button behaviors are
3367 treated as button pressed. */
3368 switch (btn_type) {
3369 case 0x8000:
3370 case 0x4000:
3371 case 0x2000:
3372 report |= SND_JACK_BTN_0;
3373 break;
3374 case 0x1000:
3375 case 0x0800:
3376 case 0x0400:
3377 report |= SND_JACK_BTN_1;
3378 break;
3379 case 0x0200:
3380 case 0x0100:
3381 case 0x0080:
3382 report |= SND_JACK_BTN_2;
3383 break;
3384 case 0x0040:
3385 case 0x0020:
3386 case 0x0010:
3387 report |= SND_JACK_BTN_3;
3388 break;
3389 case 0x0000: /* unpressed */
3390 break;
3391 default:
3392 dev_err(rt5645->component->dev,
3393 "Unexpected button code 0x%04x\n",
3394 btn_type);
3395 break;
3396 }
3397 }
3398 if (btn_type == 0)/* button release */
3399 report = rt5645->jack_type;
3400 else {
3401 mod_timer(&rt5645->btn_check_timer,
3402 msecs_to_jiffies(100));
3403 }
3404 } else {
3405 /* jack out */
3406 report = 0;
3407 snd_soc_component_update_bits(rt5645->component,
3408 RT5645_INT_IRQ_ST, 0x1, 0x0);
3409 rt5645_jack_detect(rt5645->component, 0);
3410 }
3411
3412 mutex_unlock(&rt5645->jd_mutex);
3413
3414 snd_soc_jack_report(rt5645->hp_jack, report, SND_JACK_HEADPHONE);
3415 snd_soc_jack_report(rt5645->mic_jack, report, SND_JACK_MICROPHONE);
3416 if (rt5645->en_button_func)
3417 snd_soc_jack_report(rt5645->btn_jack,
3418 report, SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3419 SND_JACK_BTN_2 | SND_JACK_BTN_3);
3420 }
3421
rt5645_rcclock_work(struct work_struct * work)3422 static void rt5645_rcclock_work(struct work_struct *work)
3423 {
3424 struct rt5645_priv *rt5645 =
3425 container_of(work, struct rt5645_priv, rcclock_work.work);
3426
3427 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
3428 RT5645_PWR_CLK25M_MASK, RT5645_PWR_CLK25M_PD);
3429 }
3430
rt5645_irq(int irq,void * data)3431 static irqreturn_t rt5645_irq(int irq, void *data)
3432 {
3433 struct rt5645_priv *rt5645 = data;
3434
3435 queue_delayed_work(system_power_efficient_wq,
3436 &rt5645->jack_detect_work, msecs_to_jiffies(250));
3437
3438 return IRQ_HANDLED;
3439 }
3440
rt5645_btn_check_callback(struct timer_list * t)3441 static void rt5645_btn_check_callback(struct timer_list *t)
3442 {
3443 struct rt5645_priv *rt5645 = timer_container_of(rt5645, t,
3444 btn_check_timer);
3445
3446 queue_delayed_work(system_power_efficient_wq,
3447 &rt5645->jack_detect_work, msecs_to_jiffies(5));
3448 }
3449
rt5645_probe(struct snd_soc_component * component)3450 static int rt5645_probe(struct snd_soc_component *component)
3451 {
3452 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3453 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
3454
3455 rt5645->component = component;
3456
3457 switch (rt5645->codec_type) {
3458 case CODEC_TYPE_RT5645:
3459 snd_soc_dapm_new_controls(dapm,
3460 rt5645_specific_dapm_widgets,
3461 ARRAY_SIZE(rt5645_specific_dapm_widgets));
3462 snd_soc_dapm_add_routes(dapm,
3463 rt5645_specific_dapm_routes,
3464 ARRAY_SIZE(rt5645_specific_dapm_routes));
3465 if (rt5645->v_id < 3) {
3466 snd_soc_dapm_add_routes(dapm,
3467 rt5645_old_dapm_routes,
3468 ARRAY_SIZE(rt5645_old_dapm_routes));
3469 }
3470 break;
3471 case CODEC_TYPE_RT5650:
3472 snd_soc_dapm_new_controls(dapm,
3473 rt5650_specific_dapm_widgets,
3474 ARRAY_SIZE(rt5650_specific_dapm_widgets));
3475 snd_soc_dapm_add_routes(dapm,
3476 rt5650_specific_dapm_routes,
3477 ARRAY_SIZE(rt5650_specific_dapm_routes));
3478 break;
3479 }
3480
3481 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
3482
3483 /* for JD function */
3484 if (rt5645->pdata.jd_mode) {
3485 snd_soc_dapm_force_enable_pin(dapm, "JD Power");
3486 snd_soc_dapm_force_enable_pin(dapm, "LDO2");
3487 snd_soc_dapm_sync(dapm);
3488 }
3489
3490 if (rt5645->pdata.long_name)
3491 component->card->long_name = rt5645->pdata.long_name;
3492
3493 rt5645->eq_param = devm_kcalloc(component->dev,
3494 RT5645_HWEQ_NUM, sizeof(struct rt5645_eq_param_s),
3495 GFP_KERNEL);
3496
3497 if (!rt5645->eq_param)
3498 return -ENOMEM;
3499
3500 return 0;
3501 }
3502
rt5645_remove(struct snd_soc_component * component)3503 static void rt5645_remove(struct snd_soc_component *component)
3504 {
3505 rt5645_reset(component);
3506 }
3507
3508 #ifdef CONFIG_PM
rt5645_suspend(struct snd_soc_component * component)3509 static int rt5645_suspend(struct snd_soc_component *component)
3510 {
3511 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
3512
3513 regcache_cache_only(rt5645->regmap, true);
3514 regcache_mark_dirty(rt5645->regmap);
3515
3516 return 0;
3517 }
3518
rt5645_resume(struct snd_soc_component * component)3519 static int rt5645_resume(struct snd_soc_component *component)
3520 {
3521 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
3522
3523 regcache_cache_only(rt5645->regmap, false);
3524 regcache_sync(rt5645->regmap);
3525
3526 return 0;
3527 }
3528 #else
3529 #define rt5645_suspend NULL
3530 #define rt5645_resume NULL
3531 #endif
3532
3533 #define RT5645_STEREO_RATES SNDRV_PCM_RATE_8000_96000
3534 #define RT5645_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
3535 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
3536
3537 static const struct snd_soc_dai_ops rt5645_aif_dai_ops = {
3538 .hw_params = rt5645_hw_params,
3539 .set_fmt = rt5645_set_dai_fmt,
3540 .set_sysclk = rt5645_set_dai_sysclk,
3541 .set_tdm_slot = rt5645_set_tdm_slot,
3542 .set_pll = rt5645_set_dai_pll,
3543 };
3544
3545 static struct snd_soc_dai_driver rt5645_dai[] = {
3546 {
3547 .name = "rt5645-aif1",
3548 .id = RT5645_AIF1,
3549 .playback = {
3550 .stream_name = "AIF1 Playback",
3551 .channels_min = 1,
3552 .channels_max = 2,
3553 .rates = RT5645_STEREO_RATES,
3554 .formats = RT5645_FORMATS,
3555 },
3556 .capture = {
3557 .stream_name = "AIF1 Capture",
3558 .channels_min = 1,
3559 .channels_max = 4,
3560 .rates = RT5645_STEREO_RATES,
3561 .formats = RT5645_FORMATS,
3562 },
3563 .ops = &rt5645_aif_dai_ops,
3564 },
3565 {
3566 .name = "rt5645-aif2",
3567 .id = RT5645_AIF2,
3568 .playback = {
3569 .stream_name = "AIF2 Playback",
3570 .channels_min = 1,
3571 .channels_max = 2,
3572 .rates = RT5645_STEREO_RATES,
3573 .formats = RT5645_FORMATS,
3574 },
3575 .capture = {
3576 .stream_name = "AIF2 Capture",
3577 .channels_min = 1,
3578 .channels_max = 2,
3579 .rates = RT5645_STEREO_RATES,
3580 .formats = RT5645_FORMATS,
3581 },
3582 .ops = &rt5645_aif_dai_ops,
3583 },
3584 };
3585
3586 static const struct snd_soc_component_driver soc_component_dev_rt5645 = {
3587 .probe = rt5645_probe,
3588 .remove = rt5645_remove,
3589 .suspend = rt5645_suspend,
3590 .resume = rt5645_resume,
3591 .set_bias_level = rt5645_set_bias_level,
3592 .controls = rt5645_snd_controls,
3593 .num_controls = ARRAY_SIZE(rt5645_snd_controls),
3594 .dapm_widgets = rt5645_dapm_widgets,
3595 .num_dapm_widgets = ARRAY_SIZE(rt5645_dapm_widgets),
3596 .dapm_routes = rt5645_dapm_routes,
3597 .num_dapm_routes = ARRAY_SIZE(rt5645_dapm_routes),
3598 .set_jack = rt5645_component_set_jack,
3599 .use_pmdown_time = 1,
3600 .endianness = 1,
3601 };
3602
3603 static const struct regmap_config rt5645_regmap = {
3604 .reg_bits = 8,
3605 .val_bits = 16,
3606 .use_single_read = true,
3607 .use_single_write = true,
3608 .max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) *
3609 RT5645_PR_SPACING),
3610 .volatile_reg = rt5645_volatile_register,
3611 .readable_reg = rt5645_readable_register,
3612
3613 .cache_type = REGCACHE_MAPLE,
3614 .reg_defaults = rt5645_reg,
3615 .num_reg_defaults = ARRAY_SIZE(rt5645_reg),
3616 .ranges = rt5645_ranges,
3617 .num_ranges = ARRAY_SIZE(rt5645_ranges),
3618 };
3619
3620 static const struct regmap_config rt5650_regmap = {
3621 .reg_bits = 8,
3622 .val_bits = 16,
3623 .use_single_read = true,
3624 .use_single_write = true,
3625 .max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) *
3626 RT5645_PR_SPACING),
3627 .volatile_reg = rt5645_volatile_register,
3628 .readable_reg = rt5645_readable_register,
3629
3630 .cache_type = REGCACHE_MAPLE,
3631 .reg_defaults = rt5650_reg,
3632 .num_reg_defaults = ARRAY_SIZE(rt5650_reg),
3633 .ranges = rt5645_ranges,
3634 .num_ranges = ARRAY_SIZE(rt5645_ranges),
3635 };
3636
3637 static const struct regmap_config temp_regmap = {
3638 .name="nocache",
3639 .reg_bits = 8,
3640 .val_bits = 16,
3641 .use_single_read = true,
3642 .use_single_write = true,
3643 .max_register = RT5645_VENDOR_ID2 + 1,
3644 .cache_type = REGCACHE_NONE,
3645 };
3646
3647 static const struct i2c_device_id rt5645_i2c_id[] = {
3648 { "rt5645" },
3649 { "rt5650" },
3650 { }
3651 };
3652 MODULE_DEVICE_TABLE(i2c, rt5645_i2c_id);
3653
3654 #ifdef CONFIG_OF
3655 static const struct of_device_id rt5645_of_match[] = {
3656 { .compatible = "realtek,rt5645", },
3657 { .compatible = "realtek,rt5650", },
3658 { }
3659 };
3660 MODULE_DEVICE_TABLE(of, rt5645_of_match);
3661 #endif
3662
3663 #ifdef CONFIG_ACPI
3664 static const struct acpi_device_id rt5645_acpi_match[] = {
3665 { "10EC3270" },
3666 { "10EC5640" },
3667 { "10EC5645" },
3668 { "10EC5648" },
3669 { "10EC5650" },
3670 { }
3671 };
3672 MODULE_DEVICE_TABLE(acpi, rt5645_acpi_match);
3673 #endif
3674
3675 static const struct rt5645_platform_data intel_braswell_platform_data = {
3676 .dmic1_data_pin = RT5645_DMIC1_DISABLE,
3677 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P,
3678 .jd_mode = 3,
3679 };
3680
3681 static const struct rt5645_platform_data buddy_platform_data = {
3682 .dmic1_data_pin = RT5645_DMIC_DATA_GPIO5,
3683 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P,
3684 .jd_mode = 4,
3685 .level_trigger_irq = true,
3686 };
3687
3688 static const struct rt5645_platform_data gpd_win_platform_data = {
3689 .jd_mode = 3,
3690 .inv_jd1_1 = true,
3691 .mono_speaker = true,
3692 .long_name = "gpd-win-pocket-rt5645",
3693 /* The GPD pocket has a diff. mic, for the win this does not matter. */
3694 .in2_diff = true,
3695 };
3696
3697 static const struct rt5645_platform_data asus_t100ha_platform_data = {
3698 .dmic1_data_pin = RT5645_DMIC_DATA_IN2N,
3699 .dmic2_data_pin = RT5645_DMIC2_DISABLE,
3700 .jd_mode = 3,
3701 .inv_jd1_1 = true,
3702 };
3703
3704 static const struct rt5645_platform_data asus_t101ha_platform_data = {
3705 .dmic1_data_pin = RT5645_DMIC_DATA_IN2N,
3706 .dmic2_data_pin = RT5645_DMIC2_DISABLE,
3707 .jd_mode = 3,
3708 };
3709
3710 static const struct rt5645_platform_data lenovo_ideapad_miix_310_pdata = {
3711 .jd_mode = 3,
3712 .in2_diff = true,
3713 };
3714
3715 static const struct rt5645_platform_data jd_mode3_monospk_platform_data = {
3716 .jd_mode = 3,
3717 .mono_speaker = true,
3718 };
3719
3720 static const struct rt5645_platform_data jd_mode3_inv_data = {
3721 .jd_mode = 3,
3722 .inv_jd1_1 = true,
3723 };
3724
3725 static const struct rt5645_platform_data jd_mode3_platform_data = {
3726 .jd_mode = 3,
3727 };
3728
3729 static const struct rt5645_platform_data lattepanda_board_platform_data = {
3730 .jd_mode = 2,
3731 .inv_jd1_1 = true
3732 };
3733
3734 static const struct rt5645_platform_data kahlee_platform_data = {
3735 .dmic1_data_pin = RT5645_DMIC_DATA_GPIO5,
3736 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P,
3737 .jd_mode = 3,
3738 };
3739
3740 static const struct rt5645_platform_data ecs_ef20_platform_data = {
3741 .dmic1_data_pin = RT5645_DMIC1_DISABLE,
3742 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P,
3743 .inv_hp_pol = 1,
3744 };
3745
3746 static const struct acpi_gpio_params ef20_hp_detect = { 1, 0, false };
3747
3748 static const struct acpi_gpio_mapping cht_rt5645_ef20_gpios[] = {
3749 { "hp-detect-gpios", &ef20_hp_detect, 1 },
3750 { },
3751 };
3752
cht_rt5645_ef20_quirk_cb(const struct dmi_system_id * id)3753 static int cht_rt5645_ef20_quirk_cb(const struct dmi_system_id *id)
3754 {
3755 cht_rt5645_gpios = cht_rt5645_ef20_gpios;
3756 return 1;
3757 }
3758
3759 static const struct dmi_system_id dmi_platform_data[] = {
3760 {
3761 .ident = "Chrome Buddy",
3762 .matches = {
3763 DMI_MATCH(DMI_PRODUCT_NAME, "Buddy"),
3764 },
3765 .driver_data = (void *)&buddy_platform_data,
3766 },
3767 {
3768 .ident = "Intel Strago",
3769 .matches = {
3770 DMI_MATCH(DMI_PRODUCT_NAME, "Strago"),
3771 },
3772 .driver_data = (void *)&intel_braswell_platform_data,
3773 },
3774 {
3775 .ident = "Google Chrome",
3776 .matches = {
3777 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
3778 },
3779 .driver_data = (void *)&intel_braswell_platform_data,
3780 },
3781 {
3782 .ident = "Google Setzer",
3783 .matches = {
3784 DMI_MATCH(DMI_PRODUCT_NAME, "Setzer"),
3785 },
3786 .driver_data = (void *)&intel_braswell_platform_data,
3787 },
3788 {
3789 .ident = "Microsoft Surface 3",
3790 .matches = {
3791 DMI_MATCH(DMI_PRODUCT_NAME, "Surface 3"),
3792 },
3793 .driver_data = (void *)&intel_braswell_platform_data,
3794 },
3795 {
3796 /*
3797 * Match for the GPDwin which unfortunately uses somewhat
3798 * generic dmi strings, which is why we test for 4 strings.
3799 * Comparing against 23 other byt/cht boards, board_vendor
3800 * and board_name are unique to the GPDwin, where as only one
3801 * other board has the same board_serial and 3 others have
3802 * the same default product_name. Also the GPDwin is the
3803 * only device to have both board_ and product_name not set.
3804 */
3805 .ident = "GPD Win / Pocket",
3806 .matches = {
3807 DMI_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"),
3808 DMI_MATCH(DMI_BOARD_NAME, "Default string"),
3809 DMI_MATCH(DMI_BOARD_SERIAL, "Default string"),
3810 DMI_MATCH(DMI_PRODUCT_NAME, "Default string"),
3811 },
3812 .driver_data = (void *)&gpd_win_platform_data,
3813 },
3814 {
3815 .ident = "ASUS T100HAN",
3816 .matches = {
3817 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
3818 DMI_MATCH(DMI_PRODUCT_NAME, "T100HAN"),
3819 },
3820 .driver_data = (void *)&asus_t100ha_platform_data,
3821 },
3822 {
3823 .ident = "ASUS T101HA",
3824 .matches = {
3825 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
3826 DMI_MATCH(DMI_PRODUCT_NAME, "T101HA"),
3827 },
3828 .driver_data = (void *)&asus_t101ha_platform_data,
3829 },
3830 {
3831 .ident = "MINIX Z83-4",
3832 .matches = {
3833 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "MINIX"),
3834 DMI_MATCH(DMI_PRODUCT_NAME, "Z83-4"),
3835 },
3836 .driver_data = (void *)&jd_mode3_platform_data,
3837 },
3838 {
3839 .ident = "Teclast X80 Pro",
3840 .matches = {
3841 DMI_MATCH(DMI_SYS_VENDOR, "TECLAST"),
3842 DMI_MATCH(DMI_PRODUCT_NAME, "X80 Pro"),
3843 },
3844 .driver_data = (void *)&jd_mode3_monospk_platform_data,
3845 },
3846 {
3847 .ident = "Lenovo Ideapad Miix 310",
3848 .matches = {
3849 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "LENOVO"),
3850 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "80SG"),
3851 DMI_EXACT_MATCH(DMI_PRODUCT_VERSION, "MIIX 310-10ICR"),
3852 },
3853 .driver_data = (void *)&lenovo_ideapad_miix_310_pdata,
3854 },
3855 {
3856 .ident = "Lenovo Ideapad Miix 320",
3857 .matches = {
3858 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "LENOVO"),
3859 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "80XF"),
3860 DMI_EXACT_MATCH(DMI_PRODUCT_VERSION, "Lenovo MIIX 320-10ICR"),
3861 },
3862 .driver_data = (void *)&intel_braswell_platform_data,
3863 },
3864 {
3865 .ident = "LattePanda board",
3866 .matches = {
3867 DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"),
3868 DMI_EXACT_MATCH(DMI_BOARD_NAME, "Cherry Trail CR"),
3869 DMI_EXACT_MATCH(DMI_BOARD_VERSION, "Default string"),
3870 /*
3871 * Above strings are too generic, LattePanda BIOS versions for
3872 * all 4 hw revisions are:
3873 * DF-BI-7-S70CR100-*
3874 * DF-BI-7-S70CR110-*
3875 * DF-BI-7-S70CR200-*
3876 * LP-BS-7-S70CR700-*
3877 * Do a partial match for S70CR to avoid false positive matches.
3878 */
3879 DMI_MATCH(DMI_BIOS_VERSION, "S70CR"),
3880 },
3881 .driver_data = (void *)&lattepanda_board_platform_data,
3882 },
3883 {
3884 .ident = "Chrome Kahlee",
3885 .matches = {
3886 DMI_MATCH(DMI_PRODUCT_NAME, "Kahlee"),
3887 },
3888 .driver_data = (void *)&kahlee_platform_data,
3889 },
3890 {
3891 .ident = "Medion E1239T",
3892 .matches = {
3893 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "MEDION"),
3894 DMI_MATCH(DMI_PRODUCT_NAME, "E1239T MD60568"),
3895 },
3896 .driver_data = (void *)&intel_braswell_platform_data,
3897 },
3898 {
3899 .ident = "EF20",
3900 .callback = cht_rt5645_ef20_quirk_cb,
3901 .matches = {
3902 DMI_MATCH(DMI_PRODUCT_NAME, "EF20"),
3903 },
3904 .driver_data = (void *)&ecs_ef20_platform_data,
3905 },
3906 {
3907 .ident = "Acer Switch V 10 (SW5-017)",
3908 .matches = {
3909 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "Acer"),
3910 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "SW5-017"),
3911 },
3912 .driver_data = (void *)&intel_braswell_platform_data,
3913 },
3914 {
3915 .ident = "Meegopad T08",
3916 .matches = {
3917 DMI_MATCH(DMI_SYS_VENDOR, "Default string"),
3918 DMI_MATCH(DMI_PRODUCT_NAME, "Default string"),
3919 DMI_MATCH(DMI_BOARD_NAME, "T3 MRD"),
3920 DMI_MATCH(DMI_BOARD_VERSION, "V1.1"),
3921 },
3922 .driver_data = (void *)&jd_mode3_inv_data,
3923 },
3924 { }
3925 };
3926
rt5645_check_dp(struct device * dev)3927 static bool rt5645_check_dp(struct device *dev)
3928 {
3929 if (device_property_present(dev, "realtek,in2-differential") ||
3930 device_property_present(dev, "realtek,dmic1-data-pin") ||
3931 device_property_present(dev, "realtek,dmic2-data-pin") ||
3932 device_property_present(dev, "realtek,jd-mode"))
3933 return true;
3934
3935 return false;
3936 }
3937
rt5645_parse_dt(struct device * dev,struct rt5645_platform_data * pdata)3938 static void rt5645_parse_dt(struct device *dev, struct rt5645_platform_data *pdata)
3939 {
3940 pdata->in2_diff = device_property_read_bool(dev, "realtek,in2-differential");
3941 device_property_read_u32(dev, "realtek,dmic1-data-pin", &pdata->dmic1_data_pin);
3942 device_property_read_u32(dev, "realtek,dmic2-data-pin", &pdata->dmic2_data_pin);
3943 device_property_read_u32(dev, "realtek,jd-mode", &pdata->jd_mode);
3944 }
3945
rt5645_get_pdata(struct device * codec_dev,struct rt5645_platform_data * pdata)3946 static void rt5645_get_pdata(struct device *codec_dev, struct rt5645_platform_data *pdata)
3947 {
3948 const struct dmi_system_id *dmi_data;
3949
3950 dmi_data = dmi_first_match(dmi_platform_data);
3951 if (dmi_data) {
3952 dev_info(codec_dev, "Detected %s platform\n", dmi_data->ident);
3953 *pdata = *((struct rt5645_platform_data *)dmi_data->driver_data);
3954 } else if (rt5645_check_dp(codec_dev)) {
3955 rt5645_parse_dt(codec_dev, pdata);
3956 } else {
3957 *pdata = jd_mode3_platform_data;
3958 }
3959
3960 if (quirk != -1) {
3961 pdata->in2_diff = QUIRK_IN2_DIFF(quirk);
3962 pdata->level_trigger_irq = QUIRK_LEVEL_IRQ(quirk);
3963 pdata->inv_jd1_1 = QUIRK_INV_JD1_1(quirk);
3964 pdata->inv_hp_pol = QUIRK_INV_HP_POL(quirk);
3965 pdata->jd_mode = QUIRK_JD_MODE(quirk);
3966 pdata->dmic1_data_pin = QUIRK_DMIC1_DATA_PIN(quirk);
3967 pdata->dmic2_data_pin = QUIRK_DMIC2_DATA_PIN(quirk);
3968 }
3969 }
3970
rt5645_components(struct device * codec_dev)3971 const char *rt5645_components(struct device *codec_dev)
3972 {
3973 struct rt5645_platform_data pdata = { };
3974 static char buf[32];
3975 const char *mic;
3976 int spk = 2;
3977
3978 rt5645_get_pdata(codec_dev, &pdata);
3979
3980 if (pdata.mono_speaker)
3981 spk = 1;
3982
3983 if (pdata.dmic1_data_pin && pdata.dmic2_data_pin)
3984 mic = "dmics12";
3985 else if (pdata.dmic1_data_pin)
3986 mic = "dmic1";
3987 else if (pdata.dmic2_data_pin)
3988 mic = "dmic2";
3989 else
3990 mic = "in2";
3991
3992 snprintf(buf, sizeof(buf), "cfg-spk:%d cfg-mic:%s", spk, mic);
3993
3994 return buf;
3995 }
3996 EXPORT_SYMBOL_GPL(rt5645_components);
3997
rt5645_i2c_probe(struct i2c_client * i2c)3998 static int rt5645_i2c_probe(struct i2c_client *i2c)
3999 {
4000 struct rt5645_priv *rt5645;
4001 int ret, i;
4002 unsigned int val;
4003 struct regmap *regmap;
4004
4005 rt5645 = devm_kzalloc(&i2c->dev, sizeof(struct rt5645_priv),
4006 GFP_KERNEL);
4007 if (rt5645 == NULL)
4008 return -ENOMEM;
4009
4010 rt5645->i2c = i2c;
4011 i2c_set_clientdata(i2c, rt5645);
4012 rt5645_get_pdata(&i2c->dev, &rt5645->pdata);
4013
4014 if (has_acpi_companion(&i2c->dev)) {
4015 if (cht_rt5645_gpios) {
4016 if (devm_acpi_dev_add_driver_gpios(&i2c->dev, cht_rt5645_gpios))
4017 dev_dbg(&i2c->dev, "Failed to add driver gpios\n");
4018 }
4019
4020 /* The ALC3270 package has the headset-mic pin not-connected */
4021 if (acpi_dev_hid_uid_match(ACPI_COMPANION(&i2c->dev), "10EC3270", NULL))
4022 rt5645->pdata.no_headset_mic = true;
4023 }
4024
4025 rt5645->gpiod_hp_det = devm_gpiod_get_optional(&i2c->dev, "hp-detect",
4026 GPIOD_IN);
4027
4028 if (IS_ERR(rt5645->gpiod_hp_det)) {
4029 dev_info(&i2c->dev, "failed to initialize gpiod\n");
4030 ret = PTR_ERR(rt5645->gpiod_hp_det);
4031 /*
4032 * Continue if optional gpiod is missing, bail for all other
4033 * errors, including -EPROBE_DEFER
4034 */
4035 if (ret != -ENOENT)
4036 return ret;
4037 }
4038
4039 rt5645->gpiod_cbj_sleeve = devm_gpiod_get_optional(&i2c->dev, "cbj-sleeve",
4040 GPIOD_OUT_LOW);
4041
4042 if (IS_ERR(rt5645->gpiod_cbj_sleeve)) {
4043 ret = PTR_ERR(rt5645->gpiod_cbj_sleeve);
4044 dev_info(&i2c->dev, "failed to initialize gpiod, ret=%d\n", ret);
4045 if (ret != -ENOENT)
4046 return ret;
4047 }
4048
4049 for (i = 0; i < ARRAY_SIZE(rt5645->supplies); i++)
4050 rt5645->supplies[i].supply = rt5645_supply_names[i];
4051
4052 ret = devm_regulator_bulk_get(&i2c->dev,
4053 ARRAY_SIZE(rt5645->supplies),
4054 rt5645->supplies);
4055 if (ret) {
4056 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
4057 return ret;
4058 }
4059
4060 ret = regulator_bulk_enable(ARRAY_SIZE(rt5645->supplies),
4061 rt5645->supplies);
4062 if (ret) {
4063 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
4064 return ret;
4065 }
4066
4067 regmap = devm_regmap_init_i2c(i2c, &temp_regmap);
4068 if (IS_ERR(regmap)) {
4069 ret = PTR_ERR(regmap);
4070 dev_err(&i2c->dev, "Failed to allocate temp register map: %d\n",
4071 ret);
4072 goto err_enable;
4073 }
4074
4075 /*
4076 * Read after 400msec, as it is the interval required between
4077 * read and power On.
4078 */
4079 msleep(TIME_TO_POWER_MS);
4080 ret = regmap_read(regmap, RT5645_VENDOR_ID2, &val);
4081 if (ret < 0) {
4082 dev_err(&i2c->dev, "Failed to read: 0x%02X\n, ret = %d", RT5645_VENDOR_ID2, ret);
4083 goto err_enable;
4084 }
4085
4086 switch (val) {
4087 case RT5645_DEVICE_ID:
4088 rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5645_regmap);
4089 rt5645->codec_type = CODEC_TYPE_RT5645;
4090 break;
4091 case RT5650_DEVICE_ID:
4092 rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5650_regmap);
4093 rt5645->codec_type = CODEC_TYPE_RT5650;
4094 break;
4095 default:
4096 dev_err(&i2c->dev,
4097 "Device with ID register %#x is not rt5645 or rt5650\n",
4098 val);
4099 ret = -ENODEV;
4100 goto err_enable;
4101 }
4102
4103 if (IS_ERR(rt5645->regmap)) {
4104 ret = PTR_ERR(rt5645->regmap);
4105 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
4106 ret);
4107 goto err_enable;
4108 }
4109
4110 regmap_write(rt5645->regmap, RT5645_RESET, 0);
4111
4112 regmap_read(regmap, RT5645_VENDOR_ID, &val);
4113 rt5645->v_id = val & 0xff;
4114
4115 regmap_write(rt5645->regmap, RT5645_AD_DA_MIXER, 0x8080);
4116
4117 ret = regmap_multi_reg_write(rt5645->regmap, init_list,
4118 ARRAY_SIZE(init_list));
4119 if (ret != 0)
4120 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
4121
4122 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
4123 ret = regmap_multi_reg_write(rt5645->regmap, rt5650_init_list,
4124 ARRAY_SIZE(rt5650_init_list));
4125 if (ret != 0)
4126 dev_warn(&i2c->dev, "Apply rt5650 patch failed: %d\n",
4127 ret);
4128 }
4129
4130 regmap_update_bits(rt5645->regmap, RT5645_CLSD_OUT_CTRL, 0xc0, 0xc0);
4131
4132 if (rt5645->pdata.in2_diff)
4133 regmap_update_bits(rt5645->regmap, RT5645_IN2_CTRL,
4134 RT5645_IN_DF2, RT5645_IN_DF2);
4135
4136 if (rt5645->pdata.dmic1_data_pin || rt5645->pdata.dmic2_data_pin) {
4137 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
4138 RT5645_GP2_PIN_MASK, RT5645_GP2_PIN_DMIC1_SCL);
4139 }
4140 switch (rt5645->pdata.dmic1_data_pin) {
4141 case RT5645_DMIC_DATA_IN2N:
4142 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
4143 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_IN2N);
4144 break;
4145
4146 case RT5645_DMIC_DATA_GPIO5:
4147 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
4148 RT5645_I2S2_DAC_PIN_MASK, RT5645_I2S2_DAC_PIN_GPIO);
4149 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
4150 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO5);
4151 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
4152 RT5645_GP5_PIN_MASK, RT5645_GP5_PIN_DMIC1_SDA);
4153 break;
4154
4155 case RT5645_DMIC_DATA_GPIO11:
4156 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
4157 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO11);
4158 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
4159 RT5645_GP11_PIN_MASK,
4160 RT5645_GP11_PIN_DMIC1_SDA);
4161 break;
4162
4163 default:
4164 break;
4165 }
4166
4167 switch (rt5645->pdata.dmic2_data_pin) {
4168 case RT5645_DMIC_DATA_IN2P:
4169 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
4170 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_IN2P);
4171 break;
4172
4173 case RT5645_DMIC_DATA_GPIO6:
4174 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
4175 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO6);
4176 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
4177 RT5645_GP6_PIN_MASK, RT5645_GP6_PIN_DMIC2_SDA);
4178 break;
4179
4180 case RT5645_DMIC_DATA_GPIO10:
4181 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
4182 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO10);
4183 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
4184 RT5645_GP10_PIN_MASK,
4185 RT5645_GP10_PIN_DMIC2_SDA);
4186 break;
4187
4188 case RT5645_DMIC_DATA_GPIO12:
4189 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
4190 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO12);
4191 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
4192 RT5645_GP12_PIN_MASK,
4193 RT5645_GP12_PIN_DMIC2_SDA);
4194 break;
4195
4196 default:
4197 break;
4198 }
4199
4200 if (rt5645->pdata.jd_mode) {
4201 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
4202 RT5645_IRQ_CLK_GATE_CTRL,
4203 RT5645_IRQ_CLK_GATE_CTRL);
4204 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
4205 RT5645_IRQ_CLK_INT, RT5645_IRQ_CLK_INT);
4206 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
4207 RT5645_IRQ_JD_1_1_EN, RT5645_IRQ_JD_1_1_EN);
4208 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
4209 RT5645_JD_PSV_MODE, RT5645_JD_PSV_MODE);
4210 regmap_update_bits(rt5645->regmap, RT5645_HPO_MIXER,
4211 RT5645_IRQ_PSV_MODE, RT5645_IRQ_PSV_MODE);
4212 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
4213 RT5645_MIC2_OVCD_EN, RT5645_MIC2_OVCD_EN);
4214 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
4215 RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ);
4216 switch (rt5645->pdata.jd_mode) {
4217 case 1:
4218 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
4219 RT5645_JD1_MODE_MASK,
4220 RT5645_JD1_MODE_0);
4221 break;
4222 case 2:
4223 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
4224 RT5645_JD1_MODE_MASK,
4225 RT5645_JD1_MODE_1);
4226 break;
4227 case 3:
4228 case 4:
4229 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
4230 RT5645_JD1_MODE_MASK,
4231 RT5645_JD1_MODE_2);
4232 break;
4233 default:
4234 break;
4235 }
4236 if (rt5645->pdata.inv_jd1_1) {
4237 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
4238 RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV);
4239 }
4240 }
4241
4242 regmap_update_bits(rt5645->regmap, RT5645_ADDA_CLK1,
4243 RT5645_I2S_PD1_MASK, RT5645_I2S_PD1_2);
4244
4245 if (rt5645->pdata.level_trigger_irq) {
4246 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
4247 RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV);
4248 }
4249 timer_setup(&rt5645->btn_check_timer, rt5645_btn_check_callback, 0);
4250
4251 mutex_init(&rt5645->jd_mutex);
4252 INIT_DELAYED_WORK(&rt5645->jack_detect_work, rt5645_jack_detect_work);
4253 INIT_DELAYED_WORK(&rt5645->rcclock_work, rt5645_rcclock_work);
4254
4255 if (rt5645->i2c->irq) {
4256 ret = request_threaded_irq(rt5645->i2c->irq, NULL, rt5645_irq,
4257 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
4258 | IRQF_ONESHOT, "rt5645", rt5645);
4259 if (ret) {
4260 dev_err(&i2c->dev, "Failed to request IRQ: %d\n", ret);
4261 goto err_enable;
4262 }
4263 }
4264
4265 ret = devm_snd_soc_register_component(&i2c->dev, &soc_component_dev_rt5645,
4266 rt5645_dai, ARRAY_SIZE(rt5645_dai));
4267 if (ret)
4268 goto err_irq;
4269
4270 return 0;
4271
4272 err_irq:
4273 if (rt5645->i2c->irq)
4274 free_irq(rt5645->i2c->irq, rt5645);
4275 err_enable:
4276 regulator_bulk_disable(ARRAY_SIZE(rt5645->supplies), rt5645->supplies);
4277 return ret;
4278 }
4279
rt5645_i2c_remove(struct i2c_client * i2c)4280 static void rt5645_i2c_remove(struct i2c_client *i2c)
4281 {
4282 struct rt5645_priv *rt5645 = i2c_get_clientdata(i2c);
4283
4284 if (i2c->irq)
4285 free_irq(i2c->irq, rt5645);
4286
4287 /*
4288 * Since the rt5645_btn_check_callback() can queue jack_detect_work,
4289 * the timer need to be delted first
4290 */
4291 timer_delete_sync(&rt5645->btn_check_timer);
4292
4293 cancel_delayed_work_sync(&rt5645->jack_detect_work);
4294 cancel_delayed_work_sync(&rt5645->rcclock_work);
4295
4296 if (rt5645->gpiod_cbj_sleeve)
4297 gpiod_set_value(rt5645->gpiod_cbj_sleeve, 0);
4298
4299 regulator_bulk_disable(ARRAY_SIZE(rt5645->supplies), rt5645->supplies);
4300 }
4301
rt5645_i2c_shutdown(struct i2c_client * i2c)4302 static void rt5645_i2c_shutdown(struct i2c_client *i2c)
4303 {
4304 struct rt5645_priv *rt5645 = i2c_get_clientdata(i2c);
4305
4306 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
4307 RT5645_RING2_SLEEVE_GND, RT5645_RING2_SLEEVE_GND);
4308 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2, RT5645_CBJ_MN_JD,
4309 RT5645_CBJ_MN_JD);
4310 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1, RT5645_CBJ_BST1_EN,
4311 0);
4312 msleep(20);
4313 regmap_write(rt5645->regmap, RT5645_RESET, 0);
4314
4315 if (rt5645->gpiod_cbj_sleeve)
4316 gpiod_set_value(rt5645->gpiod_cbj_sleeve, 0);
4317 }
4318
rt5645_sys_suspend(struct device * dev)4319 static int rt5645_sys_suspend(struct device *dev)
4320 {
4321 struct rt5645_priv *rt5645 = dev_get_drvdata(dev);
4322
4323 timer_delete_sync(&rt5645->btn_check_timer);
4324 cancel_delayed_work_sync(&rt5645->jack_detect_work);
4325 cancel_delayed_work_sync(&rt5645->rcclock_work);
4326
4327 regcache_cache_only(rt5645->regmap, true);
4328 regcache_mark_dirty(rt5645->regmap);
4329 return 0;
4330 }
4331
rt5645_sys_resume(struct device * dev)4332 static int rt5645_sys_resume(struct device *dev)
4333 {
4334 struct rt5645_priv *rt5645 = dev_get_drvdata(dev);
4335
4336 regcache_cache_only(rt5645->regmap, false);
4337 regcache_sync(rt5645->regmap);
4338
4339 if (rt5645->hp_jack) {
4340 rt5645->jack_type = 0;
4341 rt5645_jack_detect_work(&rt5645->jack_detect_work.work);
4342 }
4343 return 0;
4344 }
4345
4346 static const struct dev_pm_ops rt5645_pm = {
4347 SYSTEM_SLEEP_PM_OPS(rt5645_sys_suspend, rt5645_sys_resume)
4348 };
4349
4350 static struct i2c_driver rt5645_i2c_driver = {
4351 .driver = {
4352 .name = "rt5645",
4353 .of_match_table = of_match_ptr(rt5645_of_match),
4354 .acpi_match_table = ACPI_PTR(rt5645_acpi_match),
4355 .pm = pm_ptr(&rt5645_pm),
4356 },
4357 .probe = rt5645_i2c_probe,
4358 .remove = rt5645_i2c_remove,
4359 .shutdown = rt5645_i2c_shutdown,
4360 .id_table = rt5645_i2c_id,
4361 };
4362 module_i2c_driver(rt5645_i2c_driver);
4363
4364 MODULE_DESCRIPTION("ASoC RT5645 driver");
4365 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
4366 MODULE_LICENSE("GPL v2");
4367