xref: /linux/drivers/net/wireless/ralink/rt2x00/rt2800lib.c (revision 79790b6818e96c58fe2bffee1b418c16e64e7b80)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 	Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
4 	Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
5 	Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
6 	Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
7 
8 	Based on the original rt2800pci.c and rt2800usb.c.
9 	  Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
10 	  Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
11 	  Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
12 	  Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
13 	  Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
14 	  Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
15 	  <http://rt2x00.serialmonkey.com>
16 
17  */
18 
19 /*
20 	Module: rt2800lib
21 	Abstract: rt2800 generic device routines.
22  */
23 
24 #include <linux/crc-ccitt.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/slab.h>
28 
29 #include "rt2x00.h"
30 #include "rt2800lib.h"
31 #include "rt2800.h"
32 
33 static unsigned int modparam_watchdog = RT2800_WATCHDOG_DMA_BUSY;
34 module_param_named(watchdog, modparam_watchdog, uint, 0444);
35 MODULE_PARM_DESC(watchdog, "Enable watchdog to recover tx/rx hangs.\n"
36 		 "\t\t(0=disabled, 1=hang watchdog, 2=DMA watchdog(default), 3=both)");
37 
38 /*
39  * Register access.
40  * All access to the CSR registers will go through the methods
41  * rt2800_register_read and rt2800_register_write.
42  * BBP and RF register require indirect register access,
43  * and use the CSR registers BBPCSR and RFCSR to achieve this.
44  * These indirect registers work with busy bits,
45  * and we will try maximal REGISTER_BUSY_COUNT times to access
46  * the register while taking a REGISTER_BUSY_DELAY us delay
47  * between each attampt. When the busy bit is still set at that time,
48  * the access attempt is considered to have failed,
49  * and we will print an error.
50  * The _lock versions must be used if you already hold the csr_mutex
51  */
52 #define WAIT_FOR_BBP(__dev, __reg) \
53 	rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
54 #define WAIT_FOR_RFCSR(__dev, __reg) \
55 	rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
56 #define WAIT_FOR_RFCSR_MT7620(__dev, __reg) \
57 	rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY_MT7620, \
58 			    (__reg))
59 #define WAIT_FOR_RF(__dev, __reg) \
60 	rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
61 #define WAIT_FOR_MCU(__dev, __reg) \
62 	rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
63 			    H2M_MAILBOX_CSR_OWNER, (__reg))
64 
rt2800_is_305x_soc(struct rt2x00_dev * rt2x00dev)65 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
66 {
67 	/* check for rt2872 on SoC */
68 	if (!rt2x00_is_soc(rt2x00dev) ||
69 	    !rt2x00_rt(rt2x00dev, RT2872))
70 		return false;
71 
72 	/* we know for sure that these rf chipsets are used on rt305x boards */
73 	if (rt2x00_rf(rt2x00dev, RF3020) ||
74 	    rt2x00_rf(rt2x00dev, RF3021) ||
75 	    rt2x00_rf(rt2x00dev, RF3022))
76 		return true;
77 
78 	rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n");
79 	return false;
80 }
81 
rt2800_bbp_write(struct rt2x00_dev * rt2x00dev,const unsigned int word,const u8 value)82 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
83 			     const unsigned int word, const u8 value)
84 {
85 	u32 reg;
86 
87 	mutex_lock(&rt2x00dev->csr_mutex);
88 
89 	/*
90 	 * Wait until the BBP becomes available, afterwards we
91 	 * can safely write the new data into the register.
92 	 */
93 	if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
94 		reg = 0;
95 		rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
96 		rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
97 		rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
98 		rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
99 		rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
100 
101 		rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
102 	}
103 
104 	mutex_unlock(&rt2x00dev->csr_mutex);
105 }
106 
rt2800_bbp_read(struct rt2x00_dev * rt2x00dev,const unsigned int word)107 static u8 rt2800_bbp_read(struct rt2x00_dev *rt2x00dev, const unsigned int word)
108 {
109 	u32 reg;
110 	u8 value;
111 
112 	mutex_lock(&rt2x00dev->csr_mutex);
113 
114 	/*
115 	 * Wait until the BBP becomes available, afterwards we
116 	 * can safely write the read request into the register.
117 	 * After the data has been written, we wait until hardware
118 	 * returns the correct value, if at any time the register
119 	 * doesn't become available in time, reg will be 0xffffffff
120 	 * which means we return 0xff to the caller.
121 	 */
122 	if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
123 		reg = 0;
124 		rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
125 		rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
126 		rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
127 		rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
128 
129 		rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
130 
131 		WAIT_FOR_BBP(rt2x00dev, &reg);
132 	}
133 
134 	value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
135 
136 	mutex_unlock(&rt2x00dev->csr_mutex);
137 
138 	return value;
139 }
140 
rt2800_rfcsr_write(struct rt2x00_dev * rt2x00dev,const unsigned int word,const u8 value)141 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
142 			       const unsigned int word, const u8 value)
143 {
144 	u32 reg;
145 
146 	mutex_lock(&rt2x00dev->csr_mutex);
147 
148 	/*
149 	 * Wait until the RFCSR becomes available, afterwards we
150 	 * can safely write the new data into the register.
151 	 */
152 	switch (rt2x00dev->chip.rt) {
153 	case RT6352:
154 		if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg)) {
155 			reg = 0;
156 			rt2x00_set_field32(&reg, RF_CSR_CFG_DATA_MT7620, value);
157 			rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM_MT7620,
158 					   word);
159 			rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE_MT7620, 1);
160 			rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY_MT7620, 1);
161 
162 			rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
163 		}
164 		break;
165 
166 	default:
167 		if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
168 			reg = 0;
169 			rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
170 			rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
171 			rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
172 			rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
173 
174 			rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
175 		}
176 		break;
177 	}
178 
179 	mutex_unlock(&rt2x00dev->csr_mutex);
180 }
181 
rt2800_rfcsr_write_bank(struct rt2x00_dev * rt2x00dev,const u8 bank,const unsigned int reg,const u8 value)182 static void rt2800_rfcsr_write_bank(struct rt2x00_dev *rt2x00dev, const u8 bank,
183 				    const unsigned int reg, const u8 value)
184 {
185 	rt2800_rfcsr_write(rt2x00dev, (reg | (bank << 6)), value);
186 }
187 
rt2800_rfcsr_write_chanreg(struct rt2x00_dev * rt2x00dev,const unsigned int reg,const u8 value)188 static void rt2800_rfcsr_write_chanreg(struct rt2x00_dev *rt2x00dev,
189 				       const unsigned int reg, const u8 value)
190 {
191 	rt2800_rfcsr_write_bank(rt2x00dev, 4, reg, value);
192 	rt2800_rfcsr_write_bank(rt2x00dev, 6, reg, value);
193 }
194 
rt2800_rfcsr_write_dccal(struct rt2x00_dev * rt2x00dev,const unsigned int reg,const u8 value)195 static void rt2800_rfcsr_write_dccal(struct rt2x00_dev *rt2x00dev,
196 				     const unsigned int reg, const u8 value)
197 {
198 	rt2800_rfcsr_write_bank(rt2x00dev, 5, reg, value);
199 	rt2800_rfcsr_write_bank(rt2x00dev, 7, reg, value);
200 }
201 
rt2800_bbp_dcoc_write(struct rt2x00_dev * rt2x00dev,const u8 reg,const u8 value)202 static void rt2800_bbp_dcoc_write(struct rt2x00_dev *rt2x00dev,
203 				  const u8 reg, const u8 value)
204 {
205 	rt2800_bbp_write(rt2x00dev, 158, reg);
206 	rt2800_bbp_write(rt2x00dev, 159, value);
207 }
208 
rt2800_bbp_dcoc_read(struct rt2x00_dev * rt2x00dev,const u8 reg)209 static u8 rt2800_bbp_dcoc_read(struct rt2x00_dev *rt2x00dev, const u8 reg)
210 {
211 	rt2800_bbp_write(rt2x00dev, 158, reg);
212 	return rt2800_bbp_read(rt2x00dev, 159);
213 }
214 
rt2800_bbp_glrt_write(struct rt2x00_dev * rt2x00dev,const u8 reg,const u8 value)215 static void rt2800_bbp_glrt_write(struct rt2x00_dev *rt2x00dev,
216 				  const u8 reg, const u8 value)
217 {
218 	rt2800_bbp_write(rt2x00dev, 195, reg);
219 	rt2800_bbp_write(rt2x00dev, 196, value);
220 }
221 
rt2800_rfcsr_read(struct rt2x00_dev * rt2x00dev,const unsigned int word)222 static u8 rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
223 			    const unsigned int word)
224 {
225 	u32 reg;
226 	u8 value;
227 
228 	mutex_lock(&rt2x00dev->csr_mutex);
229 
230 	/*
231 	 * Wait until the RFCSR becomes available, afterwards we
232 	 * can safely write the read request into the register.
233 	 * After the data has been written, we wait until hardware
234 	 * returns the correct value, if at any time the register
235 	 * doesn't become available in time, reg will be 0xffffffff
236 	 * which means we return 0xff to the caller.
237 	 */
238 	switch (rt2x00dev->chip.rt) {
239 	case RT6352:
240 		if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg)) {
241 			reg = 0;
242 			rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM_MT7620,
243 					   word);
244 			rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE_MT7620, 0);
245 			rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY_MT7620, 1);
246 
247 			rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
248 
249 			WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg);
250 		}
251 
252 		value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA_MT7620);
253 		break;
254 
255 	default:
256 		if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
257 			reg = 0;
258 			rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
259 			rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
260 			rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
261 
262 			rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
263 
264 			WAIT_FOR_RFCSR(rt2x00dev, &reg);
265 		}
266 
267 		value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
268 		break;
269 	}
270 
271 	mutex_unlock(&rt2x00dev->csr_mutex);
272 
273 	return value;
274 }
275 
rt2800_rfcsr_read_bank(struct rt2x00_dev * rt2x00dev,const u8 bank,const unsigned int reg)276 static u8 rt2800_rfcsr_read_bank(struct rt2x00_dev *rt2x00dev, const u8 bank,
277 				 const unsigned int reg)
278 {
279 	return rt2800_rfcsr_read(rt2x00dev, (reg | (bank << 6)));
280 }
281 
rt2800_rf_write(struct rt2x00_dev * rt2x00dev,const unsigned int word,const u32 value)282 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
283 			    const unsigned int word, const u32 value)
284 {
285 	u32 reg;
286 
287 	mutex_lock(&rt2x00dev->csr_mutex);
288 
289 	/*
290 	 * Wait until the RF becomes available, afterwards we
291 	 * can safely write the new data into the register.
292 	 */
293 	if (WAIT_FOR_RF(rt2x00dev, &reg)) {
294 		reg = 0;
295 		rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
296 		rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
297 		rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
298 		rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
299 
300 		rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
301 		rt2x00_rf_write(rt2x00dev, word, value);
302 	}
303 
304 	mutex_unlock(&rt2x00dev->csr_mutex);
305 }
306 
307 static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = {
308 	[EEPROM_CHIP_ID]		= 0x0000,
309 	[EEPROM_VERSION]		= 0x0001,
310 	[EEPROM_MAC_ADDR_0]		= 0x0002,
311 	[EEPROM_MAC_ADDR_1]		= 0x0003,
312 	[EEPROM_MAC_ADDR_2]		= 0x0004,
313 	[EEPROM_NIC_CONF0]		= 0x001a,
314 	[EEPROM_NIC_CONF1]		= 0x001b,
315 	[EEPROM_FREQ]			= 0x001d,
316 	[EEPROM_LED_AG_CONF]		= 0x001e,
317 	[EEPROM_LED_ACT_CONF]		= 0x001f,
318 	[EEPROM_LED_POLARITY]		= 0x0020,
319 	[EEPROM_NIC_CONF2]		= 0x0021,
320 	[EEPROM_LNA]			= 0x0022,
321 	[EEPROM_RSSI_BG]		= 0x0023,
322 	[EEPROM_RSSI_BG2]		= 0x0024,
323 	[EEPROM_TXMIXER_GAIN_BG]	= 0x0024, /* overlaps with RSSI_BG2 */
324 	[EEPROM_RSSI_A]			= 0x0025,
325 	[EEPROM_RSSI_A2]		= 0x0026,
326 	[EEPROM_TXMIXER_GAIN_A]		= 0x0026, /* overlaps with RSSI_A2 */
327 	[EEPROM_EIRP_MAX_TX_POWER]	= 0x0027,
328 	[EEPROM_TXPOWER_DELTA]		= 0x0028,
329 	[EEPROM_TXPOWER_BG1]		= 0x0029,
330 	[EEPROM_TXPOWER_BG2]		= 0x0030,
331 	[EEPROM_TSSI_BOUND_BG1]		= 0x0037,
332 	[EEPROM_TSSI_BOUND_BG2]		= 0x0038,
333 	[EEPROM_TSSI_BOUND_BG3]		= 0x0039,
334 	[EEPROM_TSSI_BOUND_BG4]		= 0x003a,
335 	[EEPROM_TSSI_BOUND_BG5]		= 0x003b,
336 	[EEPROM_TXPOWER_A1]		= 0x003c,
337 	[EEPROM_TXPOWER_A2]		= 0x0053,
338 	[EEPROM_TXPOWER_INIT]		= 0x0068,
339 	[EEPROM_TSSI_BOUND_A1]		= 0x006a,
340 	[EEPROM_TSSI_BOUND_A2]		= 0x006b,
341 	[EEPROM_TSSI_BOUND_A3]		= 0x006c,
342 	[EEPROM_TSSI_BOUND_A4]		= 0x006d,
343 	[EEPROM_TSSI_BOUND_A5]		= 0x006e,
344 	[EEPROM_TXPOWER_BYRATE]		= 0x006f,
345 	[EEPROM_BBP_START]		= 0x0078,
346 };
347 
348 static const unsigned int rt2800_eeprom_map_ext[EEPROM_WORD_COUNT] = {
349 	[EEPROM_CHIP_ID]		= 0x0000,
350 	[EEPROM_VERSION]		= 0x0001,
351 	[EEPROM_MAC_ADDR_0]		= 0x0002,
352 	[EEPROM_MAC_ADDR_1]		= 0x0003,
353 	[EEPROM_MAC_ADDR_2]		= 0x0004,
354 	[EEPROM_NIC_CONF0]		= 0x001a,
355 	[EEPROM_NIC_CONF1]		= 0x001b,
356 	[EEPROM_NIC_CONF2]		= 0x001c,
357 	[EEPROM_EIRP_MAX_TX_POWER]	= 0x0020,
358 	[EEPROM_FREQ]			= 0x0022,
359 	[EEPROM_LED_AG_CONF]		= 0x0023,
360 	[EEPROM_LED_ACT_CONF]		= 0x0024,
361 	[EEPROM_LED_POLARITY]		= 0x0025,
362 	[EEPROM_LNA]			= 0x0026,
363 	[EEPROM_EXT_LNA2]		= 0x0027,
364 	[EEPROM_RSSI_BG]		= 0x0028,
365 	[EEPROM_RSSI_BG2]		= 0x0029,
366 	[EEPROM_RSSI_A]			= 0x002a,
367 	[EEPROM_RSSI_A2]		= 0x002b,
368 	[EEPROM_TXPOWER_BG1]		= 0x0030,
369 	[EEPROM_TXPOWER_BG2]		= 0x0037,
370 	[EEPROM_EXT_TXPOWER_BG3]	= 0x003e,
371 	[EEPROM_TSSI_BOUND_BG1]		= 0x0045,
372 	[EEPROM_TSSI_BOUND_BG2]		= 0x0046,
373 	[EEPROM_TSSI_BOUND_BG3]		= 0x0047,
374 	[EEPROM_TSSI_BOUND_BG4]		= 0x0048,
375 	[EEPROM_TSSI_BOUND_BG5]		= 0x0049,
376 	[EEPROM_TXPOWER_A1]		= 0x004b,
377 	[EEPROM_TXPOWER_A2]		= 0x0065,
378 	[EEPROM_EXT_TXPOWER_A3]		= 0x007f,
379 	[EEPROM_TSSI_BOUND_A1]		= 0x009a,
380 	[EEPROM_TSSI_BOUND_A2]		= 0x009b,
381 	[EEPROM_TSSI_BOUND_A3]		= 0x009c,
382 	[EEPROM_TSSI_BOUND_A4]		= 0x009d,
383 	[EEPROM_TSSI_BOUND_A5]		= 0x009e,
384 	[EEPROM_TXPOWER_BYRATE]		= 0x00a0,
385 };
386 
rt2800_eeprom_word_index(struct rt2x00_dev * rt2x00dev,const enum rt2800_eeprom_word word)387 static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev,
388 					     const enum rt2800_eeprom_word word)
389 {
390 	const unsigned int *map;
391 	unsigned int index;
392 
393 	if (WARN_ONCE(word >= EEPROM_WORD_COUNT,
394 		      "%s: invalid EEPROM word %d\n",
395 		      wiphy_name(rt2x00dev->hw->wiphy), word))
396 		return 0;
397 
398 	if (rt2x00_rt(rt2x00dev, RT3593) ||
399 	    rt2x00_rt(rt2x00dev, RT3883))
400 		map = rt2800_eeprom_map_ext;
401 	else
402 		map = rt2800_eeprom_map;
403 
404 	index = map[word];
405 
406 	/* Index 0 is valid only for EEPROM_CHIP_ID.
407 	 * Otherwise it means that the offset of the
408 	 * given word is not initialized in the map,
409 	 * or that the field is not usable on the
410 	 * actual chipset.
411 	 */
412 	WARN_ONCE(word != EEPROM_CHIP_ID && index == 0,
413 		  "%s: invalid access of EEPROM word %d\n",
414 		  wiphy_name(rt2x00dev->hw->wiphy), word);
415 
416 	return index;
417 }
418 
rt2800_eeprom_addr(struct rt2x00_dev * rt2x00dev,const enum rt2800_eeprom_word word)419 static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev,
420 				const enum rt2800_eeprom_word word)
421 {
422 	unsigned int index;
423 
424 	index = rt2800_eeprom_word_index(rt2x00dev, word);
425 	return rt2x00_eeprom_addr(rt2x00dev, index);
426 }
427 
rt2800_eeprom_read(struct rt2x00_dev * rt2x00dev,const enum rt2800_eeprom_word word)428 static u16 rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev,
429 			      const enum rt2800_eeprom_word word)
430 {
431 	unsigned int index;
432 
433 	index = rt2800_eeprom_word_index(rt2x00dev, word);
434 	return rt2x00_eeprom_read(rt2x00dev, index);
435 }
436 
rt2800_eeprom_write(struct rt2x00_dev * rt2x00dev,const enum rt2800_eeprom_word word,u16 data)437 static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev,
438 				const enum rt2800_eeprom_word word, u16 data)
439 {
440 	unsigned int index;
441 
442 	index = rt2800_eeprom_word_index(rt2x00dev, word);
443 	rt2x00_eeprom_write(rt2x00dev, index, data);
444 }
445 
rt2800_eeprom_read_from_array(struct rt2x00_dev * rt2x00dev,const enum rt2800_eeprom_word array,unsigned int offset)446 static u16 rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev,
447 					 const enum rt2800_eeprom_word array,
448 					 unsigned int offset)
449 {
450 	unsigned int index;
451 
452 	index = rt2800_eeprom_word_index(rt2x00dev, array);
453 	return rt2x00_eeprom_read(rt2x00dev, index + offset);
454 }
455 
rt2800_enable_wlan_rt3290(struct rt2x00_dev * rt2x00dev)456 static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
457 {
458 	u32 reg;
459 	int i, count;
460 
461 	reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
462 	rt2x00_set_field32(&reg, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff);
463 	rt2x00_set_field32(&reg, FRC_WL_ANT_SET, 1);
464 	rt2x00_set_field32(&reg, WLAN_CLK_EN, 0);
465 	rt2x00_set_field32(&reg, WLAN_EN, 1);
466 	rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
467 
468 	udelay(REGISTER_BUSY_DELAY);
469 
470 	count = 0;
471 	do {
472 		/*
473 		 * Check PLL_LD & XTAL_RDY.
474 		 */
475 		for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
476 			reg = rt2800_register_read(rt2x00dev, CMB_CTRL);
477 			if (rt2x00_get_field32(reg, PLL_LD) &&
478 			    rt2x00_get_field32(reg, XTAL_RDY))
479 				break;
480 			udelay(REGISTER_BUSY_DELAY);
481 		}
482 
483 		if (i >= REGISTER_BUSY_COUNT) {
484 
485 			if (count >= 10)
486 				return -EIO;
487 
488 			rt2800_register_write(rt2x00dev, 0x58, 0x018);
489 			udelay(REGISTER_BUSY_DELAY);
490 			rt2800_register_write(rt2x00dev, 0x58, 0x418);
491 			udelay(REGISTER_BUSY_DELAY);
492 			rt2800_register_write(rt2x00dev, 0x58, 0x618);
493 			udelay(REGISTER_BUSY_DELAY);
494 			count++;
495 		} else {
496 			count = 0;
497 		}
498 
499 		reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
500 		rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 0);
501 		rt2x00_set_field32(&reg, WLAN_CLK_EN, 1);
502 		rt2x00_set_field32(&reg, WLAN_RESET, 1);
503 		rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
504 		udelay(10);
505 		rt2x00_set_field32(&reg, WLAN_RESET, 0);
506 		rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
507 		udelay(10);
508 		rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
509 	} while (count != 0);
510 
511 	return 0;
512 }
513 
rt2800_mcu_request(struct rt2x00_dev * rt2x00dev,const u8 command,const u8 token,const u8 arg0,const u8 arg1)514 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
515 			const u8 command, const u8 token,
516 			const u8 arg0, const u8 arg1)
517 {
518 	u32 reg;
519 
520 	/*
521 	 * SOC devices don't support MCU requests.
522 	 */
523 	if (rt2x00_is_soc(rt2x00dev))
524 		return;
525 
526 	mutex_lock(&rt2x00dev->csr_mutex);
527 
528 	/*
529 	 * Wait until the MCU becomes available, afterwards we
530 	 * can safely write the new data into the register.
531 	 */
532 	if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
533 		rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
534 		rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
535 		rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
536 		rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
537 		rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
538 
539 		reg = 0;
540 		rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
541 		rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
542 	}
543 
544 	mutex_unlock(&rt2x00dev->csr_mutex);
545 }
546 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
547 
rt2800_wait_csr_ready(struct rt2x00_dev * rt2x00dev)548 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
549 {
550 	unsigned int i = 0;
551 	u32 reg;
552 
553 	for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
554 		reg = rt2800_register_read(rt2x00dev, MAC_CSR0);
555 		if (reg && reg != ~0)
556 			return 0;
557 		msleep(1);
558 	}
559 
560 	rt2x00_err(rt2x00dev, "Unstable hardware\n");
561 	return -EBUSY;
562 }
563 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
564 
rt2800_wait_wpdma_ready(struct rt2x00_dev * rt2x00dev)565 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
566 {
567 	unsigned int i;
568 	u32 reg;
569 
570 	/*
571 	 * Some devices are really slow to respond here. Wait a whole second
572 	 * before timing out.
573 	 */
574 	for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
575 		reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
576 		if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
577 		    !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
578 			return 0;
579 
580 		msleep(10);
581 	}
582 
583 	rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg);
584 	return -EACCES;
585 }
586 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
587 
rt2800_disable_wpdma(struct rt2x00_dev * rt2x00dev)588 void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
589 {
590 	u32 reg;
591 
592 	reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
593 	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
594 	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
595 	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
596 	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
597 	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
598 	rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
599 }
600 EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
601 
rt2800_get_txwi_rxwi_size(struct rt2x00_dev * rt2x00dev,unsigned short * txwi_size,unsigned short * rxwi_size)602 void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev,
603 			       unsigned short *txwi_size,
604 			       unsigned short *rxwi_size)
605 {
606 	switch (rt2x00dev->chip.rt) {
607 	case RT3593:
608 	case RT3883:
609 		*txwi_size = TXWI_DESC_SIZE_4WORDS;
610 		*rxwi_size = RXWI_DESC_SIZE_5WORDS;
611 		break;
612 
613 	case RT5592:
614 	case RT6352:
615 		*txwi_size = TXWI_DESC_SIZE_5WORDS;
616 		*rxwi_size = RXWI_DESC_SIZE_6WORDS;
617 		break;
618 
619 	default:
620 		*txwi_size = TXWI_DESC_SIZE_4WORDS;
621 		*rxwi_size = RXWI_DESC_SIZE_4WORDS;
622 		break;
623 	}
624 }
625 EXPORT_SYMBOL_GPL(rt2800_get_txwi_rxwi_size);
626 
rt2800_check_firmware_crc(const u8 * data,const size_t len)627 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
628 {
629 	u16 fw_crc;
630 	u16 crc;
631 
632 	/*
633 	 * The last 2 bytes in the firmware array are the crc checksum itself,
634 	 * this means that we should never pass those 2 bytes to the crc
635 	 * algorithm.
636 	 */
637 	fw_crc = (data[len - 2] << 8 | data[len - 1]);
638 
639 	/*
640 	 * Use the crc ccitt algorithm.
641 	 * This will return the same value as the legacy driver which
642 	 * used bit ordering reversion on the both the firmware bytes
643 	 * before input input as well as on the final output.
644 	 * Obviously using crc ccitt directly is much more efficient.
645 	 */
646 	crc = crc_ccitt(~0, data, len - 2);
647 
648 	/*
649 	 * There is a small difference between the crc-itu-t + bitrev and
650 	 * the crc-ccitt crc calculation. In the latter method the 2 bytes
651 	 * will be swapped, use swab16 to convert the crc to the correct
652 	 * value.
653 	 */
654 	crc = swab16(crc);
655 
656 	return fw_crc == crc;
657 }
658 
rt2800_check_firmware(struct rt2x00_dev * rt2x00dev,const u8 * data,const size_t len)659 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
660 			  const u8 *data, const size_t len)
661 {
662 	size_t offset = 0;
663 	size_t fw_len;
664 	bool multiple;
665 
666 	/*
667 	 * PCI(e) & SOC devices require firmware with a length
668 	 * of 8kb. USB devices require firmware files with a length
669 	 * of 4kb. Certain USB chipsets however require different firmware,
670 	 * which Ralink only provides attached to the original firmware
671 	 * file. Thus for USB devices, firmware files have a length
672 	 * which is a multiple of 4kb. The firmware for rt3290 chip also
673 	 * have a length which is a multiple of 4kb.
674 	 */
675 	if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
676 		fw_len = 4096;
677 	else
678 		fw_len = 8192;
679 
680 	multiple = true;
681 	/*
682 	 * Validate the firmware length
683 	 */
684 	if (len != fw_len && (!multiple || (len % fw_len) != 0))
685 		return FW_BAD_LENGTH;
686 
687 	/*
688 	 * Check if the chipset requires one of the upper parts
689 	 * of the firmware.
690 	 */
691 	if (rt2x00_is_usb(rt2x00dev) &&
692 	    !rt2x00_rt(rt2x00dev, RT2860) &&
693 	    !rt2x00_rt(rt2x00dev, RT2872) &&
694 	    !rt2x00_rt(rt2x00dev, RT3070) &&
695 	    ((len / fw_len) == 1))
696 		return FW_BAD_VERSION;
697 
698 	/*
699 	 * 8kb firmware files must be checked as if it were
700 	 * 2 separate firmware files.
701 	 */
702 	while (offset < len) {
703 		if (!rt2800_check_firmware_crc(data + offset, fw_len))
704 			return FW_BAD_CRC;
705 
706 		offset += fw_len;
707 	}
708 
709 	return FW_OK;
710 }
711 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
712 
rt2800_load_firmware(struct rt2x00_dev * rt2x00dev,const u8 * data,const size_t len)713 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
714 			 const u8 *data, const size_t len)
715 {
716 	unsigned int i;
717 	u32 reg;
718 	int retval;
719 
720 	if (rt2x00_rt(rt2x00dev, RT3290)) {
721 		retval = rt2800_enable_wlan_rt3290(rt2x00dev);
722 		if (retval)
723 			return -EBUSY;
724 	}
725 
726 	/*
727 	 * If driver doesn't wake up firmware here,
728 	 * rt2800_load_firmware will hang forever when interface is up again.
729 	 */
730 	rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
731 
732 	/*
733 	 * Wait for stable hardware.
734 	 */
735 	if (rt2800_wait_csr_ready(rt2x00dev))
736 		return -EBUSY;
737 
738 	if (rt2x00_is_pci(rt2x00dev)) {
739 		if (rt2x00_rt(rt2x00dev, RT3290) ||
740 		    rt2x00_rt(rt2x00dev, RT3572) ||
741 		    rt2x00_rt(rt2x00dev, RT5390) ||
742 		    rt2x00_rt(rt2x00dev, RT5392)) {
743 			reg = rt2800_register_read(rt2x00dev, AUX_CTRL);
744 			rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
745 			rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
746 			rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
747 		}
748 		rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
749 	}
750 
751 	rt2800_disable_wpdma(rt2x00dev);
752 
753 	/*
754 	 * Write firmware to the device.
755 	 */
756 	rt2800_drv_write_firmware(rt2x00dev, data, len);
757 
758 	/*
759 	 * Wait for device to stabilize.
760 	 */
761 	for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
762 		reg = rt2800_register_read(rt2x00dev, PBF_SYS_CTRL);
763 		if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
764 			break;
765 		msleep(1);
766 	}
767 
768 	if (i == REGISTER_BUSY_COUNT) {
769 		rt2x00_err(rt2x00dev, "PBF system register not ready\n");
770 		return -EBUSY;
771 	}
772 
773 	/*
774 	 * Disable DMA, will be reenabled later when enabling
775 	 * the radio.
776 	 */
777 	rt2800_disable_wpdma(rt2x00dev);
778 
779 	/*
780 	 * Initialize firmware.
781 	 */
782 	rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
783 	rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
784 	if (rt2x00_is_usb(rt2x00dev)) {
785 		rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
786 		rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
787 	}
788 	msleep(1);
789 
790 	return 0;
791 }
792 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
793 
rt2800_write_tx_data(struct queue_entry * entry,struct txentry_desc * txdesc)794 void rt2800_write_tx_data(struct queue_entry *entry,
795 			  struct txentry_desc *txdesc)
796 {
797 	__le32 *txwi = rt2800_drv_get_txwi(entry);
798 	u32 word;
799 	int i;
800 
801 	/*
802 	 * Initialize TX Info descriptor
803 	 */
804 	word = rt2x00_desc_read(txwi, 0);
805 	rt2x00_set_field32(&word, TXWI_W0_FRAG,
806 			   test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
807 	rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
808 			   test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
809 	rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
810 	rt2x00_set_field32(&word, TXWI_W0_TS,
811 			   test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
812 	rt2x00_set_field32(&word, TXWI_W0_AMPDU,
813 			   test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
814 	rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
815 			   txdesc->u.ht.mpdu_density);
816 	rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
817 	rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
818 	rt2x00_set_field32(&word, TXWI_W0_BW,
819 			   test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
820 	rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
821 			   test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
822 	rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
823 	rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
824 	rt2x00_desc_write(txwi, 0, word);
825 
826 	word = rt2x00_desc_read(txwi, 1);
827 	rt2x00_set_field32(&word, TXWI_W1_ACK,
828 			   test_bit(ENTRY_TXD_ACK, &txdesc->flags));
829 	rt2x00_set_field32(&word, TXWI_W1_NSEQ,
830 			   test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
831 	rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
832 	rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
833 			   test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
834 			   txdesc->key_idx : txdesc->u.ht.wcid);
835 	rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
836 			   txdesc->length);
837 	rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
838 	rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
839 	rt2x00_desc_write(txwi, 1, word);
840 
841 	/*
842 	 * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert
843 	 * the IV from the IVEIV register when TXD_W3_WIV is set to 0.
844 	 * When TXD_W3_WIV is set to 1 it will use the IV data
845 	 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
846 	 * crypto entry in the registers should be used to encrypt the frame.
847 	 *
848 	 * Nulify all remaining words as well, we don't know how to program them.
849 	 */
850 	for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++)
851 		_rt2x00_desc_write(txwi, i, 0);
852 }
853 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
854 
rt2800_agc_to_rssi(struct rt2x00_dev * rt2x00dev,u32 rxwi_w2)855 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
856 {
857 	s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
858 	s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
859 	s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
860 	s8 base_val = rt2x00_rt(rt2x00dev, RT6352) ? -2 : -12;
861 	u16 eeprom;
862 	u8 offset0;
863 	u8 offset1;
864 	u8 offset2;
865 
866 	if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
867 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG);
868 		offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
869 		offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
870 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2);
871 		offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
872 	} else {
873 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A);
874 		offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
875 		offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
876 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2);
877 		offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
878 	}
879 
880 	/*
881 	 * Convert the value from the descriptor into the RSSI value
882 	 * If the value in the descriptor is 0, it is considered invalid
883 	 * and the default (extremely low) rssi value is assumed
884 	 */
885 	rssi0 = (rssi0) ? (base_val - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
886 	rssi1 = (rssi1) ? (base_val - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
887 	rssi2 = (rssi2) ? (base_val - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
888 
889 	/*
890 	 * mac80211 only accepts a single RSSI value. Calculating the
891 	 * average doesn't deliver a fair answer either since -60:-60 would
892 	 * be considered equally good as -50:-70 while the second is the one
893 	 * which gives less energy...
894 	 */
895 	rssi0 = max(rssi0, rssi1);
896 	return (int)max(rssi0, rssi2);
897 }
898 
rt2800_process_rxwi(struct queue_entry * entry,struct rxdone_entry_desc * rxdesc)899 void rt2800_process_rxwi(struct queue_entry *entry,
900 			 struct rxdone_entry_desc *rxdesc)
901 {
902 	__le32 *rxwi = (__le32 *) entry->skb->data;
903 	u32 word;
904 
905 	word = rt2x00_desc_read(rxwi, 0);
906 
907 	rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
908 	rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
909 
910 	word = rt2x00_desc_read(rxwi, 1);
911 
912 	if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
913 		rxdesc->enc_flags |= RX_ENC_FLAG_SHORT_GI;
914 
915 	if (rt2x00_get_field32(word, RXWI_W1_BW))
916 		rxdesc->bw = RATE_INFO_BW_40;
917 
918 	/*
919 	 * Detect RX rate, always use MCS as signal type.
920 	 */
921 	rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
922 	rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
923 	rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
924 
925 	/*
926 	 * Mask of 0x8 bit to remove the short preamble flag.
927 	 */
928 	if (rxdesc->rate_mode == RATE_MODE_CCK)
929 		rxdesc->signal &= ~0x8;
930 
931 	word = rt2x00_desc_read(rxwi, 2);
932 
933 	/*
934 	 * Convert descriptor AGC value to RSSI value.
935 	 */
936 	rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
937 	/*
938 	 * Remove RXWI descriptor from start of the buffer.
939 	 */
940 	skb_pull(entry->skb, entry->queue->winfo_size);
941 }
942 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
943 
rt2800_rate_from_status(struct skb_frame_desc * skbdesc,u32 status,enum nl80211_band band)944 static void rt2800_rate_from_status(struct skb_frame_desc *skbdesc,
945 				    u32 status, enum nl80211_band band)
946 {
947 	u8 flags = 0;
948 	u8 idx = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
949 
950 	switch (rt2x00_get_field32(status, TX_STA_FIFO_PHYMODE)) {
951 	case RATE_MODE_HT_GREENFIELD:
952 		flags |= IEEE80211_TX_RC_GREEN_FIELD;
953 		fallthrough;
954 	case RATE_MODE_HT_MIX:
955 		flags |= IEEE80211_TX_RC_MCS;
956 		break;
957 	case RATE_MODE_OFDM:
958 		if (band == NL80211_BAND_2GHZ)
959 			idx += 4;
960 		break;
961 	case RATE_MODE_CCK:
962 		if (idx >= 8)
963 			idx -= 8;
964 		break;
965 	}
966 
967 	if (rt2x00_get_field32(status, TX_STA_FIFO_BW))
968 		flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
969 
970 	if (rt2x00_get_field32(status, TX_STA_FIFO_SGI))
971 		flags |= IEEE80211_TX_RC_SHORT_GI;
972 
973 	skbdesc->tx_rate_idx = idx;
974 	skbdesc->tx_rate_flags = flags;
975 }
976 
rt2800_txdone_entry_check(struct queue_entry * entry,u32 reg)977 static bool rt2800_txdone_entry_check(struct queue_entry *entry, u32 reg)
978 {
979 	__le32 *txwi;
980 	u32 word;
981 	int wcid, ack, pid;
982 	int tx_wcid, tx_ack, tx_pid, is_agg;
983 
984 	/*
985 	 * This frames has returned with an IO error,
986 	 * so the status report is not intended for this
987 	 * frame.
988 	 */
989 	if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags))
990 		return false;
991 
992 	wcid	= rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
993 	ack	= rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED);
994 	pid	= rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
995 	is_agg	= rt2x00_get_field32(reg, TX_STA_FIFO_TX_AGGRE);
996 
997 	/*
998 	 * Validate if this TX status report is intended for
999 	 * this entry by comparing the WCID/ACK/PID fields.
1000 	 */
1001 	txwi = rt2800_drv_get_txwi(entry);
1002 
1003 	word = rt2x00_desc_read(txwi, 1);
1004 	tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
1005 	tx_ack  = rt2x00_get_field32(word, TXWI_W1_ACK);
1006 	tx_pid  = rt2x00_get_field32(word, TXWI_W1_PACKETID);
1007 
1008 	if (wcid != tx_wcid || ack != tx_ack || (!is_agg && pid != tx_pid)) {
1009 		rt2x00_dbg(entry->queue->rt2x00dev,
1010 			   "TX status report missed for queue %d entry %d\n",
1011 			   entry->queue->qid, entry->entry_idx);
1012 		return false;
1013 	}
1014 
1015 	return true;
1016 }
1017 
rt2800_txdone_entry(struct queue_entry * entry,u32 status,__le32 * txwi,bool match)1018 void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi,
1019 			 bool match)
1020 {
1021 	struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1022 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1023 	struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1024 	struct txdone_entry_desc txdesc;
1025 	u32 word;
1026 	u16 mcs, real_mcs;
1027 	int aggr, ampdu, wcid, ack_req;
1028 
1029 	/*
1030 	 * Obtain the status about this packet.
1031 	 */
1032 	txdesc.flags = 0;
1033 	word = rt2x00_desc_read(txwi, 0);
1034 
1035 	mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
1036 	ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
1037 
1038 	real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
1039 	aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
1040 	wcid = rt2x00_get_field32(status, TX_STA_FIFO_WCID);
1041 	ack_req	= rt2x00_get_field32(status, TX_STA_FIFO_TX_ACK_REQUIRED);
1042 
1043 	/*
1044 	 * If a frame was meant to be sent as a single non-aggregated MPDU
1045 	 * but ended up in an aggregate the used tx rate doesn't correlate
1046 	 * with the one specified in the TXWI as the whole aggregate is sent
1047 	 * with the same rate.
1048 	 *
1049 	 * For example: two frames are sent to rt2x00, the first one sets
1050 	 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
1051 	 * and requests MCS15. If the hw aggregates both frames into one
1052 	 * AMDPU the tx status for both frames will contain MCS7 although
1053 	 * the frame was sent successfully.
1054 	 *
1055 	 * Hence, replace the requested rate with the real tx rate to not
1056 	 * confuse the rate control algortihm by providing clearly wrong
1057 	 * data.
1058 	 *
1059 	 * FIXME: if we do not find matching entry, we tell that frame was
1060 	 * posted without any retries. We need to find a way to fix that
1061 	 * and provide retry count.
1062 	 */
1063 	if (unlikely((aggr == 1 && ampdu == 0 && real_mcs != mcs)) || !match) {
1064 		rt2800_rate_from_status(skbdesc, status, rt2x00dev->curr_band);
1065 		mcs = real_mcs;
1066 	}
1067 
1068 	if (aggr == 1 || ampdu == 1)
1069 		__set_bit(TXDONE_AMPDU, &txdesc.flags);
1070 
1071 	if (!ack_req)
1072 		__set_bit(TXDONE_NO_ACK_REQ, &txdesc.flags);
1073 
1074 	/*
1075 	 * Ralink has a retry mechanism using a global fallback
1076 	 * table. We setup this fallback table to try the immediate
1077 	 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
1078 	 * always contains the MCS used for the last transmission, be
1079 	 * it successful or not.
1080 	 */
1081 	if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
1082 		/*
1083 		 * Transmission succeeded. The number of retries is
1084 		 * mcs - real_mcs
1085 		 */
1086 		__set_bit(TXDONE_SUCCESS, &txdesc.flags);
1087 		txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
1088 	} else {
1089 		/*
1090 		 * Transmission failed. The number of retries is
1091 		 * always 7 in this case (for a total number of 8
1092 		 * frames sent).
1093 		 */
1094 		__set_bit(TXDONE_FAILURE, &txdesc.flags);
1095 		txdesc.retry = rt2x00dev->long_retry;
1096 	}
1097 
1098 	/*
1099 	 * the frame was retried at least once
1100 	 * -> hw used fallback rates
1101 	 */
1102 	if (txdesc.retry)
1103 		__set_bit(TXDONE_FALLBACK, &txdesc.flags);
1104 
1105 	if (!match) {
1106 		/* RCU assures non-null sta will not be freed by mac80211. */
1107 		rcu_read_lock();
1108 		if (likely(wcid >= WCID_START && wcid <= WCID_END))
1109 			skbdesc->sta = drv_data->wcid_to_sta[wcid - WCID_START];
1110 		else
1111 			skbdesc->sta = NULL;
1112 		rt2x00lib_txdone_nomatch(entry, &txdesc);
1113 		rcu_read_unlock();
1114 	} else {
1115 		rt2x00lib_txdone(entry, &txdesc);
1116 	}
1117 }
1118 EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
1119 
rt2800_txdone(struct rt2x00_dev * rt2x00dev,unsigned int quota)1120 void rt2800_txdone(struct rt2x00_dev *rt2x00dev, unsigned int quota)
1121 {
1122 	struct data_queue *queue;
1123 	struct queue_entry *entry;
1124 	u32 reg;
1125 	u8 qid;
1126 	bool match;
1127 
1128 	while (quota-- > 0 && kfifo_get(&rt2x00dev->txstatus_fifo, &reg)) {
1129 		/*
1130 		 * TX_STA_FIFO_PID_QUEUE is a 2-bit field, thus qid is
1131 		 * guaranteed to be one of the TX QIDs .
1132 		 */
1133 		qid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_QUEUE);
1134 		queue = rt2x00queue_get_tx_queue(rt2x00dev, qid);
1135 
1136 		if (unlikely(rt2x00queue_empty(queue))) {
1137 			rt2x00_dbg(rt2x00dev, "Got TX status for an empty queue %u, dropping\n",
1138 				   qid);
1139 			break;
1140 		}
1141 
1142 		entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1143 
1144 		if (unlikely(test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags) ||
1145 			     !test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags))) {
1146 			rt2x00_warn(rt2x00dev, "Data pending for entry %u in queue %u\n",
1147 				    entry->entry_idx, qid);
1148 			break;
1149 		}
1150 
1151 		match = rt2800_txdone_entry_check(entry, reg);
1152 		rt2800_txdone_entry(entry, reg, rt2800_drv_get_txwi(entry), match);
1153 	}
1154 }
1155 EXPORT_SYMBOL_GPL(rt2800_txdone);
1156 
rt2800_entry_txstatus_timeout(struct rt2x00_dev * rt2x00dev,struct queue_entry * entry)1157 static inline bool rt2800_entry_txstatus_timeout(struct rt2x00_dev *rt2x00dev,
1158 						 struct queue_entry *entry)
1159 {
1160 	bool ret;
1161 	unsigned long tout;
1162 
1163 	if (!test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags))
1164 		return false;
1165 
1166 	if (test_bit(DEVICE_STATE_FLUSHING, &rt2x00dev->flags))
1167 		tout = msecs_to_jiffies(50);
1168 	else
1169 		tout = msecs_to_jiffies(2000);
1170 
1171 	ret = time_after(jiffies, entry->last_action + tout);
1172 	if (unlikely(ret))
1173 		rt2x00_dbg(entry->queue->rt2x00dev,
1174 			   "TX status timeout for entry %d in queue %d\n",
1175 			   entry->entry_idx, entry->queue->qid);
1176 	return ret;
1177 }
1178 
rt2800_txstatus_timeout(struct rt2x00_dev * rt2x00dev)1179 bool rt2800_txstatus_timeout(struct rt2x00_dev *rt2x00dev)
1180 {
1181 	struct data_queue *queue;
1182 	struct queue_entry *entry;
1183 
1184 	tx_queue_for_each(rt2x00dev, queue) {
1185 		entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1186 		if (rt2800_entry_txstatus_timeout(rt2x00dev, entry))
1187 			return true;
1188 	}
1189 
1190 	return false;
1191 }
1192 EXPORT_SYMBOL_GPL(rt2800_txstatus_timeout);
1193 
1194 /*
1195  * test if there is an entry in any TX queue for which DMA is done
1196  * but the TX status has not been returned yet
1197  */
rt2800_txstatus_pending(struct rt2x00_dev * rt2x00dev)1198 bool rt2800_txstatus_pending(struct rt2x00_dev *rt2x00dev)
1199 {
1200 	struct data_queue *queue;
1201 
1202 	tx_queue_for_each(rt2x00dev, queue) {
1203 		if (rt2x00queue_get_entry(queue, Q_INDEX_DMA_DONE) !=
1204 		    rt2x00queue_get_entry(queue, Q_INDEX_DONE))
1205 			return true;
1206 	}
1207 	return false;
1208 }
1209 EXPORT_SYMBOL_GPL(rt2800_txstatus_pending);
1210 
rt2800_txdone_nostatus(struct rt2x00_dev * rt2x00dev)1211 void rt2800_txdone_nostatus(struct rt2x00_dev *rt2x00dev)
1212 {
1213 	struct data_queue *queue;
1214 	struct queue_entry *entry;
1215 
1216 	/*
1217 	 * Process any trailing TX status reports for IO failures,
1218 	 * we loop until we find the first non-IO error entry. This
1219 	 * can either be a frame which is free, is being uploaded,
1220 	 * or has completed the upload but didn't have an entry
1221 	 * in the TX_STAT_FIFO register yet.
1222 	 */
1223 	tx_queue_for_each(rt2x00dev, queue) {
1224 		while (!rt2x00queue_empty(queue)) {
1225 			entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1226 
1227 			if (test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags) ||
1228 			    !test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags))
1229 				break;
1230 
1231 			if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags) ||
1232 			    rt2800_entry_txstatus_timeout(rt2x00dev, entry))
1233 				rt2x00lib_txdone_noinfo(entry, TXDONE_FAILURE);
1234 			else
1235 				break;
1236 		}
1237 	}
1238 }
1239 EXPORT_SYMBOL_GPL(rt2800_txdone_nostatus);
1240 
rt2800_check_hung(struct data_queue * queue)1241 static bool rt2800_check_hung(struct data_queue *queue)
1242 {
1243 	unsigned int cur_idx = rt2800_drv_get_dma_done(queue);
1244 
1245 	if (queue->wd_idx != cur_idx) {
1246 		queue->wd_idx = cur_idx;
1247 		queue->wd_count = 0;
1248 	} else
1249 		queue->wd_count++;
1250 
1251 	return queue->wd_count > 16;
1252 }
1253 
rt2800_update_survey(struct rt2x00_dev * rt2x00dev)1254 static void rt2800_update_survey(struct rt2x00_dev *rt2x00dev)
1255 {
1256 	struct ieee80211_channel *chan = rt2x00dev->hw->conf.chandef.chan;
1257 	struct rt2x00_chan_survey *chan_survey =
1258 		   &rt2x00dev->chan_survey[chan->hw_value];
1259 
1260 	chan_survey->time_idle += rt2800_register_read(rt2x00dev, CH_IDLE_STA);
1261 	chan_survey->time_busy += rt2800_register_read(rt2x00dev, CH_BUSY_STA);
1262 	chan_survey->time_ext_busy += rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC);
1263 }
1264 
rt2800_watchdog_hung(struct rt2x00_dev * rt2x00dev)1265 static bool rt2800_watchdog_hung(struct rt2x00_dev *rt2x00dev)
1266 {
1267 	struct data_queue *queue;
1268 	bool hung_tx = false;
1269 	bool hung_rx = false;
1270 
1271 	rt2800_update_survey(rt2x00dev);
1272 
1273 	queue_for_each(rt2x00dev, queue) {
1274 		switch (queue->qid) {
1275 		case QID_AC_VO:
1276 		case QID_AC_VI:
1277 		case QID_AC_BE:
1278 		case QID_AC_BK:
1279 		case QID_MGMT:
1280 			if (rt2x00queue_empty(queue))
1281 				continue;
1282 			hung_tx = hung_tx || rt2800_check_hung(queue);
1283 			break;
1284 		case QID_RX:
1285 			/* For station mode we should reactive at least
1286 			 * beacons. TODO: need to find good way detect
1287 			 * RX hung for AP mode.
1288 			 */
1289 			if (rt2x00dev->intf_sta_count == 0)
1290 				continue;
1291 			hung_rx = hung_rx || rt2800_check_hung(queue);
1292 			break;
1293 		default:
1294 			break;
1295 		}
1296 	}
1297 
1298 	if (!hung_tx && !hung_rx)
1299 		return false;
1300 
1301 	if (hung_tx)
1302 		rt2x00_warn(rt2x00dev, "Watchdog TX hung detected\n");
1303 
1304 	if (hung_rx)
1305 		rt2x00_warn(rt2x00dev, "Watchdog RX hung detected\n");
1306 
1307 	queue_for_each(rt2x00dev, queue)
1308 		queue->wd_count = 0;
1309 
1310 	return true;
1311 }
1312 
rt2800_watchdog_dma_busy(struct rt2x00_dev * rt2x00dev)1313 static bool rt2800_watchdog_dma_busy(struct rt2x00_dev *rt2x00dev)
1314 {
1315 	bool busy_rx, busy_tx;
1316 	u32 reg_cfg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
1317 	u32 reg_int = rt2800_register_read(rt2x00dev, INT_SOURCE_CSR);
1318 
1319 	if (rt2x00_get_field32(reg_cfg, WPDMA_GLO_CFG_RX_DMA_BUSY) &&
1320 	    rt2x00_get_field32(reg_int, INT_SOURCE_CSR_RX_COHERENT))
1321 		rt2x00dev->rxdma_busy++;
1322 	else
1323 		rt2x00dev->rxdma_busy = 0;
1324 
1325 	if (rt2x00_get_field32(reg_cfg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
1326 	    rt2x00_get_field32(reg_int, INT_SOURCE_CSR_TX_COHERENT))
1327 		rt2x00dev->txdma_busy++;
1328 	else
1329 		rt2x00dev->txdma_busy = 0;
1330 
1331 	busy_rx = rt2x00dev->rxdma_busy > 30;
1332 	busy_tx = rt2x00dev->txdma_busy > 30;
1333 
1334 	if (!busy_rx && !busy_tx)
1335 		return false;
1336 
1337 	if (busy_rx)
1338 		rt2x00_warn(rt2x00dev, "Watchdog RX DMA busy detected\n");
1339 
1340 	if (busy_tx)
1341 		rt2x00_warn(rt2x00dev, "Watchdog TX DMA busy detected\n");
1342 
1343 	rt2x00dev->rxdma_busy = 0;
1344 	rt2x00dev->txdma_busy = 0;
1345 
1346 	return true;
1347 }
1348 
rt2800_watchdog(struct rt2x00_dev * rt2x00dev)1349 void rt2800_watchdog(struct rt2x00_dev *rt2x00dev)
1350 {
1351 	bool reset = false;
1352 
1353 	if (test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags))
1354 		return;
1355 
1356 	if (rt2x00dev->link.watchdog & RT2800_WATCHDOG_DMA_BUSY)
1357 		reset = rt2800_watchdog_dma_busy(rt2x00dev);
1358 
1359 	if (rt2x00dev->link.watchdog & RT2800_WATCHDOG_HANG)
1360 		reset = rt2800_watchdog_hung(rt2x00dev) || reset;
1361 
1362 	if (reset)
1363 		ieee80211_restart_hw(rt2x00dev->hw);
1364 }
1365 EXPORT_SYMBOL_GPL(rt2800_watchdog);
1366 
rt2800_hw_beacon_base(struct rt2x00_dev * rt2x00dev,unsigned int index)1367 static unsigned int rt2800_hw_beacon_base(struct rt2x00_dev *rt2x00dev,
1368 					  unsigned int index)
1369 {
1370 	return HW_BEACON_BASE(index);
1371 }
1372 
rt2800_get_beacon_offset(struct rt2x00_dev * rt2x00dev,unsigned int index)1373 static inline u8 rt2800_get_beacon_offset(struct rt2x00_dev *rt2x00dev,
1374 					  unsigned int index)
1375 {
1376 	return BEACON_BASE_TO_OFFSET(rt2800_hw_beacon_base(rt2x00dev, index));
1377 }
1378 
rt2800_update_beacons_setup(struct rt2x00_dev * rt2x00dev)1379 static void rt2800_update_beacons_setup(struct rt2x00_dev *rt2x00dev)
1380 {
1381 	struct data_queue *queue = rt2x00dev->bcn;
1382 	struct queue_entry *entry;
1383 	int i, bcn_num = 0;
1384 	u64 off, reg = 0;
1385 	u32 bssid_dw1;
1386 
1387 	/*
1388 	 * Setup offsets of all active beacons in BCN_OFFSET{0,1} registers.
1389 	 */
1390 	for (i = 0; i < queue->limit; i++) {
1391 		entry = &queue->entries[i];
1392 		if (!test_bit(ENTRY_BCN_ENABLED, &entry->flags))
1393 			continue;
1394 		off = rt2800_get_beacon_offset(rt2x00dev, entry->entry_idx);
1395 		reg |= off << (8 * bcn_num);
1396 		bcn_num++;
1397 	}
1398 
1399 	rt2800_register_write(rt2x00dev, BCN_OFFSET0, (u32) reg);
1400 	rt2800_register_write(rt2x00dev, BCN_OFFSET1, (u32) (reg >> 32));
1401 
1402 	/*
1403 	 * H/W sends up to MAC_BSSID_DW1_BSS_BCN_NUM + 1 consecutive beacons.
1404 	 */
1405 	bssid_dw1 = rt2800_register_read(rt2x00dev, MAC_BSSID_DW1);
1406 	rt2x00_set_field32(&bssid_dw1, MAC_BSSID_DW1_BSS_BCN_NUM,
1407 			   bcn_num > 0 ? bcn_num - 1 : 0);
1408 	rt2800_register_write(rt2x00dev, MAC_BSSID_DW1, bssid_dw1);
1409 }
1410 
rt2800_write_beacon(struct queue_entry * entry,struct txentry_desc * txdesc)1411 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
1412 {
1413 	struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1414 	struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1415 	unsigned int beacon_base;
1416 	unsigned int padding_len;
1417 	u32 orig_reg, reg;
1418 	const int txwi_desc_size = entry->queue->winfo_size;
1419 
1420 	/*
1421 	 * Disable beaconing while we are reloading the beacon data,
1422 	 * otherwise we might be sending out invalid data.
1423 	 */
1424 	reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
1425 	orig_reg = reg;
1426 	rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1427 	rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1428 
1429 	/*
1430 	 * Add space for the TXWI in front of the skb.
1431 	 */
1432 	memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size);
1433 
1434 	/*
1435 	 * Register descriptor details in skb frame descriptor.
1436 	 */
1437 	skbdesc->flags |= SKBDESC_DESC_IN_SKB;
1438 	skbdesc->desc = entry->skb->data;
1439 	skbdesc->desc_len = txwi_desc_size;
1440 
1441 	/*
1442 	 * Add the TXWI for the beacon to the skb.
1443 	 */
1444 	rt2800_write_tx_data(entry, txdesc);
1445 
1446 	/*
1447 	 * Dump beacon to userspace through debugfs.
1448 	 */
1449 	rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry);
1450 
1451 	/*
1452 	 * Write entire beacon with TXWI and padding to register.
1453 	 */
1454 	padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
1455 	if (padding_len && skb_pad(entry->skb, padding_len)) {
1456 		rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n");
1457 		/* skb freed by skb_pad() on failure */
1458 		entry->skb = NULL;
1459 		rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1460 		return;
1461 	}
1462 
1463 	beacon_base = rt2800_hw_beacon_base(rt2x00dev, entry->entry_idx);
1464 
1465 	rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
1466 				   entry->skb->len + padding_len);
1467 	__set_bit(ENTRY_BCN_ENABLED, &entry->flags);
1468 
1469 	/*
1470 	 * Change global beacons settings.
1471 	 */
1472 	rt2800_update_beacons_setup(rt2x00dev);
1473 
1474 	/*
1475 	 * Restore beaconing state.
1476 	 */
1477 	rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1478 
1479 	/*
1480 	 * Clean up beacon skb.
1481 	 */
1482 	dev_kfree_skb_any(entry->skb);
1483 	entry->skb = NULL;
1484 }
1485 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
1486 
rt2800_clear_beacon_register(struct rt2x00_dev * rt2x00dev,unsigned int index)1487 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
1488 						unsigned int index)
1489 {
1490 	int i;
1491 	const int txwi_desc_size = rt2x00dev->bcn->winfo_size;
1492 	unsigned int beacon_base;
1493 
1494 	beacon_base = rt2800_hw_beacon_base(rt2x00dev, index);
1495 
1496 	/*
1497 	 * For the Beacon base registers we only need to clear
1498 	 * the whole TXWI which (when set to 0) will invalidate
1499 	 * the entire beacon.
1500 	 */
1501 	for (i = 0; i < txwi_desc_size; i += sizeof(__le32))
1502 		rt2800_register_write(rt2x00dev, beacon_base + i, 0);
1503 }
1504 
rt2800_clear_beacon(struct queue_entry * entry)1505 void rt2800_clear_beacon(struct queue_entry *entry)
1506 {
1507 	struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1508 	u32 orig_reg, reg;
1509 
1510 	/*
1511 	 * Disable beaconing while we are reloading the beacon data,
1512 	 * otherwise we might be sending out invalid data.
1513 	 */
1514 	orig_reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
1515 	reg = orig_reg;
1516 	rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1517 	rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1518 
1519 	/*
1520 	 * Clear beacon.
1521 	 */
1522 	rt2800_clear_beacon_register(rt2x00dev, entry->entry_idx);
1523 	__clear_bit(ENTRY_BCN_ENABLED, &entry->flags);
1524 
1525 	/*
1526 	 * Change global beacons settings.
1527 	 */
1528 	rt2800_update_beacons_setup(rt2x00dev);
1529 	/*
1530 	 * Restore beaconing state.
1531 	 */
1532 	rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1533 }
1534 EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
1535 
1536 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1537 const struct rt2x00debug rt2800_rt2x00debug = {
1538 	.owner	= THIS_MODULE,
1539 	.csr	= {
1540 		.read		= rt2800_register_read,
1541 		.write		= rt2800_register_write,
1542 		.flags		= RT2X00DEBUGFS_OFFSET,
1543 		.word_base	= CSR_REG_BASE,
1544 		.word_size	= sizeof(u32),
1545 		.word_count	= CSR_REG_SIZE / sizeof(u32),
1546 	},
1547 	.eeprom	= {
1548 		/* NOTE: The local EEPROM access functions can't
1549 		 * be used here, use the generic versions instead.
1550 		 */
1551 		.read		= rt2x00_eeprom_read,
1552 		.write		= rt2x00_eeprom_write,
1553 		.word_base	= EEPROM_BASE,
1554 		.word_size	= sizeof(u16),
1555 		.word_count	= EEPROM_SIZE / sizeof(u16),
1556 	},
1557 	.bbp	= {
1558 		.read		= rt2800_bbp_read,
1559 		.write		= rt2800_bbp_write,
1560 		.word_base	= BBP_BASE,
1561 		.word_size	= sizeof(u8),
1562 		.word_count	= BBP_SIZE / sizeof(u8),
1563 	},
1564 	.rf	= {
1565 		.read		= rt2x00_rf_read,
1566 		.write		= rt2800_rf_write,
1567 		.word_base	= RF_BASE,
1568 		.word_size	= sizeof(u32),
1569 		.word_count	= RF_SIZE / sizeof(u32),
1570 	},
1571 	.rfcsr	= {
1572 		.read		= rt2800_rfcsr_read,
1573 		.write		= rt2800_rfcsr_write,
1574 		.word_base	= RFCSR_BASE,
1575 		.word_size	= sizeof(u8),
1576 		.word_count	= RFCSR_SIZE / sizeof(u8),
1577 	},
1578 };
1579 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
1580 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1581 
rt2800_rfkill_poll(struct rt2x00_dev * rt2x00dev)1582 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
1583 {
1584 	u32 reg;
1585 
1586 	if (rt2x00_rt(rt2x00dev, RT3290)) {
1587 		reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
1588 		return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
1589 	} else {
1590 		reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
1591 		return rt2x00_get_field32(reg, GPIO_CTRL_VAL2);
1592 	}
1593 }
1594 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
1595 
1596 #ifdef CONFIG_RT2X00_LIB_LEDS
rt2800_brightness_set(struct led_classdev * led_cdev,enum led_brightness brightness)1597 static void rt2800_brightness_set(struct led_classdev *led_cdev,
1598 				  enum led_brightness brightness)
1599 {
1600 	struct rt2x00_led *led =
1601 	    container_of(led_cdev, struct rt2x00_led, led_dev);
1602 	unsigned int enabled = brightness != LED_OFF;
1603 	unsigned int bg_mode =
1604 	    (enabled && led->rt2x00dev->curr_band == NL80211_BAND_2GHZ);
1605 	unsigned int polarity =
1606 		rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1607 				   EEPROM_FREQ_LED_POLARITY);
1608 	unsigned int ledmode =
1609 		rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1610 				   EEPROM_FREQ_LED_MODE);
1611 	u32 reg;
1612 
1613 	/* Check for SoC (SOC devices don't support MCU requests) */
1614 	if (rt2x00_is_soc(led->rt2x00dev)) {
1615 		reg = rt2800_register_read(led->rt2x00dev, LED_CFG);
1616 
1617 		/* Set LED Polarity */
1618 		rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
1619 
1620 		/* Set LED Mode */
1621 		if (led->type == LED_TYPE_RADIO) {
1622 			rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
1623 					   enabled ? 3 : 0);
1624 		} else if (led->type == LED_TYPE_ASSOC) {
1625 			rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
1626 					   enabled ? 3 : 0);
1627 		} else if (led->type == LED_TYPE_QUALITY) {
1628 			rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
1629 					   enabled ? 3 : 0);
1630 		}
1631 
1632 		rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
1633 
1634 	} else {
1635 		if (led->type == LED_TYPE_RADIO) {
1636 			rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1637 					      enabled ? 0x20 : 0);
1638 		} else if (led->type == LED_TYPE_ASSOC) {
1639 			rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1640 					      enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
1641 		} else if (led->type == LED_TYPE_QUALITY) {
1642 			/*
1643 			 * The brightness is divided into 6 levels (0 - 5),
1644 			 * The specs tell us the following levels:
1645 			 *	0, 1 ,3, 7, 15, 31
1646 			 * to determine the level in a simple way we can simply
1647 			 * work with bitshifting:
1648 			 *	(1 << level) - 1
1649 			 */
1650 			rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
1651 					      (1 << brightness / (LED_FULL / 6)) - 1,
1652 					      polarity);
1653 		}
1654 	}
1655 }
1656 
rt2800_init_led(struct rt2x00_dev * rt2x00dev,struct rt2x00_led * led,enum led_type type)1657 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
1658 		     struct rt2x00_led *led, enum led_type type)
1659 {
1660 	led->rt2x00dev = rt2x00dev;
1661 	led->type = type;
1662 	led->led_dev.brightness_set = rt2800_brightness_set;
1663 	led->flags = LED_INITIALIZED;
1664 }
1665 #endif /* CONFIG_RT2X00_LIB_LEDS */
1666 
1667 /*
1668  * Configuration handlers.
1669  */
rt2800_config_wcid(struct rt2x00_dev * rt2x00dev,const u8 * address,int wcid)1670 static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
1671 			       const u8 *address,
1672 			       int wcid)
1673 {
1674 	struct mac_wcid_entry wcid_entry;
1675 	u32 offset;
1676 
1677 	offset = MAC_WCID_ENTRY(wcid);
1678 
1679 	memset(&wcid_entry, 0xff, sizeof(wcid_entry));
1680 	if (address)
1681 		memcpy(wcid_entry.mac, address, ETH_ALEN);
1682 
1683 	rt2800_register_multiwrite(rt2x00dev, offset,
1684 				      &wcid_entry, sizeof(wcid_entry));
1685 }
1686 
rt2800_delete_wcid_attr(struct rt2x00_dev * rt2x00dev,int wcid)1687 static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
1688 {
1689 	u32 offset;
1690 	offset = MAC_WCID_ATTR_ENTRY(wcid);
1691 	rt2800_register_write(rt2x00dev, offset, 0);
1692 }
1693 
rt2800_config_wcid_attr_bssidx(struct rt2x00_dev * rt2x00dev,int wcid,u32 bssidx)1694 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
1695 					   int wcid, u32 bssidx)
1696 {
1697 	u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
1698 	u32 reg;
1699 
1700 	/*
1701 	 * The BSS Idx numbers is split in a main value of 3 bits,
1702 	 * and a extended field for adding one additional bit to the value.
1703 	 */
1704 	reg = rt2800_register_read(rt2x00dev, offset);
1705 	rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
1706 	rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1707 			   (bssidx & 0x8) >> 3);
1708 	rt2800_register_write(rt2x00dev, offset, reg);
1709 }
1710 
rt2800_config_wcid_attr_cipher(struct rt2x00_dev * rt2x00dev,struct rt2x00lib_crypto * crypto,struct ieee80211_key_conf * key)1711 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
1712 					   struct rt2x00lib_crypto *crypto,
1713 					   struct ieee80211_key_conf *key)
1714 {
1715 	struct mac_iveiv_entry iveiv_entry;
1716 	u32 offset;
1717 	u32 reg;
1718 
1719 	offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1720 
1721 	if (crypto->cmd == SET_KEY) {
1722 		reg = rt2800_register_read(rt2x00dev, offset);
1723 		rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
1724 				   !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1725 		/*
1726 		 * Both the cipher as the BSS Idx numbers are split in a main
1727 		 * value of 3 bits, and a extended field for adding one additional
1728 		 * bit to the value.
1729 		 */
1730 		rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1731 				   (crypto->cipher & 0x7));
1732 		rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1733 				   (crypto->cipher & 0x8) >> 3);
1734 		rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1735 		rt2800_register_write(rt2x00dev, offset, reg);
1736 	} else {
1737 		/* Delete the cipher without touching the bssidx */
1738 		reg = rt2800_register_read(rt2x00dev, offset);
1739 		rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
1740 		rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
1741 		rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
1742 		rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
1743 		rt2800_register_write(rt2x00dev, offset, reg);
1744 	}
1745 
1746 	if (test_bit(DEVICE_STATE_RESET, &rt2x00dev->flags))
1747 		return;
1748 
1749 	offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1750 
1751 	memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1752 	if ((crypto->cipher == CIPHER_TKIP) ||
1753 	    (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1754 	    (crypto->cipher == CIPHER_AES))
1755 		iveiv_entry.iv[3] |= 0x20;
1756 	iveiv_entry.iv[3] |= key->keyidx << 6;
1757 	rt2800_register_multiwrite(rt2x00dev, offset,
1758 				   &iveiv_entry, sizeof(iveiv_entry));
1759 }
1760 
rt2800_config_shared_key(struct rt2x00_dev * rt2x00dev,struct rt2x00lib_crypto * crypto,struct ieee80211_key_conf * key)1761 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1762 			     struct rt2x00lib_crypto *crypto,
1763 			     struct ieee80211_key_conf *key)
1764 {
1765 	struct hw_key_entry key_entry;
1766 	struct rt2x00_field32 field;
1767 	u32 offset;
1768 	u32 reg;
1769 
1770 	if (crypto->cmd == SET_KEY) {
1771 		key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1772 
1773 		memcpy(key_entry.key, crypto->key,
1774 		       sizeof(key_entry.key));
1775 		memcpy(key_entry.tx_mic, crypto->tx_mic,
1776 		       sizeof(key_entry.tx_mic));
1777 		memcpy(key_entry.rx_mic, crypto->rx_mic,
1778 		       sizeof(key_entry.rx_mic));
1779 
1780 		offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1781 		rt2800_register_multiwrite(rt2x00dev, offset,
1782 					      &key_entry, sizeof(key_entry));
1783 	}
1784 
1785 	/*
1786 	 * The cipher types are stored over multiple registers
1787 	 * starting with SHARED_KEY_MODE_BASE each word will have
1788 	 * 32 bits and contains the cipher types for 2 bssidx each.
1789 	 * Using the correct defines correctly will cause overhead,
1790 	 * so just calculate the correct offset.
1791 	 */
1792 	field.bit_offset = 4 * (key->hw_key_idx % 8);
1793 	field.bit_mask = 0x7 << field.bit_offset;
1794 
1795 	offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1796 
1797 	reg = rt2800_register_read(rt2x00dev, offset);
1798 	rt2x00_set_field32(&reg, field,
1799 			   (crypto->cmd == SET_KEY) * crypto->cipher);
1800 	rt2800_register_write(rt2x00dev, offset, reg);
1801 
1802 	/*
1803 	 * Update WCID information
1804 	 */
1805 	rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1806 	rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1807 				       crypto->bssidx);
1808 	rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1809 
1810 	return 0;
1811 }
1812 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1813 
rt2800_config_pairwise_key(struct rt2x00_dev * rt2x00dev,struct rt2x00lib_crypto * crypto,struct ieee80211_key_conf * key)1814 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1815 			       struct rt2x00lib_crypto *crypto,
1816 			       struct ieee80211_key_conf *key)
1817 {
1818 	struct hw_key_entry key_entry;
1819 	u32 offset;
1820 
1821 	if (crypto->cmd == SET_KEY) {
1822 		/*
1823 		 * Allow key configuration only for STAs that are
1824 		 * known by the hw.
1825 		 */
1826 		if (crypto->wcid > WCID_END)
1827 			return -ENOSPC;
1828 		key->hw_key_idx = crypto->wcid;
1829 
1830 		memcpy(key_entry.key, crypto->key,
1831 		       sizeof(key_entry.key));
1832 		memcpy(key_entry.tx_mic, crypto->tx_mic,
1833 		       sizeof(key_entry.tx_mic));
1834 		memcpy(key_entry.rx_mic, crypto->rx_mic,
1835 		       sizeof(key_entry.rx_mic));
1836 
1837 		offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1838 		rt2800_register_multiwrite(rt2x00dev, offset,
1839 					      &key_entry, sizeof(key_entry));
1840 	}
1841 
1842 	/*
1843 	 * Update WCID information
1844 	 */
1845 	rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1846 
1847 	return 0;
1848 }
1849 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1850 
rt2800_set_max_psdu_len(struct rt2x00_dev * rt2x00dev)1851 static void rt2800_set_max_psdu_len(struct rt2x00_dev *rt2x00dev)
1852 {
1853 	u8 i, max_psdu;
1854 	u32 reg;
1855 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1856 
1857 	for (i = 0; i < 3; i++)
1858 		if (drv_data->ampdu_factor_cnt[i] > 0)
1859 			break;
1860 
1861 	max_psdu = min(drv_data->max_psdu, i);
1862 
1863 	reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG);
1864 	rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, max_psdu);
1865 	rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1866 }
1867 
rt2800_sta_add(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_sta * sta)1868 int rt2800_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1869 		   struct ieee80211_sta *sta)
1870 {
1871 	struct rt2x00_dev *rt2x00dev = hw->priv;
1872 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1873 	struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1874 	int wcid;
1875 
1876 	/*
1877 	 * Limit global maximum TX AMPDU length to smallest value of all
1878 	 * connected stations. In AP mode this can be suboptimal, but we
1879 	 * do not have a choice if some connected STA is not capable to
1880 	 * receive the same amount of data like the others.
1881 	 */
1882 	if (sta->deflink.ht_cap.ht_supported) {
1883 		drv_data->ampdu_factor_cnt[sta->deflink.ht_cap.ampdu_factor & 3]++;
1884 		rt2800_set_max_psdu_len(rt2x00dev);
1885 	}
1886 
1887 	/*
1888 	 * Search for the first free WCID entry and return the corresponding
1889 	 * index.
1890 	 */
1891 	wcid = find_first_zero_bit(drv_data->sta_ids, STA_IDS_SIZE) + WCID_START;
1892 
1893 	/*
1894 	 * Store selected wcid even if it is invalid so that we can
1895 	 * later decide if the STA is uploaded into the hw.
1896 	 */
1897 	sta_priv->wcid = wcid;
1898 
1899 	/*
1900 	 * No space left in the device, however, we can still communicate
1901 	 * with the STA -> No error.
1902 	 */
1903 	if (wcid > WCID_END)
1904 		return 0;
1905 
1906 	__set_bit(wcid - WCID_START, drv_data->sta_ids);
1907 	drv_data->wcid_to_sta[wcid - WCID_START] = sta;
1908 
1909 	/*
1910 	 * Clean up WCID attributes and write STA address to the device.
1911 	 */
1912 	rt2800_delete_wcid_attr(rt2x00dev, wcid);
1913 	rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1914 	rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1915 				       rt2x00lib_get_bssidx(rt2x00dev, vif));
1916 	return 0;
1917 }
1918 EXPORT_SYMBOL_GPL(rt2800_sta_add);
1919 
rt2800_sta_remove(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_sta * sta)1920 int rt2800_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1921 		      struct ieee80211_sta *sta)
1922 {
1923 	struct rt2x00_dev *rt2x00dev = hw->priv;
1924 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1925 	struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1926 	int wcid = sta_priv->wcid;
1927 
1928 	if (sta->deflink.ht_cap.ht_supported) {
1929 		drv_data->ampdu_factor_cnt[sta->deflink.ht_cap.ampdu_factor & 3]--;
1930 		rt2800_set_max_psdu_len(rt2x00dev);
1931 	}
1932 
1933 	if (wcid > WCID_END)
1934 		return 0;
1935 	/*
1936 	 * Remove WCID entry, no need to clean the attributes as they will
1937 	 * get renewed when the WCID is reused.
1938 	 */
1939 	rt2800_config_wcid(rt2x00dev, NULL, wcid);
1940 	drv_data->wcid_to_sta[wcid - WCID_START] = NULL;
1941 	__clear_bit(wcid - WCID_START, drv_data->sta_ids);
1942 
1943 	return 0;
1944 }
1945 EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1946 
rt2800_pre_reset_hw(struct rt2x00_dev * rt2x00dev)1947 void rt2800_pre_reset_hw(struct rt2x00_dev *rt2x00dev)
1948 {
1949 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1950 	struct data_queue *queue = rt2x00dev->bcn;
1951 	struct queue_entry *entry;
1952 	int i, wcid;
1953 
1954 	for (wcid = WCID_START; wcid < WCID_END; wcid++) {
1955 		drv_data->wcid_to_sta[wcid - WCID_START] = NULL;
1956 		__clear_bit(wcid - WCID_START, drv_data->sta_ids);
1957 	}
1958 
1959 	for (i = 0; i < queue->limit; i++) {
1960 		entry = &queue->entries[i];
1961 		clear_bit(ENTRY_BCN_ASSIGNED, &entry->flags);
1962 	}
1963 }
1964 EXPORT_SYMBOL_GPL(rt2800_pre_reset_hw);
1965 
rt2800_config_filter(struct rt2x00_dev * rt2x00dev,const unsigned int filter_flags)1966 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1967 			  const unsigned int filter_flags)
1968 {
1969 	u32 reg;
1970 
1971 	/*
1972 	 * Start configuration steps.
1973 	 * Note that the version error will always be dropped
1974 	 * and broadcast frames will always be accepted since
1975 	 * there is no filter for it at this time.
1976 	 */
1977 	reg = rt2800_register_read(rt2x00dev, RX_FILTER_CFG);
1978 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1979 			   !(filter_flags & FIF_FCSFAIL));
1980 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1981 			   !(filter_flags & FIF_PLCPFAIL));
1982 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1983 			   !test_bit(CONFIG_MONITORING, &rt2x00dev->flags));
1984 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1985 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1986 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1987 			   !(filter_flags & FIF_ALLMULTI));
1988 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1989 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1990 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1991 			   !(filter_flags & FIF_CONTROL));
1992 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1993 			   !(filter_flags & FIF_CONTROL));
1994 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1995 			   !(filter_flags & FIF_CONTROL));
1996 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1997 			   !(filter_flags & FIF_CONTROL));
1998 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1999 			   !(filter_flags & FIF_CONTROL));
2000 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
2001 			   !(filter_flags & FIF_PSPOLL));
2002 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 0);
2003 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
2004 			   !(filter_flags & FIF_CONTROL));
2005 	rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
2006 			   !(filter_flags & FIF_CONTROL));
2007 	rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
2008 }
2009 EXPORT_SYMBOL_GPL(rt2800_config_filter);
2010 
rt2800_config_intf(struct rt2x00_dev * rt2x00dev,struct rt2x00_intf * intf,struct rt2x00intf_conf * conf,const unsigned int flags)2011 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
2012 			struct rt2x00intf_conf *conf, const unsigned int flags)
2013 {
2014 	u32 reg;
2015 	bool update_bssid = false;
2016 
2017 	if (flags & CONFIG_UPDATE_TYPE) {
2018 		/*
2019 		 * Enable synchronisation.
2020 		 */
2021 		reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
2022 		rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
2023 		rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2024 
2025 		if (conf->sync == TSF_SYNC_AP_NONE) {
2026 			/*
2027 			 * Tune beacon queue transmit parameters for AP mode
2028 			 */
2029 			reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG);
2030 			rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
2031 			rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
2032 			rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
2033 			rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
2034 			rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
2035 		} else {
2036 			reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG);
2037 			rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
2038 			rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
2039 			rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
2040 			rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
2041 			rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
2042 		}
2043 	}
2044 
2045 	if (flags & CONFIG_UPDATE_MAC) {
2046 		if (flags & CONFIG_UPDATE_TYPE &&
2047 		    conf->sync == TSF_SYNC_AP_NONE) {
2048 			/*
2049 			 * The BSSID register has to be set to our own mac
2050 			 * address in AP mode.
2051 			 */
2052 			memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
2053 			update_bssid = true;
2054 		}
2055 
2056 		if (!is_zero_ether_addr((const u8 *)conf->mac)) {
2057 			reg = le32_to_cpu(conf->mac[1]);
2058 			rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
2059 			conf->mac[1] = cpu_to_le32(reg);
2060 		}
2061 
2062 		rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
2063 					      conf->mac, sizeof(conf->mac));
2064 	}
2065 
2066 	if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
2067 		if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
2068 			reg = le32_to_cpu(conf->bssid[1]);
2069 			rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
2070 			rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
2071 			conf->bssid[1] = cpu_to_le32(reg);
2072 		}
2073 
2074 		rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
2075 					      conf->bssid, sizeof(conf->bssid));
2076 	}
2077 }
2078 EXPORT_SYMBOL_GPL(rt2800_config_intf);
2079 
rt2800_config_ht_opmode(struct rt2x00_dev * rt2x00dev,struct rt2x00lib_erp * erp)2080 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
2081 				    struct rt2x00lib_erp *erp)
2082 {
2083 	bool any_sta_nongf = !!(erp->ht_opmode &
2084 				IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
2085 	u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
2086 	u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
2087 	u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
2088 	u32 reg;
2089 
2090 	/* default protection rate for HT20: OFDM 24M */
2091 	mm20_rate = gf20_rate = 0x4004;
2092 
2093 	/* default protection rate for HT40: duplicate OFDM 24M */
2094 	mm40_rate = gf40_rate = 0x4084;
2095 
2096 	switch (protection) {
2097 	case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
2098 		/*
2099 		 * All STAs in this BSS are HT20/40 but there might be
2100 		 * STAs not supporting greenfield mode.
2101 		 * => Disable protection for HT transmissions.
2102 		 */
2103 		mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
2104 
2105 		break;
2106 	case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2107 		/*
2108 		 * All STAs in this BSS are HT20 or HT20/40 but there
2109 		 * might be STAs not supporting greenfield mode.
2110 		 * => Protect all HT40 transmissions.
2111 		 */
2112 		mm20_mode = gf20_mode = 0;
2113 		mm40_mode = gf40_mode = 1;
2114 
2115 		break;
2116 	case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
2117 		/*
2118 		 * Nonmember protection:
2119 		 * According to 802.11n we _should_ protect all
2120 		 * HT transmissions (but we don't have to).
2121 		 *
2122 		 * But if cts_protection is enabled we _shall_ protect
2123 		 * all HT transmissions using a CCK rate.
2124 		 *
2125 		 * And if any station is non GF we _shall_ protect
2126 		 * GF transmissions.
2127 		 *
2128 		 * We decide to protect everything
2129 		 * -> fall through to mixed mode.
2130 		 */
2131 	case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2132 		/*
2133 		 * Legacy STAs are present
2134 		 * => Protect all HT transmissions.
2135 		 */
2136 		mm20_mode = mm40_mode = gf20_mode = gf40_mode = 1;
2137 
2138 		/*
2139 		 * If erp protection is needed we have to protect HT
2140 		 * transmissions with CCK 11M long preamble.
2141 		 */
2142 		if (erp->cts_protection) {
2143 			/* don't duplicate RTS/CTS in CCK mode */
2144 			mm20_rate = mm40_rate = 0x0003;
2145 			gf20_rate = gf40_rate = 0x0003;
2146 		}
2147 		break;
2148 	}
2149 
2150 	/* check for STAs not supporting greenfield mode */
2151 	if (any_sta_nongf)
2152 		gf20_mode = gf40_mode = 1;
2153 
2154 	/* Update HT protection config */
2155 	reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG);
2156 	rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
2157 	rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
2158 	rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2159 
2160 	reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG);
2161 	rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
2162 	rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
2163 	rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2164 
2165 	reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG);
2166 	rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
2167 	rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
2168 	rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2169 
2170 	reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG);
2171 	rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
2172 	rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
2173 	rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2174 }
2175 
rt2800_config_erp(struct rt2x00_dev * rt2x00dev,struct rt2x00lib_erp * erp,u32 changed)2176 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
2177 		       u32 changed)
2178 {
2179 	u32 reg;
2180 
2181 	if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2182 		reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG);
2183 		rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
2184 				   !!erp->short_preamble);
2185 		rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
2186 	}
2187 
2188 	if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2189 		reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG);
2190 		rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
2191 				   erp->cts_protection ? 2 : 0);
2192 		rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2193 	}
2194 
2195 	if (changed & BSS_CHANGED_BASIC_RATES) {
2196 		rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
2197 				      0xff0 | erp->basic_rates);
2198 		rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
2199 	}
2200 
2201 	if (changed & BSS_CHANGED_ERP_SLOT) {
2202 		reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG);
2203 		rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
2204 				   erp->slot_time);
2205 		rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
2206 
2207 		reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG);
2208 		rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
2209 		rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
2210 	}
2211 
2212 	if (changed & BSS_CHANGED_BEACON_INT) {
2213 		reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
2214 		rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
2215 				   erp->beacon_int * 16);
2216 		rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2217 	}
2218 
2219 	if (changed & BSS_CHANGED_HT)
2220 		rt2800_config_ht_opmode(rt2x00dev, erp);
2221 }
2222 EXPORT_SYMBOL_GPL(rt2800_config_erp);
2223 
rt2800_wait_bbp_rf_ready(struct rt2x00_dev * rt2x00dev,const struct rt2x00_field32 mask)2224 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev,
2225 				    const struct rt2x00_field32 mask)
2226 {
2227 	unsigned int i;
2228 	u32 reg;
2229 
2230 	for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2231 		reg = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG);
2232 		if (!rt2x00_get_field32(reg, mask))
2233 			return 0;
2234 
2235 		udelay(REGISTER_BUSY_DELAY);
2236 	}
2237 
2238 	rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n");
2239 	return -EACCES;
2240 }
2241 
rt2800_wait_bbp_ready(struct rt2x00_dev * rt2x00dev)2242 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
2243 {
2244 	unsigned int i;
2245 	u8 value;
2246 
2247 	/*
2248 	 * BBP was enabled after firmware was loaded,
2249 	 * but we need to reactivate it now.
2250 	 */
2251 	rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
2252 	rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
2253 	msleep(1);
2254 
2255 	for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2256 		value = rt2800_bbp_read(rt2x00dev, 0);
2257 		if ((value != 0xff) && (value != 0x00))
2258 			return 0;
2259 		udelay(REGISTER_BUSY_DELAY);
2260 	}
2261 
2262 	rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
2263 	return -EACCES;
2264 }
2265 
rt2800_config_3572bt_ant(struct rt2x00_dev * rt2x00dev)2266 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
2267 {
2268 	u32 reg;
2269 	u16 eeprom;
2270 	u8 led_ctrl, led_g_mode, led_r_mode;
2271 
2272 	reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
2273 	if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) {
2274 		rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
2275 		rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
2276 	} else {
2277 		rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
2278 		rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
2279 	}
2280 	rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
2281 
2282 	reg = rt2800_register_read(rt2x00dev, LED_CFG);
2283 	led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
2284 	led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
2285 	if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
2286 	    led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
2287 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ);
2288 		led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
2289 		if (led_ctrl == 0 || led_ctrl > 0x40) {
2290 			rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
2291 			rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
2292 			rt2800_register_write(rt2x00dev, LED_CFG, reg);
2293 		} else {
2294 			rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
2295 					   (led_g_mode << 2) | led_r_mode, 1);
2296 		}
2297 	}
2298 }
2299 
rt2800_set_ant_diversity(struct rt2x00_dev * rt2x00dev,enum antenna ant)2300 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
2301 				     enum antenna ant)
2302 {
2303 	u32 reg;
2304 	u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
2305 	u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
2306 
2307 	if (rt2x00_is_pci(rt2x00dev)) {
2308 		reg = rt2800_register_read(rt2x00dev, E2PROM_CSR);
2309 		rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
2310 		rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
2311 	} else if (rt2x00_is_usb(rt2x00dev))
2312 		rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
2313 				   eesk_pin, 0);
2314 
2315 	reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
2316 	rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
2317 	rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, gpio_bit3);
2318 	rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
2319 }
2320 
rt2800_config_ant(struct rt2x00_dev * rt2x00dev,struct antenna_setup * ant)2321 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
2322 {
2323 	u8 r1;
2324 	u8 r3;
2325 	u16 eeprom;
2326 
2327 	r1 = rt2800_bbp_read(rt2x00dev, 1);
2328 	r3 = rt2800_bbp_read(rt2x00dev, 3);
2329 
2330 	if (rt2x00_rt(rt2x00dev, RT3572) &&
2331 	    rt2x00_has_cap_bt_coexist(rt2x00dev))
2332 		rt2800_config_3572bt_ant(rt2x00dev);
2333 
2334 	/*
2335 	 * Configure the TX antenna.
2336 	 */
2337 	switch (ant->tx_chain_num) {
2338 	case 1:
2339 		rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
2340 		break;
2341 	case 2:
2342 		if (rt2x00_rt(rt2x00dev, RT3572) &&
2343 		    rt2x00_has_cap_bt_coexist(rt2x00dev))
2344 			rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
2345 		else
2346 			rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
2347 		break;
2348 	case 3:
2349 		rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
2350 		break;
2351 	}
2352 
2353 	/*
2354 	 * Configure the RX antenna.
2355 	 */
2356 	switch (ant->rx_chain_num) {
2357 	case 1:
2358 		if (rt2x00_rt(rt2x00dev, RT3070) ||
2359 		    rt2x00_rt(rt2x00dev, RT3090) ||
2360 		    rt2x00_rt(rt2x00dev, RT3352) ||
2361 		    rt2x00_rt(rt2x00dev, RT3390)) {
2362 			eeprom = rt2800_eeprom_read(rt2x00dev,
2363 						    EEPROM_NIC_CONF1);
2364 			if (rt2x00_get_field16(eeprom,
2365 						EEPROM_NIC_CONF1_ANT_DIVERSITY))
2366 				rt2800_set_ant_diversity(rt2x00dev,
2367 						rt2x00dev->default_ant.rx);
2368 		}
2369 		rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
2370 		break;
2371 	case 2:
2372 		if (rt2x00_rt(rt2x00dev, RT3572) &&
2373 		    rt2x00_has_cap_bt_coexist(rt2x00dev)) {
2374 			rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
2375 			rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
2376 				rt2x00dev->curr_band == NL80211_BAND_5GHZ);
2377 			rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
2378 		} else {
2379 			rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
2380 		}
2381 		break;
2382 	case 3:
2383 		rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
2384 		break;
2385 	}
2386 
2387 	rt2800_bbp_write(rt2x00dev, 3, r3);
2388 	rt2800_bbp_write(rt2x00dev, 1, r1);
2389 
2390 	if (rt2x00_rt(rt2x00dev, RT3593) ||
2391 	    rt2x00_rt(rt2x00dev, RT3883)) {
2392 		if (ant->rx_chain_num == 1)
2393 			rt2800_bbp_write(rt2x00dev, 86, 0x00);
2394 		else
2395 			rt2800_bbp_write(rt2x00dev, 86, 0x46);
2396 	}
2397 }
2398 EXPORT_SYMBOL_GPL(rt2800_config_ant);
2399 
rt2800_config_lna_gain(struct rt2x00_dev * rt2x00dev,struct rt2x00lib_conf * libconf)2400 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
2401 				   struct rt2x00lib_conf *libconf)
2402 {
2403 	u16 eeprom;
2404 	short lna_gain;
2405 
2406 	if (libconf->rf.channel <= 14) {
2407 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA);
2408 		lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
2409 	} else if (libconf->rf.channel <= 64) {
2410 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA);
2411 		lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
2412 	} else if (libconf->rf.channel <= 128) {
2413 		if (rt2x00_rt(rt2x00dev, RT3593) ||
2414 		    rt2x00_rt(rt2x00dev, RT3883)) {
2415 			eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2);
2416 			lna_gain = rt2x00_get_field16(eeprom,
2417 						      EEPROM_EXT_LNA2_A1);
2418 		} else {
2419 			eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2);
2420 			lna_gain = rt2x00_get_field16(eeprom,
2421 						      EEPROM_RSSI_BG2_LNA_A1);
2422 		}
2423 	} else {
2424 		if (rt2x00_rt(rt2x00dev, RT3593) ||
2425 		    rt2x00_rt(rt2x00dev, RT3883)) {
2426 			eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2);
2427 			lna_gain = rt2x00_get_field16(eeprom,
2428 						      EEPROM_EXT_LNA2_A2);
2429 		} else {
2430 			eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2);
2431 			lna_gain = rt2x00_get_field16(eeprom,
2432 						      EEPROM_RSSI_A2_LNA_A2);
2433 		}
2434 	}
2435 
2436 	rt2x00dev->lna_gain = lna_gain;
2437 }
2438 
rt2800_clk_is_20mhz(struct rt2x00_dev * rt2x00dev)2439 static inline bool rt2800_clk_is_20mhz(struct rt2x00_dev *rt2x00dev)
2440 {
2441 	return clk_get_rate(rt2x00dev->clk) == 20000000;
2442 }
2443 
2444 #define FREQ_OFFSET_BOUND	0x5f
2445 
rt2800_freq_cal_mode1(struct rt2x00_dev * rt2x00dev)2446 static void rt2800_freq_cal_mode1(struct rt2x00_dev *rt2x00dev)
2447 {
2448 	u8 freq_offset, prev_freq_offset;
2449 	u8 rfcsr, prev_rfcsr;
2450 
2451 	freq_offset = rt2x00_get_field8(rt2x00dev->freq_offset, RFCSR17_CODE);
2452 	freq_offset = min_t(u8, freq_offset, FREQ_OFFSET_BOUND);
2453 
2454 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 17);
2455 	prev_rfcsr = rfcsr;
2456 
2457 	rt2x00_set_field8(&rfcsr, RFCSR17_CODE, freq_offset);
2458 	if (rfcsr == prev_rfcsr)
2459 		return;
2460 
2461 	if (rt2x00_is_usb(rt2x00dev)) {
2462 		rt2800_mcu_request(rt2x00dev, MCU_FREQ_OFFSET, 0xff,
2463 				   freq_offset, prev_rfcsr);
2464 		return;
2465 	}
2466 
2467 	prev_freq_offset = rt2x00_get_field8(prev_rfcsr, RFCSR17_CODE);
2468 	while (prev_freq_offset != freq_offset) {
2469 		if (prev_freq_offset < freq_offset)
2470 			prev_freq_offset++;
2471 		else
2472 			prev_freq_offset--;
2473 
2474 		rt2x00_set_field8(&rfcsr, RFCSR17_CODE, prev_freq_offset);
2475 		rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2476 
2477 		usleep_range(1000, 1500);
2478 	}
2479 }
2480 
rt2800_config_channel_rf2xxx(struct rt2x00_dev * rt2x00dev,struct ieee80211_conf * conf,struct rf_channel * rf,struct channel_info * info)2481 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
2482 					 struct ieee80211_conf *conf,
2483 					 struct rf_channel *rf,
2484 					 struct channel_info *info)
2485 {
2486 	rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
2487 
2488 	if (rt2x00dev->default_ant.tx_chain_num == 1)
2489 		rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
2490 
2491 	if (rt2x00dev->default_ant.rx_chain_num == 1) {
2492 		rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
2493 		rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
2494 	} else if (rt2x00dev->default_ant.rx_chain_num == 2)
2495 		rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
2496 
2497 	if (rf->channel > 14) {
2498 		/*
2499 		 * When TX power is below 0, we should increase it by 7 to
2500 		 * make it a positive value (Minimum value is -7).
2501 		 * However this means that values between 0 and 7 have
2502 		 * double meaning, and we should set a 7DBm boost flag.
2503 		 */
2504 		rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
2505 				   (info->default_power1 >= 0));
2506 
2507 		if (info->default_power1 < 0)
2508 			info->default_power1 += 7;
2509 
2510 		rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
2511 
2512 		rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
2513 				   (info->default_power2 >= 0));
2514 
2515 		if (info->default_power2 < 0)
2516 			info->default_power2 += 7;
2517 
2518 		rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
2519 	} else {
2520 		rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
2521 		rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
2522 	}
2523 
2524 	rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
2525 
2526 	rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2527 	rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2528 	rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
2529 	rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2530 
2531 	udelay(200);
2532 
2533 	rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2534 	rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2535 	rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
2536 	rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2537 
2538 	udelay(200);
2539 
2540 	rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2541 	rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2542 	rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
2543 	rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2544 }
2545 
rt2800_config_channel_rf3xxx(struct rt2x00_dev * rt2x00dev,struct ieee80211_conf * conf,struct rf_channel * rf,struct channel_info * info)2546 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
2547 					 struct ieee80211_conf *conf,
2548 					 struct rf_channel *rf,
2549 					 struct channel_info *info)
2550 {
2551 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2552 	u8 rfcsr, calib_tx, calib_rx;
2553 
2554 	rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2555 
2556 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
2557 	rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
2558 	rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2559 
2560 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
2561 	rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
2562 	rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2563 
2564 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 12);
2565 	rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
2566 	rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2567 
2568 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 13);
2569 	rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
2570 	rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2571 
2572 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2573 	rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2574 	rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2575 			  rt2x00dev->default_ant.rx_chain_num <= 1);
2576 	rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD,
2577 			  rt2x00dev->default_ant.rx_chain_num <= 2);
2578 	rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2579 	rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2580 			  rt2x00dev->default_ant.tx_chain_num <= 1);
2581 	rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD,
2582 			  rt2x00dev->default_ant.tx_chain_num <= 2);
2583 	rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2584 
2585 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 23);
2586 	rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2587 	rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2588 
2589 	if (rt2x00_rt(rt2x00dev, RT3390)) {
2590 		calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
2591 		calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
2592 	} else {
2593 		if (conf_is_ht40(conf)) {
2594 			calib_tx = drv_data->calibration_bw40;
2595 			calib_rx = drv_data->calibration_bw40;
2596 		} else {
2597 			calib_tx = drv_data->calibration_bw20;
2598 			calib_rx = drv_data->calibration_bw20;
2599 		}
2600 	}
2601 
2602 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 24);
2603 	rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
2604 	rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
2605 
2606 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 31);
2607 	rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
2608 	rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2609 
2610 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
2611 	rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2612 	rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2613 
2614 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
2615 	rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2616 	rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2617 
2618 	usleep_range(1000, 1500);
2619 
2620 	rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2621 	rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2622 }
2623 
rt2800_config_channel_rf3052(struct rt2x00_dev * rt2x00dev,struct ieee80211_conf * conf,struct rf_channel * rf,struct channel_info * info)2624 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
2625 					 struct ieee80211_conf *conf,
2626 					 struct rf_channel *rf,
2627 					 struct channel_info *info)
2628 {
2629 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2630 	u8 rfcsr;
2631 	u32 reg;
2632 
2633 	if (rf->channel <= 14) {
2634 		rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2635 		rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2636 	} else {
2637 		rt2800_bbp_write(rt2x00dev, 25, 0x09);
2638 		rt2800_bbp_write(rt2x00dev, 26, 0xff);
2639 	}
2640 
2641 	rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2642 	rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
2643 
2644 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
2645 	rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
2646 	if (rf->channel <= 14)
2647 		rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
2648 	else
2649 		rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
2650 	rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2651 
2652 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 5);
2653 	if (rf->channel <= 14)
2654 		rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
2655 	else
2656 		rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
2657 	rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
2658 
2659 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 12);
2660 	if (rf->channel <= 14) {
2661 		rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
2662 		rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2663 				  info->default_power1);
2664 	} else {
2665 		rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
2666 		rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2667 				(info->default_power1 & 0x3) |
2668 				((info->default_power1 & 0xC) << 1));
2669 	}
2670 	rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2671 
2672 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 13);
2673 	if (rf->channel <= 14) {
2674 		rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
2675 		rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2676 				  info->default_power2);
2677 	} else {
2678 		rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
2679 		rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2680 				(info->default_power2 & 0x3) |
2681 				((info->default_power2 & 0xC) << 1));
2682 	}
2683 	rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2684 
2685 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2686 	rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2687 	rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2688 	rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2689 	rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2690 	rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2691 	rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2692 	if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
2693 		if (rf->channel <= 14) {
2694 			rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2695 			rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2696 		}
2697 		rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2698 		rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2699 	} else {
2700 		switch (rt2x00dev->default_ant.tx_chain_num) {
2701 		case 1:
2702 			rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2703 			fallthrough;
2704 		case 2:
2705 			rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2706 			break;
2707 		}
2708 
2709 		switch (rt2x00dev->default_ant.rx_chain_num) {
2710 		case 1:
2711 			rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2712 			fallthrough;
2713 		case 2:
2714 			rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2715 			break;
2716 		}
2717 	}
2718 	rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2719 
2720 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 23);
2721 	rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2722 	rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2723 
2724 	if (conf_is_ht40(conf)) {
2725 		rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
2726 		rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
2727 	} else {
2728 		rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
2729 		rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
2730 	}
2731 
2732 	if (rf->channel <= 14) {
2733 		rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
2734 		rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
2735 		rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2736 		rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
2737 		rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
2738 		rfcsr = 0x4c;
2739 		rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2740 				  drv_data->txmixer_gain_24g);
2741 		rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
2742 		rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2743 		rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
2744 		rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
2745 		rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
2746 		rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2747 		rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2748 		rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
2749 	} else {
2750 		rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
2751 		rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
2752 		rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
2753 		rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
2754 		rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
2755 		rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2756 		rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2757 		rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2758 		rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
2759 		rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
2760 		rfcsr = 0x7a;
2761 		rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2762 				  drv_data->txmixer_gain_5g);
2763 		rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
2764 		rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2765 		if (rf->channel <= 64) {
2766 			rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
2767 			rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
2768 			rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2769 		} else if (rf->channel <= 128) {
2770 			rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
2771 			rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
2772 			rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2773 		} else {
2774 			rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
2775 			rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
2776 			rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2777 		}
2778 		rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
2779 		rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
2780 		rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
2781 	}
2782 
2783 	reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
2784 	rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
2785 	if (rf->channel <= 14)
2786 		rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
2787 	else
2788 		rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 0);
2789 	rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
2790 
2791 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
2792 	rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2793 	rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2794 }
2795 
rt2800_config_channel_rf3053(struct rt2x00_dev * rt2x00dev,struct ieee80211_conf * conf,struct rf_channel * rf,struct channel_info * info)2796 static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev,
2797 					 struct ieee80211_conf *conf,
2798 					 struct rf_channel *rf,
2799 					 struct channel_info *info)
2800 {
2801 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2802 	u8 txrx_agc_fc;
2803 	u8 txrx_h20m;
2804 	u8 rfcsr;
2805 	u8 bbp;
2806 	const bool txbf_enabled = false; /* TODO */
2807 
2808 	/* TODO: use TX{0,1,2}FinePowerControl values from EEPROM */
2809 	bbp = rt2800_bbp_read(rt2x00dev, 109);
2810 	rt2x00_set_field8(&bbp, BBP109_TX0_POWER, 0);
2811 	rt2x00_set_field8(&bbp, BBP109_TX1_POWER, 0);
2812 	rt2800_bbp_write(rt2x00dev, 109, bbp);
2813 
2814 	bbp = rt2800_bbp_read(rt2x00dev, 110);
2815 	rt2x00_set_field8(&bbp, BBP110_TX2_POWER, 0);
2816 	rt2800_bbp_write(rt2x00dev, 110, bbp);
2817 
2818 	if (rf->channel <= 14) {
2819 		/* Restore BBP 25 & 26 for 2.4 GHz */
2820 		rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2821 		rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2822 	} else {
2823 		/* Hard code BBP 25 & 26 for 5GHz */
2824 
2825 		/* Enable IQ Phase correction */
2826 		rt2800_bbp_write(rt2x00dev, 25, 0x09);
2827 		/* Setup IQ Phase correction value */
2828 		rt2800_bbp_write(rt2x00dev, 26, 0xff);
2829 	}
2830 
2831 	rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2832 	rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3 & 0xf);
2833 
2834 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
2835 	rt2x00_set_field8(&rfcsr, RFCSR11_R, (rf->rf2 & 0x3));
2836 	rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2837 
2838 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
2839 	rt2x00_set_field8(&rfcsr, RFCSR11_PLL_IDOH, 1);
2840 	if (rf->channel <= 14)
2841 		rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 1);
2842 	else
2843 		rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 2);
2844 	rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2845 
2846 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 53);
2847 	if (rf->channel <= 14) {
2848 		rfcsr = 0;
2849 		rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2850 				  info->default_power1 & 0x1f);
2851 	} else {
2852 		if (rt2x00_is_usb(rt2x00dev))
2853 			rfcsr = 0x40;
2854 
2855 		rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2856 				  ((info->default_power1 & 0x18) << 1) |
2857 				  (info->default_power1 & 7));
2858 	}
2859 	rt2800_rfcsr_write(rt2x00dev, 53, rfcsr);
2860 
2861 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 55);
2862 	if (rf->channel <= 14) {
2863 		rfcsr = 0;
2864 		rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2865 				  info->default_power2 & 0x1f);
2866 	} else {
2867 		if (rt2x00_is_usb(rt2x00dev))
2868 			rfcsr = 0x40;
2869 
2870 		rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2871 				  ((info->default_power2 & 0x18) << 1) |
2872 				  (info->default_power2 & 7));
2873 	}
2874 	rt2800_rfcsr_write(rt2x00dev, 55, rfcsr);
2875 
2876 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 54);
2877 	if (rf->channel <= 14) {
2878 		rfcsr = 0;
2879 		rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2880 				  info->default_power3 & 0x1f);
2881 	} else {
2882 		if (rt2x00_is_usb(rt2x00dev))
2883 			rfcsr = 0x40;
2884 
2885 		rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2886 				  ((info->default_power3 & 0x18) << 1) |
2887 				  (info->default_power3 & 7));
2888 	}
2889 	rt2800_rfcsr_write(rt2x00dev, 54, rfcsr);
2890 
2891 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2892 	rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2893 	rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2894 	rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2895 	rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2896 	rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2897 	rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2898 	rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2899 	rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2900 
2901 	switch (rt2x00dev->default_ant.tx_chain_num) {
2902 	case 3:
2903 		rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2904 		fallthrough;
2905 	case 2:
2906 		rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2907 		fallthrough;
2908 	case 1:
2909 		rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2910 		break;
2911 	}
2912 
2913 	switch (rt2x00dev->default_ant.rx_chain_num) {
2914 	case 3:
2915 		rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2916 		fallthrough;
2917 	case 2:
2918 		rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2919 		fallthrough;
2920 	case 1:
2921 		rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2922 		break;
2923 	}
2924 	rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2925 
2926 	rt2800_freq_cal_mode1(rt2x00dev);
2927 
2928 	if (conf_is_ht40(conf)) {
2929 		txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw40,
2930 						RFCSR24_TX_AGC_FC);
2931 		txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw40,
2932 					      RFCSR24_TX_H20M);
2933 	} else {
2934 		txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw20,
2935 						RFCSR24_TX_AGC_FC);
2936 		txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw20,
2937 					      RFCSR24_TX_H20M);
2938 	}
2939 
2940 	/* NOTE: the reference driver does not writes the new value
2941 	 * back to RFCSR 32
2942 	 */
2943 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 32);
2944 	rt2x00_set_field8(&rfcsr, RFCSR32_TX_AGC_FC, txrx_agc_fc);
2945 
2946 	if (rf->channel <= 14)
2947 		rfcsr = 0xa0;
2948 	else
2949 		rfcsr = 0x80;
2950 	rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2951 
2952 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
2953 	rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, txrx_h20m);
2954 	rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, txrx_h20m);
2955 	rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2956 
2957 	/* Band selection */
2958 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 36);
2959 	if (rf->channel <= 14)
2960 		rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1);
2961 	else
2962 		rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0);
2963 	rt2800_rfcsr_write(rt2x00dev, 36, rfcsr);
2964 
2965 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 34);
2966 	if (rf->channel <= 14)
2967 		rfcsr = 0x3c;
2968 	else
2969 		rfcsr = 0x20;
2970 	rt2800_rfcsr_write(rt2x00dev, 34, rfcsr);
2971 
2972 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 12);
2973 	if (rf->channel <= 14)
2974 		rfcsr = 0x1a;
2975 	else
2976 		rfcsr = 0x12;
2977 	rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2978 
2979 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
2980 	if (rf->channel >= 1 && rf->channel <= 14)
2981 		rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2982 	else if (rf->channel >= 36 && rf->channel <= 64)
2983 		rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2984 	else if (rf->channel >= 100 && rf->channel <= 128)
2985 		rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2986 	else
2987 		rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2988 	rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2989 
2990 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
2991 	rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
2992 	rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2993 
2994 	rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
2995 
2996 	if (rf->channel <= 14) {
2997 		rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
2998 		rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
2999 	} else {
3000 		rt2800_rfcsr_write(rt2x00dev, 10, 0xd8);
3001 		rt2800_rfcsr_write(rt2x00dev, 13, 0x23);
3002 	}
3003 
3004 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
3005 	rt2x00_set_field8(&rfcsr, RFCSR51_BITS01, 1);
3006 	rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
3007 
3008 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
3009 	if (rf->channel <= 14) {
3010 		rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 5);
3011 		rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 3);
3012 	} else {
3013 		rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 4);
3014 		rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 2);
3015 	}
3016 	rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
3017 
3018 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
3019 	if (rf->channel <= 14)
3020 		rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 3);
3021 	else
3022 		rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 2);
3023 
3024 	if (txbf_enabled)
3025 		rt2x00_set_field8(&rfcsr, RFCSR49_TX_DIV, 1);
3026 
3027 	rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
3028 
3029 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
3030 	rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO1_EN, 0);
3031 	rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
3032 
3033 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 57);
3034 	if (rf->channel <= 14)
3035 		rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x1b);
3036 	else
3037 		rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x0f);
3038 	rt2800_rfcsr_write(rt2x00dev, 57, rfcsr);
3039 
3040 	if (rf->channel <= 14) {
3041 		rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
3042 		rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
3043 	} else {
3044 		rt2800_rfcsr_write(rt2x00dev, 44, 0x9b);
3045 		rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
3046 	}
3047 
3048 	/* Initiate VCO calibration */
3049 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
3050 	if (rf->channel <= 14) {
3051 		rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
3052 	} else {
3053 		rt2x00_set_field8(&rfcsr, RFCSR3_BIT1, 1);
3054 		rt2x00_set_field8(&rfcsr, RFCSR3_BIT2, 1);
3055 		rt2x00_set_field8(&rfcsr, RFCSR3_BIT3, 1);
3056 		rt2x00_set_field8(&rfcsr, RFCSR3_BIT4, 1);
3057 		rt2x00_set_field8(&rfcsr, RFCSR3_BIT5, 1);
3058 		rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
3059 	}
3060 	rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3061 
3062 	if (rf->channel >= 1 && rf->channel <= 14) {
3063 		rfcsr = 0x23;
3064 		if (txbf_enabled)
3065 			rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
3066 		rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
3067 
3068 		rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
3069 	} else if (rf->channel >= 36 && rf->channel <= 64) {
3070 		rfcsr = 0x36;
3071 		if (txbf_enabled)
3072 			rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
3073 		rt2800_rfcsr_write(rt2x00dev, 39, 0x36);
3074 
3075 		rt2800_rfcsr_write(rt2x00dev, 45, 0xeb);
3076 	} else if (rf->channel >= 100 && rf->channel <= 128) {
3077 		rfcsr = 0x32;
3078 		if (txbf_enabled)
3079 			rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
3080 		rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
3081 
3082 		rt2800_rfcsr_write(rt2x00dev, 45, 0xb3);
3083 	} else {
3084 		rfcsr = 0x30;
3085 		if (txbf_enabled)
3086 			rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
3087 		rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
3088 
3089 		rt2800_rfcsr_write(rt2x00dev, 45, 0x9b);
3090 	}
3091 }
3092 
rt2800_config_channel_rf3853(struct rt2x00_dev * rt2x00dev,struct ieee80211_conf * conf,struct rf_channel * rf,struct channel_info * info)3093 static void rt2800_config_channel_rf3853(struct rt2x00_dev *rt2x00dev,
3094 					 struct ieee80211_conf *conf,
3095 					 struct rf_channel *rf,
3096 					 struct channel_info *info)
3097 {
3098 	u8 rfcsr;
3099 	u8 bbp;
3100 	u8 pwr1, pwr2, pwr3;
3101 
3102 	const bool txbf_enabled = false; /* TODO */
3103 
3104 	/* TODO: add band selection */
3105 
3106 	if (rf->channel <= 14)
3107 		rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
3108 	else if (rf->channel < 132)
3109 		rt2800_rfcsr_write(rt2x00dev, 6, 0x80);
3110 	else
3111 		rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
3112 
3113 	rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
3114 	rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
3115 
3116 	if (rf->channel <= 14)
3117 		rt2800_rfcsr_write(rt2x00dev, 11, 0x46);
3118 	else
3119 		rt2800_rfcsr_write(rt2x00dev, 11, 0x48);
3120 
3121 	if (rf->channel <= 14)
3122 		rt2800_rfcsr_write(rt2x00dev, 12, 0x1a);
3123 	else
3124 		rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
3125 
3126 	rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
3127 
3128 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3129 	rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
3130 	rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
3131 	rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
3132 	rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
3133 	rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
3134 	rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
3135 	rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
3136 	rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
3137 
3138 	switch (rt2x00dev->default_ant.tx_chain_num) {
3139 	case 3:
3140 		rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
3141 		fallthrough;
3142 	case 2:
3143 		rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
3144 		fallthrough;
3145 	case 1:
3146 		rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
3147 		break;
3148 	}
3149 
3150 	switch (rt2x00dev->default_ant.rx_chain_num) {
3151 	case 3:
3152 		rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
3153 		fallthrough;
3154 	case 2:
3155 		rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
3156 		fallthrough;
3157 	case 1:
3158 		rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
3159 		break;
3160 	}
3161 	rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3162 
3163 	rt2800_freq_cal_mode1(rt2x00dev);
3164 
3165 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
3166 	if (!conf_is_ht40(conf))
3167 		rfcsr &= ~(0x06);
3168 	else
3169 		rfcsr |= 0x06;
3170 	rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3171 
3172 	if (rf->channel <= 14)
3173 		rt2800_rfcsr_write(rt2x00dev, 31, 0xa0);
3174 	else
3175 		rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3176 
3177 	if (conf_is_ht40(conf))
3178 		rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3179 	else
3180 		rt2800_rfcsr_write(rt2x00dev, 32, 0xd8);
3181 
3182 	if (rf->channel <= 14)
3183 		rt2800_rfcsr_write(rt2x00dev, 34, 0x3c);
3184 	else
3185 		rt2800_rfcsr_write(rt2x00dev, 34, 0x20);
3186 
3187 	/* loopback RF_BS */
3188 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 36);
3189 	if (rf->channel <= 14)
3190 		rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1);
3191 	else
3192 		rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0);
3193 	rt2800_rfcsr_write(rt2x00dev, 36, rfcsr);
3194 
3195 	if (rf->channel <= 14)
3196 		rfcsr = 0x23;
3197 	else if (rf->channel < 100)
3198 		rfcsr = 0x36;
3199 	else if (rf->channel < 132)
3200 		rfcsr = 0x32;
3201 	else
3202 		rfcsr = 0x30;
3203 
3204 	if (txbf_enabled)
3205 		rfcsr |= 0x40;
3206 
3207 	rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
3208 
3209 	if (rf->channel <= 14)
3210 		rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
3211 	else
3212 		rt2800_rfcsr_write(rt2x00dev, 44, 0x9b);
3213 
3214 	if (rf->channel <= 14)
3215 		rfcsr = 0xbb;
3216 	else if (rf->channel < 100)
3217 		rfcsr = 0xeb;
3218 	else if (rf->channel < 132)
3219 		rfcsr = 0xb3;
3220 	else
3221 		rfcsr = 0x9b;
3222 	rt2800_rfcsr_write(rt2x00dev, 45, rfcsr);
3223 
3224 	if (rf->channel <= 14)
3225 		rfcsr = 0x8e;
3226 	else
3227 		rfcsr = 0x8a;
3228 
3229 	if (txbf_enabled)
3230 		rfcsr |= 0x20;
3231 
3232 	rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
3233 
3234 	rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
3235 
3236 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
3237 	if (rf->channel <= 14)
3238 		rt2800_rfcsr_write(rt2x00dev, 51, 0x75);
3239 	else
3240 		rt2800_rfcsr_write(rt2x00dev, 51, 0x51);
3241 
3242 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 52);
3243 	if (rf->channel <= 14)
3244 		rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
3245 	else
3246 		rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
3247 
3248 	if (rf->channel <= 14) {
3249 		pwr1 = info->default_power1 & 0x1f;
3250 		pwr2 = info->default_power2 & 0x1f;
3251 		pwr3 = info->default_power3 & 0x1f;
3252 	} else {
3253 		pwr1 = 0x48 | ((info->default_power1 & 0x18) << 1) |
3254 			(info->default_power1 & 0x7);
3255 		pwr2 = 0x48 | ((info->default_power2 & 0x18) << 1) |
3256 			(info->default_power2 & 0x7);
3257 		pwr3 = 0x48 | ((info->default_power3 & 0x18) << 1) |
3258 			(info->default_power3 & 0x7);
3259 	}
3260 
3261 	rt2800_rfcsr_write(rt2x00dev, 53, pwr1);
3262 	rt2800_rfcsr_write(rt2x00dev, 54, pwr2);
3263 	rt2800_rfcsr_write(rt2x00dev, 55, pwr3);
3264 
3265 	rt2x00_dbg(rt2x00dev, "Channel:%d, pwr1:%02x, pwr2:%02x, pwr3:%02x\n",
3266 		   rf->channel, pwr1, pwr2, pwr3);
3267 
3268 	bbp = (info->default_power1 >> 5) |
3269 	      ((info->default_power2 & 0xe0) >> 1);
3270 	rt2800_bbp_write(rt2x00dev, 109, bbp);
3271 
3272 	bbp = rt2800_bbp_read(rt2x00dev, 110);
3273 	bbp &= 0x0f;
3274 	bbp |= (info->default_power3 & 0xe0) >> 1;
3275 	rt2800_bbp_write(rt2x00dev, 110, bbp);
3276 
3277 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 57);
3278 	if (rf->channel <= 14)
3279 		rt2800_rfcsr_write(rt2x00dev, 57, 0x6e);
3280 	else
3281 		rt2800_rfcsr_write(rt2x00dev, 57, 0x3e);
3282 
3283 	/* Enable RF tuning */
3284 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
3285 	rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
3286 	rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3287 
3288 	udelay(2000);
3289 
3290 	bbp = rt2800_bbp_read(rt2x00dev, 49);
3291 	/* clear update flag */
3292 	rt2800_bbp_write(rt2x00dev, 49, bbp & 0xfe);
3293 	rt2800_bbp_write(rt2x00dev, 49, bbp);
3294 
3295 	/* TODO: add calibration for TxBF */
3296 }
3297 
3298 #define POWER_BOUND		0x27
3299 #define POWER_BOUND_5G		0x2b
3300 
rt2800_config_channel_rf3290(struct rt2x00_dev * rt2x00dev,struct ieee80211_conf * conf,struct rf_channel * rf,struct channel_info * info)3301 static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
3302 					 struct ieee80211_conf *conf,
3303 					 struct rf_channel *rf,
3304 					 struct channel_info *info)
3305 {
3306 	u8 rfcsr;
3307 
3308 	rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
3309 	rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
3310 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
3311 	rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
3312 	rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
3313 
3314 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
3315 	if (info->default_power1 > POWER_BOUND)
3316 		rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
3317 	else
3318 		rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
3319 	rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
3320 
3321 	rt2800_freq_cal_mode1(rt2x00dev);
3322 
3323 	if (rf->channel <= 14) {
3324 		if (rf->channel == 6)
3325 			rt2800_bbp_write(rt2x00dev, 68, 0x0c);
3326 		else
3327 			rt2800_bbp_write(rt2x00dev, 68, 0x0b);
3328 
3329 		if (rf->channel >= 1 && rf->channel <= 6)
3330 			rt2800_bbp_write(rt2x00dev, 59, 0x0f);
3331 		else if (rf->channel >= 7 && rf->channel <= 11)
3332 			rt2800_bbp_write(rt2x00dev, 59, 0x0e);
3333 		else if (rf->channel >= 12 && rf->channel <= 14)
3334 			rt2800_bbp_write(rt2x00dev, 59, 0x0d);
3335 	}
3336 }
3337 
rt2800_config_channel_rf3322(struct rt2x00_dev * rt2x00dev,struct ieee80211_conf * conf,struct rf_channel * rf,struct channel_info * info)3338 static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
3339 					 struct ieee80211_conf *conf,
3340 					 struct rf_channel *rf,
3341 					 struct channel_info *info)
3342 {
3343 	u8 rfcsr;
3344 
3345 	rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
3346 	rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
3347 
3348 	rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
3349 	rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
3350 	rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
3351 
3352 	if (info->default_power1 > POWER_BOUND)
3353 		rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
3354 	else
3355 		rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
3356 
3357 	if (info->default_power2 > POWER_BOUND)
3358 		rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
3359 	else
3360 		rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
3361 
3362 	rt2800_freq_cal_mode1(rt2x00dev);
3363 
3364 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3365 	rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
3366 	rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
3367 
3368 	if ( rt2x00dev->default_ant.tx_chain_num == 2 )
3369 		rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
3370 	else
3371 		rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
3372 
3373 	if ( rt2x00dev->default_ant.rx_chain_num == 2 )
3374 		rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
3375 	else
3376 		rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
3377 
3378 	rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
3379 	rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
3380 
3381 	rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3382 
3383 	rt2800_rfcsr_write(rt2x00dev, 31, 80);
3384 }
3385 
rt2800_config_channel_rf53xx(struct rt2x00_dev * rt2x00dev,struct ieee80211_conf * conf,struct rf_channel * rf,struct channel_info * info)3386 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
3387 					 struct ieee80211_conf *conf,
3388 					 struct rf_channel *rf,
3389 					 struct channel_info *info)
3390 {
3391 	u8 rfcsr;
3392 	int idx = rf->channel-1;
3393 
3394 	rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
3395 	rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
3396 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
3397 	rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
3398 	rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
3399 
3400 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
3401 	if (info->default_power1 > POWER_BOUND)
3402 		rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
3403 	else
3404 		rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
3405 	rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
3406 
3407 	if (rt2x00_rt(rt2x00dev, RT5392)) {
3408 		rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
3409 		if (info->default_power2 > POWER_BOUND)
3410 			rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND);
3411 		else
3412 			rt2x00_set_field8(&rfcsr, RFCSR50_TX,
3413 					  info->default_power2);
3414 		rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
3415 	}
3416 
3417 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3418 	if (rt2x00_rt(rt2x00dev, RT5392)) {
3419 		rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
3420 		rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
3421 	}
3422 	rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
3423 	rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
3424 	rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
3425 	rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
3426 	rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3427 
3428 	rt2800_freq_cal_mode1(rt2x00dev);
3429 
3430 	if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
3431 		if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
3432 			/* r55/r59 value array of channel 1~14 */
3433 			static const u8 r55_bt_rev[] = {0x83, 0x83,
3434 				0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
3435 				0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
3436 			static const u8 r59_bt_rev[] = {0x0e, 0x0e,
3437 				0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
3438 				0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
3439 
3440 			rt2800_rfcsr_write(rt2x00dev, 55,
3441 					   r55_bt_rev[idx]);
3442 			rt2800_rfcsr_write(rt2x00dev, 59,
3443 					   r59_bt_rev[idx]);
3444 		} else {
3445 			static const u8 r59_bt[] = {0x8b, 0x8b, 0x8b,
3446 				0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
3447 				0x88, 0x88, 0x86, 0x85, 0x84};
3448 
3449 			rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
3450 		}
3451 	} else {
3452 		if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
3453 			static const u8 r55_nonbt_rev[] = {0x23, 0x23,
3454 				0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
3455 				0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
3456 			static const u8 r59_nonbt_rev[] = {0x07, 0x07,
3457 				0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
3458 				0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
3459 
3460 			rt2800_rfcsr_write(rt2x00dev, 55,
3461 					   r55_nonbt_rev[idx]);
3462 			rt2800_rfcsr_write(rt2x00dev, 59,
3463 					   r59_nonbt_rev[idx]);
3464 		} else if (rt2x00_rt(rt2x00dev, RT5390) ||
3465 			   rt2x00_rt(rt2x00dev, RT5392) ||
3466 			   rt2x00_rt(rt2x00dev, RT6352)) {
3467 			static const u8 r59_non_bt[] = {0x8f, 0x8f,
3468 				0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
3469 				0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
3470 
3471 			rt2800_rfcsr_write(rt2x00dev, 59,
3472 					   r59_non_bt[idx]);
3473 		} else if (rt2x00_rt(rt2x00dev, RT5350)) {
3474 			static const u8 r59_non_bt[] = {0x0b, 0x0b,
3475 				0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0a,
3476 				0x0a, 0x09, 0x08, 0x07, 0x07, 0x06};
3477 
3478 			rt2800_rfcsr_write(rt2x00dev, 59,
3479 					   r59_non_bt[idx]);
3480 		}
3481 	}
3482 }
3483 
rt2800_config_channel_rf55xx(struct rt2x00_dev * rt2x00dev,struct ieee80211_conf * conf,struct rf_channel * rf,struct channel_info * info)3484 static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev,
3485 					 struct ieee80211_conf *conf,
3486 					 struct rf_channel *rf,
3487 					 struct channel_info *info)
3488 {
3489 	u8 rfcsr, ep_reg;
3490 	u32 reg;
3491 	int power_bound;
3492 
3493 	/* TODO */
3494 	const bool is_11b = false;
3495 	const bool is_type_ep = false;
3496 
3497 	reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
3498 	rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL,
3499 			   (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0);
3500 	rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3501 
3502 	/* Order of values on rf_channel entry: N, K, mod, R */
3503 	rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff);
3504 
3505 	rfcsr = rt2800_rfcsr_read(rt2x00dev,  9);
3506 	rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf);
3507 	rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8);
3508 	rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2);
3509 	rt2800_rfcsr_write(rt2x00dev, 9, rfcsr);
3510 
3511 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
3512 	rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1);
3513 	rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3);
3514 	rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
3515 
3516 	if (rf->channel <= 14) {
3517 		rt2800_rfcsr_write(rt2x00dev, 10, 0x90);
3518 		/* FIXME: RF11 owerwrite ? */
3519 		rt2800_rfcsr_write(rt2x00dev, 11, 0x4A);
3520 		rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
3521 		rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
3522 		rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
3523 		rt2800_rfcsr_write(rt2x00dev, 24, 0x4A);
3524 		rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
3525 		rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
3526 		rt2800_rfcsr_write(rt2x00dev, 36, 0x80);
3527 		rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
3528 		rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
3529 		rt2800_rfcsr_write(rt2x00dev, 39, 0x1B);
3530 		rt2800_rfcsr_write(rt2x00dev, 40, 0x0D);
3531 		rt2800_rfcsr_write(rt2x00dev, 41, 0x9B);
3532 		rt2800_rfcsr_write(rt2x00dev, 42, 0xD5);
3533 		rt2800_rfcsr_write(rt2x00dev, 43, 0x72);
3534 		rt2800_rfcsr_write(rt2x00dev, 44, 0x0E);
3535 		rt2800_rfcsr_write(rt2x00dev, 45, 0xA2);
3536 		rt2800_rfcsr_write(rt2x00dev, 46, 0x6B);
3537 		rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3538 		rt2800_rfcsr_write(rt2x00dev, 51, 0x3E);
3539 		rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
3540 		rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
3541 		rt2800_rfcsr_write(rt2x00dev, 56, 0xA1);
3542 		rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
3543 		rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
3544 		rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3545 		rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
3546 		rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
3547 
3548 		/* TODO RF27 <- tssi */
3549 
3550 		rfcsr = rf->channel <= 10 ? 0x07 : 0x06;
3551 		rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
3552 		rt2800_rfcsr_write(rt2x00dev, 59, rfcsr);
3553 
3554 		if (is_11b) {
3555 			/* CCK */
3556 			rt2800_rfcsr_write(rt2x00dev, 31, 0xF8);
3557 			rt2800_rfcsr_write(rt2x00dev, 32, 0xC0);
3558 			if (is_type_ep)
3559 				rt2800_rfcsr_write(rt2x00dev, 55, 0x06);
3560 			else
3561 				rt2800_rfcsr_write(rt2x00dev, 55, 0x47);
3562 		} else {
3563 			/* OFDM */
3564 			if (is_type_ep)
3565 				rt2800_rfcsr_write(rt2x00dev, 55, 0x03);
3566 			else
3567 				rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
3568 		}
3569 
3570 		power_bound = POWER_BOUND;
3571 		ep_reg = 0x2;
3572 	} else {
3573 		rt2800_rfcsr_write(rt2x00dev, 10, 0x97);
3574 		/* FIMXE: RF11 overwrite */
3575 		rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
3576 		rt2800_rfcsr_write(rt2x00dev, 25, 0xBF);
3577 		rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
3578 		rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3579 		rt2800_rfcsr_write(rt2x00dev, 37, 0x04);
3580 		rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
3581 		rt2800_rfcsr_write(rt2x00dev, 40, 0x42);
3582 		rt2800_rfcsr_write(rt2x00dev, 41, 0xBB);
3583 		rt2800_rfcsr_write(rt2x00dev, 42, 0xD7);
3584 		rt2800_rfcsr_write(rt2x00dev, 45, 0x41);
3585 		rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
3586 		rt2800_rfcsr_write(rt2x00dev, 57, 0x77);
3587 		rt2800_rfcsr_write(rt2x00dev, 60, 0x05);
3588 		rt2800_rfcsr_write(rt2x00dev, 61, 0x01);
3589 
3590 		/* TODO RF27 <- tssi */
3591 
3592 		if (rf->channel >= 36 && rf->channel <= 64) {
3593 
3594 			rt2800_rfcsr_write(rt2x00dev, 12, 0x2E);
3595 			rt2800_rfcsr_write(rt2x00dev, 13, 0x22);
3596 			rt2800_rfcsr_write(rt2x00dev, 22, 0x60);
3597 			rt2800_rfcsr_write(rt2x00dev, 23, 0x7F);
3598 			if (rf->channel <= 50)
3599 				rt2800_rfcsr_write(rt2x00dev, 24, 0x09);
3600 			else if (rf->channel >= 52)
3601 				rt2800_rfcsr_write(rt2x00dev, 24, 0x07);
3602 			rt2800_rfcsr_write(rt2x00dev, 39, 0x1C);
3603 			rt2800_rfcsr_write(rt2x00dev, 43, 0x5B);
3604 			rt2800_rfcsr_write(rt2x00dev, 44, 0X40);
3605 			rt2800_rfcsr_write(rt2x00dev, 46, 0X00);
3606 			rt2800_rfcsr_write(rt2x00dev, 51, 0xFE);
3607 			rt2800_rfcsr_write(rt2x00dev, 52, 0x0C);
3608 			rt2800_rfcsr_write(rt2x00dev, 54, 0xF8);
3609 			if (rf->channel <= 50) {
3610 				rt2800_rfcsr_write(rt2x00dev, 55, 0x06),
3611 				rt2800_rfcsr_write(rt2x00dev, 56, 0xD3);
3612 			} else if (rf->channel >= 52) {
3613 				rt2800_rfcsr_write(rt2x00dev, 55, 0x04);
3614 				rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
3615 			}
3616 
3617 			rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
3618 			rt2800_rfcsr_write(rt2x00dev, 59, 0x7F);
3619 			rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
3620 
3621 		} else if (rf->channel >= 100 && rf->channel <= 165) {
3622 
3623 			rt2800_rfcsr_write(rt2x00dev, 12, 0x0E);
3624 			rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
3625 			rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
3626 			if (rf->channel <= 153) {
3627 				rt2800_rfcsr_write(rt2x00dev, 23, 0x3C);
3628 				rt2800_rfcsr_write(rt2x00dev, 24, 0x06);
3629 			} else if (rf->channel >= 155) {
3630 				rt2800_rfcsr_write(rt2x00dev, 23, 0x38);
3631 				rt2800_rfcsr_write(rt2x00dev, 24, 0x05);
3632 			}
3633 			if (rf->channel <= 138) {
3634 				rt2800_rfcsr_write(rt2x00dev, 39, 0x1A);
3635 				rt2800_rfcsr_write(rt2x00dev, 43, 0x3B);
3636 				rt2800_rfcsr_write(rt2x00dev, 44, 0x20);
3637 				rt2800_rfcsr_write(rt2x00dev, 46, 0x18);
3638 			} else if (rf->channel >= 140) {
3639 				rt2800_rfcsr_write(rt2x00dev, 39, 0x18);
3640 				rt2800_rfcsr_write(rt2x00dev, 43, 0x1B);
3641 				rt2800_rfcsr_write(rt2x00dev, 44, 0x10);
3642 				rt2800_rfcsr_write(rt2x00dev, 46, 0X08);
3643 			}
3644 			if (rf->channel <= 124)
3645 				rt2800_rfcsr_write(rt2x00dev, 51, 0xFC);
3646 			else if (rf->channel >= 126)
3647 				rt2800_rfcsr_write(rt2x00dev, 51, 0xEC);
3648 			if (rf->channel <= 138)
3649 				rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
3650 			else if (rf->channel >= 140)
3651 				rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
3652 			rt2800_rfcsr_write(rt2x00dev, 54, 0xEB);
3653 			if (rf->channel <= 138)
3654 				rt2800_rfcsr_write(rt2x00dev, 55, 0x01);
3655 			else if (rf->channel >= 140)
3656 				rt2800_rfcsr_write(rt2x00dev, 55, 0x00);
3657 			if (rf->channel <= 128)
3658 				rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
3659 			else if (rf->channel >= 130)
3660 				rt2800_rfcsr_write(rt2x00dev, 56, 0xAB);
3661 			if (rf->channel <= 116)
3662 				rt2800_rfcsr_write(rt2x00dev, 58, 0x1D);
3663 			else if (rf->channel >= 118)
3664 				rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
3665 			if (rf->channel <= 138)
3666 				rt2800_rfcsr_write(rt2x00dev, 59, 0x3F);
3667 			else if (rf->channel >= 140)
3668 				rt2800_rfcsr_write(rt2x00dev, 59, 0x7C);
3669 			if (rf->channel <= 116)
3670 				rt2800_rfcsr_write(rt2x00dev, 62, 0x1D);
3671 			else if (rf->channel >= 118)
3672 				rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
3673 		}
3674 
3675 		power_bound = POWER_BOUND_5G;
3676 		ep_reg = 0x3;
3677 	}
3678 
3679 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
3680 	if (info->default_power1 > power_bound)
3681 		rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound);
3682 	else
3683 		rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
3684 	if (is_type_ep)
3685 		rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg);
3686 	rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
3687 
3688 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
3689 	if (info->default_power2 > power_bound)
3690 		rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound);
3691 	else
3692 		rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2);
3693 	if (is_type_ep)
3694 		rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg);
3695 	rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
3696 
3697 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3698 	rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
3699 	rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
3700 
3701 	rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD,
3702 			  rt2x00dev->default_ant.tx_chain_num >= 1);
3703 	rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
3704 			  rt2x00dev->default_ant.tx_chain_num == 2);
3705 	rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
3706 
3707 	rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD,
3708 			  rt2x00dev->default_ant.rx_chain_num >= 1);
3709 	rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
3710 			  rt2x00dev->default_ant.rx_chain_num == 2);
3711 	rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
3712 
3713 	rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3714 	rt2800_rfcsr_write(rt2x00dev, 6, 0xe4);
3715 
3716 	if (conf_is_ht40(conf))
3717 		rt2800_rfcsr_write(rt2x00dev, 30, 0x16);
3718 	else
3719 		rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
3720 
3721 	if (!is_11b) {
3722 		rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3723 		rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3724 	}
3725 
3726 	/* TODO proper frequency adjustment */
3727 	rt2800_freq_cal_mode1(rt2x00dev);
3728 
3729 	/* TODO merge with others */
3730 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
3731 	rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
3732 	rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3733 
3734 	/* BBP settings */
3735 	rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3736 	rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3737 	rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3738 
3739 	rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18);
3740 	rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08);
3741 	rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38);
3742 	rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92);
3743 
3744 	/* GLRT band configuration */
3745 	rt2800_bbp_write(rt2x00dev, 195, 128);
3746 	rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0);
3747 	rt2800_bbp_write(rt2x00dev, 195, 129);
3748 	rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E);
3749 	rt2800_bbp_write(rt2x00dev, 195, 130);
3750 	rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28);
3751 	rt2800_bbp_write(rt2x00dev, 195, 131);
3752 	rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20);
3753 	rt2800_bbp_write(rt2x00dev, 195, 133);
3754 	rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F);
3755 	rt2800_bbp_write(rt2x00dev, 195, 124);
3756 	rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
3757 }
3758 
rt2800_config_channel_rf7620(struct rt2x00_dev * rt2x00dev,struct ieee80211_conf * conf,struct rf_channel * rf,struct channel_info * info)3759 static void rt2800_config_channel_rf7620(struct rt2x00_dev *rt2x00dev,
3760 					 struct ieee80211_conf *conf,
3761 					 struct rf_channel *rf,
3762 					 struct channel_info *info)
3763 {
3764 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
3765 	u8 rx_agc_fc, tx_agc_fc;
3766 	u8 rfcsr;
3767 
3768 	/* Frequeny plan setting */
3769 	/* Rdiv setting (set 0x03 if Xtal==20)
3770 	 * R13[1:0]
3771 	 */
3772 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 13);
3773 	rt2x00_set_field8(&rfcsr, RFCSR13_RDIV_MT7620,
3774 			  rt2800_clk_is_20mhz(rt2x00dev) ? 3 : 0);
3775 	rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
3776 
3777 	/* N setting
3778 	 * R20[7:0] in rf->rf1
3779 	 * R21[0] always 0
3780 	 */
3781 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 20);
3782 	rfcsr = (rf->rf1 & 0x00ff);
3783 	rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
3784 
3785 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
3786 	rt2x00_set_field8(&rfcsr, RFCSR21_BIT1, 0);
3787 	rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3788 
3789 	/* K setting (always 0)
3790 	 * R16[3:0] (RF PLL freq selection)
3791 	 */
3792 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 16);
3793 	rt2x00_set_field8(&rfcsr, RFCSR16_RF_PLL_FREQ_SEL_MT7620, 0);
3794 	rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
3795 
3796 	/* D setting (always 0)
3797 	 * R22[2:0] (D=15, R22[2:0]=<111>)
3798 	 */
3799 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
3800 	rt2x00_set_field8(&rfcsr, RFCSR22_FREQPLAN_D_MT7620, 0);
3801 	rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3802 
3803 	/* Ksd setting
3804 	 * Ksd: R17<7:0> in rf->rf2
3805 	 *      R18<7:0> in rf->rf3
3806 	 *      R19<1:0> in rf->rf4
3807 	 */
3808 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 17);
3809 	rfcsr = rf->rf2;
3810 	rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
3811 
3812 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 18);
3813 	rfcsr = rf->rf3;
3814 	rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
3815 
3816 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 19);
3817 	rt2x00_set_field8(&rfcsr, RFCSR19_K, rf->rf4);
3818 	rt2800_rfcsr_write(rt2x00dev, 19, rfcsr);
3819 
3820 	/* Default: XO=20MHz , SDM mode */
3821 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 16);
3822 	rt2x00_set_field8(&rfcsr, RFCSR16_SDM_MODE_MT7620, 0x80);
3823 	rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
3824 
3825 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
3826 	rt2x00_set_field8(&rfcsr, RFCSR21_BIT8, 1);
3827 	rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3828 
3829 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3830 	rt2x00_set_field8(&rfcsr, RFCSR1_TX2_EN_MT7620,
3831 			  rt2x00dev->default_ant.tx_chain_num != 1);
3832 	rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3833 
3834 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 2);
3835 	rt2x00_set_field8(&rfcsr, RFCSR2_TX2_EN_MT7620,
3836 			  rt2x00dev->default_ant.tx_chain_num != 1);
3837 	rt2x00_set_field8(&rfcsr, RFCSR2_RX2_EN_MT7620,
3838 			  rt2x00dev->default_ant.rx_chain_num != 1);
3839 	rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3840 
3841 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 42);
3842 	rt2x00_set_field8(&rfcsr, RFCSR42_TX2_EN_MT7620,
3843 			  rt2x00dev->default_ant.tx_chain_num != 1);
3844 	rt2800_rfcsr_write(rt2x00dev, 42, rfcsr);
3845 
3846 	/* RF for DC Cal BW */
3847 	if (conf_is_ht40(conf)) {
3848 		rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10);
3849 		rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10);
3850 		rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04);
3851 		rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10);
3852 		rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10);
3853 	} else {
3854 		rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x20);
3855 		rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x20);
3856 		rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x00);
3857 		rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x20);
3858 		rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x20);
3859 	}
3860 
3861 	if (conf_is_ht40(conf)) {
3862 		rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x08);
3863 		rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x08);
3864 	} else {
3865 		rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x28);
3866 		rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x28);
3867 	}
3868 
3869 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 28);
3870 	rt2x00_set_field8(&rfcsr, RFCSR28_CH11_HT40,
3871 			  conf_is_ht40(conf) && (rf->channel == 11));
3872 	rt2800_rfcsr_write(rt2x00dev, 28, rfcsr);
3873 
3874 	if (!test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags)) {
3875 		if (conf_is_ht40(conf)) {
3876 			rx_agc_fc = drv_data->rx_calibration_bw40;
3877 			tx_agc_fc = drv_data->tx_calibration_bw40;
3878 		} else {
3879 			rx_agc_fc = drv_data->rx_calibration_bw20;
3880 			tx_agc_fc = drv_data->tx_calibration_bw20;
3881 		}
3882 		rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
3883 		rfcsr &= (~0x3F);
3884 		rfcsr |= rx_agc_fc;
3885 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rfcsr);
3886 		rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
3887 		rfcsr &= (~0x3F);
3888 		rfcsr |= rx_agc_fc;
3889 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rfcsr);
3890 		rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 6);
3891 		rfcsr &= (~0x3F);
3892 		rfcsr |= rx_agc_fc;
3893 		rt2800_rfcsr_write_bank(rt2x00dev, 7, 6, rfcsr);
3894 		rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 7);
3895 		rfcsr &= (~0x3F);
3896 		rfcsr |= rx_agc_fc;
3897 		rt2800_rfcsr_write_bank(rt2x00dev, 7, 7, rfcsr);
3898 
3899 		rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
3900 		rfcsr &= (~0x3F);
3901 		rfcsr |= tx_agc_fc;
3902 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rfcsr);
3903 		rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
3904 		rfcsr &= (~0x3F);
3905 		rfcsr |= tx_agc_fc;
3906 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rfcsr);
3907 		rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 58);
3908 		rfcsr &= (~0x3F);
3909 		rfcsr |= tx_agc_fc;
3910 		rt2800_rfcsr_write_bank(rt2x00dev, 7, 58, rfcsr);
3911 		rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 59);
3912 		rfcsr &= (~0x3F);
3913 		rfcsr |= tx_agc_fc;
3914 		rt2800_rfcsr_write_bank(rt2x00dev, 7, 59, rfcsr);
3915 	}
3916 }
3917 
rt2800_config_alc_rt6352(struct rt2x00_dev * rt2x00dev,struct ieee80211_channel * chan,int power_level)3918 static void rt2800_config_alc_rt6352(struct rt2x00_dev *rt2x00dev,
3919 				     struct ieee80211_channel *chan,
3920 				     int power_level)
3921 {
3922 	int cur_channel = rt2x00dev->rf_channel;
3923 	u16 eeprom, chan_power, rate_power, target_power;
3924 	u16 tx_power[2];
3925 	s8 *power_group[2];
3926 	u32 mac_sys_ctrl;
3927 	u32 cnt, reg;
3928 	u8 bbp;
3929 
3930 	if (WARN_ON(cur_channel < 1 || cur_channel > 14))
3931 		return;
3932 
3933 	/* get per chain power, 2 chains in total, unit is 0.5dBm */
3934 	power_level = (power_level - 3) * 2;
3935 
3936 	/* We can't get the accurate TX power. Based on some tests, the real
3937 	 * TX power is approximately equal to channel_power + (max)rate_power.
3938 	 * Usually max rate_power is the gain of the OFDM 6M rate. The antenna
3939 	 * gain and externel PA gain are not included as we are unable to
3940 	 * obtain these values.
3941 	 */
3942 	rate_power = rt2800_eeprom_read_from_array(rt2x00dev,
3943 						   EEPROM_TXPOWER_BYRATE, 1);
3944 	rate_power &= 0x3f;
3945 	power_level -= rate_power;
3946 	if (power_level < 1)
3947 		power_level = 1;
3948 
3949 	power_group[0] = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
3950 	power_group[1] = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
3951 	for (cnt = 0; cnt < 2; cnt++) {
3952 		chan_power = power_group[cnt][cur_channel - 1];
3953 		if (chan_power >= 0x20 || chan_power == 0)
3954 			chan_power = 0x10;
3955 		tx_power[cnt] = power_level < chan_power ? power_level : chan_power;
3956 	}
3957 
3958 	reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_0);
3959 	rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_0, tx_power[0]);
3960 	rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_1, tx_power[1]);
3961 	rt2x00_set_field32(&reg, TX_ALC_CFG_0_LIMIT_0, 0x2f);
3962 	rt2x00_set_field32(&reg, TX_ALC_CFG_0_LIMIT_1, 0x2f);
3963 
3964 	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
3965 	if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_INTERNAL_TX_ALC)) {
3966 		/* init base power by eeprom target power */
3967 		target_power = rt2800_eeprom_read(rt2x00dev,
3968 						  EEPROM_TXPOWER_INIT);
3969 		rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_0, target_power);
3970 		rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_1, target_power);
3971 	}
3972 	rt2800_register_write(rt2x00dev, TX_ALC_CFG_0, reg);
3973 
3974 	reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1);
3975 	rt2x00_set_field32(&reg, TX_ALC_CFG_1_TX_TEMP_COMP, 0);
3976 	rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg);
3977 
3978 	/* Save MAC SYS CTRL registers */
3979 	mac_sys_ctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
3980 	/* Disable Tx/Rx */
3981 	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
3982 	/* Check MAC Tx/Rx idle */
3983 	if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY)))
3984 		rt2x00_warn(rt2x00dev, "RF busy while configuring ALC\n");
3985 
3986 	if (chan->center_freq > 2457) {
3987 		bbp = rt2800_bbp_read(rt2x00dev, 30);
3988 		bbp = 0x40;
3989 		rt2800_bbp_write(rt2x00dev, 30, bbp);
3990 		rt2800_rfcsr_write(rt2x00dev, 39, 0);
3991 		if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
3992 			rt2800_rfcsr_write(rt2x00dev, 42, 0xfb);
3993 		else
3994 			rt2800_rfcsr_write(rt2x00dev, 42, 0x7b);
3995 	} else {
3996 		bbp = rt2800_bbp_read(rt2x00dev, 30);
3997 		bbp = 0x1f;
3998 		rt2800_bbp_write(rt2x00dev, 30, bbp);
3999 		rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
4000 		if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
4001 			rt2800_rfcsr_write(rt2x00dev, 42, 0xdb);
4002 		else
4003 			rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
4004 	}
4005 	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, mac_sys_ctrl);
4006 
4007 	rt2800_vco_calibration(rt2x00dev);
4008 }
4009 
rt2800_bbp_write_with_rx_chain(struct rt2x00_dev * rt2x00dev,const unsigned int word,const u8 value)4010 static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev,
4011 					   const unsigned int word,
4012 					   const u8 value)
4013 {
4014 	u8 chain, reg;
4015 
4016 	for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) {
4017 		reg = rt2800_bbp_read(rt2x00dev, 27);
4018 		rt2x00_set_field8(&reg,  BBP27_RX_CHAIN_SEL, chain);
4019 		rt2800_bbp_write(rt2x00dev, 27, reg);
4020 
4021 		rt2800_bbp_write(rt2x00dev, word, value);
4022 	}
4023 }
4024 
rt2800_iq_calibrate(struct rt2x00_dev * rt2x00dev,int channel)4025 static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel)
4026 {
4027 	u8 cal;
4028 
4029 	/* TX0 IQ Gain */
4030 	rt2800_bbp_write(rt2x00dev, 158, 0x2c);
4031 	if (channel <= 14)
4032 		cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G);
4033 	else if (channel >= 36 && channel <= 64)
4034 		cal = rt2x00_eeprom_byte(rt2x00dev,
4035 					 EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G);
4036 	else if (channel >= 100 && channel <= 138)
4037 		cal = rt2x00_eeprom_byte(rt2x00dev,
4038 					 EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G);
4039 	else if (channel >= 140 && channel <= 165)
4040 		cal = rt2x00_eeprom_byte(rt2x00dev,
4041 					 EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G);
4042 	else
4043 		cal = 0;
4044 	rt2800_bbp_write(rt2x00dev, 159, cal);
4045 
4046 	/* TX0 IQ Phase */
4047 	rt2800_bbp_write(rt2x00dev, 158, 0x2d);
4048 	if (channel <= 14)
4049 		cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G);
4050 	else if (channel >= 36 && channel <= 64)
4051 		cal = rt2x00_eeprom_byte(rt2x00dev,
4052 					 EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G);
4053 	else if (channel >= 100 && channel <= 138)
4054 		cal = rt2x00_eeprom_byte(rt2x00dev,
4055 					 EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G);
4056 	else if (channel >= 140 && channel <= 165)
4057 		cal = rt2x00_eeprom_byte(rt2x00dev,
4058 					 EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G);
4059 	else
4060 		cal = 0;
4061 	rt2800_bbp_write(rt2x00dev, 159, cal);
4062 
4063 	/* TX1 IQ Gain */
4064 	rt2800_bbp_write(rt2x00dev, 158, 0x4a);
4065 	if (channel <= 14)
4066 		cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G);
4067 	else if (channel >= 36 && channel <= 64)
4068 		cal = rt2x00_eeprom_byte(rt2x00dev,
4069 					 EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G);
4070 	else if (channel >= 100 && channel <= 138)
4071 		cal = rt2x00_eeprom_byte(rt2x00dev,
4072 					 EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G);
4073 	else if (channel >= 140 && channel <= 165)
4074 		cal = rt2x00_eeprom_byte(rt2x00dev,
4075 					 EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G);
4076 	else
4077 		cal = 0;
4078 	rt2800_bbp_write(rt2x00dev, 159, cal);
4079 
4080 	/* TX1 IQ Phase */
4081 	rt2800_bbp_write(rt2x00dev, 158, 0x4b);
4082 	if (channel <= 14)
4083 		cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G);
4084 	else if (channel >= 36 && channel <= 64)
4085 		cal = rt2x00_eeprom_byte(rt2x00dev,
4086 					 EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G);
4087 	else if (channel >= 100 && channel <= 138)
4088 		cal = rt2x00_eeprom_byte(rt2x00dev,
4089 					 EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G);
4090 	else if (channel >= 140 && channel <= 165)
4091 		cal = rt2x00_eeprom_byte(rt2x00dev,
4092 					 EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G);
4093 	else
4094 		cal = 0;
4095 	rt2800_bbp_write(rt2x00dev, 159, cal);
4096 
4097 	/* FIXME: possible RX0, RX1 callibration ? */
4098 
4099 	/* RF IQ compensation control */
4100 	rt2800_bbp_write(rt2x00dev, 158, 0x04);
4101 	cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL);
4102 	rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
4103 
4104 	/* RF IQ imbalance compensation control */
4105 	rt2800_bbp_write(rt2x00dev, 158, 0x03);
4106 	cal = rt2x00_eeprom_byte(rt2x00dev,
4107 				 EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL);
4108 	rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
4109 }
4110 
rt2800_txpower_to_dev(struct rt2x00_dev * rt2x00dev,unsigned int channel,s8 txpower)4111 static s8 rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev,
4112 				  unsigned int channel,
4113 				  s8 txpower)
4114 {
4115 	if (rt2x00_rt(rt2x00dev, RT3593) ||
4116 	    rt2x00_rt(rt2x00dev, RT3883))
4117 		txpower = rt2x00_get_field8(txpower, EEPROM_TXPOWER_ALC);
4118 
4119 	if (channel <= 14)
4120 		return clamp_t(s8, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER);
4121 
4122 	if (rt2x00_rt(rt2x00dev, RT3593) ||
4123 	    rt2x00_rt(rt2x00dev, RT3883))
4124 		return clamp_t(s8, txpower, MIN_A_TXPOWER_3593,
4125 			       MAX_A_TXPOWER_3593);
4126 	else
4127 		return clamp_t(s8, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER);
4128 }
4129 
rt3883_bbp_adjust(struct rt2x00_dev * rt2x00dev,struct rf_channel * rf)4130 static void rt3883_bbp_adjust(struct rt2x00_dev *rt2x00dev,
4131 			      struct rf_channel *rf)
4132 {
4133 	u8 bbp;
4134 
4135 	bbp = (rf->channel > 14) ? 0x48 : 0x38;
4136 	rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, bbp);
4137 
4138 	rt2800_bbp_write(rt2x00dev, 69, 0x12);
4139 
4140 	if (rf->channel <= 14) {
4141 		rt2800_bbp_write(rt2x00dev, 70, 0x0a);
4142 	} else {
4143 		/* Disable CCK packet detection */
4144 		rt2800_bbp_write(rt2x00dev, 70, 0x00);
4145 	}
4146 
4147 	rt2800_bbp_write(rt2x00dev, 73, 0x10);
4148 
4149 	if (rf->channel > 14) {
4150 		rt2800_bbp_write(rt2x00dev, 62, 0x1d);
4151 		rt2800_bbp_write(rt2x00dev, 63, 0x1d);
4152 		rt2800_bbp_write(rt2x00dev, 64, 0x1d);
4153 	} else {
4154 		rt2800_bbp_write(rt2x00dev, 62, 0x2d);
4155 		rt2800_bbp_write(rt2x00dev, 63, 0x2d);
4156 		rt2800_bbp_write(rt2x00dev, 64, 0x2d);
4157 	}
4158 }
4159 
rt2800_config_channel(struct rt2x00_dev * rt2x00dev,struct ieee80211_conf * conf,struct rf_channel * rf,struct channel_info * info)4160 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
4161 				  struct ieee80211_conf *conf,
4162 				  struct rf_channel *rf,
4163 				  struct channel_info *info)
4164 {
4165 	u32 reg;
4166 	u32 tx_pin;
4167 	u8 bbp, rfcsr;
4168 
4169 	info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
4170 						     info->default_power1);
4171 	info->default_power2 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
4172 						     info->default_power2);
4173 	if (rt2x00dev->default_ant.tx_chain_num > 2)
4174 		info->default_power3 =
4175 			rt2800_txpower_to_dev(rt2x00dev, rf->channel,
4176 					      info->default_power3);
4177 
4178 	switch (rt2x00dev->chip.rt) {
4179 	case RT3883:
4180 		rt3883_bbp_adjust(rt2x00dev, rf);
4181 		break;
4182 	}
4183 
4184 	switch (rt2x00dev->chip.rf) {
4185 	case RF2020:
4186 	case RF3020:
4187 	case RF3021:
4188 	case RF3022:
4189 	case RF3320:
4190 		rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
4191 		break;
4192 	case RF3052:
4193 		rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
4194 		break;
4195 	case RF3053:
4196 		rt2800_config_channel_rf3053(rt2x00dev, conf, rf, info);
4197 		break;
4198 	case RF3290:
4199 		rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
4200 		break;
4201 	case RF3322:
4202 		rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
4203 		break;
4204 	case RF3853:
4205 		rt2800_config_channel_rf3853(rt2x00dev, conf, rf, info);
4206 		break;
4207 	case RF3070:
4208 	case RF5350:
4209 	case RF5360:
4210 	case RF5362:
4211 	case RF5370:
4212 	case RF5372:
4213 	case RF5390:
4214 	case RF5392:
4215 		rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
4216 		break;
4217 	case RF5592:
4218 		rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
4219 		break;
4220 	case RF7620:
4221 		rt2800_config_channel_rf7620(rt2x00dev, conf, rf, info);
4222 		break;
4223 	default:
4224 		rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
4225 	}
4226 
4227 	if (rt2x00_rf(rt2x00dev, RF3070) ||
4228 	    rt2x00_rf(rt2x00dev, RF3290) ||
4229 	    rt2x00_rf(rt2x00dev, RF3322) ||
4230 	    rt2x00_rf(rt2x00dev, RF5350) ||
4231 	    rt2x00_rf(rt2x00dev, RF5360) ||
4232 	    rt2x00_rf(rt2x00dev, RF5362) ||
4233 	    rt2x00_rf(rt2x00dev, RF5370) ||
4234 	    rt2x00_rf(rt2x00dev, RF5372) ||
4235 	    rt2x00_rf(rt2x00dev, RF5390) ||
4236 	    rt2x00_rf(rt2x00dev, RF5392)) {
4237 		rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
4238 		if (rt2x00_rf(rt2x00dev, RF3322)) {
4239 			rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_TX_H20M,
4240 					  conf_is_ht40(conf));
4241 			rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_RX_H20M,
4242 					  conf_is_ht40(conf));
4243 		} else {
4244 			rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M,
4245 					  conf_is_ht40(conf));
4246 			rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M,
4247 					  conf_is_ht40(conf));
4248 		}
4249 		rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
4250 
4251 		rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
4252 		rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
4253 		rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
4254 	}
4255 
4256 	/*
4257 	 * Change BBP settings
4258 	 */
4259 
4260 	if (rt2x00_rt(rt2x00dev, RT3352)) {
4261 		rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
4262 		rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
4263 		rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
4264 
4265 		rt2800_bbp_write(rt2x00dev, 27, 0x0);
4266 		rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
4267 		rt2800_bbp_write(rt2x00dev, 27, 0x20);
4268 		rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
4269 		rt2800_bbp_write(rt2x00dev, 86, 0x38);
4270 		rt2800_bbp_write(rt2x00dev, 83, 0x6a);
4271 	} else if (rt2x00_rt(rt2x00dev, RT3593)) {
4272 		if (rf->channel > 14) {
4273 			/* Disable CCK Packet detection on 5GHz */
4274 			rt2800_bbp_write(rt2x00dev, 70, 0x00);
4275 		} else {
4276 			rt2800_bbp_write(rt2x00dev, 70, 0x0a);
4277 		}
4278 
4279 		if (conf_is_ht40(conf))
4280 			rt2800_bbp_write(rt2x00dev, 105, 0x04);
4281 		else
4282 			rt2800_bbp_write(rt2x00dev, 105, 0x34);
4283 
4284 		rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
4285 		rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
4286 		rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
4287 		rt2800_bbp_write(rt2x00dev, 77, 0x98);
4288 	} else if (rt2x00_rt(rt2x00dev, RT3883)) {
4289 		rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
4290 		rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
4291 		rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
4292 
4293 		if (rt2x00dev->default_ant.rx_chain_num > 1)
4294 			rt2800_bbp_write(rt2x00dev, 86, 0x46);
4295 		else
4296 			rt2800_bbp_write(rt2x00dev, 86, 0);
4297 	} else {
4298 		rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
4299 		rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
4300 		rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
4301 		if (rt2x00_rt(rt2x00dev, RT6352))
4302 			rt2800_bbp_write(rt2x00dev, 86, 0x38);
4303 		else
4304 			rt2800_bbp_write(rt2x00dev, 86, 0);
4305 	}
4306 
4307 	if (rf->channel <= 14) {
4308 		if (!rt2x00_rt(rt2x00dev, RT5390) &&
4309 		    !rt2x00_rt(rt2x00dev, RT5392) &&
4310 		    !rt2x00_rt(rt2x00dev, RT6352)) {
4311 			if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
4312 				rt2800_bbp_write(rt2x00dev, 82, 0x62);
4313 				rt2800_bbp_write(rt2x00dev, 82, 0x62);
4314 				rt2800_bbp_write(rt2x00dev, 75, 0x46);
4315 			} else {
4316 				if (rt2x00_rt(rt2x00dev, RT3593))
4317 					rt2800_bbp_write(rt2x00dev, 82, 0x62);
4318 				else
4319 					rt2800_bbp_write(rt2x00dev, 82, 0x84);
4320 				rt2800_bbp_write(rt2x00dev, 75, 0x50);
4321 			}
4322 			if (rt2x00_rt(rt2x00dev, RT3593) ||
4323 			    rt2x00_rt(rt2x00dev, RT3883))
4324 				rt2800_bbp_write(rt2x00dev, 83, 0x8a);
4325 		}
4326 
4327 	} else {
4328 		if (rt2x00_rt(rt2x00dev, RT3572))
4329 			rt2800_bbp_write(rt2x00dev, 82, 0x94);
4330 		else if (rt2x00_rt(rt2x00dev, RT3593) ||
4331 			 rt2x00_rt(rt2x00dev, RT3883))
4332 			rt2800_bbp_write(rt2x00dev, 82, 0x82);
4333 		else if (!rt2x00_rt(rt2x00dev, RT6352))
4334 			rt2800_bbp_write(rt2x00dev, 82, 0xf2);
4335 
4336 		if (rt2x00_rt(rt2x00dev, RT3593) ||
4337 		    rt2x00_rt(rt2x00dev, RT3883))
4338 			rt2800_bbp_write(rt2x00dev, 83, 0x9a);
4339 
4340 		if (rt2x00_has_cap_external_lna_a(rt2x00dev))
4341 			rt2800_bbp_write(rt2x00dev, 75, 0x46);
4342 		else
4343 			rt2800_bbp_write(rt2x00dev, 75, 0x50);
4344 	}
4345 
4346 	reg = rt2800_register_read(rt2x00dev, TX_BAND_CFG);
4347 	rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
4348 	rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
4349 	rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
4350 	rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
4351 
4352 	if (rt2x00_rt(rt2x00dev, RT3572))
4353 		rt2800_rfcsr_write(rt2x00dev, 8, 0);
4354 
4355 	if (rt2x00_rt(rt2x00dev, RT6352)) {
4356 		tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
4357 		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFRX_EN, 1);
4358 	} else {
4359 		tx_pin = 0;
4360 	}
4361 
4362 	switch (rt2x00dev->default_ant.tx_chain_num) {
4363 	case 3:
4364 		/* Turn on tertiary PAs */
4365 		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN,
4366 				   rf->channel > 14);
4367 		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN,
4368 				   rf->channel <= 14);
4369 		fallthrough;
4370 	case 2:
4371 		/* Turn on secondary PAs */
4372 		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
4373 				   rf->channel > 14);
4374 		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
4375 				   rf->channel <= 14);
4376 		fallthrough;
4377 	case 1:
4378 		/* Turn on primary PAs */
4379 		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN,
4380 				   rf->channel > 14);
4381 		if (rt2x00_has_cap_bt_coexist(rt2x00dev))
4382 			rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
4383 		else
4384 			rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
4385 					   rf->channel <= 14);
4386 		break;
4387 	}
4388 
4389 	switch (rt2x00dev->default_ant.rx_chain_num) {
4390 	case 3:
4391 		/* Turn on tertiary LNAs */
4392 		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN, 1);
4393 		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN, 1);
4394 		fallthrough;
4395 	case 2:
4396 		/* Turn on secondary LNAs */
4397 		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
4398 		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
4399 		fallthrough;
4400 	case 1:
4401 		/* Turn on primary LNAs */
4402 		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
4403 		rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
4404 		break;
4405 	}
4406 
4407 	rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
4408 	rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
4409 
4410 	rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
4411 
4412 	if (rt2x00_rt(rt2x00dev, RT3572)) {
4413 		rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
4414 
4415 		/* AGC init */
4416 		if (rf->channel <= 14)
4417 			reg = 0x1c + (2 * rt2x00dev->lna_gain);
4418 		else
4419 			reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
4420 
4421 		rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
4422 	}
4423 
4424 	if (rt2x00_rt(rt2x00dev, RT3593)) {
4425 		reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
4426 
4427 		/* Band selection */
4428 		if (rt2x00_is_usb(rt2x00dev) ||
4429 		    rt2x00_is_pcie(rt2x00dev)) {
4430 			/* GPIO #8 controls all paths */
4431 			rt2x00_set_field32(&reg, GPIO_CTRL_DIR8, 0);
4432 			if (rf->channel <= 14)
4433 				rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 1);
4434 			else
4435 				rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 0);
4436 		}
4437 
4438 		/* LNA PE control. */
4439 		if (rt2x00_is_usb(rt2x00dev)) {
4440 			/* GPIO #4 controls PE0 and PE1,
4441 			 * GPIO #7 controls PE2
4442 			 */
4443 			rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);
4444 			rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
4445 
4446 			rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);
4447 			rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
4448 		} else if (rt2x00_is_pcie(rt2x00dev)) {
4449 			/* GPIO #4 controls PE0, PE1 and PE2 */
4450 			rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);
4451 			rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);
4452 		}
4453 
4454 		rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
4455 
4456 		/* AGC init */
4457 		if (rf->channel <= 14)
4458 			reg = 0x1c + 2 * rt2x00dev->lna_gain;
4459 		else
4460 			reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
4461 
4462 		rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
4463 
4464 		usleep_range(1000, 1500);
4465 	}
4466 
4467 	if (rt2x00_rt(rt2x00dev, RT3883)) {
4468 		if (!conf_is_ht40(conf))
4469 			rt2800_bbp_write(rt2x00dev, 105, 0x34);
4470 		else
4471 			rt2800_bbp_write(rt2x00dev, 105, 0x04);
4472 
4473 		/* AGC init */
4474 		if (rf->channel <= 14)
4475 			reg = 0x2e + rt2x00dev->lna_gain;
4476 		else
4477 			reg = 0x20 + ((rt2x00dev->lna_gain * 5) / 3);
4478 
4479 		rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
4480 
4481 		usleep_range(1000, 1500);
4482 	}
4483 
4484 	if (rt2x00_rt(rt2x00dev, RT5592)) {
4485 		bbp = conf_is_ht40(conf) ? 0x10 : 0x1a;
4486 		rt2800_bbp_glrt_write(rt2x00dev, 141, bbp);
4487 
4488 		bbp = (rf->channel <= 14 ? 0x1c : 0x24) + 2 * rt2x00dev->lna_gain;
4489 		rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, bbp);
4490 
4491 		rt2800_iq_calibrate(rt2x00dev, rf->channel);
4492 	}
4493 
4494 	if (rt2x00_rt(rt2x00dev, RT6352)) {
4495 		/* BBP for GLRT BW */
4496 		bbp = conf_is_ht40(conf) ?
4497 		      0x10 : rt2x00_has_cap_external_lna_bg(rt2x00dev) ?
4498 		      0x15 : 0x1a;
4499 		rt2800_bbp_glrt_write(rt2x00dev, 141, bbp);
4500 
4501 		bbp = conf_is_ht40(conf) ? 0x2f : 0x40;
4502 		rt2800_bbp_glrt_write(rt2x00dev, 157, bbp);
4503 
4504 		if (rt2x00dev->default_ant.rx_chain_num == 1) {
4505 			rt2800_bbp_write(rt2x00dev, 91, 0x07);
4506 			rt2800_bbp_write(rt2x00dev, 95, 0x1a);
4507 			rt2800_bbp_glrt_write(rt2x00dev, 128, 0xa0);
4508 			rt2800_bbp_glrt_write(rt2x00dev, 170, 0x12);
4509 			rt2800_bbp_glrt_write(rt2x00dev, 171, 0x10);
4510 		} else {
4511 			rt2800_bbp_write(rt2x00dev, 91, 0x06);
4512 			rt2800_bbp_write(rt2x00dev, 95, 0x9a);
4513 			rt2800_bbp_glrt_write(rt2x00dev, 128, 0xe0);
4514 			rt2800_bbp_glrt_write(rt2x00dev, 170, 0x30);
4515 			rt2800_bbp_glrt_write(rt2x00dev, 171, 0x30);
4516 		}
4517 
4518 		/* AGC init */
4519 		bbp = rf->channel <= 14 ? 0x04 + 2 * rt2x00dev->lna_gain : 0;
4520 		rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, bbp);
4521 
4522 		usleep_range(1000, 1500);
4523 	}
4524 
4525 	bbp = rt2800_bbp_read(rt2x00dev, 4);
4526 	rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
4527 	rt2800_bbp_write(rt2x00dev, 4, bbp);
4528 
4529 	bbp = rt2800_bbp_read(rt2x00dev, 3);
4530 	rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
4531 	rt2800_bbp_write(rt2x00dev, 3, bbp);
4532 
4533 	if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
4534 		if (conf_is_ht40(conf)) {
4535 			rt2800_bbp_write(rt2x00dev, 69, 0x1a);
4536 			rt2800_bbp_write(rt2x00dev, 70, 0x0a);
4537 			rt2800_bbp_write(rt2x00dev, 73, 0x16);
4538 		} else {
4539 			rt2800_bbp_write(rt2x00dev, 69, 0x16);
4540 			rt2800_bbp_write(rt2x00dev, 70, 0x08);
4541 			rt2800_bbp_write(rt2x00dev, 73, 0x11);
4542 		}
4543 	}
4544 
4545 	usleep_range(1000, 1500);
4546 
4547 	/*
4548 	 * Clear channel statistic counters
4549 	 */
4550 	reg = rt2800_register_read(rt2x00dev, CH_IDLE_STA);
4551 	reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA);
4552 	reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC);
4553 
4554 	/*
4555 	 * Clear update flag
4556 	 */
4557 	if (rt2x00_rt(rt2x00dev, RT3352) ||
4558 	    rt2x00_rt(rt2x00dev, RT5350)) {
4559 		bbp = rt2800_bbp_read(rt2x00dev, 49);
4560 		rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
4561 		rt2800_bbp_write(rt2x00dev, 49, bbp);
4562 	}
4563 }
4564 
rt2800_get_gain_calibration_delta(struct rt2x00_dev * rt2x00dev)4565 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
4566 {
4567 	u8 tssi_bounds[9];
4568 	u8 current_tssi;
4569 	u16 eeprom;
4570 	u8 step;
4571 	int i;
4572 
4573 	/*
4574 	 * First check if temperature compensation is supported.
4575 	 */
4576 	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
4577 	if (!rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC))
4578 		return 0;
4579 
4580 	/*
4581 	 * Read TSSI boundaries for temperature compensation from
4582 	 * the EEPROM.
4583 	 *
4584 	 * Array idx               0    1    2    3    4    5    6    7    8
4585 	 * Matching Delta value   -4   -3   -2   -1    0   +1   +2   +3   +4
4586 	 * Example TSSI bounds  0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
4587 	 */
4588 	if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
4589 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1);
4590 		tssi_bounds[0] = rt2x00_get_field16(eeprom,
4591 					EEPROM_TSSI_BOUND_BG1_MINUS4);
4592 		tssi_bounds[1] = rt2x00_get_field16(eeprom,
4593 					EEPROM_TSSI_BOUND_BG1_MINUS3);
4594 
4595 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2);
4596 		tssi_bounds[2] = rt2x00_get_field16(eeprom,
4597 					EEPROM_TSSI_BOUND_BG2_MINUS2);
4598 		tssi_bounds[3] = rt2x00_get_field16(eeprom,
4599 					EEPROM_TSSI_BOUND_BG2_MINUS1);
4600 
4601 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3);
4602 		tssi_bounds[4] = rt2x00_get_field16(eeprom,
4603 					EEPROM_TSSI_BOUND_BG3_REF);
4604 		tssi_bounds[5] = rt2x00_get_field16(eeprom,
4605 					EEPROM_TSSI_BOUND_BG3_PLUS1);
4606 
4607 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4);
4608 		tssi_bounds[6] = rt2x00_get_field16(eeprom,
4609 					EEPROM_TSSI_BOUND_BG4_PLUS2);
4610 		tssi_bounds[7] = rt2x00_get_field16(eeprom,
4611 					EEPROM_TSSI_BOUND_BG4_PLUS3);
4612 
4613 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5);
4614 		tssi_bounds[8] = rt2x00_get_field16(eeprom,
4615 					EEPROM_TSSI_BOUND_BG5_PLUS4);
4616 
4617 		step = rt2x00_get_field16(eeprom,
4618 					  EEPROM_TSSI_BOUND_BG5_AGC_STEP);
4619 	} else {
4620 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1);
4621 		tssi_bounds[0] = rt2x00_get_field16(eeprom,
4622 					EEPROM_TSSI_BOUND_A1_MINUS4);
4623 		tssi_bounds[1] = rt2x00_get_field16(eeprom,
4624 					EEPROM_TSSI_BOUND_A1_MINUS3);
4625 
4626 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2);
4627 		tssi_bounds[2] = rt2x00_get_field16(eeprom,
4628 					EEPROM_TSSI_BOUND_A2_MINUS2);
4629 		tssi_bounds[3] = rt2x00_get_field16(eeprom,
4630 					EEPROM_TSSI_BOUND_A2_MINUS1);
4631 
4632 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3);
4633 		tssi_bounds[4] = rt2x00_get_field16(eeprom,
4634 					EEPROM_TSSI_BOUND_A3_REF);
4635 		tssi_bounds[5] = rt2x00_get_field16(eeprom,
4636 					EEPROM_TSSI_BOUND_A3_PLUS1);
4637 
4638 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4);
4639 		tssi_bounds[6] = rt2x00_get_field16(eeprom,
4640 					EEPROM_TSSI_BOUND_A4_PLUS2);
4641 		tssi_bounds[7] = rt2x00_get_field16(eeprom,
4642 					EEPROM_TSSI_BOUND_A4_PLUS3);
4643 
4644 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5);
4645 		tssi_bounds[8] = rt2x00_get_field16(eeprom,
4646 					EEPROM_TSSI_BOUND_A5_PLUS4);
4647 
4648 		step = rt2x00_get_field16(eeprom,
4649 					  EEPROM_TSSI_BOUND_A5_AGC_STEP);
4650 	}
4651 
4652 	/*
4653 	 * Check if temperature compensation is supported.
4654 	 */
4655 	if (tssi_bounds[4] == 0xff || step == 0xff)
4656 		return 0;
4657 
4658 	/*
4659 	 * Read current TSSI (BBP 49).
4660 	 */
4661 	current_tssi = rt2800_bbp_read(rt2x00dev, 49);
4662 
4663 	/*
4664 	 * Compare TSSI value (BBP49) with the compensation boundaries
4665 	 * from the EEPROM and increase or decrease tx power.
4666 	 */
4667 	for (i = 0; i <= 3; i++) {
4668 		if (current_tssi > tssi_bounds[i])
4669 			break;
4670 	}
4671 
4672 	if (i == 4) {
4673 		for (i = 8; i >= 5; i--) {
4674 			if (current_tssi < tssi_bounds[i])
4675 				break;
4676 		}
4677 	}
4678 
4679 	return (i - 4) * step;
4680 }
4681 
rt2800_get_txpower_bw_comp(struct rt2x00_dev * rt2x00dev,enum nl80211_band band)4682 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
4683 				      enum nl80211_band band)
4684 {
4685 	u16 eeprom;
4686 	u8 comp_en;
4687 	u8 comp_type;
4688 	int comp_value = 0;
4689 
4690 	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA);
4691 
4692 	/*
4693 	 * HT40 compensation not required.
4694 	 */
4695 	if (eeprom == 0xffff ||
4696 	    !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
4697 		return 0;
4698 
4699 	if (band == NL80211_BAND_2GHZ) {
4700 		comp_en = rt2x00_get_field16(eeprom,
4701 				 EEPROM_TXPOWER_DELTA_ENABLE_2G);
4702 		if (comp_en) {
4703 			comp_type = rt2x00_get_field16(eeprom,
4704 					   EEPROM_TXPOWER_DELTA_TYPE_2G);
4705 			comp_value = rt2x00_get_field16(eeprom,
4706 					    EEPROM_TXPOWER_DELTA_VALUE_2G);
4707 			if (!comp_type)
4708 				comp_value = -comp_value;
4709 		}
4710 	} else {
4711 		comp_en = rt2x00_get_field16(eeprom,
4712 				 EEPROM_TXPOWER_DELTA_ENABLE_5G);
4713 		if (comp_en) {
4714 			comp_type = rt2x00_get_field16(eeprom,
4715 					   EEPROM_TXPOWER_DELTA_TYPE_5G);
4716 			comp_value = rt2x00_get_field16(eeprom,
4717 					    EEPROM_TXPOWER_DELTA_VALUE_5G);
4718 			if (!comp_type)
4719 				comp_value = -comp_value;
4720 		}
4721 	}
4722 
4723 	return comp_value;
4724 }
4725 
rt2800_get_txpower_reg_delta(struct rt2x00_dev * rt2x00dev,int power_level,int max_power)4726 static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev,
4727 					int power_level, int max_power)
4728 {
4729 	int delta;
4730 
4731 	if (rt2x00_has_cap_power_limit(rt2x00dev))
4732 		return 0;
4733 
4734 	/*
4735 	 * XXX: We don't know the maximum transmit power of our hardware since
4736 	 * the EEPROM doesn't expose it. We only know that we are calibrated
4737 	 * to 100% tx power.
4738 	 *
4739 	 * Hence, we assume the regulatory limit that cfg80211 calulated for
4740 	 * the current channel is our maximum and if we are requested to lower
4741 	 * the value we just reduce our tx power accordingly.
4742 	 */
4743 	delta = power_level - max_power;
4744 	return min(delta, 0);
4745 }
4746 
rt2800_compensate_txpower(struct rt2x00_dev * rt2x00dev,int is_rate_b,enum nl80211_band band,int power_level,u8 txpower,int delta)4747 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
4748 				   enum nl80211_band band, int power_level,
4749 				   u8 txpower, int delta)
4750 {
4751 	u16 eeprom;
4752 	u8 criterion;
4753 	u8 eirp_txpower;
4754 	u8 eirp_txpower_criterion;
4755 	u8 reg_limit;
4756 
4757 	if (rt2x00_rt(rt2x00dev, RT3593))
4758 		return min_t(u8, txpower, 0xc);
4759 
4760 	if (rt2x00_rt(rt2x00dev, RT3883))
4761 		return min_t(u8, txpower, 0xf);
4762 
4763 	if (rt2x00_has_cap_power_limit(rt2x00dev)) {
4764 		/*
4765 		 * Check if eirp txpower exceed txpower_limit.
4766 		 * We use OFDM 6M as criterion and its eirp txpower
4767 		 * is stored at EEPROM_EIRP_MAX_TX_POWER.
4768 		 * .11b data rate need add additional 4dbm
4769 		 * when calculating eirp txpower.
4770 		 */
4771 		eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
4772 						       EEPROM_TXPOWER_BYRATE,
4773 						       1);
4774 		criterion = rt2x00_get_field16(eeprom,
4775 					       EEPROM_TXPOWER_BYRATE_RATE0);
4776 
4777 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER);
4778 
4779 		if (band == NL80211_BAND_2GHZ)
4780 			eirp_txpower_criterion = rt2x00_get_field16(eeprom,
4781 						 EEPROM_EIRP_MAX_TX_POWER_2GHZ);
4782 		else
4783 			eirp_txpower_criterion = rt2x00_get_field16(eeprom,
4784 						 EEPROM_EIRP_MAX_TX_POWER_5GHZ);
4785 
4786 		eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
4787 			       (is_rate_b ? 4 : 0) + delta;
4788 
4789 		reg_limit = (eirp_txpower > power_level) ?
4790 					(eirp_txpower - power_level) : 0;
4791 	} else
4792 		reg_limit = 0;
4793 
4794 	txpower = max(0, txpower + delta - reg_limit);
4795 	return min_t(u8, txpower, 0xc);
4796 }
4797 
4798 
4799 enum {
4800 	TX_PWR_CFG_0_IDX,
4801 	TX_PWR_CFG_1_IDX,
4802 	TX_PWR_CFG_2_IDX,
4803 	TX_PWR_CFG_3_IDX,
4804 	TX_PWR_CFG_4_IDX,
4805 	TX_PWR_CFG_5_IDX,
4806 	TX_PWR_CFG_6_IDX,
4807 	TX_PWR_CFG_7_IDX,
4808 	TX_PWR_CFG_8_IDX,
4809 	TX_PWR_CFG_9_IDX,
4810 	TX_PWR_CFG_0_EXT_IDX,
4811 	TX_PWR_CFG_1_EXT_IDX,
4812 	TX_PWR_CFG_2_EXT_IDX,
4813 	TX_PWR_CFG_3_EXT_IDX,
4814 	TX_PWR_CFG_4_EXT_IDX,
4815 	TX_PWR_CFG_IDX_COUNT,
4816 };
4817 
rt2800_config_txpower_rt3593(struct rt2x00_dev * rt2x00dev,struct ieee80211_channel * chan,int power_level)4818 static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev,
4819 					 struct ieee80211_channel *chan,
4820 					 int power_level)
4821 {
4822 	u8 txpower;
4823 	u16 eeprom;
4824 	u32 regs[TX_PWR_CFG_IDX_COUNT];
4825 	unsigned int offset;
4826 	enum nl80211_band band = chan->band;
4827 	int delta;
4828 	int i;
4829 
4830 	memset(regs, '\0', sizeof(regs));
4831 
4832 	/* TODO: adapt TX power reduction from the rt28xx code */
4833 
4834 	/* calculate temperature compensation delta */
4835 	delta = rt2800_get_gain_calibration_delta(rt2x00dev);
4836 
4837 	if (band == NL80211_BAND_5GHZ)
4838 		offset = 16;
4839 	else
4840 		offset = 0;
4841 
4842 	if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
4843 		offset += 8;
4844 
4845 	/* read the next four txpower values */
4846 	eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4847 					       offset);
4848 
4849 	/* CCK 1MBS,2MBS */
4850 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4851 	txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
4852 					    txpower, delta);
4853 	rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4854 			   TX_PWR_CFG_0_CCK1_CH0, txpower);
4855 	rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4856 			   TX_PWR_CFG_0_CCK1_CH1, txpower);
4857 	rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
4858 			   TX_PWR_CFG_0_EXT_CCK1_CH2, txpower);
4859 
4860 	/* CCK 5.5MBS,11MBS */
4861 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4862 	txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
4863 					    txpower, delta);
4864 	rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4865 			   TX_PWR_CFG_0_CCK5_CH0, txpower);
4866 	rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4867 			   TX_PWR_CFG_0_CCK5_CH1, txpower);
4868 	rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
4869 			   TX_PWR_CFG_0_EXT_CCK5_CH2, txpower);
4870 
4871 	/* OFDM 6MBS,9MBS */
4872 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4873 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4874 					    txpower, delta);
4875 	rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4876 			   TX_PWR_CFG_0_OFDM6_CH0, txpower);
4877 	rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4878 			   TX_PWR_CFG_0_OFDM6_CH1, txpower);
4879 	rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
4880 			   TX_PWR_CFG_0_EXT_OFDM6_CH2, txpower);
4881 
4882 	/* OFDM 12MBS,18MBS */
4883 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4884 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4885 					    txpower, delta);
4886 	rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4887 			   TX_PWR_CFG_0_OFDM12_CH0, txpower);
4888 	rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4889 			   TX_PWR_CFG_0_OFDM12_CH1, txpower);
4890 	rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
4891 			   TX_PWR_CFG_0_EXT_OFDM12_CH2, txpower);
4892 
4893 	/* read the next four txpower values */
4894 	eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4895 					       offset + 1);
4896 
4897 	/* OFDM 24MBS,36MBS */
4898 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4899 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4900 					    txpower, delta);
4901 	rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4902 			   TX_PWR_CFG_1_OFDM24_CH0, txpower);
4903 	rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4904 			   TX_PWR_CFG_1_OFDM24_CH1, txpower);
4905 	rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
4906 			   TX_PWR_CFG_1_EXT_OFDM24_CH2, txpower);
4907 
4908 	/* OFDM 48MBS */
4909 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4910 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4911 					    txpower, delta);
4912 	rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4913 			   TX_PWR_CFG_1_OFDM48_CH0, txpower);
4914 	rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4915 			   TX_PWR_CFG_1_OFDM48_CH1, txpower);
4916 	rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
4917 			   TX_PWR_CFG_1_EXT_OFDM48_CH2, txpower);
4918 
4919 	/* OFDM 54MBS */
4920 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4921 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4922 					    txpower, delta);
4923 	rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4924 			   TX_PWR_CFG_7_OFDM54_CH0, txpower);
4925 	rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4926 			   TX_PWR_CFG_7_OFDM54_CH1, txpower);
4927 	rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4928 			   TX_PWR_CFG_7_OFDM54_CH2, txpower);
4929 
4930 	/* read the next four txpower values */
4931 	eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4932 					       offset + 2);
4933 
4934 	/* MCS 0,1 */
4935 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4936 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4937 					    txpower, delta);
4938 	rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4939 			   TX_PWR_CFG_1_MCS0_CH0, txpower);
4940 	rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4941 			   TX_PWR_CFG_1_MCS0_CH1, txpower);
4942 	rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
4943 			   TX_PWR_CFG_1_EXT_MCS0_CH2, txpower);
4944 
4945 	/* MCS 2,3 */
4946 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4947 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4948 					    txpower, delta);
4949 	rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4950 			   TX_PWR_CFG_1_MCS2_CH0, txpower);
4951 	rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4952 			   TX_PWR_CFG_1_MCS2_CH1, txpower);
4953 	rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
4954 			   TX_PWR_CFG_1_EXT_MCS2_CH2, txpower);
4955 
4956 	/* MCS 4,5 */
4957 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4958 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4959 					    txpower, delta);
4960 	rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4961 			   TX_PWR_CFG_2_MCS4_CH0, txpower);
4962 	rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4963 			   TX_PWR_CFG_2_MCS4_CH1, txpower);
4964 	rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
4965 			   TX_PWR_CFG_2_EXT_MCS4_CH2, txpower);
4966 
4967 	/* MCS 6 */
4968 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4969 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4970 					    txpower, delta);
4971 	rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4972 			   TX_PWR_CFG_2_MCS6_CH0, txpower);
4973 	rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4974 			   TX_PWR_CFG_2_MCS6_CH1, txpower);
4975 	rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
4976 			   TX_PWR_CFG_2_EXT_MCS6_CH2, txpower);
4977 
4978 	/* read the next four txpower values */
4979 	eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4980 					       offset + 3);
4981 
4982 	/* MCS 7 */
4983 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4984 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4985 					    txpower, delta);
4986 	rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4987 			   TX_PWR_CFG_7_MCS7_CH0, txpower);
4988 	rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4989 			   TX_PWR_CFG_7_MCS7_CH1, txpower);
4990 	rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4991 			   TX_PWR_CFG_7_MCS7_CH2, txpower);
4992 
4993 	/* MCS 8,9 */
4994 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4995 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4996 					    txpower, delta);
4997 	rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4998 			   TX_PWR_CFG_2_MCS8_CH0, txpower);
4999 	rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
5000 			   TX_PWR_CFG_2_MCS8_CH1, txpower);
5001 	rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
5002 			   TX_PWR_CFG_2_EXT_MCS8_CH2, txpower);
5003 
5004 	/* MCS 10,11 */
5005 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
5006 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
5007 					    txpower, delta);
5008 	rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
5009 			   TX_PWR_CFG_2_MCS10_CH0, txpower);
5010 	rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
5011 			   TX_PWR_CFG_2_MCS10_CH1, txpower);
5012 	rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
5013 			   TX_PWR_CFG_2_EXT_MCS10_CH2, txpower);
5014 
5015 	/* MCS 12,13 */
5016 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
5017 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
5018 					    txpower, delta);
5019 	rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
5020 			   TX_PWR_CFG_3_MCS12_CH0, txpower);
5021 	rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
5022 			   TX_PWR_CFG_3_MCS12_CH1, txpower);
5023 	rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
5024 			   TX_PWR_CFG_3_EXT_MCS12_CH2, txpower);
5025 
5026 	/* read the next four txpower values */
5027 	eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
5028 					       offset + 4);
5029 
5030 	/* MCS 14 */
5031 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
5032 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
5033 					    txpower, delta);
5034 	rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
5035 			   TX_PWR_CFG_3_MCS14_CH0, txpower);
5036 	rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
5037 			   TX_PWR_CFG_3_MCS14_CH1, txpower);
5038 	rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
5039 			   TX_PWR_CFG_3_EXT_MCS14_CH2, txpower);
5040 
5041 	/* MCS 15 */
5042 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
5043 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
5044 					    txpower, delta);
5045 	rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
5046 			   TX_PWR_CFG_8_MCS15_CH0, txpower);
5047 	rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
5048 			   TX_PWR_CFG_8_MCS15_CH1, txpower);
5049 	rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
5050 			   TX_PWR_CFG_8_MCS15_CH2, txpower);
5051 
5052 	/* MCS 16,17 */
5053 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
5054 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
5055 					    txpower, delta);
5056 	rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
5057 			   TX_PWR_CFG_5_MCS16_CH0, txpower);
5058 	rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
5059 			   TX_PWR_CFG_5_MCS16_CH1, txpower);
5060 	rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
5061 			   TX_PWR_CFG_5_MCS16_CH2, txpower);
5062 
5063 	/* MCS 18,19 */
5064 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
5065 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
5066 					    txpower, delta);
5067 	rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
5068 			   TX_PWR_CFG_5_MCS18_CH0, txpower);
5069 	rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
5070 			   TX_PWR_CFG_5_MCS18_CH1, txpower);
5071 	rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
5072 			   TX_PWR_CFG_5_MCS18_CH2, txpower);
5073 
5074 	/* read the next four txpower values */
5075 	eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
5076 					       offset + 5);
5077 
5078 	/* MCS 20,21 */
5079 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
5080 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
5081 					    txpower, delta);
5082 	rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
5083 			   TX_PWR_CFG_6_MCS20_CH0, txpower);
5084 	rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
5085 			   TX_PWR_CFG_6_MCS20_CH1, txpower);
5086 	rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
5087 			   TX_PWR_CFG_6_MCS20_CH2, txpower);
5088 
5089 	/* MCS 22 */
5090 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
5091 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
5092 					    txpower, delta);
5093 	rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
5094 			   TX_PWR_CFG_6_MCS22_CH0, txpower);
5095 	rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
5096 			   TX_PWR_CFG_6_MCS22_CH1, txpower);
5097 	rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
5098 			   TX_PWR_CFG_6_MCS22_CH2, txpower);
5099 
5100 	/* MCS 23 */
5101 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
5102 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
5103 					    txpower, delta);
5104 	rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
5105 			   TX_PWR_CFG_8_MCS23_CH0, txpower);
5106 	rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
5107 			   TX_PWR_CFG_8_MCS23_CH1, txpower);
5108 	rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
5109 			   TX_PWR_CFG_8_MCS23_CH2, txpower);
5110 
5111 	/* read the next four txpower values */
5112 	eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
5113 					       offset + 6);
5114 
5115 	/* STBC, MCS 0,1 */
5116 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
5117 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
5118 					    txpower, delta);
5119 	rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
5120 			   TX_PWR_CFG_3_STBC0_CH0, txpower);
5121 	rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
5122 			   TX_PWR_CFG_3_STBC0_CH1, txpower);
5123 	rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
5124 			   TX_PWR_CFG_3_EXT_STBC0_CH2, txpower);
5125 
5126 	/* STBC, MCS 2,3 */
5127 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
5128 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
5129 					    txpower, delta);
5130 	rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
5131 			   TX_PWR_CFG_3_STBC2_CH0, txpower);
5132 	rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
5133 			   TX_PWR_CFG_3_STBC2_CH1, txpower);
5134 	rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
5135 			   TX_PWR_CFG_3_EXT_STBC2_CH2, txpower);
5136 
5137 	/* STBC, MCS 4,5 */
5138 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
5139 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
5140 					    txpower, delta);
5141 	rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE0, txpower);
5142 	rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE1, txpower);
5143 	rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE0,
5144 			   txpower);
5145 
5146 	/* STBC, MCS 6 */
5147 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
5148 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
5149 					    txpower, delta);
5150 	rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE2, txpower);
5151 	rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE3, txpower);
5152 	rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE2,
5153 			   txpower);
5154 
5155 	/* read the next four txpower values */
5156 	eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
5157 					       offset + 7);
5158 
5159 	/* STBC, MCS 7 */
5160 	txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
5161 	txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
5162 					    txpower, delta);
5163 	rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
5164 			   TX_PWR_CFG_9_STBC7_CH0, txpower);
5165 	rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
5166 			   TX_PWR_CFG_9_STBC7_CH1, txpower);
5167 	rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
5168 			   TX_PWR_CFG_9_STBC7_CH2, txpower);
5169 
5170 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, regs[TX_PWR_CFG_0_IDX]);
5171 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, regs[TX_PWR_CFG_1_IDX]);
5172 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, regs[TX_PWR_CFG_2_IDX]);
5173 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, regs[TX_PWR_CFG_3_IDX]);
5174 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, regs[TX_PWR_CFG_4_IDX]);
5175 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_5, regs[TX_PWR_CFG_5_IDX]);
5176 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_6, regs[TX_PWR_CFG_6_IDX]);
5177 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, regs[TX_PWR_CFG_7_IDX]);
5178 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, regs[TX_PWR_CFG_8_IDX]);
5179 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, regs[TX_PWR_CFG_9_IDX]);
5180 
5181 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_0_EXT,
5182 			      regs[TX_PWR_CFG_0_EXT_IDX]);
5183 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_1_EXT,
5184 			      regs[TX_PWR_CFG_1_EXT_IDX]);
5185 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_2_EXT,
5186 			      regs[TX_PWR_CFG_2_EXT_IDX]);
5187 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_3_EXT,
5188 			      regs[TX_PWR_CFG_3_EXT_IDX]);
5189 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_4_EXT,
5190 			      regs[TX_PWR_CFG_4_EXT_IDX]);
5191 
5192 	for (i = 0; i < TX_PWR_CFG_IDX_COUNT; i++)
5193 		rt2x00_dbg(rt2x00dev,
5194 			   "band:%cGHz, BW:%c0MHz, TX_PWR_CFG_%d%s = %08lx\n",
5195 			   (band == NL80211_BAND_5GHZ) ? '5' : '2',
5196 			   (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) ?
5197 								'4' : '2',
5198 			   (i > TX_PWR_CFG_9_IDX) ?
5199 					(i - TX_PWR_CFG_9_IDX - 1) : i,
5200 			   (i > TX_PWR_CFG_9_IDX) ? "_EXT" : "",
5201 			   (unsigned long) regs[i]);
5202 }
5203 
rt2800_config_txpower_rt6352(struct rt2x00_dev * rt2x00dev,struct ieee80211_channel * chan,int power_level)5204 static void rt2800_config_txpower_rt6352(struct rt2x00_dev *rt2x00dev,
5205 					 struct ieee80211_channel *chan,
5206 					 int power_level)
5207 {
5208 	u32 reg, pwreg;
5209 	u16 eeprom;
5210 	u32 data, gdata;
5211 	u8 t, i;
5212 	enum nl80211_band band = chan->band;
5213 	int delta;
5214 
5215 	/* Warn user if bw_comp is set in EEPROM */
5216 	delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
5217 
5218 	if (delta)
5219 		rt2x00_warn(rt2x00dev, "ignoring EEPROM HT40 power delta: %d\n",
5220 			    delta);
5221 
5222 	/* populate TX_PWR_CFG_0 up to TX_PWR_CFG_4 from EEPROM for HT20, limit
5223 	 * value to 0x3f and replace 0x20 by 0x21 as this is what the vendor
5224 	 * driver does as well, though it looks kinda wrong.
5225 	 * Maybe some misunderstanding of what a signed 8-bit value is? Maybe
5226 	 * the hardware has a problem handling 0x20, and as the code initially
5227 	 * used a fixed offset between HT20 and HT40 rates they had to work-
5228 	 * around that issue and most likely just forgot about it later on.
5229 	 * Maybe we should use rt2800_get_txpower_bw_comp() here as well,
5230 	 * however, the corresponding EEPROM value is not respected by the
5231 	 * vendor driver, so maybe this is rather being taken care of the
5232 	 * TXALC and the driver doesn't need to handle it...?
5233 	 * Though this is all very awkward, just do as they did, as that's what
5234 	 * board vendors expected when they populated the EEPROM...
5235 	 */
5236 	for (i = 0; i < 5; i++) {
5237 		eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
5238 						       EEPROM_TXPOWER_BYRATE,
5239 						       i * 2);
5240 
5241 		data = eeprom;
5242 
5243 		t = eeprom & 0x3f;
5244 		if (t == 32)
5245 			t++;
5246 
5247 		gdata = t;
5248 
5249 		t = (eeprom & 0x3f00) >> 8;
5250 		if (t == 32)
5251 			t++;
5252 
5253 		gdata |= (t << 8);
5254 
5255 		eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
5256 						       EEPROM_TXPOWER_BYRATE,
5257 						       (i * 2) + 1);
5258 
5259 		t = eeprom & 0x3f;
5260 		if (t == 32)
5261 			t++;
5262 
5263 		gdata |= (t << 16);
5264 
5265 		t = (eeprom & 0x3f00) >> 8;
5266 		if (t == 32)
5267 			t++;
5268 
5269 		gdata |= (t << 24);
5270 		data |= (eeprom << 16);
5271 
5272 		if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) {
5273 			/* HT20 */
5274 			if (data != 0xffffffff)
5275 				rt2800_register_write(rt2x00dev,
5276 						      TX_PWR_CFG_0 + (i * 4),
5277 						      data);
5278 		} else {
5279 			/* HT40 */
5280 			if (gdata != 0xffffffff)
5281 				rt2800_register_write(rt2x00dev,
5282 						      TX_PWR_CFG_0 + (i * 4),
5283 						      gdata);
5284 		}
5285 	}
5286 
5287 	/* Aparently Ralink ran out of space in the BYRATE calibration section
5288 	 * of the EERPOM which is copied to the corresponding TX_PWR_CFG_x
5289 	 * registers. As recent 2T chips use 8-bit instead of 4-bit values for
5290 	 * power-offsets more space would be needed. Ralink decided to keep the
5291 	 * EEPROM layout untouched and rather have some shared values covering
5292 	 * multiple bitrates.
5293 	 * Populate the registers not covered by the EEPROM in the same way the
5294 	 * vendor driver does.
5295 	 */
5296 
5297 	/* For OFDM 54MBS use value from OFDM 48MBS */
5298 	pwreg = 0;
5299 	reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_1);
5300 	t = rt2x00_get_field32(reg, TX_PWR_CFG_1B_48MBS);
5301 	rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_54MBS, t);
5302 
5303 	/* For MCS 7 use value from MCS 6 */
5304 	reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_2);
5305 	t = rt2x00_get_field32(reg, TX_PWR_CFG_2B_MCS6_MCS7);
5306 	rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_MCS7, t);
5307 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, pwreg);
5308 
5309 	/* For MCS 15 use value from MCS 14 */
5310 	pwreg = 0;
5311 	reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_3);
5312 	t = rt2x00_get_field32(reg, TX_PWR_CFG_3B_MCS14);
5313 	rt2x00_set_field32(&pwreg, TX_PWR_CFG_8B_MCS15, t);
5314 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, pwreg);
5315 
5316 	/* For STBC MCS 7 use value from STBC MCS 6 */
5317 	pwreg = 0;
5318 	reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_4);
5319 	t = rt2x00_get_field32(reg, TX_PWR_CFG_4B_STBC_MCS6);
5320 	rt2x00_set_field32(&pwreg, TX_PWR_CFG_9B_STBC_MCS7, t);
5321 	rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, pwreg);
5322 
5323 	rt2800_config_alc_rt6352(rt2x00dev, chan, power_level);
5324 
5325 	/* TODO: temperature compensation code! */
5326 }
5327 
5328 /*
5329  * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
5330  * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
5331  * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power
5332  * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm.
5333  * Reference per rate transmit power values are located in the EEPROM at
5334  * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to
5335  * current conditions (i.e. band, bandwidth, temperature, user settings).
5336  */
rt2800_config_txpower_rt28xx(struct rt2x00_dev * rt2x00dev,struct ieee80211_channel * chan,int power_level)5337 static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev,
5338 					 struct ieee80211_channel *chan,
5339 					 int power_level)
5340 {
5341 	u8 txpower, r1;
5342 	u16 eeprom;
5343 	u32 reg, offset;
5344 	int i, is_rate_b, delta, power_ctrl;
5345 	enum nl80211_band band = chan->band;
5346 
5347 	/*
5348 	 * Calculate HT40 compensation. For 40MHz we need to add or subtract
5349 	 * value read from EEPROM (different for 2GHz and for 5GHz).
5350 	 */
5351 	delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
5352 
5353 	/*
5354 	 * Calculate temperature compensation. Depends on measurement of current
5355 	 * TSSI (Transmitter Signal Strength Indication) we know TX power (due
5356 	 * to temperature or maybe other factors) is smaller or bigger than
5357 	 * expected. We adjust it, based on TSSI reference and boundaries values
5358 	 * provided in EEPROM.
5359 	 */
5360 	switch (rt2x00dev->chip.rt) {
5361 	case RT2860:
5362 	case RT2872:
5363 	case RT2883:
5364 	case RT3070:
5365 	case RT3071:
5366 	case RT3090:
5367 	case RT3572:
5368 		delta += rt2800_get_gain_calibration_delta(rt2x00dev);
5369 		break;
5370 	default:
5371 		/* TODO: temperature compensation code for other chips. */
5372 		break;
5373 	}
5374 
5375 	/*
5376 	 * Decrease power according to user settings, on devices with unknown
5377 	 * maximum tx power. For other devices we take user power_level into
5378 	 * consideration on rt2800_compensate_txpower().
5379 	 */
5380 	delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level,
5381 					      chan->max_power);
5382 
5383 	/*
5384 	 * BBP_R1 controls TX power for all rates, it allow to set the following
5385 	 * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively.
5386 	 *
5387 	 * TODO: we do not use +6 dBm option to do not increase power beyond
5388 	 * regulatory limit, however this could be utilized for devices with
5389 	 * CAPABILITY_POWER_LIMIT.
5390 	 */
5391 	if (delta <= -12) {
5392 		power_ctrl = 2;
5393 		delta += 12;
5394 	} else if (delta <= -6) {
5395 		power_ctrl = 1;
5396 		delta += 6;
5397 	} else {
5398 		power_ctrl = 0;
5399 	}
5400 	r1 = rt2800_bbp_read(rt2x00dev, 1);
5401 	rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl);
5402 	rt2800_bbp_write(rt2x00dev, 1, r1);
5403 
5404 	offset = TX_PWR_CFG_0;
5405 
5406 	for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
5407 		/* just to be safe */
5408 		if (offset > TX_PWR_CFG_4)
5409 			break;
5410 
5411 		reg = rt2800_register_read(rt2x00dev, offset);
5412 
5413 		/* read the next four txpower values */
5414 		eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
5415 						       EEPROM_TXPOWER_BYRATE,
5416 						       i);
5417 
5418 		is_rate_b = i ? 0 : 1;
5419 		/*
5420 		 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
5421 		 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
5422 		 * TX_PWR_CFG_4: unknown
5423 		 */
5424 		txpower = rt2x00_get_field16(eeprom,
5425 					     EEPROM_TXPOWER_BYRATE_RATE0);
5426 		txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5427 					     power_level, txpower, delta);
5428 		rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
5429 
5430 		/*
5431 		 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
5432 		 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
5433 		 * TX_PWR_CFG_4: unknown
5434 		 */
5435 		txpower = rt2x00_get_field16(eeprom,
5436 					     EEPROM_TXPOWER_BYRATE_RATE1);
5437 		txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5438 					     power_level, txpower, delta);
5439 		rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
5440 
5441 		/*
5442 		 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
5443 		 * TX_PWR_CFG_2: MCS6,  TX_PWR_CFG_3: MCS14,
5444 		 * TX_PWR_CFG_4: unknown
5445 		 */
5446 		txpower = rt2x00_get_field16(eeprom,
5447 					     EEPROM_TXPOWER_BYRATE_RATE2);
5448 		txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5449 					     power_level, txpower, delta);
5450 		rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
5451 
5452 		/*
5453 		 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
5454 		 * TX_PWR_CFG_2: MCS7,  TX_PWR_CFG_3: MCS15,
5455 		 * TX_PWR_CFG_4: unknown
5456 		 */
5457 		txpower = rt2x00_get_field16(eeprom,
5458 					     EEPROM_TXPOWER_BYRATE_RATE3);
5459 		txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5460 					     power_level, txpower, delta);
5461 		rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
5462 
5463 		/* read the next four txpower values */
5464 		eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
5465 						       EEPROM_TXPOWER_BYRATE,
5466 						       i + 1);
5467 
5468 		is_rate_b = 0;
5469 		/*
5470 		 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
5471 		 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
5472 		 * TX_PWR_CFG_4: unknown
5473 		 */
5474 		txpower = rt2x00_get_field16(eeprom,
5475 					     EEPROM_TXPOWER_BYRATE_RATE0);
5476 		txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5477 					     power_level, txpower, delta);
5478 		rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
5479 
5480 		/*
5481 		 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
5482 		 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
5483 		 * TX_PWR_CFG_4: unknown
5484 		 */
5485 		txpower = rt2x00_get_field16(eeprom,
5486 					     EEPROM_TXPOWER_BYRATE_RATE1);
5487 		txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5488 					     power_level, txpower, delta);
5489 		rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
5490 
5491 		/*
5492 		 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
5493 		 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
5494 		 * TX_PWR_CFG_4: unknown
5495 		 */
5496 		txpower = rt2x00_get_field16(eeprom,
5497 					     EEPROM_TXPOWER_BYRATE_RATE2);
5498 		txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5499 					     power_level, txpower, delta);
5500 		rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
5501 
5502 		/*
5503 		 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
5504 		 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
5505 		 * TX_PWR_CFG_4: unknown
5506 		 */
5507 		txpower = rt2x00_get_field16(eeprom,
5508 					     EEPROM_TXPOWER_BYRATE_RATE3);
5509 		txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5510 					     power_level, txpower, delta);
5511 		rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
5512 
5513 		rt2800_register_write(rt2x00dev, offset, reg);
5514 
5515 		/* next TX_PWR_CFG register */
5516 		offset += 4;
5517 	}
5518 }
5519 
rt2800_config_txpower(struct rt2x00_dev * rt2x00dev,struct ieee80211_channel * chan,int power_level)5520 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
5521 				  struct ieee80211_channel *chan,
5522 				  int power_level)
5523 {
5524 	if (rt2x00_rt(rt2x00dev, RT3593) ||
5525 	    rt2x00_rt(rt2x00dev, RT3883))
5526 		rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level);
5527 	else if (rt2x00_rt(rt2x00dev, RT6352))
5528 		rt2800_config_txpower_rt6352(rt2x00dev, chan, power_level);
5529 	else
5530 		rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level);
5531 }
5532 
rt2800_gain_calibration(struct rt2x00_dev * rt2x00dev)5533 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
5534 {
5535 	rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan,
5536 			      rt2x00dev->tx_power);
5537 }
5538 EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
5539 
rt2800_vco_calibration(struct rt2x00_dev * rt2x00dev)5540 void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
5541 {
5542 	u32	tx_pin;
5543 	u8	rfcsr;
5544 	unsigned long min_sleep = 0;
5545 
5546 	/*
5547 	 * A voltage-controlled oscillator(VCO) is an electronic oscillator
5548 	 * designed to be controlled in oscillation frequency by a voltage
5549 	 * input. Maybe the temperature will affect the frequency of
5550 	 * oscillation to be shifted. The VCO calibration will be called
5551 	 * periodically to adjust the frequency to be precision.
5552 	*/
5553 
5554 	tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
5555 	tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
5556 	rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
5557 
5558 	switch (rt2x00dev->chip.rf) {
5559 	case RF2020:
5560 	case RF3020:
5561 	case RF3021:
5562 	case RF3022:
5563 	case RF3320:
5564 	case RF3052:
5565 		rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
5566 		rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
5567 		rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
5568 		break;
5569 	case RF3053:
5570 	case RF3070:
5571 	case RF3290:
5572 	case RF3853:
5573 	case RF5350:
5574 	case RF5360:
5575 	case RF5362:
5576 	case RF5370:
5577 	case RF5372:
5578 	case RF5390:
5579 	case RF5392:
5580 	case RF5592:
5581 		rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
5582 		rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
5583 		rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
5584 		min_sleep = 1000;
5585 		break;
5586 	case RF7620:
5587 		rt2800_rfcsr_write(rt2x00dev, 5, 0x40);
5588 		rt2800_rfcsr_write(rt2x00dev, 4, 0x0C);
5589 		rfcsr = rt2800_rfcsr_read(rt2x00dev, 4);
5590 		rt2x00_set_field8(&rfcsr, RFCSR4_VCOCAL_EN, 1);
5591 		rt2800_rfcsr_write(rt2x00dev, 4, rfcsr);
5592 		min_sleep = 2000;
5593 		break;
5594 	default:
5595 		WARN_ONCE(1, "Not supported RF chipset %x for VCO recalibration",
5596 			  rt2x00dev->chip.rf);
5597 		return;
5598 	}
5599 
5600 	if (min_sleep > 0)
5601 		usleep_range(min_sleep, min_sleep * 2);
5602 
5603 	tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
5604 	if (rt2x00dev->rf_channel <= 14) {
5605 		switch (rt2x00dev->default_ant.tx_chain_num) {
5606 		case 3:
5607 			rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
5608 			fallthrough;
5609 		case 2:
5610 			rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
5611 			fallthrough;
5612 		case 1:
5613 		default:
5614 			rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
5615 			break;
5616 		}
5617 	} else {
5618 		switch (rt2x00dev->default_ant.tx_chain_num) {
5619 		case 3:
5620 			rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
5621 			fallthrough;
5622 		case 2:
5623 			rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
5624 			fallthrough;
5625 		case 1:
5626 		default:
5627 			rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
5628 			break;
5629 		}
5630 	}
5631 	rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
5632 }
5633 EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
5634 
rt2800_config_retry_limit(struct rt2x00_dev * rt2x00dev,struct rt2x00lib_conf * libconf)5635 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
5636 				      struct rt2x00lib_conf *libconf)
5637 {
5638 	u32 reg;
5639 
5640 	reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG);
5641 	rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
5642 			   libconf->conf->short_frame_max_tx_count);
5643 	rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
5644 			   libconf->conf->long_frame_max_tx_count);
5645 	rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
5646 }
5647 
rt2800_config_ps(struct rt2x00_dev * rt2x00dev,struct rt2x00lib_conf * libconf)5648 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
5649 			     struct rt2x00lib_conf *libconf)
5650 {
5651 	enum dev_state state =
5652 	    (libconf->conf->flags & IEEE80211_CONF_PS) ?
5653 		STATE_SLEEP : STATE_AWAKE;
5654 	u32 reg;
5655 
5656 	if (state == STATE_SLEEP) {
5657 		rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
5658 
5659 		reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG);
5660 		rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
5661 		rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
5662 				   libconf->conf->listen_interval - 1);
5663 		rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
5664 		rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5665 
5666 		rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
5667 	} else {
5668 		reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG);
5669 		rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
5670 		rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
5671 		rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
5672 		rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5673 
5674 		rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
5675 	}
5676 }
5677 
rt2800_config(struct rt2x00_dev * rt2x00dev,struct rt2x00lib_conf * libconf,const unsigned int flags)5678 void rt2800_config(struct rt2x00_dev *rt2x00dev,
5679 		   struct rt2x00lib_conf *libconf,
5680 		   const unsigned int flags)
5681 {
5682 	/* Always recalculate LNA gain before changing configuration */
5683 	rt2800_config_lna_gain(rt2x00dev, libconf);
5684 
5685 	if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
5686 		/*
5687 		 * To provide correct survey data for survey-based ACS algorithm
5688 		 * we have to save survey data for current channel before switching.
5689 		 */
5690 		rt2800_update_survey(rt2x00dev);
5691 
5692 		rt2800_config_channel(rt2x00dev, libconf->conf,
5693 				      &libconf->rf, &libconf->channel);
5694 		rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
5695 				      libconf->conf->power_level);
5696 	}
5697 	if (flags & IEEE80211_CONF_CHANGE_POWER)
5698 		rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
5699 				      libconf->conf->power_level);
5700 	if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
5701 		rt2800_config_retry_limit(rt2x00dev, libconf);
5702 	if (flags & IEEE80211_CONF_CHANGE_PS)
5703 		rt2800_config_ps(rt2x00dev, libconf);
5704 }
5705 EXPORT_SYMBOL_GPL(rt2800_config);
5706 
5707 /*
5708  * Link tuning
5709  */
rt2800_link_stats(struct rt2x00_dev * rt2x00dev,struct link_qual * qual)5710 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
5711 {
5712 	u32 reg;
5713 
5714 	/*
5715 	 * Update FCS error count from register.
5716 	 */
5717 	reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0);
5718 	qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
5719 }
5720 EXPORT_SYMBOL_GPL(rt2800_link_stats);
5721 
rt2800_get_default_vgc(struct rt2x00_dev * rt2x00dev)5722 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
5723 {
5724 	u8 vgc;
5725 
5726 	if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
5727 		if (rt2x00_rt(rt2x00dev, RT3070) ||
5728 		    rt2x00_rt(rt2x00dev, RT3071) ||
5729 		    rt2x00_rt(rt2x00dev, RT3090) ||
5730 		    rt2x00_rt(rt2x00dev, RT3290) ||
5731 		    rt2x00_rt(rt2x00dev, RT3390) ||
5732 		    rt2x00_rt(rt2x00dev, RT3572) ||
5733 		    rt2x00_rt(rt2x00dev, RT3593) ||
5734 		    rt2x00_rt(rt2x00dev, RT5390) ||
5735 		    rt2x00_rt(rt2x00dev, RT5392) ||
5736 		    rt2x00_rt(rt2x00dev, RT5592) ||
5737 		    rt2x00_rt(rt2x00dev, RT6352))
5738 			vgc = 0x1c + (2 * rt2x00dev->lna_gain);
5739 		else
5740 			vgc = 0x2e + rt2x00dev->lna_gain;
5741 	} else { /* 5GHZ band */
5742 		if (rt2x00_rt(rt2x00dev, RT3593) ||
5743 		    rt2x00_rt(rt2x00dev, RT3883))
5744 			vgc = 0x20 + (rt2x00dev->lna_gain * 5) / 3;
5745 		else if (rt2x00_rt(rt2x00dev, RT5592))
5746 			vgc = 0x24 + (2 * rt2x00dev->lna_gain);
5747 		else {
5748 			if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
5749 				vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
5750 			else
5751 				vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
5752 		}
5753 	}
5754 
5755 	return vgc;
5756 }
5757 
rt2800_set_vgc(struct rt2x00_dev * rt2x00dev,struct link_qual * qual,u8 vgc_level)5758 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
5759 				  struct link_qual *qual, u8 vgc_level)
5760 {
5761 	if (qual->vgc_level != vgc_level) {
5762 		if (rt2x00_rt(rt2x00dev, RT3572) ||
5763 		    rt2x00_rt(rt2x00dev, RT3593) ||
5764 		    rt2x00_rt(rt2x00dev, RT3883) ||
5765 		    rt2x00_rt(rt2x00dev, RT6352)) {
5766 			rt2800_bbp_write_with_rx_chain(rt2x00dev, 66,
5767 						       vgc_level);
5768 		} else if (rt2x00_rt(rt2x00dev, RT5592)) {
5769 			rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a);
5770 			rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level);
5771 		} else {
5772 			rt2800_bbp_write(rt2x00dev, 66, vgc_level);
5773 		}
5774 
5775 		qual->vgc_level = vgc_level;
5776 		qual->vgc_level_reg = vgc_level;
5777 	}
5778 }
5779 
rt2800_reset_tuner(struct rt2x00_dev * rt2x00dev,struct link_qual * qual)5780 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
5781 {
5782 	rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
5783 }
5784 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
5785 
rt2800_link_tuner(struct rt2x00_dev * rt2x00dev,struct link_qual * qual,const u32 count)5786 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
5787 		       const u32 count)
5788 {
5789 	u8 vgc;
5790 
5791 	if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
5792 		return;
5793 
5794 	/* When RSSI is better than a certain threshold, increase VGC
5795 	 * with a chip specific value in order to improve the balance
5796 	 * between sensibility and noise isolation.
5797 	 */
5798 
5799 	vgc = rt2800_get_default_vgc(rt2x00dev);
5800 
5801 	switch (rt2x00dev->chip.rt) {
5802 	case RT3572:
5803 	case RT3593:
5804 		if (qual->rssi > -65) {
5805 			if (rt2x00dev->curr_band == NL80211_BAND_2GHZ)
5806 				vgc += 0x20;
5807 			else
5808 				vgc += 0x10;
5809 		}
5810 		break;
5811 
5812 	case RT3883:
5813 		if (qual->rssi > -65)
5814 			vgc += 0x10;
5815 		break;
5816 
5817 	case RT5592:
5818 		if (qual->rssi > -65)
5819 			vgc += 0x20;
5820 		break;
5821 
5822 	default:
5823 		if (qual->rssi > -80)
5824 			vgc += 0x10;
5825 		break;
5826 	}
5827 
5828 	rt2800_set_vgc(rt2x00dev, qual, vgc);
5829 }
5830 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
5831 
5832 /*
5833  * Initialization functions.
5834  */
rt2800_init_registers(struct rt2x00_dev * rt2x00dev)5835 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
5836 {
5837 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5838 	u32 reg;
5839 	u16 eeprom;
5840 	u8 bbp;
5841 	unsigned int i;
5842 	int ret;
5843 
5844 	rt2800_disable_wpdma(rt2x00dev);
5845 
5846 	ret = rt2800_drv_init_registers(rt2x00dev);
5847 	if (ret)
5848 		return ret;
5849 
5850 	if (rt2x00_rt(rt2x00dev, RT6352)) {
5851 		rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x01);
5852 
5853 		bbp = rt2800_bbp_read(rt2x00dev, 21);
5854 		bbp |= 0x01;
5855 		rt2800_bbp_write(rt2x00dev, 21, bbp);
5856 		bbp = rt2800_bbp_read(rt2x00dev, 21);
5857 		bbp &= (~0x01);
5858 		rt2800_bbp_write(rt2x00dev, 21, bbp);
5859 
5860 		rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00);
5861 	}
5862 
5863 	rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
5864 	rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
5865 
5866 	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
5867 
5868 	reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
5869 	rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
5870 	rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
5871 	rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
5872 	rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
5873 	rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
5874 	rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
5875 	rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
5876 
5877 	rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
5878 
5879 	reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG);
5880 	rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
5881 	rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
5882 	rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
5883 
5884 	if (rt2x00_rt(rt2x00dev, RT3290)) {
5885 		reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
5886 		if (rt2x00_get_field32(reg, WLAN_EN) == 1) {
5887 			rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 1);
5888 			rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
5889 		}
5890 
5891 		reg = rt2800_register_read(rt2x00dev, CMB_CTRL);
5892 		if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) {
5893 			rt2x00_set_field32(&reg, LDO0_EN, 1);
5894 			rt2x00_set_field32(&reg, LDO_BGSEL, 3);
5895 			rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
5896 		}
5897 
5898 		reg = rt2800_register_read(rt2x00dev, OSC_CTRL);
5899 		rt2x00_set_field32(&reg, OSC_ROSC_EN, 1);
5900 		rt2x00_set_field32(&reg, OSC_CAL_REQ, 1);
5901 		rt2x00_set_field32(&reg, OSC_REF_CYCLE, 0x27);
5902 		rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
5903 
5904 		reg = rt2800_register_read(rt2x00dev, COEX_CFG0);
5905 		rt2x00_set_field32(&reg, COEX_CFG_ANT, 0x5e);
5906 		rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
5907 
5908 		reg = rt2800_register_read(rt2x00dev, COEX_CFG2);
5909 		rt2x00_set_field32(&reg, BT_COEX_CFG1, 0x00);
5910 		rt2x00_set_field32(&reg, BT_COEX_CFG0, 0x17);
5911 		rt2x00_set_field32(&reg, WL_COEX_CFG1, 0x93);
5912 		rt2x00_set_field32(&reg, WL_COEX_CFG0, 0x7f);
5913 		rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
5914 
5915 		reg = rt2800_register_read(rt2x00dev, PLL_CTRL);
5916 		rt2x00_set_field32(&reg, PLL_CONTROL, 1);
5917 		rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
5918 	}
5919 
5920 	if (rt2x00_rt(rt2x00dev, RT3071) ||
5921 	    rt2x00_rt(rt2x00dev, RT3090) ||
5922 	    rt2x00_rt(rt2x00dev, RT3290) ||
5923 	    rt2x00_rt(rt2x00dev, RT3390)) {
5924 
5925 		if (rt2x00_rt(rt2x00dev, RT3290))
5926 			rt2800_register_write(rt2x00dev, TX_SW_CFG0,
5927 					      0x00000404);
5928 		else
5929 			rt2800_register_write(rt2x00dev, TX_SW_CFG0,
5930 					      0x00000400);
5931 
5932 		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5933 		if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
5934 		    rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
5935 		    rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
5936 			eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
5937 			if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
5938 				rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5939 						      0x0000002c);
5940 			else
5941 				rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5942 						      0x0000000f);
5943 		} else {
5944 			rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5945 		}
5946 	} else if (rt2x00_rt(rt2x00dev, RT3070)) {
5947 		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
5948 
5949 		if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
5950 			rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5951 			rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
5952 		} else {
5953 			rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5954 			rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5955 		}
5956 	} else if (rt2800_is_305x_soc(rt2x00dev)) {
5957 		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
5958 		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5959 		rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
5960 	} else if (rt2x00_rt(rt2x00dev, RT3352)) {
5961 		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
5962 		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5963 		rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5964 	} else if (rt2x00_rt(rt2x00dev, RT3572)) {
5965 		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
5966 		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5967 	} else if (rt2x00_rt(rt2x00dev, RT3593)) {
5968 		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
5969 		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5970 		if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) {
5971 			eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
5972 			if (rt2x00_get_field16(eeprom,
5973 					       EEPROM_NIC_CONF1_DAC_TEST))
5974 				rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5975 						      0x0000001f);
5976 			else
5977 				rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5978 						      0x0000000f);
5979 		} else {
5980 			rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5981 					      0x00000000);
5982 		}
5983 	} else if (rt2x00_rt(rt2x00dev, RT3883)) {
5984 		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
5985 		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5986 		rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00040000);
5987 		rt2800_register_write(rt2x00dev, TX_TXBF_CFG_0, 0x8000fc21);
5988 		rt2800_register_write(rt2x00dev, TX_TXBF_CFG_3, 0x00009c40);
5989 	} else if (rt2x00_rt(rt2x00dev, RT5390) ||
5990 		   rt2x00_rt(rt2x00dev, RT5392)) {
5991 		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
5992 		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5993 		rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5994 	} else if (rt2x00_rt(rt2x00dev, RT5592)) {
5995 		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
5996 		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5997 		rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5998 	} else if (rt2x00_rt(rt2x00dev, RT5350)) {
5999 		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
6000 	} else if (rt2x00_rt(rt2x00dev, RT6352)) {
6001 		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000401);
6002 		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0001);
6003 		rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
6004 		rt2800_register_write(rt2x00dev, TX_ALC_VGA3, 0x00000000);
6005 		rt2800_register_write(rt2x00dev, TX0_BB_GAIN_ATTEN, 0x0);
6006 		rt2800_register_write(rt2x00dev, TX1_BB_GAIN_ATTEN, 0x0);
6007 		rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6C6C666C);
6008 		rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6C6C666C);
6009 		rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT,
6010 				      0x3630363A);
6011 		rt2800_register_write(rt2x00dev, TX1_RF_GAIN_CORRECT,
6012 				      0x3630363A);
6013 		reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1);
6014 		rt2x00_set_field32(&reg, TX_ALC_CFG_1_ROS_BUSY_EN, 0);
6015 		rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg);
6016 
6017 		rt2800_register_write(rt2x00dev, AMPDU_MAX_LEN_20M1S, 0x77754433);
6018 		rt2800_register_write(rt2x00dev, AMPDU_MAX_LEN_20M2S, 0x77765543);
6019 		rt2800_register_write(rt2x00dev, AMPDU_MAX_LEN_40M1S, 0x77765544);
6020 		rt2800_register_write(rt2x00dev, AMPDU_MAX_LEN_40M2S, 0x77765544);
6021 
6022 		rt2800_register_write(rt2x00dev, HT_FBK_TO_LEGACY, 0x1010);
6023 
6024 	} else {
6025 		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
6026 		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
6027 	}
6028 
6029 	reg = rt2800_register_read(rt2x00dev, TX_LINK_CFG);
6030 	rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
6031 	rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
6032 	rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
6033 	rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
6034 	rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
6035 	rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
6036 	rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
6037 	rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
6038 	rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
6039 
6040 	reg = rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG);
6041 	rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
6042 	rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
6043 	rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
6044 	rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
6045 
6046 	reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG);
6047 	rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
6048 	if (rt2x00_is_usb(rt2x00dev)) {
6049 		drv_data->max_psdu = 3;
6050 	} else if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
6051 		   rt2x00_rt(rt2x00dev, RT2883) ||
6052 		   rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E)) {
6053 		drv_data->max_psdu = 2;
6054 	} else {
6055 		drv_data->max_psdu = 1;
6056 	}
6057 	rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, drv_data->max_psdu);
6058 	rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 10);
6059 	rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 10);
6060 	rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
6061 
6062 	reg = rt2800_register_read(rt2x00dev, LED_CFG);
6063 	rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
6064 	rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
6065 	rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
6066 	rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
6067 	rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
6068 	rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
6069 	rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
6070 	rt2800_register_write(rt2x00dev, LED_CFG, reg);
6071 
6072 	rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
6073 
6074 	reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG);
6075 	rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 2);
6076 	rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 2);
6077 	rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
6078 	rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
6079 	rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
6080 	rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
6081 	rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
6082 
6083 	reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG);
6084 	rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
6085 	rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
6086 	rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 1);
6087 	rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
6088 	rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 0);
6089 	rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
6090 	rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
6091 	rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
6092 
6093 	reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG);
6094 	rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
6095 	rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
6096 	rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
6097 	rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
6098 	rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
6099 	rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
6100 	rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
6101 	rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
6102 	rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
6103 	rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 0);
6104 	rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
6105 
6106 	reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG);
6107 	rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
6108 	rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
6109 	rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
6110 	rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
6111 	rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
6112 	rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
6113 	rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
6114 	rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
6115 	rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
6116 	rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 0);
6117 	rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
6118 
6119 	reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG);
6120 	rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
6121 	rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 1);
6122 	rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
6123 	rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 0);
6124 	rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
6125 	rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
6126 	rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
6127 	rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
6128 	rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
6129 	rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
6130 	rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
6131 
6132 	reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG);
6133 	rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
6134 	rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 1);
6135 	rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
6136 	rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 0);
6137 	rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
6138 	rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
6139 	rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
6140 	rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
6141 	rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
6142 	rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
6143 	rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
6144 
6145 	reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG);
6146 	rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
6147 	rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 1);
6148 	rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
6149 	rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 0);
6150 	rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
6151 	rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
6152 	rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
6153 	rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
6154 	rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
6155 	rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
6156 	rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
6157 
6158 	reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG);
6159 	rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
6160 	rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 1);
6161 	rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
6162 	rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 0);
6163 	rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
6164 	rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
6165 	rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
6166 	rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
6167 	rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
6168 	rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
6169 	rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
6170 
6171 	if (rt2x00_is_usb(rt2x00dev)) {
6172 		rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
6173 
6174 		reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
6175 		rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
6176 		rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
6177 		rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
6178 		rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
6179 		rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
6180 		rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
6181 		rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
6182 		rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
6183 		rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
6184 		rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
6185 	}
6186 
6187 	/*
6188 	 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
6189 	 * although it is reserved.
6190 	 */
6191 	reg = rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG);
6192 	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
6193 	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
6194 	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
6195 	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
6196 	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
6197 	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
6198 	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
6199 	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
6200 	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
6201 	rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
6202 	rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
6203 
6204 	reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002;
6205 	rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg);
6206 
6207 	if (rt2x00_rt(rt2x00dev, RT3883)) {
6208 		rt2800_register_write(rt2x00dev, TX_FBK_CFG_3S_0, 0x12111008);
6209 		rt2800_register_write(rt2x00dev, TX_FBK_CFG_3S_1, 0x16151413);
6210 	}
6211 
6212 	reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG);
6213 	rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 7);
6214 	rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
6215 			   IEEE80211_MAX_RTS_THRESHOLD);
6216 	rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 1);
6217 	rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
6218 
6219 	rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
6220 
6221 	/*
6222 	 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
6223 	 * time should be set to 16. However, the original Ralink driver uses
6224 	 * 16 for both and indeed using a value of 10 for CCK SIFS results in
6225 	 * connection problems with 11g + CTS protection. Hence, use the same
6226 	 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
6227 	 */
6228 	reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG);
6229 	rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
6230 	rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
6231 	rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
6232 	rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
6233 	rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
6234 	rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
6235 
6236 	rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
6237 
6238 	/*
6239 	 * ASIC will keep garbage value after boot, clear encryption keys.
6240 	 */
6241 	for (i = 0; i < 4; i++)
6242 		rt2800_register_write(rt2x00dev, SHARED_KEY_MODE_ENTRY(i), 0);
6243 
6244 	for (i = 0; i < 256; i++) {
6245 		rt2800_config_wcid(rt2x00dev, NULL, i);
6246 		rt2800_delete_wcid_attr(rt2x00dev, i);
6247 	}
6248 
6249 	/*
6250 	 * Clear encryption initialization vectors on start, but keep them
6251 	 * for watchdog reset. Otherwise we will have wrong IVs and not be
6252 	 * able to keep connections after reset.
6253 	 */
6254 	if (!test_bit(DEVICE_STATE_RESET, &rt2x00dev->flags))
6255 		for (i = 0; i < 256; i++)
6256 			rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
6257 
6258 	/*
6259 	 * Clear all beacons
6260 	 */
6261 	for (i = 0; i < 8; i++)
6262 		rt2800_clear_beacon_register(rt2x00dev, i);
6263 
6264 	if (rt2x00_is_usb(rt2x00dev)) {
6265 		reg = rt2800_register_read(rt2x00dev, US_CYC_CNT);
6266 		rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
6267 		rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
6268 	} else if (rt2x00_is_pcie(rt2x00dev)) {
6269 		reg = rt2800_register_read(rt2x00dev, US_CYC_CNT);
6270 		rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
6271 		rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
6272 	} else if (rt2x00_is_soc(rt2x00dev)) {
6273 		struct clk *clk = clk_get_sys("bus", NULL);
6274 		int rate;
6275 
6276 		if (IS_ERR(clk)) {
6277 			clk = clk_get_sys("cpu", NULL);
6278 
6279 			if (IS_ERR(clk)) {
6280 				rate = 125;
6281 			} else {
6282 				rate = clk_get_rate(clk) / 3000000;
6283 				clk_put(clk);
6284 			}
6285 		} else {
6286 			rate = clk_get_rate(clk) / 1000000;
6287 			clk_put(clk);
6288 		}
6289 
6290 		reg = rt2800_register_read(rt2x00dev, US_CYC_CNT);
6291 		rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, rate);
6292 		rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
6293 	}
6294 
6295 	reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG0);
6296 	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
6297 	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
6298 	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
6299 	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
6300 	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
6301 	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
6302 	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
6303 	rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
6304 	rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
6305 
6306 	reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG1);
6307 	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
6308 	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
6309 	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
6310 	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
6311 	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
6312 	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
6313 	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
6314 	rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
6315 	rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
6316 
6317 	reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG0);
6318 	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
6319 	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
6320 	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
6321 	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
6322 	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
6323 	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
6324 	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
6325 	rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
6326 	rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
6327 
6328 	reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG1);
6329 	rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
6330 	rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
6331 	rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
6332 	rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
6333 	rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
6334 
6335 	/*
6336 	 * Do not force the BA window size, we use the TXWI to set it
6337 	 */
6338 	reg = rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE);
6339 	rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
6340 	rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
6341 	rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
6342 
6343 	/*
6344 	 * We must clear the error counters.
6345 	 * These registers are cleared on read,
6346 	 * so we may pass a useless variable to store the value.
6347 	 */
6348 	reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0);
6349 	reg = rt2800_register_read(rt2x00dev, RX_STA_CNT1);
6350 	reg = rt2800_register_read(rt2x00dev, RX_STA_CNT2);
6351 	reg = rt2800_register_read(rt2x00dev, TX_STA_CNT0);
6352 	reg = rt2800_register_read(rt2x00dev, TX_STA_CNT1);
6353 	reg = rt2800_register_read(rt2x00dev, TX_STA_CNT2);
6354 
6355 	/*
6356 	 * Setup leadtime for pre tbtt interrupt to 6ms
6357 	 */
6358 	reg = rt2800_register_read(rt2x00dev, INT_TIMER_CFG);
6359 	rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
6360 	rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
6361 
6362 	/*
6363 	 * Set up channel statistics timer
6364 	 */
6365 	reg = rt2800_register_read(rt2x00dev, CH_TIME_CFG);
6366 	rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
6367 	rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
6368 	rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
6369 	rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
6370 	rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
6371 	rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
6372 
6373 	return 0;
6374 }
6375 
6376 
rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev * rt2x00dev)6377 static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev)
6378 {
6379 	u8 value;
6380 
6381 	value = rt2800_bbp_read(rt2x00dev, 4);
6382 	rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
6383 	rt2800_bbp_write(rt2x00dev, 4, value);
6384 }
6385 
rt2800_init_freq_calibration(struct rt2x00_dev * rt2x00dev)6386 static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev)
6387 {
6388 	rt2800_bbp_write(rt2x00dev, 142, 1);
6389 	rt2800_bbp_write(rt2x00dev, 143, 57);
6390 }
6391 
rt2800_init_bbp_5592_glrt(struct rt2x00_dev * rt2x00dev)6392 static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev)
6393 {
6394 	static const u8 glrt_table[] = {
6395 		0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */
6396 		0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */
6397 		0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */
6398 		0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */
6399 		0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */
6400 		0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */
6401 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */
6402 		0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */
6403 		0x2E, 0x36, 0x30, 0x6E,					    /* 208 ~ 211 */
6404 	};
6405 	int i;
6406 
6407 	for (i = 0; i < ARRAY_SIZE(glrt_table); i++) {
6408 		rt2800_bbp_write(rt2x00dev, 195, 128 + i);
6409 		rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]);
6410 	}
6411 };
6412 
rt2800_init_bbp_early(struct rt2x00_dev * rt2x00dev)6413 static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev)
6414 {
6415 	rt2800_bbp_write(rt2x00dev, 65, 0x2C);
6416 	rt2800_bbp_write(rt2x00dev, 66, 0x38);
6417 	rt2800_bbp_write(rt2x00dev, 68, 0x0B);
6418 	rt2800_bbp_write(rt2x00dev, 69, 0x12);
6419 	rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6420 	rt2800_bbp_write(rt2x00dev, 73, 0x10);
6421 	rt2800_bbp_write(rt2x00dev, 81, 0x37);
6422 	rt2800_bbp_write(rt2x00dev, 82, 0x62);
6423 	rt2800_bbp_write(rt2x00dev, 83, 0x6A);
6424 	rt2800_bbp_write(rt2x00dev, 84, 0x99);
6425 	rt2800_bbp_write(rt2x00dev, 86, 0x00);
6426 	rt2800_bbp_write(rt2x00dev, 91, 0x04);
6427 	rt2800_bbp_write(rt2x00dev, 92, 0x00);
6428 	rt2800_bbp_write(rt2x00dev, 103, 0x00);
6429 	rt2800_bbp_write(rt2x00dev, 105, 0x05);
6430 	rt2800_bbp_write(rt2x00dev, 106, 0x35);
6431 }
6432 
rt2800_disable_unused_dac_adc(struct rt2x00_dev * rt2x00dev)6433 static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev)
6434 {
6435 	u16 eeprom;
6436 	u8 value;
6437 
6438 	value = rt2800_bbp_read(rt2x00dev, 138);
6439 	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
6440 	if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
6441 		value |= 0x20;
6442 	if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
6443 		value &= ~0x02;
6444 	rt2800_bbp_write(rt2x00dev, 138, value);
6445 }
6446 
rt2800_init_bbp_305x_soc(struct rt2x00_dev * rt2x00dev)6447 static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev)
6448 {
6449 	rt2800_bbp_write(rt2x00dev, 31, 0x08);
6450 
6451 	rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6452 	rt2800_bbp_write(rt2x00dev, 66, 0x38);
6453 
6454 	rt2800_bbp_write(rt2x00dev, 69, 0x12);
6455 	rt2800_bbp_write(rt2x00dev, 73, 0x10);
6456 
6457 	rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6458 
6459 	rt2800_bbp_write(rt2x00dev, 78, 0x0e);
6460 	rt2800_bbp_write(rt2x00dev, 80, 0x08);
6461 
6462 	rt2800_bbp_write(rt2x00dev, 82, 0x62);
6463 
6464 	rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6465 
6466 	rt2800_bbp_write(rt2x00dev, 84, 0x99);
6467 
6468 	rt2800_bbp_write(rt2x00dev, 86, 0x00);
6469 
6470 	rt2800_bbp_write(rt2x00dev, 91, 0x04);
6471 
6472 	rt2800_bbp_write(rt2x00dev, 92, 0x00);
6473 
6474 	rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6475 
6476 	rt2800_bbp_write(rt2x00dev, 105, 0x01);
6477 
6478 	rt2800_bbp_write(rt2x00dev, 106, 0x35);
6479 }
6480 
rt2800_init_bbp_28xx(struct rt2x00_dev * rt2x00dev)6481 static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev)
6482 {
6483 	rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6484 	rt2800_bbp_write(rt2x00dev, 66, 0x38);
6485 
6486 	if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
6487 		rt2800_bbp_write(rt2x00dev, 69, 0x16);
6488 		rt2800_bbp_write(rt2x00dev, 73, 0x12);
6489 	} else {
6490 		rt2800_bbp_write(rt2x00dev, 69, 0x12);
6491 		rt2800_bbp_write(rt2x00dev, 73, 0x10);
6492 	}
6493 
6494 	rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6495 
6496 	rt2800_bbp_write(rt2x00dev, 81, 0x37);
6497 
6498 	rt2800_bbp_write(rt2x00dev, 82, 0x62);
6499 
6500 	rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6501 
6502 	if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
6503 		rt2800_bbp_write(rt2x00dev, 84, 0x19);
6504 	else
6505 		rt2800_bbp_write(rt2x00dev, 84, 0x99);
6506 
6507 	rt2800_bbp_write(rt2x00dev, 86, 0x00);
6508 
6509 	rt2800_bbp_write(rt2x00dev, 91, 0x04);
6510 
6511 	rt2800_bbp_write(rt2x00dev, 92, 0x00);
6512 
6513 	rt2800_bbp_write(rt2x00dev, 103, 0x00);
6514 
6515 	rt2800_bbp_write(rt2x00dev, 105, 0x05);
6516 
6517 	rt2800_bbp_write(rt2x00dev, 106, 0x35);
6518 }
6519 
rt2800_init_bbp_30xx(struct rt2x00_dev * rt2x00dev)6520 static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev)
6521 {
6522 	rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6523 	rt2800_bbp_write(rt2x00dev, 66, 0x38);
6524 
6525 	rt2800_bbp_write(rt2x00dev, 69, 0x12);
6526 	rt2800_bbp_write(rt2x00dev, 73, 0x10);
6527 
6528 	rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6529 
6530 	rt2800_bbp_write(rt2x00dev, 79, 0x13);
6531 	rt2800_bbp_write(rt2x00dev, 80, 0x05);
6532 	rt2800_bbp_write(rt2x00dev, 81, 0x33);
6533 
6534 	rt2800_bbp_write(rt2x00dev, 82, 0x62);
6535 
6536 	rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6537 
6538 	rt2800_bbp_write(rt2x00dev, 84, 0x99);
6539 
6540 	rt2800_bbp_write(rt2x00dev, 86, 0x00);
6541 
6542 	rt2800_bbp_write(rt2x00dev, 91, 0x04);
6543 
6544 	rt2800_bbp_write(rt2x00dev, 92, 0x00);
6545 
6546 	if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
6547 	    rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
6548 	    rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E))
6549 		rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6550 	else
6551 		rt2800_bbp_write(rt2x00dev, 103, 0x00);
6552 
6553 	rt2800_bbp_write(rt2x00dev, 105, 0x05);
6554 
6555 	rt2800_bbp_write(rt2x00dev, 106, 0x35);
6556 
6557 	if (rt2x00_rt(rt2x00dev, RT3071) ||
6558 	    rt2x00_rt(rt2x00dev, RT3090))
6559 		rt2800_disable_unused_dac_adc(rt2x00dev);
6560 }
6561 
rt2800_init_bbp_3290(struct rt2x00_dev * rt2x00dev)6562 static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev)
6563 {
6564 	u8 value;
6565 
6566 	rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6567 
6568 	rt2800_bbp_write(rt2x00dev, 31, 0x08);
6569 
6570 	rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6571 	rt2800_bbp_write(rt2x00dev, 66, 0x38);
6572 
6573 	rt2800_bbp_write(rt2x00dev, 68, 0x0b);
6574 
6575 	rt2800_bbp_write(rt2x00dev, 69, 0x12);
6576 	rt2800_bbp_write(rt2x00dev, 73, 0x13);
6577 	rt2800_bbp_write(rt2x00dev, 75, 0x46);
6578 	rt2800_bbp_write(rt2x00dev, 76, 0x28);
6579 
6580 	rt2800_bbp_write(rt2x00dev, 77, 0x58);
6581 
6582 	rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6583 
6584 	rt2800_bbp_write(rt2x00dev, 74, 0x0b);
6585 	rt2800_bbp_write(rt2x00dev, 79, 0x18);
6586 	rt2800_bbp_write(rt2x00dev, 80, 0x09);
6587 	rt2800_bbp_write(rt2x00dev, 81, 0x33);
6588 
6589 	rt2800_bbp_write(rt2x00dev, 82, 0x62);
6590 
6591 	rt2800_bbp_write(rt2x00dev, 83, 0x7a);
6592 
6593 	rt2800_bbp_write(rt2x00dev, 84, 0x9a);
6594 
6595 	rt2800_bbp_write(rt2x00dev, 86, 0x38);
6596 
6597 	rt2800_bbp_write(rt2x00dev, 91, 0x04);
6598 
6599 	rt2800_bbp_write(rt2x00dev, 92, 0x02);
6600 
6601 	rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6602 
6603 	rt2800_bbp_write(rt2x00dev, 104, 0x92);
6604 
6605 	rt2800_bbp_write(rt2x00dev, 105, 0x1c);
6606 
6607 	rt2800_bbp_write(rt2x00dev, 106, 0x03);
6608 
6609 	rt2800_bbp_write(rt2x00dev, 128, 0x12);
6610 
6611 	rt2800_bbp_write(rt2x00dev, 67, 0x24);
6612 	rt2800_bbp_write(rt2x00dev, 143, 0x04);
6613 	rt2800_bbp_write(rt2x00dev, 142, 0x99);
6614 	rt2800_bbp_write(rt2x00dev, 150, 0x30);
6615 	rt2800_bbp_write(rt2x00dev, 151, 0x2e);
6616 	rt2800_bbp_write(rt2x00dev, 152, 0x20);
6617 	rt2800_bbp_write(rt2x00dev, 153, 0x34);
6618 	rt2800_bbp_write(rt2x00dev, 154, 0x40);
6619 	rt2800_bbp_write(rt2x00dev, 155, 0x3b);
6620 	rt2800_bbp_write(rt2x00dev, 253, 0x04);
6621 
6622 	value = rt2800_bbp_read(rt2x00dev, 47);
6623 	rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1);
6624 	rt2800_bbp_write(rt2x00dev, 47, value);
6625 
6626 	/* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
6627 	value = rt2800_bbp_read(rt2x00dev, 3);
6628 	rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1);
6629 	rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1);
6630 	rt2800_bbp_write(rt2x00dev, 3, value);
6631 }
6632 
rt2800_init_bbp_3352(struct rt2x00_dev * rt2x00dev)6633 static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev)
6634 {
6635 	rt2800_bbp_write(rt2x00dev, 3, 0x00);
6636 	rt2800_bbp_write(rt2x00dev, 4, 0x50);
6637 
6638 	rt2800_bbp_write(rt2x00dev, 31, 0x08);
6639 
6640 	rt2800_bbp_write(rt2x00dev, 47, 0x48);
6641 
6642 	rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6643 	rt2800_bbp_write(rt2x00dev, 66, 0x38);
6644 
6645 	rt2800_bbp_write(rt2x00dev, 68, 0x0b);
6646 
6647 	rt2800_bbp_write(rt2x00dev, 69, 0x12);
6648 	rt2800_bbp_write(rt2x00dev, 73, 0x13);
6649 	rt2800_bbp_write(rt2x00dev, 75, 0x46);
6650 	rt2800_bbp_write(rt2x00dev, 76, 0x28);
6651 
6652 	rt2800_bbp_write(rt2x00dev, 77, 0x59);
6653 
6654 	rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6655 
6656 	rt2800_bbp_write(rt2x00dev, 78, 0x0e);
6657 	rt2800_bbp_write(rt2x00dev, 80, 0x08);
6658 	rt2800_bbp_write(rt2x00dev, 81, 0x37);
6659 
6660 	rt2800_bbp_write(rt2x00dev, 82, 0x62);
6661 
6662 	if (rt2x00_rt(rt2x00dev, RT5350)) {
6663 		rt2800_bbp_write(rt2x00dev, 83, 0x7a);
6664 		rt2800_bbp_write(rt2x00dev, 84, 0x9a);
6665 	} else {
6666 		rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6667 		rt2800_bbp_write(rt2x00dev, 84, 0x99);
6668 	}
6669 
6670 	rt2800_bbp_write(rt2x00dev, 86, 0x38);
6671 
6672 	rt2800_bbp_write(rt2x00dev, 88, 0x90);
6673 
6674 	rt2800_bbp_write(rt2x00dev, 91, 0x04);
6675 
6676 	rt2800_bbp_write(rt2x00dev, 92, 0x02);
6677 
6678 	rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6679 
6680 	rt2800_bbp_write(rt2x00dev, 104, 0x92);
6681 
6682 	if (rt2x00_rt(rt2x00dev, RT5350)) {
6683 		rt2800_bbp_write(rt2x00dev, 105, 0x3c);
6684 		rt2800_bbp_write(rt2x00dev, 106, 0x03);
6685 	} else {
6686 		rt2800_bbp_write(rt2x00dev, 105, 0x34);
6687 		rt2800_bbp_write(rt2x00dev, 106, 0x05);
6688 	}
6689 
6690 	rt2800_bbp_write(rt2x00dev, 120, 0x50);
6691 
6692 	rt2800_bbp_write(rt2x00dev, 137, 0x0f);
6693 
6694 	rt2800_bbp_write(rt2x00dev, 163, 0xbd);
6695 	/* Set ITxBF timeout to 0x9c40=1000msec */
6696 	rt2800_bbp_write(rt2x00dev, 179, 0x02);
6697 	rt2800_bbp_write(rt2x00dev, 180, 0x00);
6698 	rt2800_bbp_write(rt2x00dev, 182, 0x40);
6699 	rt2800_bbp_write(rt2x00dev, 180, 0x01);
6700 	rt2800_bbp_write(rt2x00dev, 182, 0x9c);
6701 	rt2800_bbp_write(rt2x00dev, 179, 0x00);
6702 	/* Reprogram the inband interface to put right values in RXWI */
6703 	rt2800_bbp_write(rt2x00dev, 142, 0x04);
6704 	rt2800_bbp_write(rt2x00dev, 143, 0x3b);
6705 	rt2800_bbp_write(rt2x00dev, 142, 0x06);
6706 	rt2800_bbp_write(rt2x00dev, 143, 0xa0);
6707 	rt2800_bbp_write(rt2x00dev, 142, 0x07);
6708 	rt2800_bbp_write(rt2x00dev, 143, 0xa1);
6709 	rt2800_bbp_write(rt2x00dev, 142, 0x08);
6710 	rt2800_bbp_write(rt2x00dev, 143, 0xa2);
6711 
6712 	rt2800_bbp_write(rt2x00dev, 148, 0xc8);
6713 
6714 	if (rt2x00_rt(rt2x00dev, RT5350)) {
6715 		/* Antenna Software OFDM */
6716 		rt2800_bbp_write(rt2x00dev, 150, 0x40);
6717 		/* Antenna Software CCK */
6718 		rt2800_bbp_write(rt2x00dev, 151, 0x30);
6719 		rt2800_bbp_write(rt2x00dev, 152, 0xa3);
6720 		/* Clear previously selected antenna */
6721 		rt2800_bbp_write(rt2x00dev, 154, 0);
6722 	}
6723 }
6724 
rt2800_init_bbp_3390(struct rt2x00_dev * rt2x00dev)6725 static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev)
6726 {
6727 	rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6728 	rt2800_bbp_write(rt2x00dev, 66, 0x38);
6729 
6730 	rt2800_bbp_write(rt2x00dev, 69, 0x12);
6731 	rt2800_bbp_write(rt2x00dev, 73, 0x10);
6732 
6733 	rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6734 
6735 	rt2800_bbp_write(rt2x00dev, 79, 0x13);
6736 	rt2800_bbp_write(rt2x00dev, 80, 0x05);
6737 	rt2800_bbp_write(rt2x00dev, 81, 0x33);
6738 
6739 	rt2800_bbp_write(rt2x00dev, 82, 0x62);
6740 
6741 	rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6742 
6743 	rt2800_bbp_write(rt2x00dev, 84, 0x99);
6744 
6745 	rt2800_bbp_write(rt2x00dev, 86, 0x00);
6746 
6747 	rt2800_bbp_write(rt2x00dev, 91, 0x04);
6748 
6749 	rt2800_bbp_write(rt2x00dev, 92, 0x00);
6750 
6751 	if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E))
6752 		rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6753 	else
6754 		rt2800_bbp_write(rt2x00dev, 103, 0x00);
6755 
6756 	rt2800_bbp_write(rt2x00dev, 105, 0x05);
6757 
6758 	rt2800_bbp_write(rt2x00dev, 106, 0x35);
6759 
6760 	rt2800_disable_unused_dac_adc(rt2x00dev);
6761 }
6762 
rt2800_init_bbp_3572(struct rt2x00_dev * rt2x00dev)6763 static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev)
6764 {
6765 	rt2800_bbp_write(rt2x00dev, 31, 0x08);
6766 
6767 	rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6768 	rt2800_bbp_write(rt2x00dev, 66, 0x38);
6769 
6770 	rt2800_bbp_write(rt2x00dev, 69, 0x12);
6771 	rt2800_bbp_write(rt2x00dev, 73, 0x10);
6772 
6773 	rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6774 
6775 	rt2800_bbp_write(rt2x00dev, 79, 0x13);
6776 	rt2800_bbp_write(rt2x00dev, 80, 0x05);
6777 	rt2800_bbp_write(rt2x00dev, 81, 0x33);
6778 
6779 	rt2800_bbp_write(rt2x00dev, 82, 0x62);
6780 
6781 	rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6782 
6783 	rt2800_bbp_write(rt2x00dev, 84, 0x99);
6784 
6785 	rt2800_bbp_write(rt2x00dev, 86, 0x00);
6786 
6787 	rt2800_bbp_write(rt2x00dev, 91, 0x04);
6788 
6789 	rt2800_bbp_write(rt2x00dev, 92, 0x00);
6790 
6791 	rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6792 
6793 	rt2800_bbp_write(rt2x00dev, 105, 0x05);
6794 
6795 	rt2800_bbp_write(rt2x00dev, 106, 0x35);
6796 
6797 	rt2800_disable_unused_dac_adc(rt2x00dev);
6798 }
6799 
rt2800_init_bbp_3593(struct rt2x00_dev * rt2x00dev)6800 static void rt2800_init_bbp_3593(struct rt2x00_dev *rt2x00dev)
6801 {
6802 	rt2800_init_bbp_early(rt2x00dev);
6803 
6804 	rt2800_bbp_write(rt2x00dev, 79, 0x13);
6805 	rt2800_bbp_write(rt2x00dev, 80, 0x05);
6806 	rt2800_bbp_write(rt2x00dev, 81, 0x33);
6807 	rt2800_bbp_write(rt2x00dev, 137, 0x0f);
6808 
6809 	rt2800_bbp_write(rt2x00dev, 84, 0x19);
6810 
6811 	/* Enable DC filter */
6812 	if (rt2x00_rt_rev_gte(rt2x00dev, RT3593, REV_RT3593E))
6813 		rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6814 }
6815 
rt2800_init_bbp_3883(struct rt2x00_dev * rt2x00dev)6816 static void rt2800_init_bbp_3883(struct rt2x00_dev *rt2x00dev)
6817 {
6818 	rt2800_init_bbp_early(rt2x00dev);
6819 
6820 	rt2800_bbp_write(rt2x00dev, 4, 0x50);
6821 	rt2800_bbp_write(rt2x00dev, 47, 0x48);
6822 
6823 	rt2800_bbp_write(rt2x00dev, 86, 0x46);
6824 	rt2800_bbp_write(rt2x00dev, 88, 0x90);
6825 
6826 	rt2800_bbp_write(rt2x00dev, 92, 0x02);
6827 
6828 	rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6829 	rt2800_bbp_write(rt2x00dev, 104, 0x92);
6830 	rt2800_bbp_write(rt2x00dev, 105, 0x34);
6831 	rt2800_bbp_write(rt2x00dev, 106, 0x12);
6832 	rt2800_bbp_write(rt2x00dev, 120, 0x50);
6833 	rt2800_bbp_write(rt2x00dev, 137, 0x0f);
6834 	rt2800_bbp_write(rt2x00dev, 163, 0x9d);
6835 
6836 	/* Set ITxBF timeout to 0x9C40=1000msec */
6837 	rt2800_bbp_write(rt2x00dev, 179, 0x02);
6838 	rt2800_bbp_write(rt2x00dev, 180, 0x00);
6839 	rt2800_bbp_write(rt2x00dev, 182, 0x40);
6840 	rt2800_bbp_write(rt2x00dev, 180, 0x01);
6841 	rt2800_bbp_write(rt2x00dev, 182, 0x9c);
6842 
6843 	rt2800_bbp_write(rt2x00dev, 179, 0x00);
6844 
6845 	/* Reprogram the inband interface to put right values in RXWI */
6846 	rt2800_bbp_write(rt2x00dev, 142, 0x04);
6847 	rt2800_bbp_write(rt2x00dev, 143, 0x3b);
6848 	rt2800_bbp_write(rt2x00dev, 142, 0x06);
6849 	rt2800_bbp_write(rt2x00dev, 143, 0xa0);
6850 	rt2800_bbp_write(rt2x00dev, 142, 0x07);
6851 	rt2800_bbp_write(rt2x00dev, 143, 0xa1);
6852 	rt2800_bbp_write(rt2x00dev, 142, 0x08);
6853 	rt2800_bbp_write(rt2x00dev, 143, 0xa2);
6854 	rt2800_bbp_write(rt2x00dev, 148, 0xc8);
6855 }
6856 
rt2800_init_bbp_53xx(struct rt2x00_dev * rt2x00dev)6857 static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev)
6858 {
6859 	int ant, div_mode;
6860 	u16 eeprom;
6861 	u8 value;
6862 
6863 	rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6864 
6865 	rt2800_bbp_write(rt2x00dev, 31, 0x08);
6866 
6867 	rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6868 	rt2800_bbp_write(rt2x00dev, 66, 0x38);
6869 
6870 	rt2800_bbp_write(rt2x00dev, 68, 0x0b);
6871 
6872 	rt2800_bbp_write(rt2x00dev, 69, 0x12);
6873 	rt2800_bbp_write(rt2x00dev, 73, 0x13);
6874 	rt2800_bbp_write(rt2x00dev, 75, 0x46);
6875 	rt2800_bbp_write(rt2x00dev, 76, 0x28);
6876 
6877 	rt2800_bbp_write(rt2x00dev, 77, 0x59);
6878 
6879 	rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6880 
6881 	rt2800_bbp_write(rt2x00dev, 79, 0x13);
6882 	rt2800_bbp_write(rt2x00dev, 80, 0x05);
6883 	rt2800_bbp_write(rt2x00dev, 81, 0x33);
6884 
6885 	rt2800_bbp_write(rt2x00dev, 82, 0x62);
6886 
6887 	rt2800_bbp_write(rt2x00dev, 83, 0x7a);
6888 
6889 	rt2800_bbp_write(rt2x00dev, 84, 0x9a);
6890 
6891 	rt2800_bbp_write(rt2x00dev, 86, 0x38);
6892 
6893 	if (rt2x00_rt(rt2x00dev, RT5392))
6894 		rt2800_bbp_write(rt2x00dev, 88, 0x90);
6895 
6896 	rt2800_bbp_write(rt2x00dev, 91, 0x04);
6897 
6898 	rt2800_bbp_write(rt2x00dev, 92, 0x02);
6899 
6900 	if (rt2x00_rt(rt2x00dev, RT5392)) {
6901 		rt2800_bbp_write(rt2x00dev, 95, 0x9a);
6902 		rt2800_bbp_write(rt2x00dev, 98, 0x12);
6903 	}
6904 
6905 	rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6906 
6907 	rt2800_bbp_write(rt2x00dev, 104, 0x92);
6908 
6909 	rt2800_bbp_write(rt2x00dev, 105, 0x3c);
6910 
6911 	if (rt2x00_rt(rt2x00dev, RT5390))
6912 		rt2800_bbp_write(rt2x00dev, 106, 0x03);
6913 	else if (rt2x00_rt(rt2x00dev, RT5392))
6914 		rt2800_bbp_write(rt2x00dev, 106, 0x12);
6915 	else
6916 		WARN_ON(1);
6917 
6918 	rt2800_bbp_write(rt2x00dev, 128, 0x12);
6919 
6920 	if (rt2x00_rt(rt2x00dev, RT5392)) {
6921 		rt2800_bbp_write(rt2x00dev, 134, 0xd0);
6922 		rt2800_bbp_write(rt2x00dev, 135, 0xf6);
6923 	}
6924 
6925 	rt2800_disable_unused_dac_adc(rt2x00dev);
6926 
6927 	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
6928 	div_mode = rt2x00_get_field16(eeprom,
6929 				      EEPROM_NIC_CONF1_ANT_DIVERSITY);
6930 	ant = (div_mode == 3) ? 1 : 0;
6931 
6932 	/* check if this is a Bluetooth combo card */
6933 	if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
6934 		u32 reg;
6935 
6936 		reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
6937 		rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
6938 		rt2x00_set_field32(&reg, GPIO_CTRL_DIR6, 0);
6939 		rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 0);
6940 		rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 0);
6941 		if (ant == 0)
6942 			rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 1);
6943 		else if (ant == 1)
6944 			rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 1);
6945 		rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
6946 	}
6947 
6948 	/* These chips have hardware RX antenna diversity */
6949 	if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R) ||
6950 	    rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5370G)) {
6951 		rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
6952 		rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
6953 		rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
6954 	}
6955 
6956 	value = rt2800_bbp_read(rt2x00dev, 152);
6957 	if (ant == 0)
6958 		rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
6959 	else
6960 		rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
6961 	rt2800_bbp_write(rt2x00dev, 152, value);
6962 
6963 	rt2800_init_freq_calibration(rt2x00dev);
6964 }
6965 
rt2800_init_bbp_5592(struct rt2x00_dev * rt2x00dev)6966 static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev)
6967 {
6968 	int ant, div_mode;
6969 	u16 eeprom;
6970 	u8 value;
6971 
6972 	rt2800_init_bbp_early(rt2x00dev);
6973 
6974 	value = rt2800_bbp_read(rt2x00dev, 105);
6975 	rt2x00_set_field8(&value, BBP105_MLD,
6976 			  rt2x00dev->default_ant.rx_chain_num == 2);
6977 	rt2800_bbp_write(rt2x00dev, 105, value);
6978 
6979 	rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6980 
6981 	rt2800_bbp_write(rt2x00dev, 20, 0x06);
6982 	rt2800_bbp_write(rt2x00dev, 31, 0x08);
6983 	rt2800_bbp_write(rt2x00dev, 65, 0x2C);
6984 	rt2800_bbp_write(rt2x00dev, 68, 0xDD);
6985 	rt2800_bbp_write(rt2x00dev, 69, 0x1A);
6986 	rt2800_bbp_write(rt2x00dev, 70, 0x05);
6987 	rt2800_bbp_write(rt2x00dev, 73, 0x13);
6988 	rt2800_bbp_write(rt2x00dev, 74, 0x0F);
6989 	rt2800_bbp_write(rt2x00dev, 75, 0x4F);
6990 	rt2800_bbp_write(rt2x00dev, 76, 0x28);
6991 	rt2800_bbp_write(rt2x00dev, 77, 0x59);
6992 	rt2800_bbp_write(rt2x00dev, 84, 0x9A);
6993 	rt2800_bbp_write(rt2x00dev, 86, 0x38);
6994 	rt2800_bbp_write(rt2x00dev, 88, 0x90);
6995 	rt2800_bbp_write(rt2x00dev, 91, 0x04);
6996 	rt2800_bbp_write(rt2x00dev, 92, 0x02);
6997 	rt2800_bbp_write(rt2x00dev, 95, 0x9a);
6998 	rt2800_bbp_write(rt2x00dev, 98, 0x12);
6999 	rt2800_bbp_write(rt2x00dev, 103, 0xC0);
7000 	rt2800_bbp_write(rt2x00dev, 104, 0x92);
7001 	/* FIXME BBP105 owerwrite */
7002 	rt2800_bbp_write(rt2x00dev, 105, 0x3C);
7003 	rt2800_bbp_write(rt2x00dev, 106, 0x35);
7004 	rt2800_bbp_write(rt2x00dev, 128, 0x12);
7005 	rt2800_bbp_write(rt2x00dev, 134, 0xD0);
7006 	rt2800_bbp_write(rt2x00dev, 135, 0xF6);
7007 	rt2800_bbp_write(rt2x00dev, 137, 0x0F);
7008 
7009 	/* Initialize GLRT (Generalized Likehood Radio Test) */
7010 	rt2800_init_bbp_5592_glrt(rt2x00dev);
7011 
7012 	rt2800_bbp4_mac_if_ctrl(rt2x00dev);
7013 
7014 	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
7015 	div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY);
7016 	ant = (div_mode == 3) ? 1 : 0;
7017 	value = rt2800_bbp_read(rt2x00dev, 152);
7018 	if (ant == 0) {
7019 		/* Main antenna */
7020 		rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
7021 	} else {
7022 		/* Auxiliary antenna */
7023 		rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
7024 	}
7025 	rt2800_bbp_write(rt2x00dev, 152, value);
7026 
7027 	if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) {
7028 		value = rt2800_bbp_read(rt2x00dev, 254);
7029 		rt2x00_set_field8(&value, BBP254_BIT7, 1);
7030 		rt2800_bbp_write(rt2x00dev, 254, value);
7031 	}
7032 
7033 	rt2800_init_freq_calibration(rt2x00dev);
7034 
7035 	rt2800_bbp_write(rt2x00dev, 84, 0x19);
7036 	if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
7037 		rt2800_bbp_write(rt2x00dev, 103, 0xc0);
7038 }
7039 
rt2800_init_bbp_6352(struct rt2x00_dev * rt2x00dev)7040 static void rt2800_init_bbp_6352(struct rt2x00_dev *rt2x00dev)
7041 {
7042 	u8 bbp;
7043 
7044 	/* Apply Maximum Likelihood Detection (MLD) for 2 stream case */
7045 	bbp = rt2800_bbp_read(rt2x00dev, 105);
7046 	rt2x00_set_field8(&bbp, BBP105_MLD,
7047 			  rt2x00dev->default_ant.rx_chain_num == 2);
7048 	rt2800_bbp_write(rt2x00dev, 105, bbp);
7049 
7050 	/* Avoid data loss and CRC errors */
7051 	rt2800_bbp4_mac_if_ctrl(rt2x00dev);
7052 
7053 	/* Fix I/Q swap issue */
7054 	bbp = rt2800_bbp_read(rt2x00dev, 1);
7055 	bbp |= 0x04;
7056 	rt2800_bbp_write(rt2x00dev, 1, bbp);
7057 
7058 	/* BBP for G band */
7059 	rt2800_bbp_write(rt2x00dev, 3, 0x08);
7060 	rt2800_bbp_write(rt2x00dev, 4, 0x00); /* rt2800_bbp4_mac_if_ctrl? */
7061 	rt2800_bbp_write(rt2x00dev, 6, 0x08);
7062 	rt2800_bbp_write(rt2x00dev, 14, 0x09);
7063 	rt2800_bbp_write(rt2x00dev, 15, 0xFF);
7064 	rt2800_bbp_write(rt2x00dev, 16, 0x01);
7065 	rt2800_bbp_write(rt2x00dev, 20, 0x06);
7066 	rt2800_bbp_write(rt2x00dev, 21, 0x00);
7067 	rt2800_bbp_write(rt2x00dev, 22, 0x00);
7068 	rt2800_bbp_write(rt2x00dev, 27, 0x00);
7069 	rt2800_bbp_write(rt2x00dev, 28, 0x00);
7070 	rt2800_bbp_write(rt2x00dev, 30, 0x00);
7071 	rt2800_bbp_write(rt2x00dev, 31, 0x48);
7072 	rt2800_bbp_write(rt2x00dev, 47, 0x40);
7073 	rt2800_bbp_write(rt2x00dev, 62, 0x00);
7074 	rt2800_bbp_write(rt2x00dev, 63, 0x00);
7075 	rt2800_bbp_write(rt2x00dev, 64, 0x00);
7076 	rt2800_bbp_write(rt2x00dev, 65, 0x2C);
7077 	rt2800_bbp_write(rt2x00dev, 66, 0x1C);
7078 	rt2800_bbp_write(rt2x00dev, 67, 0x20);
7079 	rt2800_bbp_write(rt2x00dev, 68, 0xDD);
7080 	rt2800_bbp_write(rt2x00dev, 69, 0x10);
7081 	rt2800_bbp_write(rt2x00dev, 70, 0x05);
7082 	rt2800_bbp_write(rt2x00dev, 73, 0x18);
7083 	rt2800_bbp_write(rt2x00dev, 74, 0x0F);
7084 	rt2800_bbp_write(rt2x00dev, 75, 0x60);
7085 	rt2800_bbp_write(rt2x00dev, 76, 0x44);
7086 	rt2800_bbp_write(rt2x00dev, 77, 0x59);
7087 	rt2800_bbp_write(rt2x00dev, 78, 0x1E);
7088 	rt2800_bbp_write(rt2x00dev, 79, 0x1C);
7089 	rt2800_bbp_write(rt2x00dev, 80, 0x0C);
7090 	rt2800_bbp_write(rt2x00dev, 81, 0x3A);
7091 	rt2800_bbp_write(rt2x00dev, 82, 0xB6);
7092 	rt2800_bbp_write(rt2x00dev, 83, 0x9A);
7093 	rt2800_bbp_write(rt2x00dev, 84, 0x9A);
7094 	rt2800_bbp_write(rt2x00dev, 86, 0x38);
7095 	rt2800_bbp_write(rt2x00dev, 88, 0x90);
7096 	rt2800_bbp_write(rt2x00dev, 91, 0x04);
7097 	rt2800_bbp_write(rt2x00dev, 92, 0x02);
7098 	rt2800_bbp_write(rt2x00dev, 95, 0x9A);
7099 	rt2800_bbp_write(rt2x00dev, 96, 0x00);
7100 	rt2800_bbp_write(rt2x00dev, 103, 0xC0);
7101 	rt2800_bbp_write(rt2x00dev, 104, 0x92);
7102 	/* FIXME BBP105 owerwrite */
7103 	rt2800_bbp_write(rt2x00dev, 105, 0x3C);
7104 	rt2800_bbp_write(rt2x00dev, 106, 0x12);
7105 	rt2800_bbp_write(rt2x00dev, 109, 0x00);
7106 	rt2800_bbp_write(rt2x00dev, 134, 0x10);
7107 	rt2800_bbp_write(rt2x00dev, 135, 0xA6);
7108 	rt2800_bbp_write(rt2x00dev, 137, 0x04);
7109 	rt2800_bbp_write(rt2x00dev, 142, 0x30);
7110 	rt2800_bbp_write(rt2x00dev, 143, 0xF7);
7111 	rt2800_bbp_write(rt2x00dev, 160, 0xEC);
7112 	rt2800_bbp_write(rt2x00dev, 161, 0xC4);
7113 	rt2800_bbp_write(rt2x00dev, 162, 0x77);
7114 	rt2800_bbp_write(rt2x00dev, 163, 0xF9);
7115 	rt2800_bbp_write(rt2x00dev, 164, 0x00);
7116 	rt2800_bbp_write(rt2x00dev, 165, 0x00);
7117 	rt2800_bbp_write(rt2x00dev, 186, 0x00);
7118 	rt2800_bbp_write(rt2x00dev, 187, 0x00);
7119 	rt2800_bbp_write(rt2x00dev, 188, 0x00);
7120 	rt2800_bbp_write(rt2x00dev, 186, 0x00);
7121 	rt2800_bbp_write(rt2x00dev, 187, 0x01);
7122 	rt2800_bbp_write(rt2x00dev, 188, 0x00);
7123 	rt2800_bbp_write(rt2x00dev, 189, 0x00);
7124 
7125 	rt2800_bbp_write(rt2x00dev, 91, 0x06);
7126 	rt2800_bbp_write(rt2x00dev, 92, 0x04);
7127 	rt2800_bbp_write(rt2x00dev, 93, 0x54);
7128 	rt2800_bbp_write(rt2x00dev, 99, 0x50);
7129 	rt2800_bbp_write(rt2x00dev, 148, 0x84);
7130 	rt2800_bbp_write(rt2x00dev, 167, 0x80);
7131 	rt2800_bbp_write(rt2x00dev, 178, 0xFF);
7132 	rt2800_bbp_write(rt2x00dev, 106, 0x13);
7133 
7134 	/* BBP for G band GLRT function (BBP_128 ~ BBP_221) */
7135 	rt2800_bbp_glrt_write(rt2x00dev, 0, 0x00);
7136 	rt2800_bbp_glrt_write(rt2x00dev, 1, 0x14);
7137 	rt2800_bbp_glrt_write(rt2x00dev, 2, 0x20);
7138 	rt2800_bbp_glrt_write(rt2x00dev, 3, 0x0A);
7139 	rt2800_bbp_glrt_write(rt2x00dev, 10, 0x16);
7140 	rt2800_bbp_glrt_write(rt2x00dev, 11, 0x06);
7141 	rt2800_bbp_glrt_write(rt2x00dev, 12, 0x02);
7142 	rt2800_bbp_glrt_write(rt2x00dev, 13, 0x07);
7143 	rt2800_bbp_glrt_write(rt2x00dev, 14, 0x05);
7144 	rt2800_bbp_glrt_write(rt2x00dev, 15, 0x09);
7145 	rt2800_bbp_glrt_write(rt2x00dev, 16, 0x20);
7146 	rt2800_bbp_glrt_write(rt2x00dev, 17, 0x08);
7147 	rt2800_bbp_glrt_write(rt2x00dev, 18, 0x4A);
7148 	rt2800_bbp_glrt_write(rt2x00dev, 19, 0x00);
7149 	rt2800_bbp_glrt_write(rt2x00dev, 20, 0x00);
7150 	rt2800_bbp_glrt_write(rt2x00dev, 128, 0xE0);
7151 	rt2800_bbp_glrt_write(rt2x00dev, 129, 0x1F);
7152 	rt2800_bbp_glrt_write(rt2x00dev, 130, 0x4F);
7153 	rt2800_bbp_glrt_write(rt2x00dev, 131, 0x32);
7154 	rt2800_bbp_glrt_write(rt2x00dev, 132, 0x08);
7155 	rt2800_bbp_glrt_write(rt2x00dev, 133, 0x28);
7156 	rt2800_bbp_glrt_write(rt2x00dev, 134, 0x19);
7157 	rt2800_bbp_glrt_write(rt2x00dev, 135, 0x0A);
7158 	rt2800_bbp_glrt_write(rt2x00dev, 138, 0x16);
7159 	rt2800_bbp_glrt_write(rt2x00dev, 139, 0x10);
7160 	rt2800_bbp_glrt_write(rt2x00dev, 140, 0x10);
7161 	rt2800_bbp_glrt_write(rt2x00dev, 141, 0x1A);
7162 	rt2800_bbp_glrt_write(rt2x00dev, 142, 0x36);
7163 	rt2800_bbp_glrt_write(rt2x00dev, 143, 0x2C);
7164 	rt2800_bbp_glrt_write(rt2x00dev, 144, 0x26);
7165 	rt2800_bbp_glrt_write(rt2x00dev, 145, 0x24);
7166 	rt2800_bbp_glrt_write(rt2x00dev, 146, 0x42);
7167 	rt2800_bbp_glrt_write(rt2x00dev, 147, 0x40);
7168 	rt2800_bbp_glrt_write(rt2x00dev, 148, 0x30);
7169 	rt2800_bbp_glrt_write(rt2x00dev, 149, 0x29);
7170 	rt2800_bbp_glrt_write(rt2x00dev, 150, 0x4C);
7171 	rt2800_bbp_glrt_write(rt2x00dev, 151, 0x46);
7172 	rt2800_bbp_glrt_write(rt2x00dev, 152, 0x3D);
7173 	rt2800_bbp_glrt_write(rt2x00dev, 153, 0x40);
7174 	rt2800_bbp_glrt_write(rt2x00dev, 154, 0x3E);
7175 	rt2800_bbp_glrt_write(rt2x00dev, 155, 0x38);
7176 	rt2800_bbp_glrt_write(rt2x00dev, 156, 0x3D);
7177 	rt2800_bbp_glrt_write(rt2x00dev, 157, 0x2F);
7178 	rt2800_bbp_glrt_write(rt2x00dev, 158, 0x3C);
7179 	rt2800_bbp_glrt_write(rt2x00dev, 159, 0x34);
7180 	rt2800_bbp_glrt_write(rt2x00dev, 160, 0x2C);
7181 	rt2800_bbp_glrt_write(rt2x00dev, 161, 0x2F);
7182 	rt2800_bbp_glrt_write(rt2x00dev, 162, 0x3C);
7183 	rt2800_bbp_glrt_write(rt2x00dev, 163, 0x35);
7184 	rt2800_bbp_glrt_write(rt2x00dev, 164, 0x2E);
7185 	rt2800_bbp_glrt_write(rt2x00dev, 165, 0x2F);
7186 	rt2800_bbp_glrt_write(rt2x00dev, 166, 0x49);
7187 	rt2800_bbp_glrt_write(rt2x00dev, 167, 0x41);
7188 	rt2800_bbp_glrt_write(rt2x00dev, 168, 0x36);
7189 	rt2800_bbp_glrt_write(rt2x00dev, 169, 0x39);
7190 	rt2800_bbp_glrt_write(rt2x00dev, 170, 0x30);
7191 	rt2800_bbp_glrt_write(rt2x00dev, 171, 0x30);
7192 	rt2800_bbp_glrt_write(rt2x00dev, 172, 0x0E);
7193 	rt2800_bbp_glrt_write(rt2x00dev, 173, 0x0D);
7194 	rt2800_bbp_glrt_write(rt2x00dev, 174, 0x28);
7195 	rt2800_bbp_glrt_write(rt2x00dev, 175, 0x21);
7196 	rt2800_bbp_glrt_write(rt2x00dev, 176, 0x1C);
7197 	rt2800_bbp_glrt_write(rt2x00dev, 177, 0x16);
7198 	rt2800_bbp_glrt_write(rt2x00dev, 178, 0x50);
7199 	rt2800_bbp_glrt_write(rt2x00dev, 179, 0x4A);
7200 	rt2800_bbp_glrt_write(rt2x00dev, 180, 0x43);
7201 	rt2800_bbp_glrt_write(rt2x00dev, 181, 0x50);
7202 	rt2800_bbp_glrt_write(rt2x00dev, 182, 0x10);
7203 	rt2800_bbp_glrt_write(rt2x00dev, 183, 0x10);
7204 	rt2800_bbp_glrt_write(rt2x00dev, 184, 0x10);
7205 	rt2800_bbp_glrt_write(rt2x00dev, 185, 0x10);
7206 	rt2800_bbp_glrt_write(rt2x00dev, 200, 0x7D);
7207 	rt2800_bbp_glrt_write(rt2x00dev, 201, 0x14);
7208 	rt2800_bbp_glrt_write(rt2x00dev, 202, 0x32);
7209 	rt2800_bbp_glrt_write(rt2x00dev, 203, 0x2C);
7210 	rt2800_bbp_glrt_write(rt2x00dev, 204, 0x36);
7211 	rt2800_bbp_glrt_write(rt2x00dev, 205, 0x4C);
7212 	rt2800_bbp_glrt_write(rt2x00dev, 206, 0x43);
7213 	rt2800_bbp_glrt_write(rt2x00dev, 207, 0x2C);
7214 	rt2800_bbp_glrt_write(rt2x00dev, 208, 0x2E);
7215 	rt2800_bbp_glrt_write(rt2x00dev, 209, 0x36);
7216 	rt2800_bbp_glrt_write(rt2x00dev, 210, 0x30);
7217 	rt2800_bbp_glrt_write(rt2x00dev, 211, 0x6E);
7218 
7219 	/* BBP for G band DCOC function */
7220 	rt2800_bbp_dcoc_write(rt2x00dev, 140, 0x0C);
7221 	rt2800_bbp_dcoc_write(rt2x00dev, 141, 0x00);
7222 	rt2800_bbp_dcoc_write(rt2x00dev, 142, 0x10);
7223 	rt2800_bbp_dcoc_write(rt2x00dev, 143, 0x10);
7224 	rt2800_bbp_dcoc_write(rt2x00dev, 144, 0x10);
7225 	rt2800_bbp_dcoc_write(rt2x00dev, 145, 0x10);
7226 	rt2800_bbp_dcoc_write(rt2x00dev, 146, 0x08);
7227 	rt2800_bbp_dcoc_write(rt2x00dev, 147, 0x40);
7228 	rt2800_bbp_dcoc_write(rt2x00dev, 148, 0x04);
7229 	rt2800_bbp_dcoc_write(rt2x00dev, 149, 0x04);
7230 	rt2800_bbp_dcoc_write(rt2x00dev, 150, 0x08);
7231 	rt2800_bbp_dcoc_write(rt2x00dev, 151, 0x08);
7232 	rt2800_bbp_dcoc_write(rt2x00dev, 152, 0x03);
7233 	rt2800_bbp_dcoc_write(rt2x00dev, 153, 0x03);
7234 	rt2800_bbp_dcoc_write(rt2x00dev, 154, 0x03);
7235 	rt2800_bbp_dcoc_write(rt2x00dev, 155, 0x02);
7236 	rt2800_bbp_dcoc_write(rt2x00dev, 156, 0x40);
7237 	rt2800_bbp_dcoc_write(rt2x00dev, 157, 0x40);
7238 	rt2800_bbp_dcoc_write(rt2x00dev, 158, 0x64);
7239 	rt2800_bbp_dcoc_write(rt2x00dev, 159, 0x64);
7240 
7241 	rt2800_bbp4_mac_if_ctrl(rt2x00dev);
7242 
7243 	rt2800_bbp_write(rt2x00dev, 84, 0x19);
7244 }
7245 
rt2800_init_bbp(struct rt2x00_dev * rt2x00dev)7246 static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
7247 {
7248 	unsigned int i;
7249 	u16 eeprom;
7250 	u8 reg_id;
7251 	u8 value;
7252 
7253 	if (rt2800_is_305x_soc(rt2x00dev))
7254 		rt2800_init_bbp_305x_soc(rt2x00dev);
7255 
7256 	switch (rt2x00dev->chip.rt) {
7257 	case RT2860:
7258 	case RT2872:
7259 	case RT2883:
7260 		rt2800_init_bbp_28xx(rt2x00dev);
7261 		break;
7262 	case RT3070:
7263 	case RT3071:
7264 	case RT3090:
7265 		rt2800_init_bbp_30xx(rt2x00dev);
7266 		break;
7267 	case RT3290:
7268 		rt2800_init_bbp_3290(rt2x00dev);
7269 		break;
7270 	case RT3352:
7271 	case RT5350:
7272 		rt2800_init_bbp_3352(rt2x00dev);
7273 		break;
7274 	case RT3390:
7275 		rt2800_init_bbp_3390(rt2x00dev);
7276 		break;
7277 	case RT3572:
7278 		rt2800_init_bbp_3572(rt2x00dev);
7279 		break;
7280 	case RT3593:
7281 		rt2800_init_bbp_3593(rt2x00dev);
7282 		return;
7283 	case RT3883:
7284 		rt2800_init_bbp_3883(rt2x00dev);
7285 		return;
7286 	case RT5390:
7287 	case RT5392:
7288 		rt2800_init_bbp_53xx(rt2x00dev);
7289 		break;
7290 	case RT5592:
7291 		rt2800_init_bbp_5592(rt2x00dev);
7292 		return;
7293 	case RT6352:
7294 		rt2800_init_bbp_6352(rt2x00dev);
7295 		break;
7296 	}
7297 
7298 	for (i = 0; i < EEPROM_BBP_SIZE; i++) {
7299 		eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
7300 						       EEPROM_BBP_START, i);
7301 
7302 		if (eeprom != 0xffff && eeprom != 0x0000) {
7303 			reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
7304 			value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
7305 			rt2800_bbp_write(rt2x00dev, reg_id, value);
7306 		}
7307 	}
7308 }
7309 
rt2800_led_open_drain_enable(struct rt2x00_dev * rt2x00dev)7310 static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev)
7311 {
7312 	u32 reg;
7313 
7314 	reg = rt2800_register_read(rt2x00dev, OPT_14_CSR);
7315 	rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
7316 	rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
7317 }
7318 
rt2800_init_rx_filter(struct rt2x00_dev * rt2x00dev,bool bw40,u8 filter_target)7319 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40,
7320 				u8 filter_target)
7321 {
7322 	unsigned int i;
7323 	u8 bbp;
7324 	u8 rfcsr;
7325 	u8 passband;
7326 	u8 stopband;
7327 	u8 overtuned = 0;
7328 	u8 rfcsr24 = (bw40) ? 0x27 : 0x07;
7329 
7330 	rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
7331 
7332 	bbp = rt2800_bbp_read(rt2x00dev, 4);
7333 	rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
7334 	rt2800_bbp_write(rt2x00dev, 4, bbp);
7335 
7336 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 31);
7337 	rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
7338 	rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
7339 
7340 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
7341 	rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
7342 	rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
7343 
7344 	/*
7345 	 * Set power & frequency of passband test tone
7346 	 */
7347 	rt2800_bbp_write(rt2x00dev, 24, 0);
7348 
7349 	for (i = 0; i < 100; i++) {
7350 		rt2800_bbp_write(rt2x00dev, 25, 0x90);
7351 		msleep(1);
7352 
7353 		passband = rt2800_bbp_read(rt2x00dev, 55);
7354 		if (passband)
7355 			break;
7356 	}
7357 
7358 	/*
7359 	 * Set power & frequency of stopband test tone
7360 	 */
7361 	rt2800_bbp_write(rt2x00dev, 24, 0x06);
7362 
7363 	for (i = 0; i < 100; i++) {
7364 		rt2800_bbp_write(rt2x00dev, 25, 0x90);
7365 		msleep(1);
7366 
7367 		stopband = rt2800_bbp_read(rt2x00dev, 55);
7368 
7369 		if ((passband - stopband) <= filter_target) {
7370 			rfcsr24++;
7371 			overtuned += ((passband - stopband) == filter_target);
7372 		} else
7373 			break;
7374 
7375 		rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
7376 	}
7377 
7378 	rfcsr24 -= !!overtuned;
7379 
7380 	rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
7381 	return rfcsr24;
7382 }
7383 
rt2800_rf_init_calibration(struct rt2x00_dev * rt2x00dev,const unsigned int rf_reg)7384 static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev,
7385 				       const unsigned int rf_reg)
7386 {
7387 	u8 rfcsr;
7388 
7389 	rfcsr = rt2800_rfcsr_read(rt2x00dev, rf_reg);
7390 	rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1);
7391 	rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
7392 	msleep(1);
7393 	rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0);
7394 	rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
7395 }
7396 
rt2800_rx_filter_calibration(struct rt2x00_dev * rt2x00dev)7397 static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev)
7398 {
7399 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
7400 	u8 filter_tgt_bw20;
7401 	u8 filter_tgt_bw40;
7402 	u8 rfcsr, bbp;
7403 
7404 	/*
7405 	 * TODO: sync filter_tgt values with vendor driver
7406 	 */
7407 	if (rt2x00_rt(rt2x00dev, RT3070)) {
7408 		filter_tgt_bw20 = 0x16;
7409 		filter_tgt_bw40 = 0x19;
7410 	} else {
7411 		filter_tgt_bw20 = 0x13;
7412 		filter_tgt_bw40 = 0x15;
7413 	}
7414 
7415 	drv_data->calibration_bw20 =
7416 		rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20);
7417 	drv_data->calibration_bw40 =
7418 		rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40);
7419 
7420 	/*
7421 	 * Save BBP 25 & 26 values for later use in channel switching (for 3052)
7422 	 */
7423 	drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25);
7424 	drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26);
7425 
7426 	/*
7427 	 * Set back to initial state
7428 	 */
7429 	rt2800_bbp_write(rt2x00dev, 24, 0);
7430 
7431 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
7432 	rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
7433 	rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
7434 
7435 	/*
7436 	 * Set BBP back to BW20
7437 	 */
7438 	bbp = rt2800_bbp_read(rt2x00dev, 4);
7439 	rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
7440 	rt2800_bbp_write(rt2x00dev, 4, bbp);
7441 }
7442 
rt2800_normal_mode_setup_3xxx(struct rt2x00_dev * rt2x00dev)7443 static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev)
7444 {
7445 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
7446 	u8 min_gain, rfcsr, bbp;
7447 	u16 eeprom;
7448 
7449 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 17);
7450 
7451 	rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
7452 	if (rt2x00_rt(rt2x00dev, RT3070) ||
7453 	    rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
7454 	    rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
7455 	    rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
7456 		if (!rt2x00_has_cap_external_lna_bg(rt2x00dev))
7457 			rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
7458 	}
7459 
7460 	min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2;
7461 	if (drv_data->txmixer_gain_24g >= min_gain) {
7462 		rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
7463 				  drv_data->txmixer_gain_24g);
7464 	}
7465 
7466 	rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
7467 
7468 	if (rt2x00_rt(rt2x00dev, RT3090)) {
7469 		/*  Turn off unused DAC1 and ADC1 to reduce power consumption */
7470 		bbp = rt2800_bbp_read(rt2x00dev, 138);
7471 		eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
7472 		if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
7473 			rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
7474 		if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
7475 			rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
7476 		rt2800_bbp_write(rt2x00dev, 138, bbp);
7477 	}
7478 
7479 	if (rt2x00_rt(rt2x00dev, RT3070)) {
7480 		rfcsr = rt2800_rfcsr_read(rt2x00dev, 27);
7481 		if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
7482 			rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
7483 		else
7484 			rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
7485 		rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
7486 		rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
7487 		rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
7488 		rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
7489 	} else if (rt2x00_rt(rt2x00dev, RT3071) ||
7490 		   rt2x00_rt(rt2x00dev, RT3090) ||
7491 		   rt2x00_rt(rt2x00dev, RT3390)) {
7492 		rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
7493 		rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
7494 		rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
7495 		rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
7496 		rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
7497 		rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
7498 		rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
7499 
7500 		rfcsr = rt2800_rfcsr_read(rt2x00dev, 15);
7501 		rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
7502 		rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
7503 
7504 		rfcsr = rt2800_rfcsr_read(rt2x00dev, 20);
7505 		rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
7506 		rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
7507 
7508 		rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
7509 		rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
7510 		rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
7511 	}
7512 }
7513 
rt2800_normal_mode_setup_3593(struct rt2x00_dev * rt2x00dev)7514 static void rt2800_normal_mode_setup_3593(struct rt2x00_dev *rt2x00dev)
7515 {
7516 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
7517 	u8 rfcsr;
7518 	u8 tx_gain;
7519 
7520 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
7521 	rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO2_EN, 0);
7522 	rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
7523 
7524 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
7525 	tx_gain = rt2x00_get_field8(drv_data->txmixer_gain_24g,
7526 				    RFCSR17_TXMIXER_GAIN);
7527 	rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, tx_gain);
7528 	rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
7529 
7530 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 38);
7531 	rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
7532 	rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
7533 
7534 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 39);
7535 	rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
7536 	rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
7537 
7538 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
7539 	rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
7540 	rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
7541 	rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
7542 
7543 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
7544 	rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
7545 	rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
7546 
7547 	/* TODO: enable stream mode */
7548 }
7549 
rt2800_normal_mode_setup_5xxx(struct rt2x00_dev * rt2x00dev)7550 static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev)
7551 {
7552 	u8 reg;
7553 	u16 eeprom;
7554 
7555 	/*  Turn off unused DAC1 and ADC1 to reduce power consumption */
7556 	reg = rt2800_bbp_read(rt2x00dev, 138);
7557 	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
7558 	if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
7559 		rt2x00_set_field8(&reg, BBP138_RX_ADC1, 0);
7560 	if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
7561 		rt2x00_set_field8(&reg, BBP138_TX_DAC1, 1);
7562 	rt2800_bbp_write(rt2x00dev, 138, reg);
7563 
7564 	reg = rt2800_rfcsr_read(rt2x00dev, 38);
7565 	rt2x00_set_field8(&reg, RFCSR38_RX_LO1_EN, 0);
7566 	rt2800_rfcsr_write(rt2x00dev, 38, reg);
7567 
7568 	reg = rt2800_rfcsr_read(rt2x00dev, 39);
7569 	rt2x00_set_field8(&reg, RFCSR39_RX_LO2_EN, 0);
7570 	rt2800_rfcsr_write(rt2x00dev, 39, reg);
7571 
7572 	rt2800_bbp4_mac_if_ctrl(rt2x00dev);
7573 
7574 	reg = rt2800_rfcsr_read(rt2x00dev, 30);
7575 	rt2x00_set_field8(&reg, RFCSR30_RX_VCM, 2);
7576 	rt2800_rfcsr_write(rt2x00dev, 30, reg);
7577 }
7578 
rt2800_init_rfcsr_305x_soc(struct rt2x00_dev * rt2x00dev)7579 static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev)
7580 {
7581 	rt2800_rf_init_calibration(rt2x00dev, 30);
7582 
7583 	rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
7584 	rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
7585 	rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
7586 	rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
7587 	rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
7588 	rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
7589 	rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
7590 	rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
7591 	rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
7592 	rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
7593 	rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
7594 	rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
7595 	rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
7596 	rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
7597 	rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
7598 	rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
7599 	rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
7600 	rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
7601 	rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
7602 	rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
7603 	rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
7604 	rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
7605 	rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7606 	rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
7607 	rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
7608 	rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
7609 	rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
7610 	rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
7611 	rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
7612 	rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
7613 	rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
7614 	rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
7615 }
7616 
rt2800_init_rfcsr_30xx(struct rt2x00_dev * rt2x00dev)7617 static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev)
7618 {
7619 	u8 rfcsr;
7620 	u16 eeprom;
7621 	u32 reg;
7622 
7623 	/* XXX vendor driver do this only for 3070 */
7624 	rt2800_rf_init_calibration(rt2x00dev, 30);
7625 
7626 	rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
7627 	rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
7628 	rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
7629 	rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
7630 	rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
7631 	rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
7632 	rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
7633 	rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
7634 	rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
7635 	rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
7636 	rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
7637 	rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
7638 	rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
7639 	rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
7640 	rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
7641 	rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
7642 	rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
7643 	rt2800_rfcsr_write(rt2x00dev, 25, 0x03);
7644 	rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
7645 
7646 	if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
7647 		reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7648 		rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
7649 		rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
7650 		rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7651 	} else if (rt2x00_rt(rt2x00dev, RT3071) ||
7652 		   rt2x00_rt(rt2x00dev, RT3090)) {
7653 		rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
7654 
7655 		rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
7656 		rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
7657 		rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
7658 
7659 		reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7660 		rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
7661 		if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
7662 		    rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
7663 			eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
7664 			if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
7665 				rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
7666 			else
7667 				rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
7668 		}
7669 		rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7670 
7671 		reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
7672 		rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
7673 		rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
7674 	}
7675 
7676 	rt2800_rx_filter_calibration(rt2x00dev);
7677 
7678 	if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
7679 	    rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
7680 	    rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E))
7681 		rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
7682 
7683 	rt2800_led_open_drain_enable(rt2x00dev);
7684 	rt2800_normal_mode_setup_3xxx(rt2x00dev);
7685 }
7686 
rt2800_init_rfcsr_3290(struct rt2x00_dev * rt2x00dev)7687 static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev)
7688 {
7689 	u8 rfcsr;
7690 
7691 	rt2800_rf_init_calibration(rt2x00dev, 2);
7692 
7693 	rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
7694 	rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
7695 	rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
7696 	rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
7697 	rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
7698 	rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
7699 	rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
7700 	rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
7701 	rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
7702 	rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
7703 	rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
7704 	rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
7705 	rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
7706 	rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
7707 	rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
7708 	rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
7709 	rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
7710 	rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7711 	rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7712 	rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
7713 	rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
7714 	rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
7715 	rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
7716 	rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
7717 	rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
7718 	rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
7719 	rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
7720 	rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
7721 	rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
7722 	rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
7723 	rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
7724 	rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
7725 	rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
7726 	rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
7727 	rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
7728 	rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
7729 	rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
7730 	rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
7731 	rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
7732 	rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
7733 	rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
7734 	rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
7735 	rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
7736 	rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
7737 	rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
7738 	rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
7739 
7740 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 29);
7741 	rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
7742 	rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
7743 
7744 	rt2800_led_open_drain_enable(rt2x00dev);
7745 	rt2800_normal_mode_setup_3xxx(rt2x00dev);
7746 }
7747 
rt2800_init_rfcsr_3352(struct rt2x00_dev * rt2x00dev)7748 static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev)
7749 {
7750 	int tx0_ext_pa = test_bit(CAPABILITY_EXTERNAL_PA_TX0,
7751 				  &rt2x00dev->cap_flags);
7752 	int tx1_ext_pa = test_bit(CAPABILITY_EXTERNAL_PA_TX1,
7753 				  &rt2x00dev->cap_flags);
7754 	u8 rfcsr;
7755 
7756 	rt2800_rf_init_calibration(rt2x00dev, 30);
7757 
7758 	rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
7759 	rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
7760 	rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
7761 	rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
7762 	rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
7763 	rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
7764 	rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
7765 	rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
7766 	rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
7767 	rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
7768 	rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
7769 	rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
7770 	rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
7771 	rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
7772 	rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
7773 	rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
7774 	rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
7775 	rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
7776 	rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
7777 	rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
7778 	rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
7779 	rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7780 	rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
7781 	rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
7782 	rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
7783 	rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
7784 	rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
7785 	rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
7786 	rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
7787 	rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7788 	rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7789 	rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
7790 	rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
7791 	rfcsr = 0x01;
7792 	if (tx0_ext_pa)
7793 		rt2x00_set_field8(&rfcsr, RFCSR34_TX0_EXT_PA, 1);
7794 	if (tx1_ext_pa)
7795 		rt2x00_set_field8(&rfcsr, RFCSR34_TX1_EXT_PA, 1);
7796 	rt2800_rfcsr_write(rt2x00dev, 34, rfcsr);
7797 	rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
7798 	rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
7799 	rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
7800 	rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
7801 	rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
7802 	rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
7803 	rfcsr = 0x52;
7804 	if (!tx0_ext_pa) {
7805 		rt2x00_set_field8(&rfcsr, RFCSR41_BIT1, 1);
7806 		rt2x00_set_field8(&rfcsr, RFCSR41_BIT4, 1);
7807 	}
7808 	rt2800_rfcsr_write(rt2x00dev, 41, rfcsr);
7809 	rfcsr = 0x52;
7810 	if (!tx1_ext_pa) {
7811 		rt2x00_set_field8(&rfcsr, RFCSR42_BIT1, 1);
7812 		rt2x00_set_field8(&rfcsr, RFCSR42_BIT4, 1);
7813 	}
7814 	rt2800_rfcsr_write(rt2x00dev, 42, rfcsr);
7815 	rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
7816 	rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
7817 	rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
7818 	rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
7819 	rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
7820 	rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
7821 	rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
7822 	rfcsr = 0x2d;
7823 	if (tx0_ext_pa)
7824 		rt2x00_set_field8(&rfcsr, RFCSR50_TX0_EXT_PA, 1);
7825 	if (tx1_ext_pa)
7826 		rt2x00_set_field8(&rfcsr, RFCSR50_TX1_EXT_PA, 1);
7827 	rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
7828 	rt2800_rfcsr_write(rt2x00dev, 51, (tx0_ext_pa ? 0x52 : 0x7f));
7829 	rt2800_rfcsr_write(rt2x00dev, 52, (tx0_ext_pa ? 0xc0 : 0x00));
7830 	rt2800_rfcsr_write(rt2x00dev, 53, (tx0_ext_pa ? 0xd2 : 0x52));
7831 	rt2800_rfcsr_write(rt2x00dev, 54, (tx0_ext_pa ? 0xc0 : 0x1b));
7832 	rt2800_rfcsr_write(rt2x00dev, 55, (tx1_ext_pa ? 0x52 : 0x7f));
7833 	rt2800_rfcsr_write(rt2x00dev, 56, (tx1_ext_pa ? 0xc0 : 0x00));
7834 	rt2800_rfcsr_write(rt2x00dev, 57, (tx0_ext_pa ? 0x49 : 0x52));
7835 	rt2800_rfcsr_write(rt2x00dev, 58, (tx1_ext_pa ? 0xc0 : 0x1b));
7836 	rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
7837 	rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
7838 	rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
7839 	rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
7840 	rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
7841 
7842 	rt2800_rx_filter_calibration(rt2x00dev);
7843 	rt2800_led_open_drain_enable(rt2x00dev);
7844 	rt2800_normal_mode_setup_3xxx(rt2x00dev);
7845 }
7846 
rt2800_init_rfcsr_3390(struct rt2x00_dev * rt2x00dev)7847 static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev)
7848 {
7849 	u32 reg;
7850 
7851 	rt2800_rf_init_calibration(rt2x00dev, 30);
7852 
7853 	rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
7854 	rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
7855 	rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
7856 	rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
7857 	rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
7858 	rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
7859 	rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
7860 	rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
7861 	rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
7862 	rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
7863 	rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
7864 	rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
7865 	rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
7866 	rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
7867 	rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
7868 	rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
7869 	rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
7870 	rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
7871 	rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
7872 	rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
7873 	rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
7874 	rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
7875 	rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7876 	rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
7877 	rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
7878 	rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
7879 	rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
7880 	rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
7881 	rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
7882 	rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
7883 	rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
7884 	rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
7885 
7886 	reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
7887 	rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
7888 	rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
7889 
7890 	rt2800_rx_filter_calibration(rt2x00dev);
7891 
7892 	if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
7893 		rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
7894 
7895 	rt2800_led_open_drain_enable(rt2x00dev);
7896 	rt2800_normal_mode_setup_3xxx(rt2x00dev);
7897 }
7898 
rt2800_init_rfcsr_3572(struct rt2x00_dev * rt2x00dev)7899 static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
7900 {
7901 	u8 rfcsr;
7902 	u32 reg;
7903 
7904 	rt2800_rf_init_calibration(rt2x00dev, 30);
7905 
7906 	rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
7907 	rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
7908 	rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
7909 	rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
7910 	rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
7911 	rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
7912 	rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
7913 	rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
7914 	rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
7915 	rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
7916 	rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
7917 	rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
7918 	rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
7919 	rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
7920 	rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
7921 	rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
7922 	rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
7923 	rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
7924 	rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
7925 	rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
7926 	rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
7927 	rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7928 	rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
7929 	rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
7930 	rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
7931 	rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
7932 	rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
7933 	rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
7934 	rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
7935 	rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
7936 	rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
7937 
7938 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
7939 	rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
7940 	rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
7941 
7942 	reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7943 	rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
7944 	rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
7945 	rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7946 	msleep(1);
7947 	reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7948 	rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
7949 	rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
7950 	rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7951 
7952 	rt2800_rx_filter_calibration(rt2x00dev);
7953 	rt2800_led_open_drain_enable(rt2x00dev);
7954 	rt2800_normal_mode_setup_3xxx(rt2x00dev);
7955 }
7956 
rt3593_post_bbp_init(struct rt2x00_dev * rt2x00dev)7957 static void rt3593_post_bbp_init(struct rt2x00_dev *rt2x00dev)
7958 {
7959 	u8 bbp;
7960 	bool txbf_enabled = false; /* FIXME */
7961 
7962 	bbp = rt2800_bbp_read(rt2x00dev, 105);
7963 	if (rt2x00dev->default_ant.rx_chain_num == 1)
7964 		rt2x00_set_field8(&bbp, BBP105_MLD, 0);
7965 	else
7966 		rt2x00_set_field8(&bbp, BBP105_MLD, 1);
7967 	rt2800_bbp_write(rt2x00dev, 105, bbp);
7968 
7969 	rt2800_bbp4_mac_if_ctrl(rt2x00dev);
7970 
7971 	rt2800_bbp_write(rt2x00dev, 92, 0x02);
7972 	rt2800_bbp_write(rt2x00dev, 82, 0x82);
7973 	rt2800_bbp_write(rt2x00dev, 106, 0x05);
7974 	rt2800_bbp_write(rt2x00dev, 104, 0x92);
7975 	rt2800_bbp_write(rt2x00dev, 88, 0x90);
7976 	rt2800_bbp_write(rt2x00dev, 148, 0xc8);
7977 	rt2800_bbp_write(rt2x00dev, 47, 0x48);
7978 	rt2800_bbp_write(rt2x00dev, 120, 0x50);
7979 
7980 	if (txbf_enabled)
7981 		rt2800_bbp_write(rt2x00dev, 163, 0xbd);
7982 	else
7983 		rt2800_bbp_write(rt2x00dev, 163, 0x9d);
7984 
7985 	/* SNR mapping */
7986 	rt2800_bbp_write(rt2x00dev, 142, 6);
7987 	rt2800_bbp_write(rt2x00dev, 143, 160);
7988 	rt2800_bbp_write(rt2x00dev, 142, 7);
7989 	rt2800_bbp_write(rt2x00dev, 143, 161);
7990 	rt2800_bbp_write(rt2x00dev, 142, 8);
7991 	rt2800_bbp_write(rt2x00dev, 143, 162);
7992 
7993 	/* ADC/DAC control */
7994 	rt2800_bbp_write(rt2x00dev, 31, 0x08);
7995 
7996 	/* RX AGC energy lower bound in log2 */
7997 	rt2800_bbp_write(rt2x00dev, 68, 0x0b);
7998 
7999 	/* FIXME: BBP 105 owerwrite? */
8000 	rt2800_bbp_write(rt2x00dev, 105, 0x04);
8001 
8002 }
8003 
rt2800_init_rfcsr_3593(struct rt2x00_dev * rt2x00dev)8004 static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev)
8005 {
8006 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
8007 	u32 reg;
8008 	u8 rfcsr;
8009 
8010 	/* Disable GPIO #4 and #7 function for LAN PE control */
8011 	reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
8012 	rt2x00_set_field32(&reg, GPIO_SWITCH_4, 0);
8013 	rt2x00_set_field32(&reg, GPIO_SWITCH_7, 0);
8014 	rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
8015 
8016 	/* Initialize default register values */
8017 	rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
8018 	rt2800_rfcsr_write(rt2x00dev, 3, 0x80);
8019 	rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
8020 	rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
8021 	rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
8022 	rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
8023 	rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
8024 	rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
8025 	rt2800_rfcsr_write(rt2x00dev, 12, 0x4e);
8026 	rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
8027 	rt2800_rfcsr_write(rt2x00dev, 18, 0x40);
8028 	rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
8029 	rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
8030 	rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
8031 	rt2800_rfcsr_write(rt2x00dev, 32, 0x78);
8032 	rt2800_rfcsr_write(rt2x00dev, 33, 0x3b);
8033 	rt2800_rfcsr_write(rt2x00dev, 34, 0x3c);
8034 	rt2800_rfcsr_write(rt2x00dev, 35, 0xe0);
8035 	rt2800_rfcsr_write(rt2x00dev, 38, 0x86);
8036 	rt2800_rfcsr_write(rt2x00dev, 39, 0x23);
8037 	rt2800_rfcsr_write(rt2x00dev, 44, 0xd3);
8038 	rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
8039 	rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
8040 	rt2800_rfcsr_write(rt2x00dev, 49, 0x8e);
8041 	rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
8042 	rt2800_rfcsr_write(rt2x00dev, 51, 0x75);
8043 	rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
8044 	rt2800_rfcsr_write(rt2x00dev, 53, 0x18);
8045 	rt2800_rfcsr_write(rt2x00dev, 54, 0x18);
8046 	rt2800_rfcsr_write(rt2x00dev, 55, 0x18);
8047 	rt2800_rfcsr_write(rt2x00dev, 56, 0xdb);
8048 	rt2800_rfcsr_write(rt2x00dev, 57, 0x6e);
8049 
8050 	/* Initiate calibration */
8051 	/* TODO: use rt2800_rf_init_calibration ? */
8052 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 2);
8053 	rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
8054 	rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
8055 
8056 	rt2800_freq_cal_mode1(rt2x00dev);
8057 
8058 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 18);
8059 	rt2x00_set_field8(&rfcsr, RFCSR18_XO_TUNE_BYPASS, 1);
8060 	rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
8061 
8062 	reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
8063 	rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
8064 	rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
8065 	rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
8066 	usleep_range(1000, 1500);
8067 	reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
8068 	rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
8069 	rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
8070 
8071 	/* Set initial values for RX filter calibration */
8072 	drv_data->calibration_bw20 = 0x1f;
8073 	drv_data->calibration_bw40 = 0x2f;
8074 
8075 	/* Save BBP 25 & 26 values for later use in channel switching */
8076 	drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25);
8077 	drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26);
8078 
8079 	rt2800_led_open_drain_enable(rt2x00dev);
8080 	rt2800_normal_mode_setup_3593(rt2x00dev);
8081 
8082 	rt3593_post_bbp_init(rt2x00dev);
8083 
8084 	/* TODO: enable stream mode support */
8085 }
8086 
rt2800_init_rfcsr_5350(struct rt2x00_dev * rt2x00dev)8087 static void rt2800_init_rfcsr_5350(struct rt2x00_dev *rt2x00dev)
8088 {
8089 	rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
8090 	rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
8091 	rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
8092 	rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
8093 	rt2800_rfcsr_write(rt2x00dev, 4, 0x49);
8094 	rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
8095 	rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
8096 	rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8097 	rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
8098 	rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
8099 	rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
8100 	rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
8101 	rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
8102 	if (rt2800_clk_is_20mhz(rt2x00dev))
8103 		rt2800_rfcsr_write(rt2x00dev, 13, 0x1f);
8104 	else
8105 		rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
8106 	rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
8107 	rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
8108 	rt2800_rfcsr_write(rt2x00dev, 16, 0xc0);
8109 	rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
8110 	rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
8111 	rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
8112 	rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
8113 	rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
8114 	rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
8115 	rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
8116 	rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
8117 	rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
8118 	rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
8119 	rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8120 	rt2800_rfcsr_write(rt2x00dev, 29, 0xd0);
8121 	rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
8122 	rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
8123 	rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
8124 	rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
8125 	rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
8126 	rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
8127 	rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
8128 	rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
8129 	rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
8130 	rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
8131 	rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
8132 	rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
8133 	rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
8134 	rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
8135 	rt2800_rfcsr_write(rt2x00dev, 44, 0x0c);
8136 	rt2800_rfcsr_write(rt2x00dev, 45, 0xa6);
8137 	rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
8138 	rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
8139 	rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
8140 	rt2800_rfcsr_write(rt2x00dev, 49, 0x80);
8141 	rt2800_rfcsr_write(rt2x00dev, 50, 0x00);
8142 	rt2800_rfcsr_write(rt2x00dev, 51, 0x00);
8143 	rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
8144 	rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
8145 	rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
8146 	rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
8147 	rt2800_rfcsr_write(rt2x00dev, 56, 0x82);
8148 	rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
8149 	rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
8150 	rt2800_rfcsr_write(rt2x00dev, 59, 0x0b);
8151 	rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
8152 	rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
8153 	rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
8154 	rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
8155 }
8156 
rt2800_init_rfcsr_3883(struct rt2x00_dev * rt2x00dev)8157 static void rt2800_init_rfcsr_3883(struct rt2x00_dev *rt2x00dev)
8158 {
8159 	u8 rfcsr;
8160 
8161 	/* TODO: get the actual ECO value from the SoC */
8162 	const unsigned int eco = 5;
8163 
8164 	rt2800_rf_init_calibration(rt2x00dev, 2);
8165 
8166 	rt2800_rfcsr_write(rt2x00dev, 0, 0xe0);
8167 	rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
8168 	rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
8169 	rt2800_rfcsr_write(rt2x00dev, 3, 0x20);
8170 	rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
8171 	rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
8172 	rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
8173 	rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8174 	rt2800_rfcsr_write(rt2x00dev, 8, 0x5b);
8175 	rt2800_rfcsr_write(rt2x00dev, 9, 0x08);
8176 	rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
8177 	rt2800_rfcsr_write(rt2x00dev, 11, 0x48);
8178 	rt2800_rfcsr_write(rt2x00dev, 12, 0x1a);
8179 	rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
8180 	rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
8181 	rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
8182 	rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
8183 
8184 	/* RFCSR 17 will be initialized later based on the
8185 	 * frequency offset stored in the EEPROM
8186 	 */
8187 
8188 	rt2800_rfcsr_write(rt2x00dev, 18, 0x40);
8189 	rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
8190 	rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
8191 	rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
8192 	rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
8193 	rt2800_rfcsr_write(rt2x00dev, 23, 0xc0);
8194 	rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
8195 	rt2800_rfcsr_write(rt2x00dev, 25, 0x00);
8196 	rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
8197 	rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
8198 	rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8199 	rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
8200 	rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
8201 	rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
8202 	rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
8203 	rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
8204 	rt2800_rfcsr_write(rt2x00dev, 34, 0x20);
8205 	rt2800_rfcsr_write(rt2x00dev, 35, 0x00);
8206 	rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
8207 	rt2800_rfcsr_write(rt2x00dev, 37, 0x00);
8208 	rt2800_rfcsr_write(rt2x00dev, 38, 0x86);
8209 	rt2800_rfcsr_write(rt2x00dev, 39, 0x23);
8210 	rt2800_rfcsr_write(rt2x00dev, 40, 0x00);
8211 	rt2800_rfcsr_write(rt2x00dev, 41, 0x00);
8212 	rt2800_rfcsr_write(rt2x00dev, 42, 0x00);
8213 	rt2800_rfcsr_write(rt2x00dev, 43, 0x00);
8214 	rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
8215 	rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
8216 	rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
8217 	rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
8218 	rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
8219 	rt2800_rfcsr_write(rt2x00dev, 49, 0x8e);
8220 	rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
8221 	rt2800_rfcsr_write(rt2x00dev, 51, 0x51);
8222 	rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
8223 	rt2800_rfcsr_write(rt2x00dev, 53, 0x76);
8224 	rt2800_rfcsr_write(rt2x00dev, 54, 0x76);
8225 	rt2800_rfcsr_write(rt2x00dev, 55, 0x76);
8226 	rt2800_rfcsr_write(rt2x00dev, 56, 0xdb);
8227 	rt2800_rfcsr_write(rt2x00dev, 57, 0x3e);
8228 	rt2800_rfcsr_write(rt2x00dev, 58, 0x00);
8229 	rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
8230 	rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
8231 	rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
8232 	rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
8233 	rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
8234 
8235 	/* TODO: rx filter calibration? */
8236 
8237 	rt2800_bbp_write(rt2x00dev, 137, 0x0f);
8238 
8239 	rt2800_bbp_write(rt2x00dev, 163, 0x9d);
8240 
8241 	rt2800_bbp_write(rt2x00dev, 105, 0x05);
8242 
8243 	rt2800_bbp_write(rt2x00dev, 179, 0x02);
8244 	rt2800_bbp_write(rt2x00dev, 180, 0x00);
8245 	rt2800_bbp_write(rt2x00dev, 182, 0x40);
8246 	rt2800_bbp_write(rt2x00dev, 180, 0x01);
8247 	rt2800_bbp_write(rt2x00dev, 182, 0x9c);
8248 
8249 	rt2800_bbp_write(rt2x00dev, 179, 0x00);
8250 
8251 	rt2800_bbp_write(rt2x00dev, 142, 0x04);
8252 	rt2800_bbp_write(rt2x00dev, 143, 0x3b);
8253 	rt2800_bbp_write(rt2x00dev, 142, 0x06);
8254 	rt2800_bbp_write(rt2x00dev, 143, 0xa0);
8255 	rt2800_bbp_write(rt2x00dev, 142, 0x07);
8256 	rt2800_bbp_write(rt2x00dev, 143, 0xa1);
8257 	rt2800_bbp_write(rt2x00dev, 142, 0x08);
8258 	rt2800_bbp_write(rt2x00dev, 143, 0xa2);
8259 	rt2800_bbp_write(rt2x00dev, 148, 0xc8);
8260 
8261 	if (eco == 5) {
8262 		rt2800_rfcsr_write(rt2x00dev, 32, 0xd8);
8263 		rt2800_rfcsr_write(rt2x00dev, 33, 0x32);
8264 	}
8265 
8266 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 2);
8267 	rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_BP, 0);
8268 	rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
8269 	rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
8270 	msleep(1);
8271 	rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
8272 	rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
8273 
8274 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
8275 	rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
8276 	rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
8277 
8278 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
8279 	rfcsr |= 0xc0;
8280 	rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
8281 
8282 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
8283 	rfcsr |= 0x20;
8284 	rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
8285 
8286 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 46);
8287 	rfcsr |= 0x20;
8288 	rt2800_rfcsr_write(rt2x00dev, 46, rfcsr);
8289 
8290 	rfcsr = rt2800_rfcsr_read(rt2x00dev, 20);
8291 	rfcsr &= ~0xee;
8292 	rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
8293 }
8294 
rt2800_init_rfcsr_5390(struct rt2x00_dev * rt2x00dev)8295 static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
8296 {
8297 	rt2800_rf_init_calibration(rt2x00dev, 2);
8298 
8299 	rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
8300 	rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
8301 	rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
8302 	rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
8303 	if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
8304 		rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
8305 	else
8306 		rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
8307 	rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8308 	rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
8309 	rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
8310 	rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
8311 	rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
8312 	rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
8313 	rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
8314 	rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
8315 	rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
8316 	rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
8317 
8318 	rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
8319 	rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
8320 	rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
8321 	rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
8322 	rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
8323 	if (rt2x00_is_usb(rt2x00dev) &&
8324 	    rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
8325 		rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
8326 	else
8327 		rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
8328 	rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
8329 	rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
8330 	rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8331 	rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
8332 
8333 	rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
8334 	rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
8335 	rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
8336 	rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
8337 	rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
8338 	rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
8339 	rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
8340 	rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
8341 	rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
8342 	rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
8343 
8344 	rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
8345 	rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
8346 	rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
8347 	rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
8348 	rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
8349 	rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
8350 	if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
8351 		rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
8352 	else
8353 		rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
8354 	rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
8355 	rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
8356 	rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
8357 
8358 	rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
8359 	if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
8360 		rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
8361 	else
8362 		rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
8363 	rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
8364 	rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
8365 	if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
8366 		rt2800_rfcsr_write(rt2x00dev, 56, 0x42);
8367 	else
8368 		rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
8369 	rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
8370 	rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
8371 	rt2800_rfcsr_write(rt2x00dev, 59, 0x8f);
8372 
8373 	rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
8374 	if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
8375 		if (rt2x00_is_usb(rt2x00dev))
8376 			rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
8377 		else
8378 			rt2800_rfcsr_write(rt2x00dev, 61, 0xd5);
8379 	} else {
8380 		if (rt2x00_is_usb(rt2x00dev))
8381 			rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
8382 		else
8383 			rt2800_rfcsr_write(rt2x00dev, 61, 0xb5);
8384 	}
8385 	rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
8386 	rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
8387 
8388 	rt2800_normal_mode_setup_5xxx(rt2x00dev);
8389 
8390 	rt2800_led_open_drain_enable(rt2x00dev);
8391 }
8392 
rt2800_init_rfcsr_5392(struct rt2x00_dev * rt2x00dev)8393 static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev)
8394 {
8395 	rt2800_rf_init_calibration(rt2x00dev, 2);
8396 
8397 	rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
8398 	rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
8399 	rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
8400 	rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
8401 	rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8402 	rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
8403 	rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
8404 	rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
8405 	rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
8406 	rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
8407 	rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
8408 	rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
8409 	rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
8410 	rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
8411 	rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
8412 	rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
8413 	rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
8414 	rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
8415 	rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
8416 	rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
8417 	rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
8418 	rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
8419 	rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8420 	rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
8421 	rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
8422 	rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
8423 	rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
8424 	rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
8425 	rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
8426 	rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
8427 	rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
8428 	rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
8429 	rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
8430 	rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
8431 	rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
8432 	rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
8433 	rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
8434 	rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
8435 	rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
8436 	rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
8437 	rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
8438 	rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
8439 	rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
8440 	rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
8441 	rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
8442 	rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
8443 	rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
8444 	rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
8445 	rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
8446 	rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
8447 	rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
8448 	rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
8449 	rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
8450 	rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
8451 	rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
8452 	rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
8453 	rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
8454 	rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
8455 
8456 	rt2800_normal_mode_setup_5xxx(rt2x00dev);
8457 
8458 	rt2800_led_open_drain_enable(rt2x00dev);
8459 }
8460 
rt2800_init_rfcsr_5592(struct rt2x00_dev * rt2x00dev)8461 static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev)
8462 {
8463 	rt2800_rf_init_calibration(rt2x00dev, 30);
8464 
8465 	rt2800_rfcsr_write(rt2x00dev, 1, 0x3F);
8466 	rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
8467 	rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
8468 	rt2800_rfcsr_write(rt2x00dev, 6, 0xE4);
8469 	rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8470 	rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
8471 	rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
8472 	rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
8473 	rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
8474 	rt2800_rfcsr_write(rt2x00dev, 19, 0x4D);
8475 	rt2800_rfcsr_write(rt2x00dev, 20, 0x10);
8476 	rt2800_rfcsr_write(rt2x00dev, 21, 0x8D);
8477 	rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
8478 	rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8479 	rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
8480 	rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
8481 	rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
8482 	rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
8483 	rt2800_rfcsr_write(rt2x00dev, 47, 0x0C);
8484 	rt2800_rfcsr_write(rt2x00dev, 53, 0x22);
8485 	rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
8486 
8487 	rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
8488 	msleep(1);
8489 
8490 	rt2800_freq_cal_mode1(rt2x00dev);
8491 
8492 	/* Enable DC filter */
8493 	if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
8494 		rt2800_bbp_write(rt2x00dev, 103, 0xc0);
8495 
8496 	rt2800_normal_mode_setup_5xxx(rt2x00dev);
8497 
8498 	if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C))
8499 		rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
8500 
8501 	rt2800_led_open_drain_enable(rt2x00dev);
8502 }
8503 
rt2800_rf_self_txdc_cal(struct rt2x00_dev * rt2x00dev)8504 static void rt2800_rf_self_txdc_cal(struct rt2x00_dev *rt2x00dev)
8505 {
8506 	u8 rfb5r1_org, rfb7r1_org, rfvalue;
8507 	u32 mac0518, mac051c, mac0528, mac052c;
8508 	u8 i;
8509 
8510 	mac0518 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
8511 	mac051c = rt2800_register_read(rt2x00dev, RF_BYPASS0);
8512 	mac0528 = rt2800_register_read(rt2x00dev, RF_CONTROL2);
8513 	mac052c = rt2800_register_read(rt2x00dev, RF_BYPASS2);
8514 
8515 	rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x0);
8516 	rt2800_register_write(rt2x00dev, RF_BYPASS2, 0x0);
8517 
8518 	rt2800_register_write(rt2x00dev, RF_CONTROL0, 0xC);
8519 	rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x3306);
8520 	rt2800_register_write(rt2x00dev, RF_CONTROL2, 0x3330);
8521 	rt2800_register_write(rt2x00dev, RF_BYPASS2, 0xfffff);
8522 	rfb5r1_org = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
8523 	rfb7r1_org = rt2800_rfcsr_read_bank(rt2x00dev, 7, 1);
8524 
8525 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, 0x4);
8526 	for (i = 0; i < 100; ++i) {
8527 		usleep_range(50, 100);
8528 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
8529 		if ((rfvalue & 0x04) != 0x4)
8530 			break;
8531 	}
8532 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, rfb5r1_org);
8533 
8534 	rt2800_rfcsr_write_bank(rt2x00dev, 7, 1, 0x4);
8535 	for (i = 0; i < 100; ++i) {
8536 		usleep_range(50, 100);
8537 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 1);
8538 		if ((rfvalue & 0x04) != 0x4)
8539 			break;
8540 	}
8541 	rt2800_rfcsr_write_bank(rt2x00dev, 7, 1, rfb7r1_org);
8542 
8543 	rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x0);
8544 	rt2800_register_write(rt2x00dev, RF_BYPASS2, 0x0);
8545 	rt2800_register_write(rt2x00dev, RF_CONTROL0, mac0518);
8546 	rt2800_register_write(rt2x00dev, RF_BYPASS0, mac051c);
8547 	rt2800_register_write(rt2x00dev, RF_CONTROL2, mac0528);
8548 	rt2800_register_write(rt2x00dev, RF_BYPASS2, mac052c);
8549 }
8550 
rt2800_calcrcalibrationcode(struct rt2x00_dev * rt2x00dev,int d1,int d2)8551 static int rt2800_calcrcalibrationcode(struct rt2x00_dev *rt2x00dev, int d1, int d2)
8552 {
8553 	int calcode = ((d2 - d1) * 1000) / 43;
8554 
8555 	if ((calcode % 10) >= 5)
8556 		calcode += 10;
8557 	calcode = (calcode / 10);
8558 
8559 	return calcode;
8560 }
8561 
rt2800_r_calibration(struct rt2x00_dev * rt2x00dev)8562 static void rt2800_r_calibration(struct rt2x00_dev *rt2x00dev)
8563 {
8564 	u32 savemacsysctrl;
8565 	u8 saverfb0r1, saverfb0r34, saverfb0r35;
8566 	u8 saverfb5r4, saverfb5r17, saverfb5r18;
8567 	u8 saverfb5r19, saverfb5r20;
8568 	u8 savebbpr22, savebbpr47, savebbpr49;
8569 	u8 bytevalue = 0;
8570 	int rcalcode;
8571 	u8 r_cal_code = 0;
8572 	s8 d1 = 0, d2 = 0;
8573 	u8 rfvalue;
8574 	u32 MAC_RF_BYPASS0, MAC_RF_CONTROL0, MAC_PWR_PIN_CFG;
8575 	u32 maccfg;
8576 
8577 	saverfb0r1 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1);
8578 	saverfb0r34 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 34);
8579 	saverfb0r35 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 35);
8580 	saverfb5r4 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
8581 	saverfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
8582 	saverfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18);
8583 	saverfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19);
8584 	saverfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20);
8585 
8586 	savebbpr22 = rt2800_bbp_read(rt2x00dev, 22);
8587 	savebbpr47 = rt2800_bbp_read(rt2x00dev, 47);
8588 	savebbpr49 = rt2800_bbp_read(rt2x00dev, 49);
8589 
8590 	savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
8591 	MAC_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
8592 	MAC_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
8593 	MAC_PWR_PIN_CFG = rt2800_register_read(rt2x00dev, PWR_PIN_CFG);
8594 
8595 	maccfg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
8596 	maccfg &= (~0x04);
8597 	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, maccfg);
8598 
8599 	if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_TX)))
8600 		rt2x00_warn(rt2x00dev, "Wait MAC Tx Status to MAX !!!\n");
8601 
8602 	maccfg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
8603 	maccfg &= (~0x08);
8604 	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, maccfg);
8605 
8606 	if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_RX)))
8607 		rt2x00_warn(rt2x00dev, "Wait MAC Rx Status to MAX !!!\n");
8608 
8609 	rfvalue = (MAC_RF_BYPASS0 | 0x3004);
8610 	rt2800_register_write(rt2x00dev, RF_BYPASS0, rfvalue);
8611 	rfvalue = (MAC_RF_CONTROL0 | (~0x3002));
8612 	rt2800_register_write(rt2x00dev, RF_CONTROL0, rfvalue);
8613 
8614 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, 0x27);
8615 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, 0x80);
8616 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0x83);
8617 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x00);
8618 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x20);
8619 
8620 	rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, 0x00);
8621 	rt2800_rfcsr_write_bank(rt2x00dev, 0, 34, 0x13);
8622 	rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x00);
8623 
8624 	rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x1);
8625 
8626 	rt2800_bbp_write(rt2x00dev, 47, 0x04);
8627 	rt2800_bbp_write(rt2x00dev, 22, 0x80);
8628 	usleep_range(100, 200);
8629 	bytevalue = rt2800_bbp_read(rt2x00dev, 49);
8630 	if (bytevalue > 128)
8631 		d1 = bytevalue - 256;
8632 	else
8633 		d1 = (s8)bytevalue;
8634 	rt2800_bbp_write(rt2x00dev, 22, 0x0);
8635 	rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x01);
8636 
8637 	rt2800_bbp_write(rt2x00dev, 22, 0x80);
8638 	usleep_range(100, 200);
8639 	bytevalue = rt2800_bbp_read(rt2x00dev, 49);
8640 	if (bytevalue > 128)
8641 		d2 = bytevalue - 256;
8642 	else
8643 		d2 = (s8)bytevalue;
8644 	rt2800_bbp_write(rt2x00dev, 22, 0x0);
8645 
8646 	rcalcode = rt2800_calcrcalibrationcode(rt2x00dev, d1, d2);
8647 	if (rcalcode < 0)
8648 		r_cal_code = 256 + rcalcode;
8649 	else
8650 		r_cal_code = (u8)rcalcode;
8651 
8652 	rt2800_rfcsr_write_bank(rt2x00dev, 0, 7, r_cal_code);
8653 
8654 	rt2800_bbp_write(rt2x00dev, 22, 0x0);
8655 
8656 	bytevalue = rt2800_bbp_read(rt2x00dev, 21);
8657 	bytevalue |= 0x1;
8658 	rt2800_bbp_write(rt2x00dev, 21, bytevalue);
8659 	bytevalue = rt2800_bbp_read(rt2x00dev, 21);
8660 	bytevalue &= (~0x1);
8661 	rt2800_bbp_write(rt2x00dev, 21, bytevalue);
8662 
8663 	rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, saverfb0r1);
8664 	rt2800_rfcsr_write_bank(rt2x00dev, 0, 34, saverfb0r34);
8665 	rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, saverfb0r35);
8666 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r4);
8667 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, saverfb5r17);
8668 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, saverfb5r18);
8669 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, saverfb5r19);
8670 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, saverfb5r20);
8671 
8672 	rt2800_bbp_write(rt2x00dev, 22, savebbpr22);
8673 	rt2800_bbp_write(rt2x00dev, 47, savebbpr47);
8674 	rt2800_bbp_write(rt2x00dev, 49, savebbpr49);
8675 
8676 	rt2800_register_write(rt2x00dev, RF_BYPASS0, MAC_RF_BYPASS0);
8677 	rt2800_register_write(rt2x00dev, RF_CONTROL0, MAC_RF_CONTROL0);
8678 
8679 	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl);
8680 	rt2800_register_write(rt2x00dev, PWR_PIN_CFG, MAC_PWR_PIN_CFG);
8681 }
8682 
rt2800_rxdcoc_calibration(struct rt2x00_dev * rt2x00dev)8683 static void rt2800_rxdcoc_calibration(struct rt2x00_dev *rt2x00dev)
8684 {
8685 	u8 bbpreg = 0;
8686 	u32 macvalue = 0;
8687 	u8 saverfb0r2, saverfb5r4, saverfb7r4, rfvalue;
8688 	int i;
8689 
8690 	saverfb0r2 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2);
8691 	rfvalue = saverfb0r2;
8692 	rfvalue |= 0x03;
8693 	rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfvalue);
8694 
8695 	rt2800_bbp_write(rt2x00dev, 158, 141);
8696 	bbpreg = rt2800_bbp_read(rt2x00dev, 159);
8697 	bbpreg |= 0x10;
8698 	rt2800_bbp_write(rt2x00dev, 159, bbpreg);
8699 
8700 	macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
8701 	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x8);
8702 
8703 	if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_TX)))
8704 		rt2x00_warn(rt2x00dev, "RF TX busy in RX RXDCOC calibration\n");
8705 
8706 	saverfb5r4 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
8707 	saverfb7r4 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 4);
8708 	saverfb5r4 = saverfb5r4 & (~0x40);
8709 	saverfb7r4 = saverfb7r4 & (~0x40);
8710 	rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x64);
8711 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r4);
8712 	rt2800_rfcsr_write_bank(rt2x00dev, 7, 4, saverfb7r4);
8713 
8714 	rt2800_bbp_write(rt2x00dev, 158, 140);
8715 	bbpreg = rt2800_bbp_read(rt2x00dev, 159);
8716 	bbpreg = bbpreg & (~0x40);
8717 	rt2800_bbp_write(rt2x00dev, 159, bbpreg);
8718 	bbpreg |= 0x48;
8719 	rt2800_bbp_write(rt2x00dev, 159, bbpreg);
8720 
8721 	for (i = 0; i < 10000; i++) {
8722 		bbpreg = rt2800_bbp_read(rt2x00dev, 159);
8723 		if ((bbpreg & 0x40) == 0)
8724 			break;
8725 		usleep_range(50, 100);
8726 	}
8727 
8728 	bbpreg = rt2800_bbp_read(rt2x00dev, 159);
8729 	bbpreg = bbpreg & (~0x40);
8730 	rt2800_bbp_write(rt2x00dev, 159, bbpreg);
8731 
8732 	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
8733 
8734 	rt2800_bbp_write(rt2x00dev, 158, 141);
8735 	bbpreg = rt2800_bbp_read(rt2x00dev, 159);
8736 	bbpreg &= (~0x10);
8737 	rt2800_bbp_write(rt2x00dev, 159, bbpreg);
8738 
8739 	rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, saverfb0r2);
8740 }
8741 
rt2800_do_sqrt_accumulation(u32 si)8742 static u32 rt2800_do_sqrt_accumulation(u32 si)
8743 {
8744 	u32 root, root_pre, bit;
8745 	s8 i;
8746 
8747 	bit = 1 << 15;
8748 	root = 0;
8749 	for (i = 15; i >= 0; i = i - 1) {
8750 		root_pre = root + bit;
8751 		if ((root_pre * root_pre) <= si)
8752 			root = root_pre;
8753 		bit = bit >> 1;
8754 	}
8755 
8756 	return root;
8757 }
8758 
rt2800_rxiq_calibration(struct rt2x00_dev * rt2x00dev)8759 static void rt2800_rxiq_calibration(struct rt2x00_dev *rt2x00dev)
8760 {
8761 	u8 rfb0r1, rfb0r2, rfb0r42;
8762 	u8 rfb4r0, rfb4r19;
8763 	u8 rfb5r3, rfb5r4, rfb5r17, rfb5r18, rfb5r19, rfb5r20;
8764 	u8 rfb6r0, rfb6r19;
8765 	u8 rfb7r3, rfb7r4, rfb7r17, rfb7r18, rfb7r19, rfb7r20;
8766 
8767 	u8 bbp1, bbp4;
8768 	u8 bbpr241, bbpr242;
8769 	u32 i;
8770 	u8 ch_idx;
8771 	u8 bbpval;
8772 	u8 rfval, vga_idx = 0;
8773 	int mi = 0, mq = 0, si = 0, sq = 0, riq = 0;
8774 	int sigma_i, sigma_q, r_iq, g_rx;
8775 	int g_imb;
8776 	int ph_rx;
8777 	u32 savemacsysctrl = 0;
8778 	u32 orig_RF_CONTROL0 = 0;
8779 	u32 orig_RF_BYPASS0 = 0;
8780 	u32 orig_RF_CONTROL1 = 0;
8781 	u32 orig_RF_BYPASS1 = 0;
8782 	u32 orig_RF_CONTROL3 = 0;
8783 	u32 orig_RF_BYPASS3 = 0;
8784 	u32 bbpval1 = 0;
8785 	static const u8 rf_vga_table[] = {0x20, 0x21, 0x22, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f};
8786 
8787 	savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
8788 	orig_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
8789 	orig_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
8790 	orig_RF_CONTROL1 = rt2800_register_read(rt2x00dev, RF_CONTROL1);
8791 	orig_RF_BYPASS1 = rt2800_register_read(rt2x00dev, RF_BYPASS1);
8792 	orig_RF_CONTROL3 = rt2800_register_read(rt2x00dev, RF_CONTROL3);
8793 	orig_RF_BYPASS3 = rt2800_register_read(rt2x00dev, RF_BYPASS3);
8794 
8795 	bbp1 = rt2800_bbp_read(rt2x00dev, 1);
8796 	bbp4 = rt2800_bbp_read(rt2x00dev, 4);
8797 
8798 	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x0);
8799 
8800 	if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY)))
8801 		rt2x00_warn(rt2x00dev, "Timeout waiting for MAC status in RXIQ calibration\n");
8802 
8803 	bbpval = bbp4 & (~0x18);
8804 	bbpval = bbp4 | 0x00;
8805 	rt2800_bbp_write(rt2x00dev, 4, bbpval);
8806 
8807 	bbpval = rt2800_bbp_read(rt2x00dev, 21);
8808 	bbpval = bbpval | 1;
8809 	rt2800_bbp_write(rt2x00dev, 21, bbpval);
8810 	bbpval = bbpval & 0xfe;
8811 	rt2800_bbp_write(rt2x00dev, 21, bbpval);
8812 
8813 	rt2800_register_write(rt2x00dev, RF_CONTROL1, 0x00000202);
8814 	rt2800_register_write(rt2x00dev, RF_BYPASS1, 0x00000303);
8815 	if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags))
8816 		rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x0101);
8817 	else
8818 		rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x0000);
8819 
8820 	rt2800_register_write(rt2x00dev, RF_BYPASS3, 0xf1f1);
8821 
8822 	rfb0r1 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1);
8823 	rfb0r2 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2);
8824 	rfb0r42 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42);
8825 	rfb4r0 = rt2800_rfcsr_read_bank(rt2x00dev, 4, 0);
8826 	rfb4r19 = rt2800_rfcsr_read_bank(rt2x00dev, 4, 19);
8827 	rfb5r3 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
8828 	rfb5r4 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
8829 	rfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
8830 	rfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18);
8831 	rfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19);
8832 	rfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20);
8833 
8834 	rfb6r0 = rt2800_rfcsr_read_bank(rt2x00dev, 6, 0);
8835 	rfb6r19 = rt2800_rfcsr_read_bank(rt2x00dev, 6, 19);
8836 	rfb7r3 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 3);
8837 	rfb7r4 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 4);
8838 	rfb7r17 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 17);
8839 	rfb7r18 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 18);
8840 	rfb7r19 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 19);
8841 	rfb7r20 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 20);
8842 
8843 	rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x87);
8844 	rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0x27);
8845 	rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x38);
8846 	rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x38);
8847 	rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x80);
8848 	rt2800_rfcsr_write_dccal(rt2x00dev, 18, 0xC1);
8849 	rt2800_rfcsr_write_dccal(rt2x00dev, 19, 0x60);
8850 	rt2800_rfcsr_write_dccal(rt2x00dev, 20, 0x00);
8851 
8852 	rt2800_bbp_write(rt2x00dev, 23, 0x0);
8853 	rt2800_bbp_write(rt2x00dev, 24, 0x0);
8854 
8855 	rt2800_bbp_dcoc_write(rt2x00dev, 5, 0x0);
8856 
8857 	bbpr241 = rt2800_bbp_read(rt2x00dev, 241);
8858 	bbpr242 = rt2800_bbp_read(rt2x00dev, 242);
8859 
8860 	rt2800_bbp_write(rt2x00dev, 241, 0x10);
8861 	rt2800_bbp_write(rt2x00dev, 242, 0x84);
8862 	rt2800_bbp_write(rt2x00dev, 244, 0x31);
8863 
8864 	bbpval = rt2800_bbp_dcoc_read(rt2x00dev, 3);
8865 	bbpval = bbpval & (~0x7);
8866 	rt2800_bbp_dcoc_write(rt2x00dev, 3, bbpval);
8867 
8868 	rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004);
8869 	udelay(1);
8870 	rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000006);
8871 	usleep_range(1, 200);
8872 	rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00003376);
8873 	rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001006);
8874 	udelay(1);
8875 	if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
8876 		rt2800_bbp_write(rt2x00dev, 23, 0x06);
8877 		rt2800_bbp_write(rt2x00dev, 24, 0x06);
8878 	} else {
8879 		rt2800_bbp_write(rt2x00dev, 23, 0x02);
8880 		rt2800_bbp_write(rt2x00dev, 24, 0x02);
8881 	}
8882 
8883 	for (ch_idx = 0; ch_idx < 2; ch_idx = ch_idx + 1) {
8884 		if (ch_idx == 0) {
8885 			rfval = rfb0r1 & (~0x3);
8886 			rfval = rfb0r1 | 0x1;
8887 			rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, rfval);
8888 			rfval = rfb0r2 & (~0x33);
8889 			rfval = rfb0r2 | 0x11;
8890 			rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfval);
8891 			rfval = rfb0r42 & (~0x50);
8892 			rfval = rfb0r42 | 0x10;
8893 			rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfval);
8894 
8895 			rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001006);
8896 			udelay(1);
8897 
8898 			bbpval = bbp1 & (~0x18);
8899 			bbpval = bbpval | 0x00;
8900 			rt2800_bbp_write(rt2x00dev, 1, bbpval);
8901 
8902 			rt2800_bbp_dcoc_write(rt2x00dev, 1, 0x00);
8903 		} else {
8904 			rfval = rfb0r1 & (~0x3);
8905 			rfval = rfb0r1 | 0x2;
8906 			rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, rfval);
8907 			rfval = rfb0r2 & (~0x33);
8908 			rfval = rfb0r2 | 0x22;
8909 			rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfval);
8910 			rfval = rfb0r42 & (~0x50);
8911 			rfval = rfb0r42 | 0x40;
8912 			rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfval);
8913 
8914 			rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00002006);
8915 			udelay(1);
8916 
8917 			bbpval = bbp1 & (~0x18);
8918 			bbpval = bbpval | 0x08;
8919 			rt2800_bbp_write(rt2x00dev, 1, bbpval);
8920 
8921 			rt2800_bbp_dcoc_write(rt2x00dev, 1, 0x01);
8922 		}
8923 		usleep_range(500, 1500);
8924 
8925 		vga_idx = 0;
8926 		while (vga_idx < 11) {
8927 			rt2800_rfcsr_write_dccal(rt2x00dev, 3, rf_vga_table[vga_idx]);
8928 			rt2800_rfcsr_write_dccal(rt2x00dev, 4, rf_vga_table[vga_idx]);
8929 
8930 			rt2800_bbp_dcoc_write(rt2x00dev, 0, 0x93);
8931 
8932 			for (i = 0; i < 10000; i++) {
8933 				bbpval = rt2800_bbp_read(rt2x00dev, 159);
8934 				if ((bbpval & 0xff) == 0x93)
8935 					usleep_range(50, 100);
8936 				else
8937 					break;
8938 				}
8939 
8940 			if ((bbpval & 0xff) == 0x93) {
8941 				rt2x00_warn(rt2x00dev, "Fatal Error: Calibration doesn't finish");
8942 				goto restore_value;
8943 			}
8944 			for (i = 0; i < 5; i++) {
8945 				u32 bbptemp = 0;
8946 				u8 value = 0;
8947 				int result = 0;
8948 
8949 				rt2800_bbp_write(rt2x00dev, 158, 0x1e);
8950 				rt2800_bbp_write(rt2x00dev, 159, i);
8951 				rt2800_bbp_write(rt2x00dev, 158, 0x22);
8952 				value = rt2800_bbp_read(rt2x00dev, 159);
8953 				bbptemp = bbptemp + (value << 24);
8954 				rt2800_bbp_write(rt2x00dev, 158, 0x21);
8955 				value = rt2800_bbp_read(rt2x00dev, 159);
8956 				bbptemp = bbptemp + (value << 16);
8957 				rt2800_bbp_write(rt2x00dev, 158, 0x20);
8958 				value = rt2800_bbp_read(rt2x00dev, 159);
8959 				bbptemp = bbptemp + (value << 8);
8960 				rt2800_bbp_write(rt2x00dev, 158, 0x1f);
8961 				value = rt2800_bbp_read(rt2x00dev, 159);
8962 				bbptemp = bbptemp + value;
8963 
8964 				if (i < 2 && (bbptemp & 0x800000))
8965 					result = (bbptemp & 0xffffff) - 0x1000000;
8966 				else
8967 					result = bbptemp;
8968 
8969 				if (i == 0)
8970 					mi = result / 4096;
8971 				else if (i == 1)
8972 					mq = result / 4096;
8973 				else if (i == 2)
8974 					si = bbptemp / 4096;
8975 				else if (i == 3)
8976 					sq = bbptemp / 4096;
8977 				else
8978 					riq = result / 4096;
8979 			}
8980 
8981 			bbpval1 = si - mi * mi;
8982 			rt2x00_dbg(rt2x00dev,
8983 				   "RXIQ si=%d, sq=%d, riq=%d, bbpval %d, vga_idx %d",
8984 				   si, sq, riq, bbpval1, vga_idx);
8985 
8986 			if (bbpval1 >= (100 * 100))
8987 				break;
8988 
8989 			if (bbpval1 <= 100)
8990 				vga_idx = vga_idx + 9;
8991 			else if (bbpval1 <= 158)
8992 				vga_idx = vga_idx + 8;
8993 			else if (bbpval1 <= 251)
8994 				vga_idx = vga_idx + 7;
8995 			else if (bbpval1 <= 398)
8996 				vga_idx = vga_idx + 6;
8997 			else if (bbpval1 <= 630)
8998 				vga_idx = vga_idx + 5;
8999 			else if (bbpval1 <= 1000)
9000 				vga_idx = vga_idx + 4;
9001 			else if (bbpval1 <= 1584)
9002 				vga_idx = vga_idx + 3;
9003 			else if (bbpval1 <= 2511)
9004 				vga_idx = vga_idx + 2;
9005 			else
9006 				vga_idx = vga_idx + 1;
9007 		}
9008 
9009 		sigma_i = rt2800_do_sqrt_accumulation(100 * (si - mi * mi));
9010 		sigma_q = rt2800_do_sqrt_accumulation(100 * (sq - mq * mq));
9011 		r_iq = 10 * (riq - (mi * mq));
9012 
9013 		rt2x00_dbg(rt2x00dev, "Sigma_i=%d, Sigma_q=%d, R_iq=%d", sigma_i, sigma_q, r_iq);
9014 
9015 		if (sigma_i <= 1400 && sigma_i >= 1000 &&
9016 		    (sigma_i - sigma_q) <= 112 &&
9017 		    (sigma_i - sigma_q) >= -112 &&
9018 		    mi <= 32 && mi >= -32 &&
9019 		    mq <= 32 && mq >= -32) {
9020 			r_iq = 10 * (riq - (mi * mq));
9021 			rt2x00_dbg(rt2x00dev, "RXIQ Sigma_i=%d, Sigma_q=%d, R_iq=%d\n",
9022 				   sigma_i, sigma_q, r_iq);
9023 
9024 			g_rx = (1000 * sigma_q) / sigma_i;
9025 			g_imb = ((-2) * 128 * (1000 - g_rx)) / (1000 + g_rx);
9026 			ph_rx = (r_iq * 2292) / (sigma_i * sigma_q);
9027 
9028 			if (ph_rx > 20 || ph_rx < -20) {
9029 				ph_rx = 0;
9030 				rt2x00_warn(rt2x00dev, "RXIQ calibration FAIL");
9031 			}
9032 
9033 			if (g_imb > 12 || g_imb < -12) {
9034 				g_imb = 0;
9035 				rt2x00_warn(rt2x00dev, "RXIQ calibration FAIL");
9036 			}
9037 		} else {
9038 			g_imb = 0;
9039 			ph_rx = 0;
9040 			rt2x00_dbg(rt2x00dev, "RXIQ Sigma_i=%d, Sigma_q=%d, R_iq=%d\n",
9041 				   sigma_i, sigma_q, r_iq);
9042 			rt2x00_warn(rt2x00dev, "RXIQ calibration FAIL");
9043 		}
9044 
9045 		if (ch_idx == 0) {
9046 			rt2800_bbp_write(rt2x00dev, 158, 0x37);
9047 			rt2800_bbp_write(rt2x00dev, 159, g_imb & 0x3f);
9048 			rt2800_bbp_write(rt2x00dev, 158, 0x35);
9049 			rt2800_bbp_write(rt2x00dev, 159, ph_rx & 0x3f);
9050 		} else {
9051 			rt2800_bbp_write(rt2x00dev, 158, 0x55);
9052 			rt2800_bbp_write(rt2x00dev, 159, g_imb & 0x3f);
9053 			rt2800_bbp_write(rt2x00dev, 158, 0x53);
9054 			rt2800_bbp_write(rt2x00dev, 159, ph_rx & 0x3f);
9055 		}
9056 	}
9057 
9058 restore_value:
9059 	rt2800_bbp_write(rt2x00dev, 158, 0x3);
9060 	bbpval = rt2800_bbp_read(rt2x00dev, 159);
9061 	rt2800_bbp_write(rt2x00dev, 159, (bbpval | 0x07));
9062 
9063 	rt2800_bbp_write(rt2x00dev, 158, 0x00);
9064 	rt2800_bbp_write(rt2x00dev, 159, 0x00);
9065 	rt2800_bbp_write(rt2x00dev, 1, bbp1);
9066 	rt2800_bbp_write(rt2x00dev, 4, bbp4);
9067 	rt2800_bbp_write(rt2x00dev, 241, bbpr241);
9068 	rt2800_bbp_write(rt2x00dev, 242, bbpr242);
9069 
9070 	rt2800_bbp_write(rt2x00dev, 244, 0x00);
9071 	bbpval = rt2800_bbp_read(rt2x00dev, 21);
9072 	bbpval |= 0x1;
9073 	rt2800_bbp_write(rt2x00dev, 21, bbpval);
9074 	usleep_range(10, 200);
9075 	bbpval &= 0xfe;
9076 	rt2800_bbp_write(rt2x00dev, 21, bbpval);
9077 
9078 	rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, rfb0r1);
9079 	rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfb0r2);
9080 	rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfb0r42);
9081 
9082 	rt2800_rfcsr_write_bank(rt2x00dev, 4, 0, rfb4r0);
9083 	rt2800_rfcsr_write_bank(rt2x00dev, 4, 19, rfb4r19);
9084 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rfb5r3);
9085 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rfb5r4);
9086 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, rfb5r17);
9087 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, rfb5r18);
9088 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, rfb5r19);
9089 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, rfb5r20);
9090 
9091 	rt2800_rfcsr_write_bank(rt2x00dev, 6, 0, rfb6r0);
9092 	rt2800_rfcsr_write_bank(rt2x00dev, 6, 19, rfb6r19);
9093 	rt2800_rfcsr_write_bank(rt2x00dev, 7, 3, rfb7r3);
9094 	rt2800_rfcsr_write_bank(rt2x00dev, 7, 4, rfb7r4);
9095 	rt2800_rfcsr_write_bank(rt2x00dev, 7, 17, rfb7r17);
9096 	rt2800_rfcsr_write_bank(rt2x00dev, 7, 18, rfb7r18);
9097 	rt2800_rfcsr_write_bank(rt2x00dev, 7, 19, rfb7r19);
9098 	rt2800_rfcsr_write_bank(rt2x00dev, 7, 20, rfb7r20);
9099 
9100 	rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000006);
9101 	udelay(1);
9102 	rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004);
9103 	udelay(1);
9104 	rt2800_register_write(rt2x00dev, RF_CONTROL0, orig_RF_CONTROL0);
9105 	udelay(1);
9106 	rt2800_register_write(rt2x00dev, RF_BYPASS0, orig_RF_BYPASS0);
9107 	rt2800_register_write(rt2x00dev, RF_CONTROL1, orig_RF_CONTROL1);
9108 	rt2800_register_write(rt2x00dev, RF_BYPASS1, orig_RF_BYPASS1);
9109 	rt2800_register_write(rt2x00dev, RF_CONTROL3, orig_RF_CONTROL3);
9110 	rt2800_register_write(rt2x00dev, RF_BYPASS3, orig_RF_BYPASS3);
9111 	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl);
9112 }
9113 
rt2800_rf_configstore(struct rt2x00_dev * rt2x00dev,struct rf_reg_pair rf_reg_record[][13],u8 chain)9114 static void rt2800_rf_configstore(struct rt2x00_dev *rt2x00dev,
9115 				  struct rf_reg_pair rf_reg_record[][13], u8 chain)
9116 {
9117 	u8 rfvalue = 0;
9118 
9119 	if (chain == CHAIN_0) {
9120 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1);
9121 		rf_reg_record[CHAIN_0][0].bank = 0;
9122 		rf_reg_record[CHAIN_0][0].reg = 1;
9123 		rf_reg_record[CHAIN_0][0].value = rfvalue;
9124 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2);
9125 		rf_reg_record[CHAIN_0][1].bank = 0;
9126 		rf_reg_record[CHAIN_0][1].reg = 2;
9127 		rf_reg_record[CHAIN_0][1].value = rfvalue;
9128 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 35);
9129 		rf_reg_record[CHAIN_0][2].bank = 0;
9130 		rf_reg_record[CHAIN_0][2].reg = 35;
9131 		rf_reg_record[CHAIN_0][2].value = rfvalue;
9132 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42);
9133 		rf_reg_record[CHAIN_0][3].bank = 0;
9134 		rf_reg_record[CHAIN_0][3].reg = 42;
9135 		rf_reg_record[CHAIN_0][3].value = rfvalue;
9136 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 4, 0);
9137 		rf_reg_record[CHAIN_0][4].bank = 4;
9138 		rf_reg_record[CHAIN_0][4].reg = 0;
9139 		rf_reg_record[CHAIN_0][4].value = rfvalue;
9140 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 4, 2);
9141 		rf_reg_record[CHAIN_0][5].bank = 4;
9142 		rf_reg_record[CHAIN_0][5].reg = 2;
9143 		rf_reg_record[CHAIN_0][5].value = rfvalue;
9144 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 4, 34);
9145 		rf_reg_record[CHAIN_0][6].bank = 4;
9146 		rf_reg_record[CHAIN_0][6].reg = 34;
9147 		rf_reg_record[CHAIN_0][6].value = rfvalue;
9148 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
9149 		rf_reg_record[CHAIN_0][7].bank = 5;
9150 		rf_reg_record[CHAIN_0][7].reg = 3;
9151 		rf_reg_record[CHAIN_0][7].value = rfvalue;
9152 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
9153 		rf_reg_record[CHAIN_0][8].bank = 5;
9154 		rf_reg_record[CHAIN_0][8].reg = 4;
9155 		rf_reg_record[CHAIN_0][8].value = rfvalue;
9156 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
9157 		rf_reg_record[CHAIN_0][9].bank = 5;
9158 		rf_reg_record[CHAIN_0][9].reg = 17;
9159 		rf_reg_record[CHAIN_0][9].value = rfvalue;
9160 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18);
9161 		rf_reg_record[CHAIN_0][10].bank = 5;
9162 		rf_reg_record[CHAIN_0][10].reg = 18;
9163 		rf_reg_record[CHAIN_0][10].value = rfvalue;
9164 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19);
9165 		rf_reg_record[CHAIN_0][11].bank = 5;
9166 		rf_reg_record[CHAIN_0][11].reg = 19;
9167 		rf_reg_record[CHAIN_0][11].value = rfvalue;
9168 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20);
9169 		rf_reg_record[CHAIN_0][12].bank = 5;
9170 		rf_reg_record[CHAIN_0][12].reg = 20;
9171 		rf_reg_record[CHAIN_0][12].value = rfvalue;
9172 	} else if (chain == CHAIN_1) {
9173 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1);
9174 		rf_reg_record[CHAIN_1][0].bank = 0;
9175 		rf_reg_record[CHAIN_1][0].reg = 1;
9176 		rf_reg_record[CHAIN_1][0].value = rfvalue;
9177 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2);
9178 		rf_reg_record[CHAIN_1][1].bank = 0;
9179 		rf_reg_record[CHAIN_1][1].reg = 2;
9180 		rf_reg_record[CHAIN_1][1].value = rfvalue;
9181 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 35);
9182 		rf_reg_record[CHAIN_1][2].bank = 0;
9183 		rf_reg_record[CHAIN_1][2].reg = 35;
9184 		rf_reg_record[CHAIN_1][2].value = rfvalue;
9185 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42);
9186 		rf_reg_record[CHAIN_1][3].bank = 0;
9187 		rf_reg_record[CHAIN_1][3].reg = 42;
9188 		rf_reg_record[CHAIN_1][3].value = rfvalue;
9189 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 6, 0);
9190 		rf_reg_record[CHAIN_1][4].bank = 6;
9191 		rf_reg_record[CHAIN_1][4].reg = 0;
9192 		rf_reg_record[CHAIN_1][4].value = rfvalue;
9193 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 6, 2);
9194 		rf_reg_record[CHAIN_1][5].bank = 6;
9195 		rf_reg_record[CHAIN_1][5].reg = 2;
9196 		rf_reg_record[CHAIN_1][5].value = rfvalue;
9197 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 6, 34);
9198 		rf_reg_record[CHAIN_1][6].bank = 6;
9199 		rf_reg_record[CHAIN_1][6].reg = 34;
9200 		rf_reg_record[CHAIN_1][6].value = rfvalue;
9201 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 3);
9202 		rf_reg_record[CHAIN_1][7].bank = 7;
9203 		rf_reg_record[CHAIN_1][7].reg = 3;
9204 		rf_reg_record[CHAIN_1][7].value = rfvalue;
9205 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 4);
9206 		rf_reg_record[CHAIN_1][8].bank = 7;
9207 		rf_reg_record[CHAIN_1][8].reg = 4;
9208 		rf_reg_record[CHAIN_1][8].value = rfvalue;
9209 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 17);
9210 		rf_reg_record[CHAIN_1][9].bank = 7;
9211 		rf_reg_record[CHAIN_1][9].reg = 17;
9212 		rf_reg_record[CHAIN_1][9].value = rfvalue;
9213 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 18);
9214 		rf_reg_record[CHAIN_1][10].bank = 7;
9215 		rf_reg_record[CHAIN_1][10].reg = 18;
9216 		rf_reg_record[CHAIN_1][10].value = rfvalue;
9217 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 19);
9218 		rf_reg_record[CHAIN_1][11].bank = 7;
9219 		rf_reg_record[CHAIN_1][11].reg = 19;
9220 		rf_reg_record[CHAIN_1][11].value = rfvalue;
9221 		rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 20);
9222 		rf_reg_record[CHAIN_1][12].bank = 7;
9223 		rf_reg_record[CHAIN_1][12].reg = 20;
9224 		rf_reg_record[CHAIN_1][12].value = rfvalue;
9225 	} else {
9226 		rt2x00_warn(rt2x00dev, "Unknown chain = %u\n", chain);
9227 	}
9228 }
9229 
rt2800_rf_configrecover(struct rt2x00_dev * rt2x00dev,struct rf_reg_pair rf_record[][13])9230 static void rt2800_rf_configrecover(struct rt2x00_dev *rt2x00dev,
9231 				    struct rf_reg_pair rf_record[][13])
9232 {
9233 	u8 chain_index = 0, record_index = 0;
9234 	u8 bank = 0, rf_register = 0, value = 0;
9235 
9236 	for (chain_index = 0; chain_index < 2; chain_index++) {
9237 		for (record_index = 0; record_index < 13; record_index++) {
9238 			bank = rf_record[chain_index][record_index].bank;
9239 			rf_register = rf_record[chain_index][record_index].reg;
9240 			value = rf_record[chain_index][record_index].value;
9241 			rt2800_rfcsr_write_bank(rt2x00dev, bank, rf_register, value);
9242 			rt2x00_dbg(rt2x00dev, "bank: %d, rf_register: %d, value: %x\n",
9243 				   bank, rf_register, value);
9244 		}
9245 	}
9246 }
9247 
rt2800_setbbptonegenerator(struct rt2x00_dev * rt2x00dev)9248 static void rt2800_setbbptonegenerator(struct rt2x00_dev *rt2x00dev)
9249 {
9250 	rt2800_bbp_write(rt2x00dev, 158, 0xAA);
9251 	rt2800_bbp_write(rt2x00dev, 159, 0x00);
9252 
9253 	rt2800_bbp_write(rt2x00dev, 158, 0xAB);
9254 	rt2800_bbp_write(rt2x00dev, 159, 0x0A);
9255 
9256 	rt2800_bbp_write(rt2x00dev, 158, 0xAC);
9257 	rt2800_bbp_write(rt2x00dev, 159, 0x3F);
9258 
9259 	rt2800_bbp_write(rt2x00dev, 158, 0xAD);
9260 	rt2800_bbp_write(rt2x00dev, 159, 0x3F);
9261 
9262 	rt2800_bbp_write(rt2x00dev, 244, 0x40);
9263 }
9264 
rt2800_do_fft_accumulation(struct rt2x00_dev * rt2x00dev,u8 tidx,u8 read_neg)9265 static u32 rt2800_do_fft_accumulation(struct rt2x00_dev *rt2x00dev, u8 tidx, u8 read_neg)
9266 {
9267 	u32 macvalue = 0;
9268 	int fftout_i = 0, fftout_q = 0;
9269 	u32 ptmp = 0, pint = 0;
9270 	u8 bbp = 0;
9271 	u8 tidxi;
9272 
9273 	rt2800_bbp_write(rt2x00dev, 158, 0x00);
9274 	rt2800_bbp_write(rt2x00dev, 159, 0x9b);
9275 
9276 	bbp = 0x9b;
9277 
9278 	while (bbp == 0x9b) {
9279 		usleep_range(10, 50);
9280 		bbp = rt2800_bbp_read(rt2x00dev, 159);
9281 		bbp = bbp & 0xff;
9282 	}
9283 
9284 	rt2800_bbp_write(rt2x00dev, 158, 0xba);
9285 	rt2800_bbp_write(rt2x00dev, 159, tidx);
9286 	rt2800_bbp_write(rt2x00dev, 159, tidx);
9287 	rt2800_bbp_write(rt2x00dev, 159, tidx);
9288 
9289 	macvalue = rt2800_register_read(rt2x00dev, 0x057C);
9290 
9291 	fftout_i = (macvalue >> 16);
9292 	fftout_i = (fftout_i & 0x8000) ? (fftout_i - 0x10000) : fftout_i;
9293 	fftout_q = (macvalue & 0xffff);
9294 	fftout_q = (fftout_q & 0x8000) ? (fftout_q - 0x10000) : fftout_q;
9295 	ptmp = (fftout_i * fftout_i);
9296 	ptmp = ptmp + (fftout_q * fftout_q);
9297 	pint = ptmp;
9298 	rt2x00_dbg(rt2x00dev, "I = %d,  Q = %d, power = %x\n", fftout_i, fftout_q, pint);
9299 	if (read_neg) {
9300 		pint = pint >> 1;
9301 		tidxi = 0x40 - tidx;
9302 		tidxi = tidxi & 0x3f;
9303 
9304 		rt2800_bbp_write(rt2x00dev, 158, 0xba);
9305 		rt2800_bbp_write(rt2x00dev, 159, tidxi);
9306 		rt2800_bbp_write(rt2x00dev, 159, tidxi);
9307 		rt2800_bbp_write(rt2x00dev, 159, tidxi);
9308 
9309 		macvalue = rt2800_register_read(rt2x00dev, 0x057C);
9310 
9311 		fftout_i = (macvalue >> 16);
9312 		fftout_i = (fftout_i & 0x8000) ? (fftout_i - 0x10000) : fftout_i;
9313 		fftout_q = (macvalue & 0xffff);
9314 		fftout_q = (fftout_q & 0x8000) ? (fftout_q - 0x10000) : fftout_q;
9315 		ptmp = (fftout_i * fftout_i);
9316 		ptmp = ptmp + (fftout_q * fftout_q);
9317 		ptmp = ptmp >> 1;
9318 		pint = pint + ptmp;
9319 	}
9320 
9321 	return pint;
9322 }
9323 
rt2800_read_fft_accumulation(struct rt2x00_dev * rt2x00dev,u8 tidx)9324 static u32 rt2800_read_fft_accumulation(struct rt2x00_dev *rt2x00dev, u8 tidx)
9325 {
9326 	u32 macvalue = 0;
9327 	int fftout_i = 0, fftout_q = 0;
9328 	u32 ptmp = 0, pint = 0;
9329 
9330 	rt2800_bbp_write(rt2x00dev, 158, 0xBA);
9331 	rt2800_bbp_write(rt2x00dev, 159, tidx);
9332 	rt2800_bbp_write(rt2x00dev, 159, tidx);
9333 	rt2800_bbp_write(rt2x00dev, 159, tidx);
9334 
9335 	macvalue = rt2800_register_read(rt2x00dev, 0x057C);
9336 
9337 	fftout_i = (macvalue >> 16);
9338 	fftout_i = (fftout_i & 0x8000) ? (fftout_i - 0x10000) : fftout_i;
9339 	fftout_q = (macvalue & 0xffff);
9340 	fftout_q = (fftout_q & 0x8000) ? (fftout_q - 0x10000) : fftout_q;
9341 	ptmp = (fftout_i * fftout_i);
9342 	ptmp = ptmp + (fftout_q * fftout_q);
9343 	pint = ptmp;
9344 
9345 	return pint;
9346 }
9347 
rt2800_write_dc(struct rt2x00_dev * rt2x00dev,u8 ch_idx,u8 alc,u8 iorq,u8 dc)9348 static void rt2800_write_dc(struct rt2x00_dev *rt2x00dev, u8 ch_idx, u8 alc, u8 iorq, u8 dc)
9349 {
9350 	u8 bbp = 0;
9351 
9352 	rt2800_bbp_write(rt2x00dev, 158, 0xb0);
9353 	bbp = alc | 0x80;
9354 	rt2800_bbp_write(rt2x00dev, 159, bbp);
9355 
9356 	if (ch_idx == 0)
9357 		bbp = (iorq == 0) ? 0xb1 : 0xb2;
9358 	else
9359 		bbp = (iorq == 0) ? 0xb8 : 0xb9;
9360 
9361 	rt2800_bbp_write(rt2x00dev, 158, bbp);
9362 	bbp = dc;
9363 	rt2800_bbp_write(rt2x00dev, 159, bbp);
9364 }
9365 
rt2800_loft_search(struct rt2x00_dev * rt2x00dev,u8 ch_idx,u8 alc_idx,u8 dc_result[][RF_ALC_NUM][2])9366 static void rt2800_loft_search(struct rt2x00_dev *rt2x00dev, u8 ch_idx,
9367 			       u8 alc_idx, u8 dc_result[][RF_ALC_NUM][2])
9368 {
9369 	u32 p0 = 0, p1 = 0, pf = 0;
9370 	s8 idx0 = 0, idx1 = 0;
9371 	u8 idxf[] = {0x00, 0x00};
9372 	u8 ibit = 0x20;
9373 	u8 iorq;
9374 	s8 bidx;
9375 
9376 	rt2800_bbp_write(rt2x00dev, 158, 0xb0);
9377 	rt2800_bbp_write(rt2x00dev, 159, 0x80);
9378 
9379 	for (bidx = 5; bidx >= 0; bidx--) {
9380 		for (iorq = 0; iorq <= 1; iorq++) {
9381 			if (idxf[iorq] == 0x20) {
9382 				idx0 = 0x20;
9383 				p0 = pf;
9384 			} else {
9385 				idx0 = idxf[iorq] - ibit;
9386 				idx0 = idx0 & 0x3F;
9387 				rt2800_write_dc(rt2x00dev, ch_idx, 0, iorq, idx0);
9388 				p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);
9389 			}
9390 
9391 			idx1 = idxf[iorq] + (bidx == 5 ? 0 : ibit);
9392 			idx1 = idx1 & 0x3F;
9393 			rt2800_write_dc(rt2x00dev, ch_idx, 0, iorq, idx1);
9394 			p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);
9395 
9396 			rt2x00_dbg(rt2x00dev, "alc=%u, IorQ=%u, idx_final=%2x\n",
9397 				   alc_idx, iorq, idxf[iorq]);
9398 			rt2x00_dbg(rt2x00dev, "p0=%x, p1=%x, pf=%x, idx_0=%x, idx_1=%x, ibit=%x\n",
9399 				   p0, p1, pf, idx0, idx1, ibit);
9400 
9401 			if (bidx != 5 && pf <= p0 && pf < p1) {
9402 				idxf[iorq] = idxf[iorq];
9403 			} else if (p0 < p1) {
9404 				pf = p0;
9405 				idxf[iorq] = idx0 & 0x3F;
9406 			} else {
9407 				pf = p1;
9408 				idxf[iorq] = idx1 & 0x3F;
9409 			}
9410 			rt2x00_dbg(rt2x00dev, "IorQ=%u, idx_final[%u]:%x, pf:%8x\n",
9411 				   iorq, iorq, idxf[iorq], pf);
9412 
9413 			rt2800_write_dc(rt2x00dev, ch_idx, 0, iorq, idxf[iorq]);
9414 		}
9415 		ibit = ibit >> 1;
9416 	}
9417 	dc_result[ch_idx][alc_idx][0] = idxf[0];
9418 	dc_result[ch_idx][alc_idx][1] = idxf[1];
9419 }
9420 
rt2800_iq_search(struct rt2x00_dev * rt2x00dev,u8 ch_idx,u8 * ges,u8 * pes)9421 static void rt2800_iq_search(struct rt2x00_dev *rt2x00dev, u8 ch_idx, u8 *ges, u8 *pes)
9422 {
9423 	u32 p0 = 0, p1 = 0, pf = 0;
9424 	s8 perr = 0, gerr = 0, iq_err = 0;
9425 	s8 pef = 0, gef = 0;
9426 	s8 psta, pend;
9427 	s8 gsta, gend;
9428 
9429 	u8 ibit = 0x20;
9430 	u8 first_search = 0x00, touch_neg_max = 0x00;
9431 	s8 idx0 = 0, idx1 = 0;
9432 	u8 gop;
9433 	u8 bbp = 0;
9434 	s8 bidx;
9435 
9436 	for (bidx = 5; bidx >= 1; bidx--) {
9437 		for (gop = 0; gop < 2; gop++) {
9438 			if (gop == 1 || bidx < 4) {
9439 				if (gop == 0)
9440 					iq_err = gerr;
9441 				else
9442 					iq_err = perr;
9443 
9444 				first_search = (gop == 0) ? (bidx == 3) : (bidx == 5);
9445 				touch_neg_max = (gop) ? ((iq_err & 0x0F) == 0x08) :
9446 							((iq_err & 0x3F) == 0x20);
9447 
9448 				if (touch_neg_max) {
9449 					p0 = pf;
9450 					idx0 = iq_err;
9451 				} else {
9452 					idx0 = iq_err - ibit;
9453 					bbp = (ch_idx == 0) ? ((gop == 0) ? 0x28 : 0x29) :
9454 							      ((gop == 0) ? 0x46 : 0x47);
9455 
9456 					rt2800_bbp_write(rt2x00dev, 158, bbp);
9457 					rt2800_bbp_write(rt2x00dev, 159, idx0);
9458 
9459 					p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 1);
9460 				}
9461 
9462 				idx1 = iq_err + (first_search ? 0 : ibit);
9463 				idx1 = (gop == 0) ? (idx1 & 0x0F) : (idx1 & 0x3F);
9464 
9465 				bbp = (ch_idx == 0) ? (gop == 0) ? 0x28 : 0x29 :
9466 				      (gop == 0) ? 0x46 : 0x47;
9467 
9468 				rt2800_bbp_write(rt2x00dev, 158, bbp);
9469 				rt2800_bbp_write(rt2x00dev, 159, idx1);
9470 
9471 				p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 1);
9472 
9473 				rt2x00_dbg(rt2x00dev,
9474 					   "p0=%x, p1=%x, pwer_final=%x, idx0=%x, idx1=%x, iq_err=%x, gop=%d, ibit=%x\n",
9475 					   p0, p1, pf, idx0, idx1, iq_err, gop, ibit);
9476 
9477 				if (!(!first_search && pf <= p0 && pf < p1)) {
9478 					if (p0 < p1) {
9479 						pf = p0;
9480 						iq_err = idx0;
9481 					} else {
9482 						pf = p1;
9483 						iq_err = idx1;
9484 					}
9485 				}
9486 
9487 				bbp = (ch_idx == 0) ? (gop == 0) ? 0x28 : 0x29 :
9488 						      (gop == 0) ? 0x46 : 0x47;
9489 
9490 				rt2800_bbp_write(rt2x00dev, 158, bbp);
9491 				rt2800_bbp_write(rt2x00dev, 159, iq_err);
9492 
9493 				if (gop == 0)
9494 					gerr = iq_err;
9495 				else
9496 					perr = iq_err;
9497 
9498 				rt2x00_dbg(rt2x00dev, "IQCalibration pf=%8x (%2x, %2x) !\n",
9499 					   pf, gerr & 0x0F, perr & 0x3F);
9500 			}
9501 		}
9502 
9503 		if (bidx > 0)
9504 			ibit = (ibit >> 1);
9505 	}
9506 	gerr = (gerr & 0x08) ? (gerr & 0x0F) - 0x10 : (gerr & 0x0F);
9507 	perr = (perr & 0x20) ? (perr & 0x3F) - 0x40 : (perr & 0x3F);
9508 
9509 	gerr = (gerr < -0x07) ? -0x07 : (gerr > 0x05) ? 0x05 : gerr;
9510 	gsta = gerr - 1;
9511 	gend = gerr + 2;
9512 
9513 	perr = (perr < -0x1f) ? -0x1f : (perr > 0x1d) ? 0x1d : perr;
9514 	psta = perr - 1;
9515 	pend = perr + 2;
9516 
9517 	for (gef = gsta; gef <= gend; gef = gef + 1)
9518 		for (pef = psta; pef <= pend; pef = pef + 1) {
9519 			bbp = (ch_idx == 0) ? 0x28 : 0x46;
9520 			rt2800_bbp_write(rt2x00dev, 158, bbp);
9521 			rt2800_bbp_write(rt2x00dev, 159, gef & 0x0F);
9522 
9523 			bbp = (ch_idx == 0) ? 0x29 : 0x47;
9524 			rt2800_bbp_write(rt2x00dev, 158, bbp);
9525 			rt2800_bbp_write(rt2x00dev, 159, pef & 0x3F);
9526 
9527 			p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 1);
9528 			if (gef == gsta && pef == psta) {
9529 				pf = p1;
9530 				gerr = gef;
9531 				perr = pef;
9532 			} else if (pf > p1) {
9533 				pf = p1;
9534 				gerr = gef;
9535 				perr = pef;
9536 			}
9537 			rt2x00_dbg(rt2x00dev, "Fine IQCalibration p1=%8x pf=%8x (%2x, %2x) !\n",
9538 				   p1, pf, gef & 0x0F, pef & 0x3F);
9539 		}
9540 
9541 	ges[ch_idx] = gerr & 0x0F;
9542 	pes[ch_idx] = perr & 0x3F;
9543 }
9544 
rt2800_rf_aux_tx0_loopback(struct rt2x00_dev * rt2x00dev)9545 static void rt2800_rf_aux_tx0_loopback(struct rt2x00_dev *rt2x00dev)
9546 {
9547 	rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, 0x21);
9548 	rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, 0x10);
9549 	rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x00);
9550 	rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, 0x1b);
9551 	rt2800_rfcsr_write_bank(rt2x00dev, 4, 0, 0x81);
9552 	rt2800_rfcsr_write_bank(rt2x00dev, 4, 2, 0x81);
9553 	rt2800_rfcsr_write_bank(rt2x00dev, 4, 34, 0xee);
9554 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, 0x2d);
9555 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, 0x2d);
9556 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, 0x80);
9557 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xd7);
9558 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0xa2);
9559 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x20);
9560 }
9561 
rt2800_rf_aux_tx1_loopback(struct rt2x00_dev * rt2x00dev)9562 static void rt2800_rf_aux_tx1_loopback(struct rt2x00_dev *rt2x00dev)
9563 {
9564 	rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, 0x22);
9565 	rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, 0x20);
9566 	rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x00);
9567 	rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, 0x4b);
9568 	rt2800_rfcsr_write_bank(rt2x00dev, 6, 0, 0x81);
9569 	rt2800_rfcsr_write_bank(rt2x00dev, 6, 2, 0x81);
9570 	rt2800_rfcsr_write_bank(rt2x00dev, 6, 34, 0xee);
9571 	rt2800_rfcsr_write_bank(rt2x00dev, 7, 3, 0x2d);
9572 	rt2800_rfcsr_write_bank(rt2x00dev, 7, 4, 0x2d);
9573 	rt2800_rfcsr_write_bank(rt2x00dev, 7, 17, 0x80);
9574 	rt2800_rfcsr_write_bank(rt2x00dev, 7, 18, 0xd7);
9575 	rt2800_rfcsr_write_bank(rt2x00dev, 7, 19, 0xa2);
9576 	rt2800_rfcsr_write_bank(rt2x00dev, 7, 20, 0x20);
9577 }
9578 
rt2800_loft_iq_calibration(struct rt2x00_dev * rt2x00dev)9579 static void rt2800_loft_iq_calibration(struct rt2x00_dev *rt2x00dev)
9580 {
9581 	struct rf_reg_pair rf_store[CHAIN_NUM][13];
9582 	u32 macorg1 = 0;
9583 	u32 macorg2 = 0;
9584 	u32 macorg3 = 0;
9585 	u32 macorg4 = 0;
9586 	u32 macorg5 = 0;
9587 	u32 orig528 = 0;
9588 	u32 orig52c = 0;
9589 
9590 	u32 savemacsysctrl = 0;
9591 	u32 macvalue = 0;
9592 	u32 mac13b8 = 0;
9593 	u32 p0 = 0, p1 = 0;
9594 	u32 p0_idx10 = 0, p1_idx10 = 0;
9595 
9596 	u8 rfvalue;
9597 	u8 loft_dc_search_result[CHAIN_NUM][RF_ALC_NUM][2];
9598 	u8 ger[CHAIN_NUM], per[CHAIN_NUM];
9599 
9600 	u8 vga_gain[] = {14, 14};
9601 	u8 bbp = 0, ch_idx = 0, rf_alc_idx = 0, idx = 0;
9602 	u8 bbpr30, rfb0r39, rfb0r42;
9603 	u8 bbpr1;
9604 	u8 bbpr4;
9605 	u8 bbpr241, bbpr242;
9606 	u8 count_step;
9607 
9608 	static const u8 rf_gain[] = {0x00, 0x01, 0x02, 0x04, 0x08, 0x0c};
9609 	static const u8 rfvga_gain_table[] = {0x24, 0x25, 0x26, 0x27, 0x28, 0x2c, 0x2d, 0x2e, 0x2f, 0x30,
9610 					      0x31, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3F};
9611 	static const u8 bbp_2324gain[] = {0x16, 0x14, 0x12, 0x10, 0x0c, 0x08};
9612 
9613 	savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
9614 	macorg1 = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
9615 	macorg2 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
9616 	macorg3 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
9617 	macorg4 = rt2800_register_read(rt2x00dev, RF_CONTROL3);
9618 	macorg5 = rt2800_register_read(rt2x00dev, RF_BYPASS3);
9619 	mac13b8 = rt2800_register_read(rt2x00dev, 0x13b8);
9620 	orig528 = rt2800_register_read(rt2x00dev, RF_CONTROL2);
9621 	orig52c = rt2800_register_read(rt2x00dev, RF_BYPASS2);
9622 
9623 	macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
9624 	macvalue &= (~0x04);
9625 	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
9626 
9627 	if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_TX)))
9628 		rt2x00_warn(rt2x00dev, "RF TX busy in LOFT IQ calibration\n");
9629 
9630 	macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
9631 	macvalue &= (~0x08);
9632 	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
9633 
9634 	if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_RX)))
9635 		rt2x00_warn(rt2x00dev, "RF RX busy in LOFT IQ calibration\n");
9636 
9637 	for (ch_idx = 0; ch_idx < 2; ch_idx++)
9638 		rt2800_rf_configstore(rt2x00dev, rf_store, ch_idx);
9639 
9640 	bbpr30 = rt2800_bbp_read(rt2x00dev, 30);
9641 	rfb0r39 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 39);
9642 	rfb0r42 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42);
9643 
9644 	rt2800_bbp_write(rt2x00dev, 30, 0x1F);
9645 	rt2800_rfcsr_write_bank(rt2x00dev, 0, 39, 0x80);
9646 	rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, 0x5B);
9647 
9648 	rt2800_bbp_write(rt2x00dev, 23, 0x00);
9649 	rt2800_bbp_write(rt2x00dev, 24, 0x00);
9650 
9651 	rt2800_setbbptonegenerator(rt2x00dev);
9652 
9653 	for (ch_idx = 0; ch_idx < 2; ch_idx++) {
9654 		rt2800_bbp_write(rt2x00dev, 23, 0x00);
9655 		rt2800_bbp_write(rt2x00dev, 24, 0x00);
9656 		rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00);
9657 		rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x0000000F);
9658 		rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004);
9659 		rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00003306);
9660 		rt2800_register_write(rt2x00dev, 0x13b8, 0x10);
9661 		udelay(1);
9662 
9663 		if (ch_idx == 0)
9664 			rt2800_rf_aux_tx0_loopback(rt2x00dev);
9665 		else
9666 			rt2800_rf_aux_tx1_loopback(rt2x00dev);
9667 
9668 		udelay(1);
9669 
9670 		if (ch_idx == 0)
9671 			rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001004);
9672 		else
9673 			rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00002004);
9674 
9675 		rt2800_bbp_write(rt2x00dev, 158, 0x05);
9676 		rt2800_bbp_write(rt2x00dev, 159, 0x00);
9677 
9678 		rt2800_bbp_write(rt2x00dev, 158, 0x01);
9679 		if (ch_idx == 0)
9680 			rt2800_bbp_write(rt2x00dev, 159, 0x00);
9681 		else
9682 			rt2800_bbp_write(rt2x00dev, 159, 0x01);
9683 
9684 		vga_gain[ch_idx] = 18;
9685 		for (rf_alc_idx = 0; rf_alc_idx < 3; rf_alc_idx++) {
9686 			rt2800_bbp_write(rt2x00dev, 23, bbp_2324gain[rf_alc_idx]);
9687 			rt2800_bbp_write(rt2x00dev, 24, bbp_2324gain[rf_alc_idx]);
9688 
9689 			macvalue = rt2800_register_read(rt2x00dev, RF_CONTROL3);
9690 			macvalue &= (~0x0000F1F1);
9691 			macvalue |= (rf_gain[rf_alc_idx] << 4);
9692 			macvalue |= (rf_gain[rf_alc_idx] << 12);
9693 			rt2800_register_write(rt2x00dev, RF_CONTROL3, macvalue);
9694 			macvalue = (0x0000F1F1);
9695 			rt2800_register_write(rt2x00dev, RF_BYPASS3, macvalue);
9696 
9697 			if (rf_alc_idx == 0) {
9698 				rt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x21);
9699 				for (; vga_gain[ch_idx] > 0;
9700 				     vga_gain[ch_idx] = vga_gain[ch_idx] - 2) {
9701 					rfvalue = rfvga_gain_table[vga_gain[ch_idx]];
9702 					rt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue);
9703 					rt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue);
9704 					rt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x00);
9705 					rt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x00);
9706 					p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);
9707 					rt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x21);
9708 					p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);
9709 					rt2x00_dbg(rt2x00dev, "LOFT AGC %d %d\n", p0, p1);
9710 					if ((p0 < 7000 * 7000) && (p1 < (7000 * 7000)))
9711 						break;
9712 				}
9713 
9714 				rt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x00);
9715 				rt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x00);
9716 
9717 				rt2x00_dbg(rt2x00dev, "Used VGA %d %x\n", vga_gain[ch_idx],
9718 					   rfvga_gain_table[vga_gain[ch_idx]]);
9719 			}
9720 
9721 			rfvalue = rfvga_gain_table[vga_gain[ch_idx]];
9722 
9723 			rt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue);
9724 			rt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue);
9725 
9726 			rt2800_loft_search(rt2x00dev, ch_idx, rf_alc_idx, loft_dc_search_result);
9727 		}
9728 	}
9729 
9730 	for (rf_alc_idx = 0; rf_alc_idx < 3; rf_alc_idx++) {
9731 		for (idx = 0; idx < 4; idx++) {
9732 			rt2800_bbp_write(rt2x00dev, 158, 0xB0);
9733 			bbp = (idx << 2) + rf_alc_idx;
9734 			rt2800_bbp_write(rt2x00dev, 159, bbp);
9735 			rt2x00_dbg(rt2x00dev, " ALC %2x,", bbp);
9736 
9737 			rt2800_bbp_write(rt2x00dev, 158, 0xb1);
9738 			bbp = loft_dc_search_result[CHAIN_0][rf_alc_idx][0x00];
9739 			bbp = bbp & 0x3F;
9740 			rt2800_bbp_write(rt2x00dev, 159, bbp);
9741 			rt2x00_dbg(rt2x00dev, " I0 %2x,", bbp);
9742 
9743 			rt2800_bbp_write(rt2x00dev, 158, 0xb2);
9744 			bbp = loft_dc_search_result[CHAIN_0][rf_alc_idx][0x01];
9745 			bbp = bbp & 0x3F;
9746 			rt2800_bbp_write(rt2x00dev, 159, bbp);
9747 			rt2x00_dbg(rt2x00dev, " Q0 %2x,", bbp);
9748 
9749 			rt2800_bbp_write(rt2x00dev, 158, 0xb8);
9750 			bbp = loft_dc_search_result[CHAIN_1][rf_alc_idx][0x00];
9751 			bbp = bbp & 0x3F;
9752 			rt2800_bbp_write(rt2x00dev, 159, bbp);
9753 			rt2x00_dbg(rt2x00dev, " I1 %2x,", bbp);
9754 
9755 			rt2800_bbp_write(rt2x00dev, 158, 0xb9);
9756 			bbp = loft_dc_search_result[CHAIN_1][rf_alc_idx][0x01];
9757 			bbp = bbp & 0x3F;
9758 			rt2800_bbp_write(rt2x00dev, 159, bbp);
9759 			rt2x00_dbg(rt2x00dev, " Q1 %2x\n", bbp);
9760 		}
9761 	}
9762 
9763 	rt2800_bbp_write(rt2x00dev, 23, 0x00);
9764 	rt2800_bbp_write(rt2x00dev, 24, 0x00);
9765 
9766 	rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
9767 
9768 	rt2800_bbp_write(rt2x00dev, 158, 0x00);
9769 	rt2800_bbp_write(rt2x00dev, 159, 0x00);
9770 
9771 	bbp = 0x00;
9772 	rt2800_bbp_write(rt2x00dev, 244, 0x00);
9773 
9774 	rt2800_bbp_write(rt2x00dev, 21, 0x01);
9775 	udelay(1);
9776 	rt2800_bbp_write(rt2x00dev, 21, 0x00);
9777 
9778 	rt2800_rf_configrecover(rt2x00dev, rf_store);
9779 
9780 	rt2800_register_write(rt2x00dev, TX_PIN_CFG, macorg1);
9781 	rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
9782 	rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00);
9783 	rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00);
9784 	rt2800_register_write(rt2x00dev, RF_CONTROL0, macorg2);
9785 	udelay(1);
9786 	rt2800_register_write(rt2x00dev, RF_BYPASS0, macorg3);
9787 	rt2800_register_write(rt2x00dev, RF_CONTROL3, macorg4);
9788 	rt2800_register_write(rt2x00dev, RF_BYPASS3, macorg5);
9789 	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl);
9790 	rt2800_register_write(rt2x00dev, RF_CONTROL2, orig528);
9791 	rt2800_register_write(rt2x00dev, RF_BYPASS2, orig52c);
9792 	rt2800_register_write(rt2x00dev, 0x13b8, mac13b8);
9793 
9794 	savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
9795 	macorg1 = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
9796 	macorg2 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
9797 	macorg3 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
9798 	macorg4 = rt2800_register_read(rt2x00dev, RF_CONTROL3);
9799 	macorg5 = rt2800_register_read(rt2x00dev, RF_BYPASS3);
9800 
9801 	bbpr1 = rt2800_bbp_read(rt2x00dev, 1);
9802 	bbpr4 = rt2800_bbp_read(rt2x00dev, 4);
9803 	bbpr241 = rt2800_bbp_read(rt2x00dev, 241);
9804 	bbpr242 = rt2800_bbp_read(rt2x00dev, 242);
9805 	mac13b8 = rt2800_register_read(rt2x00dev, 0x13b8);
9806 
9807 	macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
9808 	macvalue &= (~0x04);
9809 	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
9810 
9811 	if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_TX)))
9812 		rt2x00_warn(rt2x00dev, "RF TX busy in LOFT IQ calibration\n");
9813 
9814 	macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
9815 	macvalue &= (~0x08);
9816 	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
9817 
9818 	if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_RX)))
9819 		rt2x00_warn(rt2x00dev, "RF RX busy in LOFT IQ calibration\n");
9820 
9821 	if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
9822 		rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x00000101);
9823 		rt2800_register_write(rt2x00dev, RF_BYPASS3, 0x0000F1F1);
9824 	}
9825 
9826 	rt2800_bbp_write(rt2x00dev, 23, 0x00);
9827 	rt2800_bbp_write(rt2x00dev, 24, 0x00);
9828 
9829 	if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
9830 		rt2800_bbp_write(rt2x00dev, 4, bbpr4 & (~0x18));
9831 		rt2800_bbp_write(rt2x00dev, 21, 0x01);
9832 		udelay(1);
9833 		rt2800_bbp_write(rt2x00dev, 21, 0x00);
9834 
9835 		rt2800_bbp_write(rt2x00dev, 241, 0x14);
9836 		rt2800_bbp_write(rt2x00dev, 242, 0x80);
9837 		rt2800_bbp_write(rt2x00dev, 244, 0x31);
9838 	} else {
9839 		rt2800_setbbptonegenerator(rt2x00dev);
9840 	}
9841 
9842 	rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004);
9843 	rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00003306);
9844 	udelay(1);
9845 
9846 	rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x0000000F);
9847 
9848 	if (!test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
9849 		rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x00000000);
9850 		rt2800_register_write(rt2x00dev, RF_BYPASS3, 0x0000F1F1);
9851 	}
9852 
9853 	rt2800_register_write(rt2x00dev, 0x13b8, 0x00000010);
9854 
9855 	for (ch_idx = 0; ch_idx < 2; ch_idx++)
9856 		rt2800_rf_configstore(rt2x00dev, rf_store, ch_idx);
9857 
9858 	rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x3B);
9859 	rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x3B);
9860 
9861 	rt2800_bbp_write(rt2x00dev, 158, 0x03);
9862 	rt2800_bbp_write(rt2x00dev, 159, 0x60);
9863 	rt2800_bbp_write(rt2x00dev, 158, 0xB0);
9864 	rt2800_bbp_write(rt2x00dev, 159, 0x80);
9865 
9866 	for (ch_idx = 0; ch_idx < 2; ch_idx++) {
9867 		rt2800_bbp_write(rt2x00dev, 23, 0x00);
9868 		rt2800_bbp_write(rt2x00dev, 24, 0x00);
9869 
9870 		if (ch_idx == 0) {
9871 			rt2800_bbp_write(rt2x00dev, 158, 0x01);
9872 			rt2800_bbp_write(rt2x00dev, 159, 0x00);
9873 			if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
9874 				bbp = bbpr1 & (~0x18);
9875 				bbp = bbp | 0x00;
9876 				rt2800_bbp_write(rt2x00dev, 1, bbp);
9877 			}
9878 			rt2800_rf_aux_tx0_loopback(rt2x00dev);
9879 			rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001004);
9880 		} else {
9881 			rt2800_bbp_write(rt2x00dev, 158, 0x01);
9882 			rt2800_bbp_write(rt2x00dev, 159, 0x01);
9883 			if (test_bit(CAPABILITY_EXTERNAL_PA_TX1, &rt2x00dev->cap_flags)) {
9884 				bbp = bbpr1 & (~0x18);
9885 				bbp = bbp | 0x08;
9886 				rt2800_bbp_write(rt2x00dev, 1, bbp);
9887 			}
9888 			rt2800_rf_aux_tx1_loopback(rt2x00dev);
9889 			rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00002004);
9890 		}
9891 
9892 		rt2800_bbp_write(rt2x00dev, 158, 0x05);
9893 		rt2800_bbp_write(rt2x00dev, 159, 0x04);
9894 
9895 		bbp = (ch_idx == 0) ? 0x28 : 0x46;
9896 		rt2800_bbp_write(rt2x00dev, 158, bbp);
9897 		rt2800_bbp_write(rt2x00dev, 159, 0x00);
9898 
9899 		if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
9900 			rt2800_bbp_write(rt2x00dev, 23, 0x06);
9901 			rt2800_bbp_write(rt2x00dev, 24, 0x06);
9902 			count_step = 1;
9903 		} else {
9904 			rt2800_bbp_write(rt2x00dev, 23, 0x1F);
9905 			rt2800_bbp_write(rt2x00dev, 24, 0x1F);
9906 			count_step = 2;
9907 		}
9908 
9909 		for (; vga_gain[ch_idx] < 19; vga_gain[ch_idx] = (vga_gain[ch_idx] + count_step)) {
9910 			rfvalue = rfvga_gain_table[vga_gain[ch_idx]];
9911 			rt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue);
9912 			rt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue);
9913 
9914 			bbp = (ch_idx == 0) ? 0x29 : 0x47;
9915 			rt2800_bbp_write(rt2x00dev, 158, bbp);
9916 			rt2800_bbp_write(rt2x00dev, 159, 0x00);
9917 			p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 0);
9918 			if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags))
9919 				p0_idx10 = rt2800_read_fft_accumulation(rt2x00dev, 0x0A);
9920 
9921 			bbp = (ch_idx == 0) ? 0x29 : 0x47;
9922 			rt2800_bbp_write(rt2x00dev, 158, bbp);
9923 			rt2800_bbp_write(rt2x00dev, 159, 0x21);
9924 			p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 0);
9925 			if (test_bit(CAPABILITY_EXTERNAL_PA_TX1, &rt2x00dev->cap_flags))
9926 				p1_idx10 = rt2800_read_fft_accumulation(rt2x00dev, 0x0A);
9927 
9928 			rt2x00_dbg(rt2x00dev, "IQ AGC %d %d\n", p0, p1);
9929 
9930 			if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
9931 				rt2x00_dbg(rt2x00dev, "IQ AGC IDX 10 %d %d\n", p0_idx10, p1_idx10);
9932 				if ((p0_idx10 > 7000 * 7000) || (p1_idx10 > 7000 * 7000)) {
9933 					if (vga_gain[ch_idx] != 0)
9934 						vga_gain[ch_idx] = vga_gain[ch_idx] - 1;
9935 					break;
9936 				}
9937 			}
9938 
9939 			if ((p0 > 2500 * 2500) || (p1 > 2500 * 2500))
9940 				break;
9941 		}
9942 
9943 		if (vga_gain[ch_idx] > 18)
9944 			vga_gain[ch_idx] = 18;
9945 		rt2x00_dbg(rt2x00dev, "Used VGA %d %x\n", vga_gain[ch_idx],
9946 			   rfvga_gain_table[vga_gain[ch_idx]]);
9947 
9948 		bbp = (ch_idx == 0) ? 0x29 : 0x47;
9949 		rt2800_bbp_write(rt2x00dev, 158, bbp);
9950 		rt2800_bbp_write(rt2x00dev, 159, 0x00);
9951 
9952 		rt2800_iq_search(rt2x00dev, ch_idx, ger, per);
9953 	}
9954 
9955 	rt2800_bbp_write(rt2x00dev, 23, 0x00);
9956 	rt2800_bbp_write(rt2x00dev, 24, 0x00);
9957 	rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
9958 
9959 	rt2800_bbp_write(rt2x00dev, 158, 0x28);
9960 	bbp = ger[CHAIN_0] & 0x0F;
9961 	rt2800_bbp_write(rt2x00dev, 159, bbp);
9962 
9963 	rt2800_bbp_write(rt2x00dev, 158, 0x29);
9964 	bbp = per[CHAIN_0] & 0x3F;
9965 	rt2800_bbp_write(rt2x00dev, 159, bbp);
9966 
9967 	rt2800_bbp_write(rt2x00dev, 158, 0x46);
9968 	bbp = ger[CHAIN_1] & 0x0F;
9969 	rt2800_bbp_write(rt2x00dev, 159, bbp);
9970 
9971 	rt2800_bbp_write(rt2x00dev, 158, 0x47);
9972 	bbp = per[CHAIN_1] & 0x3F;
9973 	rt2800_bbp_write(rt2x00dev, 159, bbp);
9974 
9975 	if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
9976 		rt2800_bbp_write(rt2x00dev, 1, bbpr1);
9977 		rt2800_bbp_write(rt2x00dev, 241, bbpr241);
9978 		rt2800_bbp_write(rt2x00dev, 242, bbpr242);
9979 	}
9980 	rt2800_bbp_write(rt2x00dev, 244, 0x00);
9981 
9982 	rt2800_bbp_write(rt2x00dev, 158, 0x00);
9983 	rt2800_bbp_write(rt2x00dev, 159, 0x00);
9984 	rt2800_bbp_write(rt2x00dev, 158, 0xB0);
9985 	rt2800_bbp_write(rt2x00dev, 159, 0x00);
9986 
9987 	rt2800_bbp_write(rt2x00dev, 30, bbpr30);
9988 	rt2800_rfcsr_write_bank(rt2x00dev, 0, 39, rfb0r39);
9989 	rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfb0r42);
9990 
9991 	if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags))
9992 		rt2800_bbp_write(rt2x00dev, 4, bbpr4);
9993 
9994 	rt2800_bbp_write(rt2x00dev, 21, 0x01);
9995 	udelay(1);
9996 	rt2800_bbp_write(rt2x00dev, 21, 0x00);
9997 
9998 	rt2800_rf_configrecover(rt2x00dev, rf_store);
9999 
10000 	rt2800_register_write(rt2x00dev, TX_PIN_CFG, macorg1);
10001 	rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00);
10002 	rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00);
10003 	rt2800_register_write(rt2x00dev, RF_CONTROL0, macorg2);
10004 	udelay(1);
10005 	rt2800_register_write(rt2x00dev, RF_BYPASS0, macorg3);
10006 	rt2800_register_write(rt2x00dev, RF_CONTROL3, macorg4);
10007 	rt2800_register_write(rt2x00dev, RF_BYPASS3, macorg5);
10008 	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl);
10009 	rt2800_register_write(rt2x00dev, 0x13b8, mac13b8);
10010 }
10011 
rt2800_bbp_core_soft_reset(struct rt2x00_dev * rt2x00dev,bool set_bw,bool is_ht40)10012 static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev,
10013 				       bool set_bw, bool is_ht40)
10014 {
10015 	u8 bbp_val;
10016 
10017 	bbp_val = rt2800_bbp_read(rt2x00dev, 21);
10018 	bbp_val |= 0x1;
10019 	rt2800_bbp_write(rt2x00dev, 21, bbp_val);
10020 	usleep_range(100, 200);
10021 
10022 	if (set_bw) {
10023 		bbp_val = rt2800_bbp_read(rt2x00dev, 4);
10024 		rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH, 2 * is_ht40);
10025 		rt2800_bbp_write(rt2x00dev, 4, bbp_val);
10026 		usleep_range(100, 200);
10027 	}
10028 
10029 	bbp_val = rt2800_bbp_read(rt2x00dev, 21);
10030 	bbp_val &= (~0x1);
10031 	rt2800_bbp_write(rt2x00dev, 21, bbp_val);
10032 	usleep_range(100, 200);
10033 }
10034 
rt2800_rf_lp_config(struct rt2x00_dev * rt2x00dev,bool btxcal)10035 static int rt2800_rf_lp_config(struct rt2x00_dev *rt2x00dev, bool btxcal)
10036 {
10037 	u8 rf_val;
10038 
10039 	if (btxcal)
10040 		rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
10041 	else
10042 		rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x02);
10043 
10044 	rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x06);
10045 
10046 	rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
10047 	rf_val |= 0x80;
10048 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, rf_val);
10049 
10050 	if (btxcal) {
10051 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xC1);
10052 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x20);
10053 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02);
10054 		rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
10055 		rf_val &= (~0x3F);
10056 		rf_val |= 0x3F;
10057 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val);
10058 		rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
10059 		rf_val &= (~0x3F);
10060 		rf_val |= 0x3F;
10061 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val);
10062 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, 0x31);
10063 	} else {
10064 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xF1);
10065 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x18);
10066 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02);
10067 		rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
10068 		rf_val &= (~0x3F);
10069 		rf_val |= 0x34;
10070 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val);
10071 		rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
10072 		rf_val &= (~0x3F);
10073 		rf_val |= 0x34;
10074 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val);
10075 	}
10076 
10077 	return 0;
10078 }
10079 
rt2800_lp_tx_filter_bw_cal(struct rt2x00_dev * rt2x00dev)10080 static s8 rt2800_lp_tx_filter_bw_cal(struct rt2x00_dev *rt2x00dev)
10081 {
10082 	unsigned int cnt;
10083 	u8 bbp_val;
10084 	s8 cal_val;
10085 
10086 	rt2800_bbp_dcoc_write(rt2x00dev, 0, 0x82);
10087 
10088 	cnt = 0;
10089 	do {
10090 		usleep_range(500, 2000);
10091 		bbp_val = rt2800_bbp_read(rt2x00dev, 159);
10092 		if (bbp_val == 0x02 || cnt == 20)
10093 			break;
10094 
10095 		cnt++;
10096 	} while (cnt < 20);
10097 
10098 	bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 0x39);
10099 	cal_val = bbp_val & 0x7F;
10100 	if (cal_val >= 0x40)
10101 		cal_val -= 128;
10102 
10103 	return cal_val;
10104 }
10105 
rt2800_bw_filter_calibration(struct rt2x00_dev * rt2x00dev,bool btxcal)10106 static void rt2800_bw_filter_calibration(struct rt2x00_dev *rt2x00dev,
10107 					 bool btxcal)
10108 {
10109 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
10110 	u8 tx_agc_fc = 0, rx_agc_fc = 0, cmm_agc_fc;
10111 	u8 filter_target;
10112 	u8 tx_filter_target_20m = 0x09, tx_filter_target_40m = 0x02;
10113 	u8 rx_filter_target_20m = 0x27, rx_filter_target_40m = 0x31;
10114 	int loop = 0, is_ht40, cnt;
10115 	u8 bbp_val, rf_val;
10116 	s8 cal_r32_init, cal_r32_val, cal_diff;
10117 	u8 saverfb5r00, saverfb5r01, saverfb5r03, saverfb5r04, saverfb5r05;
10118 	u8 saverfb5r06, saverfb5r07;
10119 	u8 saverfb5r08, saverfb5r17, saverfb5r18, saverfb5r19, saverfb5r20;
10120 	u8 saverfb5r37, saverfb5r38, saverfb5r39, saverfb5r40, saverfb5r41;
10121 	u8 saverfb5r42, saverfb5r43, saverfb5r44, saverfb5r45, saverfb5r46;
10122 	u8 saverfb5r58, saverfb5r59;
10123 	u8 savebbp159r0, savebbp159r2, savebbpr23;
10124 	u32 MAC_RF_CONTROL0, MAC_RF_BYPASS0;
10125 
10126 	/* Save MAC registers */
10127 	MAC_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
10128 	MAC_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
10129 
10130 	/* save BBP registers */
10131 	savebbpr23 = rt2800_bbp_read(rt2x00dev, 23);
10132 
10133 	savebbp159r0 = rt2800_bbp_dcoc_read(rt2x00dev, 0);
10134 	savebbp159r2 = rt2800_bbp_dcoc_read(rt2x00dev, 2);
10135 
10136 	/* Save RF registers */
10137 	saverfb5r00 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0);
10138 	saverfb5r01 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
10139 	saverfb5r03 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
10140 	saverfb5r04 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
10141 	saverfb5r05 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 5);
10142 	saverfb5r06 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
10143 	saverfb5r07 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
10144 	saverfb5r08 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8);
10145 	saverfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
10146 	saverfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18);
10147 	saverfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19);
10148 	saverfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20);
10149 
10150 	saverfb5r37 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 37);
10151 	saverfb5r38 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 38);
10152 	saverfb5r39 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 39);
10153 	saverfb5r40 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 40);
10154 	saverfb5r41 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 41);
10155 	saverfb5r42 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 42);
10156 	saverfb5r43 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 43);
10157 	saverfb5r44 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 44);
10158 	saverfb5r45 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 45);
10159 	saverfb5r46 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 46);
10160 
10161 	saverfb5r58 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
10162 	saverfb5r59 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
10163 
10164 	rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0);
10165 	rf_val |= 0x3;
10166 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val);
10167 
10168 	rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
10169 	rf_val |= 0x1;
10170 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, rf_val);
10171 
10172 	cnt = 0;
10173 	do {
10174 		usleep_range(500, 2000);
10175 		rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
10176 		if (((rf_val & 0x1) == 0x00) || (cnt == 40))
10177 			break;
10178 		cnt++;
10179 	} while (cnt < 40);
10180 
10181 	rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0);
10182 	rf_val &= (~0x3);
10183 	rf_val |= 0x1;
10184 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val);
10185 
10186 	/* I-3 */
10187 	bbp_val = rt2800_bbp_read(rt2x00dev, 23);
10188 	bbp_val &= (~0x1F);
10189 	bbp_val |= 0x10;
10190 	rt2800_bbp_write(rt2x00dev, 23, bbp_val);
10191 
10192 	do {
10193 		/* I-4,5,6,7,8,9 */
10194 		if (loop == 0) {
10195 			is_ht40 = false;
10196 
10197 			if (btxcal)
10198 				filter_target = tx_filter_target_20m;
10199 			else
10200 				filter_target = rx_filter_target_20m;
10201 		} else {
10202 			is_ht40 = true;
10203 
10204 			if (btxcal)
10205 				filter_target = tx_filter_target_40m;
10206 			else
10207 				filter_target = rx_filter_target_40m;
10208 		}
10209 
10210 		rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8);
10211 		rf_val &= (~0x04);
10212 		if (loop == 1)
10213 			rf_val |= 0x4;
10214 
10215 		rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, rf_val);
10216 
10217 		rt2800_bbp_core_soft_reset(rt2x00dev, true, is_ht40);
10218 
10219 		rt2800_rf_lp_config(rt2x00dev, btxcal);
10220 		if (btxcal) {
10221 			tx_agc_fc = 0;
10222 			rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
10223 			rf_val &= (~0x7F);
10224 			rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val);
10225 			rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
10226 			rf_val &= (~0x7F);
10227 			rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val);
10228 		} else {
10229 			rx_agc_fc = 0;
10230 			rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
10231 			rf_val &= (~0x7F);
10232 			rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val);
10233 			rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
10234 			rf_val &= (~0x7F);
10235 			rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val);
10236 		}
10237 
10238 		usleep_range(1000, 2000);
10239 
10240 		bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 2);
10241 		bbp_val &= (~0x6);
10242 		rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val);
10243 
10244 		rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40);
10245 
10246 		cal_r32_init = rt2800_lp_tx_filter_bw_cal(rt2x00dev);
10247 
10248 		bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 2);
10249 		bbp_val |= 0x6;
10250 		rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val);
10251 do_cal:
10252 		if (btxcal) {
10253 			rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
10254 			rf_val &= (~0x7F);
10255 			rf_val |= tx_agc_fc;
10256 			rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val);
10257 			rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
10258 			rf_val &= (~0x7F);
10259 			rf_val |= tx_agc_fc;
10260 			rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val);
10261 		} else {
10262 			rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
10263 			rf_val &= (~0x7F);
10264 			rf_val |= rx_agc_fc;
10265 			rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val);
10266 			rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
10267 			rf_val &= (~0x7F);
10268 			rf_val |= rx_agc_fc;
10269 			rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val);
10270 		}
10271 
10272 		usleep_range(500, 1000);
10273 
10274 		rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40);
10275 
10276 		cal_r32_val = rt2800_lp_tx_filter_bw_cal(rt2x00dev);
10277 
10278 		cal_diff = cal_r32_init - cal_r32_val;
10279 
10280 		if (btxcal)
10281 			cmm_agc_fc = tx_agc_fc;
10282 		else
10283 			cmm_agc_fc = rx_agc_fc;
10284 
10285 		if (((cal_diff > filter_target) && (cmm_agc_fc == 0)) ||
10286 		    ((cal_diff < filter_target) && (cmm_agc_fc == 0x3f))) {
10287 			if (btxcal)
10288 				tx_agc_fc = 0;
10289 			else
10290 				rx_agc_fc = 0;
10291 		} else if ((cal_diff <= filter_target) && (cmm_agc_fc < 0x3f)) {
10292 			if (btxcal)
10293 				tx_agc_fc++;
10294 			else
10295 				rx_agc_fc++;
10296 			goto do_cal;
10297 		}
10298 
10299 		if (btxcal) {
10300 			if (loop == 0)
10301 				drv_data->tx_calibration_bw20 = tx_agc_fc;
10302 			else
10303 				drv_data->tx_calibration_bw40 = tx_agc_fc;
10304 		} else {
10305 			if (loop == 0)
10306 				drv_data->rx_calibration_bw20 = rx_agc_fc;
10307 			else
10308 				drv_data->rx_calibration_bw40 = rx_agc_fc;
10309 		}
10310 
10311 		loop++;
10312 	} while (loop <= 1);
10313 
10314 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, saverfb5r00);
10315 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, saverfb5r01);
10316 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, saverfb5r03);
10317 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r04);
10318 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, saverfb5r05);
10319 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, saverfb5r06);
10320 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, saverfb5r07);
10321 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, saverfb5r08);
10322 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, saverfb5r17);
10323 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, saverfb5r18);
10324 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, saverfb5r19);
10325 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, saverfb5r20);
10326 
10327 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 37, saverfb5r37);
10328 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 38, saverfb5r38);
10329 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 39, saverfb5r39);
10330 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 40, saverfb5r40);
10331 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 41, saverfb5r41);
10332 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 42, saverfb5r42);
10333 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 43, saverfb5r43);
10334 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 44, saverfb5r44);
10335 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 45, saverfb5r45);
10336 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 46, saverfb5r46);
10337 
10338 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, saverfb5r58);
10339 	rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, saverfb5r59);
10340 
10341 	rt2800_bbp_write(rt2x00dev, 23, savebbpr23);
10342 
10343 	rt2800_bbp_dcoc_write(rt2x00dev, 0, savebbp159r0);
10344 	rt2800_bbp_dcoc_write(rt2x00dev, 2, savebbp159r2);
10345 
10346 	bbp_val = rt2800_bbp_read(rt2x00dev, 4);
10347 	rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH,
10348 			  2 * test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags));
10349 	rt2800_bbp_write(rt2x00dev, 4, bbp_val);
10350 
10351 	rt2800_register_write(rt2x00dev, RF_CONTROL0, MAC_RF_CONTROL0);
10352 	rt2800_register_write(rt2x00dev, RF_BYPASS0, MAC_RF_BYPASS0);
10353 }
10354 
rt2800_restore_rf_bbp_rt6352(struct rt2x00_dev * rt2x00dev)10355 static void rt2800_restore_rf_bbp_rt6352(struct rt2x00_dev *rt2x00dev)
10356 {
10357 	if (rt2x00_has_cap_external_pa(rt2x00dev)) {
10358 		rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x0);
10359 		rt2800_register_write(rt2x00dev, RF_BYPASS3, 0x0);
10360 	}
10361 
10362 	if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
10363 		rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);
10364 		rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23);
10365 		rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x02);
10366 	}
10367 
10368 	if (rt2x00_has_cap_external_pa(rt2x00dev)) {
10369 		rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xd3);
10370 		rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xb3);
10371 		rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xd5);
10372 		rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
10373 		rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6c);
10374 		rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xfc);
10375 		rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1f);
10376 		rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
10377 		rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
10378 		rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xff);
10379 		rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1c);
10380 		rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20);
10381 		rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6b);
10382 		rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xf7);
10383 		rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09);
10384 	}
10385 
10386 	if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
10387 		rt2800_bbp_write(rt2x00dev, 75, 0x60);
10388 		rt2800_bbp_write(rt2x00dev, 76, 0x44);
10389 		rt2800_bbp_write(rt2x00dev, 79, 0x1c);
10390 		rt2800_bbp_write(rt2x00dev, 80, 0x0c);
10391 		rt2800_bbp_write(rt2x00dev, 82, 0xB6);
10392 	}
10393 
10394 	if (rt2x00_has_cap_external_pa(rt2x00dev)) {
10395 		rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT, 0x3630363a);
10396 		rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6c6c666c);
10397 		rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6c6c666c);
10398 	}
10399 }
10400 
rt2800_calibration_rt6352(struct rt2x00_dev * rt2x00dev)10401 static void rt2800_calibration_rt6352(struct rt2x00_dev *rt2x00dev)
10402 {
10403 	u32 reg;
10404 
10405 	if (rt2x00_has_cap_external_pa(rt2x00dev) ||
10406 	    rt2x00_has_cap_external_lna_bg(rt2x00dev))
10407 		rt2800_restore_rf_bbp_rt6352(rt2x00dev);
10408 
10409 	rt2800_r_calibration(rt2x00dev);
10410 	rt2800_rf_self_txdc_cal(rt2x00dev);
10411 	rt2800_rxdcoc_calibration(rt2x00dev);
10412 	rt2800_bw_filter_calibration(rt2x00dev, true);
10413 	rt2800_bw_filter_calibration(rt2x00dev, false);
10414 	rt2800_loft_iq_calibration(rt2x00dev);
10415 
10416 	/* missing DPD calibration for internal PA devices */
10417 
10418 	rt2800_rxdcoc_calibration(rt2x00dev);
10419 	rt2800_rxiq_calibration(rt2x00dev);
10420 
10421 	if (!rt2x00_has_cap_external_pa(rt2x00dev) &&
10422 	    !rt2x00_has_cap_external_lna_bg(rt2x00dev))
10423 		return;
10424 
10425 	if (rt2x00_has_cap_external_pa(rt2x00dev)) {
10426 		reg = rt2800_register_read(rt2x00dev, RF_CONTROL3);
10427 		reg |= 0x00000101;
10428 		rt2800_register_write(rt2x00dev, RF_CONTROL3, reg);
10429 
10430 		reg = rt2800_register_read(rt2x00dev, RF_BYPASS3);
10431 		reg |= 0x00000101;
10432 		rt2800_register_write(rt2x00dev, RF_BYPASS3, reg);
10433 	}
10434 
10435 	if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
10436 		rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x66);
10437 		rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x20);
10438 		rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x42);
10439 	}
10440 
10441 	if (rt2x00_has_cap_external_pa(rt2x00dev)) {
10442 		rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0x73);
10443 		rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0x73);
10444 		rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0x73);
10445 		rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
10446 		rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0xc8);
10447 		rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xa4);
10448 		rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x05);
10449 		rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
10450 		rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xc8);
10451 		rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xa4);
10452 		rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x05);
10453 		rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x27);
10454 		rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0xc8);
10455 		rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xa4);
10456 		rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x05);
10457 	}
10458 
10459 	if (rt2x00_has_cap_external_pa(rt2x00dev))
10460 		rt2800_rfcsr_write_dccal(rt2x00dev, 05, 0x00);
10461 
10462 	if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
10463 		rt2800_bbp_write(rt2x00dev, 75, 0x68);
10464 		rt2800_bbp_write(rt2x00dev, 76, 0x4c);
10465 		rt2800_bbp_write(rt2x00dev, 79, 0x1c);
10466 		rt2800_bbp_write(rt2x00dev, 80, 0x0c);
10467 		rt2800_bbp_write(rt2x00dev, 82, 0xb6);
10468 	}
10469 
10470 	if (rt2x00_has_cap_external_pa(rt2x00dev)) {
10471 		rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT, 0x36303636);
10472 		rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6c6c6b6c);
10473 		rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6c6c6b6c);
10474 	}
10475 }
10476 
rt2800_init_rfcsr_6352(struct rt2x00_dev * rt2x00dev)10477 static void rt2800_init_rfcsr_6352(struct rt2x00_dev *rt2x00dev)
10478 {
10479 	/* Initialize RF central register to default value */
10480 	rt2800_rfcsr_write(rt2x00dev, 0, 0x02);
10481 	rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
10482 	rt2800_rfcsr_write(rt2x00dev, 2, 0x33);
10483 	rt2800_rfcsr_write(rt2x00dev, 3, 0xFF);
10484 	rt2800_rfcsr_write(rt2x00dev, 4, 0x0C);
10485 	rt2800_rfcsr_write(rt2x00dev, 5, 0x40);
10486 	rt2800_rfcsr_write(rt2x00dev, 6, 0x00);
10487 	rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
10488 	rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
10489 	rt2800_rfcsr_write(rt2x00dev, 9, 0x00);
10490 	rt2800_rfcsr_write(rt2x00dev, 10, 0x00);
10491 	rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
10492 	rt2800_rfcsr_write(rt2x00dev, 12, rt2x00dev->freq_offset);
10493 	rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
10494 	rt2800_rfcsr_write(rt2x00dev, 14, 0x40);
10495 	rt2800_rfcsr_write(rt2x00dev, 15, 0x22);
10496 	rt2800_rfcsr_write(rt2x00dev, 16, 0x4C);
10497 	rt2800_rfcsr_write(rt2x00dev, 17, 0x00);
10498 	rt2800_rfcsr_write(rt2x00dev, 18, 0x00);
10499 	rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
10500 	rt2800_rfcsr_write(rt2x00dev, 20, 0xA0);
10501 	rt2800_rfcsr_write(rt2x00dev, 21, 0x12);
10502 	rt2800_rfcsr_write(rt2x00dev, 22, 0x07);
10503 	rt2800_rfcsr_write(rt2x00dev, 23, 0x13);
10504 	rt2800_rfcsr_write(rt2x00dev, 24, 0xFE);
10505 	rt2800_rfcsr_write(rt2x00dev, 25, 0x24);
10506 	rt2800_rfcsr_write(rt2x00dev, 26, 0x7A);
10507 	rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
10508 	rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
10509 	rt2800_rfcsr_write(rt2x00dev, 29, 0x05);
10510 	rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
10511 	rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
10512 	rt2800_rfcsr_write(rt2x00dev, 32, 0x00);
10513 	rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
10514 	rt2800_rfcsr_write(rt2x00dev, 34, 0x00);
10515 	rt2800_rfcsr_write(rt2x00dev, 35, 0x00);
10516 	rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
10517 	rt2800_rfcsr_write(rt2x00dev, 37, 0x00);
10518 	rt2800_rfcsr_write(rt2x00dev, 38, 0x00);
10519 	rt2800_rfcsr_write(rt2x00dev, 39, 0x00);
10520 	rt2800_rfcsr_write(rt2x00dev, 40, 0x00);
10521 	rt2800_rfcsr_write(rt2x00dev, 41, 0xD0);
10522 	rt2800_rfcsr_write(rt2x00dev, 42, 0x5B);
10523 	rt2800_rfcsr_write(rt2x00dev, 43, 0x00);
10524 
10525 	rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
10526 	if (rt2800_clk_is_20mhz(rt2x00dev))
10527 		rt2800_rfcsr_write(rt2x00dev, 13, 0x03);
10528 	else
10529 		rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
10530 	rt2800_rfcsr_write(rt2x00dev, 14, 0x7C);
10531 	rt2800_rfcsr_write(rt2x00dev, 16, 0x80);
10532 	rt2800_rfcsr_write(rt2x00dev, 17, 0x99);
10533 	rt2800_rfcsr_write(rt2x00dev, 18, 0x99);
10534 	rt2800_rfcsr_write(rt2x00dev, 19, 0x09);
10535 	rt2800_rfcsr_write(rt2x00dev, 20, 0x50);
10536 	rt2800_rfcsr_write(rt2x00dev, 21, 0xB0);
10537 	rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
10538 	rt2800_rfcsr_write(rt2x00dev, 23, 0x06);
10539 	rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
10540 	rt2800_rfcsr_write(rt2x00dev, 25, 0x00);
10541 	rt2800_rfcsr_write(rt2x00dev, 26, 0x5D);
10542 	rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
10543 	rt2800_rfcsr_write(rt2x00dev, 28, 0x61);
10544 	rt2800_rfcsr_write(rt2x00dev, 29, 0xB5);
10545 	rt2800_rfcsr_write(rt2x00dev, 43, 0x02);
10546 
10547 	rt2800_rfcsr_write(rt2x00dev, 28, 0x62);
10548 	rt2800_rfcsr_write(rt2x00dev, 29, 0xAD);
10549 	rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
10550 
10551 	/* Initialize RF channel register to default value */
10552 	rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x03);
10553 	rt2800_rfcsr_write_chanreg(rt2x00dev, 1, 0x00);
10554 	rt2800_rfcsr_write_chanreg(rt2x00dev, 2, 0x00);
10555 	rt2800_rfcsr_write_chanreg(rt2x00dev, 3, 0x00);
10556 	rt2800_rfcsr_write_chanreg(rt2x00dev, 4, 0x00);
10557 	rt2800_rfcsr_write_chanreg(rt2x00dev, 5, 0x08);
10558 	rt2800_rfcsr_write_chanreg(rt2x00dev, 6, 0x00);
10559 	rt2800_rfcsr_write_chanreg(rt2x00dev, 7, 0x51);
10560 	rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x53);
10561 	rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x16);
10562 	rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x61);
10563 	rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
10564 	rt2800_rfcsr_write_chanreg(rt2x00dev, 12, 0x22);
10565 	rt2800_rfcsr_write_chanreg(rt2x00dev, 13, 0x3D);
10566 	rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
10567 	rt2800_rfcsr_write_chanreg(rt2x00dev, 15, 0x13);
10568 	rt2800_rfcsr_write_chanreg(rt2x00dev, 16, 0x22);
10569 	rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x27);
10570 	rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x02);
10571 	rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
10572 	rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x01);
10573 	rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x52);
10574 	rt2800_rfcsr_write_chanreg(rt2x00dev, 22, 0x80);
10575 	rt2800_rfcsr_write_chanreg(rt2x00dev, 23, 0xB3);
10576 	rt2800_rfcsr_write_chanreg(rt2x00dev, 24, 0x00);
10577 	rt2800_rfcsr_write_chanreg(rt2x00dev, 25, 0x00);
10578 	rt2800_rfcsr_write_chanreg(rt2x00dev, 26, 0x00);
10579 	rt2800_rfcsr_write_chanreg(rt2x00dev, 27, 0x00);
10580 	rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x5C);
10581 	rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0x6B);
10582 	rt2800_rfcsr_write_chanreg(rt2x00dev, 30, 0x6B);
10583 	rt2800_rfcsr_write_chanreg(rt2x00dev, 31, 0x31);
10584 	rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x5D);
10585 	rt2800_rfcsr_write_chanreg(rt2x00dev, 33, 0x00);
10586 	rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xE6);
10587 	rt2800_rfcsr_write_chanreg(rt2x00dev, 35, 0x55);
10588 	rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x00);
10589 	rt2800_rfcsr_write_chanreg(rt2x00dev, 37, 0xBB);
10590 	rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB3);
10591 	rt2800_rfcsr_write_chanreg(rt2x00dev, 39, 0xB3);
10592 	rt2800_rfcsr_write_chanreg(rt2x00dev, 40, 0x03);
10593 	rt2800_rfcsr_write_chanreg(rt2x00dev, 41, 0x00);
10594 	rt2800_rfcsr_write_chanreg(rt2x00dev, 42, 0x00);
10595 	rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xB3);
10596 	rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xD3);
10597 	rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
10598 	rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x07);
10599 	rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x68);
10600 	rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xEF);
10601 	rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1C);
10602 	rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x07);
10603 	rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xA8);
10604 	rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0x85);
10605 	rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x10);
10606 	rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x07);
10607 	rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6A);
10608 	rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0x85);
10609 	rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x10);
10610 	rt2800_rfcsr_write_chanreg(rt2x00dev, 62, 0x1C);
10611 	rt2800_rfcsr_write_chanreg(rt2x00dev, 63, 0x00);
10612 
10613 	rt2800_rfcsr_write_bank(rt2x00dev, 6, 45, 0xC5);
10614 
10615 	rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47);
10616 	rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71);
10617 	rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x33);
10618 	rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x0E);
10619 	rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23);
10620 	rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA4);
10621 	rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x02);
10622 	rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x12);
10623 	rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x1C);
10624 	rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0xEB);
10625 	rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x7D);
10626 	rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xD6);
10627 	rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x08);
10628 	rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB4);
10629 	rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
10630 	rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3);
10631 	rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
10632 	rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
10633 	rt2800_rfcsr_write_bank(rt2x00dev, 4, 47, 0x67);
10634 	rt2800_rfcsr_write_bank(rt2x00dev, 6, 47, 0x69);
10635 	rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFF);
10636 	rt2800_rfcsr_write_bank(rt2x00dev, 4, 54, 0x27);
10637 	rt2800_rfcsr_write_bank(rt2x00dev, 6, 54, 0x20);
10638 	rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
10639 	rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF);
10640 	rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C);
10641 	rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20);
10642 	rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
10643 	rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7);
10644 	rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09);
10645 
10646 	rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51);
10647 	rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
10648 	rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
10649 	rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C);
10650 	rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64);
10651 	rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51);
10652 	rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36);
10653 	rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
10654 	rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);
10655 
10656 	rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C);
10657 	rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC);
10658 	rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F);
10659 	rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
10660 	rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
10661 	rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
10662 
10663 	/* Initialize RF channel register for DRQFN */
10664 	rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
10665 	rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3);
10666 	rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5);
10667 	rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28);
10668 	rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68);
10669 	rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7);
10670 	rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02);
10671 	rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7);
10672 
10673 	/* Initialize RF DC calibration register to default value */
10674 	rt2800_rfcsr_write_dccal(rt2x00dev, 0, 0x47);
10675 	rt2800_rfcsr_write_dccal(rt2x00dev, 1, 0x00);
10676 	rt2800_rfcsr_write_dccal(rt2x00dev, 2, 0x00);
10677 	rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x00);
10678 	rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x00);
10679 	rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
10680 	rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10);
10681 	rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10);
10682 	rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04);
10683 	rt2800_rfcsr_write_dccal(rt2x00dev, 9, 0x00);
10684 	rt2800_rfcsr_write_dccal(rt2x00dev, 10, 0x07);
10685 	rt2800_rfcsr_write_dccal(rt2x00dev, 11, 0x01);
10686 	rt2800_rfcsr_write_dccal(rt2x00dev, 12, 0x07);
10687 	rt2800_rfcsr_write_dccal(rt2x00dev, 13, 0x07);
10688 	rt2800_rfcsr_write_dccal(rt2x00dev, 14, 0x07);
10689 	rt2800_rfcsr_write_dccal(rt2x00dev, 15, 0x20);
10690 	rt2800_rfcsr_write_dccal(rt2x00dev, 16, 0x22);
10691 	rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x00);
10692 	rt2800_rfcsr_write_dccal(rt2x00dev, 18, 0x00);
10693 	rt2800_rfcsr_write_dccal(rt2x00dev, 19, 0x00);
10694 	rt2800_rfcsr_write_dccal(rt2x00dev, 20, 0x00);
10695 	rt2800_rfcsr_write_dccal(rt2x00dev, 21, 0xF1);
10696 	rt2800_rfcsr_write_dccal(rt2x00dev, 22, 0x11);
10697 	rt2800_rfcsr_write_dccal(rt2x00dev, 23, 0x02);
10698 	rt2800_rfcsr_write_dccal(rt2x00dev, 24, 0x41);
10699 	rt2800_rfcsr_write_dccal(rt2x00dev, 25, 0x20);
10700 	rt2800_rfcsr_write_dccal(rt2x00dev, 26, 0x00);
10701 	rt2800_rfcsr_write_dccal(rt2x00dev, 27, 0xD7);
10702 	rt2800_rfcsr_write_dccal(rt2x00dev, 28, 0xA2);
10703 	rt2800_rfcsr_write_dccal(rt2x00dev, 29, 0x20);
10704 	rt2800_rfcsr_write_dccal(rt2x00dev, 30, 0x49);
10705 	rt2800_rfcsr_write_dccal(rt2x00dev, 31, 0x20);
10706 	rt2800_rfcsr_write_dccal(rt2x00dev, 32, 0x04);
10707 	rt2800_rfcsr_write_dccal(rt2x00dev, 33, 0xF1);
10708 	rt2800_rfcsr_write_dccal(rt2x00dev, 34, 0xA1);
10709 	rt2800_rfcsr_write_dccal(rt2x00dev, 35, 0x01);
10710 	rt2800_rfcsr_write_dccal(rt2x00dev, 41, 0x00);
10711 	rt2800_rfcsr_write_dccal(rt2x00dev, 42, 0x00);
10712 	rt2800_rfcsr_write_dccal(rt2x00dev, 43, 0x00);
10713 	rt2800_rfcsr_write_dccal(rt2x00dev, 44, 0x00);
10714 	rt2800_rfcsr_write_dccal(rt2x00dev, 45, 0x00);
10715 	rt2800_rfcsr_write_dccal(rt2x00dev, 46, 0x00);
10716 	rt2800_rfcsr_write_dccal(rt2x00dev, 47, 0x3E);
10717 	rt2800_rfcsr_write_dccal(rt2x00dev, 48, 0x3D);
10718 	rt2800_rfcsr_write_dccal(rt2x00dev, 49, 0x3E);
10719 	rt2800_rfcsr_write_dccal(rt2x00dev, 50, 0x3D);
10720 	rt2800_rfcsr_write_dccal(rt2x00dev, 51, 0x3E);
10721 	rt2800_rfcsr_write_dccal(rt2x00dev, 52, 0x3D);
10722 	rt2800_rfcsr_write_dccal(rt2x00dev, 53, 0x00);
10723 	rt2800_rfcsr_write_dccal(rt2x00dev, 54, 0x00);
10724 	rt2800_rfcsr_write_dccal(rt2x00dev, 55, 0x00);
10725 	rt2800_rfcsr_write_dccal(rt2x00dev, 56, 0x00);
10726 	rt2800_rfcsr_write_dccal(rt2x00dev, 57, 0x00);
10727 	rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10);
10728 	rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10);
10729 	rt2800_rfcsr_write_dccal(rt2x00dev, 60, 0x0A);
10730 	rt2800_rfcsr_write_dccal(rt2x00dev, 61, 0x00);
10731 	rt2800_rfcsr_write_dccal(rt2x00dev, 62, 0x00);
10732 	rt2800_rfcsr_write_dccal(rt2x00dev, 63, 0x00);
10733 
10734 	rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x08);
10735 	rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x04);
10736 	rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x20);
10737 
10738 	rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
10739 	rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C);
10740 
10741 	/* Do calibration and init PA/LNA */
10742 	rt2800_calibration_rt6352(rt2x00dev);
10743 }
10744 
rt2800_init_rfcsr(struct rt2x00_dev * rt2x00dev)10745 static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
10746 {
10747 	if (rt2800_is_305x_soc(rt2x00dev)) {
10748 		rt2800_init_rfcsr_305x_soc(rt2x00dev);
10749 		return;
10750 	}
10751 
10752 	switch (rt2x00dev->chip.rt) {
10753 	case RT3070:
10754 	case RT3071:
10755 	case RT3090:
10756 		rt2800_init_rfcsr_30xx(rt2x00dev);
10757 		break;
10758 	case RT3290:
10759 		rt2800_init_rfcsr_3290(rt2x00dev);
10760 		break;
10761 	case RT3352:
10762 		rt2800_init_rfcsr_3352(rt2x00dev);
10763 		break;
10764 	case RT3390:
10765 		rt2800_init_rfcsr_3390(rt2x00dev);
10766 		break;
10767 	case RT3883:
10768 		rt2800_init_rfcsr_3883(rt2x00dev);
10769 		break;
10770 	case RT3572:
10771 		rt2800_init_rfcsr_3572(rt2x00dev);
10772 		break;
10773 	case RT3593:
10774 		rt2800_init_rfcsr_3593(rt2x00dev);
10775 		break;
10776 	case RT5350:
10777 		rt2800_init_rfcsr_5350(rt2x00dev);
10778 		break;
10779 	case RT5390:
10780 		rt2800_init_rfcsr_5390(rt2x00dev);
10781 		break;
10782 	case RT5392:
10783 		rt2800_init_rfcsr_5392(rt2x00dev);
10784 		break;
10785 	case RT5592:
10786 		rt2800_init_rfcsr_5592(rt2x00dev);
10787 		break;
10788 	case RT6352:
10789 		rt2800_init_rfcsr_6352(rt2x00dev);
10790 		break;
10791 	}
10792 }
10793 
rt2800_enable_radio(struct rt2x00_dev * rt2x00dev)10794 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
10795 {
10796 	u32 reg;
10797 	u16 word;
10798 
10799 	/*
10800 	 * Initialize MAC registers.
10801 	 */
10802 	if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
10803 		     rt2800_init_registers(rt2x00dev)))
10804 		return -EIO;
10805 
10806 	/*
10807 	 * Wait BBP/RF to wake up.
10808 	 */
10809 	if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY)))
10810 		return -EIO;
10811 
10812 	/*
10813 	 * Send signal during boot time to initialize firmware.
10814 	 */
10815 	rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
10816 	rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
10817 	if (rt2x00_is_usb(rt2x00dev))
10818 		rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
10819 	rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
10820 	msleep(1);
10821 
10822 	/*
10823 	 * Make sure BBP is up and running.
10824 	 */
10825 	if (unlikely(rt2800_wait_bbp_ready(rt2x00dev)))
10826 		return -EIO;
10827 
10828 	/*
10829 	 * Initialize BBP/RF registers.
10830 	 */
10831 	rt2800_init_bbp(rt2x00dev);
10832 	rt2800_init_rfcsr(rt2x00dev);
10833 
10834 	if (rt2x00_is_usb(rt2x00dev) &&
10835 	    (rt2x00_rt(rt2x00dev, RT3070) ||
10836 	     rt2x00_rt(rt2x00dev, RT3071) ||
10837 	     rt2x00_rt(rt2x00dev, RT3572))) {
10838 		udelay(200);
10839 		rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
10840 		udelay(10);
10841 	}
10842 
10843 	/*
10844 	 * Enable RX.
10845 	 */
10846 	reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
10847 	rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
10848 	rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
10849 	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
10850 
10851 	udelay(50);
10852 
10853 	reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
10854 	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
10855 	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
10856 	rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
10857 	rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
10858 
10859 	reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
10860 	rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
10861 	rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
10862 	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
10863 
10864 	/*
10865 	 * Initialize LED control
10866 	 */
10867 	word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF);
10868 	rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
10869 			   word & 0xff, (word >> 8) & 0xff);
10870 
10871 	word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF);
10872 	rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
10873 			   word & 0xff, (word >> 8) & 0xff);
10874 
10875 	word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY);
10876 	rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
10877 			   word & 0xff, (word >> 8) & 0xff);
10878 
10879 	return 0;
10880 }
10881 EXPORT_SYMBOL_GPL(rt2800_enable_radio);
10882 
rt2800_disable_radio(struct rt2x00_dev * rt2x00dev)10883 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
10884 {
10885 	u32 reg;
10886 
10887 	rt2800_disable_wpdma(rt2x00dev);
10888 
10889 	/* Wait for DMA, ignore error */
10890 	rt2800_wait_wpdma_ready(rt2x00dev);
10891 
10892 	reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
10893 	rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
10894 	rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
10895 	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
10896 }
10897 EXPORT_SYMBOL_GPL(rt2800_disable_radio);
10898 
rt2800_efuse_detect(struct rt2x00_dev * rt2x00dev)10899 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
10900 {
10901 	u32 reg;
10902 	u16 efuse_ctrl_reg;
10903 
10904 	if (rt2x00_rt(rt2x00dev, RT3290))
10905 		efuse_ctrl_reg = EFUSE_CTRL_3290;
10906 	else
10907 		efuse_ctrl_reg = EFUSE_CTRL;
10908 
10909 	reg = rt2800_register_read(rt2x00dev, efuse_ctrl_reg);
10910 	return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
10911 }
10912 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
10913 
rt2800_efuse_read(struct rt2x00_dev * rt2x00dev,unsigned int i)10914 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
10915 {
10916 	u32 reg;
10917 	u16 efuse_ctrl_reg;
10918 	u16 efuse_data0_reg;
10919 	u16 efuse_data1_reg;
10920 	u16 efuse_data2_reg;
10921 	u16 efuse_data3_reg;
10922 
10923 	if (rt2x00_rt(rt2x00dev, RT3290)) {
10924 		efuse_ctrl_reg = EFUSE_CTRL_3290;
10925 		efuse_data0_reg = EFUSE_DATA0_3290;
10926 		efuse_data1_reg = EFUSE_DATA1_3290;
10927 		efuse_data2_reg = EFUSE_DATA2_3290;
10928 		efuse_data3_reg = EFUSE_DATA3_3290;
10929 	} else {
10930 		efuse_ctrl_reg = EFUSE_CTRL;
10931 		efuse_data0_reg = EFUSE_DATA0;
10932 		efuse_data1_reg = EFUSE_DATA1;
10933 		efuse_data2_reg = EFUSE_DATA2;
10934 		efuse_data3_reg = EFUSE_DATA3;
10935 	}
10936 	mutex_lock(&rt2x00dev->csr_mutex);
10937 
10938 	reg = rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg);
10939 	rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
10940 	rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
10941 	rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
10942 	rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
10943 
10944 	/* Wait until the EEPROM has been loaded */
10945 	rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, &reg);
10946 	/* Apparently the data is read from end to start */
10947 	reg = rt2800_register_read_lock(rt2x00dev, efuse_data3_reg);
10948 	/* The returned value is in CPU order, but eeprom is le */
10949 	*(__le32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
10950 	reg = rt2800_register_read_lock(rt2x00dev, efuse_data2_reg);
10951 	*(__le32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
10952 	reg = rt2800_register_read_lock(rt2x00dev, efuse_data1_reg);
10953 	*(__le32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
10954 	reg = rt2800_register_read_lock(rt2x00dev, efuse_data0_reg);
10955 	*(__le32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
10956 
10957 	mutex_unlock(&rt2x00dev->csr_mutex);
10958 }
10959 
rt2800_read_eeprom_efuse(struct rt2x00_dev * rt2x00dev)10960 int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
10961 {
10962 	unsigned int i;
10963 
10964 	for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
10965 		rt2800_efuse_read(rt2x00dev, i);
10966 
10967 	return 0;
10968 }
10969 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
10970 
rt2800_get_txmixer_gain_24g(struct rt2x00_dev * rt2x00dev)10971 static u8 rt2800_get_txmixer_gain_24g(struct rt2x00_dev *rt2x00dev)
10972 {
10973 	u16 word;
10974 
10975 	if (rt2x00_rt(rt2x00dev, RT3593) ||
10976 	    rt2x00_rt(rt2x00dev, RT3883))
10977 		return 0;
10978 
10979 	word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG);
10980 	if ((word & 0x00ff) != 0x00ff)
10981 		return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
10982 
10983 	return 0;
10984 }
10985 
rt2800_get_txmixer_gain_5g(struct rt2x00_dev * rt2x00dev)10986 static u8 rt2800_get_txmixer_gain_5g(struct rt2x00_dev *rt2x00dev)
10987 {
10988 	u16 word;
10989 
10990 	if (rt2x00_rt(rt2x00dev, RT3593) ||
10991 	    rt2x00_rt(rt2x00dev, RT3883))
10992 		return 0;
10993 
10994 	word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A);
10995 	if ((word & 0x00ff) != 0x00ff)
10996 		return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
10997 
10998 	return 0;
10999 }
11000 
rt2800_validate_eeprom(struct rt2x00_dev * rt2x00dev)11001 static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
11002 {
11003 	struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
11004 	u16 word;
11005 	u8 *mac;
11006 	u8 default_lna_gain;
11007 	int retval;
11008 
11009 	/*
11010 	 * Read the EEPROM.
11011 	 */
11012 	retval = rt2800_read_eeprom(rt2x00dev);
11013 	if (retval)
11014 		return retval;
11015 
11016 	/*
11017 	 * Start validation of the data that has been read.
11018 	 */
11019 	mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
11020 	rt2x00lib_set_mac_address(rt2x00dev, mac);
11021 
11022 	word = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
11023 	if (word == 0xffff) {
11024 		rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
11025 		rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
11026 		rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
11027 		rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
11028 		rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
11029 	} else if (rt2x00_rt(rt2x00dev, RT2860) ||
11030 		   rt2x00_rt(rt2x00dev, RT2872)) {
11031 		/*
11032 		 * There is a max of 2 RX streams for RT28x0 series
11033 		 */
11034 		if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
11035 			rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
11036 		rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
11037 	}
11038 
11039 	word = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
11040 	if (word == 0xffff) {
11041 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
11042 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
11043 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
11044 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
11045 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
11046 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
11047 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
11048 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
11049 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
11050 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
11051 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
11052 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
11053 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
11054 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
11055 		rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
11056 		rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
11057 		rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
11058 	}
11059 
11060 	word = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ);
11061 	if ((word & 0x00ff) == 0x00ff) {
11062 		rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
11063 		rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
11064 		rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word);
11065 	}
11066 	if ((word & 0xff00) == 0xff00) {
11067 		rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
11068 				   LED_MODE_TXRX_ACTIVITY);
11069 		rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
11070 		rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
11071 		rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
11072 		rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
11073 		rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
11074 		rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word);
11075 	}
11076 
11077 	/*
11078 	 * During the LNA validation we are going to use
11079 	 * lna0 as correct value. Note that EEPROM_LNA
11080 	 * is never validated.
11081 	 */
11082 	word = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA);
11083 	default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
11084 
11085 	word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG);
11086 	if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
11087 		rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
11088 	if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
11089 		rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
11090 	rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
11091 
11092 	drv_data->txmixer_gain_24g = rt2800_get_txmixer_gain_24g(rt2x00dev);
11093 
11094 	word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2);
11095 	if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
11096 		rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
11097 	if (!rt2x00_rt(rt2x00dev, RT3593) &&
11098 	    !rt2x00_rt(rt2x00dev, RT3883)) {
11099 		if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
11100 		    rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
11101 			rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
11102 					   default_lna_gain);
11103 	}
11104 	rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
11105 
11106 	drv_data->txmixer_gain_5g = rt2800_get_txmixer_gain_5g(rt2x00dev);
11107 
11108 	word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A);
11109 	if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
11110 		rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
11111 	if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
11112 		rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
11113 	rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
11114 
11115 	word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2);
11116 	if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
11117 		rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
11118 	if (!rt2x00_rt(rt2x00dev, RT3593) &&
11119 	    !rt2x00_rt(rt2x00dev, RT3883)) {
11120 		if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
11121 		    rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
11122 			rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
11123 					   default_lna_gain);
11124 	}
11125 	rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
11126 
11127 	if (rt2x00_rt(rt2x00dev, RT3593) ||
11128 	    rt2x00_rt(rt2x00dev, RT3883)) {
11129 		word = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2);
11130 		if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0x00 ||
11131 		    rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0xff)
11132 			rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
11133 					   default_lna_gain);
11134 		if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0x00 ||
11135 		    rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0xff)
11136 			rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
11137 					   default_lna_gain);
11138 		rt2800_eeprom_write(rt2x00dev, EEPROM_EXT_LNA2, word);
11139 	}
11140 
11141 	return 0;
11142 }
11143 
rt2800_init_eeprom(struct rt2x00_dev * rt2x00dev)11144 static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
11145 {
11146 	u16 value;
11147 	u16 eeprom;
11148 	u16 rf;
11149 
11150 	/*
11151 	 * Read EEPROM word for configuration.
11152 	 */
11153 	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
11154 
11155 	/*
11156 	 * Identify RF chipset by EEPROM value
11157 	 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
11158 	 * RT53xx: defined in "EEPROM_CHIP_ID" field
11159 	 */
11160 	if (rt2x00_rt(rt2x00dev, RT3290) ||
11161 	    rt2x00_rt(rt2x00dev, RT5390) ||
11162 	    rt2x00_rt(rt2x00dev, RT5392) ||
11163 	    rt2x00_rt(rt2x00dev, RT6352))
11164 		rf = rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID);
11165 	else if (rt2x00_rt(rt2x00dev, RT3352))
11166 		rf = RF3322;
11167 	else if (rt2x00_rt(rt2x00dev, RT3883))
11168 		rf = RF3853;
11169 	else if (rt2x00_rt(rt2x00dev, RT5350))
11170 		rf = RF5350;
11171 	else if (rt2x00_rt(rt2x00dev, RT5592))
11172 		rf = RF5592;
11173 	else
11174 		rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
11175 
11176 	switch (rf) {
11177 	case RF2820:
11178 	case RF2850:
11179 	case RF2720:
11180 	case RF2750:
11181 	case RF3020:
11182 	case RF2020:
11183 	case RF3021:
11184 	case RF3022:
11185 	case RF3052:
11186 	case RF3053:
11187 	case RF3070:
11188 	case RF3290:
11189 	case RF3320:
11190 	case RF3322:
11191 	case RF3853:
11192 	case RF5350:
11193 	case RF5360:
11194 	case RF5362:
11195 	case RF5370:
11196 	case RF5372:
11197 	case RF5390:
11198 	case RF5392:
11199 	case RF5592:
11200 	case RF7620:
11201 		break;
11202 	default:
11203 		rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n",
11204 			   rf);
11205 		return -ENODEV;
11206 	}
11207 
11208 	rt2x00_set_rf(rt2x00dev, rf);
11209 
11210 	/*
11211 	 * Identify default antenna configuration.
11212 	 */
11213 	rt2x00dev->default_ant.tx_chain_num =
11214 	    rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
11215 	rt2x00dev->default_ant.rx_chain_num =
11216 	    rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
11217 
11218 	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
11219 
11220 	if (rt2x00_rt(rt2x00dev, RT3070) ||
11221 	    rt2x00_rt(rt2x00dev, RT3090) ||
11222 	    rt2x00_rt(rt2x00dev, RT3352) ||
11223 	    rt2x00_rt(rt2x00dev, RT3390)) {
11224 		value = rt2x00_get_field16(eeprom,
11225 				EEPROM_NIC_CONF1_ANT_DIVERSITY);
11226 		switch (value) {
11227 		case 0:
11228 		case 1:
11229 		case 2:
11230 			rt2x00dev->default_ant.tx = ANTENNA_A;
11231 			rt2x00dev->default_ant.rx = ANTENNA_A;
11232 			break;
11233 		case 3:
11234 			rt2x00dev->default_ant.tx = ANTENNA_A;
11235 			rt2x00dev->default_ant.rx = ANTENNA_B;
11236 			break;
11237 		}
11238 	} else {
11239 		rt2x00dev->default_ant.tx = ANTENNA_A;
11240 		rt2x00dev->default_ant.rx = ANTENNA_A;
11241 	}
11242 
11243 	/* These chips have hardware RX antenna diversity */
11244 	if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R) ||
11245 	    rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5370G)) {
11246 		rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
11247 		rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
11248 	}
11249 
11250 	/*
11251 	 * Determine external LNA informations.
11252 	 */
11253 	if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
11254 		__set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
11255 	if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
11256 		__set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
11257 
11258 	/*
11259 	 * Detect if this device has an hardware controlled radio.
11260 	 */
11261 	if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
11262 		__set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
11263 
11264 	/*
11265 	 * Detect if this device has Bluetooth co-existence.
11266 	 */
11267 	if (!rt2x00_rt(rt2x00dev, RT3352) &&
11268 	    rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
11269 		__set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
11270 
11271 	/*
11272 	 * Read frequency offset and RF programming sequence.
11273 	 */
11274 	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ);
11275 	rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
11276 
11277 	/*
11278 	 * Store led settings, for correct led behaviour.
11279 	 */
11280 #ifdef CONFIG_RT2X00_LIB_LEDS
11281 	rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
11282 	rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
11283 	rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
11284 
11285 	rt2x00dev->led_mcu_reg = eeprom;
11286 #endif /* CONFIG_RT2X00_LIB_LEDS */
11287 
11288 	/*
11289 	 * Check if support EIRP tx power limit feature.
11290 	 */
11291 	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER);
11292 
11293 	if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
11294 					EIRP_MAX_TX_POWER_LIMIT)
11295 		__set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
11296 
11297 	/*
11298 	 * Detect if device uses internal or external PA
11299 	 */
11300 	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
11301 
11302 	if (rt2x00_rt(rt2x00dev, RT3352) ||
11303 	    rt2x00_rt(rt2x00dev, RT6352)) {
11304 		if (rt2x00_get_field16(eeprom,
11305 		    EEPROM_NIC_CONF1_EXTERNAL_TX0_PA_3352))
11306 		    __set_bit(CAPABILITY_EXTERNAL_PA_TX0,
11307 			      &rt2x00dev->cap_flags);
11308 		if (rt2x00_get_field16(eeprom,
11309 		    EEPROM_NIC_CONF1_EXTERNAL_TX1_PA_3352))
11310 		    __set_bit(CAPABILITY_EXTERNAL_PA_TX1,
11311 			      &rt2x00dev->cap_flags);
11312 	}
11313 
11314 	eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF2);
11315 
11316 	if (rt2x00_rt(rt2x00dev, RT6352) && eeprom != 0 && eeprom != 0xffff) {
11317 		if (!rt2x00_get_field16(eeprom,
11318 					EEPROM_NIC_CONF2_EXTERNAL_PA)) {
11319 			__clear_bit(CAPABILITY_EXTERNAL_PA_TX0,
11320 				    &rt2x00dev->cap_flags);
11321 			__clear_bit(CAPABILITY_EXTERNAL_PA_TX1,
11322 				    &rt2x00dev->cap_flags);
11323 		}
11324 	}
11325 
11326 	return 0;
11327 }
11328 
11329 /*
11330  * RF value list for rt28xx
11331  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
11332  */
11333 static const struct rf_channel rf_vals[] = {
11334 	{ 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
11335 	{ 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
11336 	{ 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
11337 	{ 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
11338 	{ 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
11339 	{ 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
11340 	{ 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
11341 	{ 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
11342 	{ 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
11343 	{ 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
11344 	{ 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
11345 	{ 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
11346 	{ 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
11347 	{ 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
11348 
11349 	/* 802.11 UNI / HyperLan 2 */
11350 	{ 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
11351 	{ 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
11352 	{ 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
11353 	{ 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
11354 	{ 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
11355 	{ 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
11356 	{ 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
11357 	{ 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
11358 	{ 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
11359 	{ 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
11360 	{ 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
11361 	{ 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
11362 
11363 	/* 802.11 HyperLan 2 */
11364 	{ 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
11365 	{ 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
11366 	{ 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
11367 	{ 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
11368 	{ 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
11369 	{ 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
11370 	{ 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
11371 	{ 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
11372 	{ 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
11373 	{ 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
11374 	{ 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
11375 	{ 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
11376 	{ 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
11377 	{ 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
11378 	{ 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
11379 	{ 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
11380 
11381 	/* 802.11 UNII */
11382 	{ 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
11383 	{ 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
11384 	{ 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
11385 	{ 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
11386 	{ 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
11387 	{ 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
11388 	{ 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
11389 	{ 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
11390 	{ 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
11391 	{ 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
11392 	{ 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
11393 
11394 	/* 802.11 Japan */
11395 	{ 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
11396 	{ 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
11397 	{ 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
11398 	{ 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
11399 	{ 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
11400 	{ 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
11401 	{ 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
11402 };
11403 
11404 /*
11405  * RF value list for rt3xxx
11406  * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052 & RF3053)
11407  */
11408 static const struct rf_channel rf_vals_3x[] = {
11409 	{1,  241, 2, 2 },
11410 	{2,  241, 2, 7 },
11411 	{3,  242, 2, 2 },
11412 	{4,  242, 2, 7 },
11413 	{5,  243, 2, 2 },
11414 	{6,  243, 2, 7 },
11415 	{7,  244, 2, 2 },
11416 	{8,  244, 2, 7 },
11417 	{9,  245, 2, 2 },
11418 	{10, 245, 2, 7 },
11419 	{11, 246, 2, 2 },
11420 	{12, 246, 2, 7 },
11421 	{13, 247, 2, 2 },
11422 	{14, 248, 2, 4 },
11423 
11424 	/* 802.11 UNI / HyperLan 2 */
11425 	{36, 0x56, 0, 4},
11426 	{38, 0x56, 0, 6},
11427 	{40, 0x56, 0, 8},
11428 	{44, 0x57, 0, 0},
11429 	{46, 0x57, 0, 2},
11430 	{48, 0x57, 0, 4},
11431 	{52, 0x57, 0, 8},
11432 	{54, 0x57, 0, 10},
11433 	{56, 0x58, 0, 0},
11434 	{60, 0x58, 0, 4},
11435 	{62, 0x58, 0, 6},
11436 	{64, 0x58, 0, 8},
11437 
11438 	/* 802.11 HyperLan 2 */
11439 	{100, 0x5b, 0, 8},
11440 	{102, 0x5b, 0, 10},
11441 	{104, 0x5c, 0, 0},
11442 	{108, 0x5c, 0, 4},
11443 	{110, 0x5c, 0, 6},
11444 	{112, 0x5c, 0, 8},
11445 	{116, 0x5d, 0, 0},
11446 	{118, 0x5d, 0, 2},
11447 	{120, 0x5d, 0, 4},
11448 	{124, 0x5d, 0, 8},
11449 	{126, 0x5d, 0, 10},
11450 	{128, 0x5e, 0, 0},
11451 	{132, 0x5e, 0, 4},
11452 	{134, 0x5e, 0, 6},
11453 	{136, 0x5e, 0, 8},
11454 	{140, 0x5f, 0, 0},
11455 
11456 	/* 802.11 UNII */
11457 	{149, 0x5f, 0, 9},
11458 	{151, 0x5f, 0, 11},
11459 	{153, 0x60, 0, 1},
11460 	{157, 0x60, 0, 5},
11461 	{159, 0x60, 0, 7},
11462 	{161, 0x60, 0, 9},
11463 	{165, 0x61, 0, 1},
11464 	{167, 0x61, 0, 3},
11465 	{169, 0x61, 0, 5},
11466 	{171, 0x61, 0, 7},
11467 	{173, 0x61, 0, 9},
11468 };
11469 
11470 /*
11471  * RF value list for rt3xxx with Xtal20MHz
11472  * Supports: 2.4 GHz (all) (RF3322)
11473  */
11474 static const struct rf_channel rf_vals_3x_xtal20[] = {
11475 	{1,    0xE2,	 2,  0x14},
11476 	{2,    0xE3,	 2,  0x14},
11477 	{3,    0xE4,	 2,  0x14},
11478 	{4,    0xE5,	 2,  0x14},
11479 	{5,    0xE6,	 2,  0x14},
11480 	{6,    0xE7,	 2,  0x14},
11481 	{7,    0xE8,	 2,  0x14},
11482 	{8,    0xE9,	 2,  0x14},
11483 	{9,    0xEA,	 2,  0x14},
11484 	{10,   0xEB,	 2,  0x14},
11485 	{11,   0xEC,	 2,  0x14},
11486 	{12,   0xED,	 2,  0x14},
11487 	{13,   0xEE,	 2,  0x14},
11488 	{14,   0xF0,	 2,  0x18},
11489 };
11490 
11491 static const struct rf_channel rf_vals_3853[] = {
11492 	{1,  241, 6, 2},
11493 	{2,  241, 6, 7},
11494 	{3,  242, 6, 2},
11495 	{4,  242, 6, 7},
11496 	{5,  243, 6, 2},
11497 	{6,  243, 6, 7},
11498 	{7,  244, 6, 2},
11499 	{8,  244, 6, 7},
11500 	{9,  245, 6, 2},
11501 	{10, 245, 6, 7},
11502 	{11, 246, 6, 2},
11503 	{12, 246, 6, 7},
11504 	{13, 247, 6, 2},
11505 	{14, 248, 6, 4},
11506 
11507 	{36, 0x56, 8, 4},
11508 	{38, 0x56, 8, 6},
11509 	{40, 0x56, 8, 8},
11510 	{44, 0x57, 8, 0},
11511 	{46, 0x57, 8, 2},
11512 	{48, 0x57, 8, 4},
11513 	{52, 0x57, 8, 8},
11514 	{54, 0x57, 8, 10},
11515 	{56, 0x58, 8, 0},
11516 	{60, 0x58, 8, 4},
11517 	{62, 0x58, 8, 6},
11518 	{64, 0x58, 8, 8},
11519 
11520 	{100, 0x5b, 8, 8},
11521 	{102, 0x5b, 8, 10},
11522 	{104, 0x5c, 8, 0},
11523 	{108, 0x5c, 8, 4},
11524 	{110, 0x5c, 8, 6},
11525 	{112, 0x5c, 8, 8},
11526 	{114, 0x5c, 8, 10},
11527 	{116, 0x5d, 8, 0},
11528 	{118, 0x5d, 8, 2},
11529 	{120, 0x5d, 8, 4},
11530 	{124, 0x5d, 8, 8},
11531 	{126, 0x5d, 8, 10},
11532 	{128, 0x5e, 8, 0},
11533 	{132, 0x5e, 8, 4},
11534 	{134, 0x5e, 8, 6},
11535 	{136, 0x5e, 8, 8},
11536 	{140, 0x5f, 8, 0},
11537 
11538 	{149, 0x5f, 8, 9},
11539 	{151, 0x5f, 8, 11},
11540 	{153, 0x60, 8, 1},
11541 	{157, 0x60, 8, 5},
11542 	{159, 0x60, 8, 7},
11543 	{161, 0x60, 8, 9},
11544 	{165, 0x61, 8, 1},
11545 	{167, 0x61, 8, 3},
11546 	{169, 0x61, 8, 5},
11547 	{171, 0x61, 8, 7},
11548 	{173, 0x61, 8, 9},
11549 };
11550 
11551 static const struct rf_channel rf_vals_5592_xtal20[] = {
11552 	/* Channel, N, K, mod, R */
11553 	{1, 482, 4, 10, 3},
11554 	{2, 483, 4, 10, 3},
11555 	{3, 484, 4, 10, 3},
11556 	{4, 485, 4, 10, 3},
11557 	{5, 486, 4, 10, 3},
11558 	{6, 487, 4, 10, 3},
11559 	{7, 488, 4, 10, 3},
11560 	{8, 489, 4, 10, 3},
11561 	{9, 490, 4, 10, 3},
11562 	{10, 491, 4, 10, 3},
11563 	{11, 492, 4, 10, 3},
11564 	{12, 493, 4, 10, 3},
11565 	{13, 494, 4, 10, 3},
11566 	{14, 496, 8, 10, 3},
11567 	{36, 172, 8, 12, 1},
11568 	{38, 173, 0, 12, 1},
11569 	{40, 173, 4, 12, 1},
11570 	{42, 173, 8, 12, 1},
11571 	{44, 174, 0, 12, 1},
11572 	{46, 174, 4, 12, 1},
11573 	{48, 174, 8, 12, 1},
11574 	{50, 175, 0, 12, 1},
11575 	{52, 175, 4, 12, 1},
11576 	{54, 175, 8, 12, 1},
11577 	{56, 176, 0, 12, 1},
11578 	{58, 176, 4, 12, 1},
11579 	{60, 176, 8, 12, 1},
11580 	{62, 177, 0, 12, 1},
11581 	{64, 177, 4, 12, 1},
11582 	{100, 183, 4, 12, 1},
11583 	{102, 183, 8, 12, 1},
11584 	{104, 184, 0, 12, 1},
11585 	{106, 184, 4, 12, 1},
11586 	{108, 184, 8, 12, 1},
11587 	{110, 185, 0, 12, 1},
11588 	{112, 185, 4, 12, 1},
11589 	{114, 185, 8, 12, 1},
11590 	{116, 186, 0, 12, 1},
11591 	{118, 186, 4, 12, 1},
11592 	{120, 186, 8, 12, 1},
11593 	{122, 187, 0, 12, 1},
11594 	{124, 187, 4, 12, 1},
11595 	{126, 187, 8, 12, 1},
11596 	{128, 188, 0, 12, 1},
11597 	{130, 188, 4, 12, 1},
11598 	{132, 188, 8, 12, 1},
11599 	{134, 189, 0, 12, 1},
11600 	{136, 189, 4, 12, 1},
11601 	{138, 189, 8, 12, 1},
11602 	{140, 190, 0, 12, 1},
11603 	{149, 191, 6, 12, 1},
11604 	{151, 191, 10, 12, 1},
11605 	{153, 192, 2, 12, 1},
11606 	{155, 192, 6, 12, 1},
11607 	{157, 192, 10, 12, 1},
11608 	{159, 193, 2, 12, 1},
11609 	{161, 193, 6, 12, 1},
11610 	{165, 194, 2, 12, 1},
11611 	{184, 164, 0, 12, 1},
11612 	{188, 164, 4, 12, 1},
11613 	{192, 165, 8, 12, 1},
11614 	{196, 166, 0, 12, 1},
11615 };
11616 
11617 static const struct rf_channel rf_vals_5592_xtal40[] = {
11618 	/* Channel, N, K, mod, R */
11619 	{1, 241, 2, 10, 3},
11620 	{2, 241, 7, 10, 3},
11621 	{3, 242, 2, 10, 3},
11622 	{4, 242, 7, 10, 3},
11623 	{5, 243, 2, 10, 3},
11624 	{6, 243, 7, 10, 3},
11625 	{7, 244, 2, 10, 3},
11626 	{8, 244, 7, 10, 3},
11627 	{9, 245, 2, 10, 3},
11628 	{10, 245, 7, 10, 3},
11629 	{11, 246, 2, 10, 3},
11630 	{12, 246, 7, 10, 3},
11631 	{13, 247, 2, 10, 3},
11632 	{14, 248, 4, 10, 3},
11633 	{36, 86, 4, 12, 1},
11634 	{38, 86, 6, 12, 1},
11635 	{40, 86, 8, 12, 1},
11636 	{42, 86, 10, 12, 1},
11637 	{44, 87, 0, 12, 1},
11638 	{46, 87, 2, 12, 1},
11639 	{48, 87, 4, 12, 1},
11640 	{50, 87, 6, 12, 1},
11641 	{52, 87, 8, 12, 1},
11642 	{54, 87, 10, 12, 1},
11643 	{56, 88, 0, 12, 1},
11644 	{58, 88, 2, 12, 1},
11645 	{60, 88, 4, 12, 1},
11646 	{62, 88, 6, 12, 1},
11647 	{64, 88, 8, 12, 1},
11648 	{100, 91, 8, 12, 1},
11649 	{102, 91, 10, 12, 1},
11650 	{104, 92, 0, 12, 1},
11651 	{106, 92, 2, 12, 1},
11652 	{108, 92, 4, 12, 1},
11653 	{110, 92, 6, 12, 1},
11654 	{112, 92, 8, 12, 1},
11655 	{114, 92, 10, 12, 1},
11656 	{116, 93, 0, 12, 1},
11657 	{118, 93, 2, 12, 1},
11658 	{120, 93, 4, 12, 1},
11659 	{122, 93, 6, 12, 1},
11660 	{124, 93, 8, 12, 1},
11661 	{126, 93, 10, 12, 1},
11662 	{128, 94, 0, 12, 1},
11663 	{130, 94, 2, 12, 1},
11664 	{132, 94, 4, 12, 1},
11665 	{134, 94, 6, 12, 1},
11666 	{136, 94, 8, 12, 1},
11667 	{138, 94, 10, 12, 1},
11668 	{140, 95, 0, 12, 1},
11669 	{149, 95, 9, 12, 1},
11670 	{151, 95, 11, 12, 1},
11671 	{153, 96, 1, 12, 1},
11672 	{155, 96, 3, 12, 1},
11673 	{157, 96, 5, 12, 1},
11674 	{159, 96, 7, 12, 1},
11675 	{161, 96, 9, 12, 1},
11676 	{165, 97, 1, 12, 1},
11677 	{184, 82, 0, 12, 1},
11678 	{188, 82, 4, 12, 1},
11679 	{192, 82, 8, 12, 1},
11680 	{196, 83, 0, 12, 1},
11681 };
11682 
11683 static const struct rf_channel rf_vals_7620[] = {
11684 	{1, 0x50, 0x99, 0x99, 1},
11685 	{2, 0x50, 0x44, 0x44, 2},
11686 	{3, 0x50, 0xEE, 0xEE, 2},
11687 	{4, 0x50, 0x99, 0x99, 3},
11688 	{5, 0x51, 0x44, 0x44, 0},
11689 	{6, 0x51, 0xEE, 0xEE, 0},
11690 	{7, 0x51, 0x99, 0x99, 1},
11691 	{8, 0x51, 0x44, 0x44, 2},
11692 	{9, 0x51, 0xEE, 0xEE, 2},
11693 	{10, 0x51, 0x99, 0x99, 3},
11694 	{11, 0x52, 0x44, 0x44, 0},
11695 	{12, 0x52, 0xEE, 0xEE, 0},
11696 	{13, 0x52, 0x99, 0x99, 1},
11697 	{14, 0x52, 0x33, 0x33, 3},
11698 };
11699 
rt2800_probe_hw_mode(struct rt2x00_dev * rt2x00dev)11700 static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
11701 {
11702 	struct hw_mode_spec *spec = &rt2x00dev->spec;
11703 	struct channel_info *info;
11704 	s8 *default_power1;
11705 	s8 *default_power2;
11706 	s8 *default_power3;
11707 	unsigned int i, tx_chains, rx_chains;
11708 	u32 reg;
11709 
11710 	/*
11711 	 * Disable powersaving as default.
11712 	 */
11713 	rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
11714 
11715 	/*
11716 	 * Change default retry settings to values corresponding more closely
11717 	 * to rate[0].count setting of minstrel rate control algorithm.
11718 	 */
11719 	rt2x00dev->hw->wiphy->retry_short = 2;
11720 	rt2x00dev->hw->wiphy->retry_long = 2;
11721 
11722 	/*
11723 	 * Initialize all hw fields.
11724 	 */
11725 	ieee80211_hw_set(rt2x00dev->hw, REPORTS_TX_ACK_STATUS);
11726 	ieee80211_hw_set(rt2x00dev->hw, AMPDU_AGGREGATION);
11727 	ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK);
11728 	ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM);
11729 	ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS);
11730 
11731 	/*
11732 	 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
11733 	 * unless we are capable of sending the buffered frames out after the
11734 	 * DTIM transmission using rt2x00lib_beacondone. This will send out
11735 	 * multicast and broadcast traffic immediately instead of buffering it
11736 	 * infinitly and thus dropping it after some time.
11737 	 */
11738 	if (!rt2x00_is_usb(rt2x00dev))
11739 		ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING);
11740 
11741 	ieee80211_hw_set(rt2x00dev->hw, MFP_CAPABLE);
11742 
11743 	SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
11744 	SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
11745 				rt2800_eeprom_addr(rt2x00dev,
11746 						   EEPROM_MAC_ADDR_0));
11747 
11748 	/*
11749 	 * As rt2800 has a global fallback table we cannot specify
11750 	 * more then one tx rate per frame but since the hw will
11751 	 * try several rates (based on the fallback table) we should
11752 	 * initialize max_report_rates to the maximum number of rates
11753 	 * we are going to try. Otherwise mac80211 will truncate our
11754 	 * reported tx rates and the rc algortihm will end up with
11755 	 * incorrect data.
11756 	 */
11757 	rt2x00dev->hw->max_rates = 1;
11758 	rt2x00dev->hw->max_report_rates = 7;
11759 	rt2x00dev->hw->max_rate_tries = 1;
11760 
11761 	/*
11762 	 * Initialize hw_mode information.
11763 	 */
11764 	spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
11765 
11766 	switch (rt2x00dev->chip.rf) {
11767 	case RF2720:
11768 	case RF2820:
11769 		spec->num_channels = 14;
11770 		spec->channels = rf_vals;
11771 		break;
11772 
11773 	case RF2750:
11774 	case RF2850:
11775 		spec->num_channels = ARRAY_SIZE(rf_vals);
11776 		spec->channels = rf_vals;
11777 		break;
11778 
11779 	case RF2020:
11780 	case RF3020:
11781 	case RF3021:
11782 	case RF3022:
11783 	case RF3070:
11784 	case RF3290:
11785 	case RF3320:
11786 	case RF3322:
11787 	case RF5350:
11788 	case RF5360:
11789 	case RF5362:
11790 	case RF5370:
11791 	case RF5372:
11792 	case RF5390:
11793 	case RF5392:
11794 		spec->num_channels = 14;
11795 		if (rt2800_clk_is_20mhz(rt2x00dev))
11796 			spec->channels = rf_vals_3x_xtal20;
11797 		else
11798 			spec->channels = rf_vals_3x;
11799 		break;
11800 
11801 	case RF7620:
11802 		spec->num_channels = ARRAY_SIZE(rf_vals_7620);
11803 		spec->channels = rf_vals_7620;
11804 		break;
11805 
11806 	case RF3052:
11807 	case RF3053:
11808 		spec->num_channels = ARRAY_SIZE(rf_vals_3x);
11809 		spec->channels = rf_vals_3x;
11810 		break;
11811 
11812 	case RF3853:
11813 		spec->num_channels = ARRAY_SIZE(rf_vals_3853);
11814 		spec->channels = rf_vals_3853;
11815 		break;
11816 
11817 	case RF5592:
11818 		reg = rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX);
11819 		if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) {
11820 			spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40);
11821 			spec->channels = rf_vals_5592_xtal40;
11822 		} else {
11823 			spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20);
11824 			spec->channels = rf_vals_5592_xtal20;
11825 		}
11826 		break;
11827 	}
11828 
11829 	if (WARN_ON_ONCE(!spec->channels))
11830 		return -ENODEV;
11831 
11832 	spec->supported_bands = SUPPORT_BAND_2GHZ;
11833 	if (spec->num_channels > 14)
11834 		spec->supported_bands |= SUPPORT_BAND_5GHZ;
11835 
11836 	/*
11837 	 * Initialize HT information.
11838 	 */
11839 	if (!rt2x00_rf(rt2x00dev, RF2020))
11840 		spec->ht.ht_supported = true;
11841 	else
11842 		spec->ht.ht_supported = false;
11843 
11844 	spec->ht.cap =
11845 	    IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
11846 	    IEEE80211_HT_CAP_GRN_FLD |
11847 	    IEEE80211_HT_CAP_SGI_20 |
11848 	    IEEE80211_HT_CAP_SGI_40;
11849 
11850 	tx_chains = rt2x00dev->default_ant.tx_chain_num;
11851 	rx_chains = rt2x00dev->default_ant.rx_chain_num;
11852 
11853 	if (tx_chains >= 2)
11854 		spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
11855 
11856 	spec->ht.cap |= rx_chains << IEEE80211_HT_CAP_RX_STBC_SHIFT;
11857 
11858 	spec->ht.ampdu_factor = (rx_chains > 1) ? 3 : 2;
11859 	spec->ht.ampdu_density = 4;
11860 	spec->ht.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
11861 	if (tx_chains != rx_chains) {
11862 		spec->ht.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
11863 		spec->ht.mcs.tx_params |=
11864 		    (tx_chains - 1) << IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
11865 	}
11866 
11867 	switch (rx_chains) {
11868 	case 3:
11869 		spec->ht.mcs.rx_mask[2] = 0xff;
11870 		fallthrough;
11871 	case 2:
11872 		spec->ht.mcs.rx_mask[1] = 0xff;
11873 		fallthrough;
11874 	case 1:
11875 		spec->ht.mcs.rx_mask[0] = 0xff;
11876 		spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
11877 		break;
11878 	}
11879 
11880 	/*
11881 	 * Create channel information and survey arrays
11882 	 */
11883 	info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
11884 	if (!info)
11885 		return -ENOMEM;
11886 
11887 	rt2x00dev->chan_survey =
11888 		kcalloc(spec->num_channels, sizeof(struct rt2x00_chan_survey),
11889 			GFP_KERNEL);
11890 	if (!rt2x00dev->chan_survey) {
11891 		kfree(info);
11892 		return -ENOMEM;
11893 	}
11894 
11895 	spec->channels_info = info;
11896 
11897 	default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
11898 	default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
11899 
11900 	if (rt2x00dev->default_ant.tx_chain_num > 2)
11901 		default_power3 = rt2800_eeprom_addr(rt2x00dev,
11902 						    EEPROM_EXT_TXPOWER_BG3);
11903 	else
11904 		default_power3 = NULL;
11905 
11906 	for (i = 0; i < 14; i++) {
11907 		info[i].default_power1 = default_power1[i];
11908 		info[i].default_power2 = default_power2[i];
11909 		if (default_power3)
11910 			info[i].default_power3 = default_power3[i];
11911 	}
11912 
11913 	if (spec->num_channels > 14) {
11914 		default_power1 = rt2800_eeprom_addr(rt2x00dev,
11915 						    EEPROM_TXPOWER_A1);
11916 		default_power2 = rt2800_eeprom_addr(rt2x00dev,
11917 						    EEPROM_TXPOWER_A2);
11918 
11919 		if (rt2x00dev->default_ant.tx_chain_num > 2)
11920 			default_power3 =
11921 				rt2800_eeprom_addr(rt2x00dev,
11922 						   EEPROM_EXT_TXPOWER_A3);
11923 		else
11924 			default_power3 = NULL;
11925 
11926 		for (i = 14; i < spec->num_channels; i++) {
11927 			info[i].default_power1 = default_power1[i - 14];
11928 			info[i].default_power2 = default_power2[i - 14];
11929 			if (default_power3)
11930 				info[i].default_power3 = default_power3[i - 14];
11931 		}
11932 	}
11933 
11934 	switch (rt2x00dev->chip.rf) {
11935 	case RF2020:
11936 	case RF3020:
11937 	case RF3021:
11938 	case RF3022:
11939 	case RF3320:
11940 	case RF3052:
11941 	case RF3053:
11942 	case RF3070:
11943 	case RF3290:
11944 	case RF3853:
11945 	case RF5350:
11946 	case RF5360:
11947 	case RF5362:
11948 	case RF5370:
11949 	case RF5372:
11950 	case RF5390:
11951 	case RF5392:
11952 	case RF5592:
11953 	case RF7620:
11954 		__set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
11955 		break;
11956 	}
11957 
11958 	return 0;
11959 }
11960 
rt2800_probe_rt(struct rt2x00_dev * rt2x00dev)11961 static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev)
11962 {
11963 	u32 reg;
11964 	u32 rt;
11965 	u32 rev;
11966 
11967 	if (rt2x00_rt(rt2x00dev, RT3290))
11968 		reg = rt2800_register_read(rt2x00dev, MAC_CSR0_3290);
11969 	else
11970 		reg = rt2800_register_read(rt2x00dev, MAC_CSR0);
11971 
11972 	rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET);
11973 	rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION);
11974 
11975 	switch (rt) {
11976 	case RT2860:
11977 	case RT2872:
11978 	case RT2883:
11979 	case RT3070:
11980 	case RT3071:
11981 	case RT3090:
11982 	case RT3290:
11983 	case RT3352:
11984 	case RT3390:
11985 	case RT3572:
11986 	case RT3593:
11987 	case RT3883:
11988 	case RT5350:
11989 	case RT5390:
11990 	case RT5392:
11991 	case RT5592:
11992 		break;
11993 	default:
11994 		rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n",
11995 			   rt, rev);
11996 		return -ENODEV;
11997 	}
11998 
11999 	if (rt == RT5390 && rt2x00_is_soc(rt2x00dev))
12000 		rt = RT6352;
12001 
12002 	rt2x00_set_rt(rt2x00dev, rt, rev);
12003 
12004 	return 0;
12005 }
12006 
rt2800_probe_hw(struct rt2x00_dev * rt2x00dev)12007 int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
12008 {
12009 	int retval;
12010 	u32 reg;
12011 
12012 	retval = rt2800_probe_rt(rt2x00dev);
12013 	if (retval)
12014 		return retval;
12015 
12016 	/*
12017 	 * Allocate eeprom data.
12018 	 */
12019 	retval = rt2800_validate_eeprom(rt2x00dev);
12020 	if (retval)
12021 		return retval;
12022 
12023 	retval = rt2800_init_eeprom(rt2x00dev);
12024 	if (retval)
12025 		return retval;
12026 
12027 	/*
12028 	 * Enable rfkill polling by setting GPIO direction of the
12029 	 * rfkill switch GPIO pin correctly.
12030 	 */
12031 	reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
12032 	rt2x00_set_field32(&reg, GPIO_CTRL_DIR2, 1);
12033 	rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
12034 
12035 	/*
12036 	 * Initialize hw specifications.
12037 	 */
12038 	retval = rt2800_probe_hw_mode(rt2x00dev);
12039 	if (retval)
12040 		return retval;
12041 
12042 	/*
12043 	 * Set device capabilities.
12044 	 */
12045 	__set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
12046 	__set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
12047 	if (!rt2x00_is_usb(rt2x00dev))
12048 		__set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
12049 
12050 	/*
12051 	 * Set device requirements.
12052 	 */
12053 	if (!rt2x00_is_soc(rt2x00dev))
12054 		__set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
12055 	__set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
12056 	__set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
12057 	if (!rt2800_hwcrypt_disabled(rt2x00dev))
12058 		__set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
12059 	__set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
12060 	__set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
12061 	if (rt2x00_is_usb(rt2x00dev))
12062 		__set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
12063 	else {
12064 		__set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
12065 		__set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
12066 	}
12067 
12068 	rt2x00dev->link.watchdog = modparam_watchdog;
12069 	/* USB NICs don't support DMA watchdog as INT_SOURCE_CSR is invalid */
12070 	if (rt2x00_is_usb(rt2x00dev))
12071 		rt2x00dev->link.watchdog &= ~RT2800_WATCHDOG_DMA_BUSY;
12072 	if (rt2x00dev->link.watchdog) {
12073 		__set_bit(CAPABILITY_RESTART_HW, &rt2x00dev->cap_flags);
12074 		rt2x00dev->link.watchdog_interval = msecs_to_jiffies(100);
12075 	}
12076 
12077 	/*
12078 	 * Set the rssi offset.
12079 	 */
12080 	rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
12081 
12082 	return 0;
12083 }
12084 EXPORT_SYMBOL_GPL(rt2800_probe_hw);
12085 
12086 /*
12087  * IEEE80211 stack callback functions.
12088  */
rt2800_get_key_seq(struct ieee80211_hw * hw,struct ieee80211_key_conf * key,struct ieee80211_key_seq * seq)12089 void rt2800_get_key_seq(struct ieee80211_hw *hw,
12090 			struct ieee80211_key_conf *key,
12091 			struct ieee80211_key_seq *seq)
12092 {
12093 	struct rt2x00_dev *rt2x00dev = hw->priv;
12094 	struct mac_iveiv_entry iveiv_entry;
12095 	u32 offset;
12096 
12097 	if (key->cipher != WLAN_CIPHER_SUITE_TKIP)
12098 		return;
12099 
12100 	offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
12101 	rt2800_register_multiread(rt2x00dev, offset,
12102 				      &iveiv_entry, sizeof(iveiv_entry));
12103 
12104 	memcpy(&seq->tkip.iv16, &iveiv_entry.iv[0], 2);
12105 	memcpy(&seq->tkip.iv32, &iveiv_entry.iv[4], 4);
12106 }
12107 EXPORT_SYMBOL_GPL(rt2800_get_key_seq);
12108 
rt2800_set_rts_threshold(struct ieee80211_hw * hw,u32 value)12109 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
12110 {
12111 	struct rt2x00_dev *rt2x00dev = hw->priv;
12112 	u32 reg;
12113 	bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
12114 
12115 	reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG);
12116 	rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
12117 	rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
12118 
12119 	reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG);
12120 	rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
12121 	rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
12122 
12123 	reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG);
12124 	rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
12125 	rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
12126 
12127 	reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG);
12128 	rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
12129 	rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
12130 
12131 	reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG);
12132 	rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
12133 	rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
12134 
12135 	reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG);
12136 	rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
12137 	rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
12138 
12139 	reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG);
12140 	rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
12141 	rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
12142 
12143 	return 0;
12144 }
12145 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
12146 
rt2800_conf_tx(struct ieee80211_hw * hw,struct ieee80211_vif * vif,unsigned int link_id,u16 queue_idx,const struct ieee80211_tx_queue_params * params)12147 int rt2800_conf_tx(struct ieee80211_hw *hw,
12148 		   struct ieee80211_vif *vif,
12149 		   unsigned int link_id, u16 queue_idx,
12150 		   const struct ieee80211_tx_queue_params *params)
12151 {
12152 	struct rt2x00_dev *rt2x00dev = hw->priv;
12153 	struct data_queue *queue;
12154 	struct rt2x00_field32 field;
12155 	int retval;
12156 	u32 reg;
12157 	u32 offset;
12158 
12159 	/*
12160 	 * First pass the configuration through rt2x00lib, that will
12161 	 * update the queue settings and validate the input. After that
12162 	 * we are free to update the registers based on the value
12163 	 * in the queue parameter.
12164 	 */
12165 	retval = rt2x00mac_conf_tx(hw, vif, link_id, queue_idx, params);
12166 	if (retval)
12167 		return retval;
12168 
12169 	/*
12170 	 * We only need to perform additional register initialization
12171 	 * for WMM queues/
12172 	 */
12173 	if (queue_idx >= 4)
12174 		return 0;
12175 
12176 	queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
12177 
12178 	/* Update WMM TXOP register */
12179 	offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
12180 	field.bit_offset = (queue_idx & 1) * 16;
12181 	field.bit_mask = 0xffff << field.bit_offset;
12182 
12183 	reg = rt2800_register_read(rt2x00dev, offset);
12184 	rt2x00_set_field32(&reg, field, queue->txop);
12185 	rt2800_register_write(rt2x00dev, offset, reg);
12186 
12187 	/* Update WMM registers */
12188 	field.bit_offset = queue_idx * 4;
12189 	field.bit_mask = 0xf << field.bit_offset;
12190 
12191 	reg = rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG);
12192 	rt2x00_set_field32(&reg, field, queue->aifs);
12193 	rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
12194 
12195 	reg = rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG);
12196 	rt2x00_set_field32(&reg, field, queue->cw_min);
12197 	rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
12198 
12199 	reg = rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG);
12200 	rt2x00_set_field32(&reg, field, queue->cw_max);
12201 	rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
12202 
12203 	/* Update EDCA registers */
12204 	offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
12205 
12206 	reg = rt2800_register_read(rt2x00dev, offset);
12207 	rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
12208 	rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
12209 	rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
12210 	rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
12211 	rt2800_register_write(rt2x00dev, offset, reg);
12212 
12213 	return 0;
12214 }
12215 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
12216 
rt2800_get_tsf(struct ieee80211_hw * hw,struct ieee80211_vif * vif)12217 u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
12218 {
12219 	struct rt2x00_dev *rt2x00dev = hw->priv;
12220 	u64 tsf;
12221 	u32 reg;
12222 
12223 	reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW1);
12224 	tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
12225 	reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW0);
12226 	tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
12227 
12228 	return tsf;
12229 }
12230 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
12231 
rt2800_ampdu_action(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_ampdu_params * params)12232 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
12233 			struct ieee80211_ampdu_params *params)
12234 {
12235 	struct ieee80211_sta *sta = params->sta;
12236 	enum ieee80211_ampdu_mlme_action action = params->action;
12237 	u16 tid = params->tid;
12238 	struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
12239 	int ret = 0;
12240 
12241 	/*
12242 	 * Don't allow aggregation for stations the hardware isn't aware
12243 	 * of because tx status reports for frames to an unknown station
12244 	 * always contain wcid=WCID_END+1 and thus we can't distinguish
12245 	 * between multiple stations which leads to unwanted situations
12246 	 * when the hw reorders frames due to aggregation.
12247 	 */
12248 	if (sta_priv->wcid > WCID_END)
12249 		return -ENOSPC;
12250 
12251 	switch (action) {
12252 	case IEEE80211_AMPDU_RX_START:
12253 	case IEEE80211_AMPDU_RX_STOP:
12254 		/*
12255 		 * The hw itself takes care of setting up BlockAck mechanisms.
12256 		 * So, we only have to allow mac80211 to nagotiate a BlockAck
12257 		 * agreement. Once that is done, the hw will BlockAck incoming
12258 		 * AMPDUs without further setup.
12259 		 */
12260 		break;
12261 	case IEEE80211_AMPDU_TX_START:
12262 		ret = IEEE80211_AMPDU_TX_START_IMMEDIATE;
12263 		break;
12264 	case IEEE80211_AMPDU_TX_STOP_CONT:
12265 	case IEEE80211_AMPDU_TX_STOP_FLUSH:
12266 	case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
12267 		ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
12268 		break;
12269 	case IEEE80211_AMPDU_TX_OPERATIONAL:
12270 		break;
12271 	default:
12272 		rt2x00_warn((struct rt2x00_dev *)hw->priv,
12273 			    "Unknown AMPDU action\n");
12274 	}
12275 
12276 	return ret;
12277 }
12278 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
12279 
rt2800_get_survey(struct ieee80211_hw * hw,int idx,struct survey_info * survey)12280 int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
12281 		      struct survey_info *survey)
12282 {
12283 	struct rt2x00_dev *rt2x00dev = hw->priv;
12284 	struct rt2x00_chan_survey *chan_survey =
12285 		   &rt2x00dev->chan_survey[idx];
12286 	enum nl80211_band band = NL80211_BAND_2GHZ;
12287 
12288 	if (idx >= rt2x00dev->bands[band].n_channels) {
12289 		idx -= rt2x00dev->bands[band].n_channels;
12290 		band = NL80211_BAND_5GHZ;
12291 	}
12292 
12293 	if (idx >= rt2x00dev->bands[band].n_channels)
12294 		return -ENOENT;
12295 
12296 	if (idx == 0)
12297 		rt2800_update_survey(rt2x00dev);
12298 
12299 	survey->channel = &rt2x00dev->bands[band].channels[idx];
12300 
12301 	survey->filled = SURVEY_INFO_TIME |
12302 			 SURVEY_INFO_TIME_BUSY |
12303 			 SURVEY_INFO_TIME_EXT_BUSY;
12304 
12305 	survey->time = div_u64(chan_survey->time_idle + chan_survey->time_busy, 1000);
12306 	survey->time_busy = div_u64(chan_survey->time_busy, 1000);
12307 	survey->time_ext_busy = div_u64(chan_survey->time_ext_busy, 1000);
12308 
12309 	if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
12310 		survey->filled |= SURVEY_INFO_IN_USE;
12311 
12312 	return 0;
12313 
12314 }
12315 EXPORT_SYMBOL_GPL(rt2800_get_survey);
12316 
12317 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
12318 MODULE_VERSION(DRV_VERSION);
12319 MODULE_DESCRIPTION("Ralink RT2800 library");
12320 MODULE_LICENSE("GPL");
12321